diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_batch_normalization.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_batch_normalization.hpp new file mode 100644 index 0000000000000000000000000000000000000000..355a94152583a55fe19ee3544f27684a43e9c06a --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_batch_normalization.hpp @@ -0,0 +1,282 @@ +/******************************************************************************* +* Copyright 2022 Arm Ltd. and affiliates +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_ACL_BATCH_NORMALIZATION_HPP +#define CPU_AARCH64_ACL_BATCH_NORMALIZATION_HPP + +#include "cpu/cpu_batch_normalization_pd.hpp" + +#include "cpu/aarch64/acl_post_ops.hpp" +#include "cpu/aarch64/acl_utils.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +struct acl_batch_normalization_obj_t { + arm_compute::NEBatchNormalizationLayer bnorm; + arm_compute::Tensor src_tensor; + arm_compute::Tensor dst_tensor; + arm_compute::Tensor mean_tensor; + arm_compute::Tensor var_tensor; + arm_compute::Tensor beta_tensor; // shift + arm_compute::Tensor gamma_tensor; // scale +}; + +struct acl_batch_normalization_conf_t { + // src and dst + arm_compute::TensorInfo data_info; + // TensorInfo for statistics (mean and/or variance), shift and scale + arm_compute::TensorInfo stats_info; + arm_compute::ActivationLayerInfo act_info; +}; + +struct acl_batch_normalization_resource_t : public resource_t { + acl_batch_normalization_resource_t() + : acl_obj_(utils::make_unique()) {} + + status_t configure(const acl_batch_normalization_conf_t &abp, + const batch_normalization_pd_t *pd) { + if (!acl_obj_) return status::out_of_memory; + + // Init Compute Library tensors based on info from descriptor + acl_obj_->src_tensor.allocator()->init(abp.data_info); + acl_obj_->dst_tensor.allocator()->init(abp.data_info); + + acl_obj_->mean_tensor.allocator()->init(abp.stats_info); + acl_obj_->var_tensor.allocator()->init(abp.stats_info); + if (pd->use_shift()) + acl_obj_->beta_tensor.allocator()->init(abp.stats_info); + if (pd->use_scale()) + acl_obj_->gamma_tensor.allocator()->init(abp.stats_info); + + // clang-format off + acl_obj_->bnorm.configure( + &acl_obj_->src_tensor, + &acl_obj_->dst_tensor, + &acl_obj_->mean_tensor, + &acl_obj_->var_tensor, + pd->use_shift() ? &acl_obj_->beta_tensor : nullptr, + pd->use_scale() ? &acl_obj_->gamma_tensor : nullptr, + pd->desc()->batch_norm_epsilon, + abp.act_info); + // clang-format on + + return status::success; + } + + acl_batch_normalization_obj_t &get_acl_obj() const { return *acl_obj_; } + + DNNL_DISALLOW_COPY_AND_ASSIGN(acl_batch_normalization_resource_t); + +private: + std::unique_ptr acl_obj_; +}; // acl_batch_normalization_resource_t + +struct acl_batch_normalization_fwd_t : public primitive_t { + struct pd_t : public cpu_batch_normalization_fwd_pd_t { + using cpu_batch_normalization_fwd_pd_t:: + cpu_batch_normalization_fwd_pd_t; + + pd_t(const batch_normalization_desc_t *adesc, + const primitive_attr_t *attr, + const typename pd_t::base_class *hint_fwd_pd) + : cpu_batch_normalization_fwd_pd_t(adesc, attr, hint_fwd_pd) + , abp() {} + + DECLARE_COMMON_PD_T("acl", acl_batch_normalization_fwd_t); + + status_t init(engine_t *engine) { + using namespace format_tag; + + // Get memory desc to find sizes and dims + const memory_desc_wrapper src_d(src_md_); + const memory_desc_wrapper stat_d(stat_md_); + + using smask_t = primitive_attr_t::skip_mask_t; + ACL_CHECK_SUPPORT(!attr()->has_default_values(smask_t::post_ops), + "attr must have default values"); + + ACL_CHECK_SUPPORT(!set_default_formats_common(), + "Failed to set default formats"); + ACL_CHECK_SUPPORT(src_d != memory_desc_wrapper(dst_md()), + "Source and destination must have the same layout"); + + // Stats must already have been calculated + ACL_CHECK_SUPPORT(!use_global_stats(), + "stats must already have been computed (use global stats)"); + + ACL_CHECK_SUPPORT(!is_fwd(), "must be forward mode"); + + ACL_CHECK_SUPPORT(!utils::one_of(src_d.data_type(), data_type::f32, + data_type::f16), + "data type must be f32/f16"); + + // Dimensions can be permuted but no blocking or padding + ACL_CHECK_SUPPORT((!src_d.is_plain() || !stat_d.is_plain()), + "tensors must be plain"); + ACL_CHECK_SUPPORT((!src_d.is_dense() || !stat_d.is_dense()), + "tensors must be dense"); + + ACL_CHECK_SUPPORT(src_d.is_zero() || src_d.has_zero_dim(), + "zero sized src tensor"); + ACL_CHECK_SUPPORT(stat_d.is_zero() || stat_d.has_zero_dim(), + "zero sized stats tensor"); + + // mean, var, scale and shift all have a single dimension with size + // equal to the number of channels + auto acl_stats_dt = acl_utils::get_acl_data_t(stat_d.data_type()); + abp.stats_info + = arm_compute::TensorInfo(arm_compute::TensorShape(C()), 1, + acl_stats_dt, arm_compute::DataLayout::NHWC); + + // We can simplify into two cases: channels are dense or not dense + auto channel_stride = src_d.blocking_desc().strides[1]; + if (channel_stride == 1) { + // Channels are dense => NHWC + // Collapse all dims except channels into W + auto elems = src_d.nelems(); + dim_t w = elems / C(); + + // For small problems, it is better to disable threads with ACL + bool use_acl_threads = elems > 20000; + + // The number of threads each candidate implementation + // (acl,nspc) is able to use for these problem parameters + int max_threads = dnnl_get_max_threads(); + int acl_threads + = use_acl_threads ? std::min((int)w, max_threads) : 1; + int nspc_threads = std::min((int)MB(), max_threads); + + // A simple empirical heuristic which is negative when ACL is + // faster, positive when slower. The first term represents a + // constant overhead when calling ACL as an external library, + // the second term represents the cost per tensor elem for the + // two candidate implementations (scaling for the number of + // threads used) + double acl_ref_time_diff = 33 + + elems * (0.11 / acl_threads - 0.48 / nspc_threads); + + // Threads in ACL incur an additional cost + if (use_acl_threads) { + acl_ref_time_diff += 1500.0 + 130.0 * (acl_threads - 1); + } + + // If ACL is slower, don't use it, fall back to nspc_bnorm + if (acl_ref_time_diff > 0) return status::unimplemented; + + // We disable threading in ACL by moving the width into height + auto data_shape = use_acl_threads + ? arm_compute::TensorShape(C(), w, 1, 1) + : arm_compute::TensorShape(C(), 1, w, 1); + auto acl_data_dt = acl_utils::get_acl_data_t(src_d.data_type()); + abp.data_info = arm_compute::TensorInfo(data_shape, 1, + acl_data_dt, arm_compute::DataLayout::NHWC); + } else { + // Implemented in ACL but not yet optimal + return status::unimplemented; + } + + ACL_CHECK_SUPPORT(fuse_norm_relu() + && desc()->prop_kind == prop_kind::forward_training, + "forward training with fused ReLU is not supported"); + + // oneDNN only supports eltwise post ops with bnorm + for (int i = 0; i < attr()->post_ops_.len(); ++i) + if (!attr()->post_ops_.entry_[i].is_eltwise()) + return status::unimplemented; + + if (fuse_norm_relu()) { + abp.act_info = arm_compute::ActivationLayerInfo(arm_compute:: + ActivationLayerInfo::ActivationFunction::RELU); + // ACL BNorm supports fusing ReLU. If this validate fails, it + // will be for a different, unrecoverable reason + CHECK(validate(abp.act_info)); + // init any additional post ops + CHECK(post_ops.init(engine, attr_.post_ops_, src_md_)); + } else { + // init post ops, removing first eltwise for fusion + arm_compute::ActivationLayerInfo act_info; + CHECK(post_ops.init( + engine, attr_.post_ops_, src_md_, act_info)); + // ACL BNorm doesn't support all the same eltwise ops as the + // standalone ACL operator, so fall back to unfused eltwise if + // validate fails + if (validate(act_info) == status::success) { + // validate succeeded => we can fuse the eltwise + abp.act_info = act_info; + } else { + // validate unfused eltwise + remaining post ops + CHECK(validate()); + CHECK(post_ops.init(engine, attr_.post_ops_, src_md_)); + } + } + + return status::success; + } + + status_t validate() { return validate(abp.act_info); } + + status_t validate(arm_compute::ActivationLayerInfo &act_info) { + ACL_CHECK_VALID(arm_compute::NEBatchNormalizationLayer::validate( + &abp.data_info, &abp.data_info, &abp.stats_info, + &abp.stats_info, use_shift() ? &abp.stats_info : nullptr, + use_scale() ? &abp.stats_info : nullptr, + desc()->batch_norm_epsilon, act_info)); + return status::success; + } + + acl_batch_normalization_conf_t abp; + + acl_post_ops_t post_ops; + }; // pd_t + + acl_batch_normalization_fwd_t(const pd_t *apd) : primitive_t(apd) {} + + status_t create_resource( + engine_t *engine, resource_mapper_t &mapper) const override { + if (mapper.has_resource(this)) return status::success; + + auto r = utils::make_unique(); + if (!r) return status::out_of_memory; + + // Configure the resource based on information from primitive descriptor + CHECK(r->configure(pd()->abp, pd())); + mapper.add(this, std::move(r)); + + CHECK(pd()->post_ops.create_resource(engine, mapper)); + + return status::success; + } + + status_t execute(const exec_ctx_t &ctx) const override { + return execute_forward(ctx); + } + +private: + // To guard the const execute_forward, the mutex must be 'mutable' + mutable std::mutex mtx; + status_t execute_forward(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } +}; // acl_batch_normalization_fwd_t + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_benchmark_scheduler.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_benchmark_scheduler.hpp new file mode 100644 index 0000000000000000000000000000000000000000..8fddf7ea298faf64f0ad80ebafe77043e5bd5e03 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_benchmark_scheduler.hpp @@ -0,0 +1,60 @@ +/******************************************************************************* +* Copyright 2023 Arm Ltd. and affiliates +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ +#ifndef CPU_AARCH64_ACL_BENCHMARK_SCHEDULER_HPP +#define CPU_AARCH64_ACL_BENCHMARK_SCHEDULER_HPP + +#include "arm_compute/core/CPP/ICPPKernel.h" +#include "arm_compute/runtime/IScheduler.h" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { +// BenchmarkScheduler implement's ACL IScheduler interface and acts as an interceptor scheduler +// when DNNL_VERBOSE=profile,profile_externals. It intercepts calls made by the actual scheduler used by ACL and adds +// timers to benchmark execution time of ACL kernels and store kernel information. +class BenchmarkScheduler final : public arm_compute::IScheduler { +public: + BenchmarkScheduler(IScheduler &real_scheduler); + + ~BenchmarkScheduler(); + + void set_num_threads(unsigned int num_threads) override; + unsigned int num_threads() const override; + void set_num_threads_with_affinity( + unsigned int num_threads, BindFunc func) override; + void schedule(arm_compute::ICPPKernel *kernel, + const arm_compute::IScheduler::Hints &hints) override; + void schedule_op(arm_compute::ICPPKernel *kernel, + const arm_compute::IScheduler::Hints &hints, + const arm_compute::Window &window, + arm_compute::ITensorPack &tensors) override; + +protected: + void run_workloads(std::vector &workloads) override; + void run_tagged_workloads( + std::vector &workloads, const char *tag) override; + +private: + IScheduler &_real_scheduler; +}; + +#endif // CPU_AARCH64_ACL_BENCHMARK_SCHEDULER_HPP + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_binary.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_binary.hpp new file mode 100644 index 0000000000000000000000000000000000000000..a0c8a14823c9a83105d7f2612c55e26de2e97b89 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_binary.hpp @@ -0,0 +1,278 @@ +/******************************************************************************* +* Copyright 2022 Arm Ltd. and affiliates +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed tos in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_ACL_BINARY_HPP +#define CPU_AARCH64_ACL_BINARY_HPP + +#include "cpu/cpu_binary_pd.hpp" + +#include "cpu/aarch64/acl_utils.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +struct acl_binary_obj_t { + std::unique_ptr binary_op; + arm_compute::Tensor src0_tensor; + arm_compute::Tensor src1_tensor; + arm_compute::Tensor dst_tensor; +}; + +struct acl_binary_conf_t { + arm_compute::TensorInfo src0_info; + arm_compute::TensorInfo src1_info; + arm_compute::TensorInfo dst_info; + alg_kind_t alg; +}; + +struct acl_binary_resource_t : public resource_t { + acl_binary_resource_t() + : acl_obj_(utils::make_unique()) {} + + status_t configure(const acl_binary_conf_t &asp) { + if (!acl_obj_) return status::out_of_memory; + + // Init Compute Library tensors based on info from descriptor + acl_obj_->src0_tensor.allocator()->init(asp.src0_info); + acl_obj_->src1_tensor.allocator()->init(asp.src1_info); + acl_obj_->dst_tensor.allocator()->init(asp.dst_info); + + switch (asp.alg) { + case alg_kind::binary_add: { + auto add_op + = std::make_unique(); + add_op->configure(&acl_obj_->src0_tensor, + &acl_obj_->src1_tensor, &acl_obj_->dst_tensor, + arm_compute::ConvertPolicy::SATURATE); + acl_obj_->binary_op = std::move(add_op); + break; + } + case alg_kind::binary_sub: { + auto sub_op = std::make_unique< + arm_compute::NEArithmeticSubtraction>(); + sub_op->configure(&acl_obj_->src0_tensor, + &acl_obj_->src1_tensor, &acl_obj_->dst_tensor, + arm_compute::ConvertPolicy::SATURATE); + acl_obj_->binary_op = std::move(sub_op); + break; + } + case alg_kind::binary_div: { + auto div_op = std::make_unique< + arm_compute::NEElementwiseDivision>(); + div_op->configure(&acl_obj_->src0_tensor, + &acl_obj_->src1_tensor, &acl_obj_->dst_tensor); + acl_obj_->binary_op = std::move(div_op); + break; + } + case alg_kind::binary_mul: { + auto mul_op = std::make_unique< + arm_compute::NEPixelWiseMultiplication>(); + mul_op->configure(&acl_obj_->src0_tensor, + &acl_obj_->src1_tensor, &acl_obj_->dst_tensor, 1.0f, + arm_compute::ConvertPolicy::SATURATE, + arm_compute::RoundingPolicy::TO_ZERO); + acl_obj_->binary_op = std::move(mul_op); + break; + } + case alg_kind::binary_min: { + auto min_op = std::make_unique(); + min_op->configure(&acl_obj_->src0_tensor, + &acl_obj_->src1_tensor, &acl_obj_->dst_tensor); + acl_obj_->binary_op = std::move(min_op); + break; + } + case alg_kind::binary_max: { + auto max_op = std::make_unique(); + max_op->configure(&acl_obj_->src0_tensor, + &acl_obj_->src1_tensor, &acl_obj_->dst_tensor); + acl_obj_->binary_op = std::move(max_op); + break; + } + default: return status::runtime_error; + } + + return status::success; + } + + acl_binary_obj_t &get_acl_obj() const { return *acl_obj_; } + + DNNL_DISALLOW_COPY_AND_ASSIGN(acl_binary_resource_t); + +private: + std::unique_ptr acl_obj_; +}; // acl_binary_resource_t + +struct acl_binary_t : public primitive_t { + struct pd_t : public cpu_binary_pd_t { + using cpu_binary_pd_t::cpu_binary_pd_t; + + DECLARE_COMMON_PD_T("acl", acl_binary_t); + + status_t init(engine_t *engine) { + + using namespace acl_utils; + + // Only support f16/f32/s32 for now + data_type_t ddt = dst_md(0)->data_type; + if (!utils::one_of( + ddt, data_type::f16, data_type::f32, data_type::s32)) + return status::unimplemented; + + // Only support src and dst all matching for now + if (ddt != src_md(0)->data_type || src_md(1)->data_type != ddt) + return status::unimplemented; + + // Sets the memory format of dst from any to src_md(0) blocking desc + CHECK(set_default_params()); + + if (!attr()->has_default_values()) return status::unimplemented; + + asp_.alg = desc()->alg_kind; + + // All the algorithms we support + if (!utils::one_of(asp_.alg, alg_kind::binary_add, + alg_kind::binary_sub, alg_kind::binary_mul, + alg_kind::binary_div, alg_kind::binary_max, + alg_kind::binary_min)) + return status::unimplemented; + + // s32 div in ACL does not round as oneDNN expects + if (ddt == data_type::s32 && asp_.alg == alg_kind::binary_div) + return status::unimplemented; + + // ACL pointwise arithmetic operators assume that the innermost + // dimensions are dense for src0, src1 and dst. Reordering the + // logical dimensions by stride does this (if reordered_dims >= 1 ) + // and also makes memory accesses contiguous in ACL (without any + // data reordering). + memory_desc_t src_d0_permed, src_d1_permed, dst_d_permed; + int reordered_dims = reorder_dimensions_by_stride( + {&src_d0_permed, &src_d1_permed, &dst_d_permed}, + {src_md(0), src_md(1), dst_md()}); + if (reordered_dims < 1) return status::unimplemented; + + // Create ACL tensor infos with permuted descs + CHECK(tensor_info(asp_.src0_info, src_d0_permed)); + CHECK(tensor_info(asp_.src1_info, src_d1_permed)); + CHECK(tensor_info(asp_.dst_info, dst_d_permed)); + + // In this case ACL tries to treat src0 and src1 as a 1D array, but + // fails because the strides aren't equal. TODO: remove when fixed + // in ACL + if (asp_.alg == alg_kind::binary_add + && asp_.src0_info.tensor_shape() + == asp_.src1_info.tensor_shape() + && asp_.src0_info.strides_in_bytes() + != asp_.src1_info.strides_in_bytes()) { + return status::unimplemented; + } + + // This forces ACL not to parallelise with small workloads, this is + // a temporary fix and should be removed in future versions (TODO) + memory_desc_wrapper dst_d(dst_md()); + if (dst_d.nelems() < 40000) { + size_t acl_y_axis_i = 1; + CHECK(insert_singleton_dimension(asp_.src0_info, acl_y_axis_i)); + CHECK(insert_singleton_dimension(asp_.src1_info, acl_y_axis_i)); + CHECK(insert_singleton_dimension(asp_.dst_info, acl_y_axis_i)); + } + + // Call operator specific validate function to check support + ACL_CHECK_VALID(validate(asp_)); + + return status::success; + } + + acl_binary_conf_t asp_; + + private: + arm_compute::Status validate(const acl_binary_conf_t &asp) { + switch (asp.alg) { + case alg_kind::binary_add: + return arm_compute::NEArithmeticAddition::validate( + &asp.src0_info, &asp.src1_info, &asp.dst_info, + arm_compute::ConvertPolicy::SATURATE); + case alg_kind::binary_sub: + return arm_compute::NEArithmeticSubtraction::validate( + &asp.src0_info, &asp.src1_info, &asp.dst_info, + arm_compute::ConvertPolicy::SATURATE); + case alg_kind::binary_div: + return arm_compute::NEElementwiseDivision::validate( + &asp.src0_info, &asp.src1_info, &asp.dst_info); + case alg_kind::binary_mul: + return arm_compute::NEPixelWiseMultiplication::validate( + &asp.src0_info, &asp.src1_info, &asp.dst_info, 1.0f, + arm_compute::ConvertPolicy::SATURATE, + arm_compute::RoundingPolicy::TO_ZERO); + case alg_kind::binary_min: + return arm_compute::NEElementwiseMin::validate( + &asp.src0_info, &asp.src1_info, &asp.dst_info); + case alg_kind::binary_max: + return arm_compute::NEElementwiseMax::validate( + &asp.src0_info, &asp.src1_info, &asp.dst_info); + default: + return arm_compute::Status( + arm_compute::ErrorCode::RUNTIME_ERROR, + "unsupported alg_kind"); + } + } + + friend struct acl_post_ops_t; + }; // pd_t + + acl_binary_t(const pd_t *apd) : primitive_t(apd) {} + + status_t create_resource( + engine_t *engine, resource_mapper_t &mapper) const override { + if (mapper.has_resource(this)) return status::success; + + auto r = utils::make_unique(); + if (!r) return status::out_of_memory; + + // Configure the resource based on information from primitive descriptor + auto st = r->configure(pd()->asp_); + if (st == status::success) { mapper.add(this, std::move(r)); } + + return st; + } + + status_t execute(const exec_ctx_t &ctx) const override { + return execute_forward(ctx); + } + +private: + // To guard the const execute_forward, the mutex must be 'mutable' + mutable std::mutex mtx; + + status_t execute_forward(const exec_ctx_t &ctx) const; + // Execute forward with arbitrary src0, src1 and dst, used by acl_post_ops_t + status_t execute_forward(const exec_ctx_t &ctx, const void *src0, + const void *src1, void *dst) const; + + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + friend struct acl_post_ops_t; + +}; // acl_binary_t + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_convolution_utils.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_convolution_utils.hpp new file mode 100644 index 0000000000000000000000000000000000000000..4c5e134fd59708fdc5b2b70a92e01c39bba97935 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_convolution_utils.hpp @@ -0,0 +1,128 @@ +/******************************************************************************* +* Copyright 2020-2023 Arm Ltd. and affiliates +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_ACL_CONVOLUTION_UTILS_HPP +#define CPU_AARCH64_ACL_CONVOLUTION_UTILS_HPP + +#include "cpu/cpu_convolution_pd.hpp" + +#include "cpu/aarch64/acl_post_ops.hpp" +#include "cpu/aarch64/acl_utils.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +template +struct acl_obj_t { + NEConv conv; + arm_compute::Tensor src_tensor; + arm_compute::Tensor wei_tensor; + arm_compute::Tensor bia_tensor; + arm_compute::Tensor dst_tensor; +}; + +struct acl_conv_conf_t { + bool with_bias; + bool fast_math; + // If this is true, the result of the convolution goes into a temporarily + // allocated ACL tensor to be accumulated into the oneDNN dst during postops + bool use_dst_acc; + arm_compute::TensorInfo src_tensor_info; + arm_compute::TensorInfo wei_tensor_info; + arm_compute::TensorInfo bia_tensor_info; + arm_compute::TensorInfo dst_tensor_info; + arm_compute::PadStrideInfo padstride_info; + arm_compute::Size2D dilation_info; + // Additional information about the weights not included in wei_tensor_info + arm_compute::WeightsInfo weights_info; + // Note: this will default to not enabled, and will do nothing + arm_compute::ActivationLayerInfo act_info; +}; + +namespace acl_convolution_utils { + +status_t init_conf_gemm(acl_conv_conf_t &acp, memory_desc_t &src_md, + memory_desc_t &weights_md, memory_desc_t &dst_md, + memory_desc_t &bias_md, const convolution_desc_t &cd, + const primitive_attr_t &attr); + +status_t init_conf_indirect_gemm(acl_conv_conf_t &acp, memory_desc_t &src_md, + memory_desc_t &weights_md, memory_desc_t &dst_md, + memory_desc_t &bias_md, const convolution_desc_t &cd, + const primitive_attr_t &attr); + +status_t init_conf_depthwise(acl_conv_conf_t &acp, memory_desc_t &src_md, + memory_desc_t &weights_md, memory_desc_t &dst_md, + memory_desc_t &bias_md, const convolution_desc_t &cd, + const primitive_attr_t &attr); + +} // namespace acl_convolution_utils + +template +status_t execute_forward_conv_acl( + const exec_ctx_t &ctx, conv_obj_t &acl_conv_obj, const conv_pd_t *pd) { + bool with_bias = pd->acp_.with_bias; + bool use_dst_acc = pd->acp_.use_dst_acc; + + auto src_base = CTX_IN_MEM(const src_data_t *, DNNL_ARG_SRC); + auto wei_base = CTX_IN_MEM(const wei_data_t *, DNNL_ARG_WEIGHTS); + + // import_memory() and free() methods do not allocate/free any additional + // memory, only acquire/release pointers. + acl_conv_obj.src_tensor.allocator()->import_memory( + const_cast(src_base)); + acl_conv_obj.wei_tensor.allocator()->import_memory( + const_cast(wei_base)); + + if (use_dst_acc) { + // Put the result in a new tensor, it will be accumalated to the dst + // during the post ops + acl_conv_obj.dst_tensor.allocator()->allocate(); + } else { + auto dst_base = CTX_OUT_MEM(dst_data_t *, DNNL_ARG_DST); + acl_conv_obj.dst_tensor.allocator()->import_memory(dst_base); + } + + if (with_bias) { + auto bia_base = CTX_IN_MEM(const bia_data_t *, DNNL_ARG_BIAS); + acl_conv_obj.bia_tensor.allocator()->import_memory( + const_cast(bia_base)); + } + + acl_conv_obj.conv.run(); + + acl_conv_obj.src_tensor.allocator()->free(); + acl_conv_obj.wei_tensor.allocator()->free(); + if (with_bias) { acl_conv_obj.bia_tensor.allocator()->free(); } + + void *dst = acl_conv_obj.dst_tensor.buffer(); + pd->post_ops.execute(ctx, dst); + + acl_conv_obj.dst_tensor.allocator()->free(); + + return status::success; +} + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif // CPU_AARCH64_ACL_CONVOLUTION_UTILS_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_deconvolution.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_deconvolution.hpp new file mode 100644 index 0000000000000000000000000000000000000000..bc1da2a1fd37576a531b0f243d8baa12ab6412f8 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_deconvolution.hpp @@ -0,0 +1,335 @@ +/******************************************************************************* +* Copyright 2022-2023 Arm Ltd. and affiliates +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_ACL_DECONVOLUTION_HPP +#define CPU_AARCH64_ACL_DECONVOLUTION_HPP + +#include "cpu/aarch64/acl_post_ops.hpp" +#include "cpu/cpu_deconvolution_pd.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +struct acl_deconv_obj_t { + arm_compute::NEDeconvolutionLayer deconv; + arm_compute::Tensor src_tensor; + arm_compute::Tensor wei_tensor; + arm_compute::Tensor bia_tensor; + arm_compute::Tensor dst_tensor; +}; + +struct acl_deconv_conf_t { + bool with_bias; + // If this is true, the result of the convolution goes into a temporarily + // allocated ACL tensor to be accumulated into the oneDNN dst during postops + bool use_dst_acc; + bool fast_math; + arm_compute::TensorInfo src_info; + arm_compute::TensorInfo wei_info; + arm_compute::TensorInfo bia_info; + arm_compute::TensorInfo dst_info; + arm_compute::PadStrideInfo deconv_info; +}; + +struct acl_deconv_resource_t : public resource_t { + acl_deconv_resource_t() + : acl_obj_(utils::make_unique()) {} + + status_t configure(const acl_deconv_conf_t &adp) { + if (!acl_obj_) return status::out_of_memory; + + // Init Compute Library tensors based on info from descriptor + acl_obj_->src_tensor.allocator()->init(adp.src_info); + acl_obj_->wei_tensor.allocator()->init(adp.wei_info); + acl_obj_->bia_tensor.allocator()->init(adp.bia_info); + acl_obj_->dst_tensor.allocator()->init(adp.dst_info); + + // clang-format off + acl_obj_->deconv.configure( + &acl_obj_->src_tensor, + &acl_obj_->wei_tensor, + adp.with_bias ? &acl_obj_->bia_tensor : nullptr, + &acl_obj_->dst_tensor, + adp.deconv_info, adp.fast_math); + // clang-format on + + return status::success; + } + + acl_deconv_obj_t &get_acl_obj() const { return *acl_obj_; } + + DNNL_DISALLOW_COPY_AND_ASSIGN(acl_deconv_resource_t); + +private: + std::unique_ptr acl_obj_; +}; // acl_deconv_resource_t + +struct acl_deconvolution_fwd_t : public primitive_t { + struct pd_t : public cpu_deconvolution_fwd_pd_t { + using cpu_deconvolution_fwd_pd_t::cpu_deconvolution_fwd_pd_t; + pd_t(const deconvolution_desc_t *adesc, const primitive_attr_t *attr, + const deconvolution_fwd_pd_t *hint_fwd_pd) + : cpu_deconvolution_fwd_pd_t(adesc, attr, hint_fwd_pd) + , acl_pd_conf() + , post_ops() {} + + DECLARE_COMMON_PD_T("acl", acl_deconvolution_fwd_t); + + status_t init(engine_t *engine) { + using namespace data_type; + using namespace format_tag; + + const memory_desc_wrapper src_d(&src_md_); + const memory_desc_wrapper wei_d(&weights_md_); + const memory_desc_wrapper dst_d(&dst_md_); + const memory_desc_wrapper bia_d(&bias_md_); + + const auto src_data_t = src_d.data_type(); + const auto wei_data_t = wei_d.data_type(); + const auto dst_data_t = dst_d.data_type(); + const auto bia_data_t = bia_d.data_type(); + + const bool ok = is_fwd() // Only forward deconvolutions + && utils::one_of( + desc()->alg_kind, alg_kind::deconvolution_direct) + && attr()->has_default_values( + primitive_attr_t::skip_mask_t::post_ops, + dst_data_t); + if (!ok) return status::unimplemented; + + // Strides + const auto sh = KSH(); + const auto sw = KSW(); + + // Padding + const auto pt = padT(); + const auto pb = padB(); + const auto pl = padL(); + const auto pr = padR(); + + acl_pd_conf.deconv_info = arm_compute::PadStrideInfo(sw, sh, pl, pr, + pt, pb, arm_compute::DimensionRoundingType::FLOOR); + + // Tensor info + const auto mb = MB(); + + const auto ih = IH(); + const auto iw = IW(); + const auto ic = IC(); + + const auto oh = OH(); + const auto ow = OW(); + const auto oc = OC(); + + const auto kw = KW(); + const auto kh = KH(); + + const bool with_groups = G() != 1; + const int ndims = src_d.ndims(); + const bool is_1d = ndims == 3; + const bool is_3d = ndims == 5; + + // Compute Library unsupported shape scenarios + if (utils::one_of(true, is_3d, is_1d, with_groups)) { + return status::unimplemented; + } + + acl_pd_conf.with_bias + = desc_.bias_desc.format_kind != format_kind::undef; + + // Data type + + auto acl_src_data_t = acl_utils::get_acl_data_t(src_data_t); + auto acl_wei_data_t = acl_utils::get_acl_data_t(wei_data_t); + auto acl_dst_data_t = acl_utils::get_acl_data_t(dst_data_t); + auto acl_bia_data_t = acl_utils::get_acl_data_t(bia_data_t); + + if (acl_bia_data_t == arm_compute::DataType::UNKNOWN) { + acl_bia_data_t = arm_compute::DataType::F32; + } + + // Set memory formats + auto src_tag = src_d.format_kind() == format_kind::any + ? nhwc + : memory_desc_matches_one_of_tag(src_md_, nhwc, nchw); + auto dst_tag = dst_d.format_kind() == format_kind::any + ? nhwc + : memory_desc_matches_one_of_tag(dst_md_, nhwc, nchw); + + bool is_nspc = src_tag == nhwc; + + auto wei_tag = wei_d.format_kind() == format_kind::any + ? (is_nspc ? ohwi : oihw) + : memory_desc_matches_one_of_tag(weights_md_, ohwi, oihw); + + // Compute Library does not support mismatching layouts + if ((src_tag != wei_tag) || (src_tag != dst_tag)) { + return status::unimplemented; + } + + CHECK(memory_desc_init_by_tag(src_md_, src_tag)); + CHECK(memory_desc_init_by_tag(dst_md_, dst_tag)); + CHECK(memory_desc_init_by_tag(weights_md_, wei_tag)); + if (acl_pd_conf.with_bias) { + CHECK(memory_desc_init_by_tag(bias_md_, format_tag::a)); + } + + // Data layout + const auto acl_layout = is_nspc ? arm_compute::DataLayout::NHWC + : arm_compute::DataLayout::NCHW; + + acl_pd_conf.src_info = arm_compute::TensorInfo(is_nspc + ? arm_compute::TensorShape(ic, iw, ih, mb) + : arm_compute::TensorShape(iw, ih, ic, mb), + 1, acl_src_data_t, acl_layout); + + acl_pd_conf.wei_info = arm_compute::TensorInfo(is_nspc + ? arm_compute::TensorShape(ic, kw, kh, oc) + : arm_compute::TensorShape(kw, kh, ic, oc), + 1, acl_wei_data_t, acl_layout); + + acl_pd_conf.dst_info = arm_compute::TensorInfo(is_nspc + ? arm_compute::TensorShape(oc, ow, oh, mb) + : arm_compute::TensorShape(ow, oh, oc, mb), + 1, acl_dst_data_t, acl_layout); + + acl_pd_conf.bia_info = arm_compute::TensorInfo(acl_pd_conf.with_bias + ? arm_compute::TensorShape(oc) + : arm_compute::TensorShape(), + 1, acl_bia_data_t, acl_layout); + + acl_pd_conf.fast_math = utils::one_of( + attr()->fpmath_mode_, fpmath_mode::bf16, fpmath_mode::any); + + ACL_CHECK_VALID(arm_compute::NEDeconvolutionLayer::validate( + &acl_pd_conf.src_info, &acl_pd_conf.wei_info, + acl_pd_conf.with_bias ? &acl_pd_conf.bia_info : nullptr, + &acl_pd_conf.dst_info, acl_pd_conf.deconv_info, + acl_pd_conf.fast_math)); + + // Calculate scaled output tensor info for determining the convolution method + auto out_dims = arm_compute::deconvolution_output_dimensions( + iw, ih, kw, kh, acl_pd_conf.deconv_info); + uint32_t deconv_pad_x = 0; + uint32_t deconv_pad_y = 0; + auto scale_out_shape = arm_compute::misc::shape_calculator:: + compute_deconvolution_upsampled_shape(acl_pd_conf.src_info, + acl_pd_conf.wei_info, sw, sh, out_dims, + deconv_pad_x, deconv_pad_y); + + // If strides are unit in all dimensions, upsampling of input is skipped and a correct + // padding is set for convolution. Otherwise, describe deconvolution as convolution of + // upsampling input with stride = 1 and pad = 0. + arm_compute::ConvolutionMethod conv_method; + arm_compute::TensorInfo *conv_src_info; + unsigned int pad_left = 0; + unsigned int pad_right = 0; + unsigned int pad_top = 0; + unsigned int pad_bottom = 0; + if (sh != 1 || sw != 1) { + arm_compute::TensorInfo scale_out_info( + acl_pd_conf.src_info.clone() + ->set_is_resizable(true) + .reset_padding() + .set_tensor_shape(scale_out_shape)); + conv_src_info = &scale_out_info; + } else { + // compute correct padding here + pad_left = pr > pl ? pr - pl : 0; + pad_right = pl > pr ? pl - pr : 0; + pad_top = pb > pt ? pb - pt : 0; + pad_bottom = pt > pb ? pt - pb : 0; + + deconv_pad_x -= pad_left + pad_right; + deconv_pad_y -= pad_top + pad_bottom; + + pad_left += deconv_pad_x / 2; + pad_right += deconv_pad_x / 2; + pad_top += deconv_pad_y / 2; + pad_bottom += deconv_pad_y / 2; + + conv_src_info = &acl_pd_conf.src_info; + } + const arm_compute::PadStrideInfo conv_info(1, 1, pad_left, + pad_right, pad_top, pad_bottom, + arm_compute::DimensionRoundingType::CEIL); + conv_method + = arm_compute::NEConvolutionLayer::get_convolution_method( + conv_src_info, &acl_pd_conf.wei_info, + &acl_pd_conf.dst_info, conv_info, + arm_compute::WeightsInfo(), + arm_compute::Size2D(1U, 1U), + arm_compute::ActivationLayerInfo(), + acl_pd_conf.fast_math); + + // Disable use of winograd based convolution algorithm when performing + // direct deconvolution because it introduces accuracy loss. + if (conv_method == arm_compute::ConvolutionMethod::WINOGRAD) { + return status::unimplemented; + } + + CHECK(post_ops.init(engine, attr_.post_ops_, dst_md_)); + acl_pd_conf.use_dst_acc = post_ops.has_sum(); + + return status::success; + } + + acl_deconv_conf_t acl_pd_conf; + acl_post_ops_t post_ops; + + private: + bool post_ops_ok() const { + return attr()->post_ops_.find(primitive_kind::convolution) == -1; + } + }; // pd_t + + acl_deconvolution_fwd_t(const pd_t *apd) : primitive_t(apd) {} + + status_t execute(const exec_ctx_t &ctx) const override { + return execute_forward(ctx); + } + + status_t create_resource( + engine_t *engine, resource_mapper_t &mapper) const override { + if (mapper.has_resource(this)) return status::success; + + auto r = utils::make_unique(); + if (!r) return status::out_of_memory; + + // Configure the resource based on information from primitive descriptor + auto st = r->configure(pd()->acl_pd_conf); + if (st == status::success) { mapper.add(this, std::move(r)); } + + CHECK(pd()->post_ops.create_resource(engine, mapper)); + + return st; + } + +private: + // To guard the const execute_forward, the mutex must be 'mutable' + mutable std::mutex mtx; + status_t execute_forward(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } +}; // acl_deconvolution_fwd_t + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_depthwise_convolution.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_depthwise_convolution.hpp new file mode 100644 index 0000000000000000000000000000000000000000..3e3d02cf411a48bb26e8d3f62eb243a88e15ce25 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_depthwise_convolution.hpp @@ -0,0 +1,141 @@ +/******************************************************************************* +* Copyright 2023 Arm Ltd. and affiliates +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_ACL_DEPTHWISE_CONVOLUTION_HPP +#define CPU_AARCH64_ACL_DEPTHWISE_CONVOLUTION_HPP + +#include "cpu/aarch64/acl_convolution_utils.hpp" +#include "cpu/cpu_convolution_pd.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +struct acl_depthwise_convolution_resource_t : public resource_t { + acl_depthwise_convolution_resource_t() + : acl_obj_(utils::make_unique< + acl_obj_t>()) {} + + status_t configure(const acl_conv_conf_t &acp) { + if (!acl_obj_) return status::out_of_memory; + + acl_obj_->src_tensor.allocator()->init(acp.src_tensor_info); + acl_obj_->wei_tensor.allocator()->init(acp.wei_tensor_info); + acl_obj_->dst_tensor.allocator()->init(acp.dst_tensor_info); + acl_obj_->bia_tensor.allocator()->init(acp.bia_tensor_info); + + // clang-format off + acl_obj_->conv.configure( + &acl_obj_->src_tensor, + &acl_obj_->wei_tensor, + acp.with_bias ? &acl_obj_->bia_tensor : nullptr, + &acl_obj_->dst_tensor, + acp.padstride_info, + 1, // depth multiplier default value + acp.act_info); + + // clang-format on + return status::success; + } + + acl_obj_t &get_acl_obj() const { + return *acl_obj_; + } + + DNNL_DISALLOW_COPY_AND_ASSIGN(acl_depthwise_convolution_resource_t); + +private: + std::unique_ptr> + acl_obj_; +}; + +struct acl_depthwise_convolution_fwd_t : public primitive_t { + + struct pd_t : public cpu_convolution_fwd_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const typename pd_t::base_class *hint_fwd_pd) + : cpu_convolution_fwd_pd_t(adesc, attr, hint_fwd_pd), acp_() {} + + DECLARE_COMMON_PD_T("depthwise_convolution:acl", + acl_depthwise_convolution_fwd_t, USE_GLOBAL_SCRATCHPAD); + + status_t init(engine_t *engine) { + using namespace data_type; + + const bool is_fp16_ok = expect_data_types(f16, f16, f16, f16, undef) + && attr()->has_default_values( + primitive_attr_t::skip_mask_t::post_ops, f16); + const bool is_fp32_ok = expect_data_types(f32, f32, f32, f32, undef) + && attr()->has_default_values( + primitive_attr_t::skip_mask_t::post_ops, f32); + bool ok = is_fwd() + && set_default_alg_kind(alg_kind::convolution_direct) + && utils::one_of(true, is_fp16_ok, is_fp32_ok) + && !has_zero_dim_memory(); + if (!ok) return status::unimplemented; + + CHECK(acl_convolution_utils::init_conf_depthwise(acp_, src_md_, + weights_md_, dst_md_, bias_md_, *desc(), *attr())); + + CHECK(post_ops.init( + engine, attr_.post_ops_, dst_md_, acp_.act_info)); + acp_.use_dst_acc = post_ops.has_sum(); + + return status::success; + } + + acl_conv_conf_t acp_; + + acl_post_ops_t post_ops; + }; + + acl_depthwise_convolution_fwd_t(const pd_t *apd) : primitive_t(apd) {} + + status_t create_resource( + engine_t *engine, resource_mapper_t &mapper) const override { + if (mapper.has_resource(this)) return status::success; + + auto r = utils::make_unique(); + if (!r) return status::out_of_memory; + + CHECK(r->configure(pd()->acp_)); + mapper.add(this, std::move(r)); + + CHECK(pd()->post_ops.create_resource(engine, mapper)); + + return status::success; + } + + typedef typename prec_traits::type data_t; + + status_t execute(const exec_ctx_t &ctx) const override { + return execute_forward(ctx); + } + +private: + mutable std::mutex mtx; + status_t execute_forward(const exec_ctx_t &ctx) const; + + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } +}; + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif // CPU_AARCH64_ACL_DEPTHWISE_CONVOLUTION_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_eltwise.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_eltwise.hpp new file mode 100644 index 0000000000000000000000000000000000000000..5e5c398ac396b87c7ca0acf65b2106acc6339e72 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_eltwise.hpp @@ -0,0 +1,162 @@ +/******************************************************************************* +* Copyright 2021-2022 Arm Ltd. and affiliates +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_ACL_ELTWISE_HPP +#define CPU_AARCH64_ACL_ELTWISE_HPP + +#include "cpu/cpu_eltwise_pd.hpp" + +#include "cpu/aarch64/acl_utils.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +struct acl_eltwise_obj_t { + arm_compute::NEActivationLayer act; + arm_compute::Tensor src_tensor; + arm_compute::Tensor dst_tensor; +}; + +struct acl_eltwise_conf_t { + arm_compute::ActivationLayerInfo act_info; + // src and dst have the same info + arm_compute::TensorInfo data_info; +}; + +struct acl_eltwise_resource_t : public resource_t { + acl_eltwise_resource_t() + : acl_eltwise_obj_(utils::make_unique()) {} + + status_t configure(const acl_eltwise_conf_t &aep) { + if (!acl_eltwise_obj_) return status::out_of_memory; + + // Init Compute Library tensors based on info from descriptor + acl_eltwise_obj_->src_tensor.allocator()->init(aep.data_info); + acl_eltwise_obj_->dst_tensor.allocator()->init(aep.data_info); + + acl_eltwise_obj_->act.configure(&acl_eltwise_obj_->src_tensor, + &acl_eltwise_obj_->dst_tensor, aep.act_info); + + return status::success; + } + + acl_eltwise_obj_t &get_acl_obj() const { return *acl_eltwise_obj_; } + + DNNL_DISALLOW_COPY_AND_ASSIGN(acl_eltwise_resource_t); + +private: + std::unique_ptr acl_eltwise_obj_; +}; // acl_eltwise_resource_t + +struct acl_eltwise_fwd_t : public primitive_t { + struct pd_t : public cpu_eltwise_fwd_pd_t { + using cpu_eltwise_fwd_pd_t::cpu_eltwise_fwd_pd_t; + + DECLARE_COMMON_PD_T("acl", acl_eltwise_fwd_t); + + status_t init(engine_t *engine) { + using namespace utils; + using namespace data_type; + const memory_desc_wrapper src_d(src_md()); + + bool ok = is_fwd() && one_of(src_d.data_type(), f32, f16, s32, s8) + && !has_zero_dim_memory() && attr()->has_default_values() + && set_default_formats_common() && src_d.is_dense() + && src_d == memory_desc_wrapper(dst_md()); + if (!ok) return status::unimplemented; + + // Workaround for the nan-value caused by tanh of ACL for fp16 + // ARM-software/ComputeLibrary#998. Workaround for the inaccuracies + // caused by logistic/soft_relu/elu of ACL for fp16. + // TODO: Relax the error bounds in eltwise checks, or rework these + // fp16 operations in ACL for better accuracy. + using namespace dnnl::impl::alg_kind; + if (src_d.data_type() == f16 + && utils::one_of(desc_.alg_kind, eltwise_tanh, + eltwise_logistic, eltwise_soft_relu, eltwise_elu)) { + return status::unimplemented; + } + + auto acl_data_t = acl_utils::get_acl_data_t(src_d.data_type()); + + // Operator acts elementwise, so we only require that the product of + // all the dimensions equals the total number of elements. We are + // free to swap/combine dimensions. ACL performs SIMD parallelism + // over the first dimension and thread parallelism over the second. + // We pick a single dimension to thread over (taking the max of 2 to + // reduce the chance of it being 1), with the remaining dimensions + // to SIMD over. + dim_t thread_dim = std::max(W(), ndims() >= 2 ? C() : 1); + auto shape = arm_compute::TensorShape( + src_d.nelems() / thread_dim, thread_dim); + aep.data_info = arm_compute::TensorInfo(shape, 1, acl_data_t); + + CHECK(acl_utils::convert_to_acl_act(desc_, aep.act_info)); + + ACL_CHECK_VALID(arm_compute::NEActivationLayer::validate( + &aep.data_info, &aep.data_info, aep.act_info)); + + return status::success; + } + + acl_eltwise_conf_t aep; + + friend struct acl_post_ops_t; + }; + + acl_eltwise_fwd_t(const pd_t *apd) : primitive_t(apd) {} + + status_t execute(const exec_ctx_t &ctx) const override { + return execute_forward(ctx); + } + + status_t create_resource( + engine_t *engine, resource_mapper_t &mapper) const override { + if (mapper.has_resource(this)) return status::success; + + auto r = utils::make_unique(); + if (!r) return status::out_of_memory; + + // Configure the resource based on information from primitive descriptor + CHECK(r->configure(pd()->aep)); + mapper.add(this, std::move(r)); + + return status::success; + } + +private: + // execute_forward has to be const thus mutability of mtx + mutable std::mutex mtx; + + status_t execute_forward(const exec_ctx_t &ctx) const; + + // Execute forward with arbitrary src and dst, used by acl_post_ops_t + status_t execute_forward( + const exec_ctx_t &ctx, const void *src, void *dst) const; + + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + friend struct acl_post_ops_t; +}; // acl_eltwise_fwd_t + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif // CPU_AARCH64_ACL_ELTWISE_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_gemm_convolution.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_gemm_convolution.hpp new file mode 100644 index 0000000000000000000000000000000000000000..e21fbbf97c9aae25f79b61e8119885b147d117e5 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_gemm_convolution.hpp @@ -0,0 +1,156 @@ +/******************************************************************************* +* Copyright 2020-2023 Arm Ltd. and affiliates +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_ACL_GEMM_CONVOLUTION_HPP +#define CPU_AARCH64_ACL_GEMM_CONVOLUTION_HPP + +#include "cpu/cpu_convolution_pd.hpp" + +#include "cpu/aarch64/acl_convolution_utils.hpp" +#include "cpu/aarch64/acl_post_ops.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +struct acl_resource_t : public resource_t { + acl_resource_t() + : acl_obj_(utils::make_unique< + acl_obj_t>()) {} + + status_t configure(const acl_conv_conf_t &acp) { + if (!acl_obj_) return status::out_of_memory; + + // Init Compute Library tensors based on info from descriptor + acl_obj_->src_tensor.allocator()->init(acp.src_tensor_info); + acl_obj_->wei_tensor.allocator()->init(acp.wei_tensor_info); + acl_obj_->dst_tensor.allocator()->init(acp.dst_tensor_info); + acl_obj_->bia_tensor.allocator()->init(acp.bia_tensor_info); + + acl_obj_->conv.configure(&acl_obj_->src_tensor, &acl_obj_->wei_tensor, + acp.with_bias ? &acl_obj_->bia_tensor : nullptr, + &acl_obj_->dst_tensor, acp.padstride_info, acp.weights_info, + acp.dilation_info, acp.act_info, acp.fast_math); + return status::success; + } + + acl_obj_t &get_acl_obj() const { + return *acl_obj_; + } + + DNNL_DISALLOW_COPY_AND_ASSIGN(acl_resource_t); + +private: + std::unique_ptr> acl_obj_; + +}; // acl_resource_t + +template +struct acl_gemm_convolution_fwd_t : public primitive_t { + struct pd_t : public cpu_convolution_fwd_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const typename pd_t::base_class *hint_fwd_pd) + : cpu_convolution_fwd_pd_t(adesc, attr, hint_fwd_pd), acp_() {} + + DECLARE_COMMON_PD_T( + "gemm:acl", acl_gemm_convolution_fwd_t, USE_GLOBAL_SCRATCHPAD); + + status_t init(engine_t *engine) { + using namespace data_type; + using smask_t = primitive_attr_t::skip_mask_t; + + bool ok = is_fwd() + && set_default_alg_kind(alg_kind::convolution_direct) + && expect_data_types( + src_type, wei_type, bia_type, dst_type, undef) + && !has_zero_dim_memory() + && attr()->has_default_values(smask_t::post_ops, dst_type) + && output_scales_mask_ok() && zero_points_ok(); + if (!ok) return status::unimplemented; + + CHECK(acl_convolution_utils::init_conf_gemm(acp_, src_md_, + weights_md_, dst_md_, bias_md_, *desc(), *attr())); + + CHECK(post_ops.init( + engine, attr_.post_ops_, dst_md_, acp_.act_info)); + acp_.use_dst_acc = post_ops.has_sum(); + + return status::success; + } + + acl_conv_conf_t acp_; + + acl_post_ops_t post_ops; + + protected: + bool output_scales_mask_ok() const { + using namespace data_type; + const auto &mask = attr()->output_scales_.mask_; + return IMPLICATION(!utils::one_of(src_type, s8, u8), + attr()->output_scales_.has_default_values()) + // TODO: add support for per_channel quantization + && mask == 0; + } + + bool zero_points_ok() const { + using namespace data_type; + // TODO: add support for asymmetric quantization + return attr()->zero_points_.has_default_values(); + } + }; + + acl_gemm_convolution_fwd_t(const pd_t *apd) : primitive_t(apd) {} + + status_t create_resource( + engine_t *engine, resource_mapper_t &mapper) const override { + if (mapper.has_resource(this)) return status::success; + + auto r = utils::make_unique(); + if (!r) return status::out_of_memory; + + // Configure the resource based on information from primitive descriptor + CHECK(r->configure(pd()->acp_)); + mapper.add(this, std::move(r)); + + CHECK(pd()->post_ops.create_resource(engine, mapper)); + + return status::success; + } + + typedef typename prec_traits::type src_data_t; + typedef typename prec_traits::type wei_data_t; + typedef typename prec_traits::type dst_data_t; + typedef typename prec_traits::type bia_data_t; + + status_t execute(const exec_ctx_t &ctx) const override { + return execute_forward(ctx); + } + +private: + // To guard the const execute_forward(), the mutex must be 'mutable' + mutable std::mutex mtx; + status_t execute_forward(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } +}; // acl_gemm_convolution_fwd_t + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_indirect_gemm_convolution.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_indirect_gemm_convolution.hpp new file mode 100644 index 0000000000000000000000000000000000000000..2cba9ab6a6ccfefdf6cfbd8348e1a2bf23aeb3a7 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_indirect_gemm_convolution.hpp @@ -0,0 +1,147 @@ +/******************************************************************************* +* Copyright 2021-2023 Arm Ltd. and affiliates +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_ACL_INDIRECT_GEMM_CONVOLUTION_HPP +#define CPU_AARCH64_ACL_INDIRECT_GEMM_CONVOLUTION_HPP + +#include "cpu/cpu_convolution_pd.hpp" + +#include "cpu/aarch64/acl_convolution_utils.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +struct acl_indirect_gemm_resource_t : public resource_t { + acl_indirect_gemm_resource_t() + : acl_obj_(utils::make_unique>()) { + } + + status_t configure(const acl_conv_conf_t &acp) { + if (!acl_obj_) return status::out_of_memory; + + // Init Compute Library tensors based on info from descriptor + acl_obj_->src_tensor.allocator()->init(acp.src_tensor_info); + acl_obj_->wei_tensor.allocator()->init(acp.wei_tensor_info); + acl_obj_->dst_tensor.allocator()->init(acp.dst_tensor_info); + acl_obj_->bia_tensor.allocator()->init(acp.bia_tensor_info); + + // clang-format off + acl_obj_->conv.configure( + &acl_obj_->src_tensor, + &acl_obj_->wei_tensor, + acp.with_bias ? &acl_obj_->bia_tensor : nullptr, + &acl_obj_->dst_tensor, + arm_compute::Conv2dInfo(acp.padstride_info, + acp.dilation_info, + acp.act_info, + acp.fast_math, + 1, + {}, + acp.weights_info)); + // clang-format on + + return status::success; + } + + acl_obj_t &get_acl_obj() const { + return *acl_obj_; + } + + DNNL_DISALLOW_COPY_AND_ASSIGN(acl_indirect_gemm_resource_t); + +private: + std::unique_ptr> acl_obj_; + +}; // acl_indirect_gemm_resource_t + +struct acl_indirect_gemm_convolution_fwd_t : public primitive_t { + + struct pd_t : public cpu_convolution_fwd_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const typename pd_t::base_class *hint_fwd_pd) + : cpu_convolution_fwd_pd_t(adesc, attr, hint_fwd_pd), acp_() {} + + DECLARE_COMMON_PD_T("indirect_gemm:acl", + acl_indirect_gemm_convolution_fwd_t, USE_GLOBAL_SCRATCHPAD); + + status_t init(engine_t *engine) { + using namespace data_type; + const bool is_fp16_ok = expect_data_types(f16, f16, f16, f16, undef) + && attr()->has_default_values( + primitive_attr_t::skip_mask_t::post_ops, f16); + const bool is_fp32_ok = expect_data_types(f32, f32, f32, f32, undef) + && attr()->has_default_values( + primitive_attr_t::skip_mask_t::post_ops, f32); + bool ok = is_fwd() + && set_default_alg_kind(alg_kind::convolution_direct) + && utils::one_of(true, is_fp16_ok, is_fp32_ok) + && !has_zero_dim_memory(); + if (!ok) return status::unimplemented; + + CHECK(acl_convolution_utils::init_conf_indirect_gemm(acp_, src_md_, + weights_md_, dst_md_, bias_md_, *desc(), *attr())); + + CHECK(post_ops.init( + engine, attr_.post_ops_, dst_md_, acp_.act_info)); + acp_.use_dst_acc = post_ops.has_sum(); + + return status::success; + } + + acl_conv_conf_t acp_; + + acl_post_ops_t post_ops; + }; + + acl_indirect_gemm_convolution_fwd_t(const pd_t *apd) : primitive_t(apd) {} + + status_t create_resource( + engine_t *engine, resource_mapper_t &mapper) const override { + if (mapper.has_resource(this)) return status::success; + + auto r = utils::make_unique(); + if (!r) return status::out_of_memory; + + // Configure the resource based on information from primitive descriptor + CHECK(r->configure(pd()->acp_)); + mapper.add(this, std::move(r)); + + CHECK(pd()->post_ops.create_resource(engine, mapper)); + + return status::success; + } + + typedef typename prec_traits::type data_t; + + status_t execute(const exec_ctx_t &ctx) const override { + return execute_forward(ctx); + } + +private: + // To guard the const execute_forward(), the mutex must be 'mutable' + mutable std::mutex mtx; + status_t execute_forward(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } +}; + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif // CPU_AARCH64_ACL_INDIRECT_GEMM_CONVOLUTION_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_inner_product.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_inner_product.hpp new file mode 100644 index 0000000000000000000000000000000000000000..a2be164f09ca519fd0d581411c392708e598554a --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_inner_product.hpp @@ -0,0 +1,314 @@ +/******************************************************************************* +* Copyright 2021-2023 Arm Ltd. and affiliates +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_ACL_INNER_PRODUCT_HPP +#define CPU_AARCH64_ACL_INNER_PRODUCT_HPP + +#include "cpu/aarch64/acl_utils.hpp" +#include "cpu/cpu_inner_product_pd.hpp" + +#include "cpu/aarch64/acl_post_ops.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +struct acl_ip_obj_t { + arm_compute::NEFullyConnectedLayer fc; + arm_compute::Tensor src_tensor; + arm_compute::Tensor wei_tensor; + arm_compute::Tensor bia_tensor; + arm_compute::Tensor dst_tensor; +}; + +struct acl_ip_conf_t { + bool with_bias; + // If this is true, the result of the inner product goes into a temporarily + // allocated ACL tensor to be accumulated into the oneDNN dst during postops + bool use_dst_acc; + arm_compute::TensorInfo src_tensor_info; + arm_compute::TensorInfo wei_tensor_info; + arm_compute::TensorInfo bia_tensor_info; + arm_compute::TensorInfo dst_tensor_info; + arm_compute::FullyConnectedLayerInfo fc_info; + // Additional information about the weights not included in wei_tensor_info + arm_compute::WeightsInfo weights_info; +}; +struct acl_ip_resource_t : public resource_t { + acl_ip_resource_t() : acl_ip_obj_(utils::make_unique()) {} + + status_t configure(const acl_ip_conf_t &aip) { + if (!acl_ip_obj_) return status::out_of_memory; + + // Init Compute Library tensors based on info from descriptor + acl_ip_obj_->src_tensor.allocator()->init(aip.src_tensor_info); + acl_ip_obj_->wei_tensor.allocator()->init(aip.wei_tensor_info); + acl_ip_obj_->dst_tensor.allocator()->init(aip.dst_tensor_info); + acl_ip_obj_->bia_tensor.allocator()->init(aip.bia_tensor_info); + + // clang-format off + acl_ip_obj_->fc.configure( + &acl_ip_obj_->src_tensor, + &acl_ip_obj_->wei_tensor, + aip.with_bias ? &acl_ip_obj_->bia_tensor : nullptr, + &acl_ip_obj_->dst_tensor, + aip.fc_info, + aip.weights_info); + // clang-format on + + return status::success; + } + + acl_ip_obj_t &get_acl_obj() const { return *acl_ip_obj_; } + + DNNL_DISALLOW_COPY_AND_ASSIGN(acl_ip_resource_t); + +private: + std::unique_ptr acl_ip_obj_; +}; // acl_ip_resource_t + +struct acl_inner_product_fwd_t : public primitive_t { + struct pd_t : public cpu_inner_product_fwd_pd_t { + using cpu_inner_product_fwd_pd_t::cpu_inner_product_fwd_pd_t; + + pd_t(const inner_product_desc_t *adesc, const primitive_attr_t *attr, + const typename pd_t::base_class *hint_fwd_pd) + : cpu_inner_product_fwd_pd_t(adesc, attr, hint_fwd_pd), aip() {} + + DECLARE_COMMON_PD_T("acl", acl_inner_product_fwd_t); + + status_t init(engine_t *engine) { + using namespace data_type; + const bool is_fp16_ok = expect_data_types(f16, f16, f16, f16, undef) + && attr()->has_default_values( + primitive_attr_t::skip_mask_t::post_ops, f16); + const bool is_fp32_ok = expect_data_types(f32, f32, f32, f32, undef) + && attr()->has_default_values( + primitive_attr_t::skip_mask_t::post_ops, f32); + const bool ok = is_fwd() && !has_zero_dim_memory() + && utils::one_of(true, is_fp16_ok, is_fp32_ok) + && weights_md_.format_kind == format_kind::any + && set_default_params() == status::success; + + if (!ok) return status::unimplemented; + + CHECK(init_conf_ip(engine)); + + return status::success; + } + + acl_ip_conf_t aip; + + acl_post_ops_t post_ops; + + status_t init_conf_ip(engine_t *engine) { + + ACL_CHECK_SUPPORT(src_md()->ndims != weights_md()->ndims, + "source and weights dimensions must match"); + + const int ndims = src_md()->ndims; + + const bool is_2d = (ndims == 2); + const bool is_4d = (ndims == 4); + + ACL_CHECK_SUPPORT( + !(is_2d || is_4d), "ACL supports only 2d or 4d cases"); + + using namespace format_tag; + auto src_tag + = memory_desc_matches_one_of_tag(src_md_, nhwc, nchw, nc); + auto dst_tag = memory_desc_matches_one_of_tag(dst_md_, nc); + + ACL_CHECK_SUPPORT( + utils::one_of(format_tag::undef, src_tag, dst_tag), + "unsupported memory layout"); + + ACL_CHECK_SUPPORT(is_2d && src_tag != dst_tag, + "for src and dst layouts must match"); + + const dim_t ic_total = IC_total(); + const dim_t n = MB(); + const dim_t oc = OC(); + + aip.src_tensor_info = arm_compute::TensorInfo( + arm_compute::TensorShape(ic_total, n), 1, + acl_utils::get_acl_data_t(src_md()->data_type)); + + // ACL requires the weights to be in 2D flattened shape + aip.wei_tensor_info = arm_compute::TensorInfo( + arm_compute::TensorShape(oc, ic_total), 1, + acl_utils::get_acl_data_t(weights_md(0)->data_type)); + + auto acl_dst_data_t + = acl_utils::get_acl_data_t(dst_md()->data_type); + aip.dst_tensor_info = arm_compute::TensorInfo( + arm_compute::TensorShape(oc, n), 1, acl_dst_data_t); + + aip.with_bias = desc()->bias_desc.format_kind != format_kind::undef; + auto acl_bia_data_t = aip.with_bias + ? acl_utils::get_acl_data_t(weights_md(1)->data_type) + : acl_dst_data_t; + aip.bia_tensor_info = arm_compute::TensorInfo(aip.with_bias + ? arm_compute::TensorShape(oc) + : arm_compute::TensorShape(), + 1, acl_bia_data_t); + + aip.fc_info.transpose_weights = false; + + aip.fc_info.enable_fast_math = utils::one_of( + attr()->fpmath_mode_, fpmath_mode::bf16, fpmath_mode::any); + + CHECK(post_ops.init(engine, attr_.post_ops_, dst_md_, + aip.fc_info.activation_info)); + aip.use_dst_acc = post_ops.has_sum(); + + // WeightFormat::ANY tells ACL we can handle any format + aip.weights_info = arm_compute::WeightsInfo(false, 1, 1, ic_total, + false, arm_compute::WeightFormat::ANY); + + // Get the format that the ACL kernel will expect the weights to be + // in (if a kernel exists) Note that these are referred to as fixed + // format kernels, because they require one specific weights format + arm_compute::WeightFormat expected_weight_format; + ACL_CHECK_VALID(arm_compute::NEFullyConnectedLayer::has_opt_impl( + expected_weight_format, &aip.src_tensor_info, + &aip.wei_tensor_info, + aip.with_bias ? &aip.bia_tensor_info : nullptr, + &aip.dst_tensor_info, aip.fc_info, aip.weights_info)); + + // Set weights info to the one returned by has_opt_impl + aip.weights_info.set_weight_format(expected_weight_format); + + // has_opt_impl may return a non fast math kernel, even if requested + aip.fc_info.enable_fast_math + = arm_compute::is_fixed_format_fast_math( + expected_weight_format); + + // Inner product is the same as the matmul n x (chw) * (ihw) x o + // (note that the src c and weights i both correspond to the input + // channel). ACL FullyConnectedLayer assumes the chw dimensions of + // src and ihw dimensions of weights are collapsed, so we need to + // make sure that they have the same layout. Given that weights are + // more often fixed, (so reorders can be hoisted) it makes sense to + // reorder the weights to fit the src. + + // For 4D tensors we need to: + // - reorder the ihw of the weights to match the src chw + // - collapse ihw + // - pad the collapsed ihw + // But there is not yet a way to express this collapse+pad as a + // reorder. So we try to reorder the weights to match the src, + // implicitly collapse ihw in our definition of the weights + // TensorInfo and hope that the inner_dim has zero padding + // (weights_md_.dims[inner_dim] % block_by == 0). If it does, we + // fall back to a kernel without blocking (currently this is + // equivalent to non-fastmath). + + // 2D just works because we just pad the only dimension. + + // o_dim is always the first logical dimension (oihw, ohwi, oi) + dim_t o_dim = 0; + dim_t inner_dim; + // Rest of logical dimensions in order of innermost to outermost + std::vector remaining_dims = {}; + + if (src_tag == nchw) { + inner_dim = 3; // w + remaining_dims = {2, 1}; // h, i + } else if (src_tag == nhwc) { + inner_dim = 1; // i + remaining_dims = {3, 2}; // w, h + } else { // Only remaining case is 2D (nc) + inner_dim = 1; // i + remaining_dims = {}; // No other dimensions for 2D + } + + // Fallback + int block_by = arm_compute::block_by(expected_weight_format); + if (is_4d && weights_md_.dims[inner_dim] % block_by != 0 + && aip.fc_info.enable_fast_math) { + aip.fc_info.enable_fast_math = false; + aip.weights_info.set_weight_format( + arm_compute::WeightFormat::ANY); + ACL_CHECK_VALID( + arm_compute::NEFullyConnectedLayer::has_opt_impl( + expected_weight_format, &aip.src_tensor_info, + &aip.wei_tensor_info, + aip.with_bias ? &aip.bia_tensor_info : nullptr, + &aip.dst_tensor_info, aip.fc_info, + aip.weights_info)); + aip.weights_info.set_weight_format(expected_weight_format); + block_by = arm_compute::block_by(expected_weight_format); + if (weights_md_.dims[inner_dim] % block_by != 0) + return status::unimplemented; + } + + acl_utils::reorder_to_weight_format(aip.wei_tensor_info, + weights_md_, expected_weight_format, inner_dim, o_dim, + remaining_dims, {}); + + // clang-format off + + // Validate fully connected layer manually to check for return status + ACL_CHECK_VALID(arm_compute::NEFullyConnectedLayer::validate( + &aip.src_tensor_info, + &aip.wei_tensor_info, + aip.with_bias ? &aip.bia_tensor_info : nullptr, + &aip.dst_tensor_info, + aip.fc_info, + aip.weights_info)); + // clang-format on + + return status::success; + } + }; // pd_t + + acl_inner_product_fwd_t(const pd_t *apd) : primitive_t(apd) {} + + status_t create_resource( + engine_t *engine, resource_mapper_t &mapper) const override { + if (mapper.has_resource(this)) return status::success; + + auto r = utils::make_unique(); + if (!r) return status::out_of_memory; + + // Configure the resource based on information from primitive descriptor + CHECK(r->configure(pd()->aip)); + mapper.add(this, std::move(r)); + + CHECK(pd()->post_ops.create_resource(engine, mapper)); + + return status::success; + } + + status_t execute(const exec_ctx_t &ctx) const override { + return execute_forward(ctx); + } + +private: + //To guard the const execute_forward, the mutex must be 'mutable' + mutable std::mutex mtx; + status_t execute_forward(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } +}; // acl_inner_product_fwd_t + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif // CPU_AARCH64_ACL_INNER_PRODUCT_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_layer_normalization.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_layer_normalization.hpp new file mode 100644 index 0000000000000000000000000000000000000000..80dd681a84bf04217803b1fefc2f49a8db7b24db --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_layer_normalization.hpp @@ -0,0 +1,258 @@ +/******************************************************************************* +* Copyright 2023 Arm Ltd. and affiliates +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_ACL_LAYER_NORMALIZATION_HPP +#define CPU_AARCH64_ACL_LAYER_NORMALIZATION_HPP + +#include "cpu/aarch64/acl_utils.hpp" +#include "cpu/cpu_layer_normalization_pd.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +struct acl_msdnorm_obj_t { + arm_compute::NEMeanStdDevNormalizationLayer msdNorm; + arm_compute::Tensor src_tensor; + arm_compute::Tensor dst_tensor; +}; + +struct acl_msdnorm_conf_t { + arm_compute::TensorInfo data_info; // src and dst tensors +}; + +struct acl_layer_normalization_resource_t : public resource_t { + acl_layer_normalization_resource_t() + : acl_obj(utils::make_unique()) {} + + status_t configure( + const acl_msdnorm_conf_t &anp, const layer_normalization_pd_t *pd) { + if (!acl_obj) return status::out_of_memory; + + acl_obj->src_tensor.allocator()->init(anp.data_info); + acl_obj->dst_tensor.allocator()->init(anp.data_info); + + // clang-format off + acl_obj->msdNorm.configure( + &acl_obj->src_tensor, + &acl_obj->dst_tensor, + pd->desc()->layer_norm_epsilon); + // clang-format on + + return status::success; + } + + acl_msdnorm_obj_t &get_acl_obj() const { return *acl_obj; } + + DNNL_DISALLOW_COPY_AND_ASSIGN(acl_layer_normalization_resource_t); + +private: + std::unique_ptr acl_obj; +}; // acl_layer_normalization_resource_t + +struct acl_layer_normalization_fwd_t : public primitive_t { + struct pd_t : public cpu_layer_normalization_fwd_pd_t { + using cpu_layer_normalization_fwd_pd_t:: + cpu_layer_normalization_fwd_pd_t; + pd_t(const layer_normalization_desc_t *adesc, + const primitive_attr_t *attr, + const typename pd_t::base_class *hint_fwd_pd) + : cpu_layer_normalization_fwd_pd_t(adesc, attr, hint_fwd_pd) + , anp() {} + + DECLARE_COMMON_PD_T("acl", acl_layer_normalization_fwd_t); + + status_t init(engine_t *engine) { + + // dir and flags + ACL_CHECK_SUPPORT( + !is_fwd(), "ACL lnorm supports forward propagation only"); + ACL_CHECK_SUPPORT(is_training() && !use_global_stats(), + "ACL only supports forward training with lnorm if stats " + "are provided (use global stats)"); + ACL_CHECK_SUPPORT(use_scale() || use_shift(), + "ACL does not support lnorm scale and shift"); + + // attr-scales + ACL_CHECK_SUPPORT(!attr()->has_default_values(), + "ACL does not support scales attribute"); + + // tag and stat_tag + ACL_CHECK_SUPPORT(src_md()->ndims < 2 || src_md()->ndims > 5, + "src tensor must have between 2 and 5 (inclusive) " + "dimensions"); + + // msdNorm only supports lnorm for src in a channels last format. + // So if channels aren't last (ie. if they aren't dense), + // then reorder into a channels last format + std::string ref_implementation_guess = "simple:any"; + if (src_md()->format_desc.blocking.strides[ndims() - 1] != 1) { + CHECK(memory_desc_init_by_tag( + src_md_, get_channels_last_format(src_md_.ndims))); + ref_implementation_guess = "ref:any"; + } + if (dst_md_ != src_md_) + // Make sure dst and src share a format + CHECK(memory_desc_init_by_md_and_dt( + dst_md_, src_md_, src_md()->data_type)); + if (!set_default_stat_md_format(src_md_)) + return status::unimplemented; + + const memory_desc_wrapper src_d(src_md_); + const memory_desc_wrapper dst_d(dst_md_); + + ACL_CHECK_SUPPORT(src_d.has_zero_dim() || dst_d.has_zero_dim(), + "data tensor(s) must not have a zero dimension"); + + // data type + ACL_CHECK_SUPPORT(src_d.data_type() != data_type::f32, + "ACL Lnorm only supports F32"); + ACL_CHECK_SUPPORT(dst_d.data_type() != src_d.data_type(), + "src and dst must share data types"); + + // Problem shape + int C = norm_axis(); // Channel dim size + int X = src_d.nelems() / C; // Non-channel dims size + + ACL_CHECK_SUPPORT(!use_acl_heuristic(X, C, dnnl_get_max_threads(), + is_training(), ref_implementation_guess), + "ACL is unoptimal in this case"); + + anp.data_info + = arm_compute::TensorInfo(arm_compute::TensorShape(C, X), 1, + arm_compute::DataType::F32); + + ACL_CHECK_VALID( + arm_compute::NEMeanStdDevNormalizationLayer::validate( + &anp.data_info, &anp.data_info, + desc()->layer_norm_epsilon)); + + return status::success; + } + + format_tag_t get_channels_last_format(size_t ndim) { + assert(ndim > 1 && ndim < 6); + switch (ndim) { + case 2: return format_tag::nc; + case 3: return format_tag::tnc; + case 4: return format_tag::ldnc; + case 5: return format_tag::abcde; + default: return format_tag::undef; + } + } + + bool use_acl_heuristic(int X, int C, int threads, bool ref_has_stats, + std::string ref_implementation_guess) { + // Above a certain C, acl is always better, and below a certain C, + // acl is always worse. for C in between these two, whether acl is + // better can be approximated with the workload (X*C) per thread. + // The values here were derived empirically and all depend on + // threads, whether ref can use provided stats, and which reference + // implementation acl is competing with. + + int acl_competitive_C = C; + int acl_better_C = C; + int acl_better_XC_per_thread = X * C; + + if (ref_implementation_guess == "simple:any") { + acl_competitive_C = 64; + if (ref_has_stats) { + acl_better_C = 4096; + acl_better_XC_per_thread = threads == 1 ? 4096 : 8192; + } else { + acl_better_C = threads <= 2 ? 1024 : 4096; + acl_better_XC_per_thread = threads == 1 ? 1024 : 4096; + } + } else if (ref_implementation_guess == "ref:any") { + acl_competitive_C = 0; + if (ref_has_stats) { + if (threads == 1) { + acl_better_C = 64; + } else if (threads == 2) { + acl_better_C = 256; + } else { + acl_better_C = 1024; + } + + if (threads == 1) { + acl_better_XC_per_thread = 256; + } else if (threads <= 16) { + acl_better_XC_per_thread = 512; + } else { + acl_better_XC_per_thread = 1024; + } + } else { + if (threads == 1) { + acl_better_C = 64; + } else if (threads <= 32) { + acl_better_C = 256; + } else { + acl_better_C = 1024; + } + + if (threads == 1) { + acl_better_XC_per_thread = 128; + } else if (threads <= 32) { + acl_better_XC_per_thread = 256; + } else { + acl_better_XC_per_thread = 512; + } + } + } + + return C > acl_competitive_C + && (C > acl_better_C + || X * C > acl_better_XC_per_thread * threads); + } + + acl_msdnorm_conf_t anp; + + }; // pd_t + + acl_layer_normalization_fwd_t(const pd_t *apd) : primitive_t(apd) {} + + status_t create_resource( + engine_t *engine, resource_mapper_t &mapper) const override { + if (mapper.has_resource(this)) return status::success; + + auto r = utils::make_unique(); + if (!r) return status::out_of_memory; + + // Configure the resource based on information from primitive descriptor + CHECK(r->configure(pd()->anp, pd())); + mapper.add(this, std::move(r)); + + return status::success; + } + + status_t execute(const exec_ctx_t &ctx) const override { + return execute_forward(ctx); + } + +private: + // To guard the const execute_forward, the mutex must be 'mutable' + mutable std::mutex mtx; + status_t execute_forward(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } +}; // acl_layer_normalization_fwd_t + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif // CPU_AARCH64_ACL_LAYER_NORMALIZATION_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_pooling.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_pooling.hpp new file mode 100644 index 0000000000000000000000000000000000000000..639b515882f81c9ec4298f653eac1187f7ec81c9 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_pooling.hpp @@ -0,0 +1,225 @@ +/******************************************************************************* +* Copyright 2022 Arm Ltd. and affiliates +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_ACL_POOLING_HPP +#define CPU_AARCH64_ACL_POOLING_HPP + +#include "cpu/aarch64/acl_utils.hpp" +#include "cpu/cpu_pooling_pd.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +struct acl_pooling_obj_t { + arm_compute::NEPoolingLayer pool; + arm_compute::Tensor src_tensor; + arm_compute::Tensor dst_tensor; +}; + +struct acl_pooling_conf_t { + arm_compute::PoolingLayerInfo pool_info; + arm_compute::TensorInfo src_info; + arm_compute::TensorInfo dst_info; +}; + +struct acl_pooling_resource_t : public resource_t { + acl_pooling_resource_t() + : acl_pooling_obj_(utils::make_unique()) {} + + status_t configure(const acl_pooling_conf_t &app) { + if (!acl_pooling_obj_) return status::out_of_memory; + + // Init Compute Library tensors based on info from descriptor + acl_pooling_obj_->src_tensor.allocator()->init(app.src_info); + acl_pooling_obj_->dst_tensor.allocator()->init(app.dst_info); + + acl_pooling_obj_->pool.configure(&acl_pooling_obj_->src_tensor, + &acl_pooling_obj_->dst_tensor, app.pool_info); + + return status::success; + } + + acl_pooling_obj_t &get_acl_obj() const { return *acl_pooling_obj_; } + + DNNL_DISALLOW_COPY_AND_ASSIGN(acl_pooling_resource_t); + +private: + std::unique_ptr acl_pooling_obj_; +}; // acl_pooling_resource_t + +struct acl_pooling_fwd_t : public primitive_t { + struct pd_t : public cpu_pooling_fwd_pd_t { + using cpu_pooling_fwd_pd_t::cpu_pooling_fwd_pd_t; + pd_t(const pooling_desc_t *adesc, const primitive_attr_t *attr, + const pooling_fwd_pd_t *hint_fwd_pd) + : cpu_pooling_fwd_pd_t(adesc, attr, hint_fwd_pd), app() {} + + DECLARE_COMMON_PD_T("acl", acl_pooling_fwd_t); + + status_t init(engine_t *engine) { + bool ok = set_default_params() == status::success + && is_fwd() // ACL supports forward propagation only + && utils::everyone_is( + src_md()->data_type, dst_md()->data_type) + && utils::one_of( + src_md()->data_type, data_type::f32, data_type::f16) + && attr()->has_default_values() + && attr_.set_default_formats(dst_md(0)) == status::success + && !is_dilated() && !has_zero_dim_memory(); + if (!ok) return status::unimplemented; + + const pooling_desc_t *pod = desc(); + + // Choose the pooling type + const alg_kind_t alg = pod->alg_kind; + const bool is_max_pool = (alg == alg_kind::pooling_max); + app.pool_info.pool_type = is_max_pool + ? arm_compute::PoolingType::MAX + : arm_compute::PoolingType::AVG; + + // Max forward training requires a worksace tensor. + // For this workspace tensor, oneDNN uses pool window coordinates, + // Whereas ACL uses absolute image coordinates. + // Due to this mismatch, reject max forward training cases + ACL_CHECK_SUPPORT( + (is_max_pool + && pod->prop_kind == prop_kind::forward_training), + "ACL does not support training for max pooling in oneDNN"); + + // When padding is larger than the kernel, infinite values are + // produced. + // ACL and oneDNN use different values to represent infinity + // which is difficult to account for, so return unimplemented. + // See https://github.com/oneapi-src/oneDNN/issues/1205 + ACL_CHECK_SUPPORT(KH() <= padT() || KH() <= padB() || KW() <= padL() + || KW() <= padR(), + "ACL does not support pooling cases where padding >= kernel" + " in oneDNN"); + + auto src_tag = memory_desc_matches_one_of_tag( + *src_md(), format_tag::nhwc, format_tag::nchw); + auto dst_tag = memory_desc_matches_one_of_tag( + *dst_md(), format_tag::nhwc, format_tag::nchw); + + ACL_CHECK_SUPPORT( + utils::one_of(format_tag::undef, src_tag, dst_tag), + "src or dst is not format nhwc or nchw"); + ACL_CHECK_SUPPORT(src_tag != dst_tag, + "src and dst have different memory formats"); + + const memory_desc_wrapper src_d(src_md()); + const memory_desc_wrapper dst_d(dst_md()); + const int ndims = src_d.ndims(); + ACL_CHECK_SUPPORT(ndims != 4, "Tensor is not 4d"); + + // Pooling window + app.pool_info.pool_size = arm_compute::Size2D(KW(), KH()); + // Choose the data layout + bool is_nspc = utils::one_of(src_tag, format_tag::nhwc); + const auto acl_layout = is_nspc ? arm_compute::DataLayout::NHWC + : arm_compute::DataLayout::NCHW; + app.pool_info.data_layout = acl_layout; + const auto acl_data_t + = acl_utils::get_acl_data_t(src_d.data_type()); + + ACL_CHECK_SUPPORT( + !use_acl_heuristic(MB() * IC() * OH() * OW() * KH() * KW(), + dnnl_get_max_threads(), is_max_pool, is_nspc), + "ACL is unoptimal in this case"); + + app.pool_info.exclude_padding + = (alg == alg_kind::pooling_avg_exclude_padding); + + app.pool_info.pad_stride_info = arm_compute::PadStrideInfo(KSW(), + KSH(), padL(), padR(), padT(), padB(), + arm_compute::DimensionRoundingType::FLOOR); + + app.src_info = arm_compute::TensorInfo(is_nspc + ? arm_compute::TensorShape(IC(), IW(), IH(), MB()) + : arm_compute::TensorShape(IW(), IH(), IC(), MB()), + 1, acl_data_t, acl_layout); + app.dst_info = arm_compute::TensorInfo(is_nspc + ? arm_compute::TensorShape(OC(), OW(), OH(), MB()) + : arm_compute::TensorShape(OW(), OH(), OC(), MB()), + 1, acl_data_t, acl_layout); + + ACL_CHECK_VALID(arm_compute::NEPoolingLayer::validate( + &app.src_info, &app.dst_info, app.pool_info)); + + return status::success; + } + + bool use_acl_heuristic( + int problem_size, int thread_count, bool is_max, bool is_nhwc) { + // For nhwc, ACL is faster above a certain problem size 'cutoff' + // This cutoff scales linearly with thread count (except 1 thread) + // So return true iff problem size is larger than this cutoff. + // Note: This rule is approximate, Not all problems follow this rule + if (is_nhwc) { + if (is_max) { + if (thread_count == 1) + return problem_size > 512; + else + return problem_size > 4096 * thread_count; + } else { // pooling_alg == avg_p || pooling_alg == avg_np + if (thread_count == 1) + return problem_size > 1024; + else + return problem_size > 8192 * thread_count; + } + } else { // memory_format == nchw + return false; + } + } + + acl_pooling_conf_t app; + }; + + acl_pooling_fwd_t(const pd_t *apd) : primitive_t(apd) {} + + status_t execute(const exec_ctx_t &ctx) const override { + return execute_forward(ctx); + } + + status_t create_resource( + engine_t *engine, resource_mapper_t &mapper) const override { + if (mapper.has_resource(this)) return status::success; + + auto r = utils::make_unique(); + if (!r) return status::out_of_memory; + + // Configure the resource based on information from primitive descriptor + auto st = r->configure(pd()->app); + if (st == status::success) { mapper.add(this, std::move(r)); } + + return st; + } + +private: + // execute_forward has to be const thus mutability of mtx + mutable std::mutex mtx; + status_t execute_forward(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } +}; // acl_pooling_fwd_t + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif // CPU_AARCH64_ACL_POOLING_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_post_ops.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_post_ops.hpp new file mode 100644 index 0000000000000000000000000000000000000000..7b59ad71d35667ce5dfa2fd80600382135104a7e --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_post_ops.hpp @@ -0,0 +1,194 @@ +/******************************************************************************* +* Copyright 2022-2023 Arm Ltd. and affiliates +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_ACL_POST_OPS_HPP +#define CPU_AARCH64_ACL_POST_OPS_HPP + +#include "cpu/aarch64/acl_binary.hpp" +#include "cpu/aarch64/acl_eltwise.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +struct acl_post_ops_t { + + acl_post_ops_t() = default; + + // init the acl_post_ops_t. Note that this function modifies the passed in + // post ops by setting the preferred memory formats + status_t init(engine_t *engine, post_ops_t &post_ops, + const memory_desc_t &dst_md) { + + CHECK(post_ops.set_default_formats(&dst_md)); + dst_data_type = dst_md.data_type; + + // Reset properties derived from post_ops + sum_index = -1; + post_op_primitives = {}; + + for (int i = 0; i < post_ops.len(); i++) { + auto &po = post_ops.entry_[i]; + + if (po.is_sum()) { + ACL_CHECK_SUPPORT(po.sum.scale != 1.0f, + "sum post op scale must be 1 (no scale)"); + + ACL_CHECK_SUPPORT(po.sum.zero_point != 0, + "sum post op zero point must be 0 (no shift)"); + + // >= 0 means we had one already + ACL_CHECK_SUPPORT(sum_index >= 0, + "there must not be more than 1 sum post op"); + + sum_index = i; + + // Sum is an add primitive where dst = temp_dst + dst + binary_desc_t po_desc; + po_desc.primitive_kind = primitive_kind::binary; + po_desc.alg_kind = alg_kind::binary_add; + po_desc.src_desc[0] = dst_md; + po_desc.src_desc[1] = dst_md; + po_desc.dst_desc = dst_md; + auto empty_attr = dnnl_primitive_attr(); + typename acl_binary_t::pd_t acl_binary_pd( + &po_desc, &empty_attr, nullptr); + CHECK(acl_binary_pd.init(engine)); + + auto acl_binary + = std::make_shared(&acl_binary_pd); + CHECK(acl_binary->init(engine)); + post_op_primitives.push_back(acl_binary); + + } else if (po.is_binary()) { + binary_desc_t po_desc; + po_desc.primitive_kind = primitive_kind::binary; + po_desc.alg_kind = po.binary.alg; + po_desc.src_desc[0] = dst_md; + po_desc.src_desc[1] = po.binary.src1_desc; + po_desc.dst_desc = dst_md; + auto empty_attr = dnnl_primitive_attr(); + typename acl_binary_t::pd_t acl_binary_pd( + &po_desc, &empty_attr, nullptr); + CHECK(acl_binary_pd.init(engine)); + + auto acl_binary + = std::make_shared(&acl_binary_pd); + CHECK(acl_binary->init(engine)); + post_op_primitives.push_back(acl_binary); + + } else if (po.is_eltwise()) { + ACL_CHECK_SUPPORT(po.eltwise.scale != 1.0f, + "eltwise post op scale must be 1 (no scale)"); + + eltwise_desc_t eltwise_desc; + eltwise_desc.primitive_kind = primitive_kind::eltwise; + eltwise_desc.alg_kind = po.eltwise.alg; + eltwise_desc.alpha = po.eltwise.alpha; + eltwise_desc.beta = po.eltwise.beta; + memory_desc_t temp_dst = dst_md; + // pass eltwise a desc with f32 datatype to perform the operation in fp32 rather than fp16 + // since oneDNN requires all post-ops to run in fp32. + // we don't need to do that to the other post-ops as executing them in fp16 yields the same result. + if (dst_data_type == data_type::f16) { + temp_dst.data_type = data_type::f32; + } + eltwise_desc.src_desc = temp_dst; + eltwise_desc.dst_desc = temp_dst; + eltwise_desc.prop_kind = prop_kind_t::dnnl_forward; + auto empty_attr = dnnl_primitive_attr(); + typename acl_eltwise_fwd_t::pd_t acl_eltwise_pd( + &eltwise_desc, &empty_attr, nullptr); + CHECK(acl_eltwise_pd.init(engine)); + + auto acl_eltwise + = std::make_shared(&acl_eltwise_pd); + CHECK(acl_eltwise->init(engine)); + post_op_primitives.push_back(acl_eltwise); + + } else { + // Unsupported catchall + return status::unimplemented; + } + } + + return status::success; + } + + // init acl_post_ops_t, ignoring the first post op if it is an eltwise so + // that it can be fused, placing it in act_info_to_fuse. Note that this + // function modifies the passed in post ops by setting the preferred memory + // formats + status_t init(engine_t *engine, post_ops_t &base_post_ops, + const memory_desc_t &dst_md, + arm_compute::ActivationLayerInfo &act_info_to_fuse) { + + CHECK(base_post_ops.set_default_formats(&dst_md)); + dst_data_type = dst_md.data_type; + // If the first entry is eltwise, we fuse it, except when the datatype + // is fp16 because in this case we want to execute the eltwise in fp32. + if (base_post_ops.len() >= 1 && base_post_ops.entry_[0].is_eltwise() + && dst_data_type != data_type::f16) { + + const auto &first_po = base_post_ops.entry_[0].eltwise; + ACL_CHECK_SUPPORT(first_po.scale != 1.0f, + "eltwise post op scale must be 1 (no scale)"); + CHECK(acl_utils::convert_to_acl_act(first_po, act_info_to_fuse)); + + // Copy all but the first, because it has been fused + post_ops_t post_ops; + for (int idx = 1; idx < base_post_ops.len(); ++idx) { + // Construct empty entry then copy, so that we can check for failure + post_ops.entry_.emplace_back(); + post_ops.entry_.back().copy_from(base_post_ops.entry_[idx]); + } + return init(engine, post_ops, dst_md); + + } else { + // Nothing to fuse, just copy all post ops + return init(engine, base_post_ops, dst_md); + } + } + + bool has_sum() const { return sum_index >= 0; } + + status_t create_resource( + engine_t *engine, resource_mapper_t &mapper) const { + for (const auto &post_op : post_op_primitives) { + CHECK(post_op->create_resource(engine, mapper)); + } + return status::success; + } + + status_t execute(const exec_ctx_t &ctx, void *src) const; + +private: + // Index of the sum post op if there is one, < 0 means no sum + int sum_index = -1; + data_type_t dst_data_type; + // Vector of primitives used to execute the post ops. They are constructed + // in init to be either acl_binary_t (for sum, add, sub, div, mul, min and + // max) or acl_eltwise_fwd_t (for relu, elu, tanh, square, abs etc) + std::vector> post_op_primitives; +}; + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_prelu.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_prelu.hpp new file mode 100644 index 0000000000000000000000000000000000000000..8517d1bb3ee79e2f67aaa616a898aa34d769d258 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_prelu.hpp @@ -0,0 +1,159 @@ +/******************************************************************************* +* Copyright 2022 Arm Ltd. and affiliates +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ +#ifndef CPU_AARCH64_ACL_PRELU_HPP +#define CPU_AARCH64_ACL_PRELU_HPP + +#include "cpu/aarch64/acl_utils.hpp" +#include "cpu/cpu_prelu_pd.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +struct acl_prelu_obj_t { + arm_compute::NEPReluLayer prelu; + arm_compute::Tensor src_tensor; + arm_compute::Tensor weights_tensor; + arm_compute::Tensor dst_tensor; +}; + +struct acl_prelu_conf_t { + arm_compute::TensorInfo src_info; + arm_compute::TensorInfo weights_info; + arm_compute::TensorInfo dst_info; +}; + +struct acl_prelu_resource_t : public resource_t { + acl_prelu_resource_t() : acl_obj_(utils::make_unique()) {} + + status_t configure(const acl_prelu_conf_t &app) { + if (!acl_obj_) return status::out_of_memory; + + // Init Compute Library tensors based on info from descriptor + acl_obj_->src_tensor.allocator()->init(app.src_info); + acl_obj_->weights_tensor.allocator()->init(app.weights_info); + acl_obj_->dst_tensor.allocator()->init(app.dst_info); + + // clang-format off + acl_obj_->prelu.configure( + &acl_obj_->src_tensor, + &acl_obj_->weights_tensor, + &acl_obj_->dst_tensor); + // clang-format on + + return status::success; + } + + acl_prelu_obj_t &get_acl_obj() const { return *acl_obj_; } + + DNNL_DISALLOW_COPY_AND_ASSIGN(acl_prelu_resource_t); + +private: + std::unique_ptr acl_obj_; +}; // acl_prelu_resource_t + +struct acl_prelu_fwd_t : public primitive_t { + struct pd_t : public cpu_prelu_fwd_pd_t { + using cpu_prelu_fwd_pd_t::cpu_prelu_fwd_pd_t; + + DECLARE_COMMON_PD_T("acl", acl_prelu_fwd_t); + + status_t init(engine_t *engine) { + using namespace format_tag; + using namespace acl_utils; + + // Forward only + if (!prelu_pd_t::is_fwd()) return status::unimplemented; + + // Only support f32 and f16 for now + data_type_t ddt = dst_md(0)->data_type; + if (!utils::one_of(ddt, data_type::f32, data_type::f16)) + return status::unimplemented; + + if (!set_default_formats()) return status::unimplemented; + + if (!attr()->has_default_values()) return status::unimplemented; + + // ACL pointwise arithmetic operators assume that the innermost + // dimensions are dense for src, weights and dst. Reordering the + // logical dimensions by stride does this (if reordered_dims >= 1 ) + // and also makes memory accesses contiguous in ACL (without any + // data reordering). + memory_desc_t src_d_permed, weights_d_permed, dst_d_permed; + int reordered_dims = reorder_dimensions_by_stride( + {&src_d_permed, &weights_d_permed, &dst_d_permed}, + {src_md(0), weights_md(0), dst_md(0)}); + if (reordered_dims < 1) return status::unimplemented; + + // Create ACL tensor infos with permuted descs + CHECK(tensor_info(app_.src_info, src_d_permed)); + CHECK(tensor_info(app_.weights_info, weights_d_permed)); + CHECK(tensor_info(app_.dst_info, dst_d_permed)); + + // This forces ACL not to parallelise with small workloads, this is + // a temporary fix and should be removed in future versions (TODO) + memory_desc_wrapper dst_d(dst_md(0)); + if (dst_d.nelems() < 40000) { + size_t acl_y_axis_i = 1; + CHECK(insert_singleton_dimension(app_.src_info, acl_y_axis_i)); + CHECK(insert_singleton_dimension( + app_.weights_info, acl_y_axis_i)); + CHECK(insert_singleton_dimension(app_.dst_info, acl_y_axis_i)); + } + + ACL_CHECK_VALID(arm_compute::NEPReluLayer::validate( + &app_.src_info, &app_.weights_info, &app_.dst_info)); + + return status::success; + } + + acl_prelu_conf_t app_; + }; // pd_t + + acl_prelu_fwd_t(const pd_t *apd) : primitive_t(apd) {} + + status_t create_resource( + engine_t *engine, resource_mapper_t &mapper) const override { + if (mapper.has_resource(this)) return status::success; + + auto r = utils::make_unique(); + if (!r) return status::out_of_memory; + + // Configure the resource based on information from primitive descriptor + CHECK(r->configure(pd()->app_)); + + mapper.add(this, std::move(r)); + return status::success; + } + + status_t execute(const exec_ctx_t &ctx) const override { + return execute_forward(ctx); + } + +private: + // To guard the const execute_forward, the mutex must be 'mutable' + mutable std::mutex mtx; + status_t execute_forward(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } +}; // acl_prelu_fwd_t + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif // CPU_AARCH64_ACL_PRELU_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_softmax.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_softmax.hpp new file mode 100644 index 0000000000000000000000000000000000000000..2a4db7c9d4eef4e10e4f0310de2d1d5d1cda28be --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_softmax.hpp @@ -0,0 +1,239 @@ +/******************************************************************************* +* Copyright 2021-2022 Arm Ltd. and affiliates +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_ACL_SOFTMAX_HPP +#define CPU_AARCH64_ACL_SOFTMAX_HPP + +#include "cpu/cpu_softmax_pd.hpp" + +#include "cpu/aarch64/acl_utils.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +struct acl_softmax_obj_t { + std::unique_ptr softmax; + arm_compute::Tensor src_tensor; + arm_compute::Tensor dst_tensor; +}; + +struct acl_softmax_conf_t { + arm_compute::TensorInfo src_info; + arm_compute::TensorInfo dst_info; + float beta; + int32_t axis; + bool is_logsoftmax; +}; + +struct acl_softmax_resource_t : public resource_t { + acl_softmax_resource_t() + : acl_obj_(utils::make_unique()) {} + + status_t configure(const acl_softmax_conf_t &asp) { + if (!acl_obj_) return status::out_of_memory; + + // Init Compute Library tensors based on info from descriptor + acl_obj_->src_tensor.allocator()->init(asp.src_info); + acl_obj_->dst_tensor.allocator()->init(asp.dst_info); + + if (asp.is_logsoftmax) { + auto logsoftmax + = std::make_unique(); + // clang-format off + logsoftmax->configure( + &acl_obj_->src_tensor, + &acl_obj_->dst_tensor, + asp.beta, + asp.axis); + // clang-format on + acl_obj_->softmax = std::move(logsoftmax); + } else { + auto softmax = std::make_unique(); + // clang-format off + softmax->configure( + &acl_obj_->src_tensor, + &acl_obj_->dst_tensor, + asp.beta, + asp.axis); + // clang-format on + acl_obj_->softmax = std::move(softmax); + } + + return status::success; + } + + acl_softmax_obj_t &get_acl_obj() const { return *acl_obj_; } + + DNNL_DISALLOW_COPY_AND_ASSIGN(acl_softmax_resource_t); + +private: + std::unique_ptr acl_obj_; +}; // acl_softmax_resource_t + +struct acl_softmax_fwd_t : public primitive_t { + struct pd_t : public cpu_softmax_fwd_pd_t { + using cpu_softmax_fwd_pd_t::cpu_softmax_fwd_pd_t; + + DECLARE_COMMON_PD_T("acl", acl_softmax_fwd_t); + + status_t init(engine_t *engine) { + + bool ok = is_fwd() + // ACL only supports matching src/dst data types + && src_md()->data_type == dst_md()->data_type + && utils::one_of( + src_md()->data_type, data_type::f32, data_type::f16) + && attr()->has_default_values() + && set_default_formats() == status::success; + if (!ok) return status::unimplemented; + + // Get memory desc to find sizes and dims + const memory_desc_wrapper src_d(src_md()); + const data_type_t data_type = src_d.data_type(); + + // ACL only supports plain tensors, can be permuted but not blocked + if (!src_d.is_plain()) return status::unimplemented; + + // Guards against a 0-sized dimension + if (src_d.has_zero_dim()) return status::unimplemented; + + // No scaling + asp_.beta = 1; + + asp_.is_logsoftmax = is_logsoftmax(); + + // The strides give us the in memory inner size + dim_t inner_size_ = src_d.blocking_desc().strides[axis()]; + + dim_t axis_size_ = axis_size(); + + // The outer size is any left-over dimensions not inner or on the axis + dim_t outer_size_ = src_d.nelems() / (inner_size_ * axis_size_); + + // In this context, NHWC tells ACL that the logical and physical + // dimensions are the same + arm_compute::DataLayout acl_layout = arm_compute::DataLayout::NHWC; + + const arm_compute::DataType acl_data_t + = acl_utils::get_acl_data_t(data_type); + + const int threads = dnnl_get_max_threads(); + if (inner_size_ == 1) { + // A rough empirical heuristic created by fitting a polynomial + // of the tensor sizes and thread count to the run time of the + // ref and ACL softmax. This variable is greater than zero when + // ref is faster, and less than zero when ACL is faster. We can + // interpret the constant term as the constant overhead + // associated with calling the external library and the negative + // coefficient on total_size as ACL being faster at processing + // each element + double acl_ref_performance_diff = 1 + 0.005 * outer_size_ + - 0.0027 * axis_size_ + * std::ceil(double(outer_size_) / threads); + if (threads > 1 || outer_size_ > 1) { + // Using threads within ACL adds another constant overhead + acl_ref_performance_diff += 17; + } + if (acl_ref_performance_diff > 0) return status::unimplemented; + + // If the inner size is 1, we can get rid of the dimension. + // This stops ACL doing a unnecessary permute + arm_compute::TensorShape acl_tensor_shape + = arm_compute::TensorShape(axis_size_, outer_size_); + asp_.axis = 0; + + asp_.src_info = arm_compute::TensorInfo( + acl_tensor_shape, 1, acl_data_t, acl_layout); + asp_.dst_info = arm_compute::TensorInfo( + acl_tensor_shape, 1, acl_data_t, acl_layout); + } else { + // A rough empirical heuristic, see comment above + // The only difference here is that ACL does a reorder, and so + // is considerably better + double acl_ref_performance_diff = 1 + 0.005 * outer_size_ + - 0.01 * inner_size_ * axis_size_ + * std::ceil(double(outer_size_) / threads); + if (threads > 1 || outer_size_ > 1) { + // Using threads within ACL adds another constant overhead + acl_ref_performance_diff += 17; + } + + if (acl_ref_performance_diff > 0) return status::unimplemented; + + // Irrespective of the input dimensions, we construct a tensor + // with dimensions such that softmax can be applied over the + // middle axis (1), with the correct stride and vector length. + arm_compute::TensorShape acl_tensor_shape + = arm_compute::TensorShape( + inner_size_, axis_size_, outer_size_); + asp_.axis = 1; + + asp_.src_info = arm_compute::TensorInfo( + acl_tensor_shape, 1, acl_data_t, acl_layout); + asp_.dst_info = arm_compute::TensorInfo( + acl_tensor_shape, 1, acl_data_t, acl_layout); + } + + // Validate manually to check for return status + if (asp_.is_logsoftmax) { + ACL_CHECK_VALID(arm_compute::NELogSoftmaxLayer::validate( + &asp_.src_info, &asp_.dst_info, asp_.beta, asp_.axis)); + } else { + ACL_CHECK_VALID(arm_compute::NESoftmaxLayer::validate( + &asp_.src_info, &asp_.dst_info, asp_.beta, asp_.axis)); + } + + return status::success; + } + + acl_softmax_conf_t asp_; + }; // pd_t + + acl_softmax_fwd_t(const pd_t *apd) : primitive_t(apd) {} + + status_t create_resource( + engine_t *engine, resource_mapper_t &mapper) const override { + if (mapper.has_resource(this)) return status::success; + + auto r = utils::make_unique(); + if (!r) return status::out_of_memory; + + // Configure the resource based on information from primitive descriptor + auto st = r->configure(pd()->asp_); + if (st == status::success) { mapper.add(this, std::move(r)); } + + return st; + } + + status_t execute(const exec_ctx_t &ctx) const override { + return execute_forward(ctx); + } + +private: + // To guard the const execute_forward, the mutex must be 'mutable' + mutable std::mutex mtx; + status_t execute_forward(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } +}; // acl_softmax_fwd_t + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_thread.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_thread.hpp new file mode 100644 index 0000000000000000000000000000000000000000..f073376e63a318b7e0316ef2b84d71ee2a6ec17b --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_thread.hpp @@ -0,0 +1,57 @@ +/******************************************************************************* +* Copyright 2022-2023 Arm Ltd. and affiliates +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_ACL_THREAD_HPP +#define CPU_AARCH64_ACL_THREAD_HPP + +#include "common/dnnl_thread.hpp" +#include "common/verbose.hpp" + +#include "arm_compute/runtime/Scheduler.h" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +namespace acl_thread_utils { + +#if DNNL_CPU_THREADING_RUNTIME == DNNL_RUNTIME_OMP +// Number of threads in Compute Library is set by OMP_NUM_THREADS +// dnnl_get_max_threads() == OMP_NUM_THREADS +void acl_thread_bind(); +// Swap BenchmarkScheduler for default ACL scheduler builds (i.e. CPPScheduler, OMPScheduler) +// for DNNL_VERBOSE=profile,profile_externals +void acl_set_benchmark_scheduler_default(); +#endif + +#if DNNL_CPU_THREADING_RUNTIME == DNNL_RUNTIME_THREADPOOL +// Retrieve threadpool size during primitive execution and set ThreadpoolScheduler num_threads +void acl_set_tp_scheduler(); +void acl_set_threadpool_num_threads(); +// Swap BenchmarkScheduler for custom scheduler builds (i.e. ThreadPoolScheduler) for DNNL_VERBOSE=profile,profile_externals +void acl_set_tp_benchmark_scheduler(); +#endif +// Set threading for ACL +void set_acl_threading(); +} // namespace acl_thread_utils + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif // CPU_AARCH64_ACL_THREAD_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_threadpool_scheduler.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_threadpool_scheduler.hpp new file mode 100644 index 0000000000000000000000000000000000000000..e9ba21c80328cdd8e68f4270e2e9a316129ae437 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_threadpool_scheduler.hpp @@ -0,0 +1,68 @@ +/******************************************************************************* +* Copyright 2022 Arm Ltd. and affiliates +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_ACL_THREADPOOL_SCHEDULER_HPP +#define CPU_AARCH64_ACL_THREADPOOL_SCHEDULER_HPP + +#include "oneapi/dnnl/dnnl_config.h" + +#if DNNL_CPU_THREADING_RUNTIME == DNNL_RUNTIME_THREADPOOL + +#include "arm_compute/runtime/IScheduler.h" +#include "support/Mutex.h" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +class ThreadpoolScheduler final : public arm_compute::IScheduler { +public: + ThreadpoolScheduler(); + ~ThreadpoolScheduler(); + + /// Sets the number of threads the scheduler will use to run the kernels. + void set_num_threads(unsigned int num_threads) override; + /// Returns the number of threads that the ThreadpoolScheduler has in its pool. + unsigned int num_threads() const override; + + /// Multithread the execution of the passed kernel if possible. + void schedule(arm_compute::ICPPKernel *kernel, + const arm_compute::IScheduler::Hints &hints) override; + + /// Multithread the execution of the passed kernel if possible. + void schedule_op(arm_compute::ICPPKernel *kernel, + const arm_compute::IScheduler::Hints &hints, + const arm_compute::Window &window, + arm_compute::ITensorPack &tensors) override; + +protected: + /// Execute workloads in parallel using num_threads + void run_workloads(std::vector &workloads) override; + +private: + uint _num_threads {}; + arm_compute::Mutex _run_workloads_mutex {}; +}; + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif // CPU_AARCH64_ACL_THREADPOOL_SCHEDULER_HPP + +#endif // DNNL_CPU_THREADING_RUNTIME == DNNL_RUNTIME_THREADPOOL diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_utils.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_utils.hpp new file mode 100644 index 0000000000000000000000000000000000000000..150778c7e7a1bab13f92985d5e0bec826fd95089 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_utils.hpp @@ -0,0 +1,132 @@ +/******************************************************************************* +* Copyright 2021-2023 Arm Ltd. and affiliates +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_ACL_UTILS_HPP +#define CPU_AARCH64_ACL_UTILS_HPP + +#include + +#include "oneapi/dnnl/dnnl_types.h" + +#include "common/dnnl_thread.hpp" +#include "common/memory_tracking.hpp" +#include "common/primitive.hpp" +#include "common/resource.hpp" +#include "common/utils.hpp" + +#include "arm_compute/runtime/NEON/NEFunctions.h" +#include "arm_compute/runtime/Scheduler.h" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +namespace acl_utils { + +arm_compute::DataType get_acl_data_t( + const dnnl_data_type_t dt, const bool is_quantized = false); + +// Convert alg_kind_t, alpha and beta into an ACL ActivationLayerInfo. Will +// return unimplemented and a disabled ActivationLayerInfo if the conversion +// fails +status_t convert_to_acl_act(alg_kind_t eltwise_alg, float alpha, float beta, + arm_compute::ActivationLayerInfo &act_info); + +// Convert an eltwise_desc_t into an ACL ActivationLayerInfo. Will return +// unimplemented and a disabled ActivationLayerInfo if the conversion fails +status_t convert_to_acl_act( + const eltwise_desc_t &ed, arm_compute::ActivationLayerInfo &act_info); + +// Convert an eltwise post op into an ACL ActivationLayerInfo. Will return +// unimplemented and a disabled ActivationLayerInfo if the conversion fails +status_t convert_to_acl_act(const post_ops_t::entry_t::eltwise_t &elt, + arm_compute::ActivationLayerInfo &act_info); + +// Convert a memory desc to an arm_compute::TensorInfo. Note that memory desc +// must be blocking format, plain, dense and have no zero dimensions. +status_t tensor_info(arm_compute::TensorInfo &info, const memory_desc_t &md); +status_t tensor_info( + arm_compute::TensorInfo &info, const memory_desc_wrapper &md); + +// Insert a dimension of size 1 at the index dim_i of TensorInfo +status_t insert_singleton_dimension(arm_compute::TensorInfo &ti, size_t dim_i); + +// Reorder the logical dimensions of the memory descriptors (mds) by stride so +// that accessing the tensor elements in the natural order is dense. Note, this +// does not reorder the data, it just reorders the logical indices. The +// permutation is common to all mds, so the function returns when it cannot find +// a dimension with a common smallest stride. Returns the number of dimensions +// that we managed to reorder to be dense. +int reorder_dimensions_by_stride(std::vector permuted_mds, + std::vector mds); + +// Reorder a memory_desc_t and set the strides on a arm_compute::TensorInfo to +// match an arm_compute::WeightFormat. You are required to specify how various +// logical dimensions in oneDNN correspond to logical dimensions in arm_compute. +// info TensorInfo where the strides will be changed to match the reordering +// md memory descriptor where the stride and padded dimensions will be +// changed or reordering +// wf Describes the memory format/layout of the weights +// I_dim The logical dimension of md corresponding to the input channel of +// a convolution or the K dimension in a matmul +// O_dim The logical dimension of md corresponding to the output channel of a +//   convolution or the N dimension in a matmul +// spatial_dims The logical dimensions of md corresponding to the spatial +// dimensions of the weights (H, W, D for example). These will be +// the next densest after the inner blocks and the input channel. +// batch_dims The logical dimensions of md related to the batch in a batched +// matmul, ordered from innermost to outermost. ACL calls these +// the multi_stride_b. These will become the outermost (least dense) +// dimensions and will be collapsed. +void reorder_to_weight_format(arm_compute::TensorInfo &info, memory_desc_t &md, + arm_compute::WeightFormat wf, dim_t I_dim, dim_t O_dim, + std::vector spatial_dims, std::vector batch_dims = {}); + +// Logs a custom 'info' line describing an unsupported case +#define LOG_ACL_UNSUPPORTED(msg) \ + do { \ + if (verbose_has_create_dispatch()) \ + printf("onednn_verbose,cpu,acl,unsupported: %s\n", (msg)); \ + } while (0) + +// Returns unimplemented if error code x is NOT OK +#define ACL_CHECK_VALID(x) \ + do { \ + arm_compute::Status s = x; \ + if (s.error_code() != arm_compute::ErrorCode::OK) { \ + LOG_ACL_UNSUPPORTED(s.error_description().c_str()); \ + return dnnl::impl::status::unimplemented; \ + } \ + } while (0) + +// Returns unimplemented on condition x == true +#define ACL_CHECK_SUPPORT(x, msg) \ + do { \ + if (x) { \ + LOG_ACL_UNSUPPORTED(msg); \ + return dnnl::impl::status::unimplemented; \ + } \ + } while (0) + +} // namespace acl_utils + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif // CPU_AARCH64_ACL_UTILS_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/cpu_barrier.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/cpu_barrier.hpp new file mode 100644 index 0000000000000000000000000000000000000000..f90c963cbd7dab1018d2c483cdf878c5f300c38d --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/cpu_barrier.hpp @@ -0,0 +1,84 @@ +/******************************************************************************* +* Copyright 2020-2021 Intel Corporation +* Copyright 2020-2021 FUJITSU LIMITED +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_CPU_BARRIER_HPP +#define CPU_AARCH64_CPU_BARRIER_HPP + +#include + +#include "common/utils.hpp" +#include "cpu/aarch64/jit_generator.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +namespace simple_barrier { + +#define CTX_ALIGNMENT 4096 + +STRUCT_ALIGN( + CTX_ALIGNMENT, struct ctx_t { + enum { CACHE_LINE_SIZE = 256 }; + volatile size_t ctr; + char pad1[CACHE_LINE_SIZE - 1 * sizeof(size_t)]; + volatile size_t sense; + char pad2[CACHE_LINE_SIZE - 1 * sizeof(size_t)]; + }); + +/* TODO: remove ctx_64_t once batch normalization switches to barrier-less + * implementation. + * Different alignments of context structure affect performance differently for + * convolution and batch normalization. Convolution performance becomes more + * stable with page alignment compared to cache line size alignment. + * Batch normalization (that creates C / simd_w barriers) degrades with page + * alignment due to significant overhead of ctx_init in case of mb=1. */ +STRUCT_ALIGN( + 256, struct ctx_64_t { + enum { CACHE_LINE_SIZE = 256 }; + volatile size_t ctr; + char pad1[CACHE_LINE_SIZE - 1 * sizeof(size_t)]; + volatile size_t sense; + char pad2[CACHE_LINE_SIZE - 1 * sizeof(size_t)]; + }); + +template +inline void ctx_init(ctx_t *ctx) { + *ctx = utils::zero(); +} +void barrier(ctx_t *ctx, int nthr); + +/** injects actual barrier implementation into another jitted code + * @params: + * code -- jit_generator object where the barrier is to be injected + * reg_ctx -- read-only register with pointer to the barrier context + * reg_nnthr -- read-only register with the # of synchronizing threads + */ +void generate(jit_generator &code, Xbyak_aarch64::XReg reg_ctx, + Xbyak_aarch64::XReg reg_nthr, bool usedAsFunc = false); + +} // namespace simple_barrier + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/cpu_isa_traits.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/cpu_isa_traits.hpp new file mode 100644 index 0000000000000000000000000000000000000000..4a43b24c579c08fb16cc16b76d20e85baef4f760 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/cpu_isa_traits.hpp @@ -0,0 +1,237 @@ +/******************************************************************************* +* Copyright 2018-2023 Intel Corporation +* Copyright 2020-2023 FUJITSU LIMITED +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_CPU_ISA_TRAITS_HPP +#define CPU_AARCH64_CPU_ISA_TRAITS_HPP + +#include + +#include "dnnl_types.h" + +#include "common/dnnl_thread.hpp" +#include "common/utils.hpp" + +/* in order to make selinux happy memory that would be marked with X-bit should + * be obtained with mmap */ +#if !defined(_WIN32) +#define XBYAK_USE_MMAP_ALLOCATOR +#endif + +#include "cpu/aarch64/xbyak_aarch64/xbyak_aarch64/xbyak_aarch64.h" +#include "cpu/aarch64/xbyak_aarch64/xbyak_aarch64/xbyak_aarch64_util.h" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +/* The following enum is temporal implementation. + It should be made in dnnl_types.h, + but an RFC is requird to modify dnnl_types.h. + The following values are used with + static_cast, the same values + defined in dnnl_cpu_isa_t are temporaly used. */ +/// CPU instruction set flags +enum { + /// AARCH64 Advanced SIMD & floating-point + dnnl_cpu_isa_asimd = 0x1, + /// AARCH64 SVE 128 bits + dnnl_cpu_isa_sve_128 = 0x3, + /// AARCH64 SVE 256 bits + dnnl_cpu_isa_sve_256 = 0x7, + /// AARCH64 SVE 384 bits + dnnl_cpu_isa_sve_384 = 0xf, + /// AARCH64 SVE 512 bits + dnnl_cpu_isa_sve_512 = 0x27, +}; + +enum cpu_isa_bit_t : unsigned { + asimd_bit = 1u << 0, + sve_128_bit = 1u << 1, + sve_256_bit = 1u << 2, + sve_384_bit = 1u << 3, + sve_512_bit = 1u << 4, +}; + +enum cpu_isa_t : unsigned { + isa_undef = 0u, + asimd = asimd_bit, + sve_128 = sve_128_bit | asimd, + sve_256 = sve_256_bit | sve_128, + sve_384 = sve_384_bit | sve_256, + sve_512 = sve_512_bit | sve_384, + isa_all = ~0u, +}; + +enum class cpu_isa_cmp_t { + // List of infix comparison relations between two cpu_isa_t + // where we take isa_1 and isa_2 to be two cpu_isa_t instances. + + // isa_1 SUBSET isa_2 if all feature flags supported by isa_1 + // are supported by isa_2 as well (equality allowed) + SUBSET, + + // isa_1 SUPERSET isa_2 if all feature flags supported by isa_2 + // are supported by isa_1 as well (equality allowed) + SUPERSET, + + // Few more options that (depending upon need) can be enabled in future + + // 1. PROPER_SUBSET: isa_1 SUBSET isa_2 and isa_1 != isa_2 + // 2. PROPER_SUPERSET: isa_1 SUPERSET isa_2 and isa_1 != isa_2 +}; + +const char *get_isa_info(); + +cpu_isa_t get_max_cpu_isa(); +cpu_isa_t DNNL_API get_max_cpu_isa_mask(bool soft = false); +status_t set_max_cpu_isa(dnnl_cpu_isa_t isa); +dnnl_cpu_isa_t get_effective_cpu_isa(); + +static inline bool compare_isa( + cpu_isa_t isa_1, cpu_isa_cmp_t cmp, cpu_isa_t isa_2) { + // By default, comparison between ISA ignores ISA specific hints + unsigned mask_1 = static_cast(isa_1); + unsigned mask_2 = static_cast(isa_2); + unsigned mask_common = mask_1 & mask_2; + + switch (cmp) { + case cpu_isa_cmp_t::SUBSET: return mask_1 == mask_common; + case cpu_isa_cmp_t::SUPERSET: return mask_2 == mask_common; + default: assert(!"unsupported comparison of isa"); return false; + } +} + +static inline bool is_subset(cpu_isa_t isa_1, cpu_isa_t isa_2) { + return compare_isa(isa_1, cpu_isa_cmp_t::SUBSET, isa_2); +} + +static inline bool is_superset(cpu_isa_t isa_1, cpu_isa_t isa_2) { + return compare_isa(isa_1, cpu_isa_cmp_t::SUPERSET, isa_2); +} + +template +struct cpu_isa_traits {}; /* ::vlen -> 32 (for avx2) */ + +template <> +struct cpu_isa_traits { + static constexpr dnnl_cpu_isa_t user_option_val = dnnl_cpu_isa_default; + static constexpr const char *user_option_env = "default"; +}; + +template <> +struct cpu_isa_traits { + typedef Xbyak_aarch64::VReg TReg; + typedef Xbyak_aarch64::VReg16B TRegB; + typedef Xbyak_aarch64::VReg8H TRegH; + typedef Xbyak_aarch64::VReg4S TRegS; + typedef Xbyak_aarch64::VReg2D TRegD; + static constexpr int vlen_shift = 4; + static constexpr int vlen = 16; + static constexpr int n_vregs = 32; + static constexpr dnnl_cpu_isa_t user_option_val + = static_cast(dnnl_cpu_isa_asimd); + static constexpr const char *user_option_env = "advanced_simd"; +}; + +#define CPU_ISA_SVE(bits, shift) \ + template <> \ + struct cpu_isa_traits { \ + typedef Xbyak_aarch64::ZReg TReg; \ + typedef Xbyak_aarch64::ZRegB TRegB; \ + typedef Xbyak_aarch64::ZRegH TRegH; \ + typedef Xbyak_aarch64::ZRegS TRegS; \ + typedef Xbyak_aarch64::ZRegD TRegD; \ + static constexpr int vlen_shift = shift; \ + static constexpr int vlen = bits / 8; \ + static constexpr int n_vregs = 32; \ + static constexpr dnnl_cpu_isa_t user_option_val \ + = static_cast(dnnl_cpu_isa_sve_##bits); \ + static constexpr const char *user_option_env = "sve_ ## bits"; \ + }; + +CPU_ISA_SVE(128, 4) +CPU_ISA_SVE(256, 5) +CPU_ISA_SVE(512, 6) +#undef CPU_ISA_SVE + +inline const Xbyak_aarch64::util::Cpu &cpu() { + const static Xbyak_aarch64::util::Cpu cpu_; + return cpu_; +} + +namespace { + +static inline bool mayiuse(const cpu_isa_t cpu_isa, bool soft = false) { + using namespace Xbyak_aarch64::util; + + unsigned cpu_isa_mask = aarch64::get_max_cpu_isa_mask(soft); + if ((cpu_isa_mask & cpu_isa) != cpu_isa) return false; + + switch (cpu_isa) { + case asimd: return cpu().has(XBYAK_AARCH64_HWCAP_ADVSIMD); + case sve_128: + return cpu().has(XBYAK_AARCH64_HWCAP_SVE) + && cpu().getSveLen() >= SVE_128; + case sve_256: + return cpu().has(XBYAK_AARCH64_HWCAP_SVE) + && cpu().getSveLen() >= SVE_256; + case sve_384: + return cpu().has(XBYAK_AARCH64_HWCAP_SVE) + && cpu().getSveLen() >= SVE_384; + case sve_512: + return cpu().has(XBYAK_AARCH64_HWCAP_SVE) + && cpu().getSveLen() >= SVE_512; + case isa_undef: return true; + case isa_all: return false; + } + return false; +} + +static inline uint64_t get_sve_length() { + return cpu().getSveLen(); +} + +static inline bool mayiuse_atomic() { + using namespace Xbyak_aarch64::util; + return cpu().isAtomicSupported(); +} + +inline bool isa_has_bf16(cpu_isa_t isa) { + return false; +} + +} // namespace + +/* whatever is required to generate string literals... */ +#include "common/z_magic.hpp" +/* clang-format off */ +#define JIT_IMPL_NAME_HELPER(prefix, isa, suffix_if_any) \ + ((isa) == isa_undef ? prefix STRINGIFY(any) : \ + ((isa) == asimd ? prefix STRINGIFY(asimd) : \ + ((isa) == sve_128 ? prefix STRINGIFY(sve_128) : \ + ((isa) == sve_256 ? prefix STRINGIFY(sve_256) : \ + ((isa) == sve_512 ? prefix STRINGIFY(sve_512) : \ + prefix suffix_if_any))))) +/* clang-format on */ + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/cpu_reducer.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/cpu_reducer.hpp new file mode 100644 index 0000000000000000000000000000000000000000..765a6a9e4eb9274afaa2cc01e4754cbdbaa6ab72 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/cpu_reducer.hpp @@ -0,0 +1,357 @@ +/******************************************************************************* +* Copyright 2020-2021 Intel Corporation +* Copyright 2020-2021 FUJITSU LIMITED +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_CPU_REDUCER_HPP +#define CPU_AARCH64_CPU_REDUCER_HPP + +#include + +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/memory_tracking.hpp" +#include "common/nstl.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" +#include "dnnl_types.h" + +#include "cpu/aarch64/cpu_barrier.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +/** class to perform balancing over 3D array + * + * Conceptually the reduction happens according to the picture below: + * + * <--job_size-> + * +-----------+ +-----------+ +-----------+ ^ + * | | | | | | | + * | | | | | | | + * | 1 | | 2 | . . . | njobs | | reduction_size + * | | | | | | | + * | | | | | | | + * +-----------+ +-----------+ +-----------+ v + * + * | | | | | | | | | + * v v v v v v v v v + * ===================================================== vertical reduction + * + * +-----------+ +-----------+ . . . +-----------+ result + * + * In a simple case the result must be contiguous in memory. + * @class cpu_reducer_t is an implementation. + * + * Threads are divided into groups. The groups are independent of each other. + * Each group may work on several jobs (the distribution is not uniform, since + * njobs might be not a multiple of groups). Threads within a group work on + * different parts of the reduction dimension. Thread 0 in each group is called + * master (@sa reduce_balancer_t::master()). + * + * If threading driver does not allow sync between sub-group of threads (e.g. + * TBB) the # of thread per group is enforced to be 1. + */ +struct reduce_balancer_t { + reduce_balancer_t() { init(1, 1, 1, 1, 0); } /* trivial balance */ + reduce_balancer_t(int nthr, int job_size, int njobs, int reduction_size, + size_t max_buffer_size, bool lock_free = false) { + init(nthr, job_size, njobs, reduction_size, max_buffer_size, lock_free); + } + + reduce_balancer_t &init(int nthr, int job_size, int njobs, + int reduction_size, size_t max_buffer_size, + bool lock_free = false) { + allow_nthr_in_group_ = lock_free ? true : dnnl_thr_syncable(); + nthr_ = nthr; + job_size_ = job_size; + njobs_ = njobs; + reduction_size_ = reduction_size; + max_buffer_size_ = max_buffer_size; + balance(); + return *this; + } + + bool allow_nthr_in_group_; + int nthr_; + int job_size_, njobs_, reduction_size_; + + int ngroups_; /** number of independent work (thread) groups */ + int nthr_per_group_; /** number of threads within a single work group */ + int njobs_per_group_ub_; /** the max # of jobs within a work group */ + + bool master(int ithr) const { return id_in_group(ithr) == 0; } + bool idle(int ithr) const { return ithr >= nthr_per_group_ * ngroups_; } + + int group_id(int ithr) const { return ithr / nthr_per_group_; } + int id_in_group(int ithr) const { return ithr % nthr_per_group_; } + + int grp_njobs(int grp) const { + if (grp >= ngroups_) return 0; + return njobs_ / ngroups_ + (grp < njobs_ % ngroups_); + } + int grp_job_off(int grp) const { + if (grp >= ngroups_) return njobs_; + return njobs_ / ngroups_ * grp + nstl::min(grp, njobs_ % ngroups_); + } + + int ithr_njobs(int ithr) const { return grp_njobs(group_id(ithr)); } + int ithr_job_off(int ithr) const { return grp_job_off(group_id(ithr)); } + +private: + size_t max_buffer_size_; + void balance(); +}; + +/** forward declaration of reduce driver */ +template +struct reducer_2d_driver_t; + +/** class to perform a reduction over 3D array + * + * Balancing is based on @class reduce_balancer_t. + * Restrictions: the result of the reduction must be contiguous in memory. * + * The reduction happens according to the picture below (once more): + * + * <--job_size-> + * +-----------+ +-----------+ +-----------+ ^ + * | | | | | | | + * | | | | | | | + * | 1 | | 2 | . . . | njobs | | reduction_size + * | | | | | | | + * | | | | | | | + * +-----------+ +-----------+ +-----------+ v + * + * | | | | | | | | | + * v v v v v v v v v + * ===================================================== vertical reduction + * + * +-----------+ +-----------+ . . . +-----------+ (contiguous) result + * + * An example how work might be shared is shown below. + * + * In this example group 0 owns 2 (independent) jobs -- 2 big squares. + * The number of threads per group is also 2 (thread 0 of group 0 and thread 1 + * of group 0). Master threads (i.e. threads with id 0 in corresponding group) + * from each group put the partial result directly into destination memory, + * while all the other threads with-in the group use workspace (on the picture + * the only thread 1). Once intermediate results obtained each group reduces + * corresponding part (own jobs) to the destination memory. + * + * <------- group 0 -------> + * + * +-----------+ +-----------+ ^ + * | | | | | thread 0 of reduces to the dest-memory + * | | | | | group 0 +-----------+ +-----------+ + * |- - - - - -| |- - - - - -| X + * | | | | | thread 1 of reduces to workspace[tid=1]: + * | | | | | group 0 +-----------+ +-----------+ + * +-----------+ +-----------+ v + * | | | | | | + * v v v v v v + * ((barrier)) ============================= + * + * dest-memory: +-----------+ +-----------+ + */ +template +struct cpu_reducer_t { + typedef typename prec_traits::type data_t; + + struct conf_t { + conf_t() = default; + conf_t &init(const reduce_balancer_t &balancer) { + balancer_ = balancer; + return *this; + } + + void init_scratchpad(memory_tracking::registrar_t &scratchpad) const; + + reduce_balancer_t balancer_; + }; + + status_t create_kernel(); + + cpu_reducer_t(const conf_t &conf); + ~cpu_reducer_t(); + + /** initializes reducer. + * Must be called from a single thread prior to actual usage */ + void init(const memory_tracking::grantor_t &scratchpad) const { + if (balancer().nthr_per_group_ == 1 || !dnnl_thr_syncable()) return; + + auto bctx = scratchpad.template get( + memory_tracking::names::key_reducer_space_bctx); + for (int i = 0; i < balancer().ngroups_; ++i) + simple_barrier::ctx_init(&bctx[i]); + } + + /** for given thread returns the pointer where to put partial results. + * Reduction destination @p dst must be provided as well (master threads + * from each group will use it for partial result to reduce memory + * pressure). + * + * @note: job offset is already applied by get_local_ptr(), which means all + * threads should start writing from the very beginning of returned + * address. + */ + data_t *get_local_ptr(int ithr, data_t *dst, + const memory_tracking::grantor_t &scratchpad) const; + + /** performs the reduction with built-in synchronization. */ + void reduce(int ithr, data_t *dst, + const memory_tracking::grantor_t &scratchpad) const { + bool redundant_reduction + = balancer().nthr_per_group_ == 1 || balancer().idle(ithr); + if (redundant_reduction) return; + + auto bctx = scratchpad.template get( + memory_tracking::names::key_reducer_space_bctx); + simple_barrier::barrier( + &bctx[balancer().group_id(ithr)], balancer().nthr_per_group_); + + reduce_nolock(ithr, dst, scratchpad); + } + + void reduce_nolock(int ithr, data_t *dst, + const memory_tracking::grantor_t &scratchpad) const; + + const reduce_balancer_t &balancer() const { return conf_.balancer_; } + +private: + static size_t space_per_thread(const reduce_balancer_t &balancer) { + return balancer.njobs_per_group_ub_ * balancer.job_size_; + } + + /* The scratchpad is organized as follows: + * + * data_t space[nthr_][njobs_per_group_ub_][jobs_size_]; + * simple_barrier::ctx_t barriers[groups_]; */ + + const conf_t conf_; + reducer_2d_driver_t *drv_; + + DNNL_DISALLOW_COPY_AND_ASSIGN(cpu_reducer_t); +}; + +template +struct cpu_reducer_2d_t { + typedef typename prec_traits::type data_t; + + struct conf_t { + conf_t() = default; + conf_t &init(const reduce_balancer_t &balancer, int job_size_x, + int job_size_y, int x_block, int dst_x, int dst_y) { + balancer_ = balancer; + job_size_x_ = job_size_x; + job_size_y_ = job_size_y; + x_block_ = x_block; + dst_x_ = dst_x; + dst_y_ = dst_y; + return *this; + } + + void init_scratchpad(memory_tracking::registrar_t &scratchpad) const; + + reduce_balancer_t balancer_; + int job_size_x_, job_size_y_, x_block_, dst_x_, dst_y_; + }; + + status_t create_kernel(); + + cpu_reducer_2d_t(const conf_t &conf); + ~cpu_reducer_2d_t(); + + /** initializes reducer. + * Must be called from a single thread prior to actual usage */ + void init(const memory_tracking::grantor_t &scratchpad) const { + if (balancer().nthr_per_group_ == 1 || !dnnl_thr_syncable()) return; + + auto bctx = scratchpad.template get( + memory_tracking::names::key_reducer_space_bctx); + for (int i = 0; i < balancer().ngroups_; ++i) + simple_barrier::ctx_init(&bctx[i]); + } + + /** for given thread returns the pointer where to put partial results */ + data_t *get_local_ptr( + int ithr, const memory_tracking::grantor_t &scratchpad) const; + + /** performs the reduction with built-in synchronization. */ + void reduce(int ithr, data_t *dst, + const memory_tracking::grantor_t &scratchpad) const { + bool redundant_reduction + = balancer().nthr_per_group_ == 1 || balancer().idle(ithr); + if (redundant_reduction) return; + + auto bctx = scratchpad.template get( + memory_tracking::names::key_reducer_space_bctx); + simple_barrier::barrier( + &bctx[balancer().group_id(ithr)], balancer().nthr_per_group_); + + reduce_nolock(ithr, dst, scratchpad); + } + + void reduce_nolock(int ithr, data_t *dst, + const memory_tracking::grantor_t &scratchpad) const; + + const reduce_balancer_t &balancer() const { return conf_.balancer_; } + +private: + static size_t space_per_thread(const reduce_balancer_t &balancer) { + return balancer.njobs_per_group_ub_ * balancer.job_size_; + } + + /* The scratchpad is organized as follows: + * + * data_t space[nthr_][njobs_per_group_ub_][jobs_size_]; + * simple_barrier::ctx_t barriers[groups_]; */ + + const conf_t conf_; + reducer_2d_driver_t *drv_; + + int choose_x_blocking(int nx, int ny, int nthr_per_grp) const; + void reduce_block(const data_t *space_base, data_t *dst, int job, + int start_y, int start_x, int ny_start, int nx_start, int ny_step, + int nx_step) const; + + DNNL_DISALLOW_COPY_AND_ASSIGN(cpu_reducer_2d_t); +}; + +/** simple 1d accumulator: y[:] += x[:] */ +template +struct cpu_accumulator_1d_t { + typedef typename prec_traits::type data_t; + + cpu_accumulator_1d_t(); + ~cpu_accumulator_1d_t(); + void accumulate(data_t *dst, const data_t *src, size_t size); + + status_t create_kernel(); + + reducer_2d_driver_t *drv_; + + DNNL_DISALLOW_COPY_AND_ASSIGN(cpu_accumulator_1d_t); +}; + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/injectors/injector_utils.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/injectors/injector_utils.hpp new file mode 100644 index 0000000000000000000000000000000000000000..3685042f6a5db3cbf2594bd448a6ca6d1b9ea091 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/injectors/injector_utils.hpp @@ -0,0 +1,113 @@ +/******************************************************************************* +* Copyright 2020-2022 Intel Corporation +* Copyright 2021-2022 FUJITSU LIMITED +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ +#ifndef CPU_AARCH64_JIT_INJECTOR_UTILS_HPP +#define CPU_AARCH64_JIT_INJECTOR_UTILS_HPP + +#include +#include +#include +#include + +#include "cpu/aarch64/jit_generator.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { +namespace injector_utils { + +using vmm_index_set_t = typename std::set; +using vmm_index_set_iterator_t = typename std::set::iterator; +template +struct vmm_size_t; + +template <> +struct vmm_size_t { + static constexpr std::size_t bytes = 64u; +}; + +/* +template <> +struct vmm_size_t { + static constexpr std::size_t bytes = 32u; +}; + +template <> +struct vmm_size_t { + static constexpr std::size_t bytes = 16u; + };*/ + +enum class layout_t { ncsp, c_blocked, nspc, cspn, unsupported }; + +inline layout_t get_layout_type(const memory_desc_wrapper &dst_d) { + const auto strides = dst_d.blocking_desc().strides; + if (!dst_d.is_plain()) return layout_t::c_blocked; + if (strides[0] >= strides[1] + && IMPLICATION(dst_d.ndims() >= 3, strides[1] >= strides[2])) + return layout_t::ncsp; + if (strides[1] == 1) return layout_t::nspc; + if (strides[0] == 1) return layout_t::cspn; + return layout_t::unsupported; +} + +/* + * Scope guard for general purpose register and vector registers preservation. + * Pushes registers to stack during construction and pops during destruction. + */ +template +class register_preserve_guard_t { + +public: + register_preserve_guard_t(jit_generator *host, + std::initializer_list reg64_to_preserve, + std::initializer_list vmm_to_preserve = {}); + register_preserve_guard_t(register_preserve_guard_t &&other) = default; + register_preserve_guard_t &operator=(register_preserve_guard_t &&other) + = default; + DNNL_DISALLOW_COPY_AND_ASSIGN(register_preserve_guard_t); + ~register_preserve_guard_t(); + size_t calc_vmm_to_preserve_size_bytes( + const std::initializer_list &vmm_to_preserve) + const; + size_t stack_space_occupied() const; + +private: + jit_generator *host_; + std::stack reg64_stack_; + std::stack vmm_stack_; + const uint64_t cpu_sveLen_ = get_sve_length(); + size_t vmm_to_preserve_size_bytes_; +}; + +template +class conditional_register_preserve_guard_t + : public register_preserve_guard_t { +public: + conditional_register_preserve_guard_t(bool condition_to_be_met, + jit_generator *host, + std::initializer_list reg64_to_preserve, + std::initializer_list vmm_to_preserve = {}); + DNNL_DISALLOW_COPY_AND_ASSIGN(conditional_register_preserve_guard_t); +}; + +} // namespace injector_utils +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/injectors/jit_uni_binary_injector.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/injectors/jit_uni_binary_injector.hpp new file mode 100644 index 0000000000000000000000000000000000000000..81bea5d7134960a6bfa2998115aef1d4482cdd28 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/injectors/jit_uni_binary_injector.hpp @@ -0,0 +1,631 @@ +/******************************************************************************* +* Copyright 2020-2023 Intel Corporation +* Copyright 2022-2023 FUJITSU LIMITED +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_JIT_UNI_BINARY_INJECTOR_HPP +#define CPU_AARCH64_JIT_UNI_BINARY_INJECTOR_HPP + +#include +#include +#include +#include +#include +#include +#include + +#include "common/broadcast_strategy.hpp" +#include "common/c_types_map.hpp" +#include "common/primitive_attr.hpp" +#include "common/primitive_exec_types.hpp" +#include "cpu/aarch64/cpu_isa_traits.hpp" +#include "cpu/aarch64/injectors/injector_utils.hpp" +#include "cpu/aarch64/jit_generator.hpp" +#include "cpu/binary_injector_utils.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { +namespace binary_injector { +using dnnl::impl::cpu::binary_injector_utils::prepare_binary_args; + +bool binary_args_matches_tag(format_tag_t tag, const post_ops_t &post_ops); + +bool binary_args_broadcast_supported(const post_ops_t &post_ops, + const memory_desc_wrapper &dst_d, + const bcast_set_t &supported_strategy_set); + +bool binary_args_tail_supported(const post_ops_t &post_ops, + const memory_desc_wrapper &dst_d, int vlen, + const bcast_set_t &supported_strategy_set); + +bool any_binary_postop_rhs_per_oc_broadcast( + const post_ops_t &post_ops, const memory_desc_wrapper &dst_d); +bool any_binary_postop_rhs_per_oc_broadcast(const post_ops_t &post_ops, + const memory_desc_wrapper &dst_d, + const bcast_set_t &supported_strategy_set); + +bool all_binary_postop_rhs_per_oc_broadcast(const post_ops_t &post_ops, + const memory_desc_wrapper &dst_d, + const std::function &predicate); +bool all_binary_postop_rhs_per_oc_broadcast(const post_ops_t &post_ops, + const memory_desc_wrapper &dst_d, + const bcast_set_t &supported_strategy_set, + const std::function &predicate); + +/* + * Represents params related to all binary post-ops right-hand side arguments + * (arg1) that don't change during jit_uni_binary_injector_t object lifetime + * and between compute_vector_range calls. + * + * @param rhs_dt_helper_vmm_idx - index of vmm helper used when loading data for + * calculations. Treated as hint from user. If inside compute_vector_range hint + * turns out to be invalid, it will be overwriten by register preserving logic inside + * binary injector. + * @param rhs_addr_reg - gpr register, used as the currently processed address of + * rhs tensor slice. Data of rhs(arg1) for the binary operation is loaded from address + * stored inside rhs_addr_reg. + * @param rhs_helper_reg - gpr register used as helper for calculations during data + * loading phase. + * @param rhs_addr_cache_reg - gpr register used for caching part of calculated + * offset, this register is always preserved. + * @param preserve_gpr_helpers - determines whether gpr registers specified above + * should be preserved (pushed to stack and poped back afterwords) between + * compute_vector_range calls. + * @param preserve_vmm_helper - determines whether vmm helper register specified + * above should be preserved between compute_vector_range calls. + * @param abi_param_offset - offset to rhs tensor from first binary post-op operation + * specified by user from runtime structure passed to kernel as abi param 1. + * @param dst_orig_offset - offset 0 to destination tensor + * @param dst_d - descriptor of destination tensor (result after applying all post-ops + * operations). + * @param tail_opmask - register with loaded by user mask, used in avx512 for load with + * tail handling. + * @param tail_size - size of processed tail in elements. + * @param use_exact_tail_scalar_bcast - in case of scalar broadcast user can disable + * loading data with tail, usually bcast through entire vector is faster (usually 1 instruction) + * vs. broadcasting limited by tail size (potentially several instructions). In case + * when user during storing ignores values from vmm above tail size, setting this option to + * false can result in better performance. + * @param reg_tail_size - register with loaded size of tail, used in sse41/avx/avx2 + * for load with tail in runtime. + */ +struct rhs_arg_static_params_t { + rhs_arg_static_params_t(std::size_t rhs_dt_helper_vmm_idx, + const Xbyak_aarch64::XReg &rhs_addr_reg, + const Xbyak_aarch64::XReg &rhs_helper_reg, + const Xbyak_aarch64::XReg &rhs_addr_cache_reg, + bool preserve_gpr_helpers, bool preserve_vmm_helper, + std::size_t abi_param_offset, const memory_desc_wrapper &dst_d, + std::size_t tail_size = 0u, + bool use_exact_tail_scalar_bcast = false); + rhs_arg_static_params_t(std::size_t rhs_dt_helper_vmm_idx, + const Xbyak_aarch64::XReg &rhs_addr_reg, + const Xbyak_aarch64::XReg &rhs_helper_reg, + const Xbyak_aarch64::XReg &rhs_addr_cache_reg, + bool preserve_gpr_helpers, bool preserve_vmm_helper, + std::size_t abi_param_offset, std::size_t dst_orig_offset, + const memory_desc_wrapper &dst_d, std::size_t tail_size = 0u, + bool use_exact_tail_scalar_bcast = false); + rhs_arg_static_params_t(std::size_t rhs_dt_helper_vmm_idx, + const Xbyak_aarch64::XReg &rhs_addr_reg, + const Xbyak_aarch64::XReg &rhs_helper_reg, + const Xbyak_aarch64::XReg &rhs_addr_cache_reg, + bool preserve_gpr_helpers, bool preserve_vmm_helper, + std::size_t abi_param_offset, const memory_desc_wrapper &dst_d, + std::size_t tail_size, const Xbyak_aarch64::PReg &tail_opmask, + bool use_exact_tail_scalar_bcast); + rhs_arg_static_params_t(std::size_t rhs_dt_helper_vmm_idx, + const Xbyak_aarch64::XReg &rhs_addr_reg, + const Xbyak_aarch64::XReg &rhs_helper_reg, + const Xbyak_aarch64::XReg &rhs_addr_cache_reg, + bool preserve_gpr_helpers, bool preserve_vmm_helper, + std::size_t abi_param_offset, std::size_t dst_orig_offset, + const memory_desc_wrapper &dst_d, std::size_t tail_size, + const Xbyak_aarch64::PReg &tail_opmask, + bool use_exact_tail_scalar_bcast); + rhs_arg_static_params_t(std::size_t rhs_dt_helper_vmm_idx, + const Xbyak_aarch64::XReg &rhs_addr_reg, + const Xbyak_aarch64::XReg &rhs_helper_reg, + const Xbyak_aarch64::XReg &rhs_addr_cache_reg, + bool preserve_gpr_helpers, bool preserve_vmm_helper, + std::size_t abi_param_offset, const memory_desc_wrapper &dst_d, + std::size_t tail_size, const Xbyak_aarch64::PReg &tail_opmask, + const Xbyak_aarch64::XReg ®_tail_size, + bool use_exact_tail_scalar_bcast); + rhs_arg_static_params_t(std::size_t rhs_dt_helper_vmm_idx, + const Xbyak_aarch64::XReg &rhs_addr_reg, + const Xbyak_aarch64::XReg &rhs_helper_reg, + const Xbyak_aarch64::XReg &rhs_addr_cache_reg, + bool preserve_gpr_helpers, bool preserve_vmm_helper, + std::size_t abi_param_offset, std::size_t dst_orig_offset, + const memory_desc_wrapper &dst_d, std::size_t tail_size, + const Xbyak_aarch64::PReg &tail_opmask, + const Xbyak_aarch64::XReg ®_tail_size, + bool use_exact_tail_scalar_bcast); + + bool is_opmask_set() const noexcept { return is_opmask_set_; } + bool is_dst_orig_set() const noexcept { return is_dst_orig_set_; } + + mutable std::size_t rhs_dt_helper_vmm_idx; + Xbyak_aarch64::XReg rhs_addr_reg; + Xbyak_aarch64::XReg rhs_helper_reg; + Xbyak_aarch64::XReg rhs_addr_cache_reg; + bool preserve_gpr_helpers; + bool preserve_vmm_helper; + std::size_t abi_param_offset; + std::size_t dst_orig_offset; + memory_desc_wrapper dst_d; + std::size_t tail_size; + Xbyak_aarch64::PReg tail_opmask; + bool use_exact_tail_scalar_bcast; + Xbyak_aarch64::XReg reg_tail_size; + bool is_tail; + +private: + rhs_arg_static_params_t(std::size_t rhs_dt_helper_vmm_idx, + const Xbyak_aarch64::XReg &rhs_addr_reg, + const Xbyak_aarch64::XReg &rhs_helper_reg, + const Xbyak_aarch64::XReg &rhs_addr_cache_reg, + bool preserve_gpr_helpers, bool preserve_vmm_helper, + std::size_t abi_param_offset, std::size_t dst_orig_offset, + const memory_desc_wrapper &dst_d, std::size_t tail_size, + const Xbyak_aarch64::PReg &tail_opmask, + bool use_exact_tail_scalar_bcast, + const Xbyak_aarch64::XReg ®_tail_size, bool is_opmask_set, + bool is_dst_orig_set); + + bool is_opmask_set_; + bool is_dst_orig_set_; +}; + +/* + * Represents params required by jit_uni_binary_injector_t that don't change + * during it's entire lifetime. + * + * @param param1 - register storing abi param1. At the moment of calling + * compute_vector_range method can be different than the default one defined + * inside jit_generator. + * @param bcast_set_t supported_strategy_set - set allowing disabling particular + * bcast strategies + * @param rhs_arg_static_params - params related to all binary post-ops right-hand side + * arguments that don't change during entire lifetime of jit_uni_binary_injector_t + * object. + */ +struct static_params_t { + static_params_t(const Xbyak_aarch64::XReg ¶m1, + const bcast_set_t &supported_strategy_set, + const rhs_arg_static_params_t &rhs_arg_static_params); + static_params_t(const Xbyak_aarch64::XReg ¶m1, + const rhs_arg_static_params_t &rhs_arg_static_params); + + Xbyak_aarch64::XReg param1; + const bcast_set_t supported_strategy_set; + rhs_arg_static_params_t rhs_arg_static_params; +}; + +/* + * Mode of data load with tail for rhs: + * STATIC - load based on given integer. + * DYNAMIC - load based on opmask or 64-bit register. + * DEFAULT - DYNAMIC for avx512, STATIC for others. + */ + +enum class tail_lode_mode_t { STATIC, DYNAMIC, DEFAULT }; + +struct rhs_address_t { + Xbyak_aarch64::XReg base_; + int64_t offt_ = 0; + bool isBroadcast_ = false; + uint32_t bits_ = 0; + + rhs_address_t(const Xbyak_aarch64::XReg &base, const int64_t offt = 0, + bool isBroadcast = false, const uint32_t bits = 0) + : base_(base), offt_(offt), isBroadcast_(isBroadcast), bits_(bits) {} + + bool operator==(const rhs_address_t &rhs) const { + return getBit() == rhs.getBit() + && getBase().getIdx() == rhs.getBase().getIdx() + && isBroadcast_ == rhs.isBroadcast(); + } + bool operator!=(const rhs_address_t &rhs) const { return !operator==(rhs); } + + Xbyak_aarch64::XReg getBase() const { return base_; } + uint32_t getBit() const { return bits_; } + bool isBroadcast() const { return isBroadcast_; } +}; + +struct rhs_operand_t { + + bool isAddress_ = false; + uint32_t idx_; + rhs_address_t address_; + + bool operator==(const rhs_operand_t &rhs) const { + if (isAddress_) { + if (isAddress_ == rhs.isAddress_ && address_ == rhs.address_) + return true; + else + return false; + } else { + if (isAddress_ == rhs.isAddress_ && idx_ == rhs.idx_) + return true; + else + return false; + } + } + + bool operator!=(const rhs_operand_t &rhs) const { return !operator==(rhs); } + + bool isBroadcast() const { return isAddress_ && address_.isBroadcast(); } +}; + +/* + * Represents params passed to compute_vector_range method of + * jit_uni_binary_injector_t that can be different for each call. + * Contains configurable std::maps where key is vmm index and value is + * offset in elements. The offset value identifies tensor slice in particular + * vmm. This is utilized by broadcasting mechanism. Offset, depending on the + * implementation particular kernels, can be passed as value (usually during + * unrolling), inside operand, under memory address. + * + * @param vmm_idx_to_out_addr - vmm mapped to address of destination tensor with offset, + * used to calculate offset in no_broadcast strategy, but also in other strategies whose + * calculations are based on no_broadcast strategy. + * @param vmm_idx_to_out_reg - vmm mapped to register containing address of destination + * with offset, used to calculate offset in no_broadcast strategy, but also in other + * strategies whose calculations are based on no_broadcast strategy. + * @param vmm_idx_to_out_elem_off_addr - vmm mapped to offset in elements stored under + * memory address intended to use in no_broadcast strategy. + * @param vmm_idx_to_out_elem_off_addr - vmm mapped to offset in elements stored under + * memory address intended to use in no_broadcast strategy. + * @param vmm_idx_to_out_elem_off_val - vmm mapped to offset in elements passed as raw + * value intended to use in no_broadcast strategy + * @param vmm_idx_to_out_off_oprnd - vmm mapped to offset in elements inside operand + * intended to use in no_broadcast strategy + * @param vmm_idx_to_oc_elem_off_addr - vmm mapped to output channel offset in elements + * stored under memory address intended to use in per_oc broadcast strategies. + * @param vmm_idx_to_oc_elem_off_val - vmm mapped to output channel offset in elements + * passed as raw value intended to use in per_oc broadcast strategies. + * @param vmm_idx_to_oc_off_oprnd - vmm mapped to output channel offset in elements inside + * operand intended to use in per_oc broadcast strategies. + * @param vmm_idx_to_sp_elem_off_addr - vmm mapped to proper output spatial offset in + * elements stored under memory address intended to use in per_mb_spatial strategies. + * @param vmm_idx_to_sp_elem_off_val - vmm mapped to proper output spatial offset in + * elements passed as raw value intended to use in per_mb_spatial strategies. + * @param vmm_idx_to_sp_off_oprnd - vmm mapped to proper output spatial offset in + * elements inside operand intended to use in per_mb_spatial strategies. + * @param vmm_idx_to_mb_w_elem_off_addr - vmm mapped to proper output last dim + * per first dim offset in elements stored under memory address intended to use + * in per_mb_w strategies. + * @param vmm_idx_to_mb_w_elem_off_val - vmm mapped to proper output last dim + * per first dim offset in elements passed as raw value intended to use in + * per_mb_w strategies. + * @param vmm_idx_to_mb_w_off_oprnd - vmm mapped to proper output last dim + * per first dim offset in elements inside operand intended to use in per_mb_w + * strategies. + * @param vmm_idx_to_w_elem_off_addr - vmm mapped to proper output last dim + * offset in elements stored under memory address intended to use in per_w strategy. + * @param vmm_idx_to_w_elem_off_val - vmm mapped to proper output last dim + * offset in elements passed as raw value intended to use in per_w strategy. + * @param vmm_idx_to_w_off_oprnd - vmm mapped to proper output last dim offset + * in elements inside operand intended to use in per_w strategy. + * @param vmm_tail_idx - vmm indices that contains data don't fill the whole vector (tail). + * @param is_dynamic_tail_load - determines whether to load with tail in + * runtime (based on the value from reg_tail_size or opmask) or based on given + * integer. + */ + +struct rhs_arg_dynamic_params_t { + std::map vmm_idx_to_out_addr; + std::map vmm_idx_to_out_reg; + + std::map vmm_idx_to_out_elem_off_addr; + std::map vmm_idx_to_out_elem_off_val; + std::map vmm_idx_to_out_off_oprnd; + + std::map vmm_idx_to_oc_elem_off_addr; + std::map vmm_idx_to_oc_elem_off_val; + std::map vmm_idx_to_oc_off_oprnd; + + std::map vmm_idx_to_sp_elem_off_addr; + std::map vmm_idx_to_sp_elem_off_val; + std::map vmm_idx_to_sp_off_oprnd; + + std::map vmm_idx_to_mb_w_elem_off_addr; + std::map vmm_idx_to_mb_w_elem_off_val; + std::map vmm_idx_to_mb_w_off_oprnd; + + std::map vmm_idx_to_w_elem_off_addr; + std::map vmm_idx_to_w_elem_off_val; + std::map vmm_idx_to_w_off_oprnd; + + std::unordered_set vmm_tail_idx_; + tail_lode_mode_t tail_load_mode = tail_lode_mode_t::DEFAULT; +}; + +/* + * Checks if src1 data type is supported by binary injector. + */ +bool is_data_supported(cpu_isa_t isa, data_type_t data_type); + +/* + * Checks if broadcast of src1 is supported by binary injector. + */ +bool is_bcast_supported(const dnnl::impl::memory_desc_t &src1_desc, + const memory_desc_wrapper &dst_d, + const bcast_set_t &supported_strategy_set); + +/* + * Checks if binary injection for given args is supported. + */ +bool is_supported(cpu_isa_t isa, const dnnl::impl::memory_desc_t &src1_desc, + const memory_desc_wrapper &dst_d, + const bcast_set_t &supported_strategy_set); + +/* + * Main mechanism responsible for injecting binary postops supporting various + * isa: sve_512 + * types: f32, s32, u8, s8. + */ +template +class jit_uni_binary_injector_t { + using TReg = typename cpu_isa_traits::TReg; + using TRegS = typename cpu_isa_traits::TRegS; + using Vmm = typename cpu_isa_traits::TReg; + +public: + jit_uni_binary_injector_t( + jit_generator *host, const static_params_t &static_params); + + /* + * Generates code of binary post_op injected to host primitive. Applied to + * ordered set of vector registers' indexes. Function loads appropriate + * slice of rhs tensor for computations based on internally determined + * broadcast strategy and information about stored data in particular vmm + * described inside rhs_arg_params. + */ + void compute_vector_range(const injector_utils::vmm_index_set_t &vmm_idxs, + std::size_t rhs_arg_idx, const dnnl_post_ops::entry_t &post_op, + const rhs_arg_dynamic_params_t &rhs_arg_params) const; + + /* + * Generates code of binary post_op injected to host primitive. Applied to + * range ). If not it returns new vmm idx value that will be + * used as temporary vmm in future computations. + */ + int adjust_temp_vmm_hint( + int user_hint, int start_idx, int end_idx, int max_vmm_idx) const; + /* + * Taking into account rhs_broadcasting_strategy and information from user + * about tensor slice (rhs_arg_params) stored in Vmm(vmm_idx) calculates + * address of rhs tensor slice needed for binary operation and returns + * ptr to it. + */ + rhs_address_t prepare_rhs_arg_addr(std::size_t vmm_idx, + std::size_t rhs_arg_idx, const dnnl_post_ops::entry_t &post_op, + const rhs_arg_dynamic_params_t &rhs_arg_params, + const broadcasting_strategy_t rhs_broadcasting_strategy) const; + /* + * Loads data and applies particular binary operation. + */ + void inject_binary(const dnnl_post_ops::entry_t &post_op, Vmm dst, + const rhs_address_t &rhs_addr, bool with_tail, + const tail_lode_mode_t tail_load_mode) const; + + /* + * Helper functions responsible for preparing rhs tensor slice address. + */ + void append_offset_from_operand( + const std::map &vmm_idx_to_elem_addr_off, + int vmm_idx, const Xbyak_aarch64::XReg &addr_reg, + const Xbyak_aarch64::XReg &tmp_reg, + std::size_t elem_size_bytes) const; + void append_offset_under_mem_addr( + const std::map &vmm_idx_to_elem_addr_off, + int vmm_idx, const Xbyak_aarch64::XReg &addr_reg, + const Xbyak_aarch64::XReg &tmp_reg, + std::size_t elem_size_bytes) const; + void append_value_offset( + const std::map &vmm_idx_to_elem_val_off, int vmm_idx, + const Xbyak_aarch64::XReg &addr_reg, + std::size_t elem_size_bytes) const; + + void append_no_broadcast_offset( + const std::map &vmm_idx_to_out_addr, + const std::map &vmm_idx_to_out_reg, + const std::map &vmm_idx_to_out_elem_off_val, + int vmm_idx, const Xbyak_aarch64::XReg &addr_reg, + const Xbyak_aarch64::XReg &tmp_reg, + std::size_t elem_size_bytes) const; + void calculate_no_broadcast(rhs_address_t addr, std::size_t offset, + const Xbyak_aarch64::XReg &out_reg) const; + + void append_oc_offset( + const std::map &vmm_idx_to_out_addr, + const std::map &vmm_idx_to_out_reg, + const std::map &vmm_idx_to_out_elem_off_val, + int vmm_idx, const Xbyak_aarch64::XReg &addr_reg, + const Xbyak_aarch64::XReg &tmp_reg, + std::size_t elem_size_bytes) const; + void calculate_oc_ncsp(const dim_t *strides, + const Xbyak_aarch64::XReg &tmp_reg, + const bool residue = false) const; + void calculate_oc_blocked( + const dim_t *strides, const Xbyak_aarch64::XReg &tmp_reg) const; + void calculate_oc_nspc( + const dim_t *strides, const Xbyak_aarch64::XReg &tmp_reg) const; + void calculate_oc_cspn( + const dim_t *strides, const Xbyak_aarch64::XReg &tmp_reg) const; + + void append_mb_sp_offset( + const std::map &vmm_idx_to_out_addr, + const std::map &vmm_idx_to_out_reg, + const std::map &vmm_idx_to_out_elem_off_val, + int vmm_idx, const Xbyak_aarch64::XReg &addr_reg, + const Xbyak_aarch64::XReg &tmp_reg, + std::size_t elem_size_bytes) const; + void calculate_mb_sp_ncsp( + const dim_t *strides, const Xbyak_aarch64::XReg &tmp_reg) const; + void calculate_mb_sp_blocked( + const dim_t *strides, const Xbyak_aarch64::XReg &tmp_reg) const; + void calculate_mb_sp_nspc( + const dim_t *strides, const Xbyak_aarch64::XReg &tmp_reg) const; + void calculate_mb_sp_cspn( + const dim_t *strides, const Xbyak_aarch64::XReg &tmp_reg) const; + + void append_mb_w_offset( + const std::map &vmm_idx_to_out_addr, + const std::map &vmm_idx_to_out_reg, + const std::map &vmm_idx_to_out_elem_off_val, + int vmm_idx, const Xbyak_aarch64::XReg &addr_reg, + const Xbyak_aarch64::XReg &tmp_reg, + std::size_t elem_size_bytes) const; + void calculate_mb_w_ncsp( + const dim_t *strides, const Xbyak_aarch64::XReg &tmp_reg) const; + void calculate_mb_w_blocked( + const dim_t *strides, const Xbyak_aarch64::XReg &tmp_reg) const; + void calculate_mb_w_nspc( + const dim_t *strides, const Xbyak_aarch64::XReg &tmp_reg) const; + void calculate_mb_w_cspn( + const dim_t *strides, const Xbyak_aarch64::XReg &tmp_reg) const; + + void append_w_offset( + const std::map &vmm_idx_to_out_addr, + const std::map &vmm_idx_to_out_reg, + const std::map &vmm_idx_to_out_elem_off_val, + int vmm_idx, const Xbyak_aarch64::XReg &addr_reg, + const Xbyak_aarch64::XReg &tmp_reg, + std::size_t elem_size_bytes) const; + void calculate_w_ncsp( + const dim_t *strides, const Xbyak_aarch64::XReg &tmp_reg) const; + void calculate_w_blocked( + const dim_t *strides, const Xbyak_aarch64::XReg &tmp_reg) const; + void calculate_w_nspc( + const dim_t *strides, const Xbyak_aarch64::XReg &tmp_reg) const; + void calculate_w_cspn( + const dim_t *strides, const Xbyak_aarch64::XReg &tmp_reg) const; + + void compute_cmp_mask(const Xbyak_aarch64::PReg &cmp_dst, + const Xbyak_aarch64::PReg &mask, const Xbyak_aarch64::ZReg &cmp_src, + const Xbyak_aarch64::ZReg &cmp_src2, const unsigned int uimm) const; + + template + void fdiv(const Vmm &dst, const Xbyak_aarch64::PReg &mask, const Vmm &lhs, + const T &rhs) const; + template + void fdiv(const Vmm &dst, const Vmm &lhs, const T &rhs) const; + + void execute_cmp_binary(const Vmm &dst, const Xbyak_aarch64::PReg &mask, + const Vmm &lhs, const Vmm &rhs, + const unsigned int cmp_predicate) const; + template + void execute_binary(alg_kind_t binary_alg, const Vmm &dst, + const Xbyak_aarch64::PReg &mask, const Vmm &lhs, + const T &rhs) const; + /* + * Used in scalar broadcast strategy, broadcasting single value of given + * data type over entire vector Vmm register. + */ + void execute_broadcast(const data_type_t &data_type, const Vmm &tmp_reg, + const rhs_address_t &rhs_addr, + const tail_lode_mode_t tail_load_mode, + bool with_tail = false) const; + void load_rhs(const data_type_t &data_type, const Vmm &tmp_reg, + const rhs_address_t &rhs_addr, + const tail_lode_mode_t tail_load_mode, + bool with_tail = false) const; + void execute_broadcast_tail_with_opmask(const data_type_t &data_type, + const Vmm &tmp_reg, const rhs_address_t &rhs_addr) const; + void execute_broadcast_tail_statically(const data_type_t &data_type, + const Vmm &tmp_reg, const rhs_address_t &rhs_addr, + const std::size_t tail_size) const; + void execute_broadcast_tail_with_gpr(const data_type_t &data_type, + const Vmm &tmp_reg, const rhs_address_t &rhs_addr) const; + void load_rhs_tail_dynamically_with_opmask(const data_type_t &data_type, + const Vmm &tmp_vmm, const rhs_address_t &rhs_addr) const; + void load_rhs_tail_dynamically_with_gpr( + const data_type_t &data_type, const Vmm &tmp_vmm) const; + void load_rhs_tail_statically(const data_type_t &data_type, + const Vmm &tmp_vmm, const rhs_address_t &rhs_addr) const; + void execute_broadcast_no_tail(const data_type_t &data_type, + const Vmm &tmp_vmm, const rhs_address_t &rhs_addr) const; + void execute_broadcast_s8u8_no_tail(const data_type_t &data_type, + const Vmm &tmp_vmm, const rhs_address_t &rhs_addr) const; + void load_rhs_no_tail(const data_type_t &data_type, const Vmm &tmp_reg, + const rhs_address_t &rhs_addr) const; + void load_rhs_i8_no_tail(const data_type_t &data_type, const Vmm &tmp_reg, + const rhs_address_t &rhs_addr) const; + void cvt_to_f32(const Vmm &tmp_reg) const; + /* + * Returns pair consisting of flag indication preservation is needed for vmm + * index in second member that should be used as temporary vmm inside inject + * binary. + */ + std::pair should_preserve_vmm(int curr_idx, int vmm_hint, + int max_vmm_idx, bool dt_helper_vmm_needed) const; + /* + * Used in isa != avx512 where m32bcst is not supported, replaces ptr_b + * with ptr. + */ + rhs_address_t remove_bcast_bit(const rhs_address_t &rhs_addr) const; + + jit_generator *host_; + const rhs_arg_static_params_t rhs_arg_static_params_; + const Xbyak_aarch64::XReg param1_; + const bcast_set_t supported_strategy_set_; + + static constexpr int sizeof_reg64 = 8; + /* + * Instructions from SSE/AVX used to compute binary result like vaddps where + * second operand is memory, require mem operand to be 16/32 byte explicitly + * aligned. (Intel Manual chapter 2.4). + * Rule is relaxed from AVX2 (Intel Manual chapter 14.9). + * When using benchdnn zmalloc_protect doesn't guarantee that tensor memory + * address is 64 byte aligned, which can cause segmentation fault. + */ + static constexpr bool binary_op_with_unaligned_mem_operand_allowed_ = true; +}; + +} // namespace binary_injector +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/injectors/jit_uni_eltwise_injector.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/injectors/jit_uni_eltwise_injector.hpp new file mode 100644 index 0000000000000000000000000000000000000000..7301d99d5675588db4d6ad8769a9853759ce3fec --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/injectors/jit_uni_eltwise_injector.hpp @@ -0,0 +1,359 @@ +/******************************************************************************* +* Copyright 2019-2023 Intel Corporation +* Copyright 2021-2023 FUJITSU LIMITED +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_JIT_UNI_ELTWISE_INJECTOR_HPP +#define CPU_AARCH64_JIT_UNI_ELTWISE_INJECTOR_HPP + +#include +#include + +#include "common/c_types_map.hpp" +#include "common/primitive_attr.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/aarch64/injectors/injector_utils.hpp" +#include "cpu/aarch64/jit_generator.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +namespace eltwise_injector { +struct static_params_t { + + static_params_t(bool save_state = true, + Xbyak_aarch64::XReg x_table = Xbyak_aarch64::XReg(0), + Xbyak_aarch64::PReg p_mask = Xbyak_aarch64::PReg(1), + Xbyak_aarch64::PReg p_tmp0 = Xbyak_aarch64::PReg(4), + bool is_fwd = true, bool use_dst = false, bool preserve_vmm = true, + bool preserve_p_table = true) + : save_state(save_state) + , x_table(x_table) + , p_mask(p_mask) + , p_tmp0(p_tmp0) + , is_fwd(is_fwd) + , use_dst(use_dst) + , preserve_vmm(preserve_vmm) + , preserve_p_table(preserve_p_table) {} + + bool save_state; + Xbyak_aarch64::XReg x_table; + Xbyak_aarch64::PReg p_mask; + Xbyak_aarch64::PReg p_tmp0; + bool is_fwd; + bool use_dst; + bool preserve_vmm; + bool preserve_p_table; +}; + +/* + * Checks if isa is supported by eltwise injector. + */ +bool is_isa_supported(cpu_isa_t isa); + +/* + * Checks if eltwise algorithm is supported by eltwise injector. + */ +bool is_alg_supported(alg_kind_t alg); + +/* + * Checks if eltwise injection for given args is supported. + */ +bool is_supported(cpu_isa_t isa, alg_kind_t alg); + +} // namespace eltwise_injector + +template +struct jit_uni_eltwise_injector_f32 { + using TReg = typename cpu_isa_traits::TReg; + using TRegS = typename cpu_isa_traits::TRegS; + + // Arguments description: + // host - jit generator which is filled with instructions + // alg, alpha, beta, scale - user eltwise arguments + // save_state - when true, preserves on stack vmm_aux registers preventing + // results spoiling. Restores them when done in injector_postamble(). + // p_table - GPR where table label is stored to get access for pre-defined + // constants used in alg codes. + // k_mask - k_register to operate with masks in alg codes. + // is_fwd - when true, computes d = alg(s), otherwise, computes ds = alg'(s) + // - algorithm derivative. + // use_dst - defines whether source or destination point is passed to alg + // code. Depends on algorithm. See `_use_dst_for_bwd` algs definition. + jit_uni_eltwise_injector_f32(jit_generator *host, alg_kind_t alg, + float alpha, float beta, float scale, bool save_state = true, + Xbyak_aarch64::XReg x_table = Xbyak_aarch64::XReg(0), + Xbyak_aarch64::PReg p_mask = Xbyak_aarch64::PReg(1), + Xbyak_aarch64::PReg p_tmp0 = Xbyak_aarch64::PReg(4), + bool is_fwd = true, bool use_dst = false, bool preserve_vmm = true, + bool preserve_p_table = true) + : alg_(alg) + , alpha_(alpha) + , beta_(beta) + , scale_(scale) + , h(host) + , save_state_(save_state) + , x_table(x_table) + , p_mask(p_mask) + , p_tmp0(p_tmp0) + , is_fwd_(is_fwd) + , use_dst_(use_dst) + , preserve_vmm_(preserve_vmm) + , preserve_p_table_(preserve_p_table) { + assert(eltwise_injector::is_supported(isa, alg_)); + + register_table_entries(); + } + + jit_uni_eltwise_injector_f32(jit_generator *host, + const post_ops_t::entry_t::eltwise_t &eltwise, + bool save_state = true, + Xbyak_aarch64::XReg x_table = Xbyak_aarch64::XReg(0), + Xbyak_aarch64::PReg p_mask = Xbyak_aarch64::PReg(1), + Xbyak_aarch64::PReg p_tmp0 = Xbyak_aarch64::PReg(4), + bool is_fwd = true, bool use_dst = false, bool preserve_vmm = true, + bool preserve_p_table = true) + : jit_uni_eltwise_injector_f32(host, eltwise.alg, eltwise.alpha, + eltwise.beta, eltwise.scale, save_state, x_table, p_mask, + p_tmp0, is_fwd, use_dst, preserve_vmm, preserve_p_table) {} + + void compute_vector_range(size_t start_idx, size_t end_idx); + void compute_vector_range(const injector_utils::vmm_index_set_t &vmm_idxs); + void compute_vector(size_t idx) { compute_vector_range(idx, idx + 1); } + void prepare_table(bool gen_table = true); + void load_table_addr() { h->adr(x_table, l_table); } + +private: + const alg_kind_t alg_; + const float alpha_; + const float beta_; + const float scale_; + + jit_generator *const h; + + const bool save_state_; + const Xbyak_aarch64::XReg x_table; + // 99 is dummy and must be replaced meaningfull value at runtime. + Xbyak_aarch64::PReg p_all = Xbyak_aarch64::PReg(99); + const Xbyak_aarch64::PReg p_mask; + const Xbyak_aarch64::PReg p_tmp0; + const bool is_fwd_; + const bool use_dst_; + const bool preserve_vmm_; + const bool preserve_p_table_; + + Xbyak_aarch64::Label l_table; + + // if only the injector was inherited from jit_generator... + enum { + _cmp_eq_oq = jit_generator::_cmp_eq_oq, + _cmp_lt_os = jit_generator::_cmp_lt_os, + _cmp_le_os = jit_generator::_cmp_le_os, + _cmp_ge_os = jit_generator::_cmp_nlt_us, + _cmp_gt_os = jit_generator::_cmp_nle_us, + _op_floor = jit_generator::_op_floor, + _op_mxcsr = jit_generator::_op_mxcsr + }; + + const size_t vlen = get_sve_length(); + static constexpr size_t preserved_vecs_max = 9; + static constexpr size_t preserved_gprs_max = 4; + static constexpr size_t vecs_count = cpu_isa_traits::n_vregs; + static constexpr int n_mantissa_bits = 23; + static constexpr int k_mask_size = 8; + + size_t vecs_to_preserve = 0; + size_t preserved_vecs_count = 0; + size_t preserved_vec_idxs[preserved_vecs_max] = {0}; + size_t preserved_gpr_idxs[preserved_gprs_max] = {0}; + injector_utils::vmm_index_set_iterator_t start_idx_tail; + + /* These vector register must be assigned proper index. */ + TRegS vmm_mask {0}, vmm_aux0 {0}, vmm_aux1 {0}, vmm_aux2 {0}, vmm_aux3 {0}, + vmm_aux4 {0}, vmm_aux5 {0}, vmm_aux6 {0}, vmm_aux7 {0}, vmm_tmp {0}; + /* Default tempooral index. Chose a SVE register + not to be same as jit_uni_eltwise.(cpp|hpp). + This index is changed by assign_regs() in case of eltwise injection. + */ + TRegS z_tmp {31}; + + size_t aux_vecs_count(); + size_t aux_gprs_count(); + + void compute_body( + const injector_utils::vmm_index_set_iterator_t &start_idx_it, + const injector_utils::vmm_index_set_iterator_t &end_idx_it); + void injector_preamble(const injector_utils::vmm_index_set_t &vmm_idxs); + void injector_preamble_tail( + const injector_utils::vmm_index_set_iterator_t start_idx_it); + void injector_postamble(); + void assign_regs(); + void set_coef_to_regs(); + void compute_cmp_mask( + const TRegS &vmm_src, const TRegS &vmm_cmpare, int cmp_predicate); + void blend_with_mask(const TRegS &vmm_dst, const TRegS &src); + void test_mask(); + + void exp_compute_vector_fwd(const TRegS &vmm_src); + void relu_compute_vector_fwd(const TRegS &vmm_src); + void relu_zero_ns_compute_vector_fwd(const TRegS &vmm_src); + void elu_compute_vector_fwd(const TRegS &vmm_src); + void tanh_compute_vector_fwd(const TRegS &vmm_src); + void square_compute_vector_fwd(const TRegS &vmm_src); + void abs_compute_vector_fwd(const TRegS &vmm_src); + void sqrt_compute_vector_fwd(const TRegS &vmm_src); + void linear_compute_vector_fwd(const TRegS &vmm_src); + void soft_relu_compute_vector_fwd(const TRegS &vmm_src); + void mish_compute_vector_fwd(const TRegS &vmm_src); + void logistic_compute_vector_fwd(const TRegS &vmm_src); + void gelu_tanh_compute_vector_fwd(const TRegS &vmm_src); + void swish_compute_vector_fwd(const TRegS &vmm_src); + void log_compute_vector_fwd(const TRegS &vmm_src); + void clip_compute_vector_fwd(const TRegS &vmm_src); + void gelu_erf_compute_vector_fwd(const TRegS &vmm_src); + void gelu_erf_minimax_approx_compute_vector_fwd(const TRegS &vmm_src); + void round_compute_vector_fwd(const TRegS &vmm_src); + void hardswish_compute_vector_fwd(const TRegS &vmm_src); + void hardsigmoid_compute_vector_fwd(const TRegS &vmm_src); + + void exp_compute_vector_bwd(const TRegS &vmm_src); + void relu_compute_vector_bwd(const TRegS &vmm_src); + void elu_compute_vector_bwd(const TRegS &vmm_src); + void tanh_compute_vector_bwd(const TRegS &vmm_src); + void square_compute_vector_bwd(const TRegS &vmm_src); + void abs_compute_vector_bwd(const TRegS &vmm_src); + void sqrt_compute_vector_bwd(const TRegS &vmm_src); + void linear_compute_vector_bwd(const TRegS &vmm_src); + void soft_relu_compute_vector_bwd(const TRegS &vmm_src); + void logistic_compute_vector_bwd(const TRegS &vmm_src); + void mish_compute_vector_bwd(const TRegS &vmm_src); + void gelu_tanh_compute_vector_bwd(const TRegS &vmm_src); + void swish_compute_vector_bwd(const TRegS &vmm_src); + void log_compute_vector_bwd(const TRegS &vmm_src); + void clip_compute_vector_bwd(const TRegS &vmm_src); + void gelu_erf_compute_vector_bwd(const TRegS &vmm_src); + void hardswish_compute_vector_bwd(const TRegS &vmm_src); + void hardsigmoid_compute_vector_bwd(const TRegS &vmm_src); + + enum key_t { + scale = 0, // scale argument + alpha, // alpha argument + beta, // beta argument + zero, // 0.f + half, // 0.5f + one, // 1.f or mask for exponent bits + two, // 2.f + minus_one, // -1.f or changes sign to opposite + minus_two, // -2.f + ln2f, // 0.69314718f + positive_mask, // changes sign to positive + sign_mask, // gets sign value + exponent_bias, // (127 = 2^7 - 1), gets exponent bits + exp_log2ef, // 1.44269502f - formula-based for approx + exp_ln_flt_max_f, // logf(FLT_MAX) - max normal value + exp_ln_flt_min_f, // logf(FLT_MIN) - min normal value + exp_pol, // see correspondent table for float values + exp_coeff1, // 0.6931473921 (0x3f31721c) + exp_coeff2, // 0.2413862043 (0x3e772df2) + exp_not_mask17, // ~((1u << 17) - 1) + fwd_mish_max_x_for_equation_f, + // e^x(e^3x+4e^2x+e^x*(6+4*x)+4*(1+x)) = FLT_MAX; x =~ 22.18070976278534 + bwd_mish_max_x_for_equation_f, + tanh_range, // tanh(x) = x - x^3/3 for |x| < tanh_range + tanh_m1d3, // -1/3 + soft_relu_one_twenty_six, // 126.f + soft_relu_mantissa_sign_mask, // mask for mantissa bits and sign + soft_relu_pol, // see correspondent table for float values + gelu_tanh_fitting_const, // 0.044715f + gelu_tanh_fitting_const_times_three, // 0.134145f + gelu_tanh_sqrt_two_over_pi, // sqrtf(2.f/pi) = 0.797884f + gelu_erf_approx_const, // 0.3275911f - implementation based for approx + gelu_erf_one_over_sqrt_two, // 1.f / sqrtf(2.f) + gelu_erf_one_over_sqrt_pi, // 1.f / sqrtf(pi) = 0.564190f + gelu_erf_pol, // see correspondent table for float values + log_minus_inf, // -inf + log_qnan, // qnan + log_mantissa_mask, // gets mantissa bits + log_full_k_reg_mask, // sets k_register with all bits of 1 + log_full_vector_reg_mask, // sets vector register will all bits of 1 + log_five_bit_offset, // 5 bits off (31 = 2^5 - 1) + log_pol, // see correspondent table for float values + log_predefined_vals, // see correspondent table for float values + log_i127shl23, + log_x7fffff, + log_log2, + log_log1p5, + log_f2div3, + log_coeffTbl, + undef_key, + }; + + size_t table_off(key_t key, size_t key_off_val_shift = 0) { + // assumption: all table entries sharing the same key also + // share their broadcast property + // TODO: enforce through data structure + const auto it = entry_map_.find(key); // search an entry for a key + assert(it != entry_map_.end()); + const auto &te = (*it).second; + const auto scale = te.bcast ? vlen : sizeof(table_entry_val_t); + return te.off + key_off_val_shift * scale; + } + + TRegS table_val(key_t key, TRegS zreg, size_t key_off_val_shift = 0) { + Xbyak_aarch64::XReg x_addr(h->X_DEFAULT_ADDR); + auto off = table_off(key, key_off_val_shift); + + if (off) { + h->add_imm(x_addr, x_table, off, h->X_TMP_0); + } else { + x_addr = x_table; + } + + h->ldr(TReg(zreg.getIdx()), ptr(x_addr)); + return zreg; + } + + // we accept only 32bit hexadecimal table values to avoid any rounding + using table_entry_val_t = uint32_t; + using table_entry_offset_t = size_t; // offsets are in bytes wrt p_table + using table_entry_bcast_t = bool; // true => bcast value + + struct table_entry_t { + table_entry_val_t val; + table_entry_bcast_t bcast; + }; + struct mapped_table_entry_t { + table_entry_offset_t off; + table_entry_val_t val; + table_entry_bcast_t bcast; + }; + + using table_t = std::multimap; + using mapped_table_t = std::multimap; + + void register_table_entries(); + mapped_table_t entry_map_; +}; + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/injectors/jit_uni_postops_injector.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/injectors/jit_uni_postops_injector.hpp new file mode 100644 index 0000000000000000000000000000000000000000..82a69334d885eb1220e2dc242abeca85c96c0d38 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/injectors/jit_uni_postops_injector.hpp @@ -0,0 +1,167 @@ +/******************************************************************************* +* Copyright 2020-2023 Intel Corporation +* Copyright 2022-2023 FUJITSU LIMITED +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ +#ifndef CPU_AARCH64_JIT_UNI_POSTOPS_INJECTOR_HPP +#define CPU_AARCH64_JIT_UNI_POSTOPS_INJECTOR_HPP + +#include +#include +#include + +#include "common/c_types_map.hpp" +#include "common/primitive_attr.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" +#include "cpu/aarch64/injectors/injector_utils.hpp" +#include "cpu/aarch64/injectors/jit_uni_binary_injector.hpp" +#include "cpu/aarch64/injectors/jit_uni_eltwise_injector.hpp" +#include "cpu/aarch64/jit_generator.hpp" +#include + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { +namespace injector { + +/* + * Allows specifying custom injector function for given post-op type - one + * function per primitive. There are post-ops type (example: sum) that don't + * have specialized injector. They heavily rely on kernel specific intrnals, + * which makes the generalization unreasonable. As so user can prepare internal + * kernel lambda and pass it explicitly to injector. + */ +using lambda_jit_injectors_t + = std::map>; + +struct post_ops_ok_args_t; +/* + * Checks if postops injection for given args is supported. + */ +bool is_supported(const post_ops_ok_args_t &post_ops_ok_args); + +/* + * Main mechanism of handling various post-ops types. It utilizes internally + * specialized injectors to generate post-ops code to host primitive. Random + * order of post-ops is supported. + */ +template +class jit_uni_postops_injector_t { +public: + /* + * @param host - user primitive where post-ops generated code is + * injected + * @param post_ops - struct representing requested post-ops chain + * @binary_static_params - static params needed for binary_injector. + * see: jit_uni_binary_injector.hpp for more info. + * @param eltwise_static_params - allows user specify non default + * params for eltwise_injector + * @param lambda_jit_injectors - allows user specify custom injector + * function for given post-op type + */ + jit_uni_postops_injector_t(jit_generator *host, const post_ops_t &post_ops, + const binary_injector::static_params_t &binary_static_params); + jit_uni_postops_injector_t(jit_generator *host, const post_ops_t &post_ops, + const binary_injector::static_params_t &binary_static_params, + const lambda_jit_injectors_t &lambda_jit_injectors); + jit_uni_postops_injector_t(jit_generator *host, const post_ops_t &post_ops, + const binary_injector::static_params_t &binary_static_params, + const eltwise_injector::static_params_t &eltwise_static_params); + jit_uni_postops_injector_t(jit_generator *host, const post_ops_t &post_ops, + const binary_injector::static_params_t &binary_static_params, + const eltwise_injector::static_params_t &eltwise_static_params, + const lambda_jit_injectors_t &lambda_jit_injectors); + + /* + * Generates code of post_ops chain injected to host primitive. Applied to + * ordered set of vector registers' indexes. + * + * @rhs_arg_params: see jit_uni_binary_injector description + */ + void compute_vector_range(const injector_utils::vmm_index_set_t &vmm_idxs, + const binary_injector::rhs_arg_dynamic_params_t &rhs_arg_params); + + void compute_vector_range(const injector_utils::vmm_index_set_t &vmm_idxs); + + /* + * Generates code of post_ops chain injected to host primitive. Applied to + * range > alg_to_eltwise_injector_; + std::unique_ptr> + binary_injector_; + lambda_jit_injectors_t lambda_jit_injectors_; +}; + +enum post_op_type { sum = 0, eltwise, binary }; + +struct post_ops_ok_args_t { + post_ops_ok_args_t(const cpu_isa_t isa, + const std::vector &accepted_post_op_types, + const post_ops_t &post_ops, const memory_desc_wrapper *dst_d, + const bool sum_at_pos_0_only, const bool sum_requires_scale_one, + const bool sum_requires_zp_zero = true, + const bool sum_requires_same_params = true, + const bcast_set_t &enabled_bcast_strategy = default_strategies()); + + const cpu_isa_t isa; + const std::vector &accepted_post_op_types; + const post_ops_t &post_ops; + const memory_desc_wrapper *dst_d; + const bool sum_at_pos_0_only; + const bool sum_requires_scale_one; + const bool sum_requires_zp_zero; + const bool sum_requires_same_params; + const bcast_set_t enabled_bcast_strategy; +}; + +bool post_ops_ok(const post_ops_ok_args_t &args); + +} // namespace injector +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_generator.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_generator.hpp new file mode 100644 index 0000000000000000000000000000000000000000..05076637fad40fa190f4e6b5cbda361e8f589149 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_generator.hpp @@ -0,0 +1,728 @@ +/******************************************************************************* +* Copyright 2016-2023 Intel Corporation +* Copyright 2020-2023 FUJITSU LIMITED +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_JIT_GENERATOR_HPP +#define CPU_AARCH64_JIT_GENERATOR_HPP + +#include + +#include "common/bit_cast.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/aarch64/cpu_isa_traits.hpp" + +#include "cpu/jit_utils/jit_utils.hpp" + +#if defined(_WIN32) && !defined(__GNUC__) +#define STRUCT_ALIGN(al, ...) __declspec(align(al)) __VA_ARGS__ +#else +#define STRUCT_ALIGN(al, ...) __VA_ARGS__ __attribute__((__aligned__(al))) +#endif + +#define DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_name) \ + const char *name() const override { return STRINGIFY(jit_name); } \ + const char *source_file() const override { return __FILE__; } + +static const size_t CSIZE = sizeof(uint32_t); + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +// TODO: move this to jit_generator class? +namespace { + +typedef enum { + MAX_CODE_SIZE = 256 * 1024, +} max_code_size_t; + +// Callee-saved registers +constexpr Xbyak_aarch64::Operand::Code abi_save_gpr_regs[] + = {Xbyak_aarch64::Operand::X16, Xbyak_aarch64::Operand::X17, + Xbyak_aarch64::Operand::X19, Xbyak_aarch64::Operand::X20, + Xbyak_aarch64::Operand::X21, Xbyak_aarch64::Operand::X22, + Xbyak_aarch64::Operand::X23, Xbyak_aarch64::Operand::X24, + Xbyak_aarch64::Operand::X25, Xbyak_aarch64::Operand::X26, + Xbyak_aarch64::Operand::X27, Xbyak_aarch64::Operand::X28}; + +// See "Procedure Call Standsard for the ARM 64-bit Architecture (AArch64)" +static const Xbyak_aarch64::XReg abi_param1(Xbyak_aarch64::Operand::X0), + abi_param2(Xbyak_aarch64::Operand::X1), + abi_param3(Xbyak_aarch64::Operand::X2), + abi_param4(Xbyak_aarch64::Operand::X3), + abi_param5(Xbyak_aarch64::Operand::X4), + abi_param6(Xbyak_aarch64::Operand::X5), + abi_param7(Xbyak_aarch64::Operand::X6), + abi_param8(Xbyak_aarch64::Operand::X7), + abi_not_param1(Xbyak_aarch64::Operand::X15); +} // namespace + +class jit_generator : public Xbyak_aarch64::CodeGenerator, public c_compatible { +public: + using c_compatible::operator new; + using c_compatible::operator new[]; + using c_compatible::operator delete; + using c_compatible::operator delete[]; + +private: + const size_t xreg_len = 8; + const size_t vreg_len_preserve = 8; // Only bottom 8byte must be preserved. + const size_t vreg_to_preserve = 8; // VREG8 - VREG15 + + const size_t num_abi_save_gpr_regs + = sizeof(abi_save_gpr_regs) / sizeof(abi_save_gpr_regs[0]); + + const size_t preserved_stack_size = xreg_len * (2 + num_abi_save_gpr_regs) + + vreg_len_preserve * vreg_to_preserve; + + const size_t size_of_abi_save_regs = num_abi_save_gpr_regs * x0.getBit() / 8 + + vreg_to_preserve * vreg_len_preserve; + +public: + enum { + _cmp_eq_oq = 0u, + _cmp_lt_os = 1u, + _cmp_le_os = 2u, + _cmp_neq_uq = 4u, + _cmp_nlt_us = 5u, + _cmp_nle_us = 6u, + + _op_floor = 1u, + _op_mxcsr = 4u, + }; + + const uint64_t cpu_sveLen = get_sve_length(); + + const Xbyak_aarch64::WReg W_TMP_0 = w23; + const Xbyak_aarch64::WReg W_TMP_1 = w24; + const Xbyak_aarch64::WReg W_TMP_2 = w25; + const Xbyak_aarch64::WReg W_TMP_3 = w26; + const Xbyak_aarch64::WReg W_TMP_4 = w27; + const Xbyak_aarch64::XReg X_TMP_0 = x23; + const Xbyak_aarch64::XReg X_TMP_1 = x24; + const Xbyak_aarch64::XReg X_TMP_2 = x25; + const Xbyak_aarch64::XReg X_TMP_3 = x26; + const Xbyak_aarch64::XReg X_TMP_4 = x27; + const Xbyak_aarch64::XReg X_DEFAULT_ADDR = x28; + const Xbyak_aarch64::XReg X_SP = x21; + const Xbyak_aarch64::XReg X_TRANSLATOR_STACK = x22; + const Xbyak_aarch64::PReg P_TMP = p7; + const Xbyak_aarch64::PReg P_TMP_0 = p11; + const Xbyak_aarch64::PReg P_TMP_1 = p12; + const Xbyak_aarch64::PReg P_ALL_ZERO = p10; + const Xbyak_aarch64::PReg P_NOT_256 = p13; + const Xbyak_aarch64::PReg P_NOT_128 = p14; + const Xbyak_aarch64::PReg P_ALL_ONE = p0; + + const std::vector x_tmp_vec + = {X_TMP_0, X_TMP_1, X_TMP_2, X_TMP_3, X_TMP_4}; + const int x_tmp_vec_size = x_tmp_vec.size(); + + const Xbyak_aarch64::XReg param1 = abi_param1; + constexpr static size_t translator_stack_offset = 1024 * 128; + constexpr static uint32_t DUMMY_IDX = 99; + + inline size_t get_size_of_abi_save_regs() { return size_of_abi_save_regs; } + + void preamble() { + using namespace Xbyak_aarch64::util; + uint64_t sveLen = get_sve_length(); + + stp(x29, x30, pre_ptr(sp, -16)); + /* x29 is a frame pointer. */ + mov(x29, sp); + sub(sp, sp, static_cast(preserved_stack_size) - 16); + + /* x9 can be used as a temporal register. */ + mov(x9, sp); + + if (vreg_to_preserve) { + st4((v8.d - v11.d)[0], post_ptr(x9, vreg_len_preserve * 4)); + st4((v12.d - v15.d)[0], post_ptr(x9, vreg_len_preserve * 4)); + } + for (size_t i = 0; i < num_abi_save_gpr_regs; i += 2) { + stp(Xbyak_aarch64::XReg(abi_save_gpr_regs[i]), + Xbyak_aarch64::XReg(abi_save_gpr_regs[i + 1]), + post_ptr(x9, xreg_len * 2)); + } + + if (sveLen) { /* SVE is available. */ + ptrue(P_ALL_ONE.b); + pfalse(P_ALL_ZERO.b); + } + if (sveLen >= SVE_256) { + ptrue(P_NOT_128.b, Xbyak_aarch64::VL16); + not_(P_NOT_128.b, P_ALL_ONE / Xbyak_aarch64::T_z, P_NOT_128.b); + } + if (sveLen >= SVE_512) { + ptrue(P_NOT_256.b, Xbyak_aarch64::VL32); + not_(P_NOT_256.b, P_ALL_ONE / Xbyak_aarch64::T_z, P_NOT_256.b); + } + + mov(X_SP, sp); + sub_imm(X_TRANSLATOR_STACK, X_SP, translator_stack_offset, X_TMP_0); + } + + void postamble() { + using namespace Xbyak_aarch64::util; + + mov(x9, sp); + + if (vreg_to_preserve) { + ld4((v8.d - v11.d)[0], post_ptr(x9, vreg_len_preserve * 4)); + ld4((v12.d - v15.d)[0], post_ptr(x9, vreg_len_preserve * 4)); + } + + for (size_t i = 0; i < num_abi_save_gpr_regs; i += 2) { + ldp(Xbyak_aarch64::XReg(abi_save_gpr_regs[i]), + Xbyak_aarch64::XReg(abi_save_gpr_regs[i + 1]), + post_ptr(x9, xreg_len * 2)); + } + + add(sp, sp, static_cast(preserved_stack_size) - 16); + ldp(x29, x30, post_ptr(sp, 16)); + ret(); + } + + // Disallow char-based labels completely + void L(const char *label) = delete; + void L(Xbyak_aarch64::Label &label) { + Xbyak_aarch64::CodeGenerator::L(label); + } + + void L_aligned(Xbyak_aarch64::Label &label, int alignment = 16) { + align(alignment); + L(label); + } + + template + Xbyak_aarch64::XReg addr_off(const Xbyak_aarch64::XReg &base, const T off, + const Xbyak_aarch64::XReg &addr, const Xbyak_aarch64::XReg &x_tmp) { + if (off == 0) return base; + + add_imm(addr, base, off, x_tmp); + return addr; + } + + template + void set_preg(const PRegBHSD &p, T tail_size, + const Xbyak_aarch64::XReg x_tmp0 = Xbyak_aarch64::XReg(DUMMY_IDX), + const Xbyak_aarch64::XReg x_tmp1 = Xbyak_aarch64::XReg(DUMMY_IDX)) { + using namespace Xbyak_aarch64; + + assert(tail_size <= 64); // Implemented only for "SVE size <= 512" + + switch (tail_size) { + case 0: pfalse(PRegB(p.getIdx())); return; + case 1: ptrue(p, VL1); return; + case 2: ptrue(p, VL2); return; + case 3: ptrue(p, VL3); return; + case 4: ptrue(p, VL4); return; + case 5: ptrue(p, VL5); return; + case 6: ptrue(p, VL6); return; + case 7: ptrue(p, VL7); return; + case 8: ptrue(p, VL8); return; + case 16: ptrue(p, VL16); return; + case 32: ptrue(p, VL32); return; + case 64: ptrue(p, VL64); return; + } + + assert(x_tmp0.getIdx() != DUMMY_IDX && x_tmp1.getIdx() != DUMMY_IDX); + mov_imm(x_tmp0, 0); + mov_imm(x_tmp1, tail_size); + whilelt(p, x_tmp0, x_tmp1); + } + + template + void uni_add(const T &x1, const T &x2, const T &op) { + add(x1, x2, op); + } + + void uni_add(const Xbyak_aarch64::VReg4S &x1, + const Xbyak_aarch64::VReg4S &x2, const Xbyak_aarch64::VReg4S &op) { + add(x1, x2, op); + } + + void uni_add(const Xbyak_aarch64::ZReg &x1, const Xbyak_aarch64::ZReg &x2, + const Xbyak_aarch64::ZReg &op) { + add(Xbyak_aarch64::ZRegS(x1.getIdx()), + Xbyak_aarch64::ZRegS(x2.getIdx()), + Xbyak_aarch64::ZRegS(op.getIdx())); + } + + template + void udiv_mod(const T &q, const T &r, const T &divend, const T &divisor) { + assert(q.getIdx() != divisor.getIdx()); + assert(q.getIdx() != divend.getIdx()); + assert(r.getIdx() != divend.getIdx()); + + udiv(q, divend, divisor); + mul(r, q, divisor); + sub(r, divend, r); + } + + template + void umod(const T &r, const T &divend, const T &divisor) { + assert(r.getIdx() != divend.getIdx()); + assert(r.getIdx() != divisor.getIdx()); + + udiv(r, divend, divisor); + mul(r, r, divisor); + sub(r, divend, r); + } + + void uni_clear(const Xbyak_aarch64::VReg &dst) { eor(dst.b, dst.b, dst.b); } + + void uni_clear(const Xbyak_aarch64::ZReg &dst) { eor(dst.d, dst.d, dst.d); } + + template + void uni_fadd(const T &dst, const T &src, const T &src2) { + fadd(dst, src, src2); + } + + void uni_fcvtzs( + const Xbyak_aarch64::VReg4S &d, const Xbyak_aarch64::VReg4S &s) { + fcvtzs(d, s); + } + + void uni_fcvtzs( + const Xbyak_aarch64::ZRegS &d, const Xbyak_aarch64::ZRegS &s) { + fcvtzs(d, P_ALL_ONE / Xbyak_aarch64::T_z, s); + } + + template + void uni_fdiv(const TReg &dst, const TReg &src, const TReg &src2, + const TReg &tmp, const Xbyak_aarch64::PReg &pred) { + uint32_t dstIdx = dst.getIdx(); + uint32_t srcIdx = src.getIdx(); + uint32_t src2Idx = src2.getIdx(); + uint32_t tmpIdx = tmp.getIdx(); + + if (dstIdx == src2Idx) { + assert(tmpIdx != srcIdx && tmpIdx != src2Idx); + + mov(Xbyak_aarch64::ZRegD(tmpIdx), Xbyak_aarch64::ZRegD(src2Idx)); + mov(dst, pred / Xbyak_aarch64::T_m, src); + fdiv(dst, pred / Xbyak_aarch64::T_m, tmp); + } else if (dstIdx == srcIdx) { + fdiv(dst, pred / Xbyak_aarch64::T_m, src2); + } else { + mov(dst, P_ALL_ONE / Xbyak_aarch64::T_m, src); + fdiv(dst, pred / Xbyak_aarch64::T_m, src2); + } + } + + template + void uni_fdiv(const TReg &dst, const TReg &src, const TReg &src2) { + fdiv(dst, src, src2); + } + + void uni_fdiv(const Xbyak_aarch64::VReg4S &dst, + const Xbyak_aarch64::VReg4S &src, const Xbyak_aarch64::VReg4S &src2, + const Xbyak_aarch64::VReg4S &tmp, const Xbyak_aarch64::PReg &pred) { + UNUSED(tmp); + UNUSED(pred); + fdiv(dst, src, src2); + } + + template + void uni_fmad(const T &dst, const T &src, const T &src2) { + fmad(dst, P_ALL_ONE / Xbyak_aarch64::T_m, src, src2); + } + + void uni_fmad(const Xbyak_aarch64::VReg4S &dst, + const Xbyak_aarch64::VReg4S &src, + const Xbyak_aarch64::VReg4S &src2) { + fmul(dst, dst, src); + fadd(dst, dst, src2); + } + + template + void uni_fmax(const T &dst, const T &src, const T &src2) { + uint32_t dstIdx = dst.getIdx(); + uint32_t srcIdx = src.getIdx(); + if (dstIdx != srcIdx) + mov(Xbyak_aarch64::ZRegD(dstIdx), Xbyak_aarch64::ZRegD(srcIdx)); + fmax(dst, P_ALL_ONE / Xbyak_aarch64::T_m, src2); + } + + template + void uni_fmaxnm(const T &dst, const T &src, const T &src2) { + uint32_t dstIdx = dst.getIdx(); + uint32_t srcIdx = src.getIdx(); + if (dstIdx != srcIdx) + mov(Xbyak_aarch64::ZRegD(dstIdx), Xbyak_aarch64::ZRegD(srcIdx)); + fmaxnm(dst, P_ALL_ONE / Xbyak_aarch64::T_m, src2); + } + + void uni_fmaxnm(const Xbyak_aarch64::VReg4S &dst, + const Xbyak_aarch64::VReg4S &src, + const Xbyak_aarch64::VReg4S &src2) { + fmaxnm(dst, src, src2); + } + + template + void uni_fmin(const T &dst, const T &src, const T &src2) { + uint32_t dstIdx = dst.getIdx(); + uint32_t srcIdx = src.getIdx(); + if (dstIdx != srcIdx) + mov(Xbyak_aarch64::ZRegD(dstIdx), Xbyak_aarch64::ZRegD(srcIdx)); + fmin(dst, P_ALL_ONE / Xbyak_aarch64::T_m, src2); + } + + template + void uni_fmul(const T &dst, const T &src, const T &src2) { + fmul(dst, src, src2); + } + + void uni_frinti( + const Xbyak_aarch64::VReg4S &d, const Xbyak_aarch64::VReg4S &s) { + frinti(d, s); + } + + void uni_frinti( + const Xbyak_aarch64::ZRegS &d, const Xbyak_aarch64::ZRegS &s) { + frinti(d, P_ALL_ONE / Xbyak_aarch64::T_m, s); + } + + template + void uni_fsqrt(const T &dst, const T &src) { + fsqrt(dst, P_ALL_ONE / Xbyak_aarch64::T_m, src); + } + + void uni_fsqrt(const Xbyak_aarch64::VReg4S &dst, + const Xbyak_aarch64::VReg4S &src) { + fsqrt(dst, src); + } + + void uni_fsub(const Xbyak_aarch64::VReg4S &v1, + const Xbyak_aarch64::VReg4S &v2, const Xbyak_aarch64::VReg4S &v3) { + fsub(v1, v2, v3); + } + + template + void uni_fsub(const T &dst, const T &src, const T &src2) { + fsub(dst, src, src2); + } + + void uni_fsub(const Xbyak_aarch64::ZRegS &z1, + const Xbyak_aarch64::ZRegS &z2, const Xbyak_aarch64::ZRegS &z3) { + fsub(z1, z2, z3); + } + + void uni_eor(const Xbyak_aarch64::VReg &v1, const Xbyak_aarch64::VReg &v2, + const Xbyak_aarch64::VReg &v3) { + eor(Xbyak_aarch64::VReg16B(v1.getIdx()), + Xbyak_aarch64::VReg16B(v2.getIdx()), + Xbyak_aarch64::VReg16B(v3.getIdx())); + } + + void uni_eor(const Xbyak_aarch64::ZReg &z1, const Xbyak_aarch64::ZReg &z2, + const Xbyak_aarch64::ZReg &z3) { + eor(Xbyak_aarch64::ZRegD(z1.getIdx()), + Xbyak_aarch64::ZRegD(z2.getIdx()), + Xbyak_aarch64::ZRegD(z3.getIdx())); + } + + void uni_ld1rw(const Xbyak_aarch64::VReg4S &dst, + const Xbyak_aarch64::XReg &base, const int64_t off) { + if (off == 0) { + ld1r(dst, ptr(base)); + } else { + add_imm(X_DEFAULT_ADDR, base, off, X_TMP_0); + ld1r(dst, ptr(X_DEFAULT_ADDR)); + } + } + + void uni_ld1rw(const Xbyak_aarch64::ZRegS &dst, + const Xbyak_aarch64::XReg &base, const int64_t off) { + if (-32 <= off && off < 32) { + ld1rw(dst, P_ALL_ONE / Xbyak_aarch64::T_z, ptr(base, (int)off)); + } else { + add_imm(X_DEFAULT_ADDR, base, off, X_TMP_0); + ld1rw(dst, P_ALL_ONE / Xbyak_aarch64::T_z, ptr(X_DEFAULT_ADDR)); + } + } + + void uni_ldr( + const Xbyak_aarch64::VReg &dst, const Xbyak_aarch64::XReg &addr) { + ldr(Xbyak_aarch64::QReg(dst.getIdx()), ptr(addr)); + } + + void uni_ldr( + const Xbyak_aarch64::ZReg &dst, const Xbyak_aarch64::XReg &addr) { + ldr(dst, ptr(addr)); + } + + template + void uni_ldr(const Xbyak_aarch64::ZReg &r, const Xbyak_aarch64::XReg &base, + const T off) { + const int off_mod = off % cpu_sveLen; + const int off_mul_vl = off / cpu_sveLen; + + if (off_mod == 0 && -256 <= off_mul_vl && off_mul_vl <= 255) { + ldr(r, Xbyak_aarch64::ptr(base, off_mul_vl, Xbyak_aarch64::MUL_VL)); + } else { + const int offset = off_mod * 0x10 * (cpu_sveLen / 16); + add_imm(X_DEFAULT_ADDR, base, offset, X_TMP_0); + ldr(r, Xbyak_aarch64::ptr(X_DEFAULT_ADDR)); + } + } + + template + void uni_ldr(const Xbyak_aarch64::VReg &r, const Xbyak_aarch64::XReg &base, + const T off) { + const int off_mod = off % 16; + const int off_mul_vl = off / 16; + + if (off_mod == 0 && 0 <= off_mul_vl && off_mul_vl <= 65520) { + ldr(Xbyak_aarch64::QReg(r.getIdx()), Xbyak_aarch64::ptr(base, off)); + } else { + add_imm(X_DEFAULT_ADDR, base, off_mod * 4, X_TMP_0); + ldr(Xbyak_aarch64::QReg(r.getIdx()), + Xbyak_aarch64::ptr(X_DEFAULT_ADDR)); + } + } + + void uni_orr(const Xbyak_aarch64::VReg &d, const Xbyak_aarch64::VReg &s0, + const Xbyak_aarch64::VReg &s1) { + orr(d.b16, s0.b16, s1.b16); + } + + void uni_orr(const Xbyak_aarch64::ZReg &d, const Xbyak_aarch64::ZReg &s0, + const Xbyak_aarch64::ZReg &s1) { + orr(d.d, s0.d, s1.d); + } + + void uni_scvtf( + const Xbyak_aarch64::VReg4S &t0, const Xbyak_aarch64::VReg4S &t1) { + scvtf(t0, t1); + } + + void uni_scvtf( + const Xbyak_aarch64::ZRegS &t0, const Xbyak_aarch64::ZRegS &t1) { + scvtf(t0, P_ALL_ONE / Xbyak_aarch64::T_m, t1); + } + + void uni_str( + const Xbyak_aarch64::VReg &src, const Xbyak_aarch64::XReg &addr) { + str(Xbyak_aarch64::QReg(src.getIdx()), ptr(addr)); + } + + void uni_str( + const Xbyak_aarch64::ZReg &src, const Xbyak_aarch64::XReg &addr) { + str(src, ptr(addr)); + } + + template + void uni_sub(const T &x1, const T &x2, const T &op) { + sub(x1, x2, op); + } + + /* + Saturation facility functions. enable to prepare the register + holding the saturation upperbound and apply the saturation on + the floating point register + */ + template + void init_vmm(Vmm vmm, Xbyak_aarch64::XReg reg_tmp, float value) { + using namespace data_type; + bool isSVE = get_sve_length() ? true : false; + Xbyak_aarch64::ZRegS z_tmp(vmm.getIdx()); + Xbyak_aarch64::VReg4S v_tmp(vmm.getIdx()); + Xbyak_aarch64::WReg w_tmp(reg_tmp.getIdx()); + mov_imm(w_tmp, float2int(value)); + if (isSVE) /* SVE is available. */ + dup(z_tmp, w_tmp); + else + dup(v_tmp, w_tmp); + } + + template + void init_saturate_f32(Vmm vmm_lbound, Vmm vmm_ubound, + Xbyak_aarch64::XReg reg_tmp, data_type_t idt, data_type_t odt, + bool force_lbound = false) { + using namespace data_type; + bool isSVE = get_sve_length() ? true : false; + + if (!((idt == f32) && utils::one_of(odt, u8, data_type::s8, s32))) + return; + + assert(IMPLICATION( + idt == u8, vmm_lbound.getIdx() != vmm_ubound.getIdx())); + // No need to saturate on lower bound for signed integer types, as + // the conversion to int would return INT_MIN, and then proper + // saturation will happen in store_data. The param force_lbound, will + // force saturate values unconditionally to lbound. + if (odt == u8) { + if (isSVE) /* SVE is available. */ + dup(Xbyak_aarch64::ZRegS(vmm_lbound.getIdx()), 0); + else if (mayiuse(asimd)) + movi(Xbyak_aarch64::VReg4S(vmm_lbound.getIdx()), 0); + else + assert(!"unreachable"); + } else if (force_lbound) { + const float saturation_lbound + = odt == data_type::s8 ? INT8_MIN : INT32_MIN; + init_vmm(vmm_lbound, reg_tmp, saturation_lbound); + } + + float saturation_ubound = types::max_value(odt); + init_vmm(vmm_ubound, reg_tmp, saturation_ubound); + } + + template + void saturate_f32(const Vmm &vmm, const Vmm &vmm_lbound, + const Vmm &vmm_ubound, data_type_t odt, + const Xbyak_aarch64::PReg &p_true, bool force_lbound = false) { + // This function is used to saturate to odt in f32 before converting + // to s32 in order to avoid bad saturation due to cvtps2dq + // behavior (it returns INT_MIN if the f32 is out of the + // s32 range) + using namespace data_type; + bool isSVE = get_sve_length() ? true : false; + + if (!utils::one_of(odt, u8, data_type::s8, s32)) return; + + Xbyak_aarch64::VReg4S v_tmp(vmm.getIdx()); + Xbyak_aarch64::VReg4S v_lbound(vmm_lbound.getIdx()); + Xbyak_aarch64::VReg4S v_ubound(vmm_ubound.getIdx()); + Xbyak_aarch64::ZRegS z_tmp(vmm.getIdx()); + Xbyak_aarch64::ZRegS z_lbound(vmm_lbound.getIdx()); + Xbyak_aarch64::ZRegS z_ubound(vmm_ubound.getIdx()); + + // no need to apply lower saturation bound when odt is + // signed, as cvtps2dq will return MIN_INT if the value + // does not fit. The param force_lbound, will force saturate values + // unconditionally to lbound. + if (odt == u8 || force_lbound) { + if (isSVE) /* SVE is available. */ + fmax(z_tmp, p_true / Xbyak_aarch64::T_m, z_lbound); + else if (mayiuse(asimd)) + fmax(v_tmp, v_tmp, v_lbound); + else + assert(!"unreachable"); + } + if (isSVE) /* SVE is available. */ + fmin(z_tmp, p_true / Xbyak_aarch64::T_m, z_ubound); + else if (mayiuse(asimd)) + fmin(v_tmp, v_tmp, v_ubound); + else + assert(!"unreachable"); + } + + /* A utility function to process f32 tail (load, store or other) depending + * on tail size, stored in Reg64. Tail size must be value from 0 to 3/7 + * (Xmm/Ymm). Tail process functions require integer as argument to specify + * behavior for each tail size. + * + * Only supported for Xmm and Ymm. + */ + template + void runtime_tail_process(const Xbyak_aarch64::XReg ®_tail, + const Xbyak_aarch64::XReg ®_tmp, + const std::function &tail_process) { + constexpr int simd_w_ymm = 8; + constexpr int f32_bits = sizeof(float) * 8; + const auto simd_w = cpu_isa_traits::vlen * 8 / f32_bits; + assert(simd_w != cpu_isa_traits::vlen * 8 / f32_bits); + + Xbyak_aarch64::Label label_tbl, label_tbl_end; + Xbyak_aarch64::Label l_case[simd_w_ymm]; + + adr(reg_tmp, label_tbl); + mov_imm(X_TMP_0, sizeof(void *)); + madd(X_DEFAULT_ADDR, reg_tail, X_TMP_0, reg_tmp); + br(X_DEFAULT_ADDR); + + // create jump table + L(label_tbl); + for (size_t i = 0; i < simd_w; i++) + putL(l_case[i]); + + // cases for each tail size - from 0 to 3/7 + L(l_case[0]); + b(label_tbl_end); + for (size_t i = 1; i < simd_w; i++) { + L(l_case[i]); + tail_process(i); + b(label_tbl_end); + } + L(label_tbl_end); + } + + DNNL_DISALLOW_COPY_AND_ASSIGN(jit_generator); + +public: + jit_generator(void *code_ptr = nullptr, size_t code_size = MAX_CODE_SIZE, + bool use_autogrow = true) + : Xbyak_aarch64::CodeGenerator(code_size, + (code_ptr == nullptr && use_autogrow) ? Xbyak_aarch64::AutoGrow + : code_ptr) {} + virtual ~jit_generator() {} + + virtual const char *name() const = 0; + virtual const char *source_file() const = 0; + + void register_jit_code(const uint8_t *code, size_t code_size) const { + jit_utils::register_jit_code(code, code_size, name(), source_file()); + } + + const uint8_t *jit_ker() const { return jit_ker_; } + + template + void operator()(kernel_args_t... args) const { + using jit_kernel_func_t = void (*)(const kernel_args_t... args); + auto *fptr = (jit_kernel_func_t)jit_ker_; + (*fptr)(std::forward(args)...); + } + + virtual status_t create_kernel() { + generate(); + jit_ker_ = getCode(); + return (jit_ker_) ? status::success : status::runtime_error; + } + +private: + const uint8_t *getCode() { + this->ready(); + if (!is_initialized()) return nullptr; + const uint8_t *code + = reinterpret_cast(CodeGenerator::getCode()); + register_jit_code(code, getSize() * CSIZE); + return code; + } + + static inline bool is_initialized() { + /* At the moment, Xbyak_aarch64 does not have GetError()\ + so that return dummy result. */ + return true; + } + +protected: + virtual void generate() = 0; + const uint8_t *jit_ker_ = nullptr; +}; + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_op_imm_check.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_op_imm_check.hpp new file mode 100644 index 0000000000000000000000000000000000000000..a4e3d600129c579b766811b53037a30cd74e5c83 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_op_imm_check.hpp @@ -0,0 +1,97 @@ +/******************************************************************************* +* Copyright 2020-2021 FUJITSU LIMITED +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef JIT_OP_IMM_CHECK_HPP +#define JIT_OP_IMM_CHECK_HPP + +#define LDRMAX 255 +#define LDRMIN (-256) +#define STRMAX 255 +#define STRMIN (-256) +#define LD1RWMAX 252 +#define PRFMMAX 32760 +#define PRFMMIN 0 +#define PRFWMAX 31 +#define PRFWMIN (-32) + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +// Check the immediate value for LDR(vector) instruction +// +// The imm9 in the LDR instruction is the optional signed immediate vector +// offset, in the range -256 to 255, defaulting to 0. +template +bool ldr_imm_check(T ofs) { + int vlen = cpu_isa_traits::vlen; + int vlen_shift = cpu_isa_traits::vlen_shift; + int shifted_ofs = ofs >> vlen_shift; + return ((shifted_ofs) <= LDRMAX) && (shifted_ofs >= LDRMIN) + && ((ofs % vlen) == 0); +} + +// Check the immediate value for SDR(vector) instruction +// +// The imm9 in the STR instruction is the optional signed immediate vector +// offset, in the range -256 to 255, defaulting to 0. +template +bool str_imm_check(T ofs) { + int vlen = cpu_isa_traits::vlen; + int vlen_shift = cpu_isa_traits::vlen_shift; + int shifted_ofs = ofs >> vlen_shift; + return ((shifted_ofs) <= STRMAX) && (shifted_ofs >= STRMIN) + && ((ofs % vlen) == 0); +} + +// Check the immediate value for LD1RW instruction +// +// The imm6 in the LD1RW instruction is the optional unsigned immediate byte +// offset, a multiple of 4 in the range 0 to 252, defaulting to 0. +template +bool ld1rw_imm_check(T ofs) { + return ((ofs & 0x3) == 0) && (ofs <= LD1RWMAX) && (ofs >= 0); +} + +// Check the immediate value for PRFM(immediate) instruction +// +// The pimm in the PRFM instruction is the optional positive immediate byte +// offset, a multiple of 8 in the range 0 to 32760, defaulting to 0. +template +bool prfm_imm_check(T ofs) { + return (ofs <= PRFMMAX) && (ofs >= PRFMMIN) && ((ofs & 0x7) == 0); +} + +// Check the immediate value for PRFW(scalar plus immediate) instruction +// +// The imm6 in the PRFW instruction is the optional signed immediate vector +// offset, in the range -32 to 31, defaulting to 0. +template +bool prfw_imm_check(T ofs) { + int vlen = cpu_isa_traits::vlen; + int vlen_shift = cpu_isa_traits::vlen_shift; + int shifted_ofs = ofs >> vlen_shift; + + return (shifted_ofs <= PRFWMAX) && (shifted_ofs >= PRFWMIN) + && ((ofs % vlen) == 0); +} + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_primitive_conf.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_primitive_conf.hpp new file mode 100644 index 0000000000000000000000000000000000000000..085f7941c463494b1549e0d859e4a497f3ef1320 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_primitive_conf.hpp @@ -0,0 +1,581 @@ +/******************************************************************************* +* Copyright 2016-2022 Intel Corporation +* Copyright 2020-2022 FUJITSU LIMITED +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_JIT_PRIMITIVE_CONF_HPP +#define CPU_AARCH64_JIT_PRIMITIVE_CONF_HPP + +#include + +#include "common/primitive_attr.hpp" +#include "cpu/aarch64/cpu_isa_traits.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +enum class jit_memory_tag_kind_t { ncsp, nspc, blocked, undef }; + +/* convolution */ +enum conv_version_t { + ver_unused, + ver_fma, + ver_sve_512, +}; + +enum conv_loop_order_t { + loop_cgn, + loop_gnc, + loop_ngc, + loop_gncw, + loop_cwgn, + loop_ngcw, + loop_nhwcg, + loop_nwcg +}; + +enum conv_kernel_kind_t { embd_bcast, expl_bcast }; + +enum conv_1x1_loop_order_t { + loop_rbl, + loop_rlb, + loop_lbr, + loop_lrb, + loop_blr, + loop_brl +}; + +enum conv_harness_t { + harness_2d_reduction, + harness_3d_reduction, + harness_mb_reduction, + harness_compute_full_spatial, + harness_nxc +}; + +enum { + FLAG_MB_FIRST = 1 << 0, + FLAG_MB_LAST = 1 << 1, + FLAG_OC_FIRST = 1 << 2, + FLAG_OC_LAST = 1 << 3, + FLAG_IC_FIRST = 1 << 4, + FLAG_IC_LAST = 1 << 5, + FLAG_SP_FIRST = 1 << 6, + FLAG_SP_LAST = 1 << 7, + FLAG_REDUCE_FIRST = 1 << 8, + FLAG_REDUCE_LAST = 1 << 9, + FLAG_ZERO_FILTER = 1 << 0, /* Controls whether the inner kernel skips + loading weights-data from memory; this + needs to happen on the first Group/16 + iteration. */ + FLAG_ZERO_BIAS = 1 << 1, /* Controls whether the inner kernel skip + loading bias data from memory */ + FLAG_COMPUTE_BIAS = 1 << 2, /* Controls bias computation during execution + pass */ +}; + +struct jit_conv_conf_t { + prop_kind_t prop_kind; + conv_version_t ver; + conv_loop_order_t loop_order; + conv_harness_t harness; + + int simd_w; + int ndims; + int mb; + int ngroups, ic, oc, oc_without_padding, ic_without_padding; + int id, ih, iw, od, oh, ow; + int f_pad, l_pad, t_pad; + int back_pad, r_pad, b_pad; + int kd, kh, kw; + int stride_d, stride_h, stride_w; + int dilate_d, dilate_h, dilate_w; + format_tag_t src_tag, wei_tag, dst_tag; // temporary workaround + bool with_bias; + bool with_sum; + bool with_eltwise; + bool with_binary; + + bool is_fused_conv; + int dw_conv_buffer_oc; + + post_ops_t::entry_t::eltwise_t eltwise; + post_ops_t post_ops; + + int nthr, nthr_mb, nthr_g, nthr_oc_b, nthr_ic_b; + + int idp, ihp, iwp, ohp, owp; + int nb_ic, ic_block; + int nb_oc, oc_block; + int nb_iw, iw_block; + int nb_ow, ow_block; + int nb_oc_blocking; /* used in jit kernels for nb_oc work blocking taking + into account vector registers distribution */ + int nb_oc_blocking_thr_chunk; /* used for distribution of nb_oc work + within threads */ + int nb_ic_blocking, nb_ic_blocking_max; // blocking of nb_ic work + int nb_ic_L2; + int h_blocking; + int nb_oc_L2; + int ic_tail, oc_tail; + int ur_h, ur_w; + int ur_w_tail; + int ur_ic, ur_kw; + bool is_1stconv; + int nonblk_group_off; + /* fma sve512_core */ + conv_kernel_kind_t kernel_kind; + + int tr_iw, tr_ih; + int tr_kw, tr_kh; + int tr_src_num_guard_elems; + + // Transpose buffer management + size_t tr_src_buf_size, tr_src_buf_count; + size_t tr_diff_dst_buf_size, tr_diff_dst_buf_count; + int nthr_mb_work; + + /* 1st conv */ + int tr_ld; + int kh_step; + /* sve_512_u8s8u8 */ + int typesize_in; + int typesize_out; + int typesize_bia; + int typesize_acc; + int ic_nb1, ic_nb2; + int oc_nb1; + int ur_ow_max, ur_ow, ur_ow_tail; + int ur_ow_nsteps; + data_type_t bia_dt; + /* bf16 data-type for output */ + data_type_t dst_dt; + data_type_t src_dt; + /* bf16 weights update */ + data_type_t wei_dt; + data_type_t dsrc_dt; + data_type_t dwei_dt; + bool expl_bcast; + bool large_spatial, large_w_filter; + int is_oc_scale; + int max_regs_ur; // maximum accumulation registers + // dw conv + int nb_ch, ch_block, nb_ch_blocking; + bool is_depthwise, is_fast_depthwise, is_resrc_depthwise; + int aligned_threads; + // large spatial + int h_blk_size, oh_blk_size; + // s8s8 convolution + bool signed_input; + bool need_saturation; + float wei_adj_scale; + // zero-point compensation + bool src_zero_point; + bool dst_zero_point; + bool zp_src_is_common; // common, otherwise (TODO) per-channel + + bool uses_permw_transposition; + bool transpose_src; + bool transpose_dst; + int ic_block_step; + + cpu_isa_t isa; + + bool is_hw_transp; // spatial dim height-width transposed +}; + +// calculates filter size taking into account dilation +inline int calculate_extended_filter_size(int filter_size, int dilation) { + return (filter_size - 1) * (dilation + 1) + 1; +} + +inline int calculate_end_padding(int start_padding, int dst_size, int src_size, + int spatial_stride, int dilated_filter_size) { + return (dst_size - 1) * spatial_stride + dilated_filter_size + - (src_size + start_padding); +} + +inline status_t init_tag(format_tag_t &tag, const memory_desc_wrapper &mdw, + const format_tag_t &tag_value) { + if (mdw.format_kind() == format_kind::any) return status::unimplemented; + + tag = mdw.matches_one_of_tag(tag_value); + return tag == tag_value ? status::success : status::unimplemented; +} + +struct jit_conv_call_s { + const void *src; /* hack, non-const for backward_data */ + const void *dst; /* hack, non-const for forward */ + const void *filt; /* hack, non-const for backward_weights */ + const void *bias; /* hack, non-const for backward_bias */ + const void *src_prf; + const void *dst_prf; + const void *filt_prf; + const void *bias_prf; + const void *scales; + const void *acc_s32; + const void *compensation; + const int32_t *zp_compensation; + const int32_t *src_zero_point; + const int32_t *dst_zero_point; + const void *tile_cfg; + const void *tile_cfg_tail; + + // ptr to table of void * elements that are pointers to + // post_op binary src1 tensors + const void *post_ops_binary_rhs_arg_vec; + // logical (# of elems) offset to the processed output channel + // (for broadcasting [1,OC,1,1]) + size_t oc_l_off; + const void *dst_orig; // pointer to dst memory (no offset) + + size_t oc_l_off_prf; + const void *dst_orig_prf; + + size_t kd_offset; + size_t kd_offset_prf; + size_t kh_offset; + size_t kh_offset_prf; + size_t os_index_begin; + size_t os_index_begin_prf; + size_t os_index_end; + size_t os_index_end_prf; + size_t kd_padding; + size_t kd_padding_prf; + size_t kh_padding; + size_t kh_padding_prf; + size_t iwb; + size_t iwb_prf; + size_t owb; + size_t owb_prf; + size_t kw_padding; + size_t channel; + size_t channel_prf; + size_t oc_blocks; + size_t ur_w; + size_t ur_str_w; + size_t ch_blocks; + size_t ch_blocks_prf; + size_t reduce_work; + size_t reduce_work_prf; + size_t load_work; + size_t load_work_prf; + size_t t_overflow; + size_t b_overflow; + size_t f_overflow; + size_t back_overflow; + size_t last_h; + size_t tail; + size_t current_iw; + size_t is_osb; + int flags; + int flags_prf; + int oc_flag; +}; + +struct jit_deconv_call_s { + const void *src; /* hack, non-const for backward_data */ + const void *dst; /* hack, non-const for forward */ + const void *filt; /* hack, non-const for backward_weights */ + const void *bias; /* hack, non-const for backward_bias */ + const void *scales; + const void *compensation; + const int32_t *zp_src_pad_str_compensation; + const int32_t *zp_compensation; + const int32_t *src_zero_point; + const int32_t *dst_zero_point; + + /* + * ptr to table of void * elements that are pointers to post_op binary + * src1 tensors + */ + const void *post_ops_binary_rhs_arg_vec; + const void *dst_orig; /* pointer to dst memory (no offset) */ + /* + * logical (# of elems) offset to the processed output channel + * (for broadcasting [1,OC,1,1]) + */ + size_t oc_l_off; + size_t t_overflow; + size_t b_overflow; + size_t f_overflow; + size_t back_overflow; + size_t kh_padding; + size_t kd_padding; + size_t oc_blocks; +}; + +struct jit_dw_conv_call_s { + const void *input; + const void *output; + const void *filter; + const void *bias; + size_t kh_count; + size_t oh_count; + size_t oh_index; + size_t filter_pad_off; + unsigned char + exec_flags; /* Flags passed by driver execution to inner kernel */ +}; + +struct jit_1x1_conv_conf_t { + prop_kind_t prop_kind; + conv_version_t ver; + + int ndims; + int mb; + int ngroups, ic, oc, oc_without_padding, ic_without_padding; + int id, ih, iw, od, oh, ow; + int f_pad, t_pad, l_pad; + int kd, kh, kw; + int stride_d, stride_h, stride_w; + format_tag_t src_tag, wei_tag, dst_tag; // temporary workaround + bool with_bias; + bool with_sum; + bool with_eltwise; + bool with_binary; + bool with_dw_conv; + + post_ops_t post_ops; + post_ops_t::entry_t::eltwise_t eltwise; + + int is, os; + int ic_block, oc_block; + + int ur, ur_tail; + + int reduce_dim, reduce_block, nb_reduce, nb_reduce_blocking, + nb_reduce_blocking_max; + int load_dim, load_block, nb_load, nb_load_blocking, nb_load_blocking_max, + nb_load_chunk; + int bcast_dim, bcast_block, nb_bcast, nb_bcast_blocking, + nb_bcast_blocking_max; + + int reduce_loop_unroll, reduce_loop_bcast_step, reduce_loop_load_step; + int load_loop_load_step, load_loop_iter_step; + int bcast_loop_output_step, bcast_loop_output_substep; + int bcast_loop_bcast_step, bcast_loop_bcast_substep; + int fma_step; + int load_grp_count; + conv_1x1_loop_order_t loop_order; + bool use_vmovntps; + /* sve512 core */ + bool expl_bcast; + int typesize_in; + int typesize_out; + int typesize_bia; + int typesize_acc; + /* 4fma */ + bool transpose_src; + int tr_is; + int nthr, nthr_mb, nthr_g, nthr_oc_b, nthr_ic_b; + int is_oc_scale; + data_type_t bia_dt; + data_type_t dst_dt; + bool signed_input; + float wei_adj_scale; + // zero-point compensation + bool src_zero_point; + bool dst_zero_point; + bool zp_src_is_common; // common, otherwise (TODO) per-channel + + cpu_isa_t isa; + bool uses_permw_transposition; +}; + +struct jit_1x1_conv_call_s { + const void *bcast_data; + const void *load_data; + const void *output_data; + const void *bias_data; // used in forward and backward_weights only + const void *acc_s32; + const void *scales; + const void *compensation; + const void *store_buffer; + const int32_t *zp_compensation; + const int32_t *src_zero_point; + const int32_t *dst_zero_point; + + // ptr to table of void * elements that are pointers to + // post_op binary src1 tensors + const void *post_ops_binary_rhs_arg_vec; + // logical (# of elems) offset to the processed output channel + // (for broadcasting [1,OC,1,1]) + size_t oc_l_off; + const void *dst_orig; // pointer to dst memory (not offseted) + + size_t load_dim; + size_t bcast_dim; + size_t reduce_dim; + + size_t output_stride; // used in backward_weights only + + size_t first_last_flag; +}; + +struct jit_pool_conf_t { + int ndims; + int mb, c, c_without_padding; + int id, ih, iw, od, oh, ow; + int stride_d, stride_h, stride_w; + int kd, kh, kw; + int f_pad, t_pad, l_pad; + alg_kind_t alg; + bool is_training; + bool pad_w_is_null; + bool is_backward; + bool simple_alg; + bool is_c_padded; + data_type_t ind_dt; + + int c_block, c_tail, nb_c; + int ur_bc, ur_bc_tail; + int ur_c, ur_c_tail; + int ur; + size_t tail[4]; + bool safe_c_tail; + data_type_t src_dt; + data_type_t dst_dt; + + int dt_size; + bool is_bf16; + bool is_f16; + jit_memory_tag_kind_t tag_kind; + bool is_plain() const { + return (tag_kind == jit_memory_tag_kind_t::ncsp + || tag_kind == jit_memory_tag_kind_t::nspc); + } + + cpu_isa_t isa; + post_ops_t post_ops; + bool with_postops; + bool with_eltwise; + bool with_binary; + int nthr; + memory_desc_t tmp_md; +}; + +struct jit_pool_call_s { + const void *src; + const void *dst; + const void *indices; + const void *src_prf; + const void *dst_prf; + const void *indices_prf; + const void *post_ops_binary_rhs_arg_vec; + const void *dst_orig; + const void *dst_po_helper; + size_t zero_ih; + size_t zero_id; + const void *zero_ptr; + size_t kd_padding; + size_t kh_padding; + size_t kh_padding_shift; + size_t kd_padding_shift; + size_t kw_padding; + const void *init_value; + float ker_area_h; + size_t ur_bc; // contains number of channel blocks to processing + size_t b_c; // contains number of channel blocks already processed +}; + +struct jit_shuffle_conf_t { + unsigned ndims = 0; + + unsigned mb = 0, c = 0, d = 0, h = 0, w = 0, sp = 0; + + unsigned stride_mb = 0; + unsigned blk_size = 0; + unsigned group_size = 0; + unsigned axis = 0; + unsigned axis_size = 0; + unsigned simd_tail = 0; + unsigned simd_w = 0; + + jit_memory_tag_kind_t tag_kind = jit_memory_tag_kind_t::undef; + data_type_t data_type = data_type::undef; + size_t dt_size = 0; + unsigned el_size_of_indices = 0; + dim_t c_split_size = 0; + dim_t sp_split_size = 0; + + cpu_isa_t isa = isa_undef; +}; + +struct jit_shuffle_call_s { + const void *src = nullptr; + void *dst = nullptr; + const void *input_off_ptr = nullptr; + + dim_t cb_loop_size + = 0; // number of loop iterations over corresponding C batches + bool is_padded_block = false; +}; + +enum class binary_op_t : unsigned { none, c_blocked, n_spatial_c, n_c_spatial }; + +enum class binary_bcast_t : unsigned { + none, // tensor operation + scalar, + per_batch, + per_c, + per_w +}; + +struct jit_binary_conf_t { + binary_op_t op_type = binary_op_t::none; + binary_bcast_t bcast_type = binary_bcast_t::none; + bool do_scale_src0 = false; + bool do_scale_src1 = false; + bool do_sum = false; + bool with_eltwise = false; + bool with_binary = false; + bool with_postops = false; + float sum_scale = 0.f; + bool use_stride_src1 = false; + bool broadcast_src1_value = false; + bool use_stride_rhs_postops = false; + bool postops_per_oc_broadcast_exists = false; + bool is_i8 = false; + bool is_bf16 = false; + bool is_src_different_layouts = false; + dim_t outer_dims = 1; + int src1_stride = 1; + int not_bcasted_sp_dims = 0; + cpu_isa_t isa = isa_undef; + + data_type_t src0_type = data_type::undef; + data_type_t src1_type = data_type::undef; + data_type_t dst_type = data_type::undef; +}; + +struct jit_binary_call_s { + // keep all sizes at 8 bytes -- jit code expects this + const void *src0, *src1, *dst, *indices; + const float *scales_src0, *scales_src1; + size_t spat_offt_count; + const void *post_ops_binary_rhs_arg_vec; + size_t src1_stride_range; + const void *dst_orig; +}; + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_sve_512_1x1_conv_kernel.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_sve_512_1x1_conv_kernel.hpp new file mode 100644 index 0000000000000000000000000000000000000000..2d41be54911439ff9cdaf12689e4f41bade0de0d --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_sve_512_1x1_conv_kernel.hpp @@ -0,0 +1,204 @@ +/******************************************************************************* +* Copyright 2021-2023 Intel Corporation +* Copyright 2021-2023 FUJITSU LIMITED +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_JIT_SVE_1x1_CONV_KERNEL_HPP +#define CPU_AARCH64_JIT_SVE_1x1_CONV_KERNEL_HPP + +#include "common/c_types_map.hpp" +#include "common/memory_tracking.hpp" + +#include "cpu/aarch64/injectors/jit_uni_postops_injector.hpp" +#include "cpu/aarch64/jit_generator.hpp" +#include "cpu/aarch64/jit_op_imm_check.hpp" +#include "cpu/aarch64/jit_primitive_conf.hpp" + +using namespace Xbyak_aarch64; + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +/* Get vector offsets, ofs / VL(VL: 512bits = 64Bytes) */ +#define VL64_OFS(ofs) ((ofs) >> 6) + +struct jit_sve_512_1x1_conv_kernel : public jit_generator { + jit_sve_512_1x1_conv_kernel(const jit_1x1_conv_conf_t &ajcp, + const primitive_attr_t &attr, const memory_desc_t &dst_md); + + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_sve_512_1x1_conv_kernel) + + static status_t init_conf(jit_1x1_conv_conf_t &jcp, + const convolution_desc_t &cd, const memory_desc_wrapper &src_d, + const memory_desc_wrapper &weights_d, + const memory_desc_wrapper &dst_d, const primitive_attr_t &attr, + int nthreads, bool reduce_src); + + static void init_scratchpad(memory_tracking::registrar_t &scratchpad, + const jit_1x1_conv_conf_t &jcp); + + jit_1x1_conv_conf_t jcp; + const primitive_attr_t &attr_; + +private: + using reg64_t = const XReg; + + /* Flags and loop variables */ + reg64_t reg_reduce_pos_flag = x1; + reg64_t reduce_loop_iter = x2; + reg64_t reg_bcast_loop_iter = x3; + reg64_t reg_relu_ns = x20; // For forward + reg64_t reg_output_stride = x20; // For backward + + /* Pointer */ + reg64_t reg_bcast_data = x5; // Input + reg64_t reg_load_data = x6; // Weight + reg64_t reg_output_data = x7; // Output + reg64_t reg_bias_data = x8; // bias + reg64_t aux1_reg_bcast_data = x9; + reg64_t aux_reg_output_data = x10; + reg64_t aux_reg_bcast_data = x11; + reg64_t aux_reg_load_data = x12; + reg64_t reg_prev_bcast_addr + = x13; // Input: The reg keeps addr accessed by previous ldr inst + reg64_t reg_prev_out_addr + = x14; // Output: The reg keeps addr accessed by previous ldr or str inst + + /* Workload */ + reg64_t reg_load_loop_work = x15; + reg64_t reg_reduce_loop_work = x16; + reg64_t reg_bcast_loop_work = x17; + + /* Temporay registers */ + reg64_t reg_tmp_imm = x27; // tmp for add_imm + reg64_t reg_tmp_ofs = x19; // tmp reg to calc bwd wei offset in out_load + + reg64_t reg_load_dim_tail_mask = aux_reg_load_data; + + std::unique_ptr> + postops_injector_; + + constexpr static int isa_simd_width_ + = cpu_isa_traits::vlen / sizeof(float); + + ZReg vreg_bcast = ZReg(31); + PReg k_load_dim_mask = p2; + PReg k_load_dim_tail_mask = p3; + ZReg zreg_tmp = ZReg(31); + ZReg zreg_tmp1 = ZReg(30); + + constexpr static int reg64_size_ = sizeof(int64_t); + constexpr static int reg_bcast_loop_work_offt = 0; + constexpr static int reg_binary_post_op_acc_off = 1 * reg64_size_; + constexpr static int reg_abi_param1_backup = 2 * reg64_size_; + constexpr static int stack_space_needed = 3 * reg64_size_; + + template + Xbyak_aarch64::XReg EVEX_compress_addr(const Xbyak_aarch64::XReg &addr, + const Xbyak_aarch64::XReg &x_tmp, Xbyak_aarch64::XReg base, + T raw_offt, bool bcast = false) { + + assert(raw_offt <= INT_MAX); + auto offt = static_cast(raw_offt); + + add_imm(addr, base, offt, x_tmp); + if (bcast) { + // addr is the same as addr when bcast is false. + } + return addr; + } + + void prefetch( + const std::string prfop, int level, reg64_t in, long long int ofs) { + bool for_load = false; + if (prfop == "LD") { + for_load = true; + } else if (prfop == "ST") { + for_load = false; + } else { + assert(!"invalid prfop"); + } + + bool cacheline_aligned = ((ofs & 0xFF) == 0) ? true : false; + if (cacheline_aligned == true) { + Prfop op; + switch (level) { + case 1: op = (for_load == true) ? PLDL1KEEP : PSTL1KEEP; break; + case 2: op = (for_load == true) ? PLDL2KEEP : PSTL2KEEP; break; + case 3: op = (for_load == true) ? PLDL3KEEP : PSTL3KEEP; break; + default: assert(!"invalid prfop"); break; + } + + if (prfm_imm_check(ofs)) { + prfm(op, ptr(in, static_cast(ofs))); + } else { + add_imm(reg_tmp_ofs, in, ofs, reg_tmp_imm); + prfm(op, ptr(reg_tmp_ofs)); + } + } else { + PrfopSve op_sve; + switch (level) { + case 1: + op_sve = (for_load == true) ? PLDL1KEEP_SVE : PSTL1KEEP_SVE; + break; + case 2: + op_sve = (for_load == true) ? PLDL2KEEP_SVE : PSTL2KEEP_SVE; + break; + case 3: + op_sve = (for_load == true) ? PLDL3KEEP_SVE : PSTL3KEEP_SVE; + break; + default: assert(!"invalid prfop"); break; + } + + if (prfw_imm_check(ofs)) { + prfw(op_sve, P_ALL_ONE, + ptr(in, static_cast(VL64_OFS(ofs)))); + } else { + add_imm(reg_tmp_ofs, in, ofs, reg_tmp_imm); + prfw(op_sve, P_ALL_ONE, ptr(reg_tmp_ofs)); + } + } + } + + void bcast_loop(int load_loop_blk); + void reduce_loop(int load_loop_blk, int ur, int substep, bool wraparound); + + void generate() override; + static void balance(jit_1x1_conv_conf_t &jcp); + + inline size_t get_output_offset( + const bool is_out_layout_nxc, const int i_load, const int i_ur) { + const size_t i_load_shift = is_out_layout_nxc + ? jcp.load_block + : (jcp.with_dw_conv ? jcp.ow : jcp.bcast_dim) * jcp.load_block; + const size_t i_ur_shift + = is_out_layout_nxc ? jcp.load_dim : jcp.load_block; + return jcp.typesize_out * (i_load * i_load_shift + i_ur * i_ur_shift); + } + + Xbyak_aarch64::XReg output_ptr(const bool out_layout_nxc, const int i_load, + const int i_ur, Xbyak_aarch64::XReg addr); + void apply_postops(const bool is_out_layout_nxc, const int load_loop_blk, + const int ur); +}; + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_sve_512_1x1_convolution.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_sve_512_1x1_convolution.hpp new file mode 100644 index 0000000000000000000000000000000000000000..ac7b1f2b1d1a68d7cbf4beea7e1f92f6dec3fbf9 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_sve_512_1x1_convolution.hpp @@ -0,0 +1,534 @@ +/******************************************************************************* +* Copyright 2021-2023 Intel Corporation +* Copyright 2021-2023 FUJITSU LIMITED +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_JIT_SVE_1X1_CONVOLUTION_HPP +#define CPU_AARCH64_JIT_SVE_1X1_CONVOLUTION_HPP + +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/memory_tracking.hpp" +#include "common/primitive.hpp" +#include "common/primitive_hashing.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_convolution_pd.hpp" +#include "cpu/dw_convolution_utils.hpp" +#include "cpu/platform.hpp" + +#include "cpu/aarch64/cpu_reducer.hpp" +#include "cpu/aarch64/jit_sve_512_1x1_conv_kernel.hpp" +#include "cpu/aarch64/jit_uni_1x1_conv_utils.hpp" +#include "cpu/aarch64/jit_uni_dw_convolution.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +template +struct jit_sve_512_1x1_convolution_fwd_t : public primitive_t { + struct pd_t : public cpu_convolution_fwd_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const typename pd_t::base_class *hint_fwd_pd) + : cpu_convolution_fwd_pd_t(adesc, attr, hint_fwd_pd) + , jcp_() + , rtus_() {} + pd_t(const pd_t &other) : cpu_convolution_fwd_pd_t(other) { + if (copy(other) != status::success) is_initialized_ = false; + } + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit_1x1:", sve_512, ""), + jit_sve_512_1x1_convolution_fwd_t); + + status_t init(engine_t *engine) { + using namespace utils; + + bool ok = true && is_fwd() + && set_default_alg_kind(alg_kind::convolution_direct) + && expect_data_types(src_type, wei_type, dst_type, dst_type, + data_type::undef) + && attr()->has_default_values( + primitive_attr_t::skip_mask_t::post_ops, dst_type) + && !has_zero_dim_memory() && set_default_formats() + && attr_.set_default_formats(dst_md(0)) == status::success; + if (!ok) return status::unimplemented; + + const convolution_desc_t *conv_d = desc(); + const memory_desc_t *src_d = src_md(); + rtus_prepare(this, conv_d, src_d, dst_md()); + + CHECK(jit_sve_512_1x1_conv_kernel::init_conf(jcp_, *conv_d, *src_d, + *weights_md(), *dst_md(), *attr(), dnnl_get_max_threads(), + rtus_.reduce_src_)); + if (jcp_.with_dw_conv) CHECK(depthwise_po_init(engine)); + + auto scratchpad = scratchpad_registry().registrar(); + jit_sve_512_1x1_conv_kernel::init_scratchpad(scratchpad, jcp_); + + rtus_prepare_space_info(this, scratchpad, jcp_.nthr); + + return status::success; + } + + const memory_desc_t *dst_md( + int index = 0, bool user_input = false) const override { + return jcp_.with_dw_conv + ? dw_conv_pd_->dst_md(index, user_input) + : cpu_convolution_fwd_pd_t::dst_md(index, user_input); + } + + const memory_desc_t *arg_md( + int arg, bool user_input = false) const override { + if (jcp_.with_dw_conv) { + switch (arg) { + case DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_SRC: + return cpu_convolution_fwd_pd_t::dst_md(0, user_input); + case DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_WEIGHTS: + return dw_conv_pd_->weights_md(0); + case DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_BIAS: + return dw_conv_pd_->weights_md(1); + default: break; + } + } + return convolution_fwd_pd_t::arg_md(arg, user_input); + } + + arg_usage_t arg_usage(int arg) const override { + if (arg == (DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_WEIGHTS)) + return arg_usage_t::input; + + if (arg == (DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_BIAS) + && attr_post_op_dw_inputs() > 1) + return arg_usage_t::input; + + return convolution_fwd_pd_t::arg_usage(arg); + } + + jit_1x1_conv_conf_t jcp_; + reduce_to_unit_stride_t rtus_; + using dw_pd_t = jit_sve_512_dw_convolution_fwd_t::pd_t; + std::unique_ptr dw_conv_pd_; + + protected: + bool set_default_formats() { + using namespace format_tag; + + const memory_desc_wrapper src_d(&src_md_); + const memory_desc_wrapper dst_d(&dst_md_); + + const auto dat_tag_nxc = utils::pick(ndims() - 3, nwc, nhwc, ndhwc); + const auto dat_tag_nCx16c + = utils::pick(ndims() - 3, nCw16c, nChw16c, nCdhw16c); + const auto curr_src_tag + = src_d.matches_one_of_tag(dat_tag_nxc, dat_tag_nCx16c); + const auto curr_dst_tag + = dst_d.matches_one_of_tag(dat_tag_nxc, dat_tag_nCx16c); + const auto is_data_layout_nxc + = IMPLICATION(curr_src_tag != dat_tag_nxc, + src_d.format_kind() == format_kind::any) + && IMPLICATION(curr_dst_tag != dat_tag_nxc, + dst_d.format_kind() == format_kind::any) + && utils::one_of(dat_tag_nxc, curr_src_tag, curr_dst_tag); + auto dat_tag = is_data_layout_nxc ? dat_tag_nxc : dat_tag_nCx16c; + auto wei_tag = utils::pick(2 * ndims() - 6 + with_groups(), + OIw16i16o, gOIw16i16o, OIhw16i16o, gOIhw16i16o, OIdhw16i16o, + gOIdhw16i16o); + + return set_default_formats_common(dat_tag, wei_tag, dat_tag); + } + status_t copy(const pd_t &other) { + jcp_ = other.jcp_; + rtus_ = other.rtus_; + if (other.dw_conv_pd_) { + dw_conv_pd_.reset(other.dw_conv_pd_->clone()); + if (!dw_conv_pd_) return status::out_of_memory; + } + return status::success; + } + + status_t depthwise_po_init(engine_t *engine) { + + using namespace memory_tracking; + auto &jcp_1x1 = jcp_; + primitive_attr_t attr_1x1(*attr()); + if (!attr_1x1.is_initialized()) return status::out_of_memory; + const auto &src_md = dst_md_; + const memory_desc_wrapper src_d(src_md); + const auto nthr = dnnl_get_max_threads(); + auto l2_cache = platform::get_per_core_cache_size(2) * nthr; + + // Note: A robust fusion implementation would be to check if both + // 1x1 conv and dw conv that are considered here for fusion are + // optimal independently. This would require creating a new + // primitive_desc through primitive_iterator & check if they match. + // Due to concern that these creations and/or checks could be heavy, + // for 1x1: Check that no better ISA is available. + // for dw: Always fuse with same ISA. + // Caveat: May be a better dw conv exists. + + // TODO: Add a check if better ISA exists following above note. + bool ok = true + && (attr_1x1.post_ops_.find(primitive_kind::sum) == -1) + // TODO: Below may be further tuned. + && (l2_cache * 2 < src_d.size()) + // load_grp_count check can be redundant due to l2 check + // above. Adding it explicitly as the current driver doesn't + // work if this condition fails. + && (jcp_1x1.load_grp_count < 2); + if (!ok) return status::unimplemented; + + int dw_po_index + = attr_1x1.post_ops_.find(primitive_kind::convolution); + convolution_desc_t cd_dw; + primitive_attr_t attr_dw; + CHECK(get_depthwise_conv_desc( + cd_dw, src_md, attr_1x1, attr_dw, dw_po_index)); + + CHECK(safe_ptr_assign( + dw_conv_pd_, new dw_pd_t(&cd_dw, &attr_dw, nullptr))); + CHECK(dw_conv_pd_->init(engine)); + auto &jcp_dw = dw_conv_pd_->jcp_; + + ok = true + && (dnnl_memory_desc_equal(&src_md, dw_conv_pd_->src_md(0))) + && (jcp_1x1.oc_without_padding % jcp_1x1.oc_block == 0) + && IMPLICATION( + jcp_dw.ow_block, jcp_dw.ow_block == jcp_dw.ow); + if (!ok) return status::unimplemented; + + assert(dw_conv_pd_->dst_md(0)->format_kind != format_kind::any); + assert(dw_conv_pd_->weights_md(0)->format_kind != format_kind::any); + assert(IMPLICATION( + dw_conv_pd_->weights_md(1)->data_type != data_type::undef, + dw_conv_pd_->weights_md(1)->format_kind + != format_kind::any)); + + jcp_dw.is_fused_conv = true; + // TODO: Support/experiment arbitary oc_work in dw conv. + // Until then we keep oc_work perfectly divisible. + while (jcp_1x1.nb_load % jcp_1x1.nb_load_blocking != 0) + --jcp_1x1.nb_load_blocking; + jcp_1x1.nb_load_blocking_max = jcp_1x1.nb_load_blocking; + + while (jcp_1x1.nb_load_blocking % jcp_dw.nb_ch_blocking != 0) + --jcp_dw.nb_ch_blocking; + + jcp_dw.dw_conv_buffer_oc + = jcp_1x1.nb_load_blocking * jcp_1x1.oc_block; + + const auto dat_tag_nxc = utils::pick(ndims() - 3, format_tag::nwc, + format_tag::nhwc, format_tag::ndhwc); + const bool is_data_nxc = utils::everyone_is( + dat_tag_nxc, jcp_1x1.src_tag, jcp_1x1.dst_tag); + if (!is_data_nxc) + jcp_1x1.bcast_loop_output_step = jcp_1x1.ur * jcp_1x1.load_block + * jcp_1x1.typesize_out; + + registrar_t scratchpad(scratchpad_registry_); + registrar_t dw_scratchpad(scratchpad, names::prefix_fusion); + + size_t dw_conv_buffer_size_ = (size_t)nthr * jcp_dw.kh * jcp_dw.iw + * jcp_dw.dw_conv_buffer_oc; + assert(dw_conv_buffer_size_); + dw_scratchpad.book(memory_tracking::names::key_fusion_inout_buffer, + dw_conv_buffer_size_, + types::data_type_size(dw_conv_pd_->src_md()->data_type)); + + jit_uni_dw_conv_fwd_kernel::init_scratchpad(dw_scratchpad, jcp_dw); + + return status::success; + } + }; + + template + friend status_t init_rtus_driver(conv_t *self); + + jit_sve_512_1x1_convolution_fwd_t(const pd_t *apd) : primitive_t(apd) {} + + typedef typename prec_traits::type src_data_t; + typedef typename prec_traits::type wei_data_t; + typedef typename prec_traits::type dst_data_t; + + status_t init(engine_t *engine) override { + CHECK(safe_ptr_assign(kernel_, + new jit_sve_512_1x1_conv_kernel( + pd()->jcp_, *pd()->attr(), *pd()->dst_md(0)))); + CHECK(kernel_->create_kernel()); + + if (pd()->jcp_.with_dw_conv) { + CHECK(safe_ptr_assign( + kernel_dw_, new dw_conv_kernel_t(pd()->dw_conv_pd_->jcp_))); + CHECK(kernel_dw_->create_kernel()); + } + + CHECK(init_rtus_driver(this)); + return status::success; + } + + status_t execute(const exec_ctx_t &ctx) const override { + execute_forward(ctx); + return status::success; + } + +private: + void execute_forward(const exec_ctx_t &ctx) const; + void execute_forward_thr(const int ithr, const int nthr, + const src_data_t *src, const wei_data_t *weights, + const dst_data_t *bias, const wei_data_t *weights_dw, + const dst_data_t *bias_dw, dst_data_t *dst, + const memory_tracking::grantor_t &scratchpad, + const void *post_ops_binary_rhs_arg_vec, + const void *post_ops_binary_rhs_arg_vec_dw) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr kernel_; + std::unique_ptr> rtus_driver_; + using dw_conv_kernel_t = jit_uni_dw_conv_fwd_kernel_f32; + std::unique_ptr kernel_dw_; +}; + +using jit_sve_512_1x1_convolution_fwd_f32_t + = jit_sve_512_1x1_convolution_fwd_t; + +template +struct jit_sve_512_1x1_convolution_bwd_data_t : public primitive_t { + struct pd_t : public cpu_convolution_bwd_data_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const convolution_fwd_pd_t *hint_fwd_pd) + : cpu_convolution_bwd_data_pd_t(adesc, attr, hint_fwd_pd) + , jcp_() + , rtus_() {} + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit_1x1:", sve_512, ""), + jit_sve_512_1x1_convolution_bwd_data_t); + + status_t init(engine_t *engine) { + bool ok = true && desc()->prop_kind == prop_kind::backward_data + && set_default_alg_kind(alg_kind::convolution_direct) + && expect_data_types(diff_src_type, wei_type, + data_type::undef, diff_dst_type, data_type::undef) + && attr()->has_default_values() && !has_zero_dim_memory() + && set_default_formats(); + if (!ok) return status::unimplemented; + + const convolution_desc_t *conv_d = desc(); + const memory_desc_t *diff_src_d = diff_src_md(); + rtus_prepare(this, conv_d, diff_src_d, diff_dst_md()); + + status_t status = jit_sve_512_1x1_conv_kernel::init_conf(jcp_, + *conv_d, *diff_src_d, *weights_md(), *diff_dst_md(), + *attr(), dnnl_get_max_threads(), rtus_.reduce_src_); + if (status != status::success) return status; + + auto scratchpad = scratchpad_registry().registrar(); + jit_sve_512_1x1_conv_kernel::init_scratchpad(scratchpad, jcp_); + + rtus_prepare_space_info(this, scratchpad, jcp_.nthr); + + return status::success; + } + + // TODO (Roma): structs conf header cleanup + jit_1x1_conv_conf_t jcp_; + reduce_to_unit_stride_t rtus_; + + protected: + bool set_default_formats() { + using namespace format_tag; + + const memory_desc_wrapper diff_src_d(&diff_src_md_); + const memory_desc_wrapper diff_dst_d(&diff_dst_md_); + + const auto dat_tag_nxc = utils::pick(ndims() - 3, nwc, nhwc, ndhwc); + const auto dat_tag_nCx16c + = utils::pick(ndims() - 3, nCw16c, nChw16c, nCdhw16c); + const auto curr_src_tag = diff_src_d.matches_one_of_tag( + dat_tag_nxc, dat_tag_nCx16c); + const auto curr_dst_tag = diff_dst_d.matches_one_of_tag( + dat_tag_nxc, dat_tag_nCx16c); + const auto is_data_layout_nxc + = IMPLICATION(curr_src_tag != dat_tag_nxc, + diff_src_d.format_kind() == format_kind::any) + && IMPLICATION(curr_dst_tag != dat_tag_nxc, + diff_dst_d.format_kind() == format_kind::any) + && utils::one_of(dat_tag_nxc, curr_src_tag, curr_dst_tag); + auto dat_tag = is_data_layout_nxc ? dat_tag_nxc : dat_tag_nCx16c; + auto wei_tag = utils::pick(2 * ndims() - 6 + with_groups(), + IOw16o16i, gIOw16o16i, IOhw16o16i, gIOhw16o16i, IOdhw16o16i, + gIOdhw16o16i); + + return set_default_formats_common(dat_tag, wei_tag, dat_tag); + } + }; + + template + friend status_t init_rtus_driver(conv_t *self); + + jit_sve_512_1x1_convolution_bwd_data_t(const pd_t *apd) + : primitive_t(apd) {} + + typedef typename prec_traits::type diff_dst_data_t; + typedef typename prec_traits::type wei_data_t; + typedef typename prec_traits::type diff_src_data_t; + + status_t init(engine_t *engine) override { + CHECK(safe_ptr_assign(kernel_, + new jit_sve_512_1x1_conv_kernel( + pd()->jcp_, *pd()->attr(), *pd()->dst_md(0)))); + CHECK(kernel_->create_kernel()); + CHECK(init_rtus_driver(this)); + return status::success; + } + + status_t execute(const exec_ctx_t &ctx) const override { + execute_backward_data(ctx); + return status::success; + } + +private: + void execute_backward_data(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + std::unique_ptr kernel_; + std::unique_ptr> rtus_driver_; +}; + +using jit_sve_512_1x1_convolution_bwd_data_f32_t + = jit_sve_512_1x1_convolution_bwd_data_t; + +/* Backward weight */ +struct jit_sve_512_1x1_convolution_bwd_weights_t : public primitive_t { + struct pd_t : public cpu_convolution_bwd_weights_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const convolution_fwd_pd_t *hint_fwd_pd) + : cpu_convolution_bwd_weights_pd_t(adesc, attr, hint_fwd_pd) + , jcp_() + , rtus_() {} + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit_1x1:", sve_512, ""), + jit_sve_512_1x1_convolution_bwd_weights_t); + + status_t init(engine_t *engine) { + bool ok = true && desc()->prop_kind == prop_kind::backward_weights + && set_default_alg_kind(alg_kind::convolution_direct) + && expect_data_types(data_type::f32, data_type::f32, + data_type::f32, data_type::f32, data_type::f32) + && attr()->has_default_values() && !has_zero_dim_memory() + && set_default_formats(); + if (!ok) return status::unimplemented; + + const convolution_desc_t *conv_d = desc(); + const memory_desc_t *src_d = src_md(); + rtus_prepare(this, conv_d, src_d, diff_dst_md()); + + status_t status = jit_sve_512_1x1_conv_kernel::init_conf(jcp_, + *conv_d, *src_d, *diff_weights_md(), *diff_dst_md(), + *attr(), dnnl_get_max_threads(), rtus_.reduce_src_); + if (status != status::success) return status; + + init_balancers(); + + auto scratchpad = scratchpad_registry().registrar(); + jit_sve_512_1x1_conv_kernel::init_scratchpad(scratchpad, jcp_); + + auto reducer_bia_scratchpad = memory_tracking::registrar_t( + scratchpad, memory_tracking::names::prefix_reducer_bia); + reducer_bia_conf_.init_scratchpad(reducer_bia_scratchpad); + rtus_prepare_space_info(this, scratchpad, jcp_.nthr); + + return status::success; + } + + // TODO (Roma): structs conf header cleanup + jit_1x1_conv_conf_t jcp_; + cpu_reducer_t::conf_t reducer_bia_conf_; + reduce_to_unit_stride_t rtus_; + + protected: + bool set_default_formats() { + using namespace format_tag; + + const memory_desc_wrapper src_d(&src_md_); + const memory_desc_wrapper diff_dst_d(&diff_dst_md_); + + const auto dat_tag_nxc = utils::pick(ndims() - 3, nwc, nhwc, ndhwc); + const auto dat_tag_nCx16c + = utils::pick(ndims() - 3, nCw16c, nChw16c, nCdhw16c); + const auto curr_src_tag + = src_d.matches_one_of_tag(dat_tag_nxc, dat_tag_nCx16c); + const auto curr_dst_tag = diff_dst_d.matches_one_of_tag( + dat_tag_nxc, dat_tag_nCx16c); + const auto is_data_layout_nxc + = IMPLICATION(curr_src_tag != dat_tag_nxc, + src_d.format_kind() == format_kind::any) + && IMPLICATION(curr_dst_tag != dat_tag_nxc, + diff_dst_d.format_kind() == format_kind::any) + && utils::one_of(dat_tag_nxc, curr_src_tag, curr_dst_tag); + + auto dat_tag = is_data_layout_nxc ? dat_tag_nxc : dat_tag_nCx16c; + auto wei_tag = utils::pick(2 * ndims() - 6 + with_groups(), + OIw16i16o, gOIw16i16o, OIhw16i16o, gOIhw16i16o, OIdhw16i16o, + gOIdhw16i16o); + + return set_default_formats_common(dat_tag, wei_tag, dat_tag); + } + + private: + void init_balancers() { + const size_t max_buffer_size = jcp_.nthr * 3 * 5 * 5 * 16 * 16; + if (with_bias()) { + reducer_bia_conf_.init(reduce_balancer_t(jcp_.nthr, + jcp_.oc_block, jcp_.ngroups * jcp_.nb_load, jcp_.mb, + max_buffer_size, true)); + } + } + }; + + template + friend status_t init_rtus_driver(conv_t *self); + + jit_sve_512_1x1_convolution_bwd_weights_t(const pd_t *apd) + : primitive_t(apd) {} + + typedef typename prec_traits::type data_t; + + status_t init(engine_t *engine) override; + + status_t execute(const exec_ctx_t &ctx) const override { + execute_backward_weights(ctx); + return status::success; + } + +private: + void execute_backward_weights(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr kernel_; + std::unique_ptr> acc_ker_; + std::unique_ptr> reducer_bias_; + // std::unique_ptr trans_kernel_; + std::unique_ptr> rtus_driver_; +}; + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_sve_512_conv_kernel.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_sve_512_conv_kernel.hpp new file mode 100644 index 0000000000000000000000000000000000000000..525024c691a6ec1417f6180b5a23f32a9d6fc0d6 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_sve_512_conv_kernel.hpp @@ -0,0 +1,602 @@ +/******************************************************************************* +* Copyright 2020-2022 Intel Corporation +* Copyright 2020-2022 FUJITSU LIMITED +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_JIT_SVE_CONV_KERNEL_HPP +#define CPU_AARCH64_JIT_SVE_CONV_KERNEL_HPP + +#include "common/c_types_map.hpp" +#include "common/memory_tracking.hpp" + +#include "cpu/aarch64/jit_generator.hpp" +#include "cpu/aarch64/jit_primitive_conf.hpp" + +#include "cpu/aarch64/injectors/jit_uni_eltwise_injector.hpp" + +#include "cpu/aarch64/jit_op_imm_check.hpp" + +#define LDRWMAX 252 +#define ADDMAX 4095 +/* Get vector offsets, ofs / VL(VL: 512bits = 64Bytes) */ +#define VL_OFS(ofs) ((ofs) >> 6) + +using namespace Xbyak_aarch64; + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +struct jit_sve_512_conv_fwd_kernel : public jit_generator { + + jit_sve_512_conv_fwd_kernel( + const jit_conv_conf_t &ajcp, const primitive_attr_t &attr) + : jcp(ajcp), attr_(attr), eltwise_injector_(nullptr) { + + if (jcp.with_eltwise) + eltwise_injector_ = new jit_uni_eltwise_injector_f32( + this, jcp.eltwise); + } + + ~jit_sve_512_conv_fwd_kernel() { delete eltwise_injector_; } + + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_sve_512_conv_fwd_kernel) + + jit_conv_conf_t jcp; + const primitive_attr_t &attr_; + + static bool post_ops_ok(jit_conv_conf_t &jcp, const primitive_attr_t &attr); + static status_t init_conf(jit_conv_conf_t &jcp, + const convolution_desc_t &cd, memory_desc_t &src_pd, + memory_desc_t &weights_pd, memory_desc_t &dst_pd, + memory_desc_t &bias_pd, const primitive_attr_t &attr, int nthreads); + static void init_scratchpad(memory_tracking::registrar_t &scratchpad, + const jit_conv_conf_t &jcp); + +private: + using reg64_t = const XReg; + enum { + typesize = sizeof(float), + ker_reg_base_idx = 28, + }; + + reg64_t param = abi_param1; + reg64_t reg_inp = x1; // src base addr (2d) + reg64_t reg_ker = x2; // ker base addr (2d) + reg64_t aux_reg_ker_d = x2; // ker addr (3d) + reg64_t reg_out = x3; // dst base addr (2d) + reg64_t reg_ki = x3; // d-dim loop var? (3d) + reg64_t reg_owb = x5; // num of ow-block + reg64_t reg_out_prf = x6; // addr for prefetch + + reg64_t aux_reg_inp = x7; // src addr (main loop) + reg64_t aux_reg_inp2 = x24; // src addr (main loop) + reg64_t aux_reg_inp3 = x25; // src addr (main loop) + reg64_t reg_out_ofs = x7; // dst addr (store_output) + reg64_t aux_reg_ker = x8; // ker addr (main loop) + reg64_t reg_channel = x9; // reduce workload + reg64_t reg_bias = x10; // bias addr (prepare_out) + + reg64_t aux_reg_inp_d = x11; // src addr (3d) + reg64_t reg_oi = x11; + + reg64_t reg_kh = x12; // ker h size + reg64_t reg_kj = x13; // ker h workload + + /* Temporary registers for ARM insts */ + reg64_t reg_tmp_addr = x14; + reg64_t reg_prev_bcast_addr = x15; + reg64_t reg_prev_wei_addr = x16; + reg64_t reg_tmp_imm = x17; + + reg64_t reg_out_org = x27; // dst base addr (3d) + reg64_t reg_oi_org = x19; // base oi (3d) + reg64_t aux_reg_ker_d_org = x20; + reg64_t reg_ker_org = x21; // ker base addr (3d) + reg64_t reg_inp_org = x29; // src base addr (3d) + + void prefetch( + const std::string prfop, int level, reg64_t in, long long int ofs) { + bool for_load = false; + if (prfop == "LD") { + for_load = true; + } else if (prfop == "ST") { + for_load = false; + } else { + assert(!"invalid prfop"); + } + + bool cacheline_aligned = ((ofs & 0xFF) == 0) ? true : false; + if (cacheline_aligned == true) { + Prfop op = PLDL1KEEP; + switch (level) { + case 1: op = (for_load == true) ? PLDL1KEEP : PSTL1KEEP; break; + case 2: op = (for_load == true) ? PLDL2KEEP : PSTL2KEEP; break; + case 3: op = (for_load == true) ? PLDL3KEEP : PSTL3KEEP; break; + default: assert(!"invalid prfop"); break; + } + + if ((ofs <= PRFMMAX) && (ofs >= 0)) { + prfm(op, ptr(in, static_cast(ofs))); + } else { + add_imm(reg_tmp_addr, in, ofs, reg_tmp_imm); + prfm(op, ptr(reg_tmp_addr)); + } + } else { + PrfopSve op_sve = PLDL1KEEP_SVE; + switch (level) { + case 1: + op_sve = (for_load == true) ? PLDL1KEEP_SVE : PSTL1KEEP_SVE; + break; + case 2: + op_sve = (for_load == true) ? PLDL2KEEP_SVE : PSTL2KEEP_SVE; + break; + case 3: + op_sve = (for_load == true) ? PLDL3KEEP_SVE : PSTL3KEEP_SVE; + break; + default: assert(!"invalid level"); break; + } + + if ((VL_OFS(ofs) <= PRFWMAX) + && (VL_OFS(ofs) >= (-1 * PRFWMAX - 1))) { + prfw(op_sve, P_ALL_ONE, + ptr(in, static_cast(VL_OFS(ofs)))); + } else { + add_imm(reg_tmp_addr, in, ofs, reg_tmp_imm); + prfw(op_sve, P_ALL_ONE, ptr(reg_tmp_addr)); + } + } + } + + jit_uni_eltwise_injector_f32 *eltwise_injector_; + + inline void prepare_output(int ur_w); + inline void store_output(int ur_w); + inline void compute_loop_fma_core(int ur_w, int pad_l, int pad_r); + inline void compute_loop(int ur_w, int pad_l, int pad_r); + + void generate() override; + + inline size_t get_output_offset(int oi, int n_oc_block) { + const bool is_nxc_layout = is_dst_layout_nxc(); + size_t ow_str = is_nxc_layout ? jcp.ngroups * jcp.oc : jcp.oc_block; + size_t ocb_str = is_nxc_layout + ? jcp.oc_block + : (size_t)jcp.od * jcp.oh * jcp.ow * jcp.oc_block; + + return jcp.typesize_out * (n_oc_block * ocb_str + oi * ow_str); + } + + inline size_t get_input_offset(int ki, int ic, int oi, int pad_l) { + const bool is_nxc_layout = is_src_layout_nxc(); + size_t iw_str = is_nxc_layout ? jcp.ngroups * jcp.ic + : (!jcp.is_1stconv ? jcp.ic_block : 1); + size_t ic_str = !jcp.is_1stconv || is_nxc_layout + ? 1 + : (size_t)jcp.iw * jcp.ih * jcp.id; + size_t iw_idx = ki * (jcp.dilate_w + 1) + oi * jcp.stride_w - pad_l; + + return jcp.typesize_in * (iw_idx * iw_str + ic * ic_str); + } + + inline int get_kernel_offset( + int ki, int ic, int n_oc_block, int ker_number) { + return jcp.typesize_in * jcp.oc_block + * (n_oc_block * jcp.nb_ic * jcp.ic_block * jcp.kh * jcp.kw + * jcp.kd + + (ic + ker_number) + ki * jcp.ic_block); + } + + inline int get_ow_start(int ki, int pad_l) { + return nstl::max(0, + utils::div_up(pad_l - ki * (jcp.dilate_w + 1), jcp.stride_w)); + } + + inline int get_ow_end(int ur_w, int ki, int pad_r) { + return ur_w + - nstl::max(0, + utils::div_up( + pad_r - (jcp.kw - 1 - ki) * (jcp.dilate_w + 1), + jcp.stride_w)); + } + inline bool is_src_layout_nxc() { + return utils::one_of(jcp.src_tag, format_tag::ndhwc, format_tag::nhwc, + format_tag::nwc); + } + inline bool is_dst_layout_nxc() { + return utils::one_of(jcp.dst_tag, format_tag::ndhwc, format_tag::nhwc, + format_tag::nwc); + } +}; + +struct jit_sve_512_conv_bwd_data_kernel_f32 : public jit_generator { + + jit_sve_512_conv_bwd_data_kernel_f32(const jit_conv_conf_t &ajcp) + : jcp(ajcp) {} + + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_sve_512_conv_bwd_data_kernel_f32) + jit_conv_conf_t jcp; + void (*jit_ker_)(jit_conv_call_s *); + + static status_t init_conf(jit_conv_conf_t &jcp, + const convolution_desc_t &cd, memory_desc_t &diff_src_d, + memory_desc_t &weights_d, memory_desc_t &diff_dst_d, int nthreads); + static void init_scratchpad(memory_tracking::registrar_t &scratchpad, + const jit_conv_conf_t &jcp); + +private: + using reg64_t = const XReg; + enum { + typesize = sizeof(float), + }; + int ker_reg_base_idx = (jcp.nb_ic_blocking == 1) ? 16 : 24; + + reg64_t param = abi_param1; + reg64_t reg_dst = x1; + reg64_t reg_ker = x2; + reg64_t reg_src = x3; + + reg64_t reg_dst_prf = x23; + reg64_t reg_ker_prf = x5; + reg64_t reg_src_prf = x6; + reg64_t reg_iwb = x24; + + reg64_t aux_reg_dst = x7; + reg64_t aux_reg_ker = x8; + + reg64_t aux_reg_dst_prf = x9; + reg64_t aux_reg_ker_prf = x10; + + reg64_t aux_reg_dst_d_prf = x6; + reg64_t aux_reg_dst_d = x11; + reg64_t aux_reg_ker_d_prf = x12; + reg64_t aux_reg_ker_d = x2; + reg64_t reg_ki = x3; + + reg64_t reg_kj = x13; + reg64_t reg_oi = x11; + reg64_t reg_kh = x12; + + reg64_t reg_channel = x9; + + reg64_t reg_tmp = x14; + reg64_t reg_long_offt = x7; + + /* Temporary registers for ARM insts */ + reg64_t reg_prev_bcast_addr = x15; + reg64_t reg_prev_bcast_addr2 = x17; + reg64_t reg_prev_bcast_addr3 = x21; + reg64_t reg_tmp_imm = x16; + reg64_t reg_tmp_addr = x27; + + reg64_t reg_src_prf_org = x19; + reg64_t reg_src_org = x20; + reg64_t reg_oi_org = x25; + reg64_t reg_dst_org = x22; + reg64_t reg_ker_org = x26; + reg64_t reg_input_org = x22; + reg64_t reg_kernel_org = x26; + + long long int prefetch(const std::string prfop, int level, reg64_t in, + long long int ofs, long long int prev_ofs) { + bool for_load = false; + if (prfop == "LD") { + for_load = true; + } else if (prfop == "ST") { + for_load = false; + } else { + assert(!"invalid prfop"); + } + + bool cacheline_aligned = ((ofs & 0xFF) == 0) ? true : false; + if (cacheline_aligned == true) { + Prfop op = PLDL1KEEP; + switch (level) { + case 1: op = (for_load == true) ? PLDL1KEEP : PSTL1KEEP; break; + case 2: op = (for_load == true) ? PLDL2KEEP : PSTL2KEEP; break; + case 3: op = (for_load == true) ? PLDL3KEEP : PSTL3KEEP; break; + default: assert(!"invalid prfop"); break; + } + + long long int tmp_ofs = ofs - prev_ofs; + if ((ofs <= PRFMMAX) && (ofs >= 0)) { + prfm(op, ptr(in, static_cast(ofs))); + } else if ((tmp_ofs <= PRFMMAX) && (tmp_ofs >= 0)) { + prfm(op, ptr(reg_tmp_addr, static_cast(tmp_ofs))); + } else { + add_imm(reg_tmp_addr, in, ofs, reg_tmp_imm); + prfm(op, ptr(reg_tmp_addr)); + prev_ofs = ofs; + } + } else { + PrfopSve op_sve = PLDL1KEEP_SVE; + switch (level) { + case 1: + op_sve = (for_load == true) ? PLDL1KEEP_SVE : PSTL1KEEP_SVE; + break; + case 2: + op_sve = (for_load == true) ? PLDL2KEEP_SVE : PSTL2KEEP_SVE; + break; + case 3: + op_sve = (for_load == true) ? PLDL3KEEP_SVE : PSTL3KEEP_SVE; + break; + default: assert(!"invalid prfop"); break; + } + + long long int tmp_ofs = ofs - prev_ofs; + if ((VL_OFS(ofs) <= PRFWMAX) + && (VL_OFS(ofs) >= (-1 * PRFWMAX - 1))) { + prfw(op_sve, P_ALL_ONE, + ptr(in, static_cast(VL_OFS(ofs)))); + } else if ((VL_OFS(tmp_ofs) <= PRFWMAX) + && (VL_OFS(tmp_ofs) >= (-1 * PRFWMAX - 1))) { + prfw(op_sve, P_ALL_ONE, + ptr(reg_tmp_addr, + static_cast(VL_OFS(tmp_ofs)))); + } else { + add_imm(reg_tmp_addr, in, ofs, reg_tmp_imm); + prfw(op_sve, P_ALL_ONE, ptr(reg_tmp_addr)); + prev_ofs = ofs; + } + } + return prev_ofs; + } + + ZReg reg_wei = ZReg(31); + + inline void prepare_output(int ur_w); + inline void store_output(int ur_w); + inline void compute_loop_fma(int ur_w, int l_overflow, int r_overflow); + inline void compute_loop_fma_core( + int ur_w, int l_overflow, int r_overflow, int k_offset); + inline void compute_loop( + int ur_w, int l_overflow, int r_overflow, int k_offset = 0); + void generate() override; + + inline int get_iw_start(int ki, int l_overflow) { + int res = (jcp.iw - 1 + jcp.r_pad) % jcp.stride_w + + l_overflow * jcp.stride_w + - (jcp.kw - 1 - ki) * (jcp.dilate_w + 1); + while (res < 0) + res += jcp.stride_w; + + return res; + } + + inline int get_iw_end(int ur_w, int ki, int r_overflow) { + if (utils::one_of(ur_w, jcp.iw, jcp.ur_w_tail)) + ur_w += nstl::min(0, jcp.r_pad); // remove negative padding + int res = (ur_w - 1 + jcp.l_pad) % jcp.stride_w + + r_overflow * jcp.stride_w - ki * (jcp.dilate_w + 1); + while (res < 0) + res += jcp.stride_w; + + return ur_w - res; + } + + inline size_t get_diff_src_offset(int iw, int icb) { + const bool is_nxc_layout = is_dsrc_layout_nxc(); + size_t iw_str = is_nxc_layout ? jcp.ngroups * jcp.ic : jcp.ic_block; + size_t icb_str = is_nxc_layout + ? jcp.ic_block + : (size_t)jcp.id * jcp.ih * jcp.iw * jcp.ic_block; + + return typesize * (icb * icb_str + iw * iw_str); + } + + inline ptrdiff_t get_dst_offset(int iw, int oc, int kw) { + ptrdiff_t ow + = (iw + jcp.l_pad - kw * (jcp.dilate_w + 1)) / jcp.stride_w; + ptrdiff_t ow_str + = is_ddst_layout_nxc() ? jcp.ngroups * jcp.oc : jcp.oc_block; + + return typesize * (ow * ow_str + oc); + }; + + inline bool is_dsrc_layout_nxc() { + return utils::one_of(jcp.src_tag, format_tag::ndhwc, format_tag::nhwc, + format_tag::nwc); + } + inline bool is_ddst_layout_nxc() { + return utils::one_of(jcp.dst_tag, format_tag::ndhwc, format_tag::nhwc, + format_tag::nwc); + } +}; + +struct jit_sve_512_conv_bwd_weights_kernel_f32 : public jit_generator { + + jit_sve_512_conv_bwd_weights_kernel_f32(const jit_conv_conf_t &ajcp) + : jcp(ajcp) {} + + void generate() override { + if (jcp.harness != harness_nxc) { + generate_kernel(); + } else { + assert(!"none microkernel"); + } + } + + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_sve_512_conv_bwd_weights_kernel_f32) + + static status_t init_conf(jit_conv_conf_t &jcp, + const convolution_desc_t &cd, memory_desc_t &src_md, + memory_desc_t &diff_weights_md, memory_desc_t &diff_bias_md, + memory_desc_t &diff_dst_md, int nthreads); + static void init_scratchpad(memory_tracking::registrar_t &scratchpad, + const jit_conv_conf_t &jcp); + + jit_conv_conf_t jcp; + +private: + using reg64_t = const XReg; + enum { typesize = sizeof(float) }; + static const int max_ur_w; + static const int min_oh_reduce; + + reg64_t param = abi_param1; + reg64_t reg_input = x1; + reg64_t reg_kernel = x2; + reg64_t reg_output = x3; + reg64_t b_ic = x20; + reg64_t kj = x5; + reg64_t reg_kh = x6; + reg64_t reg_ur_w_trips = x7; + reg64_t reg_oj = x8; + reg64_t reg_tmp = x10; + reg64_t reg_icb = x9; + + reg64_t ki = x11; + reg64_t reg_kd_count = x12; + reg64_t reg_oi = x12; + reg64_t reg_d_index = x13; + reg64_t reg_input_d = x8; + reg64_t reg_output_d = x9; + reg64_t aux_reg_input = x12; + reg64_t aux_reg_kernel = x13; + reg64_t reg_bias = x9; + reg64_t reg_oc_tail = x10; + + /* Temporary registers */ + reg64_t reg_add_tmp = x14; + reg64_t reg_tmp_imm = x15; + + reg64_t reg_kd_count_org = x16; + reg64_t reg_input_d_org = x17; + reg64_t reg_output_d_org = x19; + + reg64_t reg_input_org = x24; + reg64_t reg_kernel_org = x22; + reg64_t reg_output_org = x23; + + reg64_t reg_pre_addr_input = x25; + reg64_t reg_pre_addr_out = x26; + reg64_t reg_pre_addr_ker = x26; + reg64_t reg_ker_start_addr = x27; + reg64_t reg_addr_diff_input = x28; + + void prefetch( + const std::string prfop, int level, reg64_t in, long long int ofs) { + bool for_load = false; + if (prfop == "LD") { + for_load = true; + } else if (prfop == "ST") { + for_load = false; + } else { + assert(!"invalid prfop"); + } + + bool cacheline_aligned = ((ofs & 0xFF) == 0) ? true : false; + if (cacheline_aligned == true) { + Prfop op = PLDL1KEEP; + switch (level) { + case 1: op = (for_load == true) ? PLDL1KEEP : PSTL1KEEP; break; + case 2: op = (for_load == true) ? PLDL2KEEP : PSTL2KEEP; break; + case 3: op = (for_load == true) ? PLDL3KEEP : PSTL3KEEP; break; + default: assert(!"invalid prfop"); break; + } + + if ((ofs <= PRFMMAX) && (ofs >= 0)) { + prfm(op, ptr(in, static_cast(ofs))); + } else { + add_imm(reg_add_tmp, in, ofs, reg_tmp_imm); + prfm(op, ptr(reg_add_tmp)); + } + } else { + PrfopSve op_sve; + switch (level) { + case 1: + op_sve = (for_load == true) ? PLDL1KEEP_SVE : PSTL1KEEP_SVE; + break; + case 2: + op_sve = (for_load == true) ? PLDL2KEEP_SVE : PSTL2KEEP_SVE; + break; + case 3: + op_sve = (for_load == true) ? PLDL3KEEP_SVE : PSTL3KEEP_SVE; + break; + default: assert(!"invalid prfop"); break; + } + + if ((VL_OFS(ofs) <= PRFWMAX) + && (VL_OFS(ofs) >= (-1 * PRFWMAX - 1))) { + prfw(op_sve, P_ALL_ONE, + ptr(in, static_cast(VL_OFS(ofs)))); + } else { + add_imm(reg_add_tmp, in, ofs, reg_tmp_imm); + prfw(op_sve, P_ALL_ONE, ptr(reg_add_tmp)); + } + } + } + + inline void bias_kernel_2d(); + inline void bias_kernel_3d(); + inline void maybe_zero_kernel(); + inline void compute_oh_step_unroll_ow_icblock( + int ic_block_step, int max_ur_w); + inline void od_step_comeback_pointers(); + inline void oh_step_comeback_pointers(); + inline void compute_oh_step_unroll_ow(int ic_block_step, int max_ur_w); + inline void compute_ic_block_step(int ur_w, int pad_l, int pad_r, + int ic_block_step, int input_offset, int kernel_offset, + int output_offset, bool input_wraparound = false); + inline void compute_oh_step_common(int ic_block_step, int max_ur_w); + inline void compute_oh_step_disp(); + inline void compute_oh_loop_common(); + inline void compute_oh_loop_partial(); + inline void compute_od_loop_partial(); + + inline bool compute_full_spat_loop(); + inline bool flat_4ops_compute(); + + inline void compute_loop(); + inline bool is_src_layout_nxc() { + return utils::one_of(jcp.src_tag, format_tag::ndhwc, format_tag::nhwc, + format_tag::nwc); + } + inline bool is_ddst_layout_nxc() { + return utils::one_of(jcp.dst_tag, format_tag::ndhwc, format_tag::nhwc, + format_tag::nwc); + } + + inline ptrdiff_t get_full_src_offset( + int i_iw, int i_ic, ptrdiff_t input_offset) { + const bool is_nxc_layout = is_src_layout_nxc(); + const size_t w_shift_st = (jcp.is_hw_transp ? jcp.iw : 1) + * (jcp.is_1stconv ? 1 : jcp.ic_block); + ptrdiff_t w_shift = is_nxc_layout ? jcp.ngroups * jcp.ic : w_shift_st; + ptrdiff_t ic_shift = (jcp.is_1stconv && !is_nxc_layout + ? (ptrdiff_t)jcp.ih * jcp.iw * jcp.id + : 1); + + ptrdiff_t local_input_offset = i_iw * w_shift + i_ic * ic_shift; + return input_offset + typesize * local_input_offset; + }; + + inline int get_iw_idx(int ow, int kw, int l_pad) { + return ow * jcp.stride_w + kw * (jcp.dilate_w + 1) - l_pad; + } + + void generate_kernel(); + + static void balance(const jit_conv_conf_t &j, int &nthr, int &nthr_mb, + int &nthr_g, int &nthr_oc_b, int &nthr_ic_b, int nthreads); +}; + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_sve_512_convolution.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_sve_512_convolution.hpp new file mode 100644 index 0000000000000000000000000000000000000000..6b44d11f1881b0beb82ff0d3d3e577cb47773673 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_sve_512_convolution.hpp @@ -0,0 +1,274 @@ +/******************************************************************************* +* Copyright 2020-2021 Intel Corporation +* Copyright 2020-2021 FUJITSU LIMITED +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_JIT_SVE_CONVOLUTION_HPP +#define CPU_AARCH64_JIT_SVE_CONVOLUTION_HPP + +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/memory_tracking.hpp" +#include "common/primitive.hpp" +#include "common/utils.hpp" + +#include "cpu/aarch64/cpu_barrier.hpp" +#include "cpu/aarch64/cpu_reducer.hpp" +#include "cpu/cpu_convolution_pd.hpp" + +#include "cpu/aarch64/jit_sve_512_conv_kernel.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +template +struct jit_sve_512_convolution_fwd_t : public primitive_t { + struct pd_t : public cpu_convolution_fwd_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const typename pd_t::base_class *hint_fwd_pd) + : cpu_convolution_fwd_pd_t(adesc, attr, hint_fwd_pd), jcp_() {} + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit:", sve_512, ""), + jit_sve_512_convolution_fwd_t); + + status_t init(engine_t *engine) { + bool ok = true && is_fwd() + && set_default_alg_kind(alg_kind::convolution_direct) + && expect_data_types(src_type, wei_type, dst_type, dst_type, + data_type::undef) + && attr()->has_default_values( + primitive_attr_t::skip_mask_t::post_ops, dst_type) + && !has_zero_dim_memory(); + if (!ok) return status::unimplemented; + + status_t status = jit_sve_512_conv_fwd_kernel::init_conf(jcp_, + *desc(), src_md_, weights_md_, dst_md_, bias_md_, *attr(), + dnnl_get_max_threads()); + if (status != status::success) return status; + + auto scratchpad = scratchpad_registry().registrar(); + jit_sve_512_conv_fwd_kernel::init_scratchpad(scratchpad, jcp_); + + return status; + } + + jit_conv_conf_t jcp_; + }; + + jit_sve_512_convolution_fwd_t(const pd_t *apd) : primitive_t(apd) {} + + typedef typename prec_traits::type src_data_t; + typedef typename prec_traits::type wei_data_t; + typedef typename prec_traits::type dst_data_t; + + status_t init(engine_t *engine) override { + CHECK(safe_ptr_assign(kernel_, + new jit_sve_512_conv_fwd_kernel(pd()->jcp_, *pd()->attr()))); + return kernel_->create_kernel(); + } + + status_t execute(const exec_ctx_t &ctx) const override { + if (pd()->ndims() == 3) + execute_forward_1d(ctx); + else if (pd()->ndims() == 4) + execute_forward_2d(ctx); + else if (pd()->ndims() == 5) + execute_forward_3d(ctx); + else + assert(false); + + if (pd()->wants_zero_pad_dst()) ctx.zero_pad_output(DNNL_ARG_DST); + + return status::success; + } + +private: + void prepare_padded_bias(const dst_data_t *&bias, + const memory_tracking::grantor_t &scratchpad) const; + void execute_forward_1d(const exec_ctx_t &ctx) const; + void execute_forward_2d(const exec_ctx_t &ctx) const; + void execute_forward_3d(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr kernel_; +}; + +template +struct jit_sve_512_convolution_bwd_data_t : public primitive_t { + struct pd_t : public cpu_convolution_bwd_data_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const convolution_fwd_pd_t *hint_fwd_pd) + : cpu_convolution_bwd_data_pd_t(adesc, attr, hint_fwd_pd), jcp_() {} + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit:", sve_512, ""), + jit_sve_512_convolution_bwd_data_t); + + status_t init(engine_t *engine) { + bool ok = true && desc()->prop_kind == prop_kind::backward_data + && set_default_alg_kind(alg_kind::convolution_direct) + && expect_data_types(diff_src_type, wei_type, + data_type::undef, diff_dst_type, data_type::undef) + && attr()->has_default_values() && !has_zero_dim_memory(); + if (!ok) return status::unimplemented; + + status_t status = jit_sve_512_conv_bwd_data_kernel_f32::init_conf( + jcp_, *desc(), diff_src_md_, weights_md_, diff_dst_md_, + dnnl_get_max_threads()); + if (status != status::success) return status; + + auto scratchpad = scratchpad_registry().registrar(); + jit_sve_512_conv_bwd_data_kernel_f32::init_scratchpad( + scratchpad, jcp_); + + return status::success; + } + + jit_conv_conf_t jcp_; + }; + + jit_sve_512_convolution_bwd_data_t(const pd_t *apd) : primitive_t(apd) {} + + typedef typename prec_traits::type diff_dst_data_t; + typedef typename prec_traits::type wei_data_t; + typedef typename prec_traits::type diff_src_data_t; + + status_t init(engine_t *engine) override { + CHECK(safe_ptr_assign( + kernel_, new jit_sve_512_conv_bwd_data_kernel_f32(pd()->jcp_))); + return kernel_->create_kernel(); + } + + status_t execute(const exec_ctx_t &ctx) const override { + if (pd()->ndims() == 3) + execute_backward_data_1d(ctx); + else if (pd()->ndims() == 4) + execute_backward_data_2d(ctx); + else if (pd()->ndims() == 5) + execute_backward_data_3d(ctx); + else + assert(false); + return status::success; + } + +private: + void execute_backward_data_1d(const exec_ctx_t &ctx) const; + void execute_backward_data_2d(const exec_ctx_t &ctx) const; + void execute_backward_data_3d(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr kernel_; +}; + +template +struct jit_sve_512_convolution_bwd_weights_t : public primitive_t { + struct pd_t : public cpu_convolution_bwd_weights_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const convolution_fwd_pd_t *hint_fwd_pd) + : cpu_convolution_bwd_weights_pd_t(adesc, attr, hint_fwd_pd) + , jcp_() {} + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit:", sve_512, ""), + jit_sve_512_convolution_bwd_weights_t); + + status_t init(engine_t *engine) { + bool ok = true && desc()->prop_kind == prop_kind::backward_weights + && set_default_alg_kind(alg_kind::convolution_direct) + && expect_data_types(src_type, diff_weights_type, + diff_weights_type, diff_dst_type, data_type::undef) + && attr()->has_default_values() && !has_zero_dim_memory(); + if (!ok) return status::unimplemented; + + status_t status + = jit_sve_512_conv_bwd_weights_kernel_f32::init_conf(jcp_, + *desc(), src_md_, diff_weights_md_, diff_bias_md_, + diff_dst_md_, dnnl_get_max_threads()); + if (status != status::success) return status; + + init_balancers(); + + auto scratchpad = scratchpad_registry().registrar(); + jit_sve_512_conv_bwd_weights_kernel_f32::init_scratchpad( + scratchpad, jcp_); + + auto reducer_bia_scratchpad = memory_tracking::registrar_t( + scratchpad, memory_tracking::names::prefix_reducer_bia); + reducer_bia_conf_.init_scratchpad(reducer_bia_scratchpad); + + return status; + } + + jit_conv_conf_t jcp_; + typename cpu_reducer_t::conf_t reducer_bia_conf_; + + private: + void init_balancers() { + const size_t max_buffer_size = jcp_.nthr * 3 * 5 * 5 * 16 * 16; + if (with_bias()) { + reducer_bia_conf_.init(reduce_balancer_t(jcp_.nthr, + jcp_.oc_block, jcp_.ngroups * jcp_.nb_oc, jcp_.mb, + max_buffer_size, true)); + } + } + }; + + jit_sve_512_convolution_bwd_weights_t(const pd_t *apd) : primitive_t(apd) {} + + typedef typename prec_traits::type src_data_t; + typedef typename prec_traits::type diff_dst_data_t; + typedef typename prec_traits::type diff_weights_data_t; + + status_t init(engine_t *engine) override; + + status_t execute(const exec_ctx_t &ctx) const override { + execute_backward_weights(ctx); + return status::success; + } + +private: + void execute_backward_weights(const exec_ctx_t &ctx) const; + void prepare_scratchpad_data(const exec_ctx_t &ctx) const; + struct thread_info_t; + void compute_diff_weights(const thread_info_t *) const; + void compute_diff_weights_2d(const thread_info_t *) const; + void compute_diff_weights_3d(const thread_info_t *) const; + void reduce_diff_weights(const thread_info_t *) const; + void reduce_diff_weights_3d(const thread_info_t *) const; + void compute_diff_bias(const thread_info_t *) const; + void reduce_diff_bias(const thread_info_t *) const; + + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + int nthr_, nthr_mb_, nthr_g_, nthr_oc_b_, nthr_ic_b_; + + jit_sve_512_conv_bwd_weights_kernel_f32 *kernel_; + cpu_accumulator_1d_t *acc_ker_; + cpu_reducer_t *reducer_bias_; +}; + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_sve_512_core_x8s8s32x_deconvolution.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_sve_512_core_x8s8s32x_deconvolution.hpp new file mode 100644 index 0000000000000000000000000000000000000000..dab19ed1b0c1cf2db34b3368f4233dc5657406ea --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_sve_512_core_x8s8s32x_deconvolution.hpp @@ -0,0 +1,352 @@ +/******************************************************************************* +* Copyright 2018-2022 Intel Corporation +* Copyright 2022 FUJITSU LIMITED +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_JIT_SVE_512_CORE_X8S8S32X_DECONVOLUTION_HPP +#define CPU_AARCH64_JIT_SVE_512_CORE_X8S8S32X_DECONVOLUTION_HPP + +#include +#include + +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/memory.hpp" +#include "common/nstl.hpp" +#include "common/primitive.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/aarch64/jit_generator.hpp" +#include "cpu/aarch64/jit_primitive_conf.hpp" +#include "cpu/aarch64/jit_uni_deconv_zp_pad_str_kernel.hpp" +#include "cpu/cpu_deconvolution_pd.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +using namespace Xbyak_aarch64; + +typedef enum { + no_last_block = 0x1U, + last_ic_block = 0x2U, + last_sp_block = 0x4U, +} ker_block_t; + +struct ur_w_blks_params_t { + struct single_ur_w_blk_params_t { + single_ur_w_blk_params_t( + int l_overflow, int r_overflow, bool process_sp_carefully) + : l_overflow(l_overflow) + , r_overflow(r_overflow) + , process_sp_carefully(process_sp_carefully) {} + + // l_overflow - no. of spatial elements of weights standing out of + // src spatial when computing the 1st output pixel in the current blk + int l_overflow; + // r_overflow - no. of spatial elements of weights standing out of + // src spatial when computing the lst output pixel in the current blk + int r_overflow; + // process_sp_carefully - indicates if loading the last src sp + // for computation of the last dst sp of the block can't be done + // by fetching 4 src sp at once + bool process_sp_carefully; + }; + std::vector blks_params; + int num_pre_blks; // num of blocks with l_overflow>0 + int num_post_blks; // num of blocks with r_overflow>0 or that need to be + // processed carefully +}; + +template +struct jit_sve_512_core_x8s8s32x_deconv_fwd_kernel : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_sve_512_core_x8s8s32x_deconv_fwd_ker_t); + + jit_sve_512_core_x8s8s32x_deconv_fwd_kernel(const jit_conv_conf_t &ajcp, + const primitive_attr_t &attr, const memory_desc_t &dst_md); + ~jit_sve_512_core_x8s8s32x_deconv_fwd_kernel(); + + const jit_conv_conf_t &jcp; + const primitive_attr_t &attr_; + +private: + const int ic_sub_step = 4; + const uint64_t isa_sveLen = cpu_isa_traits::vlen; + + /* data regs */ + const XReg reg_src = x8; + const XReg reg_filt = x9; + const XReg reg_dst = x10; + const XReg param1 = abi_param1; + const XReg reg_kh = abi_param2; + const XReg reg_ki = x14; + + const XReg reg_nur_w = x3; + const XReg reg_bias = x2; + const XReg reg_icb = reg_bias; + const XReg reg_ptr_scales = x16; + const WReg reg_ptr_saturation_ubound = w16; + const XReg reg_oc_blocks = x6; + + const XReg aux_reg_src = x11; + const XReg aux_reg_filt = x12; + + const XReg aux_reg_src_d = x13; + const XReg aux_reg_filt_d = x17; + + const XReg reg_compensation = x14; + const XReg reg_bias_alpha = abi_not_param1; + const XReg reg_overflow = x16; + const XReg reg_comp_strides = reg_overflow; + const XReg reg_ker_long_offt = x17; + const XReg ®_zp_dst_ = x17; + const XReg ®_zp_src_ = x17; + const XReg ®_zp_compensation = x11; + const XReg reg_zp_src_pad_comp = x20; + + PReg ktail_mask = p2; + const PReg mask_tmp = p4; + + const ZReg vmm_tmp0 = z28; + const ZReg vmm_tmp1 = z29; + /* used during write-out section of store_output */ + const ZReg vmm_saturation = z31; + const ZReg vmm_wei = z31; + + /* unsigned input */ + const ZReg vmm_shift = z30; + const ZReg vmm_comp = z30; + /// + + ZReg vmm_out(int i_ur, int i_oc) { + int idx = i_ur * jcp.nb_oc_blocking + i_oc; + assert(idx < 31); + return ZReg(idx); + } + + ZReg vmm_inp(int i_ic, int nb_x_blocking) const { + int idx = i_ic + nb_x_blocking * jcp.ur_w; + assert(idx < 31); + return ZReg(idx); + } + ZReg vmm_bias_alpha() { return ZReg(jcp.nb_oc_blocking * jcp.ur_w); } + + template + ZReg compress_addr(const XReg &base, T offt, const bool mask_flag = false, + const bool bcast = false) { + assert(bcast == false); + PReg mask = P_ALL_ONE; + XReg addr = base; + + if (offt) { + add_imm(X_DEFAULT_ADDR, base, offt, X_TMP_0); + addr = X_DEFAULT_ADDR; + } + + if (mask_flag) mask = PReg(ktail_mask.getIdx()); + + mov(X_TMP_0, 64); + ld1w(vmm_tmp0.s, mask / T_z, ptr(addr)); + return vmm_tmp0; + } + + int get_ow_start(int ki, int l_overflow) { + int res = (jcp.ow - 1 + jcp.r_pad) % jcp.stride_w + + l_overflow * jcp.stride_w + - (jcp.kw - 1 - ki) * (jcp.dilate_w + 1); + while (res < 0) + res += jcp.stride_w; + return res; + } + + int get_ow_end(int ur_w, int ki, int r_overflow) { + if (utils::one_of(ur_w, jcp.ow, jcp.ur_w_tail)) + ur_w += nstl::min(0, jcp.r_pad); // remove negative padding + int res = (ur_w - 1 + jcp.l_pad) % jcp.stride_w + + r_overflow * jcp.stride_w - ki * (jcp.dilate_w + 1); + while (res < 0) + res += jcp.stride_w; + return ur_w - res; + } + + int get_blocking_size() const noexcept; + int get_tail_size() const noexcept; + void prepare_output(int ur_w); + void store_output(int ur_w, bool last_oc_block); + void compute( + const ZReg &vreg_acc, const ZReg &vreg_wei, const ZReg &vreg_src); + std::function prepare_round_robin_vmm_inp_generator( + int ur_w) const noexcept; + void apply_zp_src_pad_str_comp( + int ur_w, int l_overflow, int r_overflow, bool h_padded); + void append_zp_src_pad_str_comp(int ur_w, int l_overflow, int r_overflow, + bool h_padded, bool last_oc_block); + void compute_ker(int ur_w, int l_overflow, int r_overflow, + ker_block_t last_ic_block_flag, bool h_padded = false); + void kh_loop(int ur_w, int pad_l, int pad_r, ker_block_t last_ker_block); + void icb_loop(int ur_w, int pad_l, int pad_r, bool last_block); + + ur_w_blks_params_t get_ur_w_blks_params(); + + void generate() override; + void cvt2ps(const data_type_t type_in, const ZReg &vmm_in, const ZReg &op, + const bool mask_flag); + + void uni_ld1r(const VReg4S &d, const XReg &addr) { ld1r(d, ptr(addr)); } + + void uni_ld1r(const ZRegS &d, const XReg &addr) { + ld1rw(d, P_ALL_ONE / T_z, ptr(addr)); + } + + void uni_fmin(const VReg4S &d, const VReg4S &s) { fmin(d, d, s); } + + void uni_fmin(const ZRegS &d, const ZRegS &s) { + fmin(d, P_ALL_ONE / T_m, s); + } +}; + +struct _jit_sve_512_core_x8s8s32x_deconv_fwd_kernel { + _jit_sve_512_core_x8s8s32x_deconv_fwd_kernel(const jit_conv_conf_t &ajcp, + const primitive_attr_t &attr, const memory_desc_t &dst_md) + : kernel_(nullptr) { + + int ch_block = ajcp.is_depthwise ? ajcp.ch_block : ajcp.ic_block; + switch (ch_block) { + case 16: + kernel_ = new jit_sve_512_core_x8s8s32x_deconv_fwd_kernel< + sve_512>(ajcp, attr, dst_md); + return; + case 8: + kernel_ = new jit_sve_512_core_x8s8s32x_deconv_fwd_kernel< + sve_256>(ajcp, attr, dst_md); + return; + case 4: + kernel_ = new jit_sve_512_core_x8s8s32x_deconv_fwd_kernel< + sve_128>(ajcp, attr, dst_md); + return; + default: assert(!"invalid channel blocking"); + } + } + + status_t create_kernel() { return kernel_->create_kernel(); } + + ~_jit_sve_512_core_x8s8s32x_deconv_fwd_kernel() { delete kernel_; } + + void operator()(const jit_deconv_call_s *p) const { (*kernel_)(p); } + + static status_t init_conf(jit_conv_conf_t &jcp, + const deconvolution_desc_t &cd, memory_desc_t &src_md, + memory_desc_t &weights_md, memory_desc_t &dst_md, + const bool with_bias, memory_desc_t &bias_md, + primitive_attr_t &attr, int nthreads); + + static void init_scratchpad(memory_tracking::registrar_t &scratchpad, + const jit_conv_conf_t &jcp, const primitive_attr_t &attr); + +private: + DNNL_DISALLOW_COPY_AND_ASSIGN(_jit_sve_512_core_x8s8s32x_deconv_fwd_kernel); + jit_generator *kernel_; +}; + +struct jit_sve_512_core_x8s8s32x_deconvolution_fwd_t : public primitive_t { + struct pd_t : public cpu_deconvolution_fwd_pd_t { + using cpu_deconvolution_fwd_pd_t::cpu_deconvolution_fwd_pd_t; + + DECLARE_COMMON_PD_T( + JIT_IMPL_NAME_HELPER("jit_deconvolution:", sve_512, ""), + jit_sve_512_core_x8s8s32x_deconvolution_fwd_t); + + status_t init(engine_t *engine) { + using namespace data_type; + using skip_mask_t = primitive_attr_t::skip_mask_t; + const bool ok = mayiuse(sve_512) && is_fwd() + && (desc()->alg_kind & alg_kind::deconvolution_direct) + && utils::one_of(src_md(0)->data_type, s8, u8) + && weights_md(0)->data_type == s8 + && IMPLICATION(with_bias(), + utils::one_of( + weights_md(1)->data_type, f32, s32, s8, u8)) + && utils::one_of(dst_md(0)->data_type, f32, s32, s8, u8) + && desc()->accum_data_type == s32 + && attr()->has_default_values(skip_mask_t::oscale_runtime + | skip_mask_t::post_ops + | skip_mask_t::zero_points_runtime); + if (!ok) return status::unimplemented; + + CHECK(_jit_sve_512_core_x8s8s32x_deconv_fwd_kernel::init_conf(jcp_, + *desc(), src_md_, weights_md_, dst_md_, with_bias(), + bias_md_, attr_, dnnl_get_max_threads())); + + auto scratchpad = scratchpad_registry().registrar(); + _jit_sve_512_core_x8s8s32x_deconv_fwd_kernel::init_scratchpad( + scratchpad, jcp_, *attr()); + + return status::success; + } + + jit_conv_conf_t jcp_; + }; + + jit_sve_512_core_x8s8s32x_deconvolution_fwd_t(const pd_t *apd) + : primitive_t(apd) {} + + status_t init(engine_t *engine) override { + CHECK(safe_ptr_assign(kernel_, + new _jit_sve_512_core_x8s8s32x_deconv_fwd_kernel( + pd()->jcp_, *pd()->attr(), *pd()->dst_md(0)))); + + if (zp::should_calculate_deconv_zp_src_pad_str_comp(pd()->jcp_)) { + CHECK(safe_ptr_assign(zp_src_pad_comp_kernel_, + zp::create_deconv_zp_pad_str_comp_ker( + pd()->jcp_))); + const auto zp_kernel_status + = zp_src_pad_comp_kernel_->create_kernel(); + if (zp_kernel_status != status::success) return zp_kernel_status; + } + + return kernel_->create_kernel(); + } + + status_t execute(const exec_ctx_t &ctx) const override { + auto ndims = pd()->ndims(); + if (ndims == 3) + return execute_forward_1d(ctx); + else if (ndims == 4) + return execute_forward_2d(ctx); + else if (ndims == 5) + return execute_forward_3d(ctx); + return status::runtime_error; + } + +private: + status_t execute_forward_1d(const exec_ctx_t &ctx) const; + status_t execute_forward_2d(const exec_ctx_t &ctx) const; + status_t execute_forward_3d(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + std::unique_ptr<_jit_sve_512_core_x8s8s32x_deconv_fwd_kernel> kernel_; + std::unique_ptr + zp_src_pad_comp_kernel_; +}; + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_sve_512_x8s8s32x_conv_kernel.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_sve_512_x8s8s32x_conv_kernel.hpp new file mode 100644 index 0000000000000000000000000000000000000000..044298618130113443e62dbcf34afc0103fd494d --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_sve_512_x8s8s32x_conv_kernel.hpp @@ -0,0 +1,254 @@ +/******************************************************************************* +* Copyright 2021 Intel Corporation +* Copyright 2021 FUJITSU LIMITED +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_JIT_SVE_512_X8S8S32X_CONV_KERNEL_HPP +#define CPU_AARCH64_JIT_SVE_512_X8S8S32X_CONV_KERNEL_HPP + +#include "common/c_types_map.hpp" +#include "common/memory_tracking.hpp" + +#include "cpu/aarch64/jit_generator.hpp" +#include "cpu/aarch64/jit_primitive_conf.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +using namespace Xbyak_aarch64; + +struct jit_sve_512_x8s8s32x_fwd_kernel : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(_jit_sve_512_x8s8s32x_conv_fwd_ker_t) + + enum { STATE_FIRST_DST_LOAD = 0x1U }; + + jit_sve_512_x8s8s32x_fwd_kernel( + const jit_conv_conf_t &ajcp, const primitive_attr_t &attr) + : jcp(ajcp), attr_(attr) { + if (jcp.with_eltwise) assert(!"not supported"); + + int ch_block = jcp.is_depthwise ? jcp.ch_block : jcp.ic_block; + switch (ch_block) { + case 16: sve_len_ = 64; break; + case 8: sve_len_ = 32; break; + case 4: sve_len_ = 16; break; + default: assert(!"unreachable"); break; + } + } + + ~jit_sve_512_x8s8s32x_fwd_kernel() {} + + jit_conv_conf_t jcp; + const primitive_attr_t &attr_; + + static status_t init_conf(jit_conv_conf_t &jcp, + const convolution_desc_t &cd, memory_desc_t &src_pd, + memory_desc_t &weights_pd, memory_desc_t &dst_pd, + memory_desc_t &bias_pd, const primitive_attr_t &attr, int nthreads); + static void init_scratchpad(memory_tracking::registrar_t &scratchpad, + const jit_conv_conf_t &jcp, const primitive_attr_t &attr); + +private: + size_t sve_len_; + + enum { + typesize = sizeof(float), + ker_reg_base_idx = 28, + ker_dw_reg_base_idx = 30, + ker_zp_reg_base_idx = 26, + }; + typedef enum { + no_last_block, + last_ic_block, + last_sp_block, + } ic_block_t; + + /* data regs */ + const XReg reg_ptr_scales = x7; + const XReg aux_reg_saturation = x7; + const XReg reg_inp = x8; + const XReg reg_ker = x9; + const XReg reg_out = x10; + const XReg aux_reg_inp = x11; + const XReg reg_ptr_sum_scale = x11; + const XReg aux_reg_ker = x12; + const XReg reg_compensation = x14; + const XReg aux_reg_inp_d = x13; + const XReg aux_reg_ker_d = x15; + // Using 3d regs as depthwise_3d is not yet supported + const XReg reg_inp_buffer_ptr = aux_reg_inp_d; + const XReg aux_reg_inp_buffer_ptr = aux_reg_ker_d; + + /* counter regs */ + const XReg reg_bias_alpha = x1; + const XReg reg_param1 = x0; + const XReg reg_oi = x3; + const XReg reg_bias = x2; + const XReg reg_oc_blocks = x6; + const XReg reg_owb = aux_reg_ker; + const XReg reg_scratch = reg_compensation; + const XReg reg_kj = reg_ptr_scales; + const XReg reg_ki = reg_compensation; + const XReg reg_overflow = reg_ptr_scales; + const XReg reg_icb = reg_bias; + const XReg reg_jmp_tbl_base = reg_kj; + + XReg reg_stack = x22; // translator stack register + + /* Temporay registers */ + XReg reg_tmp0_imm = x23; // tmp for add_imm + XReg reg_tmp1_imm = x24; // tmp for add_imm + XReg reg_tmp0_adr = x25; // tmp for address value + + const PReg ktail_mask = p2; + const PReg kblend_mask = p8; + + const PReg mask_tmp = p3; + const PReg mask_tmp2 = p9; + const PReg mask_all_one = p4; + + const ZReg vmm_wei = ZReg(31); + /* used during bias section of store_output */ + const ZReg vmm_comp = ZReg(30); // only for unsigned input + const ZReg vmm_bias = ZReg(31); + const ZReg vmm_pre_load = ZReg(30); // only for signed input + /* used during post_op sum section of store_output */ + const ZReg vmm_prev_dst = ZReg(31); + /* used during write-out section of store_output */ + const ZReg vmm_saturation = ZReg(30); + const ZReg vmm_zero = ZReg(31); + + /* used in compute_ker (but set during prepare_output) */ + const ZReg vmm_shift = vmm_comp; // only for unsigned input + const ZReg vmm_tmp = ZReg(28); // not used for depthwise + const ZReg vmm_one + = ZReg(29); // set at start of kernel, not used for depthwise. + + /* registers use only for depthwise + groups are always blocked by 16(padded if needed), + hence use only ZReg registers */ + const ZReg zmm_wei = ZReg(31); + ZReg zmm_tmp = ZReg(0); + ZReg zmm_src = ZReg(0); + ZReg zmm_shifted_zero = ZReg(0); + ZReg zmm_permute = ZReg(0); + + bool mask_gflag; + + ZReg vmm_out(int i_ur, int i_oc) { + int nb_x_blocking + = jcp.is_depthwise ? jcp.nb_ch_blocking : jcp.nb_oc_blocking; + int idx = i_ur * nb_x_blocking + i_oc; + assert(idx + < (jcp.is_depthwise ? ker_dw_reg_base_idx : ker_reg_base_idx)); + return ZReg(idx); + } + ZReg zmm_out(int i_ur, int i_oc) { + int idx = vmm_out(i_ur, i_oc).getIdx(); + assert(idx + < (jcp.is_depthwise ? ker_dw_reg_base_idx : ker_reg_base_idx)); + return ZReg(idx); + } + ZReg vmm_inp(int i_ic, int nb_x_blocking) { + int idx = i_ic + nb_x_blocking * jcp.ur_w; + assert(idx < 31); + return ZReg(idx); + } + ZReg zmm_inp(int i_ic, int nb_x_blocking) { + int idx = i_ic + nb_x_blocking * jcp.ur_w; + const int max_idx = ker_dw_reg_base_idx; + assert(idx < max_idx); + MAYBE_UNUSED(max_idx); + + return ZReg(idx); + } + ZReg vmm_bias_alpha() { + int nb_c_block + = jcp.is_depthwise ? jcp.nb_ch_blocking : jcp.nb_oc_blocking; + return ZReg(nb_c_block * jcp.ur_w); + } + ZReg xmm_bias_alpha() { + int nb_c_block + = jcp.is_depthwise ? jcp.nb_ch_blocking : jcp.nb_oc_blocking; + return ZReg(nb_c_block * jcp.ur_w); + } + int get_ow_start(int ki, int pad_l) { + return nstl::max(0, + utils::div_up(pad_l - ki * (jcp.dilate_w + 1), jcp.stride_w)); + } + int get_ow_end(int ur_w, int ki, int pad_r) { + return ur_w + - nstl::max(0, + utils::div_up( + pad_r - (jcp.kw - 1 - ki) * (jcp.dilate_w + 1), + jcp.stride_w)); + } + + void prepare_output(int ur_w); + void store_output(int ur_w, bool last_oc_block_flag); + void compute_ker_dw(int ur_w, int pad_l, int pad_r, + ic_block_t last_ic_block_flag, bool h_padded); + void compute_ker(int ur_w, int pad_l, int pad_r, + ic_block_t last_ic_block_flag, bool h_padded = false); + void kh_loop(int ur_w, int pad_l, int pad_r, ic_block_t last_ic_block_flag); + void icb_loop(int ur_w, int pad_l, int pad_r, bool is_last_spatial_block); + void generate() override; + void cvt2ps(data_type_t type_in, ZReg ymm_in, const XReg reg_base, + const int offset, bool mask_flag); + void vmm_mask_all_one(); + void vmm_load_src(ZReg src, XReg reg_addr, bool mask_flag); + + int get_offset(int raw_offt) { + auto offt = raw_offt; + int scale = 0; + const int EVEX_max_8b_offt = 0x200; + if (EVEX_max_8b_offt <= offt && offt < 3 * EVEX_max_8b_offt) { + offt = offt - 2 * EVEX_max_8b_offt; + scale = 1; + } else if (3 * EVEX_max_8b_offt <= offt + && offt < 5 * EVEX_max_8b_offt) { + offt = offt - 4 * EVEX_max_8b_offt; + scale = 2; + } + + auto re = offt; + if (scale) re = re + (2 * EVEX_max_8b_offt) * scale; + + return re; + } + + XReg get_comp_addr_reg(XReg base, int offset = 0) { + auto offt = get_offset(offset); + + if (offt == 0) return base; + + auto reg_tmp_adr = reg_tmp0_adr; + auto reg_tmp_imm = reg_tmp0_imm; + add_imm(reg_tmp_adr, base, offt, reg_tmp_imm); + + return reg_tmp_adr; + } + + static bool post_ops_ok(jit_conv_conf_t &jcp, const primitive_attr_t &attr); +}; + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_sve_512_x8s8s32x_convolution.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_sve_512_x8s8s32x_convolution.hpp new file mode 100644 index 0000000000000000000000000000000000000000..e6c733020791b87af4ce3ac8b2bd8c11fb667311 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_sve_512_x8s8s32x_convolution.hpp @@ -0,0 +1,122 @@ +/******************************************************************************* +* Copyright 2021 Intel Corporation +* Copyright 2021 FUJITSU LIMITED +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_JIT_SVE_X8S8S32X_CONVOLUTION_HPP +#define CPU_AARCH64_JIT_SVE_X8S8S32X_CONVOLUTION_HPP + +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/memory_tracking.hpp" +#include "common/primitive.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_convolution_pd.hpp" + +#include "cpu/aarch64/jit_sve_512_x8s8s32x_conv_kernel.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +template +struct jit_sve_512_x8s8s32x_convolution_fwd_t : public primitive_t { + struct pd_t : public cpu_convolution_fwd_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const typename pd_t::base_class *hint_fwd_pd) + : cpu_convolution_fwd_pd_t(adesc, attr, hint_fwd_pd), jcp_() {} + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit_int8:", sve_512, ""), + jit_sve_512_x8s8s32x_convolution_fwd_t); + + status_t init(engine_t *engine) { + using smask_t = primitive_attr_t::skip_mask_t; + bool ok = true && is_fwd() + && set_default_alg_kind(alg_kind::convolution_direct) + && expect_data_types(src_type, data_type::s8, + data_type::undef, dst_type, data_type::s32) + && IMPLICATION(with_bias(), + utils::one_of(bias_md_.data_type, data_type::f32, + data_type::s32, data_type::s8, + data_type::u8)) + && attr()->has_default_values( + smask_t::oscale_runtime | smask_t::post_ops, + dst_type) + && !has_zero_dim_memory(); + if (!ok) return status::unimplemented; + + status_t status = jit_sve_512_x8s8s32x_fwd_kernel::init_conf(jcp_, + *desc(), src_md_, weights_md_, dst_md_, bias_md_, *attr(), + dnnl_get_max_threads()); + if (status != status::success) return status; + + auto scratchpad = scratchpad_registry().registrar(); + jit_sve_512_x8s8s32x_fwd_kernel::init_scratchpad( + scratchpad, jcp_, *attr()); + + return status; + } + + jit_conv_conf_t jcp_; + }; + + jit_sve_512_x8s8s32x_convolution_fwd_t(const pd_t *apd) + : primitive_t(apd) {} + + typedef typename prec_traits::type src_data_t; + typedef typename prec_traits::type wei_data_t; + typedef typename prec_traits::type dst_data_t; + + status_t init(engine_t *engine) override { + CHECK(safe_ptr_assign(kernel_, + new jit_sve_512_x8s8s32x_fwd_kernel( + pd()->jcp_, *pd()->attr()))); + return kernel_->create_kernel(); + } + + status_t execute(const exec_ctx_t &ctx) const override { + const auto &_pd = pd(); + if (_pd->ndims() == 3) + return execute_forward_1d(ctx); + else if (_pd->ndims() == 4) + if (_pd->jcp_.is_depthwise) + return execute_forward_2d_dw(ctx); + else + return execute_forward_2d(ctx); + else if (_pd->ndims() == 5) + return execute_forward_3d(ctx); + return status::unimplemented; + } + +private: + status_t execute_forward_1d(const exec_ctx_t &ctx) const; + status_t execute_forward_2d(const exec_ctx_t &ctx) const; + status_t execute_forward_2d_dw(const exec_ctx_t &ctx) const; + status_t execute_forward_3d(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr kernel_; +}; + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_1x1_conv_utils.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_1x1_conv_utils.hpp new file mode 100644 index 0000000000000000000000000000000000000000..521a8c54dc7637a259f8593ac2e157bebff06d3d --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_1x1_conv_utils.hpp @@ -0,0 +1,680 @@ +/******************************************************************************* +* Copyright 2021-2023 Intel Corporation +* Copyright 2021-2023 FUJITSU LIMITED +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_JIT_UNI_1X1_CONV_UTILS_HPP +#define CPU_AARCH64_JIT_UNI_1X1_CONV_UTILS_HPP + +#include "common/convolution_pd.hpp" +#include "common/dnnl_thread.hpp" +#include "common/memory_tracking.hpp" +#include "common/nstl.hpp" +#include "common/primitive_desc_iterator.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/aarch64/jit_generator.hpp" +#include "cpu/aarch64/jit_primitive_conf.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +struct reduce_to_unit_stride_t { + convolution_desc_t conv_d_; + bool reduce_src_; + size_t space_per_thread_; +}; + +/* 1x1-kernel does not support non-unit strides so far, so the idea is: + * - for fwd or bwd_weights: to copy src to a scratch memory (with strides + * equal to 1) and then call the kernel + * - for bwd_data: reduce the problem to the one with unit stride by + * performing computations in a scratch memory (with strides equal to 1) + * and then copy the result to diff_src */ +template +inline void rtus_prepare(conv_pd_t *self, const convolution_desc_t *&conv_d, + const memory_desc_t *&src_d, const memory_desc_t *dst_d) { + const int ndims = src_d->ndims; + + bool rtus_applicable = utils::one_of(ndims, 3, 4); + if (ndims == 3) + rtus_applicable = rtus_applicable && conv_d->strides[0] != 1 + && conv_d->src_desc.data_type != data_type::s32; + else + rtus_applicable = rtus_applicable + && (conv_d->strides[0] != 1 || conv_d->strides[1] != 1); + for (int d = 2; d < ndims; ++d) { + /* TODO: relax these conditions (by improving reducer) */ + rtus_applicable = rtus_applicable && conv_d->padding[0][d - 2] == 0 + && dst_d->dims[d] * conv_d->strides[d - 2] == src_d->dims[d]; + } + if (!rtus_applicable) return; + + const auto dat_tag = ndims == 3 + ? memory_desc_wrapper(src_d).matches_one_of_tag( + format_tag::nCw8c, format_tag::nCw16c, format_tag::nwc) + : memory_desc_wrapper(src_d).matches_one_of_tag( + format_tag::nChw8c, format_tag::nChw16c, format_tag::nhwc); + if (dat_tag == format_tag::undef) return; + + const bool is_nspc + = utils::one_of(dat_tag, format_tag::nwc, format_tag::nhwc); + if (is_nspc && !mayiuse(sve_128)) return; + + // rtus is applicable, configure it. + self->rtus_.reduce_src_ = true; + conv_d = &(self->rtus_.conv_d_ = *conv_d); + self->rtus_.conv_d_.strides[0] = 1; + if (ndims == 4) self->rtus_.conv_d_.strides[1] = 1; + utils::array_set(self->rtus_.conv_d_.padding[0], 0, 2); + if (ndims == 4) utils::array_set(self->rtus_.conv_d_.padding[1], 0, 2); + const int ic = src_d->dims[1]; + if (self->desc()->prop_kind == prop_kind::backward_data) { + data_type_t data_type = self->rtus_.conv_d_.diff_src_desc.data_type; + src_d = &(self->rtus_.conv_d_.diff_src_desc = *dst_d); + self->rtus_.conv_d_.diff_src_desc.dims[1] = ic; + self->rtus_.conv_d_.diff_src_desc.data_type = data_type; + memory_desc_wrapper::compute_blocking( + self->rtus_.conv_d_.diff_src_desc, dat_tag); + } else { + data_type_t data_type = self->rtus_.conv_d_.src_desc.data_type; + src_d = &(self->rtus_.conv_d_.src_desc = *dst_d); + self->rtus_.conv_d_.src_desc.dims[1] = ic; + self->rtus_.conv_d_.src_desc.data_type = data_type; + memory_desc_wrapper::compute_blocking( + self->rtus_.conv_d_.src_desc, dat_tag); + } +} + +template +inline void rtus_prepare_space_info(conv_pd_t *self, + memory_tracking::registrar_t &scratchpad, int max_threads) { + if (!self->rtus_.reduce_src_) return; + const auto &jcp = self->jcp_; + const bool is_nspc + = utils::one_of(jcp.src_tag, format_tag::nhwc, format_tag::nwc); + + const size_t factor = utils::pick_by_prop_kind(self->desc()->prop_kind, + jcp.nb_reduce, jcp.nb_load_blocking_max, jcp.nb_bcast_blocking); + size_t typesize + = types::data_type_size(self->invariant_src_md()->data_type); + + self->rtus_.space_per_thread_ + = is_nspc ? jcp.is * jcp.ic : factor * jcp.is * jcp.ic_block; + scratchpad.book(memory_tracking::names::key_conv_rtus_space, + max_threads * self->rtus_.space_per_thread_, typesize); +} + +template +struct rtus_driver_t : public jit_generator { + + struct call_params_t { + const void *ws; /* reduced image (w/ strides = 1) */ + const void *src; /* source image (w/ non-unit strides) */ + size_t icb; + size_t os; + size_t iw_start; + }; + + DECLARE_CPU_JIT_AUX_FUNCTIONS(rtus_driver_t) + + Xbyak_aarch64::XReg reg_ws = x5; + Xbyak_aarch64::XReg reg_src = x6; + Xbyak_aarch64::XReg reg_icb = x7; + Xbyak_aarch64::XReg reg_os = x8; + Xbyak_aarch64::XReg reg_iw_start = x9; + + Xbyak_aarch64::XReg reg_cur_os = x10; + Xbyak_aarch64::XReg reg_cur_iw = x11; + Xbyak_aarch64::XReg reg_cur_src = x12; + Xbyak_aarch64::XReg reg_cur_src_fin = reg_cur_iw; /* just reuse */ + + Xbyak_aarch64::PReg tail_mask = p1; + + // nspc section + Xbyak_aarch64::XReg reg_cur_icb = x13; + Xbyak_aarch64::XReg reg_tail_mask = x14; + Xbyak_aarch64::XReg reg_icb_remainder = x15; + Xbyak_aarch64::XReg reg_ws_copy = x16; + + int iw_, stride_w_; + int src_step_h_, src_step_icb_, ws_step_icb_, vlen_, vlen_shift_; + bool src_to_ws_; + size_t typesize_; + int ic_, ic_tail_; + bool is_nspc_; + + Xbyak_aarch64::ZReg reg_zero = Xbyak_aarch64::ZReg(0); + Xbyak_aarch64::ZReg reg_v = Xbyak_aarch64::ZReg(1); + + rtus_driver_t(int iw, int stride_w, int src_step_h, int src_step_icb, + int ws_step_icb, bool src_to_ws, size_t typesize, int ic, + bool is_nspc = false) + : iw_(iw) + , stride_w_(stride_w) + , src_step_h_(src_step_h) + , src_step_icb_(src_step_icb) + , ws_step_icb_(ws_step_icb) + , src_to_ws_(src_to_ws) + , typesize_(typesize) + , ic_(ic) + , is_nspc_(is_nspc) { + using namespace Xbyak_aarch64; + + assert(ic_ > 0); + + auto Vmm = [=](int idx, size_t typesize) { + ZReg res = ZReg(idx); + if (is_nspc_) { + switch (isa) { + case sve_512: res = ZReg(idx); break; + default: assert(!"Not supported isa"); res = ZReg(idx); + } + return res; + } + switch (isa) { + case sve_512: + switch (typesize) { + case 4: res = ZReg(idx); break; + default: + assert(!"Not supported typesize"); + res = ZReg(idx); + } + } + return res; + }; + + reg_zero = Vmm(0, typesize); + reg_v = Vmm(1, typesize); + + vlen_ = reg_v.getBit() / 8; + vlen_shift_ = 0; + + int tvlen = is_nspc_ ? typesize_ : vlen_; + while (tvlen > 1) { + tvlen /= 2; + vlen_shift_++; + } + + const int simd_w = vlen_ / sizeof(float); + ic_tail_ = ic_ % simd_w; + } + + void loop_is() { + using namespace Xbyak_aarch64; + + mov(reg_cur_src, reg_src); + mov(reg_cur_iw, reg_iw_start); + mov(reg_cur_os, reg_os); + + Label is_loop; + L(is_loop); + + if (src_to_ws_) { + ldr(reg_v, ptr(reg_cur_src)); + str(reg_v, ptr(reg_ws)); + } else { + ldr(reg_v, ptr(reg_ws)); + str(reg_v, ptr(reg_cur_src)); + for (int w = 1; w < stride_w_; ++w) { + add_imm(X_TMP_3, reg_cur_src, w * vlen_, X_TMP_4); + str(reg_zero, ptr(X_TMP_3)); + } + } + + add_imm(reg_ws, reg_ws, vlen_, X_TMP_4); + add_imm(reg_cur_src, reg_cur_src, stride_w_ * vlen_, X_TMP_4); + + // for 1d or stride_h=1 convolutions the loop over h should be skipped + if (!(src_step_icb_ == iw_ || src_step_h_ == iw_)) { + Label skip_h_step; + add_imm(reg_cur_iw, reg_cur_iw, stride_w_, X_TMP_4); + cmp(reg_cur_iw, iw_); + b(LT, skip_h_step); + + if (src_to_ws_) { + add_imm(reg_cur_src, reg_cur_src, (src_step_h_ - iw_) * vlen_, + X_TMP_4); + } else { + mov(reg_cur_src_fin, reg_cur_src); + add_imm(reg_cur_src_fin, reg_cur_src_fin, + (src_step_h_ - iw_) * vlen_, X_TMP_4); + Label ih_loop; + L(ih_loop); + + for (int w = 0; w < stride_w_; ++w) { + add_imm(X_TMP_3, reg_cur_src, w * vlen_, X_TMP_4); + str(reg_zero, ptr(X_TMP_3)); + } + + add_imm(reg_cur_src, reg_cur_src, stride_w_ * vlen_, X_TMP_4); + cmp(reg_cur_src, reg_cur_src_fin); + b(LT, ih_loop); + } + mov(reg_cur_iw, 0); + L(skip_h_step); + } + + subs_imm(reg_cur_os, reg_cur_os, vlen_, X_TMP_4); + b(NE, is_loop); + + /* restore dst */ + sub(reg_ws, reg_ws, reg_os); + } + + void loop_is_nspc() { + using namespace Xbyak_aarch64; + + assert(is_nspc_); + + mov(reg_cur_src, reg_src); + mov(reg_cur_iw, reg_iw_start); + + if (isa == sve_512) { + and_(reg_icb_remainder, reg_icb, (vlen_ / typesize_) - 1); + mov_imm(X_TMP_0, 0); + whilelt(tail_mask.s, X_TMP_0, reg_icb_remainder); + } + + auto load_reg = [=](const ZReg &vreg, const XReg ®, + const int64_t offset, bool tail = false) { + if (is_superset(isa, sve_128)) { + add_imm(X_DEFAULT_ADDR, reg, offset, X_TMP_0); + switch (typesize_) { + case 4: + if (tail) + ld1w(vreg.s, tail_mask / T_z, ptr(X_DEFAULT_ADDR)); + else + ld1w(vreg.s, P_ALL_ONE / T_z, ptr(X_DEFAULT_ADDR)); + break; + case 2: + if (tail) + ld1h(vreg.h, tail_mask / T_z, ptr(X_DEFAULT_ADDR)); + else + ld1h(vreg.h, P_ALL_ONE / T_z, ptr(X_DEFAULT_ADDR)); + break; + case 1: + if (tail) + ld1b(vreg.b, tail_mask / T_z, ptr(X_DEFAULT_ADDR)); + else + ld1b(vreg.b, P_ALL_ONE / T_z, ptr(X_DEFAULT_ADDR)); + break; + default: assert(!"Unsupported typesize"); + } + } else { + assert("!Unsupported isa"); + } + }; + + auto store_reg = [=](const XReg ®, const ZReg &vreg, + const int64_t offset, bool tail = false) { + if (is_superset(isa, sve_128)) { + add_imm(X_DEFAULT_ADDR, reg, offset, X_TMP_0); + switch (typesize_) { + case 4: + if (tail) + st1w(vreg.s, tail_mask / T_z, ptr(X_DEFAULT_ADDR)); + else + st1w(vreg.s, P_ALL_ONE / T_z, ptr(X_DEFAULT_ADDR)); + break; + case 2: + if (tail) + st1h(vreg.h, tail_mask / T_z, ptr(X_DEFAULT_ADDR)); + else + st1h(vreg.h, P_ALL_ONE / T_z, ptr(X_DEFAULT_ADDR)); + break; + case 1: + if (tail) + st1b(vreg.b, tail_mask / T_z, ptr(X_DEFAULT_ADDR)); + else + st1b(vreg.b, P_ALL_ONE / T_z, ptr(X_DEFAULT_ADDR)); + break; + default: assert(!"Unsupported typesize"); + } + } else { + assert("!Unsupported isa"); + } + }; + + mov(reg_ws_copy, reg_ws); + lsl(reg_icb, reg_icb, vlen_shift_); + + const size_t w_step_factor = ic_ * typesize_; + const size_t max_load_store_bytes = typesize_ == 4 ? 32 : 16; + const size_t load_store_size + = isa == sve_512 ? vlen_ : max_load_store_bytes; + + Label is_loop, ic_loop, ic_loop_tail, ic_loop_finish; + L(is_loop); + { + mov(reg_cur_src, reg_src); + mov(reg_ws, reg_ws_copy); + mov(reg_cur_icb, reg_icb); + + L(ic_loop); + { + cmp(reg_cur_icb, load_store_size); + b(LT, ic_loop_tail); + + if (src_to_ws_) { + load_reg(reg_v, reg_cur_src, 0); + store_reg(reg_ws, reg_v, 0); + } else { + load_reg(reg_v, reg_ws, 0); + store_reg(reg_cur_src, reg_v, 0); + for (int w = 1; w < stride_w_; ++w) + store_reg(reg_cur_src, reg_zero, w * w_step_factor); + } + add_imm(reg_ws, reg_ws, load_store_size, X_TMP_0); + add_imm(reg_cur_src, reg_cur_src, load_store_size, X_TMP_0); + + sub_imm(reg_cur_icb, reg_cur_icb, load_store_size, X_TMP_0); + b(ic_loop); + } + + L(ic_loop_tail); + { + cmp(reg_cur_icb, 0); + b(EQ, ic_loop_finish); + + if (src_to_ws_) { + load_reg(reg_v, reg_cur_src, 0, true); + store_reg(reg_ws, reg_v, 0, true); + } else { + load_reg(reg_v, reg_ws, 0, true); + store_reg(reg_cur_src, reg_v, 0, true); + for (int w = 1; w < stride_w_; ++w) + store_reg( + reg_cur_src, reg_zero, w * w_step_factor, true); + } + } + L(ic_loop_finish); + + add_imm(reg_ws_copy, reg_ws_copy, w_step_factor, X_TMP_0); + add_imm(reg_src, reg_src, stride_w_ * w_step_factor, X_TMP_0); + + // for 1d or stride_h=1 convolutions the loop over h should be skipped + const bool skip_oh_step = src_step_h_ == iw_; + if (!skip_oh_step) { + mov(reg_cur_src, reg_src); + Label skip_h_step; + add_imm(reg_cur_iw, reg_cur_iw, stride_w_, X_TMP_0); + cmp(reg_cur_iw, iw_); + b(LT, skip_h_step); + + if (src_to_ws_) { + add_imm(reg_src, reg_src, + (src_step_h_ - iw_) * w_step_factor, X_TMP_0); + } else { + mov(reg_cur_src_fin, reg_cur_src); + add_imm(reg_cur_src_fin, reg_cur_src_fin, + (src_step_h_ - iw_) * w_step_factor, X_TMP_0); + Label ih_loop_nhwc, ic_ih_loop_nhwc, ic_tail_ih_loop_nhwc, + ic_finish_ih_loop_nhwc; + L(ih_loop_nhwc); + mov(reg_cur_src, reg_src); + mov(reg_cur_icb, reg_icb); + L(ic_ih_loop_nhwc); + cmp(reg_cur_icb, load_store_size); + b(LT, ic_tail_ih_loop_nhwc); + + for (int w = 0; w < stride_w_; ++w) + store_reg(reg_cur_src, reg_zero, w * w_step_factor); + + add_imm(reg_cur_src, reg_cur_src, load_store_size, X_TMP_0); + subs_imm( + reg_cur_icb, reg_cur_icb, load_store_size, X_TMP_0); + b(NE, ic_ih_loop_nhwc); + + L(ic_tail_ih_loop_nhwc); + cmp(reg_cur_icb, 0); + b(LE, ic_finish_ih_loop_nhwc); + + for (int w = 0; w < stride_w_; ++w) + store_reg( + reg_cur_src, reg_zero, w * w_step_factor, true); + + L(ic_finish_ih_loop_nhwc); + + add_imm(reg_src, reg_src, stride_w_ * w_step_factor, + X_TMP_0); + cmp(reg_src, reg_cur_src_fin); + b(LT, ih_loop_nhwc); + } + eor(reg_cur_iw, reg_cur_iw, reg_cur_iw); + L(skip_h_step); + } + + subs(reg_os, reg_os, 1); + b(NE, is_loop); + } + } + + void generate() override { + using namespace Xbyak_aarch64; + assert(isa == sve_512); + + preamble(); +#define READ_PARAM(what) \ + ldr(reg_##what, \ + ptr(abi_param1, \ + static_cast(offsetof(call_params_t, what)))) + READ_PARAM(src); + READ_PARAM(icb); + READ_PARAM(os); + READ_PARAM(iw_start); + READ_PARAM(ws); +#undef READ_PARAM + + if (!src_to_ws_) { + switch (reg_zero.getBit() / 8) { + case 64 /*ZReg*/: { + Xbyak_aarch64::ZRegS zreg_s(reg_zero.getIdx()); + fmov(zreg_s); // zero clear + break; + } + default: assert(!"rtus kernel failure"); + } + } + if (is_nspc_) { + loop_is_nspc(); + } else { + lsl(reg_os, reg_os, vlen_shift_); + + Label icb_loop; + L(icb_loop); + + loop_is(); + + add_imm(reg_ws, reg_ws, ws_step_icb_ * vlen_, X_TMP_4); + add_imm(reg_src, reg_src, src_step_icb_ * vlen_, X_TMP_4); + + subs_imm(reg_icb, reg_icb, vlen_ / typesize_, X_TMP_4); + b(NE, icb_loop); + } + + postamble(); + } +}; + +template +inline status_t init_rtus_driver(conv_t *self) { + const auto &conf = *self->pd(); + if (!conf.rtus_.reduce_src_) return status::success; + + const auto &cd = *conf.desc(); + const int ndims = conf.ndims(); + const int stride_h = (conf.ndims() == 3) ? 1 : cd.strides[0]; + const int stride_w = cd.strides[ndims - 3]; + + const bool is_bwd_data = cd.prop_kind == prop_kind::backward_data; + const auto &src_d = is_bwd_data ? *conf.diff_src_md() : *conf.src_md(); + + const int ih = ndims == 3 ? 1 : src_d.dims[2]; + const int iw = src_d.dims[ndims - 1]; + const int ic = src_d.dims[1]; + + const auto src_tag = memory_desc_wrapper(src_d).matches_one_of_tag( + format_tag::nhwc, format_tag::nwc); + const bool is_nspc = src_tag != format_tag::undef; + const int src_step_h = stride_h * iw; + const int src_step_icb = !is_nspc ? ih * iw : 1; + const int ws_step_icb = !is_nspc ? conf.jcp_.is : 1; + const bool src_to_ws = !is_bwd_data; + const size_t typesize + = types::data_type_size(self->pd()->invariant_src_md()->data_type); + + CHECK(safe_ptr_assign(self->rtus_driver_, + new rtus_driver_t(iw, stride_w, src_step_h, src_step_icb, + ws_step_icb, src_to_ws, typesize, ic, is_nspc))); + + return self->rtus_driver_->create_kernel(); +} + +inline int best_divider(int value, int min_divider, int max_divider, + bool find_max, int step = 1) { + using namespace dnnl::impl::utils; + max_divider = nstl::max(1, nstl::min(max_divider, value)); + min_divider = nstl::max(1, nstl::min(min_divider, max_divider)); + + auto loss_ratio = [](int total, int chunk) { + return float(rnd_up(total, chunk) - total) / rnd_up(total, chunk); + }; + + float min_loss = FLT_MAX; + int x_divider = max_divider; + for (int divider = max_divider; divider >= min_divider; divider -= step) { + const float loss = loss_ratio(value, divider); + if ((find_max && loss < min_loss) || (!find_max && loss <= min_loss)) { + min_loss = loss; + x_divider = divider; + } + } + return x_divider; +} + +typedef jit_1x1_conv_conf_t jcp_t; + +inline bool is_bcast_layout_nxc(const jcp_t &jcp) { + switch (jcp.prop_kind) { + case prop_kind::forward_training: + case prop_kind::forward_inference: + case prop_kind::backward_weights: + return utils::one_of(jcp.src_tag, format_tag::ndhwc, + format_tag::nhwc, format_tag::nwc); + case prop_kind::backward_data: + return utils::one_of(jcp.dst_tag, format_tag::ndhwc, + format_tag::nhwc, format_tag::nwc); + default: assert(!"invalid prop_kind"); return false; + } +} + +inline bool is_load_layout_nxc(const jcp_t &jcp) { + return jcp.prop_kind == prop_kind::backward_weights + && utils::one_of(jcp.dst_tag, format_tag::ndhwc, format_tag::nhwc, + format_tag::nwc); +} + +inline bool is_out_layout_nxc(const jcp_t &jcp) { + switch (jcp.prop_kind) { + case prop_kind::forward_training: + case prop_kind::forward_inference: + return utils::one_of(jcp.dst_tag, format_tag::ndhwc, + format_tag::nhwc, format_tag::nwc); + case prop_kind::backward_data: + return utils::one_of(jcp.src_tag, format_tag::ndhwc, + format_tag::nhwc, format_tag::nwc); + case prop_kind::backward_weights: return false; + default: assert(!"invalid prop_kind"); return false; + } +} + +inline size_t get_bcast_u_offset(const jcp_t &jcp) { + return is_bcast_layout_nxc(jcp) ? jcp.ic : jcp.ic_block; +} + +inline size_t get_bcast_j_offset(const jcp_t &jcp) { + return is_bcast_layout_nxc(jcp) ? jcp.reduce_dim : jcp.reduce_loop_unroll; +} + +inline size_t get_bcast_offset(const jcp_t &jcp, int u, int j) { + size_t offset; + if (utils::one_of(jcp.prop_kind, prop_kind::forward_training, + prop_kind::forward_inference, prop_kind::backward_data)) { + assert(jcp.reduce_loop_unroll == jcp.reduce_block); + if (is_bcast_layout_nxc(jcp) || u != jcp.reduce_loop_unroll) { + offset = j * get_bcast_j_offset(jcp) + u; + } else { + offset = (jcp.bcast_dim + j) * get_bcast_j_offset(jcp); + } + } else { + offset = u * get_bcast_u_offset(jcp) + j; + } + return sizeof(float) * offset; +} + +inline size_t get_load_u_offset(const jcp_t &jcp) { + return is_load_layout_nxc(jcp) ? jcp.oc : jcp.oc_block; +} + +inline size_t get_load_i_offset(const jcp_t &jcp) { + return is_load_layout_nxc(jcp) ? jcp.oc_block : jcp.os; +} + +inline size_t get_load_bwd_w_offset(const jcp_t &jcp, int i, int u0) { + if (is_load_layout_nxc(jcp)) { + return i * get_load_i_offset(jcp) + u0 * get_load_u_offset(jcp); + } else { + return (i * get_load_i_offset(jcp) + u0) * get_load_u_offset(jcp); + } +} + +inline size_t get_output_i_offset(const jcp_t &jcp) { + if (is_out_layout_nxc(jcp)) { + return jcp.load_block; + } else { + return (jcp.with_dw_conv ? jcp.ow : jcp.bcast_dim) * jcp.load_block; + } +} + +inline size_t get_output_j_offset(const jcp_t &jcp) { + return is_out_layout_nxc(jcp) ? jcp.load_dim : jcp.load_block; +} + +inline size_t get_load_loop_output_fwd_offset( + const jcp_t &jcp, int load_loop_blk) { + size_t offset = load_loop_blk * jcp.oc_block * sizeof(float); + if (!is_out_layout_nxc(jcp)) { + offset *= jcp.with_dw_conv ? jcp.ow : jcp.os; + } + return offset; +} + +inline size_t get_load_loop_output_bwd_d_offset( + const jcp_t &jcp, int load_loop_blk) { + size_t offset = load_loop_blk * jcp.ic_block * sizeof(float); + if (!is_out_layout_nxc(jcp)) { offset *= jcp.os; } + return offset; +} + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_batch_normalization.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_batch_normalization.hpp new file mode 100644 index 0000000000000000000000000000000000000000..3311f5b665af436232ff926a46ce7a9848431e35 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_batch_normalization.hpp @@ -0,0 +1,105 @@ +/******************************************************************************* +* Copyright 2017-2022 Intel Corporation +* Copyright 2020-2022 FUJITSU LIMITED +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_JIT_UNI_BATCH_NORMALIZATION_HPP +#define CPU_AARCH64_JIT_UNI_BATCH_NORMALIZATION_HPP + +#include + +#include "common/c_types_map.hpp" +#include "common/primitive.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_batch_normalization_pd.hpp" + +#include "cpu/aarch64/cpu_isa_traits.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +namespace bnorm_impl { +template +struct driver_t; +} + +template +struct jit_uni_batch_normalization_fwd_t : public primitive_t { + struct pd_t : public cpu_batch_normalization_fwd_pd_t { + pd_t(const batch_normalization_desc_t *adesc, + const primitive_attr_t *attr, + const batch_normalization_fwd_pd_t *hint_fwd_pd) + : cpu_batch_normalization_fwd_pd_t(adesc, attr, hint_fwd_pd) {} + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("bnorm_jit:", isa, ""), + jit_uni_batch_normalization_fwd_t); + + status_t init(engine_t *engine); + int nthr_; // To not exceed the limit in execute used for set up. + }; + + jit_uni_batch_normalization_fwd_t(const pd_t *apd); + ~jit_uni_batch_normalization_fwd_t(); + + status_t init(engine_t *engine) override; + + status_t execute(const exec_ctx_t &ctx) const override; + +private: + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + bnorm_impl::driver_t *bnorm_driver_; +}; + +template +struct jit_uni_batch_normalization_bwd_t : public primitive_t { + struct pd_t : public cpu_batch_normalization_bwd_pd_t { + pd_t(const batch_normalization_desc_t *adesc, + const primitive_attr_t *attr, + const batch_normalization_fwd_pd_t *hint_fwd_pd) + : cpu_batch_normalization_bwd_pd_t(adesc, attr, hint_fwd_pd) {} + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("bnorm_jit:", isa, ""), + jit_uni_batch_normalization_bwd_t); + + status_t init(engine_t *engine); + int nthr_; // To not exceed the limit in execute used for set up. + }; + + jit_uni_batch_normalization_bwd_t(const pd_t *apd); + ~jit_uni_batch_normalization_bwd_t(); + + status_t init(engine_t *engine) override; + + status_t execute(const exec_ctx_t &ctx) const override; + +private: + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + bnorm_impl::driver_t *bnorm_driver_; +}; + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_batch_normalization_s8.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_batch_normalization_s8.hpp new file mode 100644 index 0000000000000000000000000000000000000000..3b96d7ed5ed9fde63776e7954ba96401ca8817e6 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_batch_normalization_s8.hpp @@ -0,0 +1,77 @@ +/******************************************************************************* +* Copyright 2021 Intel Corporation +* Copyright 2021 FUJITSU LIMITED +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_JIT_UNI_BATCH_NORMALIZATION_S8_HPP +#define CPU_AARCH64_JIT_UNI_BATCH_NORMALIZATION_S8_HPP + +#include + +#include "common/c_types_map.hpp" +#include "common/primitive.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/aarch64/cpu_isa_traits.hpp" +#include "cpu/cpu_batch_normalization_pd.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +namespace bnorm_s8_impl { +template +struct driver_t; +} + +template +struct jit_uni_batch_normalization_s8_fwd_t : public primitive_t { + struct pd_t : public cpu_batch_normalization_fwd_pd_t { + pd_t(const batch_normalization_desc_t *adesc, + const primitive_attr_t *attr, + const batch_normalization_fwd_pd_t *hint_fwd_pd) + : cpu_batch_normalization_fwd_pd_t(adesc, attr, hint_fwd_pd) {} + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("bnorm_s8_jit:", isa, ""), + jit_uni_batch_normalization_s8_fwd_t); + + status_t init(engine_t *engine); + }; + + typedef int8_t data_t; + + jit_uni_batch_normalization_s8_fwd_t(const pd_t *apd); + ~jit_uni_batch_normalization_s8_fwd_t(); + + status_t init(engine_t *engine) override; + + status_t execute(const exec_ctx_t &ctx) const override; + +private: + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + bnorm_s8_impl::driver_t *bnorm_driver_; +}; + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_binary.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_binary.hpp new file mode 100644 index 0000000000000000000000000000000000000000..8ca09b9aba1856b72333341dda5e742a6599ff20 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_binary.hpp @@ -0,0 +1,116 @@ +/******************************************************************************* +* Copyright 2019-2023 Intel Corporation +* Copyright 2022-2023 FUJITSU LIMITED +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_JIT_UNI_BINARY_HPP +#define CPU_AARCH64_JIT_UNI_BINARY_HPP + +#include "common/primitive.hpp" + +#include "cpu/cpu_eltwise_pd.hpp" + +#include "cpu/aarch64/jit_uni_binary_kernel.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +struct binary_kernel_t; + +using op_t = binary_op_t; +using bcast_t = binary_bcast_t; + +struct jit_uni_binary_t : public primitive_t { + struct pd_t : public cpu_binary_pd_t { + using cpu_binary_pd_t::cpu_binary_pd_t; + + DECLARE_COMMON_PD_T("jit:uni", jit_uni_binary_t); + + status_t init(engine_t *engine); + + jit_binary_conf_t get_conf() const { return conf_; }; + + private: + op_t get_op_type(const memory_desc_wrapper &src0_d); + bool is_only_dim0_bcasted(const dims_t &bcast_dims, const int ndims); + bcast_t get_bcast_type( + const memory_desc_wrapper &src1_d, const dims_t &bcast_dims); + + // alg_preserves_zero returns true if operation preserves zero in case + // of both inputs contain zero. + bool alg_preserves_zero() const; + bool check_scales_mask() const; + bool is_bcast_pattern(const dims_t &bcast_dims, const dim_t ndims, + const dim_t N_bcast, const dim_t C_bcast, + const dim_t W_bcast) const; + bool is_bcast_pattern(const dims_t &bcast_dims, const dim_t N_bcast, + const dim_t C_bcast) const; + bool is_bcast_allowed(const int ndims) const; + bool is_format_non_blocked(const memory_desc_wrapper &mdw) const; + bool is_different_layouts_allowed(const memory_desc_wrapper &src0_d, + const memory_desc_wrapper &src1_d) const; + bool is_applicable(); + + jit_binary_conf_t conf_; + }; + + jit_uni_binary_t(const pd_t *apd); + ~jit_uni_binary_t() = default; + + status_t init(engine_t *engine) override; + + using data_t = int8_t; + + void execute_no_bcast_strategy(const data_t *src0, const data_t *src1, + data_t *dst, const float *scale0, const float *scale1, + const std::vector &post_ops_binary_rhs_arg_vec, + const bcast_t bcast_type) const; + void execute_bcast_per_batch_strategy(const data_t *src0, + const data_t *src1, data_t *dst, const float *scale0, + const float *scale1, + const std::vector &post_ops_binary_rhs_arg_vec) const; + void execute_bcast_per_c_strategy(const data_t *src0, const data_t *src1, + data_t *dst, const float *scale0, const float *scale1, + const std::vector &post_ops_binary_rhs_arg_vec, + const op_t op_type, const bcast_t bcast_type, + const bool blocked_oc_tail) const; + void execute_bcast_per_w_strategy(const data_t *src0, const data_t *src1, + data_t *dst, const float *scale0, const float *scale1, + const std::vector &post_ops_binary_rhs_arg_vec, + const op_t op_type, const bool blocked_oc_tail) const; + + status_t execute(const exec_ctx_t &ctx) const override; + +private: + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + static bool post_ops_ok(const primitive_attr_t *attr, + const memory_desc_wrapper &src0_d, const memory_desc_wrapper &dst_d, + const bool is_src1_different_layouts, const cpu_isa_t isa); + + std::unique_ptr kernel_; + // used only in bcast_c_blocked strategy if tail exists + std::unique_ptr kernel_tail_; +}; + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_binary_kernel.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_binary_kernel.hpp new file mode 100644 index 0000000000000000000000000000000000000000..530f317f0a12326d662f7793acccbf3bfe0eed20 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_binary_kernel.hpp @@ -0,0 +1,164 @@ +/******************************************************************************* +* Copyright 2021-2023 Intel Corporation +* Copyright 2022-2023 FUJITSU LIMITED +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_UNI_BINARY_KERNEL_HPP +#define CPU_AARCH64_UNI_BINARY_KERNEL_HPP + +#include + +#include "common/c_types_map.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/aarch64/cpu_isa_traits.hpp" +#include "cpu/aarch64/injectors/jit_uni_postops_injector.hpp" +#include "cpu/aarch64/jit_generator.hpp" +#include "cpu/aarch64/jit_primitive_conf.hpp" +#include "cpu/aarch64/utils/jit_io_helper.hpp" + +#include "cpu/cpu_binary_pd.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +using namespace Xbyak_aarch64; + +struct binary_kernel_t : public jit_generator { + using op_t = binary_op_t; + using bcast_t = binary_bcast_t; + + binary_kernel_t(const size_t vlen, const binary_pd_t *pd, + const jit_binary_conf_t conf, bool tail_kernel = false); + ~binary_kernel_t() override = default; + + void operator()(jit_binary_call_s *p) { jit_generator::operator()(p); } + + size_t simd_w() const noexcept { return simd_w_; } + size_t vlen() const noexcept { return vlen_; } + +protected: + size_t get_tail_size() const; + + const size_t vlen_; + const size_t simd_w_; + constexpr static int vmm_start_idx_ = 1; + const binary_pd_t *pd_; + const jit_binary_conf_t conf_; + const bool is_tail_kernel_; + const bool is_src1_outer_dims_tail_; + const size_t tail_size_; + const size_t padding_tail_size_; +}; + +template +struct jit_uni_binary_kernel_t : public binary_kernel_t { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_uni_binary_kernel_t) + + using Vmm = typename cpu_isa_traits::TReg; + + const XReg reg_param_ = abi_param1; + const XReg reg_src0_ = x8; + const XReg reg_src1_ = x9; + const XReg reg_dst_ = x10; + const XReg reg_offt_src0_ = x11; + const XReg reg_outer_dims_range_ = x12; + const XReg reg_offt_src1_ = x1; + const XReg reg_src1_stride_range_ = x15; + const XReg reg_reverse_src1_stride_range_ = x1; + const XReg reg_reverse_spat_offt_ = x13; + const XReg reg_tmp_ = x14; + const XReg reg_tmp1_ = x6; + const XReg reg_elt_inj_table_ = x15; + const XReg reg_off_rhs_postops_ = x2; + const XReg reg_scales_src0_ = x3; + const XReg reg_scales_src1_ = x5; + const XReg reg_offt_dst_ = x2; + const PReg tail_opmask_ = p2; + const PReg cmp_mask = p3; + const PReg full_mask_ = p4; + const Vmm vmm_tail_vmask_ = Vmm(0); + const Vmm vreg_sum_scale_ = Vmm(17); + const VReg xreg_sum_scale_ = VReg(9); + const Vmm vreg_zero_ = Vmm(18); + const Vmm vreg_one_ = Vmm(19); + const Vmm vreg_saturation_ubound_ = Vmm(20); + const Vmm vreg_bcast_src1_ = Vmm(21); + const VReg xreg_bcast_src1_ = VReg(13); + const Vmm vreg_scales_src0_ = Vmm(22); + const Vmm vreg_scales_src1_ = Vmm(23); + + const Vmm vmm_full_mask_ = Vmm(24); + const Vmm vmm_tmp_gather_ = Vmm(25); + const Vmm vmm_indices_ = Vmm(30); + const Vmm vmm_gathered_src_ = Vmm(31); + + const size_t unroll_regs_ = 8; + const size_t offt_src0_; + const size_t offt_src1_; + + static constexpr cpu_isa_t inject_isa = isa; + io::jit_io_multi_dt_helper_t io_; + std::unique_ptr> + postops_injector_; + const PReg elt_inj_opmask_ = p1; + const PReg elt_inj_p_tmp0_ = p2; + const PReg elt_inj_p_all_ = p3; + + void init(); + void init_post_ops_injector(); + void apply_postops(int unroll, bool tail); + void load_kernel_params(); + XReg src0_ptr(size_t offt = 0); + XReg src1_ptr(size_t offt = 0); + XReg dst_ptr(size_t offt = 0); + unsigned int cmp_predicate(alg_kind_t alg); + void perform_op( + const Vmm &v0, const Vmm &v1, const Vmm &s_src0, const Vmm &s_src1); + void prepare_isa_kernel(); + void compute_bcast(bool tail); + void load_src1(const Vmm &vreg_src1, const int offt, bool tail); + void store(int unroll, bool tail); + void compute_dst_body(int unroll, bool tail); + void compute_dst(int unroll, bool tail); + void forward(); + void forward_over_outer_dims(); + void generate() override; + + void compute_cmp_mask(const Xbyak_aarch64::PReg &cmp_dst, + const Vmm &cmp_src, const Vmm &cmp_src2, const unsigned int uimm); + + void push(const XReg ®); + void pop(const XReg ®); + + void uni_broadcast(const Vmm &dst, const Xbyak_aarch64::XReg &addr); + + jit_uni_binary_kernel_t(const binary_pd_t *pd, const jit_binary_conf_t conf, + bool tail_kernel = false); + ~jit_uni_binary_kernel_t() override = default; + + std::map + create_saturation_vmm_map() const; +}; + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_deconv_zp_pad_str_kernel.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_deconv_zp_pad_str_kernel.hpp new file mode 100644 index 0000000000000000000000000000000000000000..f49e28bcc81479fdd4f23d806fa01b3a611a272b --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_deconv_zp_pad_str_kernel.hpp @@ -0,0 +1,124 @@ +/******************************************************************************* +* Copyright 2021-2022 Intel Corporation +* Copyright 2022 FUJITSU LIMITED +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_JIT_UNI_DECONV_ZP_PAD_STR_KERNEL_HPP +#define CPU_AARCH64_JIT_UNI_DECONV_ZP_PAD_STR_KERNEL_HPP + +#include "cpu/aarch64/jit_generator.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +struct jit_conv_conf_t; + +namespace zp { + +struct jit_uni_deconv_zp_pad_str_call_params_t { + const int8_t *wei; + const int32_t *src_zero_point; + int32_t *dst_scratchpad; + bool last_oc_block; +}; + +/* + * Compute zero point source compensation applied during filter application on + * the padding as well as stride holes. + * + * zp_pad_str_compensation = conv(1, weights_s8) * zero_point_source + * + * output_format - dhwc + */ +class jit_uni_deconv_zp_pad_str_kernel_base_t : public jit_generator { +public: + jit_uni_deconv_zp_pad_str_kernel_base_t(const jit_conv_conf_t &jcp); + + void operator()(const jit_uni_deconv_zp_pad_str_call_params_t *params) { + jit_generator::operator()(params); + } + + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_uni_deconv_zp_pad_str_kernel_base_t); + +private: + DNNL_DISALLOW_COPY_AND_ASSIGN(jit_uni_deconv_zp_pad_str_kernel_base_t); + + void generate() override; + void load_addresses(); + void compute(); + virtual void compute_step(const dim_t icb_offset) = 0; + virtual void apply_zero_point() = 0; + virtual void store_result() = 0; + virtual void init() = 0; + +protected: + size_t number_reserved_vmms_ = 0; + size_t reserve_vmm(); + + const jit_conv_conf_t &jcp_; + + const Xbyak_aarch64::XReg ®_src_zp_ = x8; + const Xbyak_aarch64::XReg ®_wei_ = x9; + const Xbyak_aarch64::XReg ®_dst_ = x10; + const Xbyak_aarch64::WReg ®_last_oc_block_ = w12; + const size_t tail_size_; +}; + +template +class jit_uni_deconv_zp_pad_str_kernel_t + : public jit_uni_deconv_zp_pad_str_kernel_base_t { +public: + jit_uni_deconv_zp_pad_str_kernel_t(const jit_conv_conf_t &jcp); + +private: + using TReg = typename cpu_isa_traits::TReg; + + void init() override; + void compute_step(const dim_t icb_offset) override; + void apply_zero_point() override; + void store_result() override; + + uint32_t get_next_vmm_idx(); + + const TReg result_acc_; + const TReg vmm_tmp_; + const TReg vmm_one_bytes_; + const TReg vmm_one_words_; + + const Xbyak_aarch64::PReg &ktail_mask_ = p2; + dim_t current_vmm_; +}; + +bool should_calculate_deconv_zp_src_pad_str_comp( + const jit_conv_conf_t &jcp) noexcept; + +template +jit_uni_deconv_zp_pad_str_kernel_base_t *create_deconv_zp_pad_str_comp_ker( + const jit_conv_conf_t &jcp); + +void compute_deconv_zp_pad_str_comp_ker(const jit_conv_conf_t &jcp_, + const bool with_groups, const memory_desc_wrapper &wei_d, + const int8_t *wei, const int32_t *src_zp, int32_t *dst, + jit_uni_deconv_zp_pad_str_kernel_base_t *ker); + +} // namespace zp +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_dw_conv_kernel_f32.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_dw_conv_kernel_f32.hpp new file mode 100644 index 0000000000000000000000000000000000000000..32314e4e67653856e50926be8262fdd28091e09f --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_dw_conv_kernel_f32.hpp @@ -0,0 +1,268 @@ +/******************************************************************************* +* Copyright 2021-2022 Intel Corporation +* Copyright 2021-2022 FUJITSU LIMITED +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_JIT_UNI_DW_CONV_KERNEL_F32_HPP +#define CPU_AARCH64_JIT_UNI_DW_CONV_KERNEL_F32_HPP + +#include "common/c_types_map.hpp" +#include "common/memory_tracking.hpp" + +#include "cpu/aarch64/jit_generator.hpp" +#include "cpu/aarch64/jit_primitive_conf.hpp" + +#include "cpu/aarch64/injectors/jit_uni_eltwise_injector.hpp" + +using namespace Xbyak_aarch64; + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +template +struct jit_uni_dw_conv_fwd_kernel_f32 : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_uni_dw_conv_fwd_kernel_f32) + + jit_uni_dw_conv_fwd_kernel_f32(jit_conv_conf_t ajcp) + : jcp(ajcp), eltwise_injector_(nullptr) { + if (jcp.with_eltwise) + eltwise_injector_ = new jit_uni_eltwise_injector_f32( + this, jcp.eltwise); + } + + ~jit_uni_dw_conv_fwd_kernel_f32() { delete eltwise_injector_; } + + jit_conv_conf_t jcp; + +private: + using reg64_t = const XReg; + const int vlen = cpu_isa_traits::vlen; + + // dw convolution + reg64_t reg_input = x1; + reg64_t aux_reg_input = x2; + reg64_t reg_kernel = x3; + reg64_t aux_reg_kernel = x5; + reg64_t reg_ch_blocks = x6; + reg64_t reg_output = x7; + reg64_t reg_bias = x8; + reg64_t reg_kh = x9; + reg64_t iter_kh = x10; + reg64_t reg_oi = x11; + reg64_t aux_reg_ch_blocks = x12; + // fused convolution + reg64_t reg_input_buffer_ptr = x13; + reg64_t aux_reg_input_buffer_ptr = x14; + reg64_t reg_iw_offset = reg_input; + + /* Temprary regs */ + reg64_t reg_tmp_imm = x15; + reg64_t reg_kernel_stack = x16; + reg64_t reg_input_stack = x17; + reg64_t reg_output_stack = x27; + reg64_t reg_bias_stack = x19; + reg64_t reg_tmp_addr = x20; + + inline void load_src(int ur_ch_blocks, int ur_w); + inline void compute_loop(int ur_w, int ur_ch_blocks, int pad_l, int pad_r); + inline void ow_loop(int ur_ch_blocks); + inline void apply_filter_unrolled( + int ur_ch_blocks, int ur_w, int pad_l, int pad_r); + inline void apply_activation(int ur_ch_blocks, int ur_w); + inline void store_dst(int ur_ch_blocks, int ur_w); + + inline ZReg get_ker_reg(int idx) { + assert(idx <= 31); + return ZReg(idx + 0); + } + inline ZRegS get_ker_reg_s(int idx) { + assert(idx <= 31); + return ZRegS(idx + 0); + } + inline ZReg get_src_reg(int idx) { + assert((idx + 1) <= 31); + return ZReg(idx + 1); + } + inline ZRegS get_src_reg_s(int idx) { + assert((idx + 1) <= 31); + return ZRegS(idx + 1); + } + + inline ZReg get_acc_reg(int idx) { + assert((idx + 4) <= 31); + return ZReg(idx + 4); + } + inline ZRegS get_acc_reg_s(int idx) { + assert((idx + 4) <= 31); + return ZRegS(idx + 4); + } + + int get_ow_start(int ki, int pad_l) { + return nstl::max(0, + utils::div_up(pad_l - ki * (jcp.dilate_w + 1), jcp.stride_w)); + } + + int get_ow_end(int ur_w, int ki, int pad_r) { + return ur_w + - nstl::max(0, + utils::div_up( + pad_r - (jcp.kw - 1 - ki) * (jcp.dilate_w + 1), + jcp.stride_w)); + } + + inline bool is_src_layout_nxc() { + return utils::one_of(jcp.src_tag, format_tag::ndhwc, format_tag::nhwc, + format_tag::nwc); + } + inline bool is_dst_layout_nxc() { + return utils::one_of(jcp.dst_tag, format_tag::ndhwc, format_tag::nhwc, + format_tag::nwc); + } + + jit_uni_eltwise_injector_f32 *eltwise_injector_; + void generate() override; +}; + +template +struct jit_uni_dw_conv_bwd_data_kernel_f32 : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_uni_dw_conv_bwd_data_kernel_f32) + + jit_uni_dw_conv_bwd_data_kernel_f32(jit_conv_conf_t ajcp) : jcp(ajcp) {} + jit_conv_conf_t jcp; + +private: + using reg64_t = const XReg; + + inline ZReg get_ker_reg(int idx) { return ZReg(idx + 0); } + inline ZReg get_src_reg(int idx) { return ZReg(idx + 1); } + inline ZReg get_acc_reg(int idx) { return ZReg(idx + 4); } + inline ZRegS get_ker_reg_s(int idx) { return ZRegS(idx + 0); } + inline ZRegS get_src_reg_s(int idx) { return ZRegS(idx + 1); } + inline ZRegS get_acc_reg_s(int idx) { return ZRegS(idx + 4); } + + reg64_t reg_ddst = x1; + reg64_t aux_reg_ddst = x2; + reg64_t aux1_reg_ddst = x3; + reg64_t reg_kernel = x5; + reg64_t aux_reg_kernel = x6; + reg64_t aux1_reg_kernel = x7; + reg64_t reg_dsrc = x8; + + reg64_t reg_ur_str_w = x9; + reg64_t reg_ch_blocks = x10; + + reg64_t iter_kh = x11; + reg64_t iter_kw = x12; + reg64_t reg_kh = x13; + reg64_t reg_kw = x14; + + /* Temprary regs */ + reg64_t reg_tmp_imm = x15; + reg64_t reg_tmp_addr = x16; + + inline void loop_body(int ur_ch_blocks); + inline void load_ddst(int ur_ch_blocks, int ur_str_w); + inline void apply_filter(int ur_ch_blocks, int ur_str_w); + inline void store_dsrc(int ur_ch_blocks, int ur_str_w); + + void generate() override; +}; + +template +struct jit_uni_dw_conv_bwd_weights_kernel_f32 : public jit_generator { + + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_uni_dw_conv_bwd_weights_kernel_f32) + + jit_uni_dw_conv_bwd_weights_kernel_f32(jit_conv_conf_t ajcp) : jcp(ajcp) {} + + jit_conv_conf_t jcp; + +private: + using reg64_t = const XReg; + int simd_w = cpu_isa_traits::vlen / sizeof(float); + + inline ZReg get_bias_reg(int idx = 0) { return ZReg(idx); } + inline ZReg get_output_reg(int idx) { return ZReg(idx + 1); } + inline ZReg get_input_reg(int idx) { return ZReg(idx + 5); } + inline ZReg get_acc_reg(int idx) { return ZReg(idx + 2); } + inline ZReg get_aux_reg() { return ZReg(0); } + inline ZRegS get_bias_reg_s(int idx = 0) { return ZRegS(idx); } + inline ZRegS get_output_reg_s(int idx) { return ZRegS(idx + 1); } + inline ZRegS get_input_reg_s(int idx) { return ZRegS(idx + 5); } + inline ZRegS get_acc_reg_s(int idx) { return ZRegS(idx + 2); } + inline ZRegS get_aux_reg_s() { return ZRegS(0); } + + reg64_t reg_tmp_input = x1; + reg64_t reg_tmp_output = x2; + reg64_t reg_tmp_filter = x3; + reg64_t reg_kh_offset = x5; + + /* parameter passed by driver into kernel */ + reg64_t reg_exec_flags = x14; + + reg64_t reg_oh_worksize = x6; + reg64_t reg_oh = x5; + + reg64_t reg_iter_ow_blk = x7; + + reg64_t reg_kh = x8; + reg64_t reg_kh_count = x9; + + /* Base addresses for convolution parameters. */ + reg64_t reg_input_baddr = x10; + reg64_t reg_output_baddr = x11; + reg64_t reg_filter_baddr = x12; + reg64_t reg_bias_baddr = x13; + + /* Temporary regs */ + reg64_t reg_tmp_imm = x15; + reg64_t reg_tmp_addr = x16; + + /* Micro-kernel JIT'ing, fusing 'kw' and 'ow_block' loops into unrolled FMAs + */ + inline void compute_ow_step_unroll( + int unroll_w, int l_pad, int pad_offset, int ow_block); + + /* JIT'ing the outer loops for the micro-kernel -> {kh, oh_block} */ + inline void compute_h_step( + int unroll_w, int l_pad, int pad_offset, int ow_block); + inline void compute_h_loop( + int unroll_w, int l_pad, int pad_offset, int ow_block); + + /* Write 'width' micro-kernel JITs; depending on the padding and convolution + * size, write a micro-kernel for the left ow-block, middle ow-block(s), and + * right ow-block.*/ + inline void compute_ow_block_unroll(); + + inline void compute_zero_filter(); + inline void load_filter(); + inline void zero_filter(); + inline void load_bias(); + inline void zero_bias(); + inline void compute_bias_step_unroll(const int unroll_w); + inline void compute_bias_loop(const int block_size); + inline void store_filter(); + inline void store_bias(); + + void generate() override; +}; +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_dw_conv_kernel_utils.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_dw_conv_kernel_utils.hpp new file mode 100644 index 0000000000000000000000000000000000000000..bd928275f1862168c047b6ab8f6bacdb4a3c4735 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_dw_conv_kernel_utils.hpp @@ -0,0 +1,596 @@ +/******************************************************************************* +* Copyright 2021-2022 Intel Corporation +* Copyright 2021-2022 FUJITSU LIMITED +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_JIT_UNI_DW_CONV_KERNEL_UTILS_HPP +#define CPU_AARCH64_JIT_UNI_DW_CONV_KERNEL_UTILS_HPP + +#include "common/nstl.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "common/c_types_map.hpp" +#include "common/memory_tracking.hpp" + +#include "cpu/aarch64/jit_generator.hpp" +#include "cpu/aarch64/jit_primitive_conf.hpp" +#include "cpu/aarch64/jit_uni_dw_conv_kernel_f32.hpp" + +#include "cpu/aarch64/injectors/jit_uni_eltwise_injector.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +template +struct jit_uni_dw_conv_fwd_kernel { + + jit_uni_dw_conv_fwd_kernel(jit_conv_conf_t ajcp) : ker_(nullptr) { + ker_ = new jit_uni_dw_conv_fwd_kernel_f32(ajcp); + } + status_t create_kernel() { return ker_->create_kernel(); } + ~jit_uni_dw_conv_fwd_kernel() { delete ker_; } + + static bool post_ops_ok(jit_conv_conf_t &jcp, const primitive_attr_t &attr); + + static status_t init_conf(jit_conv_conf_t &jcp, + const convolution_desc_t &cd, memory_desc_t &src_md, + memory_desc_t &weights_md, memory_desc_t &bias_md, + memory_desc_t &dst_md, const primitive_attr_t &attr); + + static void init_scratchpad(memory_tracking::registrar_t &scratchpad, + const jit_conv_conf_t &jcp); + + jit_generator *ker() const { return ker_; } + void operator()(const jit_conv_call_s *p) const { (*ker_)(p); } + +private: + jit_uni_dw_conv_fwd_kernel_f32 *ker_; +}; + +template +bool jit_uni_dw_conv_fwd_kernel::post_ops_ok( + jit_conv_conf_t &jcp, const primitive_attr_t &attr) { + const auto &p = attr.post_ops_; + + auto is_eltwise = [&](int idx) { + return p.entry_[idx].is_eltwise() + && eltwise_injector::is_supported( + isa, p.entry_[idx].eltwise.alg); + }; + auto is_sum = [&](int idx) { return p.entry_[idx].is_sum(); }; + + switch (p.len()) { + case 0: return true; // no post_ops + case 1: return is_eltwise(0) || is_sum(0); // sum OR eltwise + case 2: return is_sum(0) && is_eltwise(1); // sum -> eltwise + default: return false; + } + + return false; +} + +template +status_t jit_uni_dw_conv_fwd_kernel::init_conf( + jit_conv_conf_t &jcp, const convolution_desc_t &cd, + memory_desc_t &src_md, memory_desc_t &weights_md, + memory_desc_t &bias_md, memory_desc_t &dst_md, + const primitive_attr_t &attr) { + + using namespace dnnl::impl::format_tag; + using namespace dnnl::impl::utils; + + const memory_desc_wrapper src_d(&src_md); + const memory_desc_wrapper weights_d(&weights_md); + const memory_desc_wrapper dst_d(&dst_md); + const memory_desc_wrapper bias_d(&bias_md); + + const int ndims = src_d.ndims(); + // Currently this kernel only supports 2D convolutions. + if (ndims != 4) return status::unimplemented; + + const auto blocked_tag = isa == sve_512 ? nChw16c : nChw8c; + const auto wei_tag = isa == sve_512 ? Goihw16g : Goihw8g; + const auto nxc_tag = nhwc; + jcp.with_bias = cd.bias_desc.format_kind != format_kind::undef; + if ((blocked_tag != nChw16c) || (wei_tag != Goihw16g)) + return status::unimplemented; + + if (src_d.format_kind() == format_kind::any) { + CHECK(memory_desc_init_by_tag(src_md, blocked_tag)); + jcp.src_tag = blocked_tag; + } else { + jcp.src_tag = src_d.matches_one_of_tag(blocked_tag, nxc_tag); + } + + if (weights_d.format_kind() == format_kind::any) { + CHECK(memory_desc_init_by_tag(weights_md, wei_tag)); + jcp.wei_tag = wei_tag; + } else { + jcp.wei_tag = weights_d.matches_one_of_tag(wei_tag); + } + + if (dst_d.format_kind() == format_kind::any) { + CHECK(memory_desc_init_by_tag(dst_md, blocked_tag)); + jcp.dst_tag = blocked_tag; + } else { + jcp.dst_tag = dst_d.matches_one_of_tag(blocked_tag, nxc_tag); + } + + if (jcp.with_bias) { + if (bias_d.format_kind() == format_kind::any) + CHECK(memory_desc_init_by_tag(bias_md, format_tag::x)); + } + + if (jcp.dst_tag != jcp.src_tag) return status::unimplemented; + const auto data_tag = jcp.src_tag; + const bool is_data_layout_nxc = data_tag == nxc_tag; + + jcp.dst_dt = cd.dst_desc.data_type; + jcp.isa = isa; + + if (!mayiuse(isa)) return status::unimplemented; + + const int simd_w = isa == sve_512 ? 16 : 8; + if (simd_w != 16) return status::unimplemented; + + jcp.prop_kind = cd.prop_kind; + + const bool with_groups = weights_d.ndims() == src_d.ndims() + 1; + if (!with_groups) return status::unimplemented; + + jcp.ngroups = weights_d.dims()[0]; + jcp.mb = src_d.dims()[0]; + + jcp.oc = dst_d.dims()[1]; + jcp.oc_without_padding = jcp.oc; + jcp.ic = src_d.dims()[1]; + + jcp.ih = src_d.dims()[2]; + jcp.iw = src_d.dims()[3]; + jcp.oh = dst_d.dims()[2]; + jcp.ow = dst_d.dims()[3]; + + jcp.kh = weights_d.dims()[3]; + jcp.kw = weights_d.dims()[4]; + + jcp.t_pad = cd.padding[0][0]; + jcp.l_pad = cd.padding[0][1]; + jcp.b_pad = cd.padding[1][0]; + jcp.r_pad = cd.padding[1][1]; + + jcp.stride_h = cd.strides[0]; + jcp.stride_w = cd.strides[1]; + + jcp.dilate_h = cd.dilates[0]; + jcp.dilate_w = cd.dilates[1]; + + int ext_kw = calculate_extended_filter_size(jcp.kw, jcp.dilate_w); + int ext_kh = calculate_extended_filter_size(jcp.kh, jcp.dilate_h); + jcp.r_pad = calculate_end_padding( + jcp.l_pad, jcp.ow, jcp.iw, jcp.stride_w, ext_kw); + jcp.b_pad = calculate_end_padding( + jcp.t_pad, jcp.oh, jcp.ih, jcp.stride_h, ext_kh); + bool kernel_outside_src = false || ext_kw <= jcp.l_pad + || ext_kw <= jcp.r_pad || ext_kh <= jcp.t_pad + || ext_kh <= jcp.b_pad; + if (kernel_outside_src) return status::unimplemented; + + jcp.typesize_out = types::data_type_size(dst_d.data_type()); + jcp.typesize_in = types::data_type_size(src_d.data_type()); + + jcp.loop_order = loop_ngcw; + + jcp.ur_w = isa == sve_512 ? 6 : isa == sve_256 ? 4 : 3; + jcp.ur_w = nstl::min(jcp.ur_w, jcp.ow); + + jcp.ch_block = simd_w; + jcp.nb_ch = div_up(jcp.oc, jcp.ch_block); + jcp.nb_ch_blocking = isa == sve_512 ? 4 : isa == sve_256 ? 3 : 2; + if (jcp.nb_ch < jcp.nb_ch_blocking) jcp.nb_ch_blocking = jcp.nb_ch; + + if (is_data_layout_nxc) { + jcp.loop_order = loop_nhwcg; + bool cache_aliasing + = (jcp.ngroups * jcp.iw * jcp.typesize_in) % 1024 == 0; + if (cache_aliasing) { + // currently only tuned for mobilenet-v1 shapes + const int limit = jcp.ow > 7 ? 7 : 4; + jcp.ur_w = nstl::min(jcp.ur_w, limit); + } + } else { + const size_t max_ch_off + = static_cast(jcp.nb_ch_blocking - 1) * jcp.ch_block; + constexpr size_t max_ex_off = 0; + + // check that input offsets fit into s32 + const size_t max_ic_off = max_ch_off * jcp.ih * jcp.iw; + const size_t max_iw_idx + = static_cast(jcp.ur_w - 1) * jcp.stride_w + + (ext_kw - 1); + const size_t max_iw_off = max_iw_idx * jcp.ch_block; + const size_t max_input_offset + = (max_ic_off + max_iw_off + max_ex_off) * jcp.typesize_in; + if (max_input_offset > INT_MAX) return status::unimplemented; + + // check that output offsets fit into s32 + const size_t max_oc_off = max_ch_off * jcp.oh * jcp.ow; + const size_t max_ow_off + = static_cast(jcp.ur_w - 1) * jcp.ch_block; + const size_t max_output_offset + = (max_oc_off + max_ow_off + max_ex_off) * jcp.typesize_out; + if (max_output_offset > INT_MAX) return status::unimplemented; + } + + jcp.ur_w_tail = jcp.ow % jcp.ur_w; + + int r_pad_no_tail = nstl::max(0, + calculate_end_padding(jcp.l_pad, jcp.ow - jcp.ur_w_tail, jcp.iw, + jcp.stride_w, ext_kw)); + if (jcp.l_pad > jcp.ur_w || r_pad_no_tail > jcp.ur_w) + return status::unimplemented; + + if (!post_ops_ok(jcp, attr)) return status::unimplemented; + + const auto &p = attr.post_ops_; + jcp.with_sum = p.find(primitive_kind::sum) != -1; + const int eltwise_ind = p.find(primitive_kind::eltwise); + jcp.with_eltwise = eltwise_ind != -1; + + if (jcp.with_eltwise) { + jcp.eltwise = p.entry_[eltwise_ind].eltwise; + if (jcp.eltwise.alg == alg_kind::eltwise_pow) + return status::unimplemented; + if (dst_d.data_type() == data_type::s32) return status::unimplemented; + } + bool ok_to_pad_channels = true && jcp.oc == jcp.ngroups + && jcp.ic == jcp.ngroups && isa == sve_512; + if (ok_to_pad_channels) { + jcp.oc = rnd_up(jcp.oc, simd_w); + jcp.ic = rnd_up(jcp.oc, simd_w); + jcp.ngroups = rnd_up(jcp.ngroups, simd_w); + } + + bool args_ok = true && jcp.oc == jcp.ngroups && jcp.ic == jcp.ngroups + && jcp.ngroups % simd_w == 0 && jcp.wei_tag == wei_tag + && data_tag != format_tag::undef && jcp.ic <= src_d.padded_dims()[1] + && jcp.oc <= dst_d.padded_dims()[1] + && jcp.ngroups <= weights_d.padded_dims()[0]; + if (!args_ok) return status::unimplemented; + + jcp.bia_dt = jcp.with_bias ? cd.bias_desc.data_type : data_type::undef; + + return status::success; +} + +template +void jit_uni_dw_conv_fwd_kernel::init_scratchpad( + memory_tracking::registrar_t &scratchpad, const jit_conv_conf_t &jcp) { + using namespace dnnl::impl::memory_tracking::names; + if (jcp.with_bias && jcp.oc_without_padding != jcp.oc) + scratchpad.book(key_conv_padded_bias, jcp.oc); +} + +template struct jit_uni_dw_conv_fwd_kernel; + +template +struct jit_uni_dw_conv_bwd_data_kernel { + + jit_uni_dw_conv_bwd_data_kernel(jit_conv_conf_t ajcp) : ker_(nullptr) { + ker_ = new jit_uni_dw_conv_bwd_data_kernel_f32(ajcp); + } + + status_t create_kernel() { return ker_->create_kernel(); } + ~jit_uni_dw_conv_bwd_data_kernel() { delete ker_; } + + static status_t init_conf(jit_conv_conf_t &jcp, + const convolution_desc_t &cd, const memory_desc_wrapper &diff_src_d, + const memory_desc_wrapper &weights_d, + const memory_desc_wrapper &diff_dst_d); + + static void init_scratchpad(memory_tracking::registrar_t &scratchpad, + const jit_conv_conf_t &jcp); + + void operator()(const jit_conv_call_s *p) const { (*ker_)(p); } + +private: + jit_uni_dw_conv_bwd_data_kernel_f32 *ker_; + + DNNL_DISALLOW_COPY_AND_ASSIGN(jit_uni_dw_conv_bwd_data_kernel); +}; + +template +status_t jit_uni_dw_conv_bwd_data_kernel::init_conf( + jit_conv_conf_t &jcp, const convolution_desc_t &cd, + const memory_desc_wrapper &diff_src_d, + const memory_desc_wrapper &weights_d, + const memory_desc_wrapper &diff_dst_d) { + using namespace dnnl::impl::format_tag; + using namespace dnnl::impl::utils; + + jcp.dsrc_dt = cd.diff_src_desc.data_type; + jcp.isa = isa; + + if (!mayiuse(isa)) return status::unimplemented; + + const int simd_w = isa == sve_512 ? 16 : 8; + + const bool with_groups = weights_d.ndims() == diff_src_d.ndims() + 1; + if (!with_groups) return status::unimplemented; + + jcp.ngroups = weights_d.dims()[0]; + jcp.mb = diff_src_d.dims()[0]; + + jcp.oc = diff_dst_d.dims()[1]; + jcp.oc_without_padding = jcp.oc; + jcp.ic = diff_src_d.dims()[1]; + + jcp.ih = diff_src_d.dims()[2]; + jcp.iw = diff_src_d.dims()[3]; + jcp.oh = diff_dst_d.dims()[2]; + jcp.ow = diff_dst_d.dims()[3]; + + jcp.kh = weights_d.dims()[3]; + jcp.kw = weights_d.dims()[4]; + + jcp.t_pad = cd.padding[0][0]; + jcp.l_pad = cd.padding[0][1]; + jcp.b_pad = cd.padding[1][0]; + jcp.r_pad = cd.padding[1][1]; + + jcp.stride_h = cd.strides[0]; + jcp.stride_w = cd.strides[1]; + + jcp.dilate_h = cd.dilates[0]; + jcp.dilate_w = cd.dilates[1]; + int ext_kw = calculate_extended_filter_size(jcp.kw, jcp.dilate_w); + int ext_kh = calculate_extended_filter_size(jcp.kh, jcp.dilate_h); + jcp.r_pad = calculate_end_padding( + jcp.l_pad, jcp.ow, jcp.iw, jcp.stride_w, ext_kw); + jcp.b_pad = calculate_end_padding( + jcp.t_pad, jcp.oh, jcp.ih, jcp.stride_h, ext_kh); + bool kernel_outside_src = false || ext_kw <= jcp.l_pad + || ext_kw <= jcp.r_pad || ext_kh <= jcp.t_pad + || ext_kh <= jcp.b_pad; + if (kernel_outside_src) { return status::unimplemented; } + + jcp.ihp = jcp.ih + jcp.t_pad + jcp.b_pad; + jcp.iwp = jcp.iw + jcp.l_pad + jcp.r_pad; + + bool ok_to_pad_channels = true && jcp.oc == jcp.ngroups + && jcp.ic == jcp.ngroups && isa == sve_512; + if (ok_to_pad_channels) { + jcp.oc = rnd_up(jcp.oc, simd_w); + jcp.ic = rnd_up(jcp.oc, simd_w); + jcp.ngroups = rnd_up(jcp.ngroups, simd_w); + } + + auto dat_tag = isa == sve_512 ? nChw16c : nChw8c; + auto wei_tag = isa == sve_512 ? Goihw16g : Goihw8g; + + jcp.src_tag = diff_src_d.matches_one_of_tag(dat_tag); + jcp.wei_tag = weights_d.matches_one_of_tag(wei_tag); + jcp.dst_tag = diff_dst_d.matches_one_of_tag(dat_tag); + + bool args_ok = true && jcp.oc == jcp.ngroups && jcp.ic == jcp.ngroups + && jcp.ngroups % simd_w == 0 && jcp.src_tag == dat_tag + && jcp.wei_tag == wei_tag && jcp.dst_tag == dat_tag + && jcp.dilate_h == 0 && jcp.dilate_w == 0 + && jcp.oh == (jcp.ihp - jcp.kh) / jcp.stride_h + 1 + && jcp.ow == (jcp.iwp - jcp.kw) / jcp.stride_w + 1 + && jcp.ic <= diff_src_d.padded_dims()[1] + && jcp.oc <= diff_dst_d.padded_dims()[1] + && jcp.ngroups <= weights_d.padded_dims()[0]; + if (!args_ok) return status::unimplemented; + + jcp.typesize_out = types::data_type_size(diff_src_d.data_type()); + jcp.typesize_in = types::data_type_size(diff_dst_d.data_type()); + + jcp.ur_w = isa == sve_512 ? 6 : isa == sve_256 ? 4 : 3; + + jcp.ch_block = simd_w; + jcp.nb_ch = jcp.ic / jcp.ch_block; + jcp.nb_ch_blocking = isa == sve_512 ? 4 : isa == sve_256 ? 3 : 2; + if (jcp.nb_ch < jcp.nb_ch_blocking) jcp.nb_ch_blocking = jcp.nb_ch; + + return status::success; +} + +template +void jit_uni_dw_conv_bwd_data_kernel::init_scratchpad( + memory_tracking::registrar_t &scratchpad, const jit_conv_conf_t &jcp) { + UNUSED(scratchpad); + UNUSED(jcp); +} + +template struct jit_uni_dw_conv_bwd_data_kernel; + +template +struct jit_uni_dw_conv_bwd_weights_kernel { + + jit_uni_dw_conv_bwd_weights_kernel(jit_conv_conf_t ajcp) : ker_(nullptr) { + ker_ = new jit_uni_dw_conv_bwd_weights_kernel_f32(ajcp); + } + + status_t create_kernel() { return ker_->create_kernel(); } + ~jit_uni_dw_conv_bwd_weights_kernel() { delete ker_; } + + static status_t init_conf(jit_conv_conf_t &jcp, + const convolution_desc_t &cd, const memory_desc_wrapper &src_d, + const memory_desc_wrapper &diff_weights_d, + const memory_desc_wrapper &diff_dst_d, int nthreads); + + static void init_scratchpad(memory_tracking::registrar_t &scratchpad, + const jit_conv_conf_t &jcp); + + static void balance(jit_conv_conf_t &jcp, int nthreads); + + void operator()(const jit_dw_conv_call_s *p) const { (*ker_)(p); } + +private: + jit_uni_dw_conv_bwd_weights_kernel_f32 *ker_; +}; + +template +status_t jit_uni_dw_conv_bwd_weights_kernel::init_conf( + jit_conv_conf_t &jcp, const convolution_desc_t &cd, + const memory_desc_wrapper &src_d, + const memory_desc_wrapper &diff_weights_d, + const memory_desc_wrapper &diff_dst_d, int nthreads) { + using namespace dnnl::impl::format_tag; + using namespace dnnl::impl::utils; + + jcp.dwei_dt = cd.diff_weights_desc.data_type; + jcp.isa = isa; + + if (!mayiuse(isa)) return status::unimplemented; + + jcp.ngroups = diff_weights_d.dims()[0]; + jcp.oc = diff_dst_d.dims()[1] / jcp.ngroups; + jcp.ic = src_d.dims()[1] / jcp.ngroups; + + const bool with_groups = diff_weights_d.ndims() == src_d.ndims() + 1; + + jcp.is_depthwise = true && with_groups && everyone_is(1, jcp.oc, jcp.ic); + + if (!jcp.is_depthwise) return status::unimplemented; + + jcp.ch_block = isa == sve_512 ? 16 : 8; + jcp.simd_w = jcp.ch_block; + + jcp.mb = src_d.dims()[0]; + + jcp.ih = src_d.dims()[2]; + jcp.iw = src_d.dims()[3]; + jcp.oh = diff_dst_d.dims()[2]; + jcp.ow = diff_dst_d.dims()[3]; + + jcp.kh = diff_weights_d.dims()[3]; + jcp.kw = diff_weights_d.dims()[4]; + + jcp.stride_h = cd.strides[0]; + jcp.stride_w = cd.strides[1]; + + jcp.t_pad = cd.padding[0][0]; + jcp.b_pad = cd.padding[1][0]; + + jcp.l_pad = cd.padding[0][1]; + jcp.r_pad = cd.padding[1][1]; + + jcp.dilate_h = cd.dilates[0]; + jcp.dilate_w = cd.dilates[1]; + + jcp.ihp = jcp.ih + jcp.t_pad + jcp.b_pad; + jcp.iwp = jcp.iw + jcp.l_pad + jcp.r_pad; + + jcp.with_bias = cd.diff_bias_desc.format_kind != format_kind::undef; + + auto dat_tag = isa == sve_512 ? nChw16c : nChw8c; + auto wei_tag = isa == sve_512 ? Goihw16g : Goihw8g; + + jcp.src_tag = src_d.matches_one_of_tag(dat_tag); + jcp.wei_tag = diff_weights_d.matches_one_of_tag(wei_tag); + jcp.dst_tag = diff_dst_d.matches_one_of_tag(dat_tag); + + bool args_ok = true && jcp.src_tag == dat_tag && jcp.wei_tag == wei_tag + && jcp.dst_tag == dat_tag && jcp.ngroups % jcp.ch_block == 0 + && jcp.dilate_h == 0 && jcp.dilate_w == 0 && jcp.kw <= 3 + && jcp.stride_w <= jcp.kw // no gaps in kernel + && jcp.oh == (jcp.ihp - jcp.kh) / jcp.stride_h + 1 + && jcp.ow == (jcp.iwp - jcp.kw) / jcp.stride_w + 1; + if (!args_ok) return status::unimplemented; + + jcp.nb_ch = jcp.ngroups / jcp.ch_block; + + /* kernel applicability check wrt boundaries + * the conditions are quite general across the kernels we have, + * but ideally the check should belong to a specific kernel... */ + const int max_hpad = (jcp.kh - 1 + 1) / 2; + const int max_wpad = (jcp.kw - 1 + 1) / 2; + const int min_ih = jcp.kh + nstl::modulo(-jcp.t_pad, jcp.stride_h); + const bool boundaries_ok = true && jcp.t_pad <= max_hpad + && jcp.b_pad <= max_hpad && jcp.l_pad <= max_wpad + && jcp.r_pad <= max_wpad + // input must fully accommodate the filter + && jcp.ih >= min_ih + // non-unit padding must be a multiple of the stride + && IMPLICATION(jcp.t_pad > 1, jcp.t_pad % jcp.stride_h == 0) + && IMPLICATION(jcp.b_pad > 1, jcp.b_pad % jcp.stride_h == 0); + if (!boundaries_ok) return status::unimplemented; + + /* BF16: accumulation of output happens in f32, down-conversion to bf16 + * happens during the reduction phase. */ + jcp.typesize_out = sizeof(float); + jcp.typesize_in = types::data_type_size(src_d.data_type()); + jcp.bia_dt = jcp.with_bias ? cd.diff_bias_desc.data_type : data_type::undef; + + balance(jcp, nthreads); + + return status::success; +} + +template +void jit_uni_dw_conv_bwd_weights_kernel::init_scratchpad( + memory_tracking::registrar_t &scratchpad, const jit_conv_conf_t &jcp) { + using namespace dnnl::impl::memory_tracking::names; + /* Notes: if splitting thread work on 'mb', then a reduction has to take + * place. Hence, book a per-thread, local weights-buffer for the + * reduction */ + if (jcp.nthr_mb > 1) { + const size_t mb = jcp.dwei_dt == data_type::bf16 ? jcp.nthr_mb + : jcp.nthr_mb - 1; + const size_t wei_size = jcp.ngroups * jcp.kh * jcp.kw; + scratchpad.book(key_conv_wei_reduction, wei_size * mb); + + if (jcp.with_bias) + scratchpad.book( + key_conv_bia_reduction, jcp.ngroups * (jcp.nthr_mb - 1)); + } else if (jcp.nthr_mb == 1 && jcp.dwei_dt == data_type::bf16) { + const size_t wei_size = jcp.ngroups * jcp.kh * jcp.kw; + scratchpad.book(key_conv_wei_reduction, wei_size); + } + if (jcp.bia_dt == data_type::bf16) + scratchpad.book(key_conv_bias_bf16_convert_wsp, jcp.ngroups); +} + +template +void jit_uni_dw_conv_bwd_weights_kernel::balance( + jit_conv_conf_t &jcp, int nthreads) { + jcp.nthr = nthreads; + jcp.nthr_g = jcp.nthr_mb = 1; + + /* Basic-Heuristics for parallel strategy: + * 1) Tries to parallel on the number of Groups (g) where tasks are + * independent. Otherwise, + * 2) Tries to split the work across g and MiniBatch (mb). + * Parallelizing on mb requires computing a reduction for weights. + * + * NOTE: because of 'task partitioning' scheme, there will be unbalanced + * per-thread load when the number of threads is high (e.g. > 16). + */ + jcp.nthr_g = nstl::min(jcp.nb_ch, jcp.nthr); + jcp.nthr_mb = nstl::min(nstl::max(1, jcp.nthr / jcp.nthr_g), jcp.mb); + + jcp.nthr = jcp.nthr_g * jcp.nthr_mb; +} + +template struct jit_uni_dw_conv_bwd_weights_kernel; +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl +#endif /* CPU_X64_JIT_UNI_DW_CONV_KERNEL_UTILS_HPP */ diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_dw_convolution.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_dw_convolution.hpp new file mode 100644 index 0000000000000000000000000000000000000000..329446d288ec27ea9aba6971b1e550d729ce8e47 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_dw_convolution.hpp @@ -0,0 +1,277 @@ +/******************************************************************************* +* Copyright 2021 Intel Corporation +* Copyright 2021 FUJITSU LIMITED +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_JIT_UNI_DW_CONVOLUTION_HPP +#define CPU_AARCH64_JIT_UNI_DW_CONVOLUTION_HPP + +#include "common/c_types_map.hpp" +#include "common/memory_tracking.hpp" +#include "common/primitive.hpp" + +#include "cpu/aarch64/cpu_barrier.hpp" +#include "cpu/aarch64/cpu_reducer.hpp" +#include "cpu/cpu_convolution_pd.hpp" + +#include "cpu/aarch64/jit_uni_dw_conv_kernel_utils.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +template +struct jit_uni_dw_convolution_fwd_t : public primitive_t { + struct pd_t : public cpu_convolution_fwd_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const typename pd_t::base_class *hint_fwd_pd) + : cpu_convolution_fwd_pd_t(adesc, attr, hint_fwd_pd), jcp_() {} + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit_dw:", jcp_.isa, ""), + jit_uni_dw_convolution_fwd_t); + + status_t init(engine_t *engine) { + bool ok = true && is_fwd() + && set_default_alg_kind(alg_kind::convolution_direct) + && expect_data_types(src_type, src_type, data_type::undef, + dst_type, data_type::f32) + && IMPLICATION(this->with_bias(), + utils::one_of(this->desc()->bias_desc.data_type, + data_type::f32, data_type::bf16)) + && attr()->has_default_values( + primitive_attr_t::skip_mask_t::post_ops, dst_type) + && !has_zero_dim_memory(); + if (!ok) return status::unimplemented; + + status_t status + = jit_uni_dw_conv_fwd_kernel::init_conf(jcp_, + *desc(), src_md_, weights_md_, bias_md_, dst_md_, + *attr()); + if (status != status::success) return status; + + auto scratchpad = scratchpad_registry().registrar(); + jit_uni_dw_conv_fwd_kernel::init_scratchpad( + scratchpad, jcp_); + + return status::success; + } + + jit_conv_conf_t jcp_; + }; + + jit_uni_dw_convolution_fwd_t(const pd_t *apd) : primitive_t(apd) {} + + typedef typename prec_traits::type f32_data_t; + typedef typename prec_traits::type bf16_data_t; + typedef typename prec_traits::type data_t; + typedef typename prec_traits::type dst_data_t; + + status_t init(engine_t *engine) override { + CHECK(safe_ptr_assign(kernel_, + new jit_uni_dw_conv_fwd_kernel(pd()->jcp_))); + return kernel_->create_kernel(); + } + + status_t execute(const exec_ctx_t &ctx) const override { + execute_forward(ctx); + return status::success; + } + +private: + void execute_forward(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr> kernel_; +}; + +using jit_sve_512_dw_convolution_fwd_t + = jit_uni_dw_convolution_fwd_t; + +template +struct jit_uni_dw_convolution_bwd_data_t : public primitive_t { + struct pd_t : public cpu_convolution_bwd_data_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const convolution_fwd_pd_t *hint_fwd_pd) + : cpu_convolution_bwd_data_pd_t(adesc, attr, hint_fwd_pd), jcp_() {} + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit_dw:", jcp_.isa, ""), + jit_uni_dw_convolution_bwd_data_t); + + status_t init(engine_t *engine) { + bool ok = true && desc()->prop_kind == prop_kind::backward_data + && set_default_alg_kind(alg_kind::convolution_direct) + && expect_data_types(diff_src_type, diff_dst_type, + data_type::undef, diff_dst_type, data_type::f32) + && attr()->has_default_values() && !has_zero_dim_memory() + && set_default_formats(); + + if (!ok) return status::unimplemented; + + status_t status = jit_uni_dw_conv_bwd_data_kernel::init_conf(jcp_, *desc(), *diff_src_md(), + *weights_md(), *diff_dst_md()); + if (status != status::success) return status; + + auto scratchpad = scratchpad_registry().registrar(); + jit_uni_dw_conv_bwd_data_kernel::init_scratchpad(scratchpad, jcp_); + + return status::success; + } + + jit_conv_conf_t jcp_; + + protected: + bool set_default_formats() { + using namespace format_tag; + + auto dat_tag = nChw16c; + auto wei_tag = Goihw16g; + + return set_default_formats_common(dat_tag, wei_tag, dat_tag); + } + }; + + jit_uni_dw_convolution_bwd_data_t(const pd_t *apd) : primitive_t(apd) {} + + typedef typename prec_traits::type diff_src_data_t; + typedef typename prec_traits::type diff_dst_data_t; + typedef typename prec_traits::type wei_data_t; + + status_t init(engine_t *engine) override { + CHECK(safe_ptr_assign(kernel_, + new jit_uni_dw_conv_bwd_data_kernel( + pd()->jcp_))); + return kernel_->create_kernel(); + } + + status_t execute(const exec_ctx_t &ctx) const override { + execute_backward_data(ctx); + return status::success; + } + +private: + void execute_backward_data(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr> + kernel_; +}; + +using jit_sve_512_dw_convolution_bwd_data_t + = jit_uni_dw_convolution_bwd_data_t; + +template +struct jit_uni_dw_convolution_bwd_weights_t : public primitive_t { + struct pd_t : public cpu_convolution_bwd_weights_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const convolution_fwd_pd_t *hint_fwd_pd) + : cpu_convolution_bwd_weights_pd_t(adesc, attr, hint_fwd_pd) + , jcp_() {} + using jit_uni_dw_convolution_bwd_weights + = jit_uni_dw_convolution_bwd_weights_t; + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit_dw:", jcp_.isa, ""), + jit_uni_dw_convolution_bwd_weights); + + status_t init(engine_t *engine) { + bool ok = true && desc()->prop_kind == prop_kind::backward_weights + && set_default_alg_kind(alg_kind::convolution_direct) + && expect_data_types(src_type, diff_weights_type, + data_type::undef, src_type, data_type::f32) + && IMPLICATION(this->with_bias(), + utils::one_of( + this->desc()->diff_bias_desc.data_type, + data_type::f32, data_type::bf16)) + && attr()->has_default_values() && !has_zero_dim_memory() + && set_default_formats(); + if (!ok) return status::unimplemented; + + const int max_threads + = dnnl_in_parallel() ? 1 : dnnl_get_max_threads(); + + status_t status = jit_uni_dw_conv_bwd_weights_kernel::init_conf(jcp_, *desc(), *src_md(), + *diff_weights_md(), *diff_dst_md(), max_threads); + if (status != status::success) return status; + + auto scratchpad = scratchpad_registry().registrar(); + jit_uni_dw_conv_bwd_weights_kernel::init_scratchpad( + scratchpad, jcp_); + + return status::success; + } + + jit_conv_conf_t jcp_; + + protected: + bool set_default_formats() { + using namespace format_tag; + + auto dat_tag = isa == sve_512 ? nChw16c : nChw8c; + auto wei_tag = isa == sve_512 ? Goihw16g : Goihw8g; + + return set_default_formats_common(dat_tag, wei_tag, dat_tag); + } + }; + + jit_uni_dw_convolution_bwd_weights_t(const pd_t *apd); + + typedef typename prec_traits::type bf16_data_t; + typedef typename prec_traits::type f32_data_t; + typedef typename prec_traits::type src_data_t; + typedef typename prec_traits::type diff_dst_data_t; + typedef typename prec_traits::type diff_weights_data_t; + + status_t init(engine_t *engine) override { + CHECK(safe_ptr_assign(kernel_, + new jit_uni_dw_conv_bwd_weights_kernel( + pd()->jcp_))); + CHECK(kernel_->create_kernel()); + + if (pd()->jcp_.nthr_mb > 1) { + CHECK(safe_ptr_assign( + acc_ker_, new cpu_accumulator_1d_t())); + CHECK(acc_ker_->create_kernel()); + } + return status::success; + } + + status_t execute(const exec_ctx_t &ctx) const override { + execute_backward_weights(ctx); + execute_reduction(ctx); + return status::success; + } + +private: + void execute_backward_weights(const exec_ctx_t &ctx) const; + void execute_reduction(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr> acc_ker_; + std::unique_ptr> kernel_; +}; + +using jit_sve_512_dw_convolution_bwd_weights_t + = jit_uni_dw_convolution_bwd_weights_t; +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_eltwise.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_eltwise.hpp new file mode 100644 index 0000000000000000000000000000000000000000..97ee5ed4c11455526a0d3ce8f59fb5b5a8bdbc6f --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_eltwise.hpp @@ -0,0 +1,94 @@ +/******************************************************************************* +* Copyright 2017-2021 Intel Corporation +* Copyright 2021 FUJITSU LIMITED +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_JIT_UNI_ELTWISE_HPP +#define CPU_AARCH64_JIT_UNI_ELTWISE_HPP + +#include + +#include "common/c_types_map.hpp" +#include "common/primitive.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_eltwise_pd.hpp" + +#include "cpu/aarch64/cpu_isa_traits.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +struct jit_uni_eltwise_kernel; + +template +struct jit_uni_eltwise_fwd_t : public primitive_t { + struct pd_t : public cpu_eltwise_fwd_pd_t { + using cpu_eltwise_fwd_pd_t::cpu_eltwise_fwd_pd_t; + + DECLARE_COMMON_PD_T( + JIT_IMPL_NAME_HELPER("jit:", isa, ""), jit_uni_eltwise_fwd_t); + + status_t init(engine_t *engine); + }; + + jit_uni_eltwise_fwd_t(const pd_t *apd); + virtual ~jit_uni_eltwise_fwd_t(); + + typedef typename prec_traits::type data_t; + + status_t init(engine_t *engine) override; + + status_t execute(const exec_ctx_t &ctx) const override; + +private: + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + std::unique_ptr kernel_; +}; + +template +struct jit_uni_eltwise_bwd_t : public primitive_t { + struct pd_t : public cpu_eltwise_bwd_pd_t { + using cpu_eltwise_bwd_pd_t::cpu_eltwise_bwd_pd_t; + + DECLARE_COMMON_PD_T( + JIT_IMPL_NAME_HELPER("jit:", isa, ""), jit_uni_eltwise_bwd_t); + + status_t init(engine_t *engine); + }; + + jit_uni_eltwise_bwd_t(const pd_t *apd); + virtual ~jit_uni_eltwise_bwd_t(); + + typedef typename prec_traits::type data_t; + + status_t init(engine_t *engine) override; + + status_t execute(const exec_ctx_t &ctx) const override; + +private: + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + std::unique_ptr kernel_; +}; + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_eltwise_int.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_eltwise_int.hpp new file mode 100644 index 0000000000000000000000000000000000000000..7f646a2275a7d104c0af200e2bb7dca17f6cf772 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_eltwise_int.hpp @@ -0,0 +1,72 @@ +/******************************************************************************* +* Copyright 2021 Intel Corporation +* Copyright 2021 FUJITSU LIMITED +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_JIT_UNI_ELTWISE_INT_HPP +#define CPU_AARCH64_JIT_UNI_ELTWISE_INT_HPP + +#include + +#include "common/c_types_map.hpp" +#include "common/primitive.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_eltwise_pd.hpp" + +#include "cpu/aarch64/cpu_isa_traits.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +struct jit_uni_eltwise_int_kernel; + +template +struct jit_uni_eltwise_int_fwd_t : public primitive_t { + struct pd_t : public cpu_eltwise_fwd_pd_t { + using cpu_eltwise_fwd_pd_t::cpu_eltwise_fwd_pd_t; + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit_int8:", isa, ""), + jit_uni_eltwise_int_fwd_t); + + status_t init(engine_t *engine); + }; + + jit_uni_eltwise_int_fwd_t(const pd_t *apd); + ~jit_uni_eltwise_int_fwd_t(); + + typedef typename prec_traits::type data_t; + + status_t init(engine_t *engine) override; + + status_t execute(const exec_ctx_t &ctx) const override { + return execute_forward(ctx); + } + +private: + status_t execute_forward(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + jit_uni_eltwise_int_kernel *kernel_ = nullptr; +}; + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_i8i8_pooling.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_i8i8_pooling.hpp new file mode 100644 index 0000000000000000000000000000000000000000..3ef662e2eb5d026324a5ec69f95c8f580123ee96 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_i8i8_pooling.hpp @@ -0,0 +1,99 @@ +/******************************************************************************* +* Copyright 2020 Intel Corporation +* Copyright 2020-2021 FUJITSU LIMITED +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_JIT_UNI_I8I8_POOLING_HPP +#define CPU_AARCH64_JIT_UNI_I8I8_POOLING_HPP + +#include "common/c_types_map.hpp" +#include "common/primitive.hpp" +#include "common/type_helpers.hpp" + +#include "cpu/cpu_pooling_pd.hpp" + +#include "cpu/aarch64/cpu_isa_traits.hpp" +#include "cpu/aarch64/jit_primitive_conf.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +template +struct jit_uni_i8i8_pooling_fwd_ker_t; + +template +struct jit_uni_i8i8_pooling_fwd_t : public primitive_t { + struct pd_t : public cpu_pooling_fwd_pd_t { + using cpu_pooling_fwd_pd_t::cpu_pooling_fwd_pd_t; + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit_int:", isa, ""), + jit_uni_i8i8_pooling_fwd_t); + + status_t init(engine_t *engine) { + bool ok = true && mayiuse(isa) && utils::one_of(ndims(), 3, 4, 5) + && set_default_params() == status::success + && desc()->prop_kind == prop_kind::forward_inference + && utils::one_of(desc()->alg_kind, alg_kind::pooling_max, + alg_kind::pooling_avg_include_padding, + alg_kind::pooling_avg_exclude_padding) + && utils::one_of(src_md()->data_type, data_type::s32, + data_type::s8, data_type::u8) + && src_md()->data_type == dst_md()->data_type + && attr()->has_default_values( + primitive_attr_t::skip_mask_t::post_ops) + && memory_desc_matches_one_of_tag(*src_md(), + format_tag::nwc, format_tag::nhwc, + format_tag::ndhwc) + != format_tag::undef + && memory_desc_matches_one_of_tag(*dst_md(), + format_tag::nwc, format_tag::nhwc, + format_tag::ndhwc) + != format_tag::undef + && !is_dilated(); + if (!ok) return status::unimplemented; + + return jit_conf(); + } + + jit_pool_conf_t jpp_; + + protected: + status_t jit_conf(); + }; + + jit_uni_i8i8_pooling_fwd_t(const pd_t *apd); + ~jit_uni_i8i8_pooling_fwd_t(); + + status_t init(engine_t *engine) override; + + status_t execute(const exec_ctx_t &ctx) const override { + return execute_forward(ctx); + } + +private: + status_t execute_forward(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr> ker_; +}; + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_pool_kernel.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_pool_kernel.hpp new file mode 100644 index 0000000000000000000000000000000000000000..8eb9264b35a4ab023509aaaa71847322248cd6d5 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_pool_kernel.hpp @@ -0,0 +1,178 @@ +/******************************************************************************* +* Copyright 2017-2022 Intel Corporation +* Copyright 2018 YANDEX LLC +* Copyright 2020-2022 FUJITSU LIMITED +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_JIT_UNI_POOL_KERNEL_HPP +#define CPU_AARCH64_JIT_UNI_POOL_KERNEL_HPP + +#include +#include +#include + +#include "common/memory_tracking.hpp" + +#include "cpu/aarch64/injectors/jit_uni_postops_injector.hpp" +#include "cpu/aarch64/jit_generator.hpp" +#include "cpu/aarch64/jit_primitive_conf.hpp" + +using namespace Xbyak_aarch64; + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +template +struct jit_uni_pool_kernel : public jit_generator { + + jit_uni_pool_kernel( + const jit_pool_conf_t &ajpp, const memory_desc_t *dst_md); + jit_pool_conf_t jpp; + ~jit_uni_pool_kernel(); + + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_uni_pool_kernel) + + static status_t init_conf(jit_pool_conf_t &jbp, + memory_tracking::registrar_t &scratchpad, primitive_attr_t &attr, + const pooling_pd_t *ppd); + +private: + using TReg = typename cpu_isa_traits::TReg; + using TRegS = typename cpu_isa_traits::TRegS; + + int vmm_idx_upper_bound() const noexcept { return 31; } + + int reg_idx(int idx) const noexcept { return vmm_idx_upper_bound() - idx; } + + VReg xreg(int idx) const noexcept { return VReg(reg_idx(idx)); } + ZReg yreg(int idx) const noexcept { return ZReg(reg_idx(idx)); } + ZReg zreg(int idx) const noexcept { return ZReg(reg_idx(idx)); } + TReg vreg(int idx) const noexcept { return TReg(reg_idx(idx)); } + + VReg vmm_mask = VReg(0); + ZReg ymm_tmp_1 = ZReg(0); + TRegS vmm_tmp_1 = TRegS(0); + + TReg vmm_c_tail_mask = TReg(2); + + VReg xmm_ker_area_h = VReg(2); + VReg xmm_one = VReg(2); + VReg xmm_tmp = VReg(3); + + TRegS vmm_ker_area_h = TRegS(2); + TRegS vmm_one = TRegS(2); + TReg vmm_tmp = TReg(3); + ZReg ymm_tmp = ZReg(3); + + TRegS vmm_k_offset = TRegS(1); + + inline uint32_t reg_idx() { + if (!jpp.is_backward) { + return (jpp.is_training) ? 4 : 1; + } else + return 4; + } + + ZReg z_tmp0 = z4; + + PReg k_c_tail_mask_s = p4; + PReg k_c_tail_mask_s_not = p2; + PReg k_c_tail_mask_b = p7; + PReg k_mask_cvt = p5; + PReg k_store_mask = p6; + + /* Caution: Chose predicate registers not used by x64's implementation. */ + PReg p_all_zero = p1; + PReg p_tmp0 = p3; + + using xreg_t = const XReg; + xreg_t reg_param = x0; + xreg_t reg_input = x4; + xreg_t aux_reg_input = x5; + xreg_t reg_index = x10; + xreg_t reg_output = x12; + xreg_t reg_kd_pad_shift = x13; + + xreg_t kj = x14; + xreg_t oi_iter = x15; + xreg_t reg_kh = x7; + const WReg reg_k_shift = w3; + xreg_t tmp_gpr = x6; + xreg_t reg_ker_area_h = x2; + xreg_t reg_nbc = x1; + + xreg_t reg_zero_ptr = x5; + xreg_t reg_zero_id = x13; + xreg_t reg_zero_ih = x14; + xreg_t aux_reg_zero_ih = x15; + xreg_t ki = x12; + xreg_t aux_reg_input_d = x4; + + int prev_kw; + + void prepare_tail_mask(); + void push_vmm_val(const int idx); + void pop_vmm_val(const int idx); + void load(const int idx, const xreg_t ®_ptr, const int offset, + const bool is_c_tail_proccessing); + void store(const int idx, const xreg_t ®_ptr, const int offset, + const bool is_c_tail_proccessing); + + void maybe_recalculate_divisor(int jj, int ur_w, int pad_l, int pad_r, + bool with_c_tail_proccessing); + void avg_step(int ur_w, int ur_bc, int pad_l, int pad_r, + bool with_c_tail_proccessing); + void max_step_fwd(int ur_w, int ur_bc, int pad_l, int pad_r, + bool with_c_tail_proccessing); + void max_step_bwd(int ur_w, int ur_bc, int pad_l, int pad_r, + bool with_c_tail_proccessing); + + void zero_diff_src(int ur_bc, bool with_c_tail_proccessing); + + void step(int ur_w, int ur_bc, int pad_l, int pad_r, + bool with_c_tail_proccessing) { + if (jpp.alg == alg_kind::pooling_max) { + if (jpp.is_backward) + max_step_bwd( + ur_w, ur_bc, pad_l, pad_r, with_c_tail_proccessing); + else + max_step_fwd( + ur_w, ur_bc, pad_l, pad_r, with_c_tail_proccessing); + } else + avg_step(ur_w, ur_bc, pad_l, pad_r, with_c_tail_proccessing); + } + + void generate() override; + + void apply_postops(int ur_bc, int ur_w, int c_block, + const std::function &is_tail_predicate); + + static bool post_ops_ok(jit_pool_conf_t &jpp, const primitive_attr_t &attr, + const memory_desc_wrapper &dst_d); + + std::unique_ptr> + postops_injector_; +}; + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_pooling.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_pooling.hpp new file mode 100644 index 0000000000000000000000000000000000000000..b555cc9a66f1f2e51d6a847049d94180c3d88989 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_pooling.hpp @@ -0,0 +1,191 @@ +/******************************************************************************* +* Copyright 2017-2022 Intel Corporation +* Copyright 2020-2022 FUJITSU LIMITED +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_JIT_UNI_POOLING_HPP +#define CPU_AARCH64_JIT_UNI_POOLING_HPP + +#include +#include + +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/primitive.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_pooling_pd.hpp" + +#include "cpu/aarch64/jit_uni_pool_kernel.hpp" +#include "cpu/aarch64/jit_uni_reorder.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +namespace jit_uni_pooling_utils { +struct trans_wrapper_t; +struct trans_context_t; +} // namespace jit_uni_pooling_utils + +template +struct jit_uni_pooling_fwd_t : public primitive_t { + struct pd_t : public cpu_pooling_fwd_pd_t { + using cpu_pooling_fwd_pd_t::cpu_pooling_fwd_pd_t; + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit:", jpp_.isa, ""), + jit_uni_pooling_fwd_t); + + status_t init(engine_t *engine) { + using namespace utils; + + const bool ok = is_fwd() && !has_zero_dim_memory() + && everyone_is( + d_type, src_md()->data_type, dst_md()->data_type) + && attr()->has_default_values( + primitive_attr_t::skip_mask_t::post_ops, d_type) + && !is_dilated() && set_default_params() == status::success; + if (!ok) return status::unimplemented; + + const bool is_training + = desc_.prop_kind == prop_kind::forward_training; + if (desc()->alg_kind == alg_kind::pooling_max && is_training) + init_default_ws(); + + auto scratchpad = scratchpad_registry().registrar(); + + CHECK(jit_uni_pool_kernel::init_conf( + jpp_, scratchpad, attr_, this)); + + return status::success; + } + + jit_pool_conf_t jpp_; + }; + + explicit jit_uni_pooling_fwd_t(const pd_t *apd); + jit_uni_pooling_fwd_t(jit_uni_pooling_fwd_t &&) = default; + jit_uni_pooling_fwd_t &operator=(jit_uni_pooling_fwd_t &&) = default; + ~jit_uni_pooling_fwd_t(); + + using data_t = typename prec_traits::type; + + status_t init(engine_t *engine) override; + + status_t execute(const exec_ctx_t &ctx) const override { + auto src = CTX_IN_MEM(const data_t *, DNNL_ARG_SRC); + auto dst = CTX_OUT_MEM(data_t *, DNNL_ARG_DST); + auto ws = CTX_OUT_MEM(char *, DNNL_ARG_WORKSPACE); + + if (pd()->ndims() == 5) + execute_forward_3d(src, dst, ws, ctx); + else + execute_forward(src, dst, ws, ctx); + + return status::success; + } + +private: + void execute_forward(const data_t *src, data_t *dst, char *indices, + const exec_ctx_t &ctx) const; + void execute_forward_3d(const data_t *src, data_t *dst, char *indices, + const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + status_t init_ncsp_trans_ctx(); + + std::unique_ptr> kernel_; + std::unique_ptr trans_ctx_; + static constexpr data_type_t wsp_dt_ = data_type::f32; +}; + +template +struct jit_uni_pooling_bwd_t : public primitive_t { + struct pd_t : public cpu_pooling_bwd_pd_t { + using cpu_pooling_bwd_pd_t::cpu_pooling_bwd_pd_t; + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit:", jpp_.isa, ""), + jit_uni_pooling_bwd_t); + + status_t init(engine_t *engine) { + using namespace utils; + + const bool ok = true && set_default_params() == status::success + && !is_fwd() && !has_zero_dim_memory() + && everyone_is(d_type, diff_src_md()->data_type, + diff_dst_md()->data_type) + && attr()->has_default_values() && !is_dilated(); + if (!ok) return status::unimplemented; + + if (desc()->alg_kind == alg_kind::pooling_max) { + init_default_ws(); + if (!compare_ws(hint_fwd_pd_)) return status::unimplemented; + } + + auto scratchpad = scratchpad_registry().registrar(); + + CHECK(jit_uni_pool_kernel::init_conf( + jpp_, scratchpad, attr_, this)); + + return status::success; + } + + jit_pool_conf_t jpp_; + }; + + explicit jit_uni_pooling_bwd_t(const pd_t *apd); + jit_uni_pooling_bwd_t(jit_uni_pooling_bwd_t &&) = default; + jit_uni_pooling_bwd_t &operator=(jit_uni_pooling_bwd_t &&) = default; + ~jit_uni_pooling_bwd_t(); + + using data_t = typename prec_traits::type; + + status_t init(engine_t *engine) override; + + status_t execute(const exec_ctx_t &ctx) const override { + auto diff_dst = CTX_IN_MEM(const data_t *, DNNL_ARG_DIFF_DST); + auto ws = CTX_IN_MEM(const char *, DNNL_ARG_WORKSPACE); + auto diff_src = CTX_OUT_MEM(data_t *, DNNL_ARG_DIFF_SRC); + + if (pd()->ndims() == 5) + execute_backward_3d(diff_dst, ws, diff_src, ctx); + else + execute_backward(diff_dst, ws, diff_src, ctx); + + return status::success; + } + +private: + void execute_backward(const data_t *diff_dst, const char *indices, + data_t *diff_src, const exec_ctx_t &ctx) const; + void execute_backward_3d(const data_t *diff_dst, const char *indices, + data_t *diff_src, const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + status_t init_ncsp_trans_ctx(); + + std::unique_ptr> kernel_; + std::unique_ptr trans_ctx_; + static constexpr data_type_t wsp_dt_ = data_type::f32; +}; + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_reorder.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_reorder.hpp new file mode 100644 index 0000000000000000000000000000000000000000..4587fd82e21dd78bd06c0ae5f592bf1b04b6bf76 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_reorder.hpp @@ -0,0 +1,314 @@ +/******************************************************************************* +* Copyright 2018-2023 Intel Corporation +* Copyright 2020-2023 FUJITSU LIMITED +* Copyright 2022 Arm Ltd. and affiliates +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_JIT_UNI_REORDER_HPP +#define CPU_AARCH64_JIT_UNI_REORDER_HPP + +#include + +#include "common/c_types_map.hpp" +#include "common/type_helpers.hpp" + +#include "cpu/reorder/cpu_reorder_pd.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +namespace tr { + +constexpr int max_ndims = DNNL_MAX_NDIMS; + +struct node_t { + static constexpr int64_t empty_field = -1; + + size_t n = 0; + size_t tail_size = 0; + int dim_id = empty_field; + int parent_node_id = empty_field; + bool is_zero_pad_needed = false; + ptrdiff_t is = 0; // input stride + ptrdiff_t os = 0; // output stride + ptrdiff_t ss = 0; // scale stride + ptrdiff_t cs = 0; // compensation stride + + bool is_dim_id_empty() const { return dim_id == empty_field; } + bool is_parent_empty() const { return parent_node_id == empty_field; } +}; + +enum class scale_type_t { NONE, COMMON, MANY }; + +struct prb_t { + /* The compensation mask value indicates how big an additional buffer should be. + * Possible values for reorder: + * 1) standard compensation = 1 = 0b01 + * 2) asymmetric compensation = 2 = 0b10 + * 3) compensation if tensor contains group = 3 = 0b11 */ + static constexpr int invalid_comp_mask = 0; + static constexpr int standard_comp_mask = 0b1; + static constexpr int asymmetric_comp_mask = 0b10; + static constexpr int comp_mask_with_groups + = standard_comp_mask + asymmetric_comp_mask; + + bool is_tail_in_one_of_child_nodes(int parent_node_id) const { + for (int i = parent_node_id; i >= 0; i--) { + if (nodes[i].parent_node_id == parent_node_id) { + if (nodes[i].tail_size != 0) + return true; + else + parent_node_id = i; + } + } + + return false; + } + + int tail(int d) const { + assert(d < ndims); + return static_cast(nodes[d].tail_size); + } + + int n(int d) const { + assert(d < ndims); + return static_cast(nodes[d].n); + } + int is(int d) const { + assert(d < ndims); + return static_cast(nodes[d].is); + } + int os(int d) const { + assert(d < ndims); + return static_cast(nodes[d].os); + } + int ss(int d) const { + assert(d < ndims); + return static_cast(nodes[d].ss); + } + + int cs(int d) const { + assert(d < ndims); + return static_cast(nodes[d].cs); + } + + data_type_t itype; + data_type_t otype; + int ndims; + node_t nodes[max_ndims]; + ptrdiff_t ioff; + ptrdiff_t ooff; + scale_type_t src_scale_type; + scale_type_t dst_scale_type; + float beta; + int full_ndims; + bool is_tail_present = false; + float scale_adjust = 1.f; + int compensation_mask = invalid_comp_mask; + bool req_s8s8_comp = false; + bool req_asymmetric_comp = false; + bool req_src_zp = false; + bool req_dst_zp = false; +}; + +status_t prb_init(prb_t &prb, const memory_desc_t &imd, + const memory_desc_t &omd, const primitive_attr_t *attr); + +/** sorts the problem nodes so that output strides come in ascending order */ +void prb_normalize(prb_t &p); + +/** fill parent node info for blocked nodes */ +void prb_node_dependency(prb_t &p); + +/** folds nodes together if possible */ +void prb_simplify(prb_t &p); + +/** splits the node dim into two of sizes n1 and n / n1 + * @warning n must be multiple of n1 */ +void prb_node_split(prb_t &p, int dim, size_t n1); + +/** swaps d0 and d1 nodes */ +void prb_node_swap(prb_t &p, int d0, int d1); + +/** moves node d0 to the d1 position. + * nodes (d0, d1] are shifted to the left if d0 < d1 or + * to the right if d0 > d1 */ +void prb_node_move(prb_t &p, int d0, int d1); + +/** dumps the problem to stdout */ +void prb_dump(const prb_t &p); + +struct call_param_t { + const void *in = nullptr; + void *out = nullptr; + const float *src_scales = nullptr; + const float *dst_scales = nullptr; + int32_t src_zp = 0; + int32_t dst_zp = 0; + int32_t *compensation_scratch = nullptr; +}; + +// The additional structure is needed because +// using a data structure with tail processing +// data for non-tail cases reduces kernel +// performance. This is because there is too +// much data that has to be transferred to the kernel. +struct tail_call_param_t { + call_param_t base_params; + int64_t curr_data_chunks[DNNL_MAX_NDIMS] = {-1}; + int64_t zeroing_data = static_cast(false); + int64_t skip_kernel_execution = static_cast(false); +}; + +struct kernel_t { + struct desc_t { + int id; + prb_t prb; + }; + + kernel_t(const desc_t &desc) + : desc_(desc) + , compensation_needed_( + desc.prb.req_s8s8_comp || desc.prb.req_asymmetric_comp) {} + virtual void operator()(const call_param_t *c) const = 0; + virtual void operator()(const tail_call_param_t *c) const = 0; + virtual status_t create_kernel() = 0; + virtual ~kernel_t() {} + + /** inits kernel descriptor: + * desc -- kernel descriptor (output) + * prb -- transposition problem (input) + * ndims_ker_max -- limit the maximum number of dimensions kernel + * will process (optional, 0 -- no limitation) */ + static status_t desc_init( + desc_t &desc, const prb_t &prb, int ndims_ker_max = 0); + + /** creates kernel for the problem described in desc */ + static kernel_t *create(const desc_t &desc); + +protected: + const desc_t desc_; + const prb_t &prb_ = desc_.prb; + bool compensation_needed_ = false; +}; + +/* TODO: add trans_t class */ + +struct jit_single_blk_kernel_t; + +} // namespace tr + +struct jit_uni_reorder_t : public primitive_t { + using primitive_t::primitive_t; + struct pd_t : public cpu_reorder_pd_t { + using cpu_reorder_pd_t::cpu_reorder_pd_t; + + DECLARE_COMMON_PD_T("jit:uni", jit_uni_reorder_t); + + tr::prb_t prb_; + tr::kernel_t::desc_t ker_desc_; + int nthr_; + bool with_groups_ = false; + dim_t D_mask_ = 0; + + status_t init( + engine_t *engine, engine_t *src_engine, engine_t *dst_engine); + + private: + status_t init_scratchpad(); + static status_t create(reorder_pd_t **reorder_pd, engine_t *engine, + const primitive_attr_t *attr, engine_t *src_engine, + const memory_desc_t *src_md, engine_t *dst_engine, + const memory_desc_t *dst_md); + + friend dnnl::impl::impl_list_item_t; + }; + + status_t init(engine_t *engine) override; + status_t execute(const exec_ctx_t &ctx) const override; + + enum { ndims_driver_max = 4 }; + +private: + void omp_driver_0d(int off, const char *in, char *out, + const float *src_scales, const float *dst_scales, int src_zp, + int dst_zp, int32_t *compensation_scratch) const; + void omp_driver_1d(int ithr, int nthr, int off, const char *in, char *out, + const float *src_scales, const float *dst_scales, int src_zp, + int dst_zp, int32_t *compensation_scratch) const; + void omp_driver_2d(int ithr, int nthr, int off, const char *in, char *out, + const float *src_scales, const float *dst_scales, int src_zp, + int dst_zp, int32_t *compensation_scratch) const; + void omp_driver_3d(int ithr, int nthr, int off, const char *in, char *out, + const float *src_scales, const float *dst_scales, int src_zp, + int dst_zp, int32_t *compensation_scratch) const; + void omp_driver_4d(int ithr, int nthr, int off, const char *in, char *out, + const float *src_scales, const float *dst_scales, int src_zp, + int dst_zp, int32_t *compensation_scratch) const; + + void omp_driver(const char *in, char *out, const float *src_scales, + const float *dst_scales, int src_zp, int dst_zp, + const memory_tracking::grantor_t &scratchpad) const; + + void fill_curr_data_chunks(const tr::prb_t &prb, const int off, + const ptrdiff_t *omp_data_chunks, const int omp_ndims, + tr::tail_call_param_t &c) const; + + void reduce_compensation(char *out, + const int32_t *compensation_reduce_scratch, const int nthr, + const dim_t wspace_per_thr_size) const; + + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + std::unique_ptr kernel_; +}; + +struct jit_blk_reorder_t : public primitive_t { + using primitive_t::primitive_t; + struct pd_t : public cpu_reorder_pd_t { + using cpu_reorder_pd_t::cpu_reorder_pd_t; + DECLARE_COMMON_PD_T("jit:blk", jit_blk_reorder_t); + + tr::prb_t prb_; + + private: + static status_t create(reorder_pd_t **reorder_pd, engine_t *engine, + const primitive_attr_t *attr, engine_t *src_engine, + const memory_desc_t *src_md, engine_t *dst_engine, + const memory_desc_t *dst_md); + + // Swap last two nodes, put block 4, 8, 16 nodes to first + static void prb_tile_normalize(tr::prb_t &p); + friend dnnl::impl::impl_list_item_t; + }; + + status_t init(engine_t *engine) override; + status_t execute(const exec_ctx_t &ctx) const override; + + jit_blk_reorder_t(const pd_t *apd); + ~jit_blk_reorder_t(); + +private: + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + std::unique_ptr kernel_; +}; + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_softmax.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_softmax.hpp new file mode 100644 index 0000000000000000000000000000000000000000..67f6a1ec6a95c91921ab14461189acfa77097cd5 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_softmax.hpp @@ -0,0 +1,193 @@ +/******************************************************************************* +* Copyright 2019-2022 Intel Corporation +* Copyright 2020-2022 FUJITSU LIMITED +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_JIT_UNI_SOFTMAX_HPP +#define CPU_AARCH64_JIT_UNI_SOFTMAX_HPP + +#include + +#include "common/c_types_map.hpp" +#include "common/memory_tracking.hpp" +#include "common/primitive.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/aarch64/cpu_isa_traits.hpp" +#include "cpu/cpu_softmax_pd.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +namespace softmax_impl { +template +struct driver_t; +} + +template +struct jit_uni_softmax_fwd_t : public primitive_t { + struct pd_t : public cpu_softmax_fwd_pd_t { + using cpu_softmax_fwd_pd_t::cpu_softmax_fwd_pd_t; + + DECLARE_COMMON_PD_T( + JIT_IMPL_NAME_HELPER("jit:", isa, ""), jit_uni_softmax_fwd_t); + + status_t init(engine_t *engine) { + auto is_dense = [&]() { + const memory_desc_wrapper src_d(src_md()); + const auto &bd = src_d.blocking_desc(); + + if (!src_d.is_dense(true) || !src_d.only_padded_dim(axis())) + return false; + + if (src_d.is_plain()) return bd.strides[axis()] == 1; + + // It is fine to use float here as the kernel uses halfs of + // vector registers. + const auto blk_size = cpu_isa_traits::vlen / sizeof(float); + // 31 is a general limit, 2 is for unroll_regs_ = 4; + const size_t max_stride = (1LL << (31 - 2)) - 1; + const int last_blk = bd.inner_nblks - 1; + return bd.inner_blks[last_blk] == blk_size + && bd.inner_idxs[last_blk] == axis() + && sizeof(float) * bd.strides[axis()] < max_stride; + }; + + using namespace data_type; + using skip_mask_t = primitive_attr_t::skip_mask_t; + + const auto src_dt = src_md()->data_type; + const auto dst_dt = dst_md()->data_type; + bool ok = mayiuse(isa) && is_fwd() && !has_zero_dim_memory() + && utils::one_of(src_dt, f32, s8, u8) + && utils::one_of(dst_dt, f32, s8, u8) && mayiuse(sve_512) + && attr()->has_default_values(skip_mask_t::scales_runtime) + && attr_scales_ok() + && set_default_formats() == status::success; + if (!ok) return status::unimplemented; + + ok = memory_desc_wrapper(src_md()).similar_to( + memory_desc_wrapper(dst_md()), true, false, 0) + && is_dense(); // not dense impl can be easily done + if (!ok) return status::unimplemented; + + nthr_ = dnnl_get_max_threads(); + init_scratchpad(); + + return status::success; + }; + + int nthr_; // To not exceed the limit in execute used for set up. + + private: + void init_scratchpad() { + if (utils::one_of( + dst_md()->data_type, data_type::u8, data_type::s8)) { + auto scratchpad = scratchpad_registry().registrar(); + scratchpad.template book( + memory_tracking::names::key_softmax_interim_store, + axis_size(true) * sizeof(float) * nthr_); + } + } + }; + + jit_uni_softmax_fwd_t(const pd_t *apd); + ~jit_uni_softmax_fwd_t(); + + status_t init(engine_t *engine) override; + + status_t execute(const exec_ctx_t &ctx) const override; + +private: + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + softmax_impl::driver_t *softmax_driver_; +}; + +template +struct jit_uni_softmax_bwd_t : public primitive_t { + struct pd_t : public cpu_softmax_bwd_pd_t { + using cpu_softmax_bwd_pd_t::cpu_softmax_bwd_pd_t; + + DECLARE_COMMON_PD_T( + JIT_IMPL_NAME_HELPER("jit:", isa, ""), jit_uni_softmax_bwd_t); + + status_t init(engine_t *engine) { + auto is_dense = [&]() { + const memory_desc_wrapper dst_d(dst_md()); + const auto &bd = dst_d.blocking_desc(); + + if (!dst_d.is_dense(true) || !dst_d.only_padded_dim(axis())) + return false; + + // It is fine to use float here as the kernel uses halfs of + // vector registers. + const auto blk_size = cpu_isa_traits::vlen / sizeof(float); + if (dst_d.is_plain()) + return bd.strides[axis()] == 1; + else { + // 31 is a general limit, 2 is for unroll_regs_ = 4; + const size_t max_stride = (1LL << (31 - 2)) - 1; + const int last_blk = bd.inner_nblks - 1; + return bd.inner_blks[last_blk] == blk_size + && bd.inner_idxs[last_blk] == axis() + && sizeof(float) * bd.strides[axis()] < max_stride; + } + }; + + using namespace data_type; + bool ok = mayiuse(isa) && !is_fwd() && !has_zero_dim_memory() + && utils::one_of(dst_md()->data_type, f32) + && utils::one_of(diff_dst_md()->data_type, f32) + && utils::one_of(diff_src_md()->data_type, f32) + && mayiuse(sve_512) && attr()->has_default_values() + && set_default_formats() == status::success; + if (!ok) return status::unimplemented; + + ok = memory_desc_wrapper(diff_src_md()) + .similar_to(memory_desc_wrapper(diff_dst_md()), + true, false, 0) + && memory_desc_wrapper(diff_dst_md()) + == memory_desc_wrapper(dst_md()) + && is_dense(); // not dense impl can be easily done + if (!ok) return status::unimplemented; + + return status::success; + }; + }; + + jit_uni_softmax_bwd_t(const pd_t *apd); + ~jit_uni_softmax_bwd_t(); + + status_t init(engine_t *engine) override; + + status_t execute(const exec_ctx_t &ctx) const override; + +private: + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + softmax_impl::driver_t *softmax_driver_; +}; + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/matmul/acl_matmul.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/matmul/acl_matmul.hpp new file mode 100644 index 0000000000000000000000000000000000000000..451cc78d52df4a33d5e2677fe1d6ab1f1ff8536f --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/matmul/acl_matmul.hpp @@ -0,0 +1,153 @@ +/******************************************************************************* +* Copyright 2021-2023 Arm Ltd. and affiliates +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef ACL_MATMUL_HPP +#define ACL_MATMUL_HPP + +#include "cpu/aarch64/matmul/acl_matmul_utils.hpp" + +#include "cpu/aarch64/acl_post_ops.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { +namespace matmul { + +struct acl_resource_t : public resource_t { + acl_resource_t() : acl_obj_(utils::make_unique()) {} + + status_t configure(const acl_matmul_conf_t &) { + if (!acl_obj_) return status::out_of_memory; + acl_obj_->src_tensor.allocator()->init(amp.src_tensor_info); + acl_obj_->wei_tensor.allocator()->init(amp.wei_tensor_info); + acl_obj_->dst_tensor.allocator()->init(amp.dst_tensor_info); + // Configure transpose kernel for src, wei or both + if (amp.is_transA) { + acl_obj_->src_acc_tensor.allocator()->init(amp.src_acc_info); + acl_obj_->transA.configure( + &acl_obj_->src_acc_tensor, &acl_obj_->src_tensor); + } + // Configure GEMM + acl_obj_->gemm.configure(&acl_obj_->src_tensor, &acl_obj_->wei_tensor, + nullptr, &acl_obj_->dst_tensor, amp.alpha, 0.0f, amp.gemm_info); + return status::success; + } + acl_matmul_obj_t &get_acl_obj() const { return *acl_obj_; } + + DNNL_DISALLOW_COPY_AND_ASSIGN(acl_resource_t); + +private: + std::unique_ptr acl_obj_; +}; + +struct acl_matmul_t : public primitive_t { + struct pd_t : public dnnl::impl::cpu::matmul::cpu_matmul_pd_t { + + pd_t(const matmul_desc_t *adesc, const primitive_attr_t *attr, + const cpu_matmul_pd_t *hint_fwd_pd) + : cpu_matmul_pd_t(adesc, attr, hint_fwd_pd), amp_(), post_ops() {} + + using cpu_matmul_pd_t::cpu_matmul_pd_t; + + DECLARE_COMMON_PD_T("gemm:acl", acl_matmul_t, USE_GLOBAL_SCRATCHPAD); + + status_t init(engine_t *engine) { + using smask_t = primitive_attr_t::skip_mask_t; + const bool is_fp32_ok + = utils::everyone_is(data_type::f32, src_md()->data_type, + weights_md()->data_type, dst_md()->data_type, + desc()->accum_data_type) + && platform::has_data_type_support(data_type::f32); + const bool is_fp16_ok + = utils::everyone_is(data_type::f16, src_md()->data_type, + weights_md()->data_type, dst_md()->data_type) + && platform::has_data_type_support(data_type::f16); + bool ok = is_dense_data() + && utils::one_of(true, is_fp32_ok, is_fp16_ok) + && !has_zero_dim_memory() + && weights_md_.format_kind == format_kind::any + && set_default_formats() + && attr()->has_default_values( + smask_t::oscale | smask_t::post_ops) + && attr_oscale_ok() && !has_runtime_dims_or_strides(); + if (!ok) return status::unimplemented; + + CHECK(acl_matmul_utils::init_conf_matmul( + amp_, src_md_, weights_md_, dst_md_, *desc(), *attr())); + + arm_compute::ActivationLayerInfo act_info; + CHECK(post_ops.init(engine, attr_.post_ops_, dst_md_, act_info)); + amp_.gemm_info.set_activation_info(act_info); + amp_.use_dst_acc = post_ops.has_sum(); + + // Validate ACL GEMM + ACL_CHECK_VALID(arm_compute::NEGEMM::validate(&_.src_tensor_info, + &_.wei_tensor_info, nullptr, &_.dst_tensor_info, + amp_.alpha, 0.0f, amp_.gemm_info)); + + return status::success; + } + + acl_matmul_conf_t amp_; + + acl_post_ops_t post_ops; + + protected: + bool attr_oscale_ok() const { + const auto &oscale = attr()->output_scales_; + return oscale.mask_ == 0; + } + }; + + acl_matmul_t(const pd_t *apd) : primitive_t(apd) {} + + status_t create_resource( + engine_t *engine, resource_mapper_t &mapper) const override { + if (mapper.has_resource(this)) return status::success; + auto r = utils::make_unique(); + if (!r) return status::out_of_memory; + + // Configure the resource based on information from primitive descriptor + CHECK(r->configure(pd()->amp_)); + mapper.add(this, std::move(r)); + + CHECK(pd()->post_ops.create_resource(engine, mapper)); + + return status::success; + } + + typedef typename prec_traits::type data_t; + + status_t execute(const exec_ctx_t &ctx) const override { + return execute_forward(ctx); + } + +private: + // To guard the const execute_forward(), the mutex must be 'mutable' + mutable std::mutex mtx; + status_t execute_forward(const exec_ctx_t &ctx) const; + + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } +}; // acl_matmul_t + +} // namespace matmul +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/matmul/acl_matmul_utils.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/matmul/acl_matmul_utils.hpp new file mode 100644 index 0000000000000000000000000000000000000000..67bb2e78ebfe2025b41f93e92a69dab401c35086 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/matmul/acl_matmul_utils.hpp @@ -0,0 +1,64 @@ +/******************************************************************************* +* Copyright 2021-2023 Arm Ltd. and affiliates +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_ACL_MATMUL_UTILS_HPP +#define CPU_AARCH64_ACL_MATMUL_UTILS_HPP + +#include "cpu/matmul/cpu_matmul_pd.hpp" + +#include "cpu/aarch64/acl_utils.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +struct acl_matmul_obj_t { + arm_compute::NEGEMM gemm; + arm_compute::NETranspose transA; + arm_compute::Tensor src_tensor; + arm_compute::Tensor src_acc_tensor; + arm_compute::Tensor wei_tensor; + arm_compute::Tensor dst_tensor; +}; + +struct acl_matmul_conf_t { + bool is_transA; + // If this is true, the result of the matmul goes into a temporarily + // allocated ACL tensor to be accumulated into the oneDNN dst during postops + bool use_dst_acc; + arm_compute::TensorInfo src_tensor_info; + arm_compute::TensorInfo src_acc_info; + arm_compute::TensorInfo wei_tensor_info; + arm_compute::TensorInfo dst_tensor_info; + arm_compute::GEMMInfo gemm_info; + float alpha; +}; + +namespace acl_matmul_utils { + +status_t init_conf_matmul(acl_matmul_conf_t &, memory_desc_t &src_md, + memory_desc_t &wei_md, memory_desc_t &dst_md, const matmul_desc_t &md, + const primitive_attr_t &attr); + +} // namespace acl_matmul_utils + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif // CPU_AARCH64_ACL_MATMUL_UTILS_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/shuffle/jit_uni_shuffle.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/shuffle/jit_uni_shuffle.hpp new file mode 100644 index 0000000000000000000000000000000000000000..24b809c563f34d0a434c47792c78435353059d81 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/shuffle/jit_uni_shuffle.hpp @@ -0,0 +1,75 @@ +/******************************************************************************* +* Copyright 2020-2022 Intel Corporation +* Copyright 2022 FUJITSU LIMITED +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_JIT_UNI_SHUFFLE_HPP +#define CPU_AARCH64_JIT_UNI_SHUFFLE_HPP + +#include "common/c_types_map.hpp" +#include "common/primitive.hpp" + +#include "cpu/cpu_shuffle_pd.hpp" + +#include "cpu/aarch64/cpu_isa_traits.hpp" +#include "cpu/aarch64/shuffle/jit_uni_shuffle_kernel.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +template +struct jit_uni_shuffle_kernel_t; + +template +struct jit_uni_shuffle_t : public primitive_t { + struct pd_t : public cpu_shuffle_pd_t { + using cpu_shuffle_pd_t::cpu_shuffle_pd_t; + + DECLARE_COMMON_PD_T( + JIT_IMPL_NAME_HELPER("jit:", conf_.isa, ""), jit_uni_shuffle_t); + + status_t init(engine_t *engine); + + jit_shuffle_conf_t get_conf() const { return conf_; }; + + private: + jit_shuffle_conf_t conf_; + }; + + jit_uni_shuffle_t(const pd_t *apd); + + ~jit_uni_shuffle_t(); + + status_t init(engine_t *engine) override; + + status_t execute(const exec_ctx_t &ctx) const override; + +private: + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + status_t precompute_offsets(); + std::unique_ptr> kernel_; + unsigned *input_off_; +}; + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/shuffle/jit_uni_shuffle_kernel.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/shuffle/jit_uni_shuffle_kernel.hpp new file mode 100644 index 0000000000000000000000000000000000000000..20c2c00157ae3454b0c8135dc9ebc30db26942c1 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/shuffle/jit_uni_shuffle_kernel.hpp @@ -0,0 +1,115 @@ +/******************************************************************************* +* Copyright 2021-2022 Intel Corporation +* Copyright 2022 FUJITSU LIMITED +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_JIT_UNI_SHUFFLE_KERNEL_HPP +#define CPU_AARCH64_JIT_UNI_SHUFFLE_KERNEL_HPP + +#include "common/c_types_map.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_shuffle_pd.hpp" + +#include "cpu/aarch64/cpu_isa_traits.hpp" +#include "cpu/aarch64/jit_generator.hpp" +#include "cpu/aarch64/jit_primitive_conf.hpp" +#include "cpu/aarch64/shuffle/jit_uni_shuffle.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +using namespace Xbyak_aarch64; + +template +struct jit_uni_shuffle_kernel_t : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_uni_shuffle_kernel_t) + + jit_uni_shuffle_kernel_t(const jit_shuffle_conf_t conf); + + using TReg = typename utils::conditional::type; + using TRegS = typename cpu_isa_traits::TRegS; + + constexpr int vmm_idx(int idx) const { + return (cpu_isa_traits::n_vregs - 1) - idx; + } + + /* + * Prepare the mask to be used during tail processing. + * if it is sve_512 at least then k_tail_mask_ is filled. + */ + void prepare_mask(); + + /* + * Emulates the behavior of vgatherdps for architectures + * that do not support this instruction. + */ + void emu_gather_data(const XReg ®_src_addr, const int indices_idx, + const int data_idx, const bool is_tail = false); + + void gather_data(const XReg ®_src_addr, const int indices_idx, + const int data_idx, const bool is_tail = false); + + void store_data(const int data_idx, const XReg ®_dst_addr, + const int offset = 0, const bool is_tail = false); + + void shuffle_blocked_format(); + + void append_zero_padding( + const XReg ®_dst_addr, const bool zero_extend_write); + + void generate() override; + + const TReg vmm_full_mask_ = TReg(1); + const TReg vmm_src_ = TReg(2); + const TReg vmm_tmp_ = TReg(3); + const TReg vmm_indices_ = TReg(4); + const TReg vmm_zero_ = TReg(11); + + const PReg k_tail_mask_ = p1; + const PReg k_full_mask_ = p2; + + const XReg ®_tmp_ = x7; + const XReg ®_dst_ = x3; + const XReg ®_indices_ = x1; + const XReg ®_work_ = x2; + // Always mimic the Unix ABI + const XReg ®_param = x0; + const XReg ®_src_ = x6; + const XReg ®_tmp1_ = x8; + const XReg ®_tmp2_ = x9; + const XReg ®_tmp3_ = x10; + const XReg ®_tmp4_ = x11; + const XReg ®_tmp5_ = x12; + const XReg ®_tmp6_ = x13; + const XReg ®_padded_block = x14; //WReg(x14.getIdx()); + + const jit_shuffle_conf_t conf_; + const size_t padding_size_; + const uint64_t isa_sveLen + = is_superset(isa, sve_128) ? cpu_isa_traits::vlen : 0; +}; + +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/utils/jit_io_helper.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/utils/jit_io_helper.hpp new file mode 100644 index 0000000000000000000000000000000000000000..e20ca731d5f8fd21114d472145feb49366719e8e --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/utils/jit_io_helper.hpp @@ -0,0 +1,211 @@ +/******************************************************************************* +* Copyright 2021-2022 Intel Corporation +* Copyright 2022 FUJITSU LIMITED +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_AARCH64_UTILS_JIT_IO_HELPER_HPP +#define CPU_AARCH64_UTILS_JIT_IO_HELPER_HPP + +#include +#include +#include + +#include "common/optional.hpp" + +#include "cpu/aarch64/cpu_isa_traits.hpp" +#include "cpu/aarch64/jit_generator.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace aarch64 { + +namespace io { + +class io_conf_t { +public: + io_conf_t() = default; + io_conf_t(const bool nt_stores_enabled); + io_conf_t(const io_conf_t &other) = default; + + io_conf_t &operator=(const io_conf_t &other) = default; + + bool nt_stores_enabled_ = false; +}; + +class io_tail_conf_t { +public: + io_tail_conf_t(const std::size_t simd_w, const std::size_t tail_size, + const Xbyak_aarch64::PReg &tail_opmask, const int tail_vmm_mask_idx, + const Xbyak_aarch64::XReg ®_tmp, + const Xbyak_aarch64::XReg ®_tmp1); + io_tail_conf_t(const io_tail_conf_t &other) = default; + + io_tail_conf_t &operator=(const io_tail_conf_t &other) = default; + + std::size_t simd_w_ = 0; + std::size_t tail_size_ = 0; + Xbyak_aarch64::PReg tail_opmask_ = Xbyak_aarch64::PReg(1); + int tail_vmm_mask_idx_ = 0; + Xbyak_aarch64::XReg reg_tmp_ = Xbyak_aarch64::XReg(26); + Xbyak_aarch64::XReg reg_tmp1_ = Xbyak_aarch64::XReg(25); +}; + +class io_saturation_conf_t { +public: + io_saturation_conf_t(const int vreg_zero_saturation_idx, + const int vreg_saturation_ubound_idx, + const Xbyak_aarch64::XReg ®_tmp); + io_saturation_conf_t(const io_saturation_conf_t &other) = default; + + io_saturation_conf_t &operator=(const io_saturation_conf_t &other) + = default; + + int vreg_zero_saturation_idx_ = 0; + int vreg_saturation_ubound_idx_ = 0; + Xbyak_aarch64::XReg reg_tmp_ = Xbyak_aarch64::XReg(26); +}; + +class io_gather_conf_t { +public: + io_gather_conf_t(const std::size_t simd_w, + const Xbyak_aarch64::PReg &full_opmask, const int full_vmm_mask_idx, + const Xbyak_aarch64::XReg ®_tmp, + const Xbyak_aarch64::XReg ®_tmp1, + const utils::optional_t &vmm_tmp_idx = utils::nullopt); + io_gather_conf_t(const io_gather_conf_t &other) = default; + + io_gather_conf_t &operator=(const io_gather_conf_t &other) = default; + + std::size_t simd_w_ = 0; + Xbyak_aarch64::PReg full_opmask_ = Xbyak_aarch64::PReg(0); + int full_vmm_mask_idx_ = 0; + Xbyak_aarch64::XReg reg_tmp_ = Xbyak_aarch64::XReg(26); + Xbyak_aarch64::XReg reg_tmp1_ = Xbyak_aarch64::XReg(25); + // It is needed, when io_helper use emulation for gather + // and it is not needed for sse. + utils::optional_t vmm_tmp_idx_ = utils::nullopt; +}; + +template +class jit_io_multi_dt_helper_t; + +template +class jit_io_helper_t { +public: + friend class jit_io_multi_dt_helper_t; + + jit_io_helper_t(jit_generator *host, const cpu_isa_t &isa, + const data_type_t &data_type, const io_conf_t &io_conf, + const utils::optional_t &tail_conf = utils::nullopt, + const utils::optional_t &saturation_conf + = utils::nullopt, + const utils::optional_t &gather_conf + = utils::nullopt); + jit_io_helper_t(jit_io_helper_t &&) = default; + jit_io_helper_t &operator=(jit_io_helper_t &&) = default; + + ~jit_io_helper_t(); + void prepare_tail_mask(); + void prepare_full_mask(); + /* + * Sometimes the values in the register can be nan at the + * beginning of the kernel, then using vcmpps(vmm, vmm, vmm) + * will not set all bits to 1, instead of that this instruction will + * return zero. At the beginning, it is worth to zeroing + * full mask vmm to be sure, that vcmpps work properly. + */ + void init_full_mask(); + void init_saturate_f32() const; + void gather(const Xbyak_aarch64::XReg &src_reg, const Vmm &indices_vmm, + const Vmm &dst_vmm, const bool tail); + void broadcast(const Xbyak_aarch64::XReg &src_addr, const int src_offt, + const Vmm &dst_vmm); + void load(const Xbyak_aarch64::XReg &src_addr, const int src_offt, + const Vmm &dst_vmm, const bool tail); + void store(const Vmm &src_vmm, const Xbyak_aarch64::XReg &dst_addr, + const int offt, const bool tail); + +private: + void compute_cmp_mask(const Vmm &cmp_dst, const Vmm &cmp_src, + const Vmm &cmp_src2, const unsigned int uimm); + void prepare_opmask(const std::size_t how_many_bits_to_set, + const Xbyak_aarch64::XReg ®_tmp0, + const Xbyak_aarch64::XReg ®_tmp1, + const Xbyak_aarch64::PReg &mask); + + void load_f32(const Xbyak_aarch64::XReg &src_addr, const int offt, + const Vmm &dst_vmm, const bool tail, + const Xbyak_aarch64::PReg &mask); + void load_s32(const Xbyak_aarch64::XReg &src_addr, const int offt, + const Vmm &dst_vmm, const bool tail, + const Xbyak_aarch64::PReg &mask); + void load_i8(const Xbyak_aarch64::XReg &src_addr, const int offt, + const Vmm &dst_vmm, const Xbyak_aarch64::PReg &mask); + void saturate(const Vmm &vmm); + void store_f32(const Vmm &src_vmm, const Xbyak_aarch64::XReg &dst_addr, + const int offt, const bool tail, const Xbyak_aarch64::PReg &mask); + void store_i8(const Vmm &src_vmm, const Xbyak_aarch64::XReg &dst_addr, + const int offt, const Xbyak_aarch64::PReg &mask); + void convert_to_f32(const Vmm &dst_vmm, const Vmm &src_vmm, + const data_type_t src_data_type); + + void store_i8_sdb(Xbyak_aarch64::XReg addr, const Vmm &src_vmm, + const Xbyak_aarch64::PReg &mask); + void store_i8_udb(Xbyak_aarch64::XReg addr, const Vmm &src_vmm, + const Xbyak_aarch64::PReg &mask); + + jit_generator *host_; + const cpu_isa_t isa_; + const data_type_t data_type_; + const io_conf_t io_conf_; + const utils::optional_t tail_conf_; + const utils::optional_t saturation_conf_; + const utils::optional_t gather_conf_; +}; + +template +class jit_io_multi_dt_helper_t { +public: + using data_types_t = std::unordered_set>; + + jit_io_multi_dt_helper_t(jit_generator *host, const cpu_isa_t &isa, + const data_types_t &data_types, const io_conf_t &io_conf, + const utils::optional_t &tail_conf = utils::nullopt, + const std::map &saturation_confs + = std::map {}, + const utils::optional_t &gather_conf + = utils::nullopt); + ~jit_io_multi_dt_helper_t(); + void prepare_tail_mask(); + void prepare_full_mask(); + void init_saturate_f32(const data_types_t &store_data_types); + void init_full_mask(); + + std::shared_ptr> at(const data_type_t dt) const; + +private: + std::unordered_map>, + std::hash> + storage_; +}; + +} // namespace io +} // namespace aarch64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/gemm/f32/gemm_utils_f32.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/gemm/f32/gemm_utils_f32.hpp new file mode 100644 index 0000000000000000000000000000000000000000..36bad397b32455dc3848d22aca890bfd4405a4da --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/gemm/f32/gemm_utils_f32.hpp @@ -0,0 +1,69 @@ +/******************************************************************************* +* Copyright 2018-2020 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_GEMM_F32_GEMM_UTILS_F32_HPP +#define CPU_GEMM_F32_GEMM_UTILS_F32_HPP + +#include + +namespace dnnl { +namespace impl { +namespace cpu { + +namespace gemm_utils { +template +struct gemm_traits {}; + +template +struct gemm_traits { + static constexpr dim_t m = 8; + static constexpr dim_t n = 6; + static constexpr dim_t BM = 4032; + static constexpr dim_t BN = isTransA ? 96 : 192; + static constexpr dim_t BK = isTransB ? 96 : 512; +}; + +template +struct gemm_traits { + static constexpr dim_t m = 16; + static constexpr dim_t n = 6; + static constexpr dim_t BM = 4032; + static constexpr dim_t BN = isTransA ? 96 : 48; + static constexpr dim_t BK = isTransB ? 96 : 256; +}; + +template +using unroll_factor = gemm_traits; + +template +void sum_two_matrices(dim_t m, dim_t n, data_t *__restrict p_src, dim_t ld_src, + data_t *__restrict p_dst, dim_t ld_dst); + +void calc_nthr_nocopy_avx512_common(dim_t m, dim_t n, dim_t k, int nthrs, + int *nthrs_m, int *nthrs_n, int *nthrs_k, dim_t *BM, dim_t *BN, + dim_t *BK); + +void calc_nthr_nocopy_avx(dim_t m, dim_t n, dim_t k, int nthrs, int *nthrs_m, + int *nthrs_n, int *nthrs_k, dim_t *BM, dim_t *BN, dim_t *BK); + +void partition_unit_diff( + int ithr, int nthr, dim_t n, dim_t *t_offset, dim_t *t_block); +}; // namespace gemm_utils + +} // namespace cpu +} // namespace impl +} // namespace dnnl +#endif // CPU_GEMM_F32_GEMM_UTILS_F32_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/gemm/f32/ref_gemm_f32.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/gemm/f32/ref_gemm_f32.hpp new file mode 100644 index 0000000000000000000000000000000000000000..9a82049f746bf91d6a7219d79fb227e320af8755 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/gemm/f32/ref_gemm_f32.hpp @@ -0,0 +1,37 @@ +/******************************************************************************* +* Copyright 2018-2020 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_GEMM_F32_REF_GEMM_F32_HPP +#define CPU_GEMM_F32_REF_GEMM_F32_HPP + +#include "oneapi/dnnl/dnnl_types.h" + +#include "common/c_types_map.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { + +template +dnnl_status_t ref_gemm(const char *transa, const char *transb, const dim_t *M, + const dim_t *N, const dim_t *K, const data_t *alpha, const data_t *A, + const dim_t *lda, const data_t *B, const dim_t *ldb, const data_t *beta, + data_t *C, const dim_t *ldc, const data_t *bias); +} +} // namespace impl +} // namespace dnnl + +#endif // CPU_GEMM_F32_REF_GEMM_F32_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/gemm/gemm.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/gemm/gemm.hpp new file mode 100644 index 0000000000000000000000000000000000000000..35082757a115ca94e8b8f17265436a186df37b12 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/gemm/gemm.hpp @@ -0,0 +1,93 @@ +/******************************************************************************* +* Copyright 2018-2022 Intel Corporation +* Copyright 2022 Arm Ltd. and affiliates +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_GEMM_GEMM_HPP +#define CPU_GEMM_GEMM_HPP + +#include "oneapi/dnnl/dnnl_types.h" + +#include "common/bfloat16.hpp" + +#include "cpu/platform.hpp" + +#include "cpu/gemm/os_blas.hpp" + +#if DNNL_X64 +#include "cpu/x64/cpu_isa_traits.hpp" +#endif + +#if DNNL_AARCH64 +#include "cpu/aarch64/cpu_isa_traits.hpp" +#endif + +namespace dnnl { +namespace impl { +namespace cpu { + +dnnl_status_t extended_sgemm(const char *transa, const char *transb, + const dim_t *M, const dim_t *N, const dim_t *K, const float *alpha, + const float *A, const dim_t *lda, const float *B, const dim_t *ldb, + const float *beta, float *C, const dim_t *ldc, + const float *bias = nullptr, bool force_jit_gemm = false); + +template +dnnl_status_t gemm_s8x8s32(const char *transa, const char *transb, + const char *offsetc, const dim_t *M, const dim_t *N, const dim_t *K, + const float *alpha, const int8_t *A, const dim_t *lda, const int8_t *ao, + const b_dt *B, const dim_t *ldb, const b_dt *bo, const float *beta, + int32_t *c, const dim_t *ldc, const int32_t *co); + +dnnl_status_t gemm_bf16bf16f32(const char *transa, const char *transb, + const dim_t *M, const dim_t *N, const dim_t *K, const float *alpha, + const bfloat16_t *A, const dim_t *lda, const bfloat16_t *B, + const dim_t *ldb, const float *beta, float *C, const dim_t *ldc); + +#if defined(USE_CBLAS) +#define GEMM_IMPL_STR "x64:gemm:blas" +#elif DNNL_X64 +#define GEMM_IMPL_STR "x64:gemm:jit" +#else +#define GEMM_IMPL_STR "gemm:ref" +#endif + +#if USE_MKL_IGEMM +#define IGEMM_S8U8S32_IMPL_STR "x64:gemm_s8u8s32:blas" +#define IGEMM_S8S8S32_IMPL_STR "x64:gemm_s8s8s32:blas" +#elif DNNL_X64 +#define IGEMM_S8U8S32_IMPL_STR "x64:gemm_s8u8s32:jit" +#define IGEMM_S8S8S32_IMPL_STR "x64:gemm_s8s8s32:jit" +#else +#define IGEMM_S8U8S32_IMPL_STR "gemm_s8u8s32:ref" +#define IGEMM_S8S8S32_IMPL_STR "gemm_s8s8s32:ref" +#endif + +#if !defined(USE_MKL_IGEMM) && defined(DNNL_X64) +#define IGEMM_S8U8S32_ISA_STR \ + JIT_IMPL_NAME_HELPER(IGEMM_S8U8S32_IMPL_STR ":", \ + mayiuse(avx512_core_vnni) \ + ? avx512_core_vnni \ + : (mayiuse(avx512_core) ? avx512_core : isa_undef), \ + "") +#else +#define IGEMM_S8U8S32_ISA_STR IGEMM_S8U8S32_IMPL_STR +#endif + +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif // CPU_GEMM_GEMM_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/gemm/gemm_msan_unpoison.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/gemm/gemm_msan_unpoison.hpp new file mode 100644 index 0000000000000000000000000000000000000000..571c1b5bb34e1c3128d96db7ee90d8fe55fef4cd --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/gemm/gemm_msan_unpoison.hpp @@ -0,0 +1,44 @@ +/******************************************************************************* +* Copyright 2020 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_GEMM_GEMM_MSAN_UNPOISON_HPP +#define CPU_GEMM_GEMM_MSAN_UNPOISON_HPP + +namespace dnnl { +namespace impl { +namespace cpu { + +inline void msan_unpoison_matrix( + void *C, dim_t M, dim_t N, dim_t LDC, size_t typesize) { + assert(C != nullptr && LDC >= M && typesize); + if (msan_enabled && C != nullptr) { + if ((M <= 0) || (N <= 0)) return; + + size_t col_size = M * typesize; + size_t col_stride = LDC * typesize; + uint8_t *col = (uint8_t *)C; + for (dim_t j = 0; j < N; j++) { + msan_unpoison(col, col_size); + col += col_stride; + } + } +} + +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/gemm/gemm_pack.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/gemm/gemm_pack.hpp new file mode 100644 index 0000000000000000000000000000000000000000..f6cb34cedc43ea44cf965ac5d462697f86374af2 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/gemm/gemm_pack.hpp @@ -0,0 +1,97 @@ +/******************************************************************************* +* Copyright 2019-2020 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_GEMM_GEMM_PACK_HPP +#define CPU_GEMM_GEMM_PACK_HPP + +#include "oneapi/dnnl/dnnl_config.h" +#include "oneapi/dnnl/dnnl_types.h" + +#include "common/bfloat16.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { + +bool pack_sgemm_supported(); +bool pack_gemm_bf16bf16f32_supported(); + +dnnl_status_t DNNL_API sgemm_pack_get_size(const char *identifier, + const char *transa, const char *transb, const dim_t *M, const dim_t *N, + const dim_t *K, const dim_t *lda, const dim_t *ldb, size_t *size, + bool *pack = nullptr); + +dnnl_status_t DNNL_API gemm_bf16bf16f32_pack_get_size(const char *identifier, + const char *transa, const char *transb, const dim_t *M, const dim_t *N, + const dim_t *K, const dim_t *lda, const dim_t *ldb, size_t *size, + bool *pack = nullptr); + +dnnl_status_t DNNL_API gemm_s8u8s32_pack_get_size(const char *identifier, + const char *transa, const char *transb, const dim_t *M, const dim_t *N, + const dim_t *K, const dim_t *lda, const dim_t *ldb, size_t *size, + bool *pack = nullptr); + +dnnl_status_t DNNL_API gemm_s8s8s32_pack_get_size(const char *identifier, + const char *transa, const char *transb, const dim_t *M, const dim_t *N, + const dim_t *K, const dim_t *lda, const dim_t *ldb, size_t *size, + bool *pack = nullptr); + +dnnl_status_t DNNL_API sgemm_pack(const char *identifier, const char *transa, + const char *transb, const dim_t *M, const dim_t *N, const dim_t *K, + const dim_t *lda, const dim_t *ldb, const float *src, float *dst); + +dnnl_status_t DNNL_API gemm_bf16bf16f32_pack(const char *identifier, + const char *transa, const char *transb, const dim_t *M, const dim_t *N, + const dim_t *K, const dim_t *lda, const dim_t *ldb, + const bfloat16_t *src, bfloat16_t *dst); + +dnnl_status_t DNNL_API gemm_s8u8s32_pack(const char *identifier, + const char *transa, const char *transb, const dim_t *M, const dim_t *N, + const dim_t *K, const dim_t *lda, const dim_t *ldb, const void *src, + void *dst); + +dnnl_status_t DNNL_API gemm_s8s8s32_pack(const char *identifier, + const char *transa, const char *transb, const dim_t *M, const dim_t *N, + const dim_t *K, const dim_t *lda, const dim_t *ldb, const void *src, + void *dst); + +dnnl_status_t DNNL_API sgemm_compute(const char *transa, const char *transb, + const dim_t *M, const dim_t *N, const dim_t *K, const float *A, + const dim_t *lda, const float *B, const dim_t *ldb, const float *beta, + float *C, const dim_t *ldc); + +dnnl_status_t DNNL_API gemm_bf16bf16f32_compute(const char *transa, + const char *transb, const dim_t *M, const dim_t *N, const dim_t *K, + const bfloat16_t *A, const dim_t *lda, const bfloat16_t *B, + const dim_t *ldb, const float *beta, float *C, const dim_t *ldc); + +dnnl_status_t DNNL_API gemm_s8u8s32_compute(const char *transa, + const char *transb, const char *offsetc, const dim_t *M, const dim_t *N, + const dim_t *K, const int8_t *A, const dim_t *lda, const uint8_t *B, + const dim_t *ldb, const float *beta, int32_t *C, const dim_t *ldc, + const int32_t *co); + +dnnl_status_t DNNL_API gemm_s8s8s32_compute(const char *transa, + const char *transb, const char *offsetc, const dim_t *M, const dim_t *N, + const dim_t *K, const int8_t *A, const dim_t *lda, const int8_t *B, + const dim_t *ldb, const float *beta, int32_t *C, const dim_t *ldc, + const int32_t *co); + +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif // CPU_GEMM_GEMM_PACK_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/gemm/os_blas.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/gemm/os_blas.hpp new file mode 100644 index 0000000000000000000000000000000000000000..e9d9e481dac1e2db0a9278ee51ac301edbb6a953 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/gemm/os_blas.hpp @@ -0,0 +1,66 @@ +/******************************************************************************* +* Copyright 2017-2020 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_GEMM_OS_BLAS_HPP +#define CPU_GEMM_OS_BLAS_HPP + +/* oneDNN provides gemm functionality on its own using jit generated + * kernels. This is the only official supported option. + * + * However, for the debugging purposes we keep (internally) an ability + * to use cblas functions from the other libraries. The following macros + * affect the behavior: + * - USE_CBLAS allow using sgemm and other regular BLAS functionality + * - USE_MKL (implies USE_CBLAS) same as above + allow using igemm and + * packed gemm from Intel MKL library. + */ + +#if defined(USE_MKL) + +#if !defined(USE_CBLAS) +#define USE_CBLAS +#endif + +#include "mkl_cblas.h" +#include "mkl_version.h" + +#define USE_MKL_PACKED_GEMM (INTEL_MKL_VERSION >= 20190001) +#define USE_MKL_IGEMM \ + (INTEL_MKL_VERSION >= 20180000 && __INTEL_MKL_BUILD_DATE >= 20170628) + +#else /* defined(USE_MKL) */ + +#define USE_MKL_PACKED_GEMM 0 +#define USE_MKL_IGEMM 0 + +#if defined(USE_CBLAS) + +#if defined(_SX) +extern "C" { +#endif + +#include "cblas.h" + +#if defined(_SX) +} +#endif + +#endif /* defined(USE_CBLAS) */ +#endif /* defined(USE_MKL) */ + +#endif /* CPU_GEMM_OS_BLAS_HPP */ + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/gemm/s8x8s32/ref_gemm_s8x8s32.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/gemm/s8x8s32/ref_gemm_s8x8s32.hpp new file mode 100644 index 0000000000000000000000000000000000000000..913db94e6c1e925ec0f1afb3345f33534b7834ed --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/gemm/s8x8s32/ref_gemm_s8x8s32.hpp @@ -0,0 +1,39 @@ +/******************************************************************************* +* Copyright 2018-2020 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_GEMM_S8X8S32_REF_GEMM_S8X8S32_HPP +#define CPU_GEMM_S8X8S32_REF_GEMM_S8X8S32_HPP + +#include + +#include "oneapi/dnnl/dnnl_types.h" + +#include "common/c_types_map.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { + +template +dnnl_status_t ref_gemm_s8x8s32(const char *transa, const char *transb, + const char *offsetc, const dim_t *M, const dim_t *N, const dim_t *K, + const float *alpha, const int8_t *A, const dim_t *LDA, const int8_t *ao, + const b_dt *B, const dim_t *LDB, const b_dt *bo, const float *beta, + int32_t *C, const dim_t *LDC, const int32_t *co); +} +} // namespace impl +} // namespace dnnl +#endif // CPU_GEMM_S8X8S32_REF_GEMM_S8X8S32_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/gemm/s8x8s32/simple_gemm_s8s8s32.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/gemm/s8x8s32/simple_gemm_s8s8s32.hpp new file mode 100644 index 0000000000000000000000000000000000000000..9a92f5d60696710b2243ed72fb5371ca2dce1c99 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/gemm/s8x8s32/simple_gemm_s8s8s32.hpp @@ -0,0 +1,39 @@ +/******************************************************************************* +* Copyright 2018-2020 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_GEMM_S8X8S32_SIMPLE_GEMM_S8S8S32_HPP +#define CPU_GEMM_S8X8S32_SIMPLE_GEMM_S8S8S32_HPP + +#include + +#include "oneapi/dnnl/dnnl_types.h" + +#include "common/c_types_map.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { + +dnnl_status_t simple_gemm_s8s8s32(const char *transA, const char *transB, + const char *offsetC, const dim_t *m, const dim_t *n, const dim_t *k, + const float *alpha, const int8_t *a, const dim_t *lda, const int8_t *oa, + const int8_t *b, const dim_t *ldb, const int8_t *ob, const float *beta, + int32_t *c, const dim_t *ldc, const int32_t *oc); +} +} // namespace impl +} // namespace dnnl + +#endif // CPU_GEMM_S8X8S32_SIMPLE_GEMM_S8S8S32_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/jit_utils/jit_utils.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/jit_utils/jit_utils.hpp new file mode 100644 index 0000000000000000000000000000000000000000..6636f97648b13ba93c2bfcd41b1f62bc07507510 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/jit_utils/jit_utils.hpp @@ -0,0 +1,34 @@ +/******************************************************************************* +* Copyright 2019-2021 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_JIT_UTILS_JIT_UTILS_HPP +#define CPU_JIT_UTILS_JIT_UTILS_HPP + +#include + +namespace dnnl { +namespace impl { +namespace cpu { +namespace jit_utils { + +void register_jit_code(const void *code, size_t code_size, + const char *code_name, const char *source_file_name); + +} +} // namespace cpu +} // namespace impl +} // namespace dnnl +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/jit_utils/linux_perf/linux_perf.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/jit_utils/linux_perf/linux_perf.hpp new file mode 100644 index 0000000000000000000000000000000000000000..5ec927e1252a1cd84a28cd679f9261977762fb87 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/jit_utils/linux_perf/linux_perf.hpp @@ -0,0 +1,39 @@ +/******************************************************************************* +* Copyright 2019-2021 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_JIT_UTILS_LINUX_PERF_LINUX_PERF_HPP +#define CPU_JIT_UTILS_LINUX_PERF_LINUX_PERF_HPP + +#ifdef __linux__ +#include + +namespace dnnl { +namespace impl { +namespace cpu { +namespace jit_utils { + +void linux_perf_jitdump_record_code_load( + const void *code, size_t code_size, const char *code_name); + +void linux_perf_perfmap_record_code_load( + const void *code, size_t code_size, const char *code_name); +} // namespace jit_utils +} // namespace cpu +} // namespace impl +} // namespace dnnl +#endif + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/matmul/cpu_matmul_pd.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/matmul/cpu_matmul_pd.hpp new file mode 100644 index 0000000000000000000000000000000000000000..7306b890c2457277ace2502e8cf8b419f98dde24 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/matmul/cpu_matmul_pd.hpp @@ -0,0 +1,38 @@ +/******************************************************************************* +* Copyright 2019-2020 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_MATMUL_CPU_MATMUL_PD_HPP +#define CPU_MATMUL_CPU_MATMUL_PD_HPP + +#include "common/matmul_pd.hpp" + +#include "cpu/cpu_engine.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace matmul { + +struct cpu_matmul_pd_t : public matmul_pd_t { + using matmul_pd_t::matmul_pd_t; +}; + +} // namespace matmul +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/matmul/gemm_based_common.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/matmul/gemm_based_common.hpp new file mode 100644 index 0000000000000000000000000000000000000000..0886ec4be089c29d14e8ecb6e56d4e896a1366e2 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/matmul/gemm_based_common.hpp @@ -0,0 +1,168 @@ +/******************************************************************************* +* Copyright 2019-2022 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_MATMUL_GEMM_BASED_COMMON_HPP +#define CPU_MATMUL_GEMM_BASED_COMMON_HPP + +#include + +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/primitive_attr.hpp" +#include "common/type_helpers.hpp" + +#include "cpu/matmul/cpu_matmul_pd.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace matmul { +namespace gemm_based { + +struct params_t { + // indicates if an auxiliary array for intermediate computations is not + // required + bool dst_is_acc_; + + // indicates if output scales from attributes are applied + // by gemm (alpha parameter) or post-op kernel (pp_kernel_) + bool gemm_applies_output_scales_ = false; + + // sum post-op scaling factor that is fused into gemm + float gemm_beta_ = 0.f; + + // indicates if a special post processing kernel + // should be invoked after gemm + bool has_pp_kernel_ = false; + + // indicates if src batch dims can be fused into M, so that a single + // GeMM call can be made + bool use_single_gemm_call_optimization_ = false; + + float default_pp_scales_ = 1.0f; + + // an attribute for post processing kernel + primitive_attr_t pp_attr_; + + // auxiliary functions + + // returns gemm alpha parameter (a single value for now) + float get_gemm_alpha(const float *primitive_scales) const { + return gemm_applies_output_scales_ ? primitive_scales[0] : 1.f; + } + + // returns scaling factors for post processing kernel + const float *get_post_processing_scales( + const float *primitive_scales) const { + return gemm_applies_output_scales_ ? &default_pp_scales_ + : primitive_scales; + } +}; + +inline bool check_gemm_compatible_formats(const matmul_pd_t &pd) { + + const memory_desc_wrapper dst_d(pd.dst_md()); + const int ndims = dst_d.ndims(); + + auto check_input_format = [=](const memory_desc_t *md) { + memory_desc_wrapper mdw(md); + + if (!mdw.is_plain()) return false; + + const dims_t &strides = mdw.blocking_desc().strides; + + // disable md with zero stride for a particular dimension + for (int dim = 0; dim < ndims; ++dim) + if (strides[dim] == 0) return false; + + // for GeMM atleast one of the two innermost axes must be contiguous + return utils::one_of(1, strides[ndims - 1], strides[ndims - 2]); + }; + + bool ok = check_input_format(pd.src_md()) + && check_input_format(pd.weights_md()) && dst_d.is_plain() + && dst_d.blocking_desc().strides[ndims - 1] == 1; + + return ok; +} + +inline bool check_gemm_binary_per_oc_compatible_formats(const matmul_pd_t &pd) { + const memory_desc_wrapper dst_d(pd.dst_md()); + const dims_t &strides = dst_d.blocking_desc().strides; + const dims_t &dims = dst_d.dims(); + const int ndims = dst_d.ndims(); + + // check d, h, w... (b2, m, n... for matmul) dimensions are continuous + bool ok = true; + for (int i = 2; i < ndims - 1; i++) + ok = ok && strides[i] == strides[i + 1] * dims[i + 1]; + // only allowed for nchw and nhwc (b0xb1xMxN or b0xMxNxb1 for matmul) + return ok && strides[0] == utils::array_product(dims + 1, ndims - 1); +} + +inline size_t get_scratchpad_block_elements(const dim_t batch, dim_t M, + const dim_t N, const bool use_single_gemm_call_optimization, + const int nthr) { + assert(batch > 0); + assert(M > 0); + assert(N > 0); + size_t buffer_size; + if (use_single_gemm_call_optimization) { + buffer_size = (size_t)batch * M * N; + } else { + const size_t work_per_thr = utils::div_up((size_t)batch * M * N, nthr); + if (work_per_thr >= (size_t)N) { + buffer_size = nstl::min( + (size_t)M * N, utils::rnd_dn(work_per_thr, N)); + } else { + buffer_size = work_per_thr; + } + } + return utils::rnd_up(buffer_size, 64); +} + +inline size_t get_scratchpad_num_elements(const dim_t batch, dim_t M, + const dim_t N, const bool use_single_gemm_call_optimization, + const int nthr) { + const int num_scratchpad_blocks + = use_single_gemm_call_optimization ? 1 : nthr; + return get_scratchpad_block_elements( + batch, M, N, use_single_gemm_call_optimization, nthr) + * num_scratchpad_blocks; +} + +inline void book_acc_scratchpad(matmul_pd_t &pd, const params_t ¶ms, + size_t sizeof_acc_data, const int nthr) { + + if (params.dst_is_acc_) return; // scratchpad buffer is not required + + // scratchpad buffer must be allocated on execution stage + if (pd.has_runtime_dims_or_strides()) return; + + const size_t buffer_size = get_scratchpad_num_elements(pd.batch(), pd.M(), + pd.N(), params.use_single_gemm_call_optimization_, nthr); + auto scratchpad = pd.scratchpad_registry().registrar(); + scratchpad.book(memory_tracking::names::key_matmul_dst_in_acc_dt, + buffer_size, sizeof_acc_data); +} + +} // namespace gemm_based +} // namespace matmul +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/matmul/gemm_bf16_matmul.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/matmul/gemm_bf16_matmul.hpp new file mode 100644 index 0000000000000000000000000000000000000000..c8d5d5649fce392013b038b2c1989a100bf05345 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/matmul/gemm_bf16_matmul.hpp @@ -0,0 +1,115 @@ +/******************************************************************************* +* Copyright 2019-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_MATMUL_GEMM_BF16_MATMUL_HPP +#define CPU_MATMUL_GEMM_BF16_MATMUL_HPP + +#include + +#include "common/bfloat16.hpp" +#include "common/c_types_map.hpp" +#include "common/primitive.hpp" +#include "common/type_helpers.hpp" + +#include "cpu/gemm_inner_product_utils.hpp" + +#include "cpu/matmul/cpu_matmul_pd.hpp" +#include "cpu/matmul/gemm_based_common.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace matmul { + +template +struct gemm_bf16_matmul_t : public primitive_t { + struct pd_t : public cpu_matmul_pd_t { + using cpu_matmul_pd_t::cpu_matmul_pd_t; + + DECLARE_COMMON_PD_T("gemm:jit:bf16", gemm_bf16_matmul_t); + + status_t init(engine_t *engine); + const gemm_based::params_t ¶ms() const { return params_; } + + int nthr_; // To not exceed the limit in execute used for set up. + + private: + status_t check_and_configure_attributes(); + gemm_based::params_t params_; + }; + + gemm_bf16_matmul_t(const pd_t *apd) : primitive_t(apd) {} + + status_t init(engine_t *engine) override { + if (pd()->params().has_pp_kernel_) { + const bool has_runtime_dims + = memory_desc_wrapper(pd()->dst_md()).has_runtime_dims(); + const int nthr = pd()->nthr_; + const dim_t batch = pd()->batch(); + const dim_t M = pd()->M(); + + // mb value is calculated based on work-sharing using + // balance211 in execute() + dim_t mb = DNNL_RUNTIME_DIM_VAL; + if (!has_runtime_dims && ((batch * M) % nthr == 0)) { + const dim_t m_per_thr = nstl::max(1, (batch * M) / nthr); + if (m_per_thr >= M && m_per_thr % M == 0) { + mb = M; + } else if (m_per_thr < M && M % m_per_thr == 0) { + mb = m_per_thr; + } + } + + const bool skip_sum + = should_skip_sum_po(); // sum can be done by gemm itself + CHECK(safe_ptr_assign(pp_kernel_, + inner_product_utils::pp_kernel_t::create(pd()->N(), mb, + pd()->ldc(), &pd()->params().pp_attr_, + pd()->desc()->bias_desc.data_type, + pd()->desc()->accum_data_type, pd()->dst_md(), + skip_sum))); + return pp_kernel_->create_kernel(); + } + return status::success; + } + + static constexpr data_type_t src_type = data_type::bf16; + static constexpr data_type_t weights_type = data_type::bf16; + static constexpr data_type_t acc_type = data_type::f32; + + typedef typename prec_traits::type src_data_t; + typedef typename prec_traits::type weights_data_t; + typedef typename prec_traits::type dst_data_t; + typedef typename prec_traits::type acc_data_t; + + status_t execute(const exec_ctx_t &ctx) const override { + return execute_ref(ctx); + } + +private: + bool should_skip_sum_po() const noexcept; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + status_t execute_ref(const exec_ctx_t &ctx) const; + + std::unique_ptr pp_kernel_; +}; + +} // namespace matmul +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/matmul/gemm_f32_matmul.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/matmul/gemm_f32_matmul.hpp new file mode 100644 index 0000000000000000000000000000000000000000..66c70b0b532e3f567a5caf01d1ee0841eab61850 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/matmul/gemm_f32_matmul.hpp @@ -0,0 +1,116 @@ +/******************************************************************************* +* Copyright 2019-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_MATMUL_GEMM_F32_MATMUL_HPP +#define CPU_MATMUL_GEMM_F32_MATMUL_HPP + +#include + +#include "common/c_types_map.hpp" +#include "common/primitive.hpp" +#include "common/type_helpers.hpp" + +#include "cpu/gemm_inner_product_utils.hpp" + +#include "cpu/matmul/cpu_matmul_pd.hpp" +#include "cpu/matmul/gemm_based_common.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace matmul { + +struct gemm_f32_matmul_t : public primitive_t { + struct pd_t : public cpu_matmul_pd_t { + using cpu_matmul_pd_t::cpu_matmul_pd_t; + + DECLARE_COMMON_PD_T("gemm:jit:f32", gemm_f32_matmul_t); + + status_t init(engine_t *engine); + const gemm_based::params_t ¶ms() const { return params_; } + + int nthr_; // To not exceed the limit in execute used for set up. + + private: + status_t check_and_configure_attributes(); + gemm_based::params_t params_; + }; + + gemm_f32_matmul_t(const pd_t *apd) : primitive_t(apd) {} + + status_t init(engine_t *engine) override { + if (pd()->params().has_pp_kernel_) { + const bool has_runtime_dims + = memory_desc_wrapper(pd()->dst_md()).has_runtime_dims(); + const int nthr = pd()->nthr_; + const dim_t batch = pd()->batch(); + const dim_t M = pd()->M(); + + // mb value is calculated based on work-sharing using + // balance211 in execute() + dim_t mb = DNNL_RUNTIME_DIM_VAL; + if (!has_runtime_dims && ((batch * M) % nthr == 0)) { + const dim_t m_per_thr = nstl::max(1, (batch * M) / nthr); + if (m_per_thr >= M && m_per_thr % M == 0) { + mb = M; + } else if (m_per_thr < M && M % m_per_thr == 0) { + mb = m_per_thr; + } + } + + const bool skip_sum = should_skip_sum_po( + pd()->dst_md() + ->data_type); // sum can be done by gemm itself + CHECK(safe_ptr_assign(pp_kernel_, + inner_product_utils::pp_kernel_t::create(pd()->N(), mb, + pd()->ldc(), &pd()->params().pp_attr_, + pd()->desc()->bias_desc.data_type, + pd()->desc()->accum_data_type, pd()->dst_md(), + skip_sum))); + return pp_kernel_->create_kernel(); + } + + return status::success; + } + + static constexpr data_type_t src_type = data_type::f32; + static constexpr data_type_t weights_type = data_type::f32; + static constexpr data_type_t dst_type = data_type::f32; + static constexpr data_type_t acc_type = data_type::f32; + + typedef typename prec_traits::type src_data_t; + typedef typename prec_traits::type weights_data_t; + typedef typename prec_traits::type dst_data_t; + typedef typename prec_traits::type acc_data_t; + + status_t execute(const exec_ctx_t &ctx) const override { + return execute_ref(ctx); + } + +private: + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + status_t execute_ref(const exec_ctx_t &ctx) const; + bool should_skip_sum_po(data_type_t dst_dt) const noexcept; + + std::unique_ptr pp_kernel_; +}; + +} // namespace matmul +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/matmul/gemm_x8s8s32x_matmul.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/matmul/gemm_x8s8s32x_matmul.hpp new file mode 100644 index 0000000000000000000000000000000000000000..26de28da289d85853566315c94121abdf0644647 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/matmul/gemm_x8s8s32x_matmul.hpp @@ -0,0 +1,102 @@ +/******************************************************************************* +* Copyright 2019-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_MATMUL_GEMM_X8S8S32X_MATMUL_HPP +#define CPU_MATMUL_GEMM_X8S8S32X_MATMUL_HPP + +#include + +#include + +#include "common/c_types_map.hpp" +#include "common/primitive.hpp" +#include "common/type_helpers.hpp" + +#include "cpu/gemm_inner_product_utils.hpp" + +#include "cpu/matmul/cpu_matmul_pd.hpp" +#include "cpu/matmul/gemm_based_common.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace matmul { + +struct gemm_x8s8s32x_matmul_t : public primitive_t { + struct pd_t : public cpu_matmul_pd_t { + using cpu_matmul_pd_t::cpu_matmul_pd_t; + + DECLARE_COMMON_PD_T("gemm:jit", gemm_x8s8s32x_matmul_t); + + status_t init(engine_t *engine); + const gemm_based::params_t ¶ms() const { return params_; } + + int nthr_; // To not exceed the limit in execute used for set up. + + private: + gemm_based::params_t params_; + }; + + gemm_x8s8s32x_matmul_t(const pd_t *apd) : primitive_t(apd) {} + + status_t init(engine_t *engine) override { + if (pd()->params().has_pp_kernel_) { + const bool has_runtime_dims + = memory_desc_wrapper(pd()->dst_md()).has_runtime_dims(); + const int nthr = pd()->nthr_; + const dim_t batch = pd()->batch(); + const dim_t M = pd()->M(); + + // mb value is calculated based on work-sharing using + // balance211 in execute() + dim_t mb = DNNL_RUNTIME_DIM_VAL; + if (!has_runtime_dims && ((batch * M) % nthr == 0)) { + const dim_t m_per_thr = nstl::max(1, (batch * M) / nthr); + if (m_per_thr >= M && m_per_thr % M == 0) { + mb = M; + } else if (m_per_thr < M && M % m_per_thr == 0) { + mb = m_per_thr; + } + } + + CHECK(safe_ptr_assign(pp_kernel_, + inner_product_utils::pp_kernel_t::create(pd()->N(), mb, + pd()->ldc(), &pd()->params().pp_attr_, + pd()->desc()->bias_desc.data_type, + pd()->desc()->accum_data_type, pd()->dst_md(), + false))); + return pp_kernel_->create_kernel(); + } + return status::success; + } + + status_t execute(const exec_ctx_t &ctx) const override { + return execute_ref(ctx); + } + +private: + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + status_t execute_ref(const exec_ctx_t &ctx) const; + + std::unique_ptr pp_kernel_; +}; + +} // namespace matmul +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/matmul/matmul_utils.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/matmul/matmul_utils.hpp new file mode 100644 index 0000000000000000000000000000000000000000..1030aeb097f768aff521cf1454bb87f6d379a997 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/matmul/matmul_utils.hpp @@ -0,0 +1,184 @@ +/******************************************************************************* +* Copyright 2020-2023 Intel Corporation +* Copyright 2022 Arm Ltd. and affiliates +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_MATMUL_UTILS_HPP +#define CPU_MATMUL_UTILS_HPP + +#include "common/memory_desc_wrapper.hpp" +#include "common/utils.hpp" + +#include "cpu/binary_injector_utils.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { + +namespace matmul { + +struct matmul_helper_t { + using mdw_t = const memory_desc_wrapper; + + matmul_helper_t(mdw_t &src_md, mdw_t &weights_md, mdw_t &dst_md) + : src_md_(src_md), weights_md_(weights_md), dst_md_(dst_md) {} + + int ndims() const { return dst_md_.ndims(); } + bool batched() const { return ndims() > 2; } + + dim_t batch() const { return get_batch_size(dst_md_); }; + dim_t src_batch() const { return get_batch_size(src_md_); }; + dim_t wei_batch() const { return get_batch_size(weights_md_); }; + + dim_t M() const { return dst_md_.dims()[ndims() - 2]; } + dim_t N() const { return dst_md_.dims()[ndims() - 1]; } + dim_t K() const { return src_md_.dims()[ndims() - 1]; } + + char transA() const { + const auto &strides = &src_md_.blocking_desc().strides[ndims() - 2]; + return (strides[1] == 1 && src_md_.dims()[ndims() - 2] > 1) ? 'N' : 'T'; + } + + char transB() const { + const auto &strides = &weights_md_.blocking_desc().strides[ndims() - 2]; + return (strides[1] == 1 && weights_md_.dims()[ndims() - 2] > 1) ? 'N' + : 'T'; + } + + dim_t lda() const { + const auto &strides = &src_md_.blocking_desc().strides[ndims() - 2]; + return strides[transA() == 'N' ? 0 : 1]; + } + + dim_t get_a_stride(int dim) const { + if (dim >= ndims() || dim < 0) return 0; + return src_md_.blocking_desc().strides[dim]; + } + + dim_t ldb() const { + const auto &strides = &weights_md_.blocking_desc().strides[ndims() - 2]; + return strides[transB() == 'N' ? 0 : 1]; + } + + dim_t ldc() const { return dst_md_.blocking_desc().strides[ndims() - 2]; } + + bool use_single_gemm_call_optimization(const post_ops_t &post_ops) { + using namespace binary_injector_utils; + bool is_binary_po_per_oc; + bool is_binary_po_per_oc_sp; + bool is_binary_po_channel_bcast; + std::tie(is_binary_po_per_oc, is_binary_po_per_oc_sp, + is_binary_po_channel_bcast) + = bcast_strategies_present_tup(post_ops.entry_, dst_md_, + broadcasting_strategy_t::per_oc, + broadcasting_strategy_t::per_oc_spatial, + broadcasting_strategy_t::per_mb_spatial); + + const bool can_use_po_with_fused_batch = !is_binary_po_channel_bcast + && IMPLICATION(is_binary_po_per_oc || is_binary_po_per_oc_sp, + ndims() == 2); + + // single GeMM call can be made, avoid parallelization over GeMM calls + return can_use_po_with_fused_batch && can_fuse_src_batch_dims(); + } + +private: + mdw_t src_md_; + mdw_t weights_md_; + mdw_t dst_md_; + + // TODO similar optimization is also possible for wei batch fusion. + bool can_fuse_src_batch_dims() const { + /* Note: + We can fuse src batch dims so that a single GeMM can be used if + 0. always for batch = 1 case + 1. src is not transposed + 2. wei batch dims are all 1's + 3. The strides in batch dims are trivial (allowing permutations). + 4. src and dst layout are identical. Example: + src layout : {batch dim_idx permutations}xMxK + dst layout : {identical batch dim_idx perm}xMxN; + + For example, + src_layout : aXdXcXbXmXk + wei_layout: 1X1X1X1xkxn or 1X1X1X1xnxk + dst_layout : aXdXcXbXmXn + + A single GeMM call can be used instead with m = a*d*c*b*m + */ + // Note 0: + if (batch() == 1) return true; + + // Note 1: + if (transA() == 'T') return false; + + // Note 2: + if (wei_batch() != 1) return false; + + // determine batch dims layout + dims_t src_strides; + const int batch_ndims = ndims() - 2; + utils::array_copy( + src_strides, src_md_.blocking_desc().strides, batch_ndims); + + // compute ou_dims. It is required to get correct perm + dims_t blocks = {0}; + src_md_.compute_blocks(blocks); + dims_t ou_dims; + for (int i = 0; i < batch_ndims; ++i) + ou_dims[i] = src_md_.padded_dims()[i] / blocks[i]; + + dims_t perm; + for (int i = 0; i < batch_ndims; ++i) + perm[i] = i; + + // permute batch dim idx by sorting based on strides. + utils::simultaneous_sort(src_strides, ou_dims, perm, batch_ndims, + [](stride_t a, stride_t b) { return a - b; }); + + dim_t src_stride = M() * lda(); + dim_t dst_stride = M() * ldc(); + + // Note 3-4: + for (int i = 0; i < batch_ndims; ++i) { + const int dim_idx = perm[i]; + if (src_md_.blocking_desc().strides[dim_idx] != src_stride + || dst_md_.blocking_desc().strides[dim_idx] != dst_stride) + return false; + src_stride = src_stride * src_md_.dims()[dim_idx]; + dst_stride = dst_stride * dst_md_.dims()[dim_idx]; + } + + return true; + } + dim_t get_batch_size(const mdw_t &tensor_md) const { + int batch_dims = ndims() - 2; + dim_t batch_size = 1; + for (int b_idx = 0; b_idx < batch_dims; b_idx++) { + dim_t batch_dim = tensor_md.dims()[b_idx]; + if (DNNL_RUNTIME_DIM_VAL == batch_dim) return DNNL_RUNTIME_DIM_VAL; + + batch_size *= batch_dim; + } + + return batch_size; + } +}; + +} // namespace matmul +} // namespace cpu +} // namespace impl +} // namespace dnnl +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/matmul/ref_matmul.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/matmul/ref_matmul.hpp new file mode 100644 index 0000000000000000000000000000000000000000..f7ab1bee329be89026a890edfd33401b91f136fa --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/matmul/ref_matmul.hpp @@ -0,0 +1,105 @@ +/******************************************************************************* +* Copyright 2019-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_MATMUL_REF_MATMUL_HPP +#define CPU_MATMUL_REF_MATMUL_HPP + +#include + +#include "common/bfloat16.hpp" +#include "common/c_types_map.hpp" +#include "common/primitive.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/platform.hpp" +#include "cpu/primitive_attr_postops.hpp" + +#include "cpu/matmul/cpu_matmul_pd.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace matmul { + +struct ref_matmul_t : public primitive_t { + struct pd_t : public cpu_matmul_pd_t { + using cpu_matmul_pd_t::cpu_matmul_pd_t; + + DECLARE_COMMON_PD_T("ref:any", ref_matmul_t); + + status_t init(engine_t *engine) { + using namespace data_type; + using smask_t = primitive_attr_t::skip_mask_t; + const auto src_type = src_md(0)->data_type; + const auto wei_type = weights_md(0)->data_type; + const auto bia_type = weights_md(1)->data_type; + const auto dst_type = dst_md(0)->data_type; + + bool ok = is_dense_data() && utils::one_of(src_type, f32, bf16, f16) + && utils::one_of(wei_type, f32, bf16, f16) + && utils::one_of(dst_type, f32, bf16, f16) + && src_type == wei_type + && IMPLICATION(src_type == f32, dst_type == f32) + && IMPLICATION(src_type == bf16, + utils::one_of(dst_type, f32, bf16)) + && IMPLICATION( + src_type == f16, utils::one_of(dst_type, f32, f16)) + && IMPLICATION(with_bias(), + utils::one_of(bia_type, f32, bf16, f16) + && IMPLICATION( + src_type == f32, bia_type == f32) + && IMPLICATION(src_type == f16, + utils::one_of(bia_type, f32, f16)) + && IMPLICATION(src_type == bf16, + utils::one_of(bia_type, f32, bf16))) + && platform::has_data_type_support(src_type) + && attr()->has_default_values(smask_t::scales_runtime + | smask_t::post_ops | smask_t::sum_dt, + dst_type) + && attr_.post_ops_.check_sum_consistency(dst_type, + /* is_int8 */ false) + && attr_scales_ok() && set_default_formats() + && attr_.set_default_formats(dst_md(0)) == status::success; + return ok ? status::success : status::unimplemented; + } + }; + + ref_matmul_t(const pd_t *apd) : primitive_t(apd) {} + + status_t init(engine_t *engine) override { + ref_post_ops + = utils::make_unique(pd()->attr()->post_ops_); + if (!ref_post_ops) return status::out_of_memory; + return status::success; + } + + status_t execute(const exec_ctx_t &ctx) const override { + return execute_ref(ctx); + } + +private: + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + status_t execute_ref(const exec_ctx_t &ctx) const; + std::unique_ptr ref_post_ops; +}; + +} // namespace matmul +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/matmul/ref_matmul_int8.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/matmul/ref_matmul_int8.hpp new file mode 100644 index 0000000000000000000000000000000000000000..67b0e1f6f6103df71d20e9d582dfd0c62d5a38e8 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/matmul/ref_matmul_int8.hpp @@ -0,0 +1,104 @@ +/******************************************************************************* +* Copyright 2021-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_MATMUL_REF_MATMUL_INT8_HPP +#define CPU_MATMUL_REF_MATMUL_INT8_HPP + +#include + +#include "common/c_types_map.hpp" +#include "common/primitive.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/platform.hpp" +#include "cpu/primitive_attr_postops.hpp" + +#include "cpu/matmul/cpu_matmul_pd.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace matmul { + +struct ref_matmul_int8_t : public primitive_t { + struct pd_t : public cpu_matmul_pd_t { + using cpu_matmul_pd_t::cpu_matmul_pd_t; + + DECLARE_COMMON_PD_T("ref:any", ref_matmul_int8_t); + + status_t init(engine_t *engine) { + using namespace data_type; + using smask_t = primitive_attr_t::skip_mask_t; + const auto src_type = src_md(0)->data_type; + const auto wei_type = weights_md(0)->data_type; + const auto bia_type = weights_md(1)->data_type; + const auto dst_type = dst_md(0)->data_type; + + bool ok = utils::one_of(src_type, s8, u8) && wei_type == s8 + && IMPLICATION(with_bias(), + utils::one_of(bia_type, f32, bf16, s32, s8, u8)) + && utils::one_of(dst_type, f32, bf16, s32, s8, u8) + && attr()->has_default_values(smask_t::scales_runtime + | smask_t::zero_points_runtime + | smask_t::post_ops | smask_t::sum_dt, + dst_type) + && attr_.post_ops_.check_sum_consistency(dst_type, + /* is_int8 */ true) + && attr_scales_ok() && attr_zero_points_ok() + && set_default_formats() + && attr_.set_default_formats(dst_md(0)) == status::success; + return ok ? status::success : status::unimplemented; + } + + private: + bool attr_zero_points_ok() const { + int mask_src = 0, mask_wei = 0, mask_dst = 0; + attr()->zero_points_.get(DNNL_ARG_SRC, &mask_src); + attr()->zero_points_.get(DNNL_ARG_WEIGHTS, &mask_wei); + attr()->zero_points_.get(DNNL_ARG_DST, &mask_dst); + + return (mask_src == 0 || (ndims() == 2 && mask_src == 1 << 1)) + && (mask_wei == 0) + && (mask_dst == 0 || (ndims() == 2 && mask_dst == 1 << 1)); + } + }; + + ref_matmul_int8_t(const pd_t *apd) : primitive_t(apd) {} + + status_t init(engine_t *engine) override { + ref_post_ops + = utils::make_unique(pd()->attr()->post_ops_); + if (!ref_post_ops) return status::out_of_memory; + return status::success; + } + + status_t execute(const exec_ctx_t &ctx) const override { + return execute_ref(ctx); + } + +private: + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + status_t execute_ref(const exec_ctx_t &ctx) const; + std::unique_ptr ref_post_ops; +}; + +} // namespace matmul +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/matmul/ref_sparse_matmul.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/matmul/ref_sparse_matmul.hpp new file mode 100644 index 0000000000000000000000000000000000000000..beeac35fcaa81348812d2d74a131449e65e5ed03 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/matmul/ref_sparse_matmul.hpp @@ -0,0 +1,90 @@ +/******************************************************************************* +* Copyright 2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_MATMUL_REF_SPARSE_MATMUL_HPP +#define CPU_MATMUL_REF_SPARSE_MATMUL_HPP + +#include "common/c_types_map.hpp" +#include "common/primitive.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/matmul/cpu_matmul_pd.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace matmul { + +struct ref_sparse_matmul_t : public primitive_t { + struct pd_t : public cpu_matmul_pd_t { + using cpu_matmul_pd_t::cpu_matmul_pd_t; + + DECLARE_COMMON_PD_T("ref:any", ref_sparse_matmul_t); + + status_t init(engine_t *engine) { + using namespace data_type; + const auto src_type = src_md(0)->data_type; + const auto wei_type = weights_md(0)->data_type; + const auto dst_type = dst_md(0)->data_type; + + memory_desc_wrapper src_d(src_md()); + memory_desc_wrapper wei_d(weights_md(0)); + + const bool ok + = utils::everyone_is(f32, src_type, wei_type, dst_type) + && utils::one_of(true, wei_d.is_sparse_desc(), + src_d.is_sparse_desc()) + && IMPLICATION( + wei_d.is_sparse_desc(), !src_d.is_sparse_desc()) + && IMPLICATION(src_d.is_sparse_desc(), + utils::everyone_is(s32, src_d.metadata_type(0), + src_d.metadata_type(1))) + && IMPLICATION(wei_d.is_sparse_desc(), + utils::everyone_is(s32, wei_d.metadata_type(0), + wei_d.metadata_type(1))) + && !with_bias() && attr()->has_default_values() + && set_default_formats() && formats_ok(src_d, wei_d); + return ok ? status::success : status::unimplemented; + } + + bool formats_ok(const memory_desc_wrapper &src_d, + const memory_desc_wrapper &wei_d) const { + if (!memory_desc_wrapper(dst_md()).matches_one_of_tag( + format_tag::ab)) + return false; + if (src_d.is_sparse_desc()) + return wei_d.matches_one_of_tag(format_tag::ab); + if (wei_d.is_sparse_desc()) + return src_d.matches_one_of_tag(format_tag::ab); + return false; + } + }; + + ref_sparse_matmul_t(const pd_t *apd) : primitive_t(apd) {} + + status_t execute(const exec_ctx_t &ctx) const override; + +private: + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } +}; + +} // namespace matmul +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/ppc64/ppc64_gemm_driver.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/ppc64/ppc64_gemm_driver.hpp new file mode 100644 index 0000000000000000000000000000000000000000..d71fd2d7ac5feb8871e69dfb627692f4984c2a74 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/ppc64/ppc64_gemm_driver.hpp @@ -0,0 +1,33 @@ +/******************************************************************************* +* Copyright 2022 IBM Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_PPC64_GEMM_GEMM_DRIVER_HPP +#define CPU_PPC64_GEMM_GEMM_DRIVER_HPP + +namespace dnnl { +namespace impl { +namespace cpu { +namespace ppc64 { + +dnnl_status_t cblas_gemm_s8x8s32_ppc64(int, int, char const *, dim_t, dim_t, + dim_t, float, int8_t const *, dim_t, int8_t const *, uint8_t const *, + dim_t, uint8_t const *, int *, float, dim_t, int const *, int); + +} // namespace ppc64 +} // namespace cpu +} // namespace impl +} // namespace dnnl +#endif // CPU_PPC64_GEMM_GEMM_DRIVER_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/ppc64/ppc64_gemm_s8x8s32.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/ppc64/ppc64_gemm_s8x8s32.hpp new file mode 100644 index 0000000000000000000000000000000000000000..d61331caee8be4a58a83d3aadea22381ae7767e2 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/ppc64/ppc64_gemm_s8x8s32.hpp @@ -0,0 +1,3074 @@ +/******************************************************************************* +* Copyright 2022 IBM Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include +#include "cpu/simple_q10n.hpp" + +namespace dnnl { +namespace impl { + +uint64_t mker; + +typedef __vector signed long long vec_i64 __attribute__((aligned(8))); +typedef __vector short vec_i16 __attribute__((aligned(2))); +typedef __vector unsigned char vec_t; +typedef __vector signed char vec_st; + +int pack_N16_16bit(dim_t k, dim_t m, short *a, dim_t lda, short *ap) { + int32_t i, j; + int32_t kcell, cell, koff, moff, krows, mrows, block4, block2, mcell, + chunk4count, k8, m4, m16; + int32_t m_cap = (m + 3) & ~3; + int32_t k_cap = (k + 1) & ~1; + krows = (k + 1) >> 1; + mrows = (m + 3) >> 2; + block4 = 4 * krows; + block2 = 2 * krows; + k8 = (k >> 3) << 3; + m4 = (m >> 2) << 2; + m16 = (m >> 4) << 4; + + // MAIN BLOCK + for (j = 0; j < m16; j += 4) { + for (i = 0; i < k8; i += 8) { + kcell = i >> 1; // 0, 1, 2, 3 + mcell = j >> 2; + short *dest = &ap[32 * ((mcell >> 2) * krows + kcell) + + 8 * (mcell & 3)]; + + vec_t V0, V1, V2, V3; + vec_t D01A, D01B, D23A, D23B; + vec_t D0, D1, D2, D3; + vec_t swizA + = {0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23}; + vec_t swizB = {8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, + 30, 31}; + vec_t swizL + = {0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 23}; + vec_t swizR = {8, 9, 10, 11, 12, 13, 14, 15, 24, 25, 26, 27, 28, 29, + 30, 31}; + + V0 = *(vec_t *)&a[lda * (j + 0) + i]; + V1 = *(vec_t *)&a[lda * (j + 1) + i]; + V2 = *(vec_t *)&a[lda * (j + 2) + i]; + V3 = *(vec_t *)&a[lda * (j + 3) + i]; + + D01A = vec_perm(V0, V1, swizA); + D01B = vec_perm(V0, V1, swizB); + D23A = vec_perm(V2, V3, swizA); + D23B = vec_perm(V2, V3, swizB); + D0 = vec_perm(D01A, D23A, swizL); + D1 = vec_perm(D01A, D23A, swizR); + D2 = vec_perm(D01B, D23B, swizL); + D3 = vec_perm(D01B, D23B, swizR); + + *(vec_t *)&dest[0] = D0; + *(vec_t *)&dest[32] = D1; + *(vec_t *)&dest[64] = D2; + *(vec_t *)&dest[96] = D3; + } + } + + for (j = m16; j < m4; ++j) { + for (i = 0; i < k8; ++i) { + kcell = i >> 1; + mcell = j >> 2; + chunk4count = mcell >> 2; + if (mcell < (mrows & ~3)) + cell = (chunk4count * block4) + (4 * kcell) + (mcell & 3); + else { + cell = (chunk4count * block4); + if (m_cap & 8) { + switch (mcell & 3) { + case 0: + case 1: cell += 2 * kcell + (mcell & 1); break; + case 2: cell += block2 + kcell; break; + } + } else if (m_cap & 4) + cell += kcell; + } + koff = i & 1; + moff = j & 3; + ap[8 * cell + 2 * moff + koff] = a[lda * j + i]; + } + } + + // HIGH EDGE IN M DIRECTION + for (j = m4; j < m_cap; ++j) { + for (i = 0; i < k8; ++i) { + kcell = i >> 1; + mcell = j >> 2; + chunk4count = mcell >> 2; + if (mcell < (mrows & ~3)) + cell = (chunk4count * block4) + (4 * kcell) + (mcell & 3); + else { + cell = (chunk4count * block4); + if (m_cap & 8) { + switch (mcell & 3) { + case 0: + case 1: cell += 2 * kcell + (mcell & 1); break; + case 2: cell += block2 + kcell; break; + } + } else if (m_cap & 4) + cell += kcell; + } + koff = i & 1; + moff = j & 3; + if (j < m) + ap[8 * cell + 2 * moff + koff] = a[lda * j + i]; + else + ap[8 * cell + 2 * moff + koff] = 0; + } + } + + // HIGH EDGE IN K DIRECTION + for (j = 0; j < m4; ++j) { + for (i = k8; i < k_cap; ++i) { + kcell = i >> 1; + mcell = j >> 2; + chunk4count = mcell >> 2; + if (mcell < (mrows & ~3)) + cell = (chunk4count * block4) + (4 * kcell) + (mcell & 3); + else { + cell = (chunk4count * block4); + if (m_cap & 8) { + switch (mcell & 3) { + case 0: + case 1: cell += 2 * kcell + (mcell & 1); break; + case 2: cell += block2 + kcell; break; + } + } else if (m_cap & 4) + cell += kcell; + } + koff = i & 1; + moff = j & 3; + if (i < k) + ap[8 * cell + 2 * moff + koff] = a[lda * j + i]; + else + ap[8 * cell + 2 * moff + koff] = 0; + } + } + + // UPPER CORNER (HIGH M, HIGH K) + for (j = m4; j < m_cap; ++j) { + for (i = k8; i < k_cap; ++i) { + kcell = i >> 1; + mcell = j >> 2; + chunk4count = mcell >> 2; + if (mcell < (mrows & ~3)) + cell = (chunk4count * block4) + (4 * kcell) + (mcell & 3); + else { + cell = (chunk4count * block4); + if (m_cap & 8) { + switch (mcell & 3) { + case 0: + case 1: cell += 2 * kcell + (mcell & 1); break; + case 2: cell += block2 + kcell; break; + } + } else if (m_cap & 4) + cell += kcell; + } + koff = i & 1; + moff = j & 3; + if (j < m && i < k) + ap[8 * cell + 2 * moff + koff] = a[lda * j + i]; + else + ap[8 * cell + 2 * moff + koff] = 0; + } + } + return 0; +} + +int pack_T16_16bit(dim_t k, dim_t m, short *a, dim_t lda, short *ap) { + int32_t i, j; + int32_t kcell, cell, koff, moff, krows, mrows, block4, block2, mcell, + chunk4count, k4, m8, m16; + int32_t m_cap = (m + 3) & ~3; + int32_t k_cap = (k + 1) & ~1; + krows = (k + 1) >> 1; + mrows = (m + 3) >> 2; + block4 = 4 * krows; + block2 = 2 * krows; + k4 = (k >> 2) << 2; + m16 = (m >> 4) << 4; + m8 = (m >> 3) << 3; + + // MAIN BLOCK + for (i = 0; i < k4; i += 4) { + for (j = 0; j < m16; j += 16) { + short *src = &a[lda * i + j]; + short *dst = &ap[2 * j * krows + 16 * i]; + vec_t V0, V1, V2, V3, V4, V5, V6, V7; + vec_t D0, D1, D2, D3, D4, D5, D6, D7; + vec_t swizL + = {0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23}; + vec_t swizR = {8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, + 30, 31}; + + V0 = *(vec_t *)&src[0]; + V1 = *(vec_t *)&src[lda]; + V2 = *(vec_t *)&src[8]; + V3 = *(vec_t *)&src[lda + 8]; + V4 = *(vec_t *)&src[2 * lda]; + V5 = *(vec_t *)&src[3 * lda]; + V6 = *(vec_t *)&src[2 * lda + 8]; + V7 = *(vec_t *)&src[3 * lda + 8]; + D0 = vec_perm(V0, V1, swizL); + D1 = vec_perm(V0, V1, swizR); + D2 = vec_perm(V2, V3, swizL); + D3 = vec_perm(V2, V3, swizR); + D4 = vec_perm(V4, V5, swizL); + D5 = vec_perm(V4, V5, swizR); + D6 = vec_perm(V6, V7, swizL); + D7 = vec_perm(V6, V7, swizR); + + *(vec_t *)&dst[0] = D0; + *(vec_t *)&dst[8] = D1; + *(vec_t *)&dst[16] = D2; + *(vec_t *)&dst[24] = D3; + *(vec_t *)&dst[32] = D4; + *(vec_t *)&dst[40] = D5; + *(vec_t *)&dst[48] = D6; + *(vec_t *)&dst[56] = D7; + } + } + + for (i = 0; i < k4; ++i) { + for (j = m16; j < m8; ++j) { + kcell = i >> 1; + mcell = j >> 2; + chunk4count = mcell >> 2; + if (mcell < (mrows & ~3)) + cell = (chunk4count * block4) + (4 * kcell) + (mcell & 3); + else { + cell = chunk4count * block4; + if (m_cap & 8) { + switch (mcell & 3) { + case 0: + case 1: cell += 2 * kcell + (mcell & 1); break; + case 2: cell += block2 + kcell; break; + } + } else if (m_cap & 4) + cell += kcell; + } + koff = i & 1; + moff = j & 3; + ap[8 * cell + 2 * moff + koff] = a[lda * i + j]; + } + } + + // HIGH EDGE IN M DIRECTION + for (i = 0; i < k4; ++i) { + for (j = m8; j < m_cap; ++j) { + kcell = i >> 1; + mcell = j >> 2; + chunk4count = mcell >> 2; + if (mcell < (mrows & ~3)) + cell = (chunk4count * block4) + (4 * kcell) + (mcell & 3); + else { + cell = chunk4count * block4; + if (m_cap & 8) { + switch (mcell & 3) { + case 0: + case 1: cell += 2 * kcell + (mcell & 1); break; + case 2: cell += block2 + kcell; break; + } + } else if (m_cap & 4) + cell += kcell; + } + koff = i & 1; + moff = j & 3; + if (j < m) + ap[8 * cell + 2 * moff + koff] = a[lda * i + j]; + else + ap[8 * cell + 2 * moff + koff] = 0; + } + } + + // HIGH EDGE IN K DIRECTION + for (i = k4; i < k_cap; ++i) { + for (j = 0; j < m8; ++j) { + kcell = i >> 1; + mcell = j >> 2; + chunk4count = mcell >> 2; + if (mcell < (mrows & ~3)) + cell = (chunk4count * block4) + (4 * kcell) + (mcell & 3); + else { + cell = chunk4count * block4; + if (m_cap & 8) { + switch (mcell & 3) { + case 0: + case 1: cell += 2 * kcell + (mcell & 1); break; + case 2: cell += block2 + kcell; break; + } + } else if (m_cap & 4) + cell += kcell; + } + koff = i & 1; + moff = j & 3; + if (i < k) + ap[8 * cell + 2 * moff + koff] = a[lda * i + j]; + else + ap[8 * cell + 2 * moff + koff] = 0; + } + } + + // UPPER CORNER (HIGH M, HIGH K) + for (i = k4; i < k_cap; ++i) { + for (j = m8; j < m_cap; ++j) { + kcell = i >> 1; + mcell = j >> 2; + chunk4count = mcell >> 2; + if (mcell < (mrows & ~3)) + cell = (chunk4count * block4) + (4 * kcell) + (mcell & 3); + else { + cell = chunk4count * block4; + if (m_cap & 8) { + switch (mcell & 3) { + case 0: + case 1: cell += 2 * kcell + (mcell & 1); break; + case 2: cell += block2 + kcell; break; + } + } else if (m_cap & 4) + cell += kcell; + } + koff = i & 1; + moff = j & 3; + if (i < k && j < m) + ap[8 * cell + 2 * moff + koff] = a[lda * i + j]; + else + ap[8 * cell + 2 * moff + koff] = 0; + } + } + return 0; +} + +int pack_T8_16bit(dim_t k, dim_t n, short *b, dim_t ldb, short *bp) { + int32_t i, j; + int32_t kcell, cell, koff, noff, krows, k4, n8, n16; + int32_t n_cap = (n + 3) & ~3; + int32_t k_cap = (k + 1) & ~1; + krows = (k + 1) >> 1; + k4 = (k >> 2) << 2; + n8 = (n >> 3) << 3; + n16 = (n >> 4) << 4; + + // MAIN BLOCK + for (i = 0; i < k4; i += 4) { + for (j = 0; j < n16; j += 16) { + short *src = &b[ldb * i + j]; + short *dst0145 = &bp[2 * j * krows + 8 * i]; + short *dst2367 = &bp[2 * (j + 8) * krows + 8 * i]; + vec_t V0, V1, V2, V3, V4, V5, V6, V7; + vec_t D0, D1, D2, D3, D4, D5, D6, D7; + vec_t swizL + = {0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23}; + vec_t swizR = {8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, + 30, 31}; + + V0 = *(vec_t *)&src[0]; + V1 = *(vec_t *)&src[ldb]; + V2 = *(vec_t *)&src[8]; + V3 = *(vec_t *)&src[ldb + 8]; + V4 = *(vec_t *)&src[2 * ldb]; + V5 = *(vec_t *)&src[3 * ldb]; + V6 = *(vec_t *)&src[2 * ldb + 8]; + V7 = *(vec_t *)&src[3 * ldb + 8]; + D0 = vec_perm(V0, V1, swizL); + D1 = vec_perm(V0, V1, swizR); + D2 = vec_perm(V2, V3, swizL); + D3 = vec_perm(V2, V3, swizR); + D4 = vec_perm(V4, V5, swizL); + D5 = vec_perm(V4, V5, swizR); + D6 = vec_perm(V6, V7, swizL); + D7 = vec_perm(V6, V7, swizR); + + *(vec_t *)&dst0145[0] = D0; + *(vec_t *)&dst0145[8] = D1; + *(vec_t *)&dst2367[0] = D2; + *(vec_t *)&dst2367[8] = D3; + *(vec_t *)&dst0145[16] = D4; + *(vec_t *)&dst0145[24] = D5; + *(vec_t *)&dst2367[16] = D6; + *(vec_t *)&dst2367[24] = D7; + } + for (j = n16; j < n8; j += 8) { + int32_t columns_done = ((j & (~7)) >> 3) << 1; + short *dst = &bp[8 * (columns_done * krows + (i & (~1)))]; + vec_t V0, V1, V2, V3; + vec_t D0, D1, D2, D3; + vec_t swizL + = {0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23}; + vec_t swizR = {8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, + 30, 31}; + + V0 = *(vec_t *)&b[ldb * (i + 0) + j]; + V1 = *(vec_t *)&b[ldb * (i + 1) + j]; + V2 = *(vec_t *)&b[ldb * (i + 2) + j]; + V3 = *(vec_t *)&b[ldb * (i + 3) + j]; + D0 = vec_perm(V0, V1, swizL); + D1 = vec_perm(V0, V1, swizR); + D2 = vec_perm(V2, V3, swizL); + D3 = vec_perm(V2, V3, swizR); + + *(vec_t *)&dst[0] = D0; + *(vec_t *)&dst[8] = D1; + *(vec_t *)&dst[16] = D2; + *(vec_t *)&dst[24] = D3; + } + } + + // HIGH EDGE IN N DIRECTION + for (i = 0; i < k4; ++i) { + for (j = n8; j < n_cap; ++j) { + kcell = i >> 1; + // special handling if j is in a PARTIAL last "group of 8" + int32_t maingroup = (j & (~7)) < (n & (~7)); + int32_t columns_done = ((j & (~7)) >> 3) << 1; + int32_t groupwidth = (maingroup || ((n & 7) > 4)) ? 2 : 1; + int32_t j_hiflag = (j & 4) >> 2; + cell = columns_done * krows + kcell * groupwidth + j_hiflag; + koff = i & 1; + noff = j & 3; + if (j < n) + bp[8 * cell + 2 * noff + koff] = b[ldb * i + j]; + else + bp[8 * cell + 2 * noff + koff] = 0; + } + } + + // HIGH EDGE IN K DIRECTION + for (i = k4; i < k_cap; ++i) { + for (j = 0; j < n8; ++j) { + kcell = i >> 1; + // special handling if j is in a PARTIAL last "group of 8" + int32_t maingroup = (j & (~7)) < (n & (~7)); + int32_t columns_done = ((j & (~7)) >> 3) << 1; + int32_t groupwidth = (maingroup || ((n & 7) > 4)) ? 2 : 1; + int32_t j_hiflag = (j & 4) >> 2; + cell = columns_done * krows + kcell * groupwidth + j_hiflag; + koff = i & 1; + noff = j & 3; + if (i < k) + bp[8 * cell + 2 * noff + koff] = b[ldb * i + j]; + else + bp[8 * cell + 2 * noff + koff] = 0; + } + } + + // UPPER CORNER (HIGH N, HIGH K) + for (i = k4; i < k_cap; ++i) { + for (j = n8; j < n_cap; ++j) { + kcell = i >> 1; + // special handling if j is in a PARTIAL last "group of 8" + int32_t maingroup = (j & (~7)) < (n & (~7)); + int32_t columns_done = ((j & (~7)) >> 3) << 1; + int32_t groupwidth = (maingroup || ((n & 7) > 4)) ? 2 : 1; + int32_t j_hiflag = (j & 4) >> 2; + cell = columns_done * krows + kcell * groupwidth + j_hiflag; + koff = i & 1; + noff = j & 3; + if (i < k && j < n) + bp[8 * cell + 2 * noff + koff] = b[ldb * i + j]; + else + bp[8 * cell + 2 * noff + koff] = 0; + } + } + return 0; +} + +int pack_N8_16bit(dim_t k, dim_t n, short *b, dim_t ldb, short *bp) { + int32_t i, j; + int32_t kcell, cell, koff, noff, krows, k8, k16, n4, n8; + int32_t n_cap = (n + 3) & ~3; + int32_t k_cap = (k + 1) & ~1; + krows = (k + 1) >> 1; + k8 = (k >> 3) << 3; + k16 = (k >> 4) << 4; + n4 = (n >> 2) << 2; + n8 = (n >> 3) << 3; + + // MAIN BLOCK + for (j = 0; j < n8; j += 4) { + for (i = 0; i < k16; i += 16) { + kcell = i >> 1; // 0, 1, 2, 3 + int32_t columns_done = ((j & (~7)) >> 3) << 1; + int32_t j_hiflag = (j & 4) >> 2; + koff = i & 1; + noff = j & 3; + short *dst = &bp[8 * (columns_done * krows + kcell * 2 + j_hiflag)]; + + vec_t V0, V1, V2, V3, V4, V5, V6, V7; + vec_t D01A, D01B, D23A, D23B, D45A, D45B, D67A, D67B; + vec_t D0, D1, D2, D3, D4, D5, D6, D7; + vec_t swizA + = {0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23}; + vec_t swizB = {8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, + 30, 31}; + vec_t swizL + = {0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 23}; + vec_t swizR = {8, 9, 10, 11, 12, 13, 14, 15, 24, 25, 26, 27, 28, 29, + 30, 31}; + + V0 = *(vec_t *)&b[ldb * (j + 0) + i]; + V1 = *(vec_t *)&b[ldb * (j + 1) + i]; + V2 = *(vec_t *)&b[ldb * (j + 2) + i]; + V3 = *(vec_t *)&b[ldb * (j + 3) + i]; + V4 = *(vec_t *)&b[ldb * (j + 0) + i + 8]; + V5 = *(vec_t *)&b[ldb * (j + 1) + i + 8]; + V6 = *(vec_t *)&b[ldb * (j + 2) + i + 8]; + V7 = *(vec_t *)&b[ldb * (j + 3) + i + 8]; + + D01A = vec_perm(V0, V1, swizA); + D01B = vec_perm(V0, V1, swizB); + D23A = vec_perm(V2, V3, swizA); + D23B = vec_perm(V2, V3, swizB); + D45A = vec_perm(V4, V5, swizA); + D45B = vec_perm(V4, V5, swizB); + D67A = vec_perm(V6, V7, swizA); + D67B = vec_perm(V6, V7, swizB); + D0 = vec_perm(D01A, D23A, swizL); + D1 = vec_perm(D01A, D23A, swizR); + D2 = vec_perm(D01B, D23B, swizL); + D3 = vec_perm(D01B, D23B, swizR); + D4 = vec_perm(D45A, D67A, swizL); + D5 = vec_perm(D45A, D67A, swizR); + D6 = vec_perm(D45B, D67B, swizL); + D7 = vec_perm(D45B, D67B, swizR); + + *(vec_t *)&dst[0] = D0; + *(vec_t *)&dst[16] = D1; + *(vec_t *)&dst[32] = D2; + *(vec_t *)&dst[48] = D3; + *(vec_t *)&dst[64] = D4; + *(vec_t *)&dst[80] = D5; + *(vec_t *)&dst[96] = D6; + *(vec_t *)&dst[112] = D7; + } + for (i = k16; i < k8; i += 8) { + kcell = i >> 1; // 0, 1, 2, 3 + int32_t columns_done = ((j & (~7)) >> 3) << 1; + int32_t j_hiflag = (j & 4) >> 2; + koff = i & 1; + noff = j & 3; + short *dst = &bp[8 * (columns_done * krows + kcell * 2 + j_hiflag)]; + + vec_t V0, V1, V2, V3; + vec_t D01A, D01B, D23A, D23B; + vec_t D0, D1, D2, D3; + vec_t swizA + = {0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23}; + vec_t swizB = {8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, + 30, 31}; + vec_t swizL + = {0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 23}; + vec_t swizR = {8, 9, 10, 11, 12, 13, 14, 15, 24, 25, 26, 27, 28, 29, + 30, 31}; + + V0 = *(vec_t *)&b[ldb * (j + 0) + i]; + V1 = *(vec_t *)&b[ldb * (j + 1) + i]; + V2 = *(vec_t *)&b[ldb * (j + 2) + i]; + V3 = *(vec_t *)&b[ldb * (j + 3) + i]; + + D01A = vec_perm(V0, V1, swizA); + D01B = vec_perm(V0, V1, swizB); + D23A = vec_perm(V2, V3, swizA); + D23B = vec_perm(V2, V3, swizB); + D0 = vec_perm(D01A, D23A, swizL); + D1 = vec_perm(D01A, D23A, swizR); + D2 = vec_perm(D01B, D23B, swizL); + D3 = vec_perm(D01B, D23B, swizR); + + *(vec_t *)&dst[0] = D0; + *(vec_t *)&dst[16] = D1; + *(vec_t *)&dst[32] = D2; + *(vec_t *)&dst[48] = D3; + } + } + + for (j = n8; j < n4; ++j) { + for (i = 0; i < k8; ++i) { + kcell = i >> 1; + int32_t maingroup = (j & (~7)) < (n & (~7)); + int32_t columns_done = ((j & (~7)) >> 3) << 1; + int32_t groupwidth = (maingroup || ((n & 7) > 4)) ? 2 : 1; + int32_t j_hiflag = (j & 4) >> 2; + cell = columns_done * krows + kcell * groupwidth + j_hiflag; + koff = i & 1; + noff = j & 3; + bp[8 * cell + 2 * noff + koff] = b[ldb * j + i]; + } + } + + // HIGH EDGE IN N DIRECTION + for (j = n4; j < n_cap; ++j) { + for (i = 0; i < k8; ++i) { + kcell = i >> 1; + // special handling if j is in a PARTIAL last "group of 8" + int32_t maingroup = (j & (~7)) < (n & (~7)); + int32_t columns_done = ((j & (~7)) >> 3) << 1; + int32_t groupwidth = (maingroup || ((n & 7) > 4)) ? 2 : 1; + int32_t j_hiflag = (j & 4) >> 2; + cell = columns_done * krows + kcell * groupwidth + j_hiflag; + koff = i & 1; + noff = j & 3; + if (j < n) + bp[8 * cell + 2 * noff + koff] = b[ldb * j + i]; + else + bp[8 * cell + 2 * noff + koff] = 0; + } + } + + // HIGH EDGE IN K DIRECTION + for (j = 0; j < n4; ++j) { + for (i = k8; i < k_cap; ++i) { + kcell = i >> 1; + // special handling if j is in a PARTIAL last "group of 8" + int32_t maingroup = (j & (~7)) < (n & (~7)); + int32_t columns_done = ((j & (~7)) >> 3) << 1; + int32_t groupwidth = (maingroup || ((n & 7) > 4)) ? 2 : 1; + int32_t j_hiflag = (j & 4) >> 2; + cell = columns_done * krows + kcell * groupwidth + j_hiflag; + koff = i & 1; + noff = j & 3; + if (i < k) + bp[8 * cell + 2 * noff + koff] = b[ldb * j + i]; + else + bp[8 * cell + 2 * noff + koff] = 0; + } + } + + // UPPER CORNER (HIGH N, HIGH K) + for (j = n4; j < n_cap; ++j) { + for (i = k8; i < k_cap; ++i) { + kcell = i >> 1; + // special handling if j is in a PARTIAL last "group of 8" + int32_t maingroup = (j & (~7)) < (n & (~7)); + int32_t columns_done = ((j & (~7)) >> 3) << 1; + int32_t groupwidth = (maingroup || ((n & 7) > 4)) ? 2 : 1; + int32_t j_hiflag = (j & 4) >> 2; + cell = columns_done * krows + kcell * groupwidth + j_hiflag; + koff = i & 1; + noff = j & 3; + if (j < n && i < k) + bp[8 * cell + 2 * noff + koff] = b[ldb * j + i]; + else + bp[8 * cell + 2 * noff + koff] = 0; + } + } + return 0; +} + +int pack_T16_8bit(dim_t k, dim_t m, const int8_t *a, dim_t lda, int8_t *ap) { + int32_t i, j; + int32_t m_cap = (m + 3) & ~3; + int32_t k_cap = (k + 3) & ~3; + int32_t kcell, cell, koff, moff, krows, mrows, block4, block2, mcell, + chunk4count, m16, k4; + m16 = (m >> 4) << 4; + k4 = (k >> 2) << 2; + krows = (k + 3) >> 2; + mrows = (m + 3) >> 2; + block4 = 4 * krows; + block2 = 2 * krows; + + // MAIN BLOCK + for (i = 0; i < k4; i += 4) { + for (j = 0; j < m16; j += 16) { + vec_t V0, V1, V2, V3; + vec_t D01A, D01B, D23A, D23B; + vec_t D0, D1, D2, D3; + vec_t swizA + = {0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23}; + vec_t swizB = {8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, + 15, 31}; + vec_t swizL + = {0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23}; + vec_t swizR = {8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, + 30, 31}; + int8_t *dest; + + V0 = *(vec_t *)&a[lda * (i + 0) + j]; + V1 = *(vec_t *)&a[lda * (i + 1) + j]; + V2 = *(vec_t *)&a[lda * (i + 2) + j]; + V3 = *(vec_t *)&a[lda * (i + 3) + j]; + + D01A = vec_perm(V0, V1, swizA); + D01B = vec_perm(V0, V1, swizB); + D23A = vec_perm(V2, V3, swizA); + D23B = vec_perm(V2, V3, swizB); + D0 = vec_perm(D01A, D23A, swizL); + D1 = vec_perm(D01A, D23A, swizR); + D2 = vec_perm(D01B, D23B, swizL); + D3 = vec_perm(D01B, D23B, swizR); + + dest = &ap[16 * (((j >> 4) * block4) + i)]; + + *(vec_t *)&dest[0] = D0; + *(vec_t *)&dest[16] = D1; + *(vec_t *)&dest[32] = D2; + *(vec_t *)&dest[48] = D3; + } + } + + // HIGH EDGE IN M DIRECTION + for (i = 0; i < k4; ++i) { + for (j = m16; j < m_cap; ++j) { + kcell = i >> 2; + mcell = j >> 2; + chunk4count = mcell >> 2; + if (mcell < (mrows & ~3)) + cell = (chunk4count * block4) + (4 * kcell) + (mcell & 3); + else { + cell = chunk4count * block4; + if (m_cap & 8) { + switch (mcell & 3) { + case 0: + case 1: cell += 2 * kcell + (mcell & 1); break; + case 2: cell += block2 + kcell; break; + } + } else if (m_cap & 4) + cell += kcell; + } + koff = i & 3; + moff = j & 3; + if (j < m) + ap[16 * cell + 4 * moff + koff] = a[lda * i + j]; + else + ap[16 * cell + 4 * moff + koff] = 0; + } + } + + // HIGH EDGE IN K DIRECTION + for (i = k4; i < k_cap; ++i) { + for (j = 0; j < m16; ++j) { + kcell = i >> 2; + mcell = j >> 2; + chunk4count = mcell >> 2; + if (mcell < (mrows & ~3)) + cell = (chunk4count * block4) + (4 * kcell) + (mcell & 3); + else { + cell = chunk4count * block4; + if (m_cap & 8) { + switch (mcell & 3) { + case 0: + case 1: cell += 2 * kcell + (mcell & 1); break; + case 2: cell += block2 + kcell; break; + } + } else if (m_cap & 4) + cell += kcell; + } + koff = i & 3; + moff = j & 3; + if (i < k) + ap[16 * cell + 4 * moff + koff] = a[lda * i + j]; + else + ap[16 * cell + 4 * moff + koff] = 0; + } + } + + // UPPER CORNER (HIGH M, HIGH K) + for (i = k4; i < k_cap; ++i) { + for (j = m16; j < m_cap; ++j) { + kcell = i >> 2; + mcell = j >> 2; + chunk4count = mcell >> 2; + if (mcell < (mrows & ~3)) + cell = (chunk4count * block4) + (4 * kcell) + (mcell & 3); + else { + cell = chunk4count * block4; + if (m_cap & 8) { + switch (mcell & 3) { + case 0: + case 1: cell += 2 * kcell + (mcell & 1); break; + case 2: cell += block2 + kcell; break; + } + } else if (m_cap & 4) + cell += kcell; + } + koff = i & 3; + moff = j & 3; + if (i < k && j < m) + ap[16 * cell + 4 * moff + koff] = a[lda * i + j]; + else + ap[16 * cell + 4 * moff + koff] = 0; + } + } + + return 0; +} + +int pack_N8_8bit(dim_t k, dim_t n, const uint8_t *b, dim_t ldb, uint8_t *bp) { + int32_t i, j; + int32_t kcell, cell, koff, noff, krows, k8, n8; + int32_t n_cap = (n + 3) & ~3; + int32_t k_cap = (k + 3) & ~3; + krows = (k + 3) >> 2; + k8 = k >> 3; + n8 = n >> 3; + + // MAIN BLOCK + for (j = 0; j < (n8 << 3); j += 8) { + for (i = 0; i < (k8 << 3); i += 8) { + vec_t V0, V1, V2, V3; + vec_t D0, D1, D2, D3; + vec_t swizA = { + 0, 1, 2, 3, 8, 9, 10, 11, 16, 17, 18, 19, 24, 25, 26, 27}; + vec_t swizB = { + 4, 5, 6, 7, 12, 13, 14, 15, 20, 21, 22, 23, 28, 29, 30, 31}; + const uint8_t *src = &b[ldb * j + i]; + uint8_t *dest = &bp[16 * (krows * (j >> 2) + (i >> 1))]; + + *(signed long long *)&V0[0] = *(signed long long *)&src[ldb * 0]; + *(signed long long *)&V0[8] = *(signed long long *)&src[ldb * 1]; + *(signed long long *)&V1[0] = *(signed long long *)&src[ldb * 2]; + *(signed long long *)&V1[8] = *(signed long long *)&src[ldb * 3]; + *(signed long long *)&V2[0] = *(signed long long *)&src[ldb * 4]; + *(signed long long *)&V2[8] = *(signed long long *)&src[ldb * 5]; + *(signed long long *)&V3[0] = *(signed long long *)&src[ldb * 6]; + *(signed long long *)&V3[8] = *(signed long long *)&src[ldb * 7]; + + D0 = vec_perm(V0, V1, swizA); + D1 = vec_perm(V2, V3, swizA); + D2 = vec_perm(V0, V1, swizB); + D3 = vec_perm(V2, V3, swizB); + + *(vec_t *)&dest[0] = D0; + *(vec_t *)&dest[16] = D1; + *(vec_t *)&dest[32] = D2; + *(vec_t *)&dest[48] = D3; + } + } + + // HIGH EDGE IN N DIRECTION + for (j = (n8 << 3); j < n_cap; ++j) { + for (i = 0; i < (k8 << 3); ++i) { + kcell = i >> 2; + // special handling if j is in a PARTIAL last "group of 8" + int32_t maingroup = (j & (~7)) < (n & (~7)); + int32_t columns_done = ((j & (~7)) >> 3) << 1; + int32_t groupwidth = (maingroup || ((n & 7) > 4)) ? 2 : 1; + int32_t j_hiflag = (j & 4) >> 2; + cell = columns_done * krows + kcell * groupwidth + j_hiflag; + koff = i & 3; + noff = j & 3; + if (j < n) + bp[16 * cell + 4 * noff + koff] = b[ldb * j + i]; + else + bp[16 * cell + 4 * noff + koff] = 0; + } + } + + // HIGH EDGE IN K DIRECTION + for (j = 0; j < (n8 << 3); ++j) { + for (i = (k8 << 3); i < k_cap; ++i) { + kcell = i >> 2; + // special handling if j is in a PARTIAL last "group of 8" + int32_t maingroup = (j & (~7)) < (n & (~7)); + int32_t columns_done = ((j & (~7)) >> 3) << 1; + int32_t groupwidth = (maingroup || ((n & 7) > 4)) ? 2 : 1; + int32_t j_hiflag = (j & 4) >> 2; + cell = columns_done * krows + kcell * groupwidth + j_hiflag; + koff = i & 3; + noff = j & 3; + if (i < k) + bp[16 * cell + 4 * noff + koff] = b[ldb * j + i]; + else + bp[16 * cell + 4 * noff + koff] = 0; + } + } + + // UPPER CORNER (HIGH N, HIGH K) + for (j = (n8 << 3); j < n_cap; ++j) { + for (i = (k8 << 3); i < k_cap; ++i) { + kcell = i >> 2; + // special handling if j is in a PARTIAL last "group of 8" + int32_t maingroup = (j & (~7)) < (n & (~7)); + int32_t columns_done = ((j & (~7)) >> 3) << 1; + int32_t groupwidth = (maingroup || ((n & 7) > 4)) ? 2 : 1; + int32_t j_hiflag = (j & 4) >> 2; + cell = columns_done * krows + kcell * groupwidth + j_hiflag; + koff = i & 3; + noff = j & 3; + if (j < n && i < k) + bp[16 * cell + 4 * noff + koff] = b[ldb * j + i]; + else + bp[16 * cell + 4 * noff + koff] = 0; + } + } + + return 0; +} + +int pack_N16_8bit(dim_t k, dim_t m, const int8_t *a, dim_t lda, int8_t *ap) { + int32_t i, j; + int32_t m_cap = (m + 3) & ~3; + int32_t k_cap = (k + 3) & ~3; + int32_t kcell, cell, koff, moff, krows, mrows, block4, block2, mcell, + chunk4count, m16, k4, k16; + m16 = (m >> 4) << 4; + k4 = (k >> 2) << 2; + k16 = (k >> 4) << 4; + krows = (k + 3) >> 2; + mrows = (m + 3) >> 2; + block4 = 4 * krows; + block2 = 2 * krows; + + // MAIN BLOCK + for (j = 0; j < m16; j += 16) { + for (i = 0; i < k16; i += 16) { + vec_t V0, V1, V2, V3; + vec_t D01A, D01B, D23A, D23B; + vec_t D0, D1, D2, D3; + vec_t swizA + = {0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 23}; + vec_t swizB = {8, 9, 10, 11, 12, 13, 14, 15, 24, 25, 26, 27, 28, 29, + 30, 31}; + vec_t swizL = { + 0, 1, 2, 3, 8, 9, 10, 11, 16, 17, 18, 19, 24, 25, 26, 27}; + vec_t swizR = { + 4, 5, 6, 7, 12, 13, 14, 15, 20, 21, 22, 23, 28, 29, 30, 31}; + + const int8_t *src = &a[lda * j + i]; + int8_t *dest = &ap[j * (krows << 2) + (i << 4)]; + + V0 = *(vec_t *)&src[0 * lda]; + V1 = *(vec_t *)&src[1 * lda]; + V2 = *(vec_t *)&src[2 * lda]; + V3 = *(vec_t *)&src[3 * lda]; + D01A = vec_perm(V0, V1, swizA); + D01B = vec_perm(V0, V1, swizB); + D23A = vec_perm(V2, V3, swizA); + D23B = vec_perm(V2, V3, swizB); + D0 = vec_perm(D01A, D23A, swizL); + D1 = vec_perm(D01A, D23A, swizR); + D2 = vec_perm(D01B, D23B, swizL); + D3 = vec_perm(D01B, D23B, swizR); + *(vec_t *)&dest[0] = D0; + *(vec_t *)&dest[64] = D1; + *(vec_t *)&dest[128] = D2; + *(vec_t *)&dest[192] = D3; + + V0 = *(vec_t *)&src[4 * lda]; + V1 = *(vec_t *)&src[5 * lda]; + V2 = *(vec_t *)&src[6 * lda]; + V3 = *(vec_t *)&src[7 * lda]; + D01A = vec_perm(V0, V1, swizA); + D01B = vec_perm(V0, V1, swizB); + D23A = vec_perm(V2, V3, swizA); + D23B = vec_perm(V2, V3, swizB); + D0 = vec_perm(D01A, D23A, swizL); + D1 = vec_perm(D01A, D23A, swizR); + D2 = vec_perm(D01B, D23B, swizL); + D3 = vec_perm(D01B, D23B, swizR); + *(vec_t *)&dest[16] = D0; + *(vec_t *)&dest[80] = D1; + *(vec_t *)&dest[144] = D2; + *(vec_t *)&dest[208] = D3; + + V0 = *(vec_t *)&src[8 * lda]; + V1 = *(vec_t *)&src[9 * lda]; + V2 = *(vec_t *)&src[10 * lda]; + V3 = *(vec_t *)&src[11 * lda]; + D01A = vec_perm(V0, V1, swizA); + D01B = vec_perm(V0, V1, swizB); + D23A = vec_perm(V2, V3, swizA); + D23B = vec_perm(V2, V3, swizB); + D0 = vec_perm(D01A, D23A, swizL); + D1 = vec_perm(D01A, D23A, swizR); + D2 = vec_perm(D01B, D23B, swizL); + D3 = vec_perm(D01B, D23B, swizR); + *(vec_t *)&dest[32] = D0; + *(vec_t *)&dest[96] = D1; + *(vec_t *)&dest[160] = D2; + *(vec_t *)&dest[224] = D3; + + V0 = *(vec_t *)&src[12 * lda]; + V1 = *(vec_t *)&src[13 * lda]; + V2 = *(vec_t *)&src[14 * lda]; + V3 = *(vec_t *)&src[15 * lda]; + D01A = vec_perm(V0, V1, swizA); + D01B = vec_perm(V0, V1, swizB); + D23A = vec_perm(V2, V3, swizA); + D23B = vec_perm(V2, V3, swizB); + D0 = vec_perm(D01A, D23A, swizL); + D1 = vec_perm(D01A, D23A, swizR); + D2 = vec_perm(D01B, D23B, swizL); + D3 = vec_perm(D01B, D23B, swizR); + *(vec_t *)&dest[48] = D0; + *(vec_t *)&dest[112] = D1; + *(vec_t *)&dest[176] = D2; + *(vec_t *)&dest[240] = D3; + } + for (i = k16; i < k4; i += 4) { + vec_t D0, D1, D2, D3; + const int8_t *src = &a[lda * j + i]; + int8_t *dest = &ap[j * (krows << 2) + (i << 4)]; + + *(int *)&D0[0] = *(int *)&src[0 * lda]; + *(int *)&D0[4] = *(int *)&src[1 * lda]; + *(int *)&D0[8] = *(int *)&src[2 * lda]; + *(int *)&D0[12] = *(int *)&src[3 * lda]; + *(int *)&D1[0] = *(int *)&src[4 * lda]; + *(int *)&D1[4] = *(int *)&src[5 * lda]; + *(int *)&D1[8] = *(int *)&src[6 * lda]; + *(int *)&D1[12] = *(int *)&src[7 * lda]; + *(int *)&D2[0] = *(int *)&src[8 * lda]; + *(int *)&D2[4] = *(int *)&src[9 * lda]; + *(int *)&D2[8] = *(int *)&src[10 * lda]; + *(int *)&D2[12] = *(int *)&src[11 * lda]; + *(int *)&D3[0] = *(int *)&src[12 * lda]; + *(int *)&D3[4] = *(int *)&src[13 * lda]; + *(int *)&D3[8] = *(int *)&src[14 * lda]; + *(int *)&D3[12] = *(int *)&src[15 * lda]; + + *(vec_t *)&dest[0] = D0; + *(vec_t *)&dest[16] = D1; + *(vec_t *)&dest[32] = D2; + *(vec_t *)&dest[48] = D3; + } + } + + // HIGH EDGE IN M DIRECTION + for (j = m16; j < m_cap; ++j) { + for (i = 0; i < k4; ++i) { + kcell = i >> 2; + mcell = j >> 2; + chunk4count = mcell >> 2; + + if (mcell < (mrows & ~3)) + cell = (chunk4count * block4) + (4 * kcell) + (mcell & 3); + else { + cell = (chunk4count * block4); + if (m_cap & 8) { + switch (mcell & 3) { + case 0: + case 1: cell += 2 * kcell + (mcell & 1); break; + case 2: cell += block2 + kcell; break; + } + } else if (m_cap & 4) + cell += kcell; + } + koff = i & 3; + moff = j & 3; + if (j < m) + ap[16 * cell + 4 * moff + koff] = a[lda * j + i]; + else + ap[16 * cell + 4 * moff + koff] = 0; + } + } + + // HIGH EDGE IN K DIRECTION + for (j = 0; j < m16; ++j) { + for (i = k4; i < k_cap; ++i) { + kcell = i >> 2; + mcell = j >> 2; + chunk4count = mcell >> 2; + + if (mcell < (mrows & ~3)) + cell = (chunk4count * block4) + (4 * kcell) + (mcell & 3); + else { + cell = (chunk4count * block4); + if (m_cap & 8) { + switch (mcell & 3) { + case 0: + case 1: cell += 2 * kcell + (mcell & 1); break; + case 2: cell += block2 + kcell; break; + } + } else if (m_cap & 4) + cell += kcell; + } + koff = i & 3; + moff = j & 3; + if (i < k) + ap[16 * cell + 4 * moff + koff] = a[lda * j + i]; + else + ap[16 * cell + 4 * moff + koff] = 0; + } + } + + // UPPER CORNER (HIGH M, HIGH K) + for (j = m16; j < m_cap; ++j) { + for (i = k4; i < k_cap; ++i) { + kcell = i >> 2; + mcell = j >> 2; + chunk4count = mcell >> 2; + + if (mcell < (mrows & ~3)) + cell = (chunk4count * block4) + (4 * kcell) + (mcell & 3); + else { + cell = (chunk4count * block4); + if (m_cap & 8) { + switch (mcell & 3) { + case 0: + case 1: cell += 2 * kcell + (mcell & 1); break; + case 2: cell += block2 + kcell; break; + } + } else if (m_cap & 4) + cell += kcell; + } + koff = i & 3; + moff = j & 3; + if (j < m && i < k) + ap[16 * cell + 4 * moff + koff] = a[lda * j + i]; + else + ap[16 * cell + 4 * moff + koff] = 0; + } + } + + return 0; +} + +int pack_T8_8bit(dim_t k, dim_t n, const uint8_t *b, dim_t ldb, uint8_t *bp) { + int32_t i, j; + int32_t kcell, cell, koff, noff, krows, k8, n8; + int32_t n_cap = (n + 3) & ~3; + int32_t k_cap = (k + 3) & ~3; + krows = (k + 3) >> 2; + k8 = (k >> 3) << 3; + n8 = (n >> 3) << 3; + + // MAIN BLOCK + for (i = 0; i < k8; i += 8) { + for (j = 0; j < n8; j += 8) { + vec_t V0, V1, V2, V3; + vec_t D01A, D01B, D23A, D23B; + vec_t D0, D1, D2, D3; + vec_t swizA + = {0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23}; + vec_t swizB = {8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, + 15, 31}; + vec_t swizL + = {0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23}; + vec_t swizR = {8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, + 30, 31}; + uint8_t *dest; + + *(signed long long *)&V0[0] + = *(signed long long *)&b[ldb * (i + 0) + j]; + *(signed long long *)&V1[0] + = *(signed long long *)&b[ldb * (i + 1) + j]; + *(signed long long *)&V2[0] + = *(signed long long *)&b[ldb * (i + 2) + j]; + *(signed long long *)&V3[0] + = *(signed long long *)&b[ldb * (i + 3) + j]; + *(signed long long *)&V0[8] + = *(signed long long *)&b[ldb * (i + 4) + j]; + *(signed long long *)&V1[8] + = *(signed long long *)&b[ldb * (i + 5) + j]; + *(signed long long *)&V2[8] + = *(signed long long *)&b[ldb * (i + 6) + j]; + *(signed long long *)&V3[8] + = *(signed long long *)&b[ldb * (i + 7) + j]; + + D01A = vec_perm(V0, V1, swizA); + D01B = vec_perm(V0, V1, swizB); + D23A = vec_perm(V2, V3, swizA); + D23B = vec_perm(V2, V3, swizB); + D0 = vec_perm(D01A, D23A, swizL); + D1 = vec_perm(D01A, D23A, swizR); + D2 = vec_perm(D01B, D23B, swizL); + D3 = vec_perm(D01B, D23B, swizR); + + dest = &bp[16 * ((j >> 2) * krows + (i >> 1))]; + + *(vec_t *)&dest[0] = D0; + *(vec_t *)&dest[16] = D1; + *(vec_t *)&dest[32] = D2; + *(vec_t *)&dest[48] = D3; + } + } + + // HIGH EDGE IN N DIRECTION + for (i = 0; i < k8; ++i) { + for (j = n8; j < n_cap; ++j) { + kcell = i >> 2; + // special handling if j is in a PARTIAL last "group of 8" + int32_t maingroup = (j & (~7)) < (n & (~7)); + int32_t columns_done = ((j & (~7)) >> 3) << 1; + int32_t groupwidth = (maingroup || ((n & 7) > 4)) ? 2 : 1; + int32_t j_hiflag = (j & 4) >> 2; + cell = columns_done * krows + kcell * groupwidth + j_hiflag; + koff = i & 3; + noff = j & 3; + if (j < n) + bp[16 * cell + 4 * noff + koff] = b[ldb * i + j]; + else + bp[16 * cell + 4 * noff + koff] = 0; + } + } + + // HIGH EDGE IN K DIRECTION + for (i = k8; i < k_cap; ++i) { + for (j = 0; j < n8; ++j) { + kcell = i >> 2; + // special handling if j is in a PARTIAL last "group of 8" + int32_t maingroup = (j & (~7)) < (n & (~7)); + int32_t columns_done = ((j & (~7)) >> 3) << 1; + int32_t groupwidth = (maingroup || ((n & 7) > 4)) ? 2 : 1; + int32_t j_hiflag = (j & 4) >> 2; + cell = columns_done * krows + kcell * groupwidth + j_hiflag; + koff = i & 3; + noff = j & 3; + if (i < k) + bp[16 * cell + 4 * noff + koff] = b[ldb * i + j]; + else + bp[16 * cell + 4 * noff + koff] = 0; + } + } + + // UPPER CORNER (HIGH N, HIGH K) + for (i = k8; i < k_cap; ++i) { + for (j = n8; j < n_cap; ++j) { + kcell = i >> 2; + // special handling if j is in a PARTIAL last "group of 8" + int32_t maingroup = (j & (~7)) < (n & (~7)); + int32_t columns_done = ((j & (~7)) >> 3) << 1; + int32_t groupwidth = (maingroup || ((n & 7) > 4)) ? 2 : 1; + int32_t j_hiflag = (j & 4) >> 2; + cell = columns_done * krows + kcell * groupwidth + j_hiflag; + koff = i & 3; + noff = j & 3; + if (i < k && j < n) + bp[16 * cell + 4 * noff + koff] = b[ldb * i + j]; + else + bp[16 * cell + 4 * noff + koff] = 0; + } + } + + return 0; +} + +typedef __vector int32_t v4si_t __attribute__((aligned(4))); + +#define SWIZZLE_4x4 \ + { \ + result_i[0] = vec_perm(result[0], result[1], swizA); \ + result_i[1] = vec_perm(result[0], result[1], swizB); \ + result_i[2] = vec_perm(result[2], result[3], swizA); \ + result_i[3] = vec_perm(result[2], result[3], swizB); \ + result_t[0] = vec_perm(result_i[0], result_i[2], swizC); \ + result_t[1] = vec_perm(result_i[0], result_i[2], swizD); \ + result_t[2] = vec_perm(result_i[1], result_i[3], swizC); \ + result_t[3] = vec_perm(result_i[1], result_i[3], swizD); \ + } + +#define SAVE_ACC(ACC, J) \ + __builtin_mma_disassemble_acc((void *)result, ACC); \ + SWIZZLE_4x4 rowC = (v4si_t *)&CO[0 * ldc + J]; \ + rowC[0] = vec_cts( \ + beta * vec_ctf(rowC[0], 0) + alpha * vec_ctf(result_t[0], 0), 0); \ + rowC = (v4si_t *)&CO[1 * ldc + J]; \ + rowC[0] = vec_cts( \ + beta * vec_ctf(rowC[0], 0) + alpha * vec_ctf(result_t[1], 0), 0); \ + rowC = (v4si_t *)&CO[2 * ldc + J]; \ + rowC[0] = vec_cts( \ + beta * vec_ctf(rowC[0], 0) + alpha * vec_ctf(result_t[2], 0), 0); \ + rowC = (v4si_t *)&CO[3 * ldc + J]; \ + rowC[0] = vec_cts( \ + beta * vec_ctf(rowC[0], 0) + alpha * vec_ctf(result_t[3], 0), 0); + +#define SAVE_ACC1(ACC, J) \ + __builtin_mma_disassemble_acc((void *)result, ACC); \ + SWIZZLE_4x4 rowC = (v4si_t *)&CO[4 * ldc + J]; \ + rowC[0] = vec_cts( \ + beta * vec_ctf(rowC[0], 0) + alpha * vec_ctf(result_t[0], 0), 0); \ + rowC = (v4si_t *)&CO[5 * ldc + J]; \ + rowC[0] = vec_cts( \ + beta * vec_ctf(rowC[0], 0) + alpha * vec_ctf(result_t[1], 0), 0); \ + rowC = (v4si_t *)&CO[6 * ldc + J]; \ + rowC[0] = vec_cts( \ + beta * vec_ctf(rowC[0], 0) + alpha * vec_ctf(result_t[2], 0), 0); \ + rowC = (v4si_t *)&CO[7 * ldc + J]; \ + rowC[0] = vec_cts( \ + beta * vec_ctf(rowC[0], 0) + alpha * vec_ctf(result_t[3], 0), 0); + +#define SAVE_ACC_COND(ACC, J) \ + __builtin_mma_disassemble_acc((void *)result, ACC); \ + SWIZZLE_4x4 rowC = (v4si_t *)&CO[0 * ldc + J]; \ + rowC[0] = vec_cts( \ + beta * vec_ctf(rowC[0], 0) + alpha * vec_ctf(result_t[0], 0), 0); \ + rowC = (v4si_t *)&CO[1 * ldc + J]; \ + if ((n_cap - n) < 3) \ + rowC[0] = vec_cts( \ + beta * vec_ctf(rowC[0], 0) + alpha * vec_ctf(result_t[1], 0), \ + 0); \ + rowC = (v4si_t *)&CO[2 * ldc + J]; \ + if ((n_cap - n) < 2) \ + rowC[0] = vec_cts( \ + beta * vec_ctf(rowC[0], 0) + alpha * vec_ctf(result_t[2], 0), \ + 0); \ + rowC = (v4si_t *)&CO[3 * ldc + J]; \ + if ((n_cap - n) < 1) \ + rowC[0] = vec_cts( \ + beta * vec_ctf(rowC[0], 0) + alpha * vec_ctf(result_t[3], 0), \ + 0); + +#define SAVE_ACC1_COND(ACC, J) \ + __builtin_mma_disassemble_acc((void *)result, ACC); \ + SWIZZLE_4x4 rowC = (v4si_t *)&CO[4 * ldc + J]; \ + rowC[0] = vec_cts( \ + beta * vec_ctf(rowC[0], 0) + alpha * vec_ctf(result_t[0], 0), 0); \ + rowC = (v4si_t *)&CO[5 * ldc + J]; \ + if ((n_cap - n) < 3) \ + rowC[0] = vec_cts( \ + beta * vec_ctf(rowC[0], 0) + alpha * vec_ctf(result_t[1], 0), \ + 0); \ + rowC = (v4si_t *)&CO[6 * ldc + J]; \ + if ((n_cap - n) < 2) \ + rowC[0] = vec_cts( \ + beta * vec_ctf(rowC[0], 0) + alpha * vec_ctf(result_t[2], 0), \ + 0); \ + rowC = (v4si_t *)&CO[7 * ldc + J]; \ + if ((n_cap - n) < 1) \ + rowC[0] = vec_cts( \ + beta * vec_ctf(rowC[0], 0) + alpha * vec_ctf(result_t[3], 0), \ + 0); + +#define SAVE_ACC_ABSC(ACC, J) \ + __builtin_mma_disassemble_acc((void *)result, ACC); \ + SWIZZLE_4x4 rowC = (v4si_t *)&CO[0 * ldc + J]; \ + rowC[0] = result_t[0]; \ + rowC = (v4si_t *)&CO[1 * ldc + J]; \ + rowC[0] = result_t[1]; \ + rowC = (v4si_t *)&CO[2 * ldc + J]; \ + rowC[0] = result_t[2]; \ + rowC = (v4si_t *)&CO[3 * ldc + J]; \ + rowC[0] = result_t[3]; + +#define SAVE_ACC1_ABSC(ACC, J) \ + __builtin_mma_disassemble_acc((void *)result, ACC); \ + SWIZZLE_4x4 rowC = (v4si_t *)&CO[4 * ldc + J]; \ + rowC[0] = result_t[0]; \ + rowC = (v4si_t *)&CO[5 * ldc + J]; \ + rowC[0] = result_t[1]; \ + rowC = (v4si_t *)&CO[6 * ldc + J]; \ + rowC[0] = result_t[2]; \ + rowC = (v4si_t *)&CO[7 * ldc + J]; \ + rowC[0] = result_t[3]; + +#define SAVE_ACC_COND_ABSC(ACC, J) \ + __builtin_mma_disassemble_acc((void *)result, ACC); \ + SWIZZLE_4x4 rowC = (v4si_t *)&CO[0 * ldc + J]; \ + rowC[0] = result_t[0]; \ + rowC = (v4si_t *)&CO[1 * ldc + J]; \ + if ((n_cap - n) < 3) rowC[0] = result_t[1]; \ + rowC = (v4si_t *)&CO[2 * ldc + J]; \ + if ((n_cap - n) < 2) rowC[0] = result_t[2]; \ + rowC = (v4si_t *)&CO[3 * ldc + J]; \ + if ((n_cap - n) < 1) rowC[0] = result_t[3]; + +#define SAVE_ACC1_COND_ABSC(ACC, J) \ + __builtin_mma_disassemble_acc((void *)result, ACC); \ + SWIZZLE_4x4 rowC = (v4si_t *)&CO[4 * ldc + J]; \ + rowC[0] = result_t[0]; \ + rowC = (v4si_t *)&CO[5 * ldc + J]; \ + if ((n_cap - n) < 3) rowC[0] = result_t[1]; \ + rowC = (v4si_t *)&CO[6 * ldc + J]; \ + if ((n_cap - n) < 2) rowC[0] = result_t[2]; \ + rowC = (v4si_t *)&CO[7 * ldc + J]; \ + if ((n_cap - n) < 1) rowC[0] = result_t[3]; + +#define SET_ACC_ZERO4() \ + __builtin_mma_xxsetaccz(&acc0); \ + __builtin_mma_xxsetaccz(&acc1); \ + __builtin_mma_xxsetaccz(&acc2); \ + __builtin_mma_xxsetaccz(&acc3); + +#define SET_ACC_ZERO8() \ + __builtin_mma_xxsetaccz(&acc0); \ + __builtin_mma_xxsetaccz(&acc1); \ + __builtin_mma_xxsetaccz(&acc2); \ + __builtin_mma_xxsetaccz(&acc3); \ + __builtin_mma_xxsetaccz(&acc4); \ + __builtin_mma_xxsetaccz(&acc5); \ + __builtin_mma_xxsetaccz(&acc6); \ + __builtin_mma_xxsetaccz(&acc7); + +#define PREFETCH1(x, y) \ + asm volatile("dcbt %0, %1" : : "r"(x), "b"(y) : "memory"); + +#define MMA __builtin_mma_xvi16ger2pp + +void gemm_kernel_16bit(dim_t m, dim_t n, dim_t k, float alpha, short *A, + short *B, int32_t *C, float beta, dim_t ldc) { + int32_t i; + int32_t m_cap = (m + 3) & ~3; + int32_t n_cap = (n + 3) & ~3; + int32_t k_cap = (k + 1) & ~1; + int32_t m_skip; + int32_t n_skip = (n & 8) != (n_cap & 8); + int32_t fastpath; + v4si_t result[4], result_i[4], result_t[4]; + vec_t swizA = {0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23}; + vec_t swizB + = {8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31}; + vec_t swizC = {0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 23}; + vec_t swizD + = {8, 9, 10, 11, 12, 13, 14, 15, 24, 25, 26, 27, 28, 29, 30, 31}; + fastpath = ((alpha == 1.0) && (beta == 0.0)); + + /* Loop for multiples of 8 */ + i = n_cap >> 3; + while (i) { + int32_t j; + int32_t *CO; + short *AO; + CO = C; + C += ldc << 3; + AO = A; + PREFETCH1(A, 128); + PREFETCH1(A, 256); + /* Loop for m >= 16. */ + j = m_cap >> 4; + m_skip = (m >> 4) != (m_cap >> 4); + while (j) { + short *BO = B; + v4si_t *rowC; + __vector_quad acc0, acc1, acc2, acc3, acc4, acc5, acc6, acc7; + SET_ACC_ZERO8(); + int32_t l; + vec_t *rowA = (vec_t *)AO; + vec_t *rowB = (vec_t *)BO; + for (l = 0; l < k_cap / 2; l++) { + MMA(&acc0, rowA[0], rowB[0]); + MMA(&acc1, rowA[0], rowB[1]); + MMA(&acc2, rowA[1], rowB[0]); + MMA(&acc3, rowA[1], rowB[1]); + MMA(&acc4, rowA[2], rowB[0]); + MMA(&acc5, rowA[2], rowB[1]); + MMA(&acc6, rowA[3], rowB[0]); + MMA(&acc7, rowA[3], rowB[1]); + rowA += 4; + rowB += 2; + } + + if (fastpath) { + SAVE_ACC_ABSC(&acc0, 0); + if ((i == 1) && n_skip) { + SAVE_ACC1_COND_ABSC(&acc1, 0); + } else { + SAVE_ACC1_ABSC(&acc1, 0); + } + CO += 4; + SAVE_ACC_ABSC(&acc2, 0); + if ((i == 1) && n_skip) { + SAVE_ACC1_COND_ABSC(&acc3, 0); + } else { + SAVE_ACC1_ABSC(&acc3, 0); + } + CO += 4; + SAVE_ACC_ABSC(&acc4, 0); + if ((i == 1) && n_skip) { + SAVE_ACC1_COND_ABSC(&acc5, 0); + } else { + SAVE_ACC1_ABSC(&acc5, 0); + } + CO += 4; + if (((j == 1) && m_skip) || ((i == 1) && n_skip)) { + if ((j == 1) && m_skip) { + int32_t count = 4 - (m_cap - m); + int32_t ii; + __builtin_mma_disassemble_acc((void *)result, &acc6); + SWIZZLE_4x4 for (ii = 0; ii < count; ++ii) + CO[0 * ldc + ii] + = result_t[0][ii]; + for (ii = 0; ii < count; ++ii) + CO[1 * ldc + ii] = result_t[1][ii]; + for (ii = 0; ii < count; ++ii) + CO[2 * ldc + ii] = result_t[2][ii]; + for (ii = 0; ii < count; ++ii) + CO[3 * ldc + ii] = result_t[3][ii]; + __builtin_mma_disassemble_acc((void *)result, &acc7); + SWIZZLE_4x4 for (ii = 0; ii < count; ++ii) + CO[4 * ldc + ii] + = result_t[0][ii]; + if ((i > 1) || (!(n_skip)) || (n_cap & 4) + || (n_cap - n) < 3) + for (ii = 0; ii < count; ++ii) + CO[5 * ldc + ii] = result_t[1][ii]; + if ((i > 1) || (!(n_skip)) || (n_cap & 4) + || (n_cap - n) < 2) + for (ii = 0; ii < count; ++ii) + CO[6 * ldc + ii] = result_t[2][ii]; + if ((i > 1) || (!(n_skip)) || (n_cap & 4) + || (n_cap - n) < 1) + for (ii = 0; ii < count; ++ii) + CO[7 * ldc + ii] = result_t[3][ii]; + } else { + SAVE_ACC_ABSC(&acc6, 0); + SAVE_ACC1_COND_ABSC(&acc7, 0); + } + } else { + SAVE_ACC_ABSC(&acc6, 0); + SAVE_ACC1_ABSC(&acc7, 0); + } + } else { + SAVE_ACC(&acc0, 0); + if ((i == 1) && n_skip) { + SAVE_ACC1_COND(&acc1, 0); + } else { + SAVE_ACC1(&acc1, 0); + } + CO += 4; + SAVE_ACC(&acc2, 0); + if ((i == 1) && n_skip) { + SAVE_ACC1_COND(&acc3, 0); + } else { + SAVE_ACC1(&acc3, 0); + } + CO += 4; + SAVE_ACC(&acc4, 0); + if ((i == 1) && n_skip) { + SAVE_ACC1_COND(&acc5, 0); + } else { + SAVE_ACC1(&acc5, 0); + } + CO += 4; + if (((j == 1) && m_skip) || ((i == 1) && n_skip)) { + if ((j == 1) && m_skip) { + int32_t count = 4 - (m_cap - m); + int32_t ii; + __builtin_mma_disassemble_acc((void *)result, &acc6); + SWIZZLE_4x4 for (ii = 0; ii < count; ++ii) + CO[0 * ldc + ii] + = beta * CO[0 * ldc + ii] + + alpha * result_t[0][ii]; + for (ii = 0; ii < count; ++ii) + CO[1 * ldc + ii] = beta * CO[1 * ldc + ii] + + alpha * result_t[1][ii]; + for (ii = 0; ii < count; ++ii) + CO[2 * ldc + ii] = beta * CO[2 * ldc + ii] + + alpha * result_t[2][ii]; + for (ii = 0; ii < count; ++ii) + CO[3 * ldc + ii] = beta * CO[3 * ldc + ii] + + alpha * result_t[3][ii]; + __builtin_mma_disassemble_acc((void *)result, &acc7); + SWIZZLE_4x4 for (ii = 0; ii < count; ++ii) + CO[4 * ldc + ii] + = beta * CO[4 * ldc + ii] + + alpha * result_t[0][ii]; + if ((i > 1) || (!(n_skip)) || (n_cap & 4) + || (n_cap - n) < 3) + for (ii = 0; ii < count; ++ii) + CO[5 * ldc + ii] = beta * CO[5 * ldc + ii] + + alpha * result_t[1][ii]; + if ((i > 1) || (!(n_skip)) || (n_cap & 4) + || (n_cap - n) < 2) + for (ii = 0; ii < count; ++ii) + CO[6 * ldc + ii] = beta * CO[6 * ldc + ii] + + alpha * result_t[2][ii]; + if ((i > 1) || (!(n_skip)) || (n_cap & 4) + || (n_cap - n) < 1) + for (ii = 0; ii < count; ++ii) + CO[7 * ldc + ii] = beta * CO[7 * ldc + ii] + + alpha * result_t[3][ii]; + } else { + SAVE_ACC(&acc6, 0); + SAVE_ACC1_COND(&acc7, 0); + } + } else { + SAVE_ACC(&acc6, 0); + SAVE_ACC1(&acc7, 0); + } + } + CO += 4; + AO += (k_cap << 4); + BO += (k_cap << 3); + --j; + } + + if (m_skip) goto endloop8; + + m_skip = (m & 8) != (m_cap & 8); + + if (m_cap & 8) { + short *BO = B; + v4si_t *rowC; + __vector_quad acc0, acc1, acc2, acc3; + SET_ACC_ZERO4(); + vec_t *rowA = (vec_t *)AO; + vec_t *rowB = (vec_t *)BO; + int32_t l; + for (l = 0; l < k_cap / 2; l++) { + MMA(&acc0, rowA[0], rowB[0]); + MMA(&acc1, rowA[0], rowB[1]); + MMA(&acc2, rowA[1], rowB[0]); + MMA(&acc3, rowA[1], rowB[1]); + rowA += 2; + rowB += 2; + } + + if (fastpath) { + SAVE_ACC_ABSC(&acc0, 0); + if ((i == 1) && n_skip) { + SAVE_ACC1_COND_ABSC(&acc1, 0); + } else { + SAVE_ACC1_ABSC(&acc1, 0); + } + CO += 4; + if (m_skip || ((i == 1) & n_skip)) { + if (m_skip) { + int32_t count = 4 - (m_cap - m); + int32_t ii; + __builtin_mma_disassemble_acc((void *)result, &acc2); + SWIZZLE_4x4 for (ii = 0; ii < count; ++ii) + CO[0 * ldc + ii] + = result_t[0][ii]; + for (ii = 0; ii < count; ++ii) + CO[1 * ldc + ii] = result_t[1][ii]; + for (ii = 0; ii < count; ++ii) + CO[2 * ldc + ii] = result_t[2][ii]; + for (ii = 0; ii < count; ++ii) + CO[3 * ldc + ii] = result_t[3][ii]; + __builtin_mma_disassemble_acc((void *)result, &acc3); + SWIZZLE_4x4 for (ii = 0; ii < count; ++ii) + CO[4 * ldc + ii] + = result_t[0][ii]; + if ((i > 1) || (!n_skip) || (n_cap & 4) + || (n_cap - n) < 3) + for (ii = 0; ii < count; ++ii) + CO[5 * ldc + ii] = result_t[1][ii]; + if ((i > 1) || (!n_skip) || (n_cap & 4) + || (n_cap - n) < 2) + for (ii = 0; ii < count; ++ii) + CO[6 * ldc + ii] = result_t[2][ii]; + if ((i > 1) || (!n_skip) || (n_cap & 4) + || (n_cap - n) < 1) + for (ii = 0; ii < count; ++ii) + CO[7 * ldc + ii] = result_t[3][ii]; + } else { + SAVE_ACC_ABSC(&acc2, 0); + SAVE_ACC1_COND_ABSC(&acc3, 0); + } + } else { + SAVE_ACC_ABSC(&acc2, 0); + SAVE_ACC1_ABSC(&acc3, 0); + } + } else { + SAVE_ACC(&acc0, 0); + if ((i == 1) && n_skip) { + SAVE_ACC1_COND(&acc1, 0); + } else { + SAVE_ACC1(&acc1, 0); + } + CO += 4; + if (m_skip || ((i == 1) & n_skip)) { + if (m_skip) { + int32_t count = 4 - (m_cap - m); + int32_t ii; + __builtin_mma_disassemble_acc((void *)result, &acc2); + SWIZZLE_4x4 for (ii = 0; ii < count; ++ii) + CO[0 * ldc + ii] + = beta * CO[0 * ldc + ii] + + alpha * result_t[0][ii]; + for (ii = 0; ii < count; ++ii) + CO[1 * ldc + ii] = beta * CO[1 * ldc + ii] + + alpha * result_t[1][ii]; + for (ii = 0; ii < count; ++ii) + CO[2 * ldc + ii] = beta * CO[2 * ldc + ii] + + alpha * result_t[2][ii]; + for (ii = 0; ii < count; ++ii) + CO[3 * ldc + ii] = beta * CO[3 * ldc + ii] + + alpha * result_t[3][ii]; + __builtin_mma_disassemble_acc((void *)result, &acc3); + SWIZZLE_4x4 for (ii = 0; ii < count; ++ii) + CO[4 * ldc + ii] + = beta * CO[4 * ldc + ii] + + alpha * result_t[0][ii]; + if ((i > 1) || (!n_skip) || (n_cap & 4) + || (n_cap - n) < 3) + for (ii = 0; ii < count; ++ii) + CO[5 * ldc + ii] = beta * CO[5 * ldc + ii] + + alpha * result_t[1][ii]; + if ((i > 1) || (!n_skip) || (n_cap & 4) + || (n_cap - n) < 2) + for (ii = 0; ii < count; ++ii) + CO[6 * ldc + ii] = beta * CO[6 * ldc + ii] + + alpha * result_t[2][ii]; + if ((i > 1) || (!n_skip) || (n_cap & 4) + || (n_cap - n) < 1) + for (ii = 0; ii < count; ++ii) + CO[7 * ldc + ii] = beta * CO[7 * ldc + ii] + + alpha * result_t[3][ii]; + } else { + SAVE_ACC(&acc2, 0); + SAVE_ACC1_COND(&acc3, 0); + } + } else { + SAVE_ACC(&acc2, 0); + SAVE_ACC1(&acc3, 0); + } + } + CO += 4; + AO += (k_cap << 3); + BO += (k_cap << 3); + } + + if (m_skip) goto endloop8; + + m_skip = (m & 4) != (m_cap & 4); + + if (m_cap & 4) { + short *BO = B; + v4si_t *rowC; + __vector_quad acc0, acc1; + __builtin_mma_xxsetaccz(&acc0); + __builtin_mma_xxsetaccz(&acc1); + vec_t *rowA = (vec_t *)AO; + vec_t *rowB = (vec_t *)BO; + int32_t l = 0; + for (l = 0; l < k_cap / 2; l++) { + MMA(&acc0, rowA[0], rowB[0]); + MMA(&acc1, rowA[0], rowB[1]); + rowA += 1; + rowB += 2; + } + + if (fastpath) { + if (m_skip || ((i == 1) & n_skip)) { + if (m_skip) { + int32_t count = 4 - (m_cap - m); + int32_t ii; + __builtin_mma_disassemble_acc((void *)result, &acc0); + SWIZZLE_4x4 for (ii = 0; ii < count; ++ii) + CO[0 * ldc + ii] + = result_t[0][ii]; + for (ii = 0; ii < count; ++ii) + CO[1 * ldc + ii] = result_t[1][ii]; + for (ii = 0; ii < count; ++ii) + CO[2 * ldc + ii] = result_t[2][ii]; + for (ii = 0; ii < count; ++ii) + CO[3 * ldc + ii] = result_t[3][ii]; + __builtin_mma_disassemble_acc((void *)result, &acc1); + SWIZZLE_4x4 for (ii = 0; ii < count; ++ii) + CO[4 * ldc + ii] + = result_t[0][ii]; + if ((i == 1) & n_skip) { + if ((n_cap & 4) || (n_cap - n) < 3) + for (ii = 0; ii < count; ++ii) + CO[5 * ldc + ii] = result_t[1][ii]; + if ((n_cap & 4) || (n_cap - n) < 2) + for (ii = 0; ii < count; ++ii) + CO[6 * ldc + ii] = result_t[2][ii]; + if ((n_cap & 4) || (n_cap - n) < 1) + for (ii = 0; ii < count; ++ii) + CO[7 * ldc + ii] = result_t[3][ii]; + } else { + for (ii = 0; ii < count; ++ii) + CO[5 * ldc + ii] = result_t[1][ii]; + for (ii = 0; ii < count; ++ii) + CO[6 * ldc + ii] = result_t[2][ii]; + for (ii = 0; ii < count; ++ii) + CO[7 * ldc + ii] = result_t[3][ii]; + } + } else { + SAVE_ACC_ABSC(&acc0, 0); + SAVE_ACC1_COND_ABSC(&acc1, 0); + } + } else { + SAVE_ACC_ABSC(&acc0, 0); + SAVE_ACC1_ABSC(&acc1, 0); + } + } else { + if (m_skip || ((i == 1) & n_skip)) { + if (m_skip) { + int32_t count = 4 - (m_cap - m); + int32_t ii; + __builtin_mma_disassemble_acc((void *)result, &acc0); + SWIZZLE_4x4 for (ii = 0; ii < count; ++ii) + CO[0 * ldc + ii] + = beta * CO[0 * ldc + ii] + + alpha * result_t[0][ii]; + for (ii = 0; ii < count; ++ii) + CO[1 * ldc + ii] = beta * CO[1 * ldc + ii] + + alpha * result_t[1][ii]; + for (ii = 0; ii < count; ++ii) + CO[2 * ldc + ii] = beta * CO[2 * ldc + ii] + + alpha * result_t[2][ii]; + for (ii = 0; ii < count; ++ii) + CO[3 * ldc + ii] = beta * CO[3 * ldc + ii] + + alpha * result_t[3][ii]; + __builtin_mma_disassemble_acc((void *)result, &acc1); + SWIZZLE_4x4 for (ii = 0; ii < count; ++ii) + CO[4 * ldc + ii] + = beta * CO[4 * ldc + ii] + + alpha * result_t[0][ii]; + if ((i == 1) & n_skip) { + if ((n_cap & 4) || (n_cap - n) < 3) + for (ii = 0; ii < count; ++ii) + CO[5 * ldc + ii] = beta * CO[5 * ldc + ii] + + alpha * result_t[1][ii]; + if ((n_cap & 4) || (n_cap - n) < 2) + for (ii = 0; ii < count; ++ii) + CO[6 * ldc + ii] = beta * CO[6 * ldc + ii] + + alpha * result_t[2][ii]; + if ((n_cap & 4) || (n_cap - n) < 1) + for (ii = 0; ii < count; ++ii) + CO[7 * ldc + ii] = beta * CO[7 * ldc + ii] + + alpha * result_t[3][ii]; + } else { + for (ii = 0; ii < count; ++ii) + CO[5 * ldc + ii] = beta * CO[5 * ldc + ii] + + alpha * result_t[1][ii]; + for (ii = 0; ii < count; ++ii) + CO[6 * ldc + ii] = beta * CO[6 * ldc + ii] + + alpha * result_t[2][ii]; + for (ii = 0; ii < count; ++ii) + CO[7 * ldc + ii] = beta * CO[7 * ldc + ii] + + alpha * result_t[3][ii]; + } + } else { + SAVE_ACC(&acc0, 0); + SAVE_ACC1_COND(&acc1, 0); + } + } else { + SAVE_ACC(&acc0, 0); + SAVE_ACC1(&acc1, 0); + } + } + CO += 4; + AO += (k_cap << 2); + BO += (k_cap << 3); + } + + endloop8: + B += k_cap << 3; + i -= 1; + } + + if (n_cap & 4) { + int32_t j; + int32_t *CO; + short *AO; + CO = C; + C += ldc << 2; + AO = A; + int32_t n_skip = (n != n_cap); + /* Loop for m >= 32. */ + m_skip = (m >> 5) != (m_cap >> 5); + for (j = 0; j < (m_cap >> 5); j++) { + short *BO = B; + short *A1 = AO + (16 * k_cap); + v4si_t *rowC; + __vector_quad acc0, acc1, acc2, acc3, acc4, acc5, acc6, acc7; + SET_ACC_ZERO8(); + vec_t *rowA = (vec_t *)AO; + vec_t *rowA1 = (vec_t *)A1; + vec_t *rowB = (vec_t *)BO; + int32_t l; + for (l = 0; l < k_cap / 2; l++) { + MMA(&acc0, rowA[0], rowB[0]); + MMA(&acc1, rowA[1], rowB[0]); + MMA(&acc2, rowA[2], rowB[0]); + MMA(&acc3, rowA[3], rowB[0]); + MMA(&acc4, rowA1[0], rowB[0]); + MMA(&acc5, rowA1[1], rowB[0]); + MMA(&acc6, rowA1[2], rowB[0]); + MMA(&acc7, rowA1[3], rowB[0]); + rowA += 4; + rowA1 += 4; + rowB += 1; + } + + if (fastpath) { + if (m_skip || n_skip) { + SAVE_ACC_COND_ABSC(&acc0, 0); + SAVE_ACC_COND_ABSC(&acc1, 4); + SAVE_ACC_COND_ABSC(&acc2, 8); + SAVE_ACC_COND_ABSC(&acc3, 12); + SAVE_ACC_COND_ABSC(&acc4, 16); + SAVE_ACC_COND_ABSC(&acc5, 20); + SAVE_ACC_COND_ABSC(&acc6, 24); + if ((j == (m_cap >> 5) - 1) && m_skip) { + int32_t ii; + int32_t count = 4 - (m_cap - m); + __builtin_mma_disassemble_acc((void *)result, &acc7); + SWIZZLE_4x4 for (ii = 0; ii < count; ++ii) + CO[0 * ldc + 28 + ii] + = result_t[0][ii]; + if ((n_cap - n) < 3) + for (ii = 0; ii < count; ++ii) + CO[1 * ldc + 28 + ii] = result_t[1][ii]; + if ((n_cap - n) < 2) + for (ii = 0; ii < count; ++ii) + CO[2 * ldc + 28 + ii] = result_t[2][ii]; + if ((n_cap - n) < 1) + for (ii = 0; ii < count; ++ii) + CO[3 * ldc + 28 + ii] = result_t[3][ii]; + } else { + SAVE_ACC_COND_ABSC(&acc7, 28); + } + CO += 32; + } else { + SAVE_ACC_ABSC(&acc0, 0); + SAVE_ACC_ABSC(&acc1, 4); + CO += 8; + SAVE_ACC_ABSC(&acc2, 0); + SAVE_ACC_ABSC(&acc3, 4); + CO += 8; + SAVE_ACC_ABSC(&acc4, 0); + SAVE_ACC_ABSC(&acc5, 4); + CO += 8; + SAVE_ACC_ABSC(&acc6, 0); + SAVE_ACC_ABSC(&acc7, 4); + CO += 8; + } + } else { + if (m_skip || n_skip) { + SAVE_ACC_COND(&acc0, 0); + SAVE_ACC_COND(&acc1, 4); + SAVE_ACC_COND(&acc2, 8); + SAVE_ACC_COND(&acc3, 12); + SAVE_ACC_COND(&acc4, 16); + SAVE_ACC_COND(&acc5, 20); + SAVE_ACC_COND(&acc6, 24); + if ((j == (m_cap >> 5) - 1) && m_skip) { + int32_t ii; + int32_t count = 4 - (m_cap - m); + __builtin_mma_disassemble_acc((void *)result, &acc7); + SWIZZLE_4x4 for (ii = 0; ii < count; ++ii) + CO[0 * ldc + 28 + ii] + = beta * CO[0 * ldc + 28 + ii] + + alpha * result_t[0][ii]; + if ((n_cap - n) < 3) + for (ii = 0; ii < count; ++ii) + CO[1 * ldc + 28 + ii] + = beta * CO[1 * ldc + 28 + ii] + + alpha * result_t[1][ii]; + if ((n_cap - n) < 2) + for (ii = 0; ii < count; ++ii) + CO[2 * ldc + 28 + ii] + = beta * CO[2 * ldc + 28 + ii] + + alpha * result_t[2][ii]; + if ((n_cap - n) < 1) + for (ii = 0; ii < count; ++ii) + CO[3 * ldc + 28 + ii] + = beta * CO[3 * ldc + 28 + ii] + + alpha * result_t[3][ii]; + } else { + SAVE_ACC_COND(&acc7, 28); + } + CO += 32; + } else { + SAVE_ACC(&acc0, 0); + SAVE_ACC(&acc1, 4); + CO += 8; + SAVE_ACC(&acc2, 0); + SAVE_ACC(&acc3, 4); + CO += 8; + SAVE_ACC(&acc4, 0); + SAVE_ACC(&acc5, 4); + CO += 8; + SAVE_ACC(&acc6, 0); + SAVE_ACC(&acc7, 4); + CO += 8; + } + } + AO += k_cap << 5; + BO += k_cap << 2; + } + + if (m_skip) goto endloop4; + + m_skip = (m & 16) != (m_cap & 16); + + if (m_cap & 16) { + short *BO = B; + v4si_t *rowC; + __vector_quad acc0, acc1, acc2, acc3; + SET_ACC_ZERO4(); + vec_t *rowA = (vec_t *)AO; + vec_t *rowB = (vec_t *)BO; + int32_t l; + for (l = 0; l < k_cap / 2; l++) { + MMA(&acc0, rowA[0], rowB[0]); + MMA(&acc1, rowA[1], rowB[0]); + MMA(&acc2, rowA[2], rowB[0]); + MMA(&acc3, rowA[3], rowB[0]); + rowA += 4; + rowB += 1; + } + + if (fastpath) { + if (m_skip || n_skip) { + SAVE_ACC_COND_ABSC(&acc0, 0); + SAVE_ACC_COND_ABSC(&acc1, 4); + SAVE_ACC_COND_ABSC(&acc2, 8); + if (m_skip) { + __builtin_mma_disassemble_acc((void *)result, &acc3); + SWIZZLE_4x4 int32_t count = 4 - (m_cap - m); + int32_t ii; + for (ii = 0; ii < count; ++ii) + CO[0 * ldc + 12 + ii] = result_t[0][ii]; + if ((n_cap - n) < 3) + for (ii = 0; ii < count; ++ii) + CO[1 * ldc + 12 + ii] = result_t[1][ii]; + if ((n_cap - n) < 2) + for (ii = 0; ii < count; ++ii) + CO[2 * ldc + 12 + ii] = result_t[2][ii]; + if ((n_cap - n) < 1) + for (ii = 0; ii < count; ++ii) + CO[3 * ldc + 12 + ii] = result_t[3][ii]; + } else { + SAVE_ACC_COND_ABSC(&acc3, 12); + } + CO += 16; + } else { + SAVE_ACC_ABSC(&acc0, 0); + SAVE_ACC_ABSC(&acc1, 4); + CO += 8; + SAVE_ACC_ABSC(&acc2, 0); + SAVE_ACC_ABSC(&acc3, 4); + CO += 8; + } + } else { + if (m_skip || n_skip) { + SAVE_ACC_COND(&acc0, 0); + SAVE_ACC_COND(&acc1, 4); + SAVE_ACC_COND(&acc2, 8); + if (m_skip) { + __builtin_mma_disassemble_acc((void *)result, &acc3); + SWIZZLE_4x4 int32_t count = 4 - (m_cap - m); + int32_t ii; + for (ii = 0; ii < count; ++ii) + CO[0 * ldc + 12 + ii] = beta * CO[0 * ldc + 12 + ii] + + alpha * result_t[0][ii]; + if ((n_cap - n) < 3) + for (ii = 0; ii < count; ++ii) + CO[1 * ldc + 12 + ii] + = beta * CO[1 * ldc + 12 + ii] + + alpha * result_t[1][ii]; + if ((n_cap - n) < 2) + for (ii = 0; ii < count; ++ii) + CO[2 * ldc + 12 + ii] + = beta * CO[2 * ldc + 12 + ii] + + alpha * result_t[2][ii]; + if ((n_cap - n) < 1) + for (ii = 0; ii < count; ++ii) + CO[3 * ldc + 12 + ii] + = beta * CO[3 * ldc + 12 + ii] + + alpha * result_t[3][ii]; + } else { + SAVE_ACC_COND(&acc3, 12); + } + CO += 16; + } else { + SAVE_ACC(&acc0, 0); + SAVE_ACC(&acc1, 4); + CO += 8; + SAVE_ACC(&acc2, 0); + SAVE_ACC(&acc3, 4); + CO += 8; + } + } + AO += k_cap << 4; + BO += k_cap << 2; + } + + if (m_skip) goto endloop4; + + m_skip = (m & 8) != (m_cap & 8); + + if (m_cap & 8) { + short *BO = B; + v4si_t *rowC; + __vector_quad acc0, acc1; + __builtin_mma_xxsetaccz(&acc0); + __builtin_mma_xxsetaccz(&acc1); + vec_t *rowA = (vec_t *)AO; + vec_t *rowB = (vec_t *)BO; + int32_t l; + for (l = 0; l < k_cap / 2; l++) { + MMA(&acc0, rowA[0], rowB[0]); + MMA(&acc1, rowA[1], rowB[0]); + rowA += 2; + rowB += 1; + } + + if (fastpath) { + if (m_skip || n_skip) { + SAVE_ACC_COND_ABSC(&acc0, 0); + if (m_skip) { + int32_t ii; + int32_t count = 4 - (m_cap - m); + __builtin_mma_disassemble_acc((void *)result, &acc1); + SWIZZLE_4x4 for (ii = 0; ii < count; ++ii) + CO[0 * ldc + 4 + ii] + = result_t[0][ii]; + if ((n_cap - n) < 3) + for (ii = 0; ii < count; ++ii) + CO[1 * ldc + 4 + ii] = result_t[1][ii]; + if ((n_cap - n) < 2) + for (ii = 0; ii < count; ++ii) + CO[2 * ldc + 4 + ii] = result_t[2][ii]; + if ((n_cap - n) < 1) + for (ii = 0; ii < count; ++ii) + CO[3 * ldc + 4 + ii] = result_t[3][ii]; + } else { + SAVE_ACC_COND_ABSC(&acc1, 4); + } + } else { + SAVE_ACC_ABSC(&acc0, 0); + SAVE_ACC_ABSC(&acc1, 4); + } + } else { + if (m_skip || n_skip) { + SAVE_ACC_COND(&acc0, 0); + if (m_skip) { + int32_t ii; + int32_t count = 4 - (m_cap - m); + __builtin_mma_disassemble_acc((void *)result, &acc1); + SWIZZLE_4x4 for (ii = 0; ii < count; ++ii) + CO[0 * ldc + 4 + ii] + = beta * CO[0 * ldc + 4 + ii] + + alpha * result_t[0][ii]; + if ((n_cap - n) < 3) + for (ii = 0; ii < count; ++ii) + CO[1 * ldc + 4 + ii] + = beta * CO[1 * ldc + 4 + ii] + + alpha * result_t[1][ii]; + if ((n_cap - n) < 2) + for (ii = 0; ii < count; ++ii) + CO[2 * ldc + 4 + ii] + = beta * CO[2 * ldc + 4 + ii] + + alpha * result_t[2][ii]; + if ((n_cap - n) < 1) + for (ii = 0; ii < count; ++ii) + CO[3 * ldc + 4 + ii] + = beta * CO[3 * ldc + 4 + ii] + + alpha * result_t[3][ii]; + } else { + SAVE_ACC_COND(&acc1, 4); + } + } else { + SAVE_ACC(&acc0, 0); + SAVE_ACC(&acc1, 4); + } + } + CO += 8; + AO += k_cap << 3; + BO += k_cap << 2; + } + + if (m_skip) goto endloop4; + + m_skip = (m & 4) != (m_cap & 4); + + if (m_cap & 4) { + short *BO = B; + v4si_t *rowC; + __vector_quad acc0; + __builtin_mma_xxsetaccz(&acc0); + int32_t l; + vec_t *rowA = (vec_t *)AO; + vec_t *rowB = (vec_t *)BO; + for (l = 0; l < k_cap / 2; l++) { + MMA(&acc0, rowA[0], rowB[0]); + rowA += 1; + rowB += 1; + } + + if (fastpath) { + if (m_skip || n_skip) { + int32_t count = 4 - (m_cap - m); + int32_t ii; + __builtin_mma_disassemble_acc((void *)result, &acc0); + SWIZZLE_4x4 for (ii = 0; ii < count; ++ii) CO[0 * ldc + ii] + = result_t[0][ii]; + if ((n_cap - n) < 3) + for (ii = 0; ii < count; ++ii) + CO[1 * ldc + ii] = result_t[1][ii]; + if ((n_cap - n) < 2) + for (ii = 0; ii < count; ++ii) + CO[2 * ldc + ii] = result_t[2][ii]; + if ((n_cap - n) < 1) + for (ii = 0; ii < count; ++ii) + CO[3 * ldc + ii] = result_t[3][ii]; + } else { + SAVE_ACC_ABSC(&acc0, 0); + } + } else { + if (m_skip || n_skip) { + int32_t count = 4 - (m_cap - m); + int32_t ii; + __builtin_mma_disassemble_acc((void *)result, &acc0); + SWIZZLE_4x4 for (ii = 0; ii < count; ++ii) CO[0 * ldc + ii] + = beta * CO[0 * ldc + ii] + alpha * result_t[0][ii]; + if ((n_cap - n) < 3) + for (ii = 0; ii < count; ++ii) + CO[1 * ldc + ii] = beta * CO[1 * ldc + ii] + + alpha * result_t[1][ii]; + if ((n_cap - n) < 2) + for (ii = 0; ii < count; ++ii) + CO[2 * ldc + ii] = beta * CO[2 * ldc + ii] + + alpha * result_t[2][ii]; + if ((n_cap - n) < 1) + for (ii = 0; ii < count; ++ii) + CO[3 * ldc + ii] = beta * CO[3 * ldc + ii] + + alpha * result_t[3][ii]; + } else { + SAVE_ACC(&acc0, 0); + } + } + CO += 4; + AO += k_cap << 2; + BO += k_cap << 2; + } + + endloop4: + B += k_cap << 2; + } + return; +} + +#undef MMA +#define MMA __builtin_mma_xvi8ger4pp + +void gemm_kernel_8bit(dim_t m, dim_t n, dim_t k, float alpha, int8_t *A, + uint8_t *B, int32_t *C, float beta, dim_t ldc) { + int32_t i; + int32_t m_cap = (m + 3) & ~3; + int32_t n_cap = (n + 3) & ~3; + int32_t k_cap = (k + 3) & ~3; + int32_t m_skip; + int32_t n_skip = (n & 8) != (n_cap & 8); + int32_t fastpath; + v4si_t result[4], result_i[4], result_t[4]; + vec_t swizA = {0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23}; + vec_t swizB + = {8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31}; + vec_t swizC = {0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 23}; + vec_t swizD + = {8, 9, 10, 11, 12, 13, 14, 15, 24, 25, 26, 27, 28, 29, 30, 31}; + fastpath = ((alpha == 1.0) && (beta == 0.0)); + + /* Loop for multiples of 8 */ + i = n_cap >> 3; + while (i) { + int32_t j; + int32_t *CO; + int8_t *AO; + CO = C; + C += ldc << 3; + AO = A; + PREFETCH1(A, 128); + PREFETCH1(A, 256); + /* Loop for m >= 16. */ + j = m_cap >> 4; + m_skip = (m >> 4) != (m_cap >> 4); + while (j) { + uint8_t *BO = B; + v4si_t *rowC; + __vector_quad acc0, acc1, acc2, acc3, acc4, acc5, acc6, acc7; + SET_ACC_ZERO8(); + int32_t l; + vec_t *rowA = (vec_t *)AO; + vec_t *rowB = (vec_t *)BO; + for (l = 0; l < k_cap / 4; l++) { + MMA(&acc0, rowA[0], rowB[0]); + MMA(&acc1, rowA[0], rowB[1]); + MMA(&acc2, rowA[1], rowB[0]); + MMA(&acc3, rowA[1], rowB[1]); + MMA(&acc4, rowA[2], rowB[0]); + MMA(&acc5, rowA[2], rowB[1]); + MMA(&acc6, rowA[3], rowB[0]); + MMA(&acc7, rowA[3], rowB[1]); + rowA += 4; + rowB += 2; + } + + if (fastpath) { + SAVE_ACC_ABSC(&acc0, 0); + if ((i == 1) && n_skip) { + SAVE_ACC1_COND_ABSC(&acc1, 0); + } else { + SAVE_ACC1_ABSC(&acc1, 0); + } + CO += 4; + SAVE_ACC_ABSC(&acc2, 0); + if ((i == 1) && n_skip) { + SAVE_ACC1_COND_ABSC(&acc3, 0); + } else { + SAVE_ACC1_ABSC(&acc3, 0); + } + CO += 4; + SAVE_ACC_ABSC(&acc4, 0); + if ((i == 1) && n_skip) { + SAVE_ACC1_COND_ABSC(&acc5, 0); + } else { + SAVE_ACC1_ABSC(&acc5, 0); + } + CO += 4; + if (((j == 1) && m_skip) || ((i == 1) && n_skip)) { + if ((j == 1) && m_skip) { + int32_t count = 4 - (m_cap - m); + int32_t ii; + __builtin_mma_disassemble_acc((void *)result, &acc6); + SWIZZLE_4x4 for (ii = 0; ii < count; ++ii) + CO[0 * ldc + ii] + = result_t[0][ii]; + for (ii = 0; ii < count; ++ii) + CO[1 * ldc + ii] = result_t[1][ii]; + for (ii = 0; ii < count; ++ii) + CO[2 * ldc + ii] = result_t[2][ii]; + for (ii = 0; ii < count; ++ii) + CO[3 * ldc + ii] = result_t[3][ii]; + __builtin_mma_disassemble_acc((void *)result, &acc7); + SWIZZLE_4x4 for (ii = 0; ii < count; ++ii) + CO[4 * ldc + ii] + = result_t[0][ii]; + if ((i > 1) || (!n_skip) || (n_cap & 4) + || (n_cap - n) < 3) + for (ii = 0; ii < count; ++ii) + CO[5 * ldc + ii] = result_t[1][ii]; + if ((i > 1) || (!n_skip) || (n_cap & 4) + || (n_cap - n) < 2) + for (ii = 0; ii < count; ++ii) + CO[6 * ldc + ii] = result_t[2][ii]; + if ((i > 1) || (!n_skip) || (n_cap & 4) + || (n_cap - n) < 1) + for (ii = 0; ii < count; ++ii) + CO[7 * ldc + ii] = result_t[3][ii]; + } else { + SAVE_ACC_ABSC(&acc6, 0); + SAVE_ACC1_COND_ABSC(&acc7, 0); + } + } else { + SAVE_ACC_ABSC(&acc6, 0); + SAVE_ACC1_ABSC(&acc7, 0); + } + } else { + SAVE_ACC(&acc0, 0); + if ((i == 1) && n_skip) { + SAVE_ACC1_COND(&acc1, 0); + } else { + SAVE_ACC1(&acc1, 0); + } + CO += 4; + SAVE_ACC(&acc2, 0); + if ((i == 1) && n_skip) { + SAVE_ACC1_COND(&acc3, 0); + } else { + SAVE_ACC1(&acc3, 0); + } + CO += 4; + SAVE_ACC(&acc4, 0); + if ((i == 1) && n_skip) { + SAVE_ACC1_COND(&acc5, 0); + } else { + SAVE_ACC1(&acc5, 0); + } + CO += 4; + if (((j == 1) && m_skip) || ((i == 1) && n_skip)) { + if ((j == 1) && m_skip) { + int32_t count = 4 - (m_cap - m); + int32_t ii; + __builtin_mma_disassemble_acc((void *)result, &acc6); + SWIZZLE_4x4 for (ii = 0; ii < count; ++ii) + CO[0 * ldc + ii] + = beta * CO[0 * ldc + ii] + + alpha * result_t[0][ii]; + for (ii = 0; ii < count; ++ii) + CO[1 * ldc + ii] = beta * CO[1 * ldc + ii] + + alpha * result_t[1][ii]; + for (ii = 0; ii < count; ++ii) + CO[2 * ldc + ii] = beta * CO[2 * ldc + ii] + + alpha * result_t[2][ii]; + for (ii = 0; ii < count; ++ii) + CO[3 * ldc + ii] = beta * CO[3 * ldc + ii] + + alpha * result_t[3][ii]; + __builtin_mma_disassemble_acc((void *)result, &acc7); + SWIZZLE_4x4 for (ii = 0; ii < count; ++ii) + CO[4 * ldc + ii] + = beta * CO[4 * ldc + ii] + + alpha * result_t[0][ii]; + if ((i > 1) || (!n_skip) || (n_cap & 4) + || (n_cap - n) < 3) + for (ii = 0; ii < count; ++ii) + CO[5 * ldc + ii] = beta * CO[5 * ldc + ii] + + alpha * result_t[1][ii]; + if ((i > 1) || (!n_skip) || (n_cap & 4) + || (n_cap - n) < 2) + for (ii = 0; ii < count; ++ii) + CO[6 * ldc + ii] = beta * CO[6 * ldc + ii] + + alpha * result_t[2][ii]; + if ((i > 1) || (!n_skip) || (n_cap & 4) + || (n_cap - n) < 1) + for (ii = 0; ii < count; ++ii) + CO[7 * ldc + ii] = beta * CO[7 * ldc + ii] + + alpha * result_t[3][ii]; + } else { + SAVE_ACC(&acc6, 0); + SAVE_ACC1_COND(&acc7, 0); + } + } else { + SAVE_ACC(&acc6, 0); + SAVE_ACC1(&acc7, 0); + } + } + CO += 4; + AO += (k_cap << 4); + BO += (k_cap << 3); + --j; + } + + if (m_skip) goto endloop8; + + m_skip = (m & 8) != (m_cap & 8); + + if (m_cap & 8) { + uint8_t *BO = B; + v4si_t *rowC; + __vector_quad acc0, acc1, acc2, acc3; + SET_ACC_ZERO4(); + vec_t *rowA = (vec_t *)AO; + vec_t *rowB = (vec_t *)BO; + int32_t l; + for (l = 0; l < k_cap / 4; l++) { + MMA(&acc0, rowA[0], rowB[0]); + MMA(&acc1, rowA[0], rowB[1]); + MMA(&acc2, rowA[1], rowB[0]); + MMA(&acc3, rowA[1], rowB[1]); + rowA += 2; + rowB += 2; + } + + if (fastpath) { + SAVE_ACC_ABSC(&acc0, 0); + if ((i == 1) && n_skip) { + SAVE_ACC1_COND_ABSC(&acc1, 0); + } else { + SAVE_ACC1_ABSC(&acc1, 0); + } + CO += 4; + if (m_skip || ((i == 1) & n_skip)) { + if (m_skip) { + int32_t count = 4 - (m_cap - m); + int32_t ii; + __builtin_mma_disassemble_acc((void *)result, &acc2); + SWIZZLE_4x4 for (ii = 0; ii < count; ++ii) + CO[0 * ldc + ii] + = result_t[0][ii]; + for (ii = 0; ii < count; ++ii) + CO[1 * ldc + ii] = result_t[1][ii]; + for (ii = 0; ii < count; ++ii) + CO[2 * ldc + ii] = result_t[2][ii]; + for (ii = 0; ii < count; ++ii) + CO[3 * ldc + ii] = result_t[3][ii]; + __builtin_mma_disassemble_acc((void *)result, &acc3); + SWIZZLE_4x4 for (ii = 0; ii < count; ++ii) + CO[4 * ldc + ii] + = result_t[0][ii]; + if ((i > 1) || (!n_skip) || (n_cap & 4) + || (n_cap - n) < 3) + for (ii = 0; ii < count; ++ii) + CO[5 * ldc + ii] = result_t[1][ii]; + if ((i > 1) || (!n_skip) || (n_cap & 4) + || (n_cap - n) < 2) + for (ii = 0; ii < count; ++ii) + CO[6 * ldc + ii] = result_t[2][ii]; + if ((i > 1) || (!n_skip) || (n_cap & 4) + || (n_cap - n) < 1) + for (ii = 0; ii < count; ++ii) + CO[7 * ldc + ii] = result_t[3][ii]; + } else { + SAVE_ACC_ABSC(&acc2, 0); + SAVE_ACC1_COND_ABSC(&acc3, 0); + } + } else { + SAVE_ACC_ABSC(&acc2, 0); + SAVE_ACC1_ABSC(&acc3, 0); + } + } else { + SAVE_ACC(&acc0, 0); + if ((i == 1) && n_skip) { + SAVE_ACC1_COND(&acc1, 0); + } else { + SAVE_ACC1(&acc1, 0); + } + CO += 4; + if (m_skip || ((i == 1) & n_skip)) { + if (m_skip) { + int32_t count = 4 - (m_cap - m); + int32_t ii; + __builtin_mma_disassemble_acc((void *)result, &acc2); + SWIZZLE_4x4 for (ii = 0; ii < count; ++ii) + CO[0 * ldc + ii] + = beta * CO[0 * ldc + ii] + + alpha * result_t[0][ii]; + for (ii = 0; ii < count; ++ii) + CO[1 * ldc + ii] = beta * CO[1 * ldc + ii] + + alpha * result_t[1][ii]; + for (ii = 0; ii < count; ++ii) + CO[2 * ldc + ii] = beta * CO[2 * ldc + ii] + + alpha * result_t[2][ii]; + for (ii = 0; ii < count; ++ii) + CO[3 * ldc + ii] = beta * CO[3 * ldc + ii] + + alpha * result_t[3][ii]; + __builtin_mma_disassemble_acc((void *)result, &acc3); + SWIZZLE_4x4 for (ii = 0; ii < count; ++ii) + CO[4 * ldc + ii] + = beta * CO[4 * ldc + ii] + + alpha * result_t[0][ii]; + if ((i > 1) || (!n_skip) || (n_cap & 4) + || (n_cap - n) < 3) + for (ii = 0; ii < count; ++ii) + CO[5 * ldc + ii] = beta * CO[5 * ldc + ii] + + alpha * result_t[1][ii]; + if ((i > 1) || (!n_skip) || (n_cap & 4) + || (n_cap - n) < 2) + for (ii = 0; ii < count; ++ii) + CO[6 * ldc + ii] = beta * CO[6 * ldc + ii] + + alpha * result_t[2][ii]; + if ((i > 1) || (!n_skip) || (n_cap & 4) + || (n_cap - n) < 1) + for (ii = 0; ii < count; ++ii) + CO[7 * ldc + ii] = beta * CO[7 * ldc + ii] + + alpha * result_t[3][ii]; + } else { + SAVE_ACC(&acc2, 0); + SAVE_ACC1_COND(&acc3, 0); + } + } else { + SAVE_ACC(&acc2, 0); + SAVE_ACC1(&acc3, 0); + } + } + CO += 4; + AO += (k_cap << 3); + BO += (k_cap << 3); + } + + if (m_skip) goto endloop8; + + m_skip = (m & 4) != (m_cap & 4); + + if (m_cap & 4) { + uint8_t *BO = B; + v4si_t *rowC; + __vector_quad acc0, acc1; + __builtin_mma_xxsetaccz(&acc0); + __builtin_mma_xxsetaccz(&acc1); + vec_t *rowA = (vec_t *)AO; + vec_t *rowB = (vec_t *)BO; + int32_t l = 0; + for (l = 0; l < k_cap / 4; l++) { + MMA(&acc0, rowA[0], rowB[0]); + MMA(&acc1, rowA[0], rowB[1]); + rowA += 1; + rowB += 2; + } + + if (fastpath) { + if (m_skip || ((i == 1) & n_skip)) { + if (m_skip) { + int32_t count = 4 - (m_cap - m); + int32_t ii; + __builtin_mma_disassemble_acc((void *)result, &acc0); + SWIZZLE_4x4 for (ii = 0; ii < count; ++ii) + CO[0 * ldc + ii] + = result_t[0][ii]; + for (ii = 0; ii < count; ++ii) + CO[1 * ldc + ii] = result_t[1][ii]; + for (ii = 0; ii < count; ++ii) + CO[2 * ldc + ii] = result_t[2][ii]; + for (ii = 0; ii < count; ++ii) + CO[3 * ldc + ii] = result_t[3][ii]; + __builtin_mma_disassemble_acc((void *)result, &acc1); + SWIZZLE_4x4 for (ii = 0; ii < count; ++ii) + CO[4 * ldc + ii] + = result_t[0][ii]; + if ((i == 1) & n_skip) { + if ((n_cap & 4) || (n_cap - n) < 3) + for (ii = 0; ii < count; ++ii) + CO[5 * ldc + ii] = result_t[1][ii]; + if ((n_cap & 4) || (n_cap - n) < 2) + for (ii = 0; ii < count; ++ii) + CO[6 * ldc + ii] = result_t[2][ii]; + if ((n_cap & 4) || (n_cap - n) < 1) + for (ii = 0; ii < count; ++ii) + CO[7 * ldc + ii] = result_t[3][ii]; + } else { + for (ii = 0; ii < count; ++ii) + CO[5 * ldc + ii] = result_t[1][ii]; + for (ii = 0; ii < count; ++ii) + CO[6 * ldc + ii] = result_t[2][ii]; + for (ii = 0; ii < count; ++ii) + CO[7 * ldc + ii] = result_t[3][ii]; + } + } else { + SAVE_ACC_ABSC(&acc0, 0); + SAVE_ACC1_COND_ABSC(&acc1, 0); + } + } else { + SAVE_ACC_ABSC(&acc0, 0); + SAVE_ACC1_ABSC(&acc1, 0); + } + } else { + if (m_skip || ((i == 1) & n_skip)) { + if (m_skip) { + int32_t count = 4 - (m_cap - m); + int32_t ii; + __builtin_mma_disassemble_acc((void *)result, &acc0); + SWIZZLE_4x4 for (ii = 0; ii < count; ++ii) + CO[0 * ldc + ii] + = beta * CO[0 * ldc + ii] + + alpha * result_t[0][ii]; + for (ii = 0; ii < count; ++ii) + CO[1 * ldc + ii] = beta * CO[1 * ldc + ii] + + alpha * result_t[1][ii]; + for (ii = 0; ii < count; ++ii) + CO[2 * ldc + ii] = beta * CO[2 * ldc + ii] + + alpha * result_t[2][ii]; + for (ii = 0; ii < count; ++ii) + CO[3 * ldc + ii] = beta * CO[3 * ldc + ii] + + alpha * result_t[3][ii]; + __builtin_mma_disassemble_acc((void *)result, &acc1); + SWIZZLE_4x4 for (ii = 0; ii < count; ++ii) + CO[4 * ldc + ii] + = beta * CO[4 * ldc + ii] + + alpha * result_t[0][ii]; + if ((i == 1) & n_skip) { + if ((n_cap & 4) || (n_cap - n) < 3) + for (ii = 0; ii < count; ++ii) + CO[5 * ldc + ii] = beta * CO[5 * ldc + ii] + + alpha * result_t[1][ii]; + if ((n_cap & 4) || (n_cap - n) < 2) + for (ii = 0; ii < count; ++ii) + CO[6 * ldc + ii] = beta * CO[6 * ldc + ii] + + alpha * result_t[2][ii]; + if ((n_cap & 4) || (n_cap - n) < 1) + for (ii = 0; ii < count; ++ii) + CO[7 * ldc + ii] = beta * CO[7 * ldc + ii] + + alpha * result_t[3][ii]; + } else { + for (ii = 0; ii < count; ++ii) + CO[5 * ldc + ii] = beta * CO[5 * ldc + ii] + + alpha * result_t[1][ii]; + for (ii = 0; ii < count; ++ii) + CO[6 * ldc + ii] = beta * CO[6 * ldc + ii] + + alpha * result_t[2][ii]; + for (ii = 0; ii < count; ++ii) + CO[7 * ldc + ii] = beta * CO[7 * ldc + ii] + + alpha * result_t[3][ii]; + } + } else { + SAVE_ACC(&acc0, 0); + SAVE_ACC1_COND(&acc1, 0); + } + } else { + SAVE_ACC(&acc0, 0); + SAVE_ACC1(&acc1, 0); + } + } + CO += 4; + AO += (k_cap << 2); + BO += (k_cap << 3); + } + + endloop8: + B += k_cap << 3; + i -= 1; + } + + if (n_cap & 4) { + int32_t j; + int32_t *CO; + int8_t *AO; + CO = C; + C += ldc << 2; + AO = A; + int32_t n_skip = (n != n_cap); + /* Loop for m >= 32. */ + m_skip = (m >> 5) != (m_cap >> 5); + for (j = 0; j < (m_cap >> 5); j++) { + uint8_t *BO = B; + int8_t *A1 = AO + (16 * k_cap); + v4si_t *rowC; + __vector_quad acc0, acc1, acc2, acc3, acc4, acc5, acc6, acc7; + SET_ACC_ZERO8(); + vec_t *rowA = (vec_t *)AO; + vec_t *rowA1 = (vec_t *)A1; + vec_t *rowB = (vec_t *)BO; + int32_t l; + for (l = 0; l < k_cap / 4; l++) { + MMA(&acc0, rowA[0], rowB[0]); + MMA(&acc1, rowA[1], rowB[0]); + MMA(&acc2, rowA[2], rowB[0]); + MMA(&acc3, rowA[3], rowB[0]); + MMA(&acc4, rowA1[0], rowB[0]); + MMA(&acc5, rowA1[1], rowB[0]); + MMA(&acc6, rowA1[2], rowB[0]); + MMA(&acc7, rowA1[3], rowB[0]); + rowA += 4; + rowA1 += 4; + rowB += 1; + } + + if (fastpath) { + if (m_skip || n_skip) { + SAVE_ACC_COND_ABSC(&acc0, 0); + SAVE_ACC_COND_ABSC(&acc1, 4); + SAVE_ACC_COND_ABSC(&acc2, 8); + SAVE_ACC_COND_ABSC(&acc3, 12); + SAVE_ACC_COND_ABSC(&acc4, 16); + SAVE_ACC_COND_ABSC(&acc5, 20); + SAVE_ACC_COND_ABSC(&acc6, 24); + if ((j == (m_cap >> 5) - 1) && m_skip) { + int32_t ii; + int32_t count = 4 - (m_cap - m); + __builtin_mma_disassemble_acc((void *)result, &acc7); + SWIZZLE_4x4 for (ii = 0; ii < count; ++ii) + CO[0 * ldc + 28 + ii] + = result_t[0][ii]; + if ((n_cap - n) < 3) + for (ii = 0; ii < count; ++ii) + CO[1 * ldc + 28 + ii] = result_t[1][ii]; + if ((n_cap - n) < 2) + for (ii = 0; ii < count; ++ii) + CO[2 * ldc + 28 + ii] = result_t[2][ii]; + if ((n_cap - n) < 1) + for (ii = 0; ii < count; ++ii) + CO[3 * ldc + 28 + ii] = result_t[3][ii]; + } else { + SAVE_ACC_COND_ABSC(&acc7, 28); + } + CO += 32; + } else { + SAVE_ACC_ABSC(&acc0, 0); + SAVE_ACC_ABSC(&acc1, 4); + CO += 8; + SAVE_ACC_ABSC(&acc2, 0); + SAVE_ACC_ABSC(&acc3, 4); + CO += 8; + SAVE_ACC_ABSC(&acc4, 0); + SAVE_ACC_ABSC(&acc5, 4); + CO += 8; + SAVE_ACC_ABSC(&acc6, 0); + SAVE_ACC_ABSC(&acc7, 4); + CO += 8; + } + } else { + if (m_skip || n_skip) { + SAVE_ACC_COND(&acc0, 0); + SAVE_ACC_COND(&acc1, 4); + SAVE_ACC_COND(&acc2, 8); + SAVE_ACC_COND(&acc3, 12); + SAVE_ACC_COND(&acc4, 16); + SAVE_ACC_COND(&acc5, 20); + SAVE_ACC_COND(&acc6, 24); + if ((j == (m_cap >> 5) - 1) && m_skip) { + int32_t ii; + int32_t count = 4 - (m_cap - m); + __builtin_mma_disassemble_acc((void *)result, &acc7); + SWIZZLE_4x4 for (ii = 0; ii < count; ++ii) + CO[0 * ldc + 28 + ii] + = beta * CO[0 * ldc + 28 + ii] + + alpha * result_t[0][ii]; + if ((n_cap - n) < 3) + for (ii = 0; ii < count; ++ii) + CO[1 * ldc + 28 + ii] + = beta * CO[1 * ldc + 28 + ii] + + alpha * result_t[1][ii]; + if ((n_cap - n) < 2) + for (ii = 0; ii < count; ++ii) + CO[2 * ldc + 28 + ii] + = beta * CO[2 * ldc + 28 + ii] + + alpha * result_t[2][ii]; + if ((n_cap - n) < 1) + for (ii = 0; ii < count; ++ii) + CO[3 * ldc + 28 + ii] + = beta * CO[3 * ldc + 28 + ii] + + alpha * result_t[3][ii]; + } else { + SAVE_ACC_COND(&acc7, 28); + } + CO += 32; + } else { + SAVE_ACC(&acc0, 0); + SAVE_ACC(&acc1, 4); + CO += 8; + SAVE_ACC(&acc2, 0); + SAVE_ACC(&acc3, 4); + CO += 8; + SAVE_ACC(&acc4, 0); + SAVE_ACC(&acc5, 4); + CO += 8; + SAVE_ACC(&acc6, 0); + SAVE_ACC(&acc7, 4); + CO += 8; + } + } + AO += k_cap << 5; + BO += k_cap << 2; + } + + if (m_skip) goto endloop4; + + m_skip = (m & 16) != (m_cap & 16); + + if (m_cap & 16) { + uint8_t *BO = B; + v4si_t *rowC; + __vector_quad acc0, acc1, acc2, acc3; + SET_ACC_ZERO4(); + vec_t *rowA = (vec_t *)AO; + vec_t *rowB = (vec_t *)BO; + int32_t l; + for (l = 0; l < k_cap / 4; l++) { + MMA(&acc0, rowA[0], rowB[0]); + MMA(&acc1, rowA[1], rowB[0]); + MMA(&acc2, rowA[2], rowB[0]); + MMA(&acc3, rowA[3], rowB[0]); + rowA += 4; + rowB += 1; + } + + if (fastpath) { + if (m_skip || n_skip) { + SAVE_ACC_COND_ABSC(&acc0, 0); + SAVE_ACC_COND_ABSC(&acc1, 4); + SAVE_ACC_COND_ABSC(&acc2, 8); + if (m_skip) { + __builtin_mma_disassemble_acc((void *)result, &acc3); + SWIZZLE_4x4 int32_t count = 4 - (m_cap - m); + int32_t ii; + for (ii = 0; ii < count; ++ii) + CO[0 * ldc + 12 + ii] = result_t[0][ii]; + if ((n_cap - n) < 3) + for (ii = 0; ii < count; ++ii) + CO[1 * ldc + 12 + ii] = result_t[1][ii]; + if ((n_cap - n) < 2) + for (ii = 0; ii < count; ++ii) + CO[2 * ldc + 12 + ii] = result_t[2][ii]; + if ((n_cap - n) < 1) + for (ii = 0; ii < count; ++ii) + CO[3 * ldc + 12 + ii] = result_t[3][ii]; + } else { + SAVE_ACC_COND_ABSC(&acc3, 12); + } + CO += 16; + } else { + SAVE_ACC_ABSC(&acc0, 0); + SAVE_ACC_ABSC(&acc1, 4); + CO += 8; + SAVE_ACC_ABSC(&acc2, 0); + SAVE_ACC_ABSC(&acc3, 4); + CO += 8; + } + } else { + if (m_skip || n_skip) { + SAVE_ACC_COND(&acc0, 0); + SAVE_ACC_COND(&acc1, 4); + SAVE_ACC_COND(&acc2, 8); + if (m_skip) { + __builtin_mma_disassemble_acc((void *)result, &acc3); + SWIZZLE_4x4 int32_t count = 4 - (m_cap - m); + int32_t ii; + for (ii = 0; ii < count; ++ii) + CO[0 * ldc + 12 + ii] = beta * CO[0 * ldc + 12 + ii] + + alpha * result_t[0][ii]; + if ((n_cap - n) < 3) + for (ii = 0; ii < count; ++ii) + CO[1 * ldc + 12 + ii] + = beta * CO[1 * ldc + 12 + ii] + + alpha * result_t[1][ii]; + if ((n_cap - n) < 2) + for (ii = 0; ii < count; ++ii) + CO[2 * ldc + 12 + ii] + = beta * CO[2 * ldc + 12 + ii] + + alpha * result_t[2][ii]; + if ((n_cap - n) < 1) + for (ii = 0; ii < count; ++ii) + CO[3 * ldc + 12 + ii] + = beta * CO[3 * ldc + 12 + ii] + + alpha * result_t[3][ii]; + } else { + SAVE_ACC_COND(&acc3, 12); + } + CO += 16; + } else { + SAVE_ACC(&acc0, 0); + SAVE_ACC(&acc1, 4); + CO += 8; + SAVE_ACC(&acc2, 0); + SAVE_ACC(&acc3, 4); + CO += 8; + } + } + AO += k_cap << 4; + BO += k_cap << 2; + } + + if (m_skip) goto endloop4; + + m_skip = (m & 8) != (m_cap & 8); + + if (m_cap & 8) { + uint8_t *BO = B; + v4si_t *rowC; + __vector_quad acc0, acc1; + __builtin_mma_xxsetaccz(&acc0); + __builtin_mma_xxsetaccz(&acc1); + vec_t *rowA = (vec_t *)AO; + vec_t *rowB = (vec_t *)BO; + int32_t l; + for (l = 0; l < k_cap / 4; l++) { + MMA(&acc0, rowA[0], rowB[0]); + MMA(&acc1, rowA[1], rowB[0]); + rowA += 2; + rowB += 1; + } + + if (fastpath) { + if (m_skip || n_skip) { + SAVE_ACC_COND_ABSC(&acc0, 0); + if (m_skip) { + int32_t ii; + int32_t count = 4 - (m_cap - m); + __builtin_mma_disassemble_acc((void *)result, &acc1); + SWIZZLE_4x4 for (ii = 0; ii < count; ++ii) + CO[0 * ldc + 4 + ii] + = result_t[0][ii]; + if ((n_cap - n) < 3) + for (ii = 0; ii < count; ++ii) + CO[1 * ldc + 4 + ii] = result_t[1][ii]; + if ((n_cap - n) < 2) + for (ii = 0; ii < count; ++ii) + CO[2 * ldc + 4 + ii] = result_t[2][ii]; + if ((n_cap - n) < 1) + for (ii = 0; ii < count; ++ii) + CO[3 * ldc + 4 + ii] = result_t[3][ii]; + } else { + SAVE_ACC_COND_ABSC(&acc1, 4); + } + } else { + SAVE_ACC_ABSC(&acc0, 0); + SAVE_ACC_ABSC(&acc1, 4); + } + } else { + if (m_skip || n_skip) { + SAVE_ACC_COND(&acc0, 0); + if (m_skip) { + int32_t ii; + int32_t count = 4 - (m_cap - m); + __builtin_mma_disassemble_acc((void *)result, &acc1); + SWIZZLE_4x4 for (ii = 0; ii < count; ++ii) + CO[0 * ldc + 4 + ii] + = beta * CO[0 * ldc + 4 + ii] + + alpha * result_t[0][ii]; + if ((n_cap - n) < 3) + for (ii = 0; ii < count; ++ii) + CO[1 * ldc + 4 + ii] + = beta * CO[1 * ldc + 4 + ii] + + alpha * result_t[1][ii]; + if ((n_cap - n) < 2) + for (ii = 0; ii < count; ++ii) + CO[2 * ldc + 4 + ii] + = beta * CO[2 * ldc + 4 + ii] + + alpha * result_t[2][ii]; + if ((n_cap - n) < 1) + for (ii = 0; ii < count; ++ii) + CO[3 * ldc + 4 + ii] + = beta * CO[3 * ldc + 4 + ii] + + alpha * result_t[3][ii]; + } else { + SAVE_ACC_COND(&acc1, 4); + } + } else { + SAVE_ACC(&acc0, 0); + SAVE_ACC(&acc1, 4); + } + } + CO += 8; + AO += k_cap << 3; + BO += k_cap << 2; + } + + if (m_skip) goto endloop4; + + m_skip = (m & 4) != (m_cap & 4); + + if (m_cap & 4) { + uint8_t *BO = B; + v4si_t *rowC; + __vector_quad acc0; + __builtin_mma_xxsetaccz(&acc0); + int32_t l; + vec_t *rowA = (vec_t *)AO; + vec_t *rowB = (vec_t *)BO; + for (l = 0; l < k_cap / 4; l++) { + MMA(&acc0, rowA[0], rowB[0]); + rowA += 1; + rowB += 1; + } + + if (fastpath) { + if (m_skip || n_skip) { + int32_t count = 4 - (m_cap - m); + int32_t ii; + __builtin_mma_disassemble_acc((void *)result, &acc0); + SWIZZLE_4x4 for (ii = 0; ii < count; ++ii) CO[0 * ldc + ii] + = result_t[0][ii]; + if ((n_cap - n) < 3) + for (ii = 0; ii < count; ++ii) + CO[1 * ldc + ii] = result_t[1][ii]; + if ((n_cap - n) < 2) + for (ii = 0; ii < count; ++ii) + CO[2 * ldc + ii] = result_t[2][ii]; + if ((n_cap - n) < 1) + for (ii = 0; ii < count; ++ii) + CO[3 * ldc + ii] = result_t[3][ii]; + } else { + SAVE_ACC_ABSC(&acc0, 0); + } + } else { + if (m_skip || n_skip) { + int32_t count = 4 - (m_cap - m); + int32_t ii; + __builtin_mma_disassemble_acc((void *)result, &acc0); + SWIZZLE_4x4 for (ii = 0; ii < count; ++ii) CO[0 * ldc + ii] + = beta * CO[0 * ldc + ii] + alpha * result_t[0][ii]; + if ((n_cap - n) < 3) + for (ii = 0; ii < count; ++ii) + CO[1 * ldc + ii] = beta * CO[1 * ldc + ii] + + alpha * result_t[1][ii]; + if ((n_cap - n) < 2) + for (ii = 0; ii < count; ++ii) + CO[2 * ldc + ii] = beta * CO[2 * ldc + ii] + + alpha * result_t[2][ii]; + if ((n_cap - n) < 1) + for (ii = 0; ii < count; ++ii) + CO[3 * ldc + ii] = beta * CO[3 * ldc + ii] + + alpha * result_t[3][ii]; + } else { + SAVE_ACC(&acc0, 0); + } + } + CO += 4; + AO += k_cap << 2; + BO += k_cap << 2; + } + + endloop4: + B += k_cap << 2; + } + return; +} + +} // namespace impl +} // namespace dnnl diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/reorder/cpu_reorder.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/reorder/cpu_reorder.hpp new file mode 100644 index 0000000000000000000000000000000000000000..82ea2b13e2fe14794e5a008810397f6ef1aea7e9 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/reorder/cpu_reorder.hpp @@ -0,0 +1,128 @@ +/******************************************************************************* +* Copyright 2020-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_REORDER_CPU_REORDER_HPP +#define CPU_REORDER_CPU_REORDER_HPP + +#include +#include + +#include "cpu/reorder/simple_reorder.hpp" + +#include "common/impl_list_item.hpp" +#include "common/memory.hpp" +#include "common/type_helpers.hpp" + +#include "cpu/cpu_engine.hpp" +#include "cpu/reorder/cpu_reorder_pd.hpp" + +#if DNNL_X64 +#include "cpu/x64/jit_uni_reorder.hpp" +#include "cpu/x64/matmul/brgemm_matmul_reorders.hpp" +#elif DNNL_AARCH64 +#include "cpu/aarch64/jit_uni_reorder.hpp" +#endif + +#include "cpu/rnn/rnn_reorders.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { + +using namespace dnnl::impl::data_type; +using namespace dnnl::impl::format_tag; + +struct reorder_impl_key_t { + data_type_t src_dt; + data_type_t dst_dt; // data_type::undef if arbitrary + int ndims; // 0 if arbitrary + + bool operator<(const reorder_impl_key_t &rhs) const { + return value() < rhs.value(); + } + +private: + enum { MAX_DT_NUM = 10 }; + size_t value() const { + return ((size_t)ndims * MAX_DT_NUM + (size_t)src_dt) * MAX_DT_NUM + + (size_t)dst_dt; + } +}; + +using impl_list_map_t + = std::map>; + +/* regular reorders */ +extern const impl_list_map_t ®ular_f32_bf16_impl_list_map(); +extern const impl_list_map_t ®ular_f32_f16_impl_list_map(); +extern const impl_list_map_t ®ular_f32_f32_impl_list_map(); +extern const impl_list_map_t ®ular_f32_s32_impl_list_map(); +extern const impl_list_map_t ®ular_f32_s8_impl_list_map(); +extern const impl_list_map_t ®ular_f32_u8_impl_list_map(); +extern const impl_list_map_t ®ular_bf16_impl_list_map(); +extern const impl_list_map_t ®ular_f16_impl_list_map(); +extern const impl_list_map_t ®ular_s32_impl_list_map(); +extern const impl_list_map_t ®ular_s8_impl_list_map(); +extern const impl_list_map_t ®ular_u8_impl_list_map(); + +/* conv reorders w/ compensation */ +extern const impl_list_map_t &comp_f32_s8_impl_list_map(); +extern const impl_list_map_t &comp_bf16_s8_impl_list_map(); +extern const impl_list_map_t &comp_s8_s8_impl_list_map(); + +// clang-format off + +#define REG_SR(idt, ifmt, odt, ofmt, ...) \ + impl_list_item_t(impl_list_item_t::reorder_type_deduction_helper_t< \ + simple_reorder_t::pd_t>()), + +#define REG_SR_BIDIR(idt, ifmt, odt, ofmt) \ + REG_SR(idt, ifmt, odt, ofmt, fmt_order::keep) \ + REG_SR(idt, ifmt, odt, ofmt, fmt_order::reverse) + +#define REG_SR_DIRECT_COPY(idt, odt) \ + REG_SR(idt, any, odt, any, fmt_order::any, spec::direct_copy) \ + REG_SR(idt, any, odt, any, fmt_order::any, spec::direct_copy_except_dim_0) + +// clang-format on + +#if defined(__INTEL_COMPILER) || (defined(__GNUC__) && !defined(__clang__)) +/* Direct copy for icc which is faster than jitted code; + * Direct copy for gcc which might or might not be faster than jitted + * code, but still worth it because doesn't require jitting, i.e. much + * faster creation time. This is tentative solution and should be + * removed later (when we will cache jitted code?...). */ +#define REG_FAST_DIRECT_COPY_F32_F32 REG_SR_DIRECT_COPY(f32, f32) +#else +#define REG_FAST_DIRECT_COPY_F32_F32 +#endif + +#ifdef __INTEL_COMPILER +/* direct copy for icc, which is faster than jitted code */ +#define REG_FAST_DIRECT_COPY(sdt, ddt) REG_SR_DIRECT_COPY(sdt, ddt) +#else +#define REG_FAST_DIRECT_COPY(sdt, ddt) +#endif + +#define CPU_REORDER_INSTANCE(...) \ + impl_list_item_t(impl_list_item_t::reorder_type_deduction_helper_t< \ + __VA_ARGS__::pd_t>()), + +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/reorder/cpu_reorder_pd.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/reorder/cpu_reorder_pd.hpp new file mode 100644 index 0000000000000000000000000000000000000000..639a20310dd35c7ec21fb16f60ea8b8cc57cfbf8 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/reorder/cpu_reorder_pd.hpp @@ -0,0 +1,112 @@ +/******************************************************************************* +* Copyright 2016-2022 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_REORDER_CPU_REORDER_PD_HPP +#define CPU_REORDER_CPU_REORDER_PD_HPP + +#include + +#include "common/c_types_map.hpp" +#include "common/reorder_pd.hpp" +#include "common/utils.hpp" +#include "cpu/cpu_engine.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { + +struct cpu_reorder_pd_t : public reorder_pd_t { + using reorder_pd_t::reorder_pd_t; + + status_t init( + engine_t *engine, engine_t *src_engine, engine_t *dst_engine) { + const auto &post_ops = attr()->post_ops_; + bool args_ok = IMPLICATION(post_ops.len() != 0, + post_ops.len() == 1 + && post_ops.entry_[0].kind == primitive_kind::sum); + return args_ok ? status::success : status::unimplemented; + } + + // The function splits dimension products based on input mask and returns + // them as `D_start`, `D_mask` and `D_rest`. + // Its used to estimate amount of memory for scratchpad and precomputed + // destination scales. + void get_D_values(const memory_desc_wrapper &input_d, int mask, + dim_t *D_start, dim_t *D_mask, dim_t *D_rest) const { + int ndims = input_d.ndims(); + int ndims_start = 0, ndims_mask = 0; + // XXX: Currently user can pass a mask that has non-zero values in + // dimensions that do not exist in a md. Since attributes are created + // separately mask can't be validated. + // This line truncates a given mask in range [0, 1 << ndims - 1] + // TODO: Such masks can be either prohibited at pd creation step at + // API level or checked by each implementation that relies on it. + mask &= (1 << ndims) - 1; + + for (; mask > 0 && !(mask & 0x1); mask >>= 1) + ++ndims_start; + for (; mask > 0 && mask & 0x1; mask >>= 1) + ++ndims_mask; + assert(mask == 0); + + if (D_start) + *D_start = utils::array_product(input_d.dims(), ndims_start); + if (D_mask) + *D_mask = utils::array_product( + input_d.dims() + ndims_start, ndims_mask); + assert(*D_mask >= 1); + if (D_rest) *D_rest = input_d.nelems() / (*D_start * *D_mask); + } + + // The function serves same purpose as `dnnl::impl::cpu::precompute_scales`. + // The reason it's dedicated to reorder is it's the only primitive so far + // that utilizes `mask > 0` for destination scales. + const float *precompute_scales(const memory_tracking::grantor_t &scratchpad, + const primitive_attr_t *attr, size_t count, + const float *dst_scales) const { + using namespace dnnl::impl::memory_tracking::names; + + int mask = -1; + bool is_set = false; + auto status = attr->scales_.get(DNNL_ARG_DST, &mask, &is_set); + if (status != status::success) return nullptr; + + // It's possible that mask > 0 but `count` is still `1`. This case is + // covered by `DEFINE_ARG_SCALES_BUFFER` macro and no need to inverse + // in such case. + if (is_set && mask > 0 && count > 1) { + auto loc_scales = scratchpad.template get( + key_reorder_precomputed_dst_scales); + if (!loc_scales) return nullptr; + + PRAGMA_OMP_SIMD() + for (size_t c = 0; c < count; c++) + loc_scales[c] = 1.f / dst_scales[c]; + + return loc_scales; + } else { + return dst_scales; + } + } +}; + +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/reorder/simple_reorder.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/reorder/simple_reorder.hpp new file mode 100644 index 0000000000000000000000000000000000000000..2dee00a8ec2ae7419e69d98fcf7b2b8145c565f6 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/reorder/simple_reorder.hpp @@ -0,0 +1,2210 @@ +/******************************************************************************* +* Copyright 2016-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_REORDER_SIMPLE_REORDER_HPP +#define CPU_REORDER_SIMPLE_REORDER_HPP + +#include +#include + +#include "common/bfloat16.hpp" +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/math_utils.hpp" +#include "common/primitive.hpp" +#include "common/primitive_attr.hpp" +#include "common/tag_traits.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_primitive.hpp" +#include "cpu/reorder/cpu_reorder_pd.hpp" + +#include "cpu/simple_q10n.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { + +using bd = block_dim_t; +using ib = inner_blk_t; + +template +using data_t = typename prec_traits::type; + +template +using _qz_a1b0 = qz_a1b0, data_t>; + +template +using _qz = qz, data_t>; + +namespace fmt_order { +const bool keep = true; +const bool reverse = false; +const bool any = keep; +} // namespace fmt_order + +namespace spec { +struct direct_copy {}; +struct direct_copy_except_dim_0 {}; +struct reference {}; +struct conv_req_comp {}; // {s8, u8: asymmetric quantization} +} // namespace spec + +#define SIMPLE_REORDER_TEMPL_DECL \ + impl::data_type_t type_i, impl::format_tag_t tag_i, \ + impl::data_type_t type_o, impl::format_tag_t tag_o, \ + bool order_keep +#define SIMPLE_REORDER_TEMPL_CALL type_i, tag_i, type_o, tag_o, order_keep + +#define DECLARE_COMMON_PARAMS() \ + auto input = CTX_IN_MEM(const data_t *, DNNL_ARG_FROM); \ + auto output = CTX_OUT_MEM(data_t *, DNNL_ARG_TO); \ + const auto &scratchpad = ctx.get_scratchpad_grantor(); \ + MAYBE_UNUSED(scratchpad); \ + const auto input_d = ctx.memory_mdw(DNNL_ARG_FROM, pd->src_md()); \ + const auto output_d = ctx.memory_mdw(DNNL_ARG_TO, pd->dst_md()); \ + DEFINE_ARG_SCALES_BUFFER_ATTR(pd->attr(), src_scales, DNNL_ARG_FROM); \ + DEFINE_ARG_SCALES_BUFFER_ATTR(pd->attr(), dst_scales_, DNNL_ARG_TO); \ + int src_scales_mask, dst_scales_mask; \ + CHECK(get_scales_mask(pd->attr(), &src_scales_mask, &dst_scales_mask)); \ + int scales_mask = std::max(src_scales_mask, dst_scales_mask); \ + MAYBE_UNUSED(scales_mask); \ + dim_t D_start, D_mask, D_rest; \ + pd->get_D_values(input_d, scales_mask, &D_start, &D_mask, &D_rest); \ + const float *dst_scales = pd->precompute_scales( \ + scratchpad, pd->attr(), D_mask, dst_scales_); \ + MAYBE_UNUSED(dst_scales); \ + DEFINE_ZERO_POINT_VALUE_ATTR(pd->attr(), src_zp, DNNL_ARG_FROM); \ + DEFINE_ZERO_POINT_VALUE_ATTR(pd->attr(), dst_zp, DNNL_ARG_TO); \ + const float alpha = src_scales[0] * dst_scales[0]; \ + MAYBE_UNUSED(alpha); \ + const float beta = pd->beta(); \ + MAYBE_UNUSED(beta); + +#define GET_SCRATCHPAD_SIZE_ZERO() \ + static size_t get_scratchpad_size(const memory_desc_wrapper &input_d, \ + const memory_desc_wrapper &output_d) { \ + return 0; \ + } + +/* specific reorders: common template */ +template +struct simple_reorder_impl {}; + +namespace { +inline bool simple_fmt_check(bool order_keep, impl::format_tag_t tag_i, + impl::format_tag_t tag_o, const memory_desc_wrapper &input_d, + const memory_desc_wrapper &output_d) { + if (input_d.has_runtime_dims_or_strides()) return false; + return input_d.matches_tag(order_keep ? tag_i : tag_o) + && output_d.matches_tag(order_keep ? tag_o : tag_i); +} +inline bool simple_po_check(const primitive_attr_t *attr) { + const auto &po = attr->post_ops_; + return po.len() == 0 || (po.len() == 1 && po.entry_[0].is_sum(false)); +} +inline status_t get_scales_mask( + const primitive_attr_t *attr, int *src_mask, int *dst_mask) { + const auto &s = attr->scales_; + if (src_mask) { + *src_mask = 0; + if (!s.get(DNNL_ARG_SRC).has_default_values()) + *src_mask = s.get(DNNL_ARG_SRC).mask_; + } + if (dst_mask) { + *dst_mask = 0; + if (!s.get(DNNL_ARG_DST).has_default_values()) + *dst_mask = s.get(DNNL_ARG_DST).mask_; + } + + // This is used in a check function. + if (*src_mask > 0 && *dst_mask > 0 && *dst_mask != *src_mask) + return status::invalid_arguments; + return status::success; +} +inline bool simple_attr_check(const primitive_attr_t *attr, + bool many_scales_support, bool sum_support) { + using smask_t = primitive_attr_t::skip_mask_t; + smask_t skip_mask = smask_t::scales_runtime; + if (sum_support) skip_mask = skip_mask | smask_t::post_ops; + if (!attr->has_default_values(skip_mask)) return false; + if (sum_support) simple_po_check(attr); + if (many_scales_support) return true; + int src_mask, dst_mask; + if (get_scales_mask(attr, &src_mask, &dst_mask) != status::success) + return false; + return src_mask == 0 && dst_mask == 0; +} +} // namespace + +/* specific reorders: implementation */ +template +struct simple_reorder_impl::type> { + static bool is_applicable(const memory_desc_wrapper &input_d, + const memory_desc_wrapper &output_d, const primitive_attr_t *attr) { + using namespace data_type; + using namespace utils; + + if (input_d.has_runtime_dims_or_strides()) return false; + + int src_scales_mask, dst_scales_mask; + auto status = get_scales_mask(attr, &src_scales_mask, &dst_scales_mask); + if (status != status::success) return false; + int scales_mask = std::max(src_scales_mask, dst_scales_mask); + + static constexpr bool w_groups = one_of( + tag_o, format_tag::wigo, format_tag::hwigo, format_tag::dhwigo); + + const bool req_comp = output_d.extra().flags + & memory_extra_flags::compensation_conv_s8s8; + const bool req_asymmetric_comp = output_d.extra().flags + & memory_extra_flags::compensation_conv_asymmetric_src; + + auto mask_ok = [&](bool check, int mask) { + return IMPLICATION(check, mask == (w_groups ? 0x3 : 0x1)); + }; + + return simple_attr_check(attr, true, false) + && output_d.matches_tag(tag_o) && input_d.is_plain() + && (req_comp || req_asymmetric_comp) + && mask_ok(req_comp, output_d.extra().compensation_mask) + && mask_ok(req_asymmetric_comp, + output_d.extra().asymm_compensation_mask) + && IMPLICATION(!w_groups, one_of(scales_mask, 0, 0x1)) + && IMPLICATION(w_groups, one_of(scales_mask, 0, 0x3)) + && one_of(input_d.data_type(), f32, s8, bf16) + && output_d.data_type() == s8; + } + + GET_SCRATCHPAD_SIZE_ZERO(); + + static status_t execute(const cpu_reorder_pd_t *pd, const exec_ctx_t &ctx) { + DECLARE_COMMON_PARAMS(); + + static constexpr bool w_groups = utils::one_of( + tag_o, format_tag::wigo, format_tag::hwigo, format_tag::dhwigo); + static constexpr bool w_height + = !utils::one_of(tag_o, format_tag::wio, format_tag::wigo); + static constexpr bool w_depth + = utils::one_of(tag_o, format_tag::dhwio, format_tag::dhwigo); + + const auto &dims = input_d.dims(); + + const dim_t G = w_groups ? dims[0] : 1; + const dim_t OC = dims[w_groups + 0]; + const dim_t IC = dims[w_groups + 1]; + const dim_t D = w_depth ? dims[w_groups + 2] : 1; + const dim_t H = w_height ? dims[w_groups + w_depth + 2] : 1; + const dim_t W = dims[w_groups + w_depth + w_height + 2]; + + const bool req_comp = output_d.extra().flags + & memory_extra_flags::compensation_conv_s8s8; + const bool has_asymmetric_comp = output_d.extra().flags + & memory_extra_flags::compensation_conv_asymmetric_src; + + assert(req_comp || has_asymmetric_comp); + + float adj_scale + = (output_d.extra().flags & memory_extra_flags::scale_adjust) + ? output_d.extra().scale_adjust + : 1.f; + + size_t offset = output_d.size() - output_d.additional_buffer_size(); + size_t comp_size = output_d.additional_buffer_size( + memory_extra_flags::compensation_conv_s8s8); + size_t zp_offset = offset + (req_comp ? comp_size : 0); + int32_t *cp = req_comp ? reinterpret_cast(output + offset) + : nullptr; + int32_t *zp = has_asymmetric_comp + ? reinterpret_cast(output + zp_offset) + : nullptr; + + const bool per_oc = scales_mask & (1 << (w_groups + 0)); + const bool per_ic = scales_mask & (1 << (w_groups + 1)); + const size_t ic_stride = per_ic ? 1 : 0; + const size_t oc_stride = per_oc ? per_ic ? IC : 1 : 0; + + parallel_nd(G, OC, [&](dim_t g, dim_t oc) { + if (req_comp) cp[g * OC + oc] = 0; + if (has_asymmetric_comp) zp[g * OC + oc] = 0; + for_(dim_t ic = 0; ic < IC; ic++) + for_(dim_t d = 0; d < D; d++) + for_(dim_t h = 0; h < H; h++) + for (dim_t w = 0; w < W; w++) { + auto i = w_depth + ? input[input_d.blk_off(g, oc, ic, d, h, w)] + : w_height + ? input[input_d.blk_off(g, oc, ic, h, w)] + : input[input_d.blk_off(g, oc, ic, w)]; + auto &o = w_depth ? output[output_d.blk_off( + g, oc, ic, d, h, w)] + : w_height + ? output[output_d.blk_off(g, oc, ic, h, w)] + : output[output_d.blk_off(g, oc, ic, w)]; + const size_t os_off + = (g * OC + oc) * oc_stride + ic * ic_stride; + const float s = src_scales[src_scales_mask == 0 ? 0 : os_off]; + const float d = dst_scales[dst_scales_mask == 0 ? 0 : os_off]; + + o = qz_b0, data_t>()( + i, s * adj_scale * d); + if (req_comp) cp[g * OC + oc] -= (int32_t)o; + if (has_asymmetric_comp) zp[g * OC + oc] -= (int32_t)o; + } + if (req_comp) cp[g * OC + oc] *= 128; + }); + return status::success; + } +}; + +template +struct simple_reorder_impl::type> { + static bool is_applicable(const memory_desc_wrapper &input_d, + const memory_desc_wrapper &output_d, const primitive_attr_t *attr) { + using namespace format_tag; + using namespace data_type; + using namespace utils; + + if (input_d.has_runtime_dims_or_strides()) return false; + + int src_scales_mask, dst_scales_mask; + auto status = get_scales_mask(attr, &src_scales_mask, &dst_scales_mask); + if (status != status::success) return false; + int scales_mask = std::max(src_scales_mask, dst_scales_mask); + + const bool w_groups = !one_of(tag_o, OIw4i16o4i, OIw2i8o4i, OIw4o4i, + OIhw4i16o4i, OIhw2i8o4i, OIhw4o4i, OIdhw4i16o4i, OIdhw2i8o4i, + OIdhw4o4i, OI4i16o4i, OI4i32o4i, OI4i64o4i, OIw4i32o4i, + OIw4i64o4i, OIhw4i32o4i, OIhw4i64o4i, OIdhw4i32o4i, + OIdhw4i64o4i); + + const bool req_comp = output_d.extra().flags + & memory_extra_flags::compensation_conv_s8s8; + const bool req_asymmetric_comp = output_d.extra().flags + & memory_extra_flags::compensation_conv_asymmetric_src; + + auto mask_ok = [&](bool check, int mask) { + return IMPLICATION(check, mask == (w_groups ? 0x3 : 0x1)); + }; + + return simple_attr_check(attr, true, false) + && input_d.matches_tag(tag_i) && output_d.matches_tag(tag_o) + && (req_comp || req_asymmetric_comp) + && mask_ok(req_comp, output_d.extra().compensation_mask) + && mask_ok(req_asymmetric_comp, + output_d.extra().asymm_compensation_mask) + && IMPLICATION(!w_groups, one_of(scales_mask, 0, 0x1)) + && IMPLICATION(w_groups, one_of(scales_mask, 0, 0x3)) + && one_of(input_d.data_type(), f32, s8, bf16) + && output_d.data_type() == s8; + } + + GET_SCRATCHPAD_SIZE_ZERO(); + + static status_t execute(const cpu_reorder_pd_t *pd, const exec_ctx_t &ctx) { + DECLARE_COMMON_PARAMS(); + using namespace format_tag; + + static constexpr bool w_groups = !utils::one_of(tag_o, OIw4o4i, + OIw4i16o4i, OIhw4i16o4i, OIdhw4i16o4i, OIhw4o4i, OIw2i8o4i, + OIhw2i8o4i, OIdhw2i8o4i, OIdhw4o4i, OI4i16o4i, OI4i32o4i, + OI4i64o4i, OIw4i32o4i, OIw4i64o4i, OIhw4i32o4i, OIhw4i64o4i, + OIdhw4i32o4i, OIdhw4i64o4i); + + constexpr int is_0d + = utils::one_of(tag_o, OI4i16o4i, OI4i32o4i, OI4i64o4i); + constexpr int is_1d + = utils::one_of(tag_o, gOIw4i16o4i, OIw4i16o4i, gOIw2i8o4i, + OIw2i8o4i, gOIw4o4i, OIw4o4i, OIw4i32o4i, OIw4i64o4i); + constexpr int is_3d = utils::one_of(tag_o, gOIdhw4i16o4i, OIdhw4i16o4i, + gOIdhw2i8o4i, OIdhw2i8o4i, gOIdhw4o4i, OIdhw4o4i, OIdhw4i32o4i, + OIdhw4i64o4i); + constexpr dim_t icblksize = utils::one_of(tag_traits::inner_blks, + ib::_4a4b, ib::_4b4c) + ? 4 + : utils::one_of(tag_traits::inner_blks, ib::_2c8b4c, + ib::_2b8a4b) + ? 8 + : 16; + constexpr dim_t ocblksize + = tag_traits::inner_blks == ib::_4b32a4b ? 32 + : tag_traits::inner_blks == ib::_4b64a4b ? 64 + : icblksize; + + const auto &plain_d = order_keep ? input_d : output_d; + const auto &dims = input_d.dims(); + const int ndims = input_d.ndims(); + const auto &pdims + = order_keep ? output_d.padded_dims() : input_d.padded_dims(); + + const dim_t G = w_groups ? dims[0] : 1; + const dim_t OC = dims[w_groups + 0]; + const dim_t PADDED_OC = pdims[w_groups + 0]; + const dim_t NB_OC = pdims[w_groups + 0] / ocblksize; + const dim_t IC = dims[w_groups + 1]; + const dim_t NB_IC = pdims[w_groups + 1] / icblksize; + const dim_t D = is_3d ? dims[2 + w_groups] : 1; + const dim_t H = is_1d || is_0d ? 1 : dims[2 + w_groups + is_3d]; + const dim_t W = is_0d ? 1 : dims[w_groups + is_3d + 3 - is_1d]; + + // XXX: Currently user can pass a mask that has non-zero values in + // dimensions that do not exist in a md. Since attributes are created + // separately mask can't be validated. + // This line truncates a given mask in range [0, 1 << ndims - 1] + // TODO: Such masks can be either prohibited at pd creation step at + // API level or checked by each implementation that relies on it. + scales_mask &= (1 << ndims) - 1; + + const bool req_comp = output_d.extra().flags + & memory_extra_flags::compensation_conv_s8s8; + const bool has_asymmetric_comp = output_d.extra().flags + & memory_extra_flags::compensation_conv_asymmetric_src; + + assert(req_comp || has_asymmetric_comp); + + float adj_scale + = (output_d.extra().flags & memory_extra_flags::scale_adjust) + ? output_d.extra().scale_adjust + : 1.f; + + const bool per_oc = scales_mask & (1 << (w_groups + 0)); + const bool per_ic = scales_mask & (1 << (w_groups + 1)); + const size_t ic_stride = per_ic ? 1 : 0; + const size_t oc_stride = per_oc ? per_ic ? IC : 1 : 0; + const size_t nb_ic_stride = (per_ic ? 1 : 0) * icblksize; + const size_t nb_oc_stride = (per_oc ? per_ic ? IC : 1 : 0) * ocblksize; + + // This kernel is used primarily for tensors with multiple inner + // blocks for which generic zero padding must be used. + // TODO: apply zero padding inside parallel_nd() + ctx.zero_pad_output(DNNL_ARG_TO); + + auto ker = [&](const data_t *inp, data_t *out, + int32_t *c, int32_t *zp, const float *s, + const float *d, const dim_t oc_block, + const dim_t ic_block) { +#define index AB_or_BC_blk_off::inner_blks> + for_(dim_t ic = 0; ic < ic_block; ++ic) + for (dim_t oc = 0; oc < oc_block; ++oc) { + const auto plain_off + = oc * plain_d.blocking_desc().strides[w_groups + 0] + + ic * plain_d.blocking_desc().strides[w_groups + 1]; + const size_t os_off = oc * oc_stride + ic * ic_stride; + const float src_scale = s[src_scales_mask == 0 ? 0 : os_off]; + const float dst_scale = d[dst_scales_mask == 0 ? 0 : os_off]; + out[index(oc, ic)] = qz_b0, data_t>()( + inp[plain_off], src_scale * adj_scale * dst_scale); + if (req_comp) c[oc] -= (128 * (int32_t)(out[index(oc, ic)])); + if (has_asymmetric_comp) + zp[oc] -= (int32_t)(out[index(oc, ic)]); + } +#undef index + }; + + constexpr dim_t i_mult_ic = icblksize; + constexpr dim_t i_mult_oc = ocblksize; + constexpr dim_t o_mult = 1; + + size_t offset = output_d.size() - output_d.additional_buffer_size(); + size_t comp_size = output_d.additional_buffer_size( + memory_extra_flags::compensation_conv_s8s8); + size_t zp_offset = offset + (req_comp ? comp_size : 0); + int32_t *cp = req_comp ? reinterpret_cast(output + offset) + : nullptr; + int32_t *zp = has_asymmetric_comp + ? reinterpret_cast(output + zp_offset) + : nullptr; + + parallel_nd(G * PADDED_OC, [&](dim_t i) { + if (req_comp) cp[i] = 0; + if (has_asymmetric_comp) zp[i] = 0; + }); + +#define wei_blk_off(md, g, o, i, d, h, w) \ + (is_0d ? (md).blk_off(g, o, i) \ + : is_1d ? (md).blk_off(g, o, i, w) \ + : is_3d ? (md).blk_off(g, o, i, d, h, w) \ + : (md).blk_off(g, o, i, h, w)) + parallel_nd(G, NB_OC, [&](dim_t g, dim_t O) { + for_(dim_t I = 0; I < NB_IC; I++) + for_(dim_t d = 0; d < D; d++) + for_(dim_t h = 0; h < H; h++) + for (dim_t w = 0; w < W; w++) { + auto i = &input[wei_blk_off( + input_d, g, i_mult_oc * O, i_mult_ic * I, d, h, w)]; + auto o = &output[wei_blk_off( + output_d, g, o_mult * O, o_mult * I, d, h, w)]; + const dim_t oc_block = nstl::min(ocblksize, OC - O * ocblksize); + const dim_t ic_block = nstl::min(icblksize, IC - I * icblksize); + dim_t _offset = (g * NB_OC + O) * ocblksize; + dim_t os_nb_off + = (g * NB_OC + O) * nb_oc_stride + I * nb_ic_stride; + const float *src_scales_ptr + = &src_scales[src_scales_mask == 0 ? 0 : os_nb_off]; + const float *dst_scales_ptr + = &dst_scales[dst_scales_mask == 0 ? 0 : os_nb_off]; + ker(i, o, (order_keep && req_comp) ? &cp[_offset] : nullptr, + (order_keep && has_asymmetric_comp) ? &zp[_offset] + : nullptr, + src_scales_ptr, dst_scales_ptr, oc_block, ic_block); + } + }); + +#undef wei_blk_off + + return status::success; + } +}; + +/* Asymmetric Blocking */ +template +struct simple_reorder_impl::type> { + static bool is_applicable(const memory_desc_wrapper &input_d, + const memory_desc_wrapper &output_d, const primitive_attr_t *attr) { + using namespace format_tag; + using namespace data_type; + using namespace utils; + + if (input_d.has_runtime_dims_or_strides()) return false; + + const bool w_groups = !one_of(tag_o, Owi16o, Owhi16o); + + // Current formats are only used in jit kernels that natively + // support s8 instructions, hence, there is no need for signed + // compensation. + const bool req_comp = output_d.extra().flags + & memory_extra_flags::compensation_conv_s8s8; + + const bool req_asymmetric_comp = output_d.extra().flags + & memory_extra_flags::compensation_conv_asymmetric_src; + + auto mask_ok = [&](bool check, int mask) { + const int c_mask = 0x1, + g_mask = 0x3; // mask for i/o-channel and ngroups + return IMPLICATION(check, mask == (w_groups ? g_mask : c_mask)); + }; + + return simple_attr_check(attr, true, false) + && input_d.matches_tag(tag_i) && output_d.matches_tag(tag_o) + && mask_ok(req_asymmetric_comp, + output_d.extra().asymm_compensation_mask) + && one_of(input_d.data_type(), f32, s8, bf16) + && output_d.data_type() == s8 && !req_comp; + } + + GET_SCRATCHPAD_SIZE_ZERO(); + + static status_t execute(const cpu_reorder_pd_t *pd, const exec_ctx_t &ctx) { + DECLARE_COMMON_PARAMS(); + using namespace format_tag; + + static constexpr bool w_groups = !utils::one_of(tag_o, Owi16o, Owhi16o); + constexpr int is_1d = utils::one_of(tag_o, Owi16o, gOwi16o); + const bool is_3d = false; // TODO once enabled + + constexpr dim_t oc_blksize = 16; + + const auto &plain_d = order_keep ? input_d : output_d; + const auto &dims = input_d.dims(); + const auto &pdims + = order_keep ? output_d.padded_dims() : input_d.padded_dims(); + + const dim_t G = w_groups ? dims[0] : 1; + const dim_t OC = dims[w_groups + 0]; + const dim_t NB_OC = pdims[w_groups + 0] / oc_blksize; + const dim_t IC = dims[w_groups + 1]; + + const dim_t D = is_3d ? dims[2 + w_groups] : 1; + const dim_t H = is_1d ? 1 : dims[2 + w_groups + is_3d]; + const dim_t W = dims[w_groups + is_3d + 3 - is_1d]; + + const bool has_asymmetric_comp = output_d.extra().flags + & memory_extra_flags::compensation_conv_asymmetric_src; + + float adj_scale + = (output_d.extra().flags & memory_extra_flags::scale_adjust) + ? output_d.extra().scale_adjust + : 1.f; + + auto ker = [&](const data_t *inp, data_t *out, + int32_t *zp, const float *s, const float *d, + const dim_t oc_block) { + for (dim_t oc = 0; oc < oc_block; ++oc) { + const auto plain_off + = oc * plain_d.blocking_desc().strides[w_groups + 0]; + out[oc] = qz_b0, data_t>()( + inp[plain_off], s[oc] * adj_scale * d[oc]); + if (has_asymmetric_comp) zp[oc] -= (int32_t)(out[oc]); + } + // fill memory with '0' in case of padded channel dimensions + for (dim_t oc = oc_block; oc < oc_blksize; ++oc) { + out[oc] = 0; + } + }; + + size_t offset = output_d.size() - output_d.additional_buffer_size(); + int32_t *zp = has_asymmetric_comp + ? reinterpret_cast(output + offset) + : nullptr; + + if (has_asymmetric_comp) { + parallel_nd(G * NB_OC * oc_blksize, [&](dim_t i) { zp[i] = 0; }); + } + +#define wei_blk_off(md, g, o, i, d, h, w) \ + (is_1d ? (md).blk_off(g, o, i, w) \ + : is_3d ? (md).blk_off(g, o, i, d, h, w) \ + : (md).blk_off(g, o, i, h, w)) + + parallel_nd(G, NB_OC, [&](dim_t g, dim_t O) { + for_(dim_t I = 0; I < IC; I++) + for_(dim_t d = 0; d < D; d++) + for_(dim_t h = 0; h < H; h++) + for (dim_t w = 0; w < W; w++) { + auto i = &input[wei_blk_off( + input_d, g, oc_blksize * O, I, d, h, w)]; + auto o = &output[wei_blk_off(output_d, g, O, I, d, h, w)]; + const dim_t oc_block + = nstl::min(oc_blksize, OC - O * oc_blksize); + dim_t _offset = (g * NB_OC + O) * oc_blksize; + int32_t *zp_ptr = (order_keep && has_asymmetric_comp) + ? &zp[_offset] + : nullptr; + const float *src_scales_ptr + = &src_scales[src_scales_mask == 0 ? 0 : _offset]; + const float *dst_scales_ptr + = &dst_scales[dst_scales_mask == 0 ? 0 : _offset]; + ker(i, o, zp_ptr, src_scales_ptr, dst_scales_ptr, oc_block); + } + }); + +#undef wei_blk_off + + return status::success; + } +}; + +/* Asymmetric Blocking */ +template +struct simple_reorder_impl::type> { + static bool is_applicable(const memory_desc_wrapper &input_d, + const memory_desc_wrapper &output_d, const primitive_attr_t *attr) { + using namespace format_tag; + using namespace data_type; + using namespace utils; + + if (input_d.has_runtime_dims_or_strides()) return false; + + int src_scales_mask, dst_scales_mask; + auto status = get_scales_mask(attr, &src_scales_mask, &dst_scales_mask); + if (status != status::success) return false; + int scales_mask = std::max(src_scales_mask, dst_scales_mask); + + const bool w_groups = !one_of(tag_o, OwI16o4i, OIw16i16o4i, OhwI16o4i, + OIhw16i16o4i, OdhwI16o4i, OIdhw16i16o4i); + + // Current formats are only used in jit kernels that natively + // support s8 instructions, hence, there is no need for signed + // compensation. + const bool req_comp = output_d.extra().flags + & memory_extra_flags::compensation_conv_s8s8; + + const bool req_asymmetric_comp = output_d.extra().flags + & memory_extra_flags::compensation_conv_asymmetric_src; + + auto mask_ok = [&](bool check, int mask) { + const int c_mask = 0x1, + g_mask = 0x3; // mask for o-channel and ngroups + return IMPLICATION(check, mask == (w_groups ? g_mask : c_mask)); + }; + + return simple_attr_check(attr, true, false) + && input_d.matches_tag(tag_i) && output_d.matches_tag(tag_o) + && mask_ok(req_asymmetric_comp, + output_d.extra().asymm_compensation_mask) + && one_of(input_d.data_type(), f32, s8, bf16) + && IMPLICATION(!w_groups, one_of(scales_mask, 0, 0x1)) + && IMPLICATION(w_groups, one_of(scales_mask, 0, 0x3)) + && output_d.data_type() == s8 && !req_comp; + } + + GET_SCRATCHPAD_SIZE_ZERO(); + + static status_t execute(const cpu_reorder_pd_t *pd, const exec_ctx_t &ctx) { + DECLARE_COMMON_PARAMS(); + using namespace format_tag; + + static constexpr bool w_groups + = !utils::one_of(tag_o, OwI16o4i, OIw16i16o4i, OhwI16o4i, + OIhw16i16o4i, OdhwI16o4i, OIdhw16i16o4i); + constexpr int is_1d = utils::one_of( + tag_o, OwI16o4i, gOwI16o4i, OIw16i16o4i, gOIw16i16o4i); + const bool is_3d = utils::one_of( + tag_o, OdhwI16o4i, gOdhwI16o4i, OIdhw16i16o4i, gOIdhw16i16o4i); + + constexpr dim_t oc_blksize = 16; + constexpr dim_t ic_blksize + = utils::one_of(tag_traits::inner_blks, ib::_16b16a4b, + ib::_16c16b4c) + ? 64 + : utils::one_of( + tag_traits::inner_blks, ib::_16a4b, ib::_16b4c) + ? 4 + : 1; + assert(ic_blksize != 1); + + const auto &plain_d = order_keep ? input_d : output_d; + const auto &dims = input_d.dims(); + const auto &pdims + = order_keep ? output_d.padded_dims() : input_d.padded_dims(); + + const dim_t G = w_groups ? dims[0] : 1; + const dim_t OC = dims[w_groups + 0]; + const dim_t NB_OC = pdims[w_groups + 0] / oc_blksize; + const dim_t IC = dims[w_groups + 1]; + const dim_t NB_IC = pdims[w_groups + 1] / ic_blksize; + + const dim_t D = is_3d ? dims[2 + w_groups] : 1; + const dim_t H = is_1d ? 1 : dims[2 + w_groups + is_3d]; + const dim_t W = dims[w_groups + is_3d + 3 - is_1d]; + + const bool has_asymmetric_comp = output_d.extra().flags + & memory_extra_flags::compensation_conv_asymmetric_src; + + float adj_scale + = (output_d.extra().flags & memory_extra_flags::scale_adjust) + ? output_d.extra().scale_adjust + : 1.f; + + // This kernel is used primarily for tensors with multiple inner + // blocks for which generic zero padding must be used. + // TODO: apply zero padding inside parallel_nd() + ctx.zero_pad_output(DNNL_ARG_TO); + + auto ker = [&](const data_t *inp, data_t *out, + int32_t *zp, const float *s, const float *d, + const dim_t oc_block, const dim_t ic_block) { + for_(dim_t ic = 0; ic < ic_block; ++ic) + for (dim_t oc = 0; oc < oc_block; ++oc) { + const auto plain_off + = oc * plain_d.blocking_desc().strides[w_groups + 0] + + ic * plain_d.blocking_desc().strides[w_groups + 1]; + auto index = AB_or_BC_blk_off::inner_blks>( + oc, ic); + out[index] = qz_b0, data_t>()( + inp[plain_off], s[oc] * adj_scale * d[oc]); + + if (has_asymmetric_comp) zp[oc] -= (int32_t)(out[index]); + } + }; + + size_t offset = output_d.size() - output_d.additional_buffer_size(); + int32_t *zp = has_asymmetric_comp + ? reinterpret_cast(output + offset) + : nullptr; + + if (has_asymmetric_comp) { + parallel_nd(G * NB_OC * oc_blksize, [&](dim_t i) { zp[i] = 0; }); + } + +#define wei_blk_off(md, g, o, i, d, h, w) \ + (is_1d ? (md).blk_off(g, o, i, w) \ + : is_3d ? (md).blk_off(g, o, i, d, h, w) \ + : (md).blk_off(g, o, i, h, w)) + + parallel_nd(G, NB_OC, [&](dim_t g, dim_t O) { + for_(dim_t I = 0; I < NB_IC; I++) + for_(dim_t d = 0; d < D; d++) + for_(dim_t h = 0; h < H; h++) + for (dim_t w = 0; w < W; w++) { + auto i = &input[wei_blk_off( + input_d, g, oc_blksize * O, ic_blksize * I, d, h, w)]; + auto o = &output[wei_blk_off(output_d, g, O, I, d, h, w)]; + const dim_t oc_block + = nstl::min(oc_blksize, OC - O * oc_blksize); + const dim_t ic_block + = nstl::min(ic_blksize, IC - I * ic_blksize); + dim_t _offset = (g * NB_OC + O) * oc_blksize; + int32_t *zp_ptr = (order_keep && has_asymmetric_comp) + ? &zp[_offset] + : nullptr; + const float *src_scales_ptr + = &src_scales[src_scales_mask == 0 ? 0 : _offset]; + const float *dst_scales_ptr + = &dst_scales[dst_scales_mask == 0 ? 0 : _offset]; + ker(i, o, zp_ptr, src_scales_ptr, dst_scales_ptr, oc_block, + ic_block); + } + }); + +#undef wei_blk_off + + return status::success; + } +}; + +template +struct simple_reorder_impl::type> { + static bool is_applicable(const memory_desc_wrapper &input_d, + const memory_desc_wrapper &output_d, const primitive_attr_t *attr) { + using namespace format_tag; + using namespace data_type; + using namespace utils; + + if (input_d.has_runtime_dims_or_strides()) return false; + + const bool req_comp = output_d.extra().flags + & memory_extra_flags::compensation_conv_s8s8; + const bool req_asymmetric_comp = output_d.extra().flags + & memory_extra_flags::compensation_conv_asymmetric_src; + + const auto ndims = input_d.ndims(); + auto mask_ok = [&](bool check, int mask) { + return IMPLICATION( + check, mask == (1 << ndims) - 1 - (1 << (ndims - 2))); + }; + + int src_scales_mask, dst_scales_mask; + auto status = get_scales_mask(attr, &src_scales_mask, &dst_scales_mask); + if (status != status::success) return false; + int scales_mask = std::max(src_scales_mask, dst_scales_mask); + const size_t D_mask + = array_product(input_d.dims(), math::ilog2q(scales_mask + 1)); + + return simple_attr_check(attr, true, false) + && input_d.matches_tag(tag_i) && output_d.matches_tag(tag_o) + && mask_ok(req_comp, output_d.extra().compensation_mask) + && mask_ok(req_asymmetric_comp, + output_d.extra().asymm_compensation_mask) + && one_of(input_d.data_type(), f32, s8, bf16, f16) + && output_d.data_type() == s8 && D_mask == 1; + } + + GET_SCRATCHPAD_SIZE_ZERO(); + + static status_t execute(const cpu_reorder_pd_t *pd, const exec_ctx_t &ctx) { + DECLARE_COMMON_PARAMS(); + using namespace format_tag; + + // {[batch_dim][d0][d1], [batch_dim][d1][d0]} -> [batch_dim][D1][D0][16][D1_blksize][4] + // 2D: batch_dim - none, d0 <-> a, d1 <-> b + // 3D: batch_dim <-> a, d0 <-> b, d1 <-> c + constexpr dim_t D0_blksize = 64; + constexpr dim_t D1_blksize + = (utils::one_of(tag_traits::inner_blks, ib::_16a64b4a, + ib::_16b64c4b)) + ? 64 + : (utils::one_of(tag_traits::inner_blks, ib::_16a48b4a, + ib::_16b48c4b)) + ? 48 + : (utils::one_of(tag_traits::inner_blks, ib::_16a32b4a, + ib::_16b32c4b)) + ? 32 + : (utils::one_of(tag_traits::inner_blks, ib::_16a16b4a, + ib::_16b16c4b)) + ? 16 + : 1; + assert(D1_blksize != 1); + + const auto &plain_d = order_keep ? input_d : output_d; + const auto &dims = input_d.dims(); + const auto ndims = input_d.ndims(); + const auto &pdims + = order_keep ? output_d.padded_dims() : input_d.padded_dims(); + + const dim_t batch_dim = ndims > 2 ? dims[ndims - 3] : 1; + const dim_t D0dim = dims[ndims - 2]; + const dim_t NB_D0dim = pdims[ndims - 2] / D0_blksize; + const dim_t D1dim = dims[ndims - 1]; + const dim_t NB_D1dim = pdims[ndims - 1] / D1_blksize; + assert(pdims[ndims - 1] == NB_D1dim * D1_blksize); + + const bool req_comp = output_d.extra().flags + & memory_extra_flags::compensation_conv_s8s8; + const bool has_asymmetric_comp = output_d.extra().flags + & memory_extra_flags::compensation_conv_asymmetric_src; + + float adj_scale + = (output_d.extra().flags & memory_extra_flags::scale_adjust) + ? output_d.extra().scale_adjust + : 1.f; + + auto ker = [&](const data_t *inp, data_t *out, + int32_t *cp, int32_t *zp, const float *s, + const float *d, const int d0_block, + const int d1_block) { + for (int d0 = 0; d0 < d0_block; ++d0) { + for (int d1 = 0; d1 < d1_block; ++d1) { + const auto plain_off + = d0 * plain_d.blocking_desc().strides[ndims - 2] + + d1 * plain_d.blocking_desc().strides[ndims - 1]; + auto index + = AB_or_BC_blk_off::inner_blks>( + d0, d1); + out[index] = qz_b0, data_t>()( + inp[plain_off], s[0] * adj_scale * d[0]); + + auto o = static_cast(out[index]); + if (req_comp) cp[d1] -= (128 * o); + if (has_asymmetric_comp) zp[d1] -= o; + } + for (int d1 = d1_block; d1 < D1_blksize; ++d1) { + auto index + = AB_or_BC_blk_off::inner_blks>( + d0, d1); + out[index] = qz_b0, data_t>()( + 0, s[0] * adj_scale * d[0]); + } + } + + for_(int d0 = d0_block; d0 < D0_blksize; ++d0) + for (int d1 = 0; d1 < D1_blksize; ++d1) { + auto index = AB_or_BC_blk_off::inner_blks>( + d0, d1); + out[index] = qz_b0, data_t>()( + 0, s[0] * adj_scale * d[0]); + } + }; + + const auto w_d = order_keep ? output_d : input_d; + size_t offset = w_d.size() - w_d.additional_buffer_size(); + size_t comp_size = output_d.additional_buffer_size( + memory_extra_flags::compensation_conv_s8s8); + size_t zp_offset = offset + (req_comp ? comp_size : 0); + int32_t *cp = req_comp ? reinterpret_cast(output + offset) + : nullptr; + int32_t *zp = has_asymmetric_comp + ? reinterpret_cast(output + zp_offset) + : nullptr; + + if (has_asymmetric_comp || req_comp) { + parallel_nd(batch_dim * NB_D1dim * D1_blksize, [&](dim_t i) { + if (req_comp) cp[i] = 0; + if (has_asymmetric_comp) zp[i] = 0; + }); + } + +#define get_blk_off(md, batch, d0, d1) \ + (ndims == 3 ? (md).blk_off((batch), (d0), (d1)) : (md).blk_off((d0), (d1))) + + parallel_nd(batch_dim, NB_D1dim, [&](dim_t batch, dim_t D1) { + for (int D0 = 0; D0 < NB_D0dim; D0++) { + auto i = &input[get_blk_off( + input_d, batch, D0_blksize * D0, D1_blksize * D1)]; + auto o = &output[get_blk_off(output_d, batch, D0, D1)]; + const dim_t d0_block + = nstl::min(D0_blksize, D0dim - D0 * D0_blksize); + const dim_t d1_block + = nstl::min(D1_blksize, D1dim - D1 * D1_blksize); + dim_t _offset = batch * NB_D1dim * D1_blksize + D1 * D1_blksize; + int32_t *zp_ptr = (order_keep && has_asymmetric_comp) + ? &zp[_offset] + : nullptr; + const float *src_scales_ptr + = &src_scales[src_scales_mask == 0 ? 0 : _offset]; + const float *dst_scales_ptr + = &dst_scales[dst_scales_mask == 0 ? 0 : _offset]; + ker(i, o, (order_keep && req_comp) ? &cp[_offset] : nullptr, + zp_ptr, src_scales_ptr, dst_scales_ptr, d0_block, + d1_block); + } + }); + +#undef get_blk_off + + return status::success; + } +}; + +template +struct simple_reorder_impl::type> { + static bool is_applicable(const memory_desc_wrapper &input_d, + const memory_desc_wrapper &output_d, const primitive_attr_t *attr) { + using namespace data_type; + using namespace utils; + + if (input_d.has_runtime_dims_or_strides()) return false; + + int src_scales_mask, dst_scales_mask; + auto status = get_scales_mask(attr, &src_scales_mask, &dst_scales_mask); + if (status != status::success) return false; + int scales_mask = std::max(src_scales_mask, dst_scales_mask); + + const dim_t g = input_d.dims()[0]; + const dim_t oc = input_d.dims()[1]; + const dim_t ic = input_d.dims()[2]; + + const bool req_comp = output_d.extra().flags + & memory_extra_flags::compensation_conv_s8s8; + const bool req_asymmetric_comp = output_d.extra().flags + & memory_extra_flags::compensation_conv_asymmetric_src; + int s8s8_comp_mask = output_d.extra().compensation_mask; + int zp_comp_mask = output_d.extra().asymm_compensation_mask; + int comp_mask = std::max(s8s8_comp_mask, zp_comp_mask); + + const size_t D_mask + = array_product(input_d.dims(), math::ilog2q(comp_mask + 1)); + + return order_keep && oc == 1 && ic == 1 // depth-wise case + && simple_attr_check(attr, true, false) + && (req_comp || req_asymmetric_comp) + && IMPLICATION(req_comp && req_asymmetric_comp, + output_d.extra().compensation_mask + == output_d.extra().asymm_compensation_mask) + && input_d.matches_tag(tag_i) && output_d.matches_tag(tag_o) + && IMPLICATION( + req_comp, one_of(D_mask, (size_t)1, (size_t)g * oc)) + && one_of(scales_mask, 0, 0x3) + && one_of(input_d.data_type(), f32, s8, bf16) + && output_d.data_type() == s8; + } + + GET_SCRATCHPAD_SIZE_ZERO(); + + static status_t execute(const cpu_reorder_pd_t *pd, const exec_ctx_t &ctx) { + DECLARE_COMMON_PARAMS(); + + constexpr bool is_1d + = utils::one_of(tag_i, format_tag::goiw, format_tag::wigo); + constexpr dim_t blksize + = utils::one_of(tag_o, format_tag::Goihw4g, format_tag::Goiw4g) + ? 4 + : utils::one_of(tag_o, format_tag::Goihw8g, format_tag::Goiw8g) + ? 8 + : 16; + + const auto &dims = input_d.dims(); + const auto &pdims = output_d.padded_dims(); + const dim_t G = dims[0]; + const dim_t Gp = pdims[0]; + const dim_t OC = dims[1]; + const dim_t IC = dims[2]; + const dim_t H = is_1d ? 1 : dims[3]; + const dim_t W = dims[4 - is_1d]; + const bool zero_padding_needed = !output_d.is_dense(); + + const bool req_comp = output_d.extra().flags + & memory_extra_flags::compensation_conv_s8s8; + const bool has_asymmetric_comp = output_d.extra().flags + & memory_extra_flags::compensation_conv_asymmetric_src; + + assert(req_comp || has_asymmetric_comp); + + float adj_scale + = (output_d.extra().flags & memory_extra_flags::scale_adjust) + ? output_d.extra().scale_adjust + : 1.f; + + auto ker_out = [&](const data_t *inp, data_t *out, + const float *src_scales, const float *dst_scales, + const dim_t g_block) { + PRAGMA_OMP_SIMD() + for (dim_t g = 0; g < g_block; g++) { + const auto i_off = g * input_d.blocking_desc().strides[0]; + const float src_scale + = src_scales[src_scales_mask == 0 ? 0 : g * OC]; + const float dst_scale + = dst_scales[dst_scales_mask == 0 ? 0 : g * OC]; + out[g] = qz_b0, data_t>()( + inp[i_off], src_scale * adj_scale * dst_scale); + } + }; + + /* Note: having separate kernels for s8 and zero-point fixes a + * compiler-generated bug which results in seg-fault. */ + auto ker_s8 = [&](const data_t *out, int32_t *cp, + const dim_t g_block) { + PRAGMA_OMP_SIMD() + for (dim_t g = 0; g < g_block; g++) { + cp[g * OC] -= 128 * (int32_t)(out[g]); + } + }; + auto ker_zp = [&](const data_t *out, int32_t *zp, + const dim_t g_block) { + PRAGMA_OMP_SIMD() + for (dim_t g = 0; g < g_block; g++) { + zp[g * OC] -= (int32_t)(out[g]); + } + }; + + size_t offset = output_d.size() - output_d.additional_buffer_size(); + size_t comp_size = output_d.additional_buffer_size( + memory_extra_flags::compensation_conv_s8s8); + size_t zp_offset = offset + (req_comp ? comp_size : 0); + int32_t *cp = req_comp ? reinterpret_cast(output + offset) + : nullptr; + int32_t *zp = has_asymmetric_comp + ? reinterpret_cast(output + zp_offset) + : nullptr; + + parallel_nd((Gp / blksize) * OC, [&](dim_t ib) { + PRAGMA_OMP_SIMD() + for (dim_t i = 0; i < blksize; i++) { + if (req_comp) cp[ib * blksize + i] = 0; + if (has_asymmetric_comp) zp[ib * blksize + i] = 0; + } + }); + +#define wei_blk_off(md, g, o, i, h, w) \ + (is_1d ? (md).blk_off(g, o, i, w) : (md).blk_off(g, o, i, h, w)) + + parallel_nd(Gp / blksize, OC, [&](dim_t gb, dim_t O) { + for (dim_t I = 0; I < IC; I++) { + for_(dim_t h = 0; h < H; h++) + for (dim_t w = 0; w < W; w++) { + const dim_t g_block = nstl::min(G - gb * blksize, blksize); + const auto inp = &input[wei_blk_off( + input_d, gb * blksize, O, I, h, w)]; + const auto out + = &output[wei_blk_off(output_d, gb, O, I, h, w)]; + dim_t offset = gb * blksize + O; + const float *src_scales_ptr + = &src_scales[src_scales_mask == 0 ? 0 : offset]; + const float *dst_scales_ptr + = &dst_scales[dst_scales_mask == 0 ? 0 : offset]; + + ker_out(inp, out, src_scales_ptr, dst_scales_ptr, g_block); + if (req_comp) ker_s8(out, &cp[offset], g_block); + if (has_asymmetric_comp) ker_zp(out, &zp[offset], g_block); + + if (zero_padding_needed) { + PRAGMA_OMP_SIMD() + for (int off = g_block; off < blksize; off++) + out[off] = 0; + } + } + } + }); + +#undef wei_blk_off + + return status::success; + } +}; + +/* bf16 reorders */ +template +struct simple_reorder_impl::type> { + static bool is_applicable(const memory_desc_wrapper &input_d, + const memory_desc_wrapper &output_d, const primitive_attr_t *attr) { + using namespace data_type; + + if (input_d.has_runtime_dims_or_strides()) return false; + + return order_keep && input_d.matches_tag(tag_i) + && output_d.matches_tag(tag_o) && input_d.data_type() == f32 + && output_d.data_type() == bf16 && attr->has_default_values(); + } + + static size_t get_scratchpad_size(const memory_desc_wrapper &input_d, + const memory_desc_wrapper &output_d) { + const dim_t blksize = 16; + return sizeof(float) * blksize * blksize * dnnl_get_max_threads(); + } + + static status_t execute(const cpu_reorder_pd_t *pd, const exec_ctx_t &ctx) { + DECLARE_COMMON_PARAMS(); + using namespace format_tag; + + static constexpr bool w_groups = tag_i == goihw; + const dim_t blksize = 16; + const int sblk = 2; + + const auto &plain_d = input_d; + const auto &dims = input_d.dims(); + const auto &pdims = output_d.padded_dims(); + + const dim_t G = w_groups ? dims[0] : 1; + const dim_t OC = dims[w_groups + 0]; + const dim_t NB_OC = pdims[w_groups + 0] / blksize; + const dim_t IC = dims[w_groups + 1]; + const dim_t NB_IC = pdims[w_groups + 1] / blksize; + const dim_t H = dims[w_groups + 2]; + const dim_t W = dims[w_groups + 3]; + + const size_t wsp_size = blksize * blksize; + float *wspace = scratchpad.template get( + memory_tracking::names::key_reorder_space); + + auto index = [&](dim_t ic, dim_t oc) -> dim_t { + if (utils::one_of(tag_o, gOIhw16i16o, OIhw16i16o)) + return (ic * blksize + oc); + else if (utils::one_of(tag_o, gOIhw8i16o2i, OIhw8i16o2i)) + return ((ic / sblk) * blksize * sblk + sblk * oc + ic % sblk); + else if (utils::one_of(tag_o, gOIhw8o16i2o, gIOhw8o16i2o, + OIhw8o16i2o, IOhw8o16i2o)) + return ((oc / sblk) * blksize * sblk + sblk * ic + oc % sblk); + else + assert(!"Invalid weight format"); + return dim_t(0); + }; + + auto ker = [&](const data_t *inp, data_t *out, + const dim_t curr_oc_block, const dim_t oc_block, + const dim_t curr_ic_block, const dim_t ic_block) { + dim_t ic = 0; + for (ic = 0; ic < curr_ic_block; ++ic) { + dim_t oc = 0; + for (oc = 0; oc < curr_oc_block; ++oc) { + const auto plain_off + = oc * plain_d.blocking_desc().strides[w_groups + 0] + + ic + * plain_d.blocking_desc() + .strides[w_groups + 1]; + out[index(ic, oc)] = inp[plain_off]; + } + for (/* continue */; oc < oc_block; ++oc) { + out[index(ic, oc)] = (data_t)0; + } + } + for (/* continue */; ic < ic_block; ++ic) { + for (dim_t oc = 0; oc < oc_block; ++oc) { + out[index(ic, oc)] = (data_t)0; + } + } + }; + + constexpr int i_mult = blksize; + constexpr int o_mult = 1; + + parallel_nd_ext(0, G, NB_OC, NB_IC, H, W, + [&](int ithr, int, dim_t g, dim_t O, dim_t I, dim_t h, + dim_t w) { + float *_wspace = wspace + wsp_size * ithr; + auto i = &input[input_d.blk_off( + g, i_mult * O, i_mult * I, h, w)]; + auto o = &output[output_d.blk_off( + g, o_mult * O, o_mult * I, h, w)]; + const dim_t oc_block = nstl::min(blksize, OC - O * blksize); + const dim_t ic_block = nstl::min(blksize, IC - I * blksize); + ker(i, _wspace, oc_block, blksize, ic_block, blksize); + cvt_float_to_bfloat16(o, _wspace, wsp_size); + }); + + return status::success; + } +}; + +template +struct simple_reorder_impl::type> { + static bool is_applicable(const memory_desc_wrapper &input_d, + const memory_desc_wrapper &output_d, const primitive_attr_t *attr) { + using namespace data_type; + + if (input_d.has_runtime_dims_or_strides()) return false; + + return input_d.matches_tag(tag_i) && output_d.matches_tag(tag_o) + && input_d.data_type() == f32 && output_d.data_type() == bf16 + && attr->has_default_values(); + } + + static size_t get_scratchpad_size(const memory_desc_wrapper &input_d, + const memory_desc_wrapper &output_d) { + const size_t blksize = 16; + const size_t W = input_d.dims()[3]; + return sizeof(float) * blksize * W * dnnl_get_max_threads(); + } + + static status_t execute(const cpu_reorder_pd_t *pd, const exec_ctx_t &ctx) { + DECLARE_COMMON_PARAMS(); + + const dim_t blksize = 16; + + const auto &flat_d = input_d; + const auto &dims = input_d.dims(); + const auto &pdims = output_d.padded_dims(); + + const dim_t C = dims[1]; + const dim_t H = dims[2]; + const dim_t W = dims[3]; + + const dim_t wsp_size = W * blksize; + float *wspace = scratchpad.template get( + memory_tracking::names::key_reorder_space); + + auto ker = [&](const data_t *i, data_t *o, + const dim_t curr_c_block, const dim_t c_block) { + for (dim_t w = 0; w < W; ++w) { + dim_t c = 0; + for (c = 0; c < curr_c_block; ++c) { + const ptrdiff_t flat_off = 0 + + c * flat_d.blocking_desc().strides[1] + + w * flat_d.blocking_desc().strides[3]; + o[w * blksize + c] = i[flat_off]; + } + for (/* continue */; c < c_block; ++c) { + o[w * blksize + c] = (data_t)0; + } + } + }; + + constexpr int i_c_mult = blksize; + constexpr int o_c_mult = 1; + + parallel_nd_ext(0, dims[0], pdims[1] / blksize, H, + [&](int ithr, int, dim_t n, dim_t nb_c, dim_t h) { + float *_wspace = wspace + wsp_size * ithr; + auto i = &input[input_d.blk_off(n, i_c_mult * nb_c, h)]; + auto o = &output[output_d.blk_off(n, o_c_mult * nb_c, h)]; + const dim_t c_block + = nstl::min(blksize, C - nb_c * blksize); + ker(i, _wspace, c_block, blksize); + cvt_float_to_bfloat16(o, _wspace, wsp_size); + }); + + return status::success; + } +}; + +/* reorders with tail support */ + +template +struct simple_reorder_impl::type> { + static bool is_applicable(const memory_desc_wrapper &input_d, + const memory_desc_wrapper &output_d, const primitive_attr_t *attr) { + return simple_fmt_check(order_keep, tag_i, tag_o, input_d, output_d) + && simple_attr_check(attr, false, true); + } + + GET_SCRATCHPAD_SIZE_ZERO(); + + static status_t execute(const cpu_reorder_pd_t *pd, const exec_ctx_t &ctx) { + DECLARE_COMMON_PARAMS(); + using namespace format_tag; + + constexpr int is_1d = utils::one_of(tag_i, nCw4c, nCw8c); + constexpr int is_3d = utils::one_of(tag_i, nCdhw4c, nCdhw8c); + + constexpr dim_t blksize_i + = tag_traits::inner_blks == ib::_4b ? 4 : 8; + constexpr dim_t blksize_16 = 16; + + constexpr dim_t ic_mult = order_keep ? blksize_16 / blksize_i : 1; + constexpr dim_t oc_mult = order_keep ? 1 : blksize_16 / blksize_i; + + const auto &dims = input_d.dims(); + const auto &pdims + = order_keep ? output_d.padded_dims() : input_d.padded_dims(); + + const auto &d_i = order_keep ? input_d : output_d; + const auto stride_C_in_blk_i = d_i.blocking_desc().strides[1]; + + const dim_t C = dims[1]; + const dim_t D = is_3d ? dims[2] : 1; + const dim_t H = is_1d ? 1 : dims[2 + is_3d]; + const dim_t W = dims[3 + is_3d - is_1d]; + + auto ker = [&](const data_t *i, data_t *o, + const int block) { + const int nb = utils::div_up(block, blksize_i); + if (alpha == 1.0 && beta == 0.0) { + for (int b = 0; b < nb; ++b) { + const ptrdiff_t i_off + = b * (order_keep ? stride_C_in_blk_i : blksize_i); + const ptrdiff_t o_off + = b * (order_keep ? blksize_i : stride_C_in_blk_i); + const int block_i + = nstl::min(blksize_i, block - b * blksize_i); + for (int c = 0; c < block_i; ++c) { + o[o_off + c] = _qz_a1b0()(i[i_off + c]); + } + if (b + 1 == nb) { + // zero padding + const auto pad_size = order_keep + ? blksize_16 - ((nb - 1) * blksize_i) + : blksize_i; + const auto pad_start = block_i + o_off; + const auto pad_end = pad_size + o_off; + PRAGMA_OMP_SIMD() + for (int i = pad_start; i < pad_end; i++) { + o[i] = 0; + } + } + } + } else { + for (int b = 0; b < nb; ++b) { + const ptrdiff_t i_off + = b * (order_keep ? stride_C_in_blk_i : blksize_i); + const ptrdiff_t o_off + = b * (order_keep ? blksize_i : stride_C_in_blk_i); + const int block_i + = nstl::min(blksize_i, block - b * blksize_i); + for (int c = 0; c < block_i; ++c) { + o[o_off + c] = _qz()( + i[i_off + c], o[o_off + c], alpha, beta); + } + if (b + 1 == nb) { + // zero padding + const auto pad_size = order_keep + ? blksize_16 - ((nb - 1) * blksize_i) + : blksize_i; + const auto pad_start = block_i + o_off; + const auto pad_end = pad_size + o_off; + PRAGMA_OMP_SIMD() + for (int i = pad_start; i < pad_end; i++) { + o[i] = 0; + } + } + } + } + }; + +#define data_blk_off(md, n, c, d, h, w) \ + (is_1d ? (md).blk_off(n, c, w) \ + : is_3d ? (md).blk_off(n, c, d, h, w) \ + : (md).blk_off(n, c, h, w)) + + parallel_nd(dims[0], pdims[1] / blksize_16, D, H, W, + [&](dim_t n, dim_t nb_c, dim_t d, dim_t h, dim_t w) { + auto i = &input[data_blk_off( + input_d, n, ic_mult * nb_c, d, h, w)]; + auto o = &output[data_blk_off( + output_d, n, oc_mult * nb_c, d, h, w)]; + const int block + = nstl::min(blksize_16, C - nb_c * blksize_16); + ker(i, o, block); + }); + +#undef data_blk_off + + return status::success; + } +}; + +#define PLAIN_TO_BLOCKED_IS_APPLICABLE() \ + static bool is_applicable(const memory_desc_wrapper &input_d, \ + const memory_desc_wrapper &output_d, \ + const primitive_attr_t *attr) { \ + return !input_d.has_runtime_dims_or_strides() \ + && simple_attr_check(attr, false, true) \ + && (order_keep ? output_d.matches_tag(tag_o) \ + && input_d.is_plain() \ + : input_d.matches_tag(tag_o) \ + && output_d.is_plain()); \ + } + +template +struct simple_reorder_impl::block_dims == bd::_A + || tag_traits::block_dims == bd::_B) + && tag_traits::ndims >= 3 + && tag_traits::ndims <= 6>::type> { + PLAIN_TO_BLOCKED_IS_APPLICABLE(); + + GET_SCRATCHPAD_SIZE_ZERO(); + + static status_t execute(const cpu_reorder_pd_t *pd, const exec_ctx_t &ctx) { + DECLARE_COMMON_PARAMS(); + + const auto &flat_d = order_keep ? input_d : output_d; + const auto &block_d = order_keep ? output_d : input_d; + const dims_t &dims = input_d.dims(); + const dims_t &pdims = block_d.padded_dims(); + + const int ndims = tag_traits::ndims; + const int blk_idx = tag_traits::block_dims == bd::_A ? 0 : 1; + + const dim_t H0 = dims[0]; + const dim_t H1 = dims[1]; + const dim_t M0 = ndims == 6 ? dims[ndims - 4] : 1; + const dim_t M1 = ndims >= 5 ? dims[ndims - 3] : 1; + const dim_t M2 = ndims >= 4 ? dims[ndims - 2] : 1; + const dim_t L = dims[ndims - 1]; + const dim_t l_blk_stride = block_d.blocking_desc().strides[ndims - 1]; + const dim_t l_flat_stride = flat_d.blocking_desc().strides[ndims - 1]; + const dim_t blk_flat_stride = flat_d.blocking_desc().strides[blk_idx]; + using namespace data_type; + using namespace utils; + + dim_t blksize = -1; + switch (tag_traits::inner_blks) { + case ib::_4a: + case ib::_4b: blksize = 4; break; + case ib::_8a: + case ib::_8b: blksize = 8; break; + default: blksize = 16; + } + + constexpr bool f32bf16 + = one_of(type_i, f32, bf16) && one_of(type_o, f32, bf16); + + auto wrap_qz_a1b0 = [=](data_t &out, data_t inp) { + if (f32bf16) + out = inp; + else + out = _qz_a1b0()(inp); + }; + + auto wrap_qz = [=](data_t &out, data_t inp, float alpha, + float beta) { + if (f32bf16) + out = alpha * inp + (beta ? beta * out : 0); + else + out = _qz()(inp, out, alpha, beta); + }; + + auto ker = [&](const data_t *i, data_t *o, int block) { + if (alpha == 1.0 && beta == 0.0) { + for (int l = 0; l < L; ++l) { + for (int blk = 0; blk < block; ++blk) { + const dim_t flat_off + = blk * blk_flat_stride + l * l_flat_stride; + const dim_t blk_offset = l * l_blk_stride + blk; + if (order_keep) { + wrap_qz_a1b0(o[blk_offset], i[flat_off]); + } else { + wrap_qz_a1b0(o[flat_off], i[blk_offset]); + } + } + if (order_keep) { + // zero padding + const auto pad_start = block + l * l_blk_stride; + const auto pad_end = blksize + l * l_blk_stride; + PRAGMA_OMP_SIMD() + for (int i = pad_start; i < pad_end; ++i) { + o[i] = 0; + } + } + } + } else { + for (int l = 0; l < L; ++l) { + for (int blk = 0; blk < block; ++blk) { + const dim_t flat_off + = blk * blk_flat_stride + l * l_flat_stride; + const dim_t blk_offset = l * l_blk_stride + blk; + if (order_keep) + wrap_qz(o[blk_offset], i[flat_off], alpha, beta); + else + wrap_qz(o[flat_off], i[blk_offset], alpha, beta); + } + if (order_keep) { + // zero padding + const auto pad_start = block + l * l_blk_stride; + const auto pad_end = blksize + l * l_blk_stride; + PRAGMA_OMP_SIMD() + for (int i = pad_start; i < pad_end; ++i) { + o[i] = 0; + } + } + } + } + }; + +#define off(md, h0, h1, m0, m1, m2) \ + (ndims >= 6 ? (md).blk_off(h0, h1, m0, m1, m2) \ + : ndims >= 5 ? (md).blk_off(h0, h1, m1, m2) \ + : ndims >= 4 ? (md).blk_off(h0, h1, m2) \ + : /* ndims >= 3 ? */ (md).blk_off(h0, h1)) + + const int i_mult = order_keep ? blksize : 1; + const int o_mult = order_keep ? 1 : blksize; + + if (blk_idx == 0) { + const dim_t BH0 = pdims[0] / blksize; + parallel_nd(BH0, H1, M0, M1, M2, + [&](dim_t bh0, dim_t h1, dim_t m0, dim_t m1, dim_t m2) { + auto i = &input[off( + input_d, bh0 * i_mult, h1, m0, m1, m2)]; + auto o = &output[off( + output_d, bh0 * o_mult, h1, m0, m1, m2)]; + const int block + = nstl::min(blksize, H0 - bh0 * blksize); + ker(i, o, block); + }); + } else if (blk_idx == 1) { + const dim_t BH1 = pdims[1] / blksize; + parallel_nd(H0, BH1, M0, M1, M2, + [&](dim_t h0, dim_t bh1, dim_t m0, dim_t m1, dim_t m2) { + auto i = &input[off( + input_d, h0, bh1 * i_mult, m0, m1, m2)]; + auto o = &output[off( + output_d, h0, bh1 * o_mult, m0, m1, m2)]; + const int block + = nstl::min(blksize, H1 - bh1 * blksize); + ker(i, o, block); + }); + } else { + assert(!"unimplemented"); + } + +#undef off + + return status::success; + } +}; + +template +struct simple_reorder_impl::block_dims == bd::_AB + || tag_traits::block_dims == bd::_BC) + && IMPLICATION(tag_traits::block_dims == bd::_AB, + tag_traits::ndims >= 3 + && tag_traits::ndims <= 5) + && IMPLICATION(tag_traits::block_dims == bd::_BC, + tag_traits::ndims >= 4 + && tag_traits::ndims <= 6)>::type> { + PLAIN_TO_BLOCKED_IS_APPLICABLE(); + + GET_SCRATCHPAD_SIZE_ZERO(); + + static status_t execute(const cpu_reorder_pd_t *pd, const exec_ctx_t &ctx) { + DECLARE_COMMON_PARAMS(); + + const auto &flat_d = order_keep ? input_d : output_d; + const auto &dims = input_d.dims(); + const auto &pdims + = order_keep ? output_d.padded_dims() : input_d.padded_dims(); + + constexpr int ndims = tag_traits::ndims; + + static constexpr bool with_g = tag_traits::block_dims == bd::_BC; + const dim_t G = with_g ? dims[0] : 1; + + const dim_t H0 = dims[0 + with_g]; + const dim_t H1 = dims[1 + with_g]; + + const dim_t M0 = ndims >= 5 + with_g ? dims[ndims - 3] : 1; + const dim_t M1 = ndims >= 4 + with_g ? dims[ndims - 2] : 1; + const dim_t M2 = ndims >= 3 + with_g ? dims[ndims - 1] : 1; + + const dim_t h0_flat_stride = flat_d.blocking_desc().strides[with_g + 0]; + const dim_t h1_flat_stride = flat_d.blocking_desc().strides[with_g + 1]; + using namespace data_type; + using namespace utils; + + dim_t blksize_0 = -1; + dim_t blksize_1 = -1; + switch (tag_traits::inner_blks) { + case ib::_4b4a: + case ib::_4b4c: + case ib::_4c4b: + blksize_0 = 4; + blksize_1 = 4; + break; + case ib::_8a8b: + case ib::_8b8a: + case ib::_8b8c: + case ib::_8c8b: + case ib::_2c8b4c: + blksize_0 = 8; + blksize_1 = 8; + break; + case ib::_16a16b: + case ib::_16b16a: + case ib::_16b16c: + case ib::_16c16b: + case ib::_8a16b2a: + case ib::_4b16a4b: + case ib::_8b16a2b: + case ib::_8b16c2b: + case ib::_4c16b4c: + case ib::_8c16b2c: + blksize_0 = 16; + blksize_1 = 16; + break; + default: blksize_0 = -1; blksize_1 = -1; + } + + const dim_t NB_H0 = pdims[0 + with_g] / blksize_0; + const dim_t NB_H1 = pdims[1 + with_g] / blksize_1; + + constexpr bool f32bf16 + = one_of(type_i, f32, bf16) && one_of(type_o, f32, bf16); + + auto wrap_qz_a1b0 = [=](data_t &out, data_t inp) { + if (f32bf16) + out = inp; + else + out = _qz_a1b0()(inp); + }; + + auto wrap_qz = [=](data_t &out, data_t inp, float alpha, + float beta) { + if (f32bf16) + out = alpha * inp + (beta ? beta * out : 0); + else + out = _qz()(inp, out, alpha, beta); + }; + + auto ker = [&](const data_t *i, data_t *o, + const int block_h0, const int block_h1) { +#define blk_off AB_or_BC_blk_off::inner_blks> + if (alpha == 1.0 && beta == 0.0) { + for (int h0 = 0; h0 < block_h0; ++h0) { + for (int h1 = 0; h1 < block_h1; ++h1) { + const dim_t flat_off + = h0 * h0_flat_stride + h1 * h1_flat_stride; + if (order_keep) + wrap_qz_a1b0(o[blk_off(h0, h1)], i[flat_off]); + else + wrap_qz_a1b0(o[flat_off], i[blk_off(h0, h1)]); + } + if (order_keep && block_h1 < blksize_1) { + // zero padding + PRAGMA_OMP_SIMD() + for (int h1 = block_h1; h1 < blksize_1; h1++) { + o[blk_off(h0, h1)] = 0; + } + } + } + if (order_keep && block_h0 < blksize_0) { + // zero padding + for (int h0 = block_h0; h0 < blksize_0; h0++) { + PRAGMA_OMP_SIMD() + for (int h1 = 0; h1 < blksize_1; ++h1) { + o[blk_off(h0, h1)] = 0; + } + } + } + } else { + for (int h0 = 0; h0 < block_h0; ++h0) { + for (int h1 = 0; h1 < block_h1; ++h1) { + const dim_t flat_off + = h0 * h0_flat_stride + h1 * h1_flat_stride; + if (order_keep) + wrap_qz(o[blk_off(h0, h1)], i[flat_off], alpha, + beta); + else + wrap_qz(o[flat_off], i[blk_off(h0, h1)], alpha, + beta); + } + if (order_keep && block_h1 < blksize_1) { + // zero padding + PRAGMA_OMP_SIMD() + for (int h1 = block_h1; h1 < blksize_1; h1++) { + o[blk_off(h0, h1)] = 0; + } + } + } + if (order_keep && block_h0 < blksize_0) { + // zero padding + for (int h0 = block_h0; h0 < blksize_0; h0++) { + PRAGMA_OMP_SIMD() + for (int h1 = 0; h1 < blksize_1; ++h1) { + o[blk_off(h0, h1)] = 0; + } + } + } + } + +#undef blk_off + }; + + const int i_mult_0 = order_keep ? blksize_0 : 1; + const int o_mult_0 = order_keep ? 1 : blksize_0; + + const int i_mult_1 = order_keep ? blksize_1 : 1; + const int o_mult_1 = order_keep ? 1 : blksize_1; + +#define off(md, g, h0, h1, m0, m1, m2) \ + (ndims >= 5 + with_g ? (md).blk_off(g, h0, h1, m0, m1, m2) \ + : ndims >= 4 + with_g \ + ? (md).blk_off(g, h0, h1, m1, m2) \ + : /* ndims >= 3 + with_g ? */ (md).blk_off( \ + g, h0, h1, m2)) + + parallel_nd(G, NB_H0, NB_H1, M0, M1, M2, + [&](dim_t g, dim_t nb_h0, dim_t nb_h1, dim_t m0, dim_t m1, + dim_t m2) { + auto i = &input[off(input_d, g, i_mult_0 * nb_h0, + i_mult_1 * nb_h1, m0, m1, m2)]; + auto o = &output[off(output_d, g, o_mult_0 * nb_h0, + o_mult_1 * nb_h1, m0, m1, m2)]; + const int block_h0 + = nstl::min(blksize_0, H0 - nb_h0 * blksize_0); + const int block_h1 + = nstl::min(blksize_1, H1 - nb_h1 * blksize_1); + ker(i, o, block_h0, block_h1); + }); + +#undef off + + return status::success; + } +}; + +/* generic and direct-copy reorders */ + +template +struct simple_reorder_impl::type> { + static bool is_applicable(const memory_desc_wrapper &input_d, + const memory_desc_wrapper &output_d, const primitive_attr_t *attr) { + return !input_d.has_runtime_dims_or_strides() + && input_d.similar_to(output_d, true, false, 0) + && input_d.is_dense() && output_d.is_dense() + && simple_attr_check(attr, false, true); + } + + GET_SCRATCHPAD_SIZE_ZERO(); + + static status_t execute(const cpu_reorder_pd_t *pd, const exec_ctx_t &ctx) { + DECLARE_COMMON_PARAMS(); + + input += input_d.blk_off(0); + output += output_d.blk_off(0); + + const size_t nelems = input_d.nelems(); + + constexpr int block_size = 16; + const auto num_blocks = nelems / block_size; + const auto rem_elems = nelems % block_size; + + parallel(0, [&](const int ithr, const int nthr) { + size_t start {0}, end {0}; + balance211(num_blocks, nthr, ithr, start, end); + start = start * block_size; + end = end * block_size; + + if (alpha == 1.0 && beta == 0.0) { + PRAGMA_OMP_SIMD() + for (size_t e = start; e < end; ++e) { + output[e] = qz_a1b0, data_t>()( + input[e]); + } + } else if (alpha == 1.0) { + PRAGMA_OMP_SIMD() + for (size_t e = start; e < end; ++e) { + output[e] = qz_a1, data_t>()( + input[e], output[e], beta); + } + } else if (beta == 0.0) { + PRAGMA_OMP_SIMD() + for (size_t e = start; e < end; ++e) { + output[e] = qz_b0, data_t>()( + input[e], alpha); + } + } else { + PRAGMA_OMP_SIMD() + for (size_t e = start; e < end; ++e) { + output[e] = qz, data_t>()( + input[e], output[e], alpha, beta); + } + } + + if (rem_elems != 0 && ithr == nthr - 1) { + if (alpha == 1.0 && beta == 0.0) { + PRAGMA_OMP_SIMD() + for (size_t e = nelems - rem_elems; e < nelems; ++e) { + output[e] = qz_a1b0, data_t>()( + input[e]); + } + } else if (alpha == 1.0) { + PRAGMA_OMP_SIMD() + for (size_t e = nelems - rem_elems; e < nelems; ++e) { + output[e] = qz_a1, data_t>()( + input[e], output[e], beta); + } + } else if (beta == 0.0) { + PRAGMA_OMP_SIMD() + for (size_t e = nelems - rem_elems; e < nelems; ++e) { + output[e] = qz_b0, data_t>()( + input[e], alpha); + } + } else { + PRAGMA_OMP_SIMD() + for (size_t e = nelems - rem_elems; e < nelems; ++e) { + output[e] = qz, data_t>()( + input[e], output[e], alpha, beta); + } + } + } + }); + return status::success; + } +}; + +template +struct simple_reorder_impl::type> { + static bool is_applicable(const memory_desc_wrapper &input_d, + const memory_desc_wrapper &output_d, const primitive_attr_t *attr) { + auto is_dense_no_0 = [](const memory_desc_wrapper &data_d) { + return nelems_no_dim_0(data_d) == _size_no_dim_0(data_d); + }; + return !input_d.has_runtime_dims_or_strides() + && input_d.similar_to(output_d, true, false, 1) + && is_dense_no_0(input_d) && is_dense_no_0(output_d) + && simple_attr_check(attr, false, true); + } + + GET_SCRATCHPAD_SIZE_ZERO(); + + static status_t execute(const cpu_reorder_pd_t *pd, const exec_ctx_t &ctx) { + DECLARE_COMMON_PARAMS(); + using namespace utils; + + input += input_d.blk_off(0); + output += output_d.blk_off(0); + + const int N = input_d.dims()[0]; + const dim_t is = input_d.blocking_desc().strides[0]; + const dim_t os = output_d.blocking_desc().strides[0]; + const dim_t nelems_no_d0 = nelems_no_dim_0(input_d); + const dim_t work_amount = N * nelems_no_d0; + + if (alpha == 1.0 && beta == 0.0) { + parallel(0, [&](const int ithr, const int nthr) { + dim_t n {0}, dim1_s {0}; + dim_t start {0}, end {0}; + balance211(work_amount, nthr, ithr, start, end); + nd_iterator_init(start, n, N, dim1_s, nelems_no_d0); + while (start < end) { + dim_t work_rem = end - start; + dim_t dim1_e = std::min(dim1_s + work_rem, nelems_no_d0); + PRAGMA_OMP_SIMD() + for (dim_t e = dim1_s; e < dim1_e; ++e) { + output[os * n + e] + = _qz_a1b0()(input[is * n + e]); + } + nd_iterator_jump(start, end, n, N, dim1_s, nelems_no_d0); + } + }); + } else { + parallel(0, [&](const int ithr, const int nthr) { + dim_t n {0}, dim1_s {0}; + dim_t start {0}, end {0}; + balance211(work_amount, nthr, ithr, start, end); + nd_iterator_init(start, n, N, dim1_s, nelems_no_d0); + while (start < end) { + dim_t work_rem = end - start; + dim_t dim1_e = std::min(dim1_s + work_rem, nelems_no_d0); + PRAGMA_OMP_SIMD() + for (dim_t e = dim1_s; e < dim1_e; ++e) { + output[os * n + e] + = _qz()(input[is * n + e], + output[os * n + e], alpha, beta); + } + nd_iterator_jump(start, end, n, N, dim1_s, nelems_no_d0); + } + }); + } + + return status::success; + } + +private: + static dim_t nelems_no_dim_0(const memory_desc_wrapper &data_d) { + const int ndims = data_d.ndims(); + if (ndims <= 1) return 1; + return utils::array_product(data_d.dims() + 1, data_d.ndims() - 1); + } + + static dim_t _size_no_dim_0(const memory_desc_wrapper &data_d) { + dims_t blocks; + data_d.compute_blocks(blocks); + + const auto &blk = data_d.blocking_desc(); + + dim_t blk_size = 1; + for (int iblk = 0; iblk < blk.inner_nblks; ++iblk) + blk_size *= blk.inner_blks[iblk]; + + dim_t max_size = blk_size; + for (int d = 1; d < data_d.ndims(); ++d) { + max_size = nstl::max(max_size, + data_d.padded_dims()[d] / blocks[d] * blk.strides[d]); + } + + return max_size; + } +}; + +template +struct simple_reorder_impl::type> { + static bool is_applicable(const memory_desc_wrapper &input_d, + const memory_desc_wrapper &output_d, const primitive_attr_t *attr) { + /* supported smask: 0x0...011..10...0, + * i.e. 1 should be contiguous */ + int src_scales_mask = -1; + int dst_scales_mask = -1; + CHECK(get_scales_mask(attr, &src_scales_mask, &dst_scales_mask)); + + for (auto smask : {src_scales_mask, dst_scales_mask}) { + for (; smask > 0 && !(smask & 0x1); smask >>= 1) + ; + for (; smask > 0 && smask & 0x1; smask >>= 1) + ; + if (smask != 0) return false; + } + + using skip_mask_t = dnnl_primitive_attr::skip_mask_t; + return input_d.is_blocking_desc() && output_d.is_blocking_desc() + && !output_d.is_additional_buffer() + && !input_d.is_additional_buffer() + && attr->has_default_values(skip_mask_t::scales_runtime + | skip_mask_t::zero_points_runtime + | skip_mask_t::post_ops) + && simple_po_check(attr); + } + + GET_SCRATCHPAD_SIZE_ZERO(); + + static status_t execute(const cpu_reorder_pd_t *pd, const exec_ctx_t &ctx) { + DECLARE_COMMON_PARAMS(); + + // This kernel is used also for tensors with multiple inner + // blocks for which generic zero padding must be used. + // TODO: apply zero padding inside parallel_nd() + ctx.zero_pad_output(DNNL_ARG_TO); + + parallel_nd(D_start, D_mask, D_rest, + [&](ptrdiff_t ds, ptrdiff_t dm, ptrdiff_t dr) { + const float src_scale + = src_scales[src_scales_mask == 0 ? 0 : dm]; + const float dst_scale + = dst_scales[dst_scales_mask == 0 ? 0 : dm]; + + const size_t e = (ds * D_mask + dm) * D_rest + dr; + const auto &i = input[input_d.off_l(e)]; + auto &o = output[output_d.off_l(e)]; + + float f = src_scale * ((float)i - src_zp); + if (beta) f += beta * o; + f = f * dst_scale + dst_zp; + o = _qz_a1b0()(f); + }); + + return status::success; + } +}; + +/* high level class declaration */ + +template +struct simple_reorder_t : public primitive_t { + struct pd_t : public cpu_reorder_pd_t { + using cpu_reorder_pd_t::cpu_reorder_pd_t; + + DECLARE_COMMON_PD_T("simple:any", simple_reorder_t); + + private: + static status_t create(reorder_pd_t **reorder_pd, engine_t *engine, + const primitive_attr_t *attr, engine_t *src_engine, + const memory_desc_t *src_md, engine_t *dst_engine, + const memory_desc_t *dst_md) { + using skip_mask_t = dnnl_primitive_attr::skip_mask_t; + bool args_ok = src_md->data_type == type_i + && dst_md->data_type == type_o + && attr->has_default_values(skip_mask_t::scales_runtime + | skip_mask_t::zero_points + | skip_mask_t::zero_points_runtime + | skip_mask_t::post_ops) + && simple_reorder_impl::is_applicable(src_md, dst_md, attr); + if (!args_ok) return status::invalid_arguments; + + int mask = -1; + bool is_set = false; + CHECK(attr->scales_.get(DNNL_ARG_DST, &mask, &is_set)); + const memory_desc_wrapper input_d(src_md); + if (input_d.has_runtime_dims_or_strides() && is_set && mask > 0) + return status::unimplemented; + + auto _pd = new pd_t(attr, src_engine->kind(), src_md, + dst_engine->kind(), dst_md); + if (_pd == nullptr) return status::out_of_memory; + if (_pd->init(engine, src_engine, dst_engine) != status::success) { + delete _pd; + return status::unimplemented; + } + + const size_t scratchpad_sz_ + = simple_reorder_impl::get_scratchpad_size(src_md, dst_md); + auto scratchpad = _pd->scratchpad_registry().registrar(); + scratchpad.book(memory_tracking::names::key_reorder_space, + scratchpad_sz_, 1, 16); + + if (is_set && mask > 0) { + dim_t D_mask; + _pd->get_D_values(input_d, mask, nullptr, &D_mask, nullptr); + scratchpad.template book( + memory_tracking::names:: + key_reorder_precomputed_dst_scales, + D_mask); + } + + CHECK(_pd->init_scratchpad_md()); + return safe_ptr_assign(*reorder_pd, _pd); + } + friend dnnl::impl::impl_list_item_t; + }; + + simple_reorder_t(const pd_t *apd) : primitive_t(apd) {} + + status_t execute(const exec_ctx_t &ctx) const override { + return simple_reorder_impl::execute( + pd(), ctx); + } + +private: + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } +}; + +#undef SIMPLE_REORDER_TEMPL_DECL +#undef SIMPLE_REORDER_TEMPL_CALL + +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/rnn/cpu_rnn_pd.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/rnn/cpu_rnn_pd.hpp new file mode 100644 index 0000000000000000000000000000000000000000..8f32420bf9f9fcf6036fadb146775c96e0ad6aed --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/rnn/cpu_rnn_pd.hpp @@ -0,0 +1,313 @@ +/******************************************************************************* +* Copyright 2018-2022 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_RNN_CPU_RNN_PD_HPP +#define CPU_RNN_CPU_RNN_PD_HPP + +#include "common/c_types_map.hpp" +#include "common/nstl.hpp" +#include "common/rnn_pd.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_engine.hpp" + +#include "cpu/rnn/rnn_utils.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { + +struct cpu_rnn_fwd_pd_t : public rnn_fwd_pd_t { + using rnn_fwd_pd_t::rnn_fwd_pd_t; + +protected: + status_t set_default_params() { + using namespace format_tag; + if (src_layer_md_.format_kind == format_kind::any) + CHECK(memory_desc_init_by_tag(src_layer_md_, tnc)); + if (dst_layer_md_.format_kind == format_kind::any) + CHECK(memory_desc_init_by_tag(dst_layer_md_, tnc)); + + if (is_augru()) { + if (augru_attention_md().format_kind == format_kind::any) + CHECK(memory_desc_init_by_tag(augru_attention_md(), tnc)); + } + + // Optional parameters + if (with_src_iter() && src_iter_md_.format_kind == format_kind::any) + CHECK(memory_desc_init_by_tag(src_iter_md_, ldnc)); + if (with_src_iter_c() && src_iter_c_md_.format_kind == format_kind::any) + CHECK(memory_desc_init_by_tag(src_iter_c_md_, ldnc)); + if (is_lstm_peephole() + && weights_peephole_md_.format_kind == format_kind::any) + CHECK(memory_desc_init_by_tag(weights_peephole_md_, ldgo)); + if (with_bias() && bias_md_.format_kind == format_kind::any) + CHECK(memory_desc_init_by_tag(bias_md_, ldgo)); + if (with_dst_iter() && dst_iter_md_.format_kind == format_kind::any) + CHECK(memory_desc_init_by_tag(dst_iter_md_, ldnc)); + if (with_dst_iter_c() && dst_iter_c_md_.format_kind == format_kind::any) + CHECK(memory_desc_init_by_tag(dst_iter_c_md_, ldnc)); + + return status::success; + } + + status_t check_layout_consistency(bool is_brgemm) { + using namespace format_tag; + using namespace data_type; + using namespace types; + + const auto is_blocked = [&](const memory_desc_t &md, int ndims, + bool require_last_dim_contiguous) { + return md.format_kind == format_kind::blocked && md.ndims == ndims + && IMPLICATION(require_last_dim_contiguous, + md.format_desc.blocking.strides[md.ndims - 1] == 1); + }; + + bool ok = true; + ok = ok && is_blocked(src_layer_md_, 3, true) + && is_blocked(dst_layer_md_, 3, true); + ok = ok + && IMPLICATION(!is_zero_md(&src_iter_md_), + is_blocked(src_iter_md_, 4, true)) + && IMPLICATION(!is_zero_md(&src_iter_c_md_), + is_blocked(src_iter_c_md_, 4, true)) + && IMPLICATION(!is_zero_md(&dst_iter_md_), + is_blocked(dst_iter_md_, 4, true)) + && IMPLICATION(!is_zero_md(&dst_iter_c_md_), + is_blocked(dst_iter_c_md_, 4, true)); + + if (weights_layer_md_.format_kind == format_kind::rnn_packed) + ok = ok + && (weights_layer_md_.format_desc.rnn_packed_desc.format + == rnn_packed_memory_format_t::ldigo_p); + else + ok = ok + && (rnn_utils::is_ldigo(&weights_layer_md_) + || rnn_utils::is_ldigo_blocked(&weights_layer_md_)); + + if (weights_iter_md_.format_kind == format_kind::rnn_packed) + ok = ok + && (weights_iter_md_.format_desc.rnn_packed_desc.format + == rnn_packed_memory_format_t::ldigo_p); + else + ok = ok + && (rnn_utils::is_ldigo(&weights_iter_md_) + || rnn_utils::is_ldigo_blocked(&weights_iter_md_)); + + ok = ok + && IMPLICATION(is_lstm_peephole(), + memory_desc_matches_tag(weights_peephole_md_, ldgo)); + + if (is_lstm_projection()) { + if (weights_projection_md_.format_kind == format_kind::rnn_packed) + ok = ok + && (weights_projection_md_.format_desc.rnn_packed_desc + .format + == rnn_packed_memory_format_t::ldio_p); + else + ok = ok + && (rnn_utils::is_ldio(&weights_projection_md_) + || rnn_utils::is_ldio_blocked( + &weights_projection_md_)); + } + + ok = ok + && IMPLICATION( + with_bias(), memory_desc_matches_tag(bias_md_, ldgo)); + + /* Int8 is supported only for packed weights, if not BRGEMM version */ + const data_type_t weights_iter_dt = weights_iter_md_.data_type; + const data_type_t weights_layer_dt = weights_layer_md_.data_type; + if (!rnn_utils::is_ldigo_blocked(&weights_iter_md_)) + ok = ok + && IMPLICATION(weights_iter_dt == s8, + weights_iter_md_.format_kind + == format_kind::rnn_packed); + if (!rnn_utils::is_ldigo_blocked(&weights_layer_md_)) + ok = ok + && IMPLICATION(weights_layer_dt == s8, + weights_layer_md_.format_kind + == format_kind::rnn_packed); + return ok ? status::success : status::unimplemented; + } +}; + +struct cpu_rnn_bwd_pd_t : public rnn_bwd_pd_t { + using rnn_bwd_pd_t::rnn_bwd_pd_t; + +protected: + status_t set_default_params() { + using namespace format_tag; + if (src_layer_md_.format_kind == format_kind::any) + CHECK(memory_desc_init_by_tag(src_layer_md_, tnc)); + if (dst_layer_md_.format_kind == format_kind::any) + CHECK(memory_desc_init_by_tag(dst_layer_md_, tnc)); + + if (is_augru()) { + if (augru_attention_md().format_kind == format_kind::any) + CHECK(memory_desc_init_by_tag(augru_attention_md(), tnc)); + if (diff_augru_attention_md().format_kind == format_kind::any) + CHECK(memory_desc_init_by_tag(diff_augru_attention_md(), tnc)); + } + + if (diff_src_layer_md_.format_kind == format_kind::any) + CHECK(memory_desc_init_by_tag(diff_src_layer_md_, tnc)); + if (diff_weights_layer_md_.format_kind == format_kind::any) { + CHECK(memory_desc_init_by_tag(diff_weights_layer_md_, ldigo)); + CHECK(rnn_utils::set_good_strides(diff_weights_layer_md_, ldigo)); + } + if (diff_weights_iter_md_.format_kind == format_kind::any) { + CHECK(memory_desc_init_by_tag(diff_weights_iter_md_, ldigo)); + CHECK(rnn_utils::set_good_strides(diff_weights_iter_md_, ldigo)); + } + if (diff_dst_layer_md_.format_kind == format_kind::any) + CHECK(memory_desc_init_by_tag(diff_dst_layer_md_, tnc)); + + // Optional parameters + if (with_src_iter() && src_iter_md_.format_kind == format_kind::any) + CHECK(memory_desc_init_by_tag(src_iter_md_, ldnc)); + if (with_src_iter_c() && src_iter_c_md_.format_kind == format_kind::any) + CHECK(memory_desc_init_by_tag(src_iter_c_md_, ldnc)); + if (is_lstm_peephole() + && weights_peephole_md_.format_kind == format_kind::any) + CHECK(memory_desc_init_by_tag(weights_peephole_md_, ldgo)); + if (is_lstm_projection() + && weights_projection_md_.format_kind == format_kind::any) + CHECK(memory_desc_init_by_tag(weights_projection_md_, ldoi)); + if (with_bias() && bias_md_.format_kind == format_kind::any) + CHECK(memory_desc_init_by_tag(bias_md_, ldgo)); + if (with_dst_iter() && dst_iter_md_.format_kind == format_kind::any) + CHECK(memory_desc_init_by_tag(dst_iter_md_, ldnc)); + if (with_dst_iter_c() && dst_iter_c_md_.format_kind == format_kind::any) + CHECK(memory_desc_init_by_tag(dst_iter_c_md_, ldnc)); + + if (with_src_iter() + && diff_src_iter_md_.format_kind == format_kind::any) + CHECK(memory_desc_init_by_tag(diff_src_iter_md_, ldnc)); + if (with_src_iter_c() + && diff_src_iter_c_md_.format_kind == format_kind::any) + CHECK(memory_desc_init_by_tag(diff_src_iter_c_md_, ldnc)); + if (is_lstm_peephole() + && diff_weights_peephole_md_.format_kind == format_kind::any) + CHECK(memory_desc_init_by_tag(diff_weights_peephole_md_, ldgo)); + if (is_lstm_projection() + && diff_weights_projection_md_.format_kind == format_kind::any) + CHECK(memory_desc_init_by_tag(diff_weights_projection_md_, ldio)); + if (with_bias() && diff_bias_md_.format_kind == format_kind::any) + CHECK(memory_desc_init_by_tag(diff_bias_md_, ldgo)); + if (with_dst_iter() + && diff_dst_iter_md_.format_kind == format_kind::any) + CHECK(memory_desc_init_by_tag(diff_dst_iter_md_, ldnc)); + if (with_dst_iter_c() + && diff_dst_iter_c_md_.format_kind == format_kind::any) + CHECK(memory_desc_init_by_tag(diff_dst_iter_c_md_, ldnc)); + + return status::success; + } + + status_t check_layout_consistency(bool is_brgemm) { + using namespace format_tag; + using namespace types; + + const auto is_blocked = [&](const memory_desc_t &md, int ndims, + bool require_last_dim_contiguous) { + return md.format_kind == format_kind::blocked && md.ndims == ndims + && IMPLICATION(require_last_dim_contiguous, + md.format_desc.blocking.strides[md.ndims - 1] == 1); + }; + + bool ok = true; + ok = ok && is_blocked(src_layer_md_, 3, true) + && is_blocked(dst_layer_md_, 3, true); + ok = ok + && IMPLICATION(!is_zero_md(&src_iter_md_), + is_blocked(src_iter_md_, 4, true)) + && IMPLICATION(!is_zero_md(&src_iter_c_md_), + is_blocked(src_iter_c_md_, 4, true)) + && IMPLICATION(!is_zero_md(&dst_iter_md_), + is_blocked(dst_iter_md_, 4, true)) + && IMPLICATION(!is_zero_md(&dst_iter_c_md_), + is_blocked(dst_iter_c_md_, 4, true)); + + const auto check_weights_consistency = + [&](const memory_desc_t &weights_md) { + if (weights_md.format_kind == format_kind::rnn_packed) + return ok + && weights_md.format_desc.rnn_packed_desc.format + == rnn_packed_memory_format_t::ldgoi_p; + else if (is_brgemm) + return ok && rnn_utils::is_ldgoi_blocked(&weights_md); + else + return ok && rnn_utils::is_ldgoi(&weights_md); + }; + + ok = check_weights_consistency(weights_layer_md_); + ok = check_weights_consistency(weights_iter_md_); + + ok = ok + && IMPLICATION(is_augru(), + memory_desc_matches_tag(augru_attention_md(), tnc)); + ok = ok + && IMPLICATION(is_lstm_peephole(), + memory_desc_matches_tag(weights_peephole_md_, ldgo)); + ok = ok + && IMPLICATION(is_lstm_projection(), + memory_desc_matches_tag(weights_projection_md_, ldoi)); + ok = ok + && IMPLICATION( + with_bias(), memory_desc_matches_tag(bias_md_, ldgo)); + + ok = ok && is_blocked(diff_src_layer_md_, 3, true) + && is_blocked(diff_dst_layer_md_, 3, true); + ok = ok + && IMPLICATION(!is_zero_md(&diff_src_iter_md_), + is_blocked(diff_src_iter_md_, 4, true)) + && IMPLICATION(!is_zero_md(&diff_src_iter_c_md_), + is_blocked(diff_src_iter_c_md_, 4, true)) + && IMPLICATION(!is_zero_md(&diff_dst_iter_md_), + is_blocked(diff_dst_iter_md_, 4, true)) + && IMPLICATION(!is_zero_md(&diff_dst_iter_c_md_), + is_blocked(diff_dst_iter_c_md_, 4, true)); + + ok = ok + && IMPLICATION(is_augru(), + memory_desc_matches_tag( + diff_augru_attention_md(), tnc)); + ok = ok && rnn_utils::is_ldigo(&diff_weights_layer_md_) + && rnn_utils::is_ldigo(&diff_weights_iter_md_); + ok = ok + && IMPLICATION(is_lstm_peephole() + && !is_zero_md(&diff_weights_peephole_md_), + memory_desc_matches_tag( + diff_weights_peephole_md_, ldgo)); + ok = ok + && IMPLICATION(!is_zero_md(&diff_weights_projection_md_), + memory_desc_matches_tag( + diff_weights_projection_md_, ldio)); + ok = ok + && IMPLICATION(!is_zero_md(&diff_bias_md_), + memory_desc_matches_tag(diff_bias_md_, ldgo)); + + return ok ? status::success : status::unimplemented; + } +}; + +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/rnn/postgemm_dispatcher.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/rnn/postgemm_dispatcher.hpp new file mode 100644 index 0000000000000000000000000000000000000000..c56133e1d6662ff3c89e99e31e94e07f70622c22 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/rnn/postgemm_dispatcher.hpp @@ -0,0 +1,323 @@ +/******************************************************************************* +* Copyright 2019-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_RNN_POSTGEMM_DISPATCHER_HPP +#define CPU_RNN_POSTGEMM_DISPATCHER_HPP + +#include + +#include "common/z_magic.hpp" + +#include "cpu/platform.hpp" + +#include "cpu/rnn/cpu_rnn_pd.hpp" +#include "cpu/rnn/rnn_utils.hpp" + +#if DNNL_X64 +#include "cpu/x64/rnn/jit_uni_gru_cell_postgemm_1_bwd.hpp" +#include "cpu/x64/rnn/jit_uni_gru_cell_postgemm_1_fwd.hpp" +#include "cpu/x64/rnn/jit_uni_gru_cell_postgemm_2_bwd.hpp" +#include "cpu/x64/rnn/jit_uni_gru_cell_postgemm_2_fwd.hpp" +#include "cpu/x64/rnn/jit_uni_gru_lbr_cell_postgemm_bwd.hpp" +#include "cpu/x64/rnn/jit_uni_gru_lbr_cell_postgemm_fwd.hpp" +#include "cpu/x64/rnn/jit_uni_lstm_cell_postgemm_bwd.hpp" +#include "cpu/x64/rnn/jit_uni_lstm_cell_postgemm_fwd.hpp" +#include "cpu/x64/rnn/jit_uni_lstm_cell_projection_postgemm_fwd.hpp" +#include "cpu/x64/rnn/jit_uni_rnn_cell_postgemm_bwd.hpp" +#include "cpu/x64/rnn/jit_uni_rnn_cell_postgemm_fwd.hpp" +#include "cpu/x64/rnn/jit_uni_rnn_common_postgemm.hpp" +#endif + +namespace dnnl { +namespace impl { +namespace cpu { + +template +float activation(float s, float alpha, float cliping); + +template +struct rnn_postgemm_dispatcher { + + typedef typename prec_traits::type src_layer_t; + typedef typename prec_traits::type src_iter_t; + typedef typename prec_traits::type dst_layer_t; + typedef typename prec_traits::type dst_iter_t; + typedef typename prec_traits::type gemm_acc_t; + typedef typename prec_traits::type scratch_t; + typedef typename prec_traits::type ht_t; + typedef typename prec_traits::type gates_t; + + using class_name + = rnn_postgemm_dispatcher; + typedef rnn_postgemm_sig((class_name::*postgemm_f)); + + rnn_postgemm_dispatcher( + const rnn_utils::rnn_conf_t &rnn, const rnn_pd_t *pd) + : pd_(pd) { + // add check if in testing mode + if (pd->attr()->rnn_tparams_.test_mode_) { + const auto ngates = utils::map(pd->cell_kind(), 0, + alg_kind::vanilla_rnn, 1, alg_kind::vanilla_lstm, 4, + alg_kind::vanilla_gru, 3, alg_kind::lbr_gru, 3, + alg_kind::vanilla_augru, 3, alg_kind::lbr_augru, 3); + assert(pd->attr()->rnn_tparams_.ngates_ == ngates); + MAYBE_UNUSED(ngates); + } + + switch (pd->cell_kind()) { + case alg_kind::vanilla_lstm: + postgemm_func = &class_name::lstm_postgemm; + // used for int8 requantization after projection + postgemm_part2_func = pd->is_lstm_projection() && pd_->is_fwd() + ? &class_name::lstm_projection_postgemm + : nullptr; + break; + case alg_kind::vanilla_rnn: + postgemm_func = &class_name::rnn_postgemm; + switch (pd->activation_kind()) { + case alg_kind::eltwise_relu: + activation_func + = &activation; + break; + case alg_kind::eltwise_tanh: + activation_func + = &activation; + break; + case alg_kind::eltwise_logistic: + activation_func + = &activation; + break; + default: assert(!"Unsupported activation function"); break; + } + break; + case alg_kind::vanilla_gru: + case alg_kind::vanilla_augru: + postgemm_func = &class_name::gru_part1_postgemm; + postgemm_part2_func = &class_name::gru_part2_postgemm; + break; + case alg_kind::lbr_gru: + case alg_kind::lbr_augru: + postgemm_func = &class_name::gru_lbr_postgemm; + break; + default: assert(!"Unsupported algorithm kind"); break; + } + } + + ~rnn_postgemm_dispatcher() = default; + + status_t init(const rnn_utils::rnn_conf_t &rnn) { + DNNL_X64_ONLY(CHECK(initialize_jit(rnn))); + return status::success; + } + + rnn_postgemm_sig(unpoison) { + // XXX (rsdubtso): This is a big hammer that unpoisons everything + // that a postgemm may touch to avoid writing per-cell-kind + // versions of unpoisoning code. This must be removed alongside with + // the big unpoison_outputs() hammer in common/primitive.cpp. + + const size_t states_nelems + = rnn.ws_states_layer_nld * rnn.ws_states_layer_ld; + const size_t gates_nelems + = rnn.scratch_gates_nld * rnn.scratch_gates_ld; + + if (pd_->is_fwd()) { + msan_unpoison(dst_layer_, sizeof(*dst_layer_) * states_nelems); + msan_unpoison(dst_iter_, sizeof(*dst_iter_) * states_nelems); + if (rnn.is_training) + msan_unpoison(ws_gates_, sizeof(*ws_gates_) * gates_nelems); + } else { + msan_unpoison(diff_src_layer_, + sizeof(*diff_src_layer_) * (rnn.n_iter + 1) + * rnn.ws_diff_states_layer_nld + * rnn.ws_diff_states_layer_ld); + msan_unpoison(diff_augru_attention_, + sizeof(*diff_augru_attention_) * rnn.n_iter * rnn.mb + * rnn.dhc); + msan_unpoison(diff_src_iter_, + sizeof(*diff_src_iter_) * (rnn.n_iter + 1) + * rnn.ws_diff_states_iter_nld + * rnn.ws_diff_states_iter_ld); + msan_unpoison(diff_src_iter_c_, + sizeof(*diff_src_iter_c_) * (rnn.n_iter + 1) + * rnn.ws_diff_states_iter_c_nld + * rnn.ws_diff_states_iter_c_ld); + msan_unpoison( + scratch_gates_, sizeof(*scratch_gates_) * gates_nelems); + msan_unpoison( + scratch_cell_, sizeof(*scratch_cell_) * states_nelems); + } + } + + // template + rnn_postgemm_sig(execute) { + /* This block has an impact on performance in case it is executed + * multiple times. Be careful when changing it. + * XXX: The code is compiler sensitive, jit might help with that. + */ +#if DNNL_X64 + if (rnn_postgemm_) { + rnn_postgemm_->execute(rnn, cell_position, ws_gates_, + scratch_gates_, augru_attention_, dst_layer_, dst_iter_c_, + src_iter_, src_iter_c_, diff_src_layer_, + diff_augru_attention_, diff_src_iter_, diff_src_iter_c_, + diff_dst_layer_, diff_dst_iter_, diff_dst_iter_c_, + weights_peephole_, bias_, ws_grid_, scratch_cell_, + dst_iter_, weights_scales_, block_step); + unpoison(rnn, cell_position, ws_gates_, scratch_gates_, + augru_attention_, dst_layer_, dst_iter_c_, src_iter_, + src_iter_c_, diff_src_layer_, diff_augru_attention_, + diff_src_iter_, diff_src_iter_c_, diff_dst_layer_, + diff_dst_iter_, diff_dst_iter_c_, weights_peephole_, bias_, + ws_grid_, scratch_cell_, dst_iter_, weights_scales_, + block_step); + return; + } +#endif + (this->*postgemm_func)(rnn, cell_position, ws_gates_, scratch_gates_, + augru_attention_, dst_layer_, dst_iter_c_, src_iter_, + src_iter_c_, diff_src_layer_, diff_augru_attention_, + diff_src_iter_, diff_src_iter_c_, diff_dst_layer_, + diff_dst_iter_, diff_dst_iter_c_, weights_peephole_, bias_, + ws_grid_, scratch_cell_, dst_iter_, weights_scales_, + block_step); + } + + // template + rnn_postgemm_sig(execute_part2) { + /* This block has an impact on performance in case it is executed + * multiple times. Be careful when changing it. + * XXX: The code is compiler sensitive, jit might help with that. + */ +#if DNNL_X64 + if (rnn_postgemm_part2_) { + rnn_postgemm_part2_->execute(rnn, cell_position, ws_gates_, + scratch_gates_, augru_attention_, dst_layer_, dst_iter_c_, + src_iter_, src_iter_c_, diff_src_layer_, + diff_augru_attention_, diff_src_iter_, diff_src_iter_c_, + diff_dst_layer_, diff_dst_iter_, diff_dst_iter_c_, + weights_peephole_, bias_, ws_grid_, scratch_cell_, + dst_iter_, weights_scales_, block_step); + unpoison(rnn, cell_position, ws_gates_, scratch_gates_, + augru_attention_, dst_layer_, dst_iter_c_, src_iter_, + src_iter_c_, diff_src_layer_, diff_augru_attention_, + diff_src_iter_, diff_src_iter_c_, diff_dst_layer_, + diff_dst_iter_, diff_dst_iter_c_, weights_peephole_, bias_, + ws_grid_, scratch_cell_, dst_iter_, weights_scales_, + block_step); + return; + } +#endif + (this->*postgemm_part2_func)(rnn, cell_position, ws_gates_, + scratch_gates_, augru_attention_, dst_layer_, dst_iter_c_, + src_iter_, src_iter_c_, diff_src_layer_, diff_augru_attention_, + diff_src_iter_, diff_src_iter_c_, diff_dst_layer_, + diff_dst_iter_, diff_dst_iter_c_, weights_peephole_, bias_, + ws_grid_, scratch_cell_, dst_iter_, weights_scales_, + block_step); + } + +private: + float (*activation_func)(float s, float alpha, float cliping); + rnn_postgemm_sig(rnn_postgemm); + rnn_postgemm_sig(lstm_postgemm); + rnn_postgemm_sig(lstm_projection_postgemm); + rnn_postgemm_sig(gru_part1_postgemm); + rnn_postgemm_sig(gru_part2_postgemm); + rnn_postgemm_sig(gru_lbr_postgemm); + + const rnn_pd_t *pd_; + + postgemm_f postgemm_func; + postgemm_f postgemm_part2_func; + + DNNL_DISALLOW_COPY_AND_ASSIGN(rnn_postgemm_dispatcher); + +#if DNNL_X64 + std::unique_ptr rnn_postgemm_; + std::unique_ptr rnn_postgemm_part2_; + + status_t initialize_jit(const rnn_utils::rnn_conf_t &rnn) { + using namespace dnnl::impl::cpu::x64; + + if (pd_->attr()->rnn_tparams_.test_mode_) return status::success; + + const bool jit_fwd = pd_->is_fwd() + && utils::one_of(src_type, data_type::f32, data_type::u8, + data_type::s8, data_type::bf16); + const bool jit_bwd = !pd_->is_fwd() + && utils::one_of(src_type, data_type::f32, data_type::bf16); + +#define CREATE_WITH_DIR(k, ker_t) \ + do { \ + if (mayiuse(avx512_core)) \ + k.reset(new ker_t(rnn, pd_)); \ + else if (mayiuse(avx2)) \ + k.reset(new ker_t(rnn, pd_)); \ + else \ + k.reset(new ker_t(rnn, pd_)); \ + } while (0) +#define CREATE(k, ker_t) \ + do { \ + if (jit_fwd) CREATE_WITH_DIR(k, CONCAT2(ker_t, _fwd)); \ + if (jit_bwd) CREATE_WITH_DIR(k, CONCAT2(ker_t, _bwd)); \ + } while (0) + + if (pd_->cell_kind() == alg_kind::vanilla_lstm) { + CREATE(rnn_postgemm_, jit_uni_lstm_cell_postgemm); + } else if (pd_->cell_kind() == alg_kind::vanilla_rnn) { + CREATE(rnn_postgemm_, jit_uni_rnn_cell_postgemm); + } else if (utils::one_of(pd_->cell_kind(), alg_kind::vanilla_gru, + alg_kind::vanilla_augru)) { + CREATE(rnn_postgemm_, jit_uni_gru_cell_postgemm_part1); + CREATE(rnn_postgemm_part2_, jit_uni_gru_cell_postgemm_part2); + } else if (utils::one_of(pd_->cell_kind(), alg_kind::lbr_gru, + alg_kind::lbr_augru)) { + CREATE(rnn_postgemm_, jit_uni_gru_lbr_cell_postgemm); + } + +#undef CREATE +#undef CREATE_WITH_DIR + + if (rnn_postgemm_) CHECK(rnn_postgemm_->init(src_type)); + if (rnn_postgemm_part2_) CHECK(rnn_postgemm_part2_->init(src_type)); + return status::success; + } +#endif +}; + +using rnn_postgemm_fwd_f32_t = rnn_postgemm_dispatcher; +using rnn_postgemm_bwd_f32_t = rnn_postgemm_dispatcher; + +using rnn_postgemm_fwd_bf16_t = rnn_postgemm_dispatcher; +using rnn_postgemm_bwd_bf16_t = rnn_postgemm_dispatcher; + +using rnn_postgemm_fwd_u8_t = rnn_postgemm_dispatcher; +using rnn_postgemm_fwd_s8_t = rnn_postgemm_dispatcher; + +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/rnn/ref_rnn.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/rnn/ref_rnn.hpp new file mode 100644 index 0000000000000000000000000000000000000000..97d3c6b60bbcc4f1221cdabfcc98d80cca53c5f1 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/rnn/ref_rnn.hpp @@ -0,0 +1,751 @@ +/******************************************************************************* +* Copyright 2018-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_RNN_REF_RNN_HPP +#define CPU_RNN_REF_RNN_HPP + +#include +#include + +#include "common/c_types_map.hpp" +#include "common/memory_tracking.hpp" +#include "common/primitive.hpp" +#include "common/reorder.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/gemm/gemm.hpp" +#include "cpu/gemm/os_blas.hpp" + +#include "cpu/rnn/cpu_rnn_pd.hpp" +#include "cpu/rnn/postgemm_dispatcher.hpp" +#if DNNL_X64 +#include "cpu/x64/rnn/rnn_brgemm_utils.hpp" +#endif +#include "cpu/rnn/rnn_utils.hpp" +namespace dnnl { +namespace impl { +namespace cpu { + +namespace { +template +// The loop body needs to be put in a function as some versions of icc have +// an issue with lambdas & macros inside omp simd loops +inline void body_loop(int i, int k, const gates_t *ws_gates, acc_t *diff_bias, + const rnn_utils::rnn_conf_t &rnn, + rnn_utils::cell_position_t cell_position) { + if (rnn.diff_weights_overwrite && (cell_position & rnn_utils::last_iter)) + diff_bias[i * rnn.dhc + k] = 0.0f; + for (int j = 0; j < rnn.mb; j++) + diff_bias[i * rnn.dhc + k] + += ws_gates[j * rnn.scratch_gates_ld + i * rnn.dhc + k]; +} +} // namespace + +template +void gates_reduction(const rnn_utils::rnn_conf_t &rnn, + rnn_utils::cell_position_t cell_position, const gates_t *ws_gates_, + acc_t *diff_bias_) { + + // @todo block k on simd-width to enable vectorization in + // parallel_nd path +#if DNNL_CPU_RUNTIME == DNNL_RUNTIME_OMP && _OPENMP >= 201307 \ + && (!defined(__INTEL_COMPILER) || __INTEL_COMPILER < 1910) +#pragma omp parallel for simd collapse(2) + for (int i = 0; i < rnn.n_gates; i++) + for (int k = 0; k < rnn.dhc; k++) + body_loop(i, k, ws_gates_, diff_bias_, rnn, cell_position); +#else + parallel_nd(rnn.n_gates, rnn.dhc, [&](dim_t i, dim_t k) { + body_loop(i, k, ws_gates_, diff_bias_, rnn, cell_position); + }); +#endif +} + +template +struct _ref_rnn_common_t : public primitive_t { + static constexpr impl::data_type_t scratch_type + = aprop == prop_kind::forward ? acc_type : src_type; + + /* These types are defined for each element in the cell execution */ + typedef typename prec_traits::type src_layer_t; + typedef typename prec_traits::type src_iter_t; + typedef typename prec_traits::type dst_layer_t; + typedef typename prec_traits::type dst_iter_t; + typedef typename prec_traits::type weights_t; + typedef typename prec_traits::type gemm_data_t; + typedef typename prec_traits::type gemm_acc_t; + typedef typename prec_traits::type scratch_t; + typedef typename prec_traits::type ht_t; + typedef typename prec_traits::type gates_t; + + using class_name + = _ref_rnn_common_t; +#if DNNL_X64 + using ref_rnn_brgemm_t = x64::rnn_brgemm_utils::rnn_brgemm_t; +#endif + + typedef rnn_cell_execution_sig((class_name::*cell_execution_f)); + typedef rnn_grid_execution_sig((class_name::*grid_execution_f)); + typedef rnn_merged_layer_execution_sig( + (class_name::*merged_layer_execution_f)); + + typedef rnn_gemm_sig((class_name::*gemm_t)); + typedef rnn_bias_prepare_sig((class_name::*bias_prepare_t)); + typedef rnn_bias_finalize_sig((class_name::*bias_finalize_t)); + typedef rnn_weights_assign_sig((class_name::*weights_assign_t)); + + using base_pd_t = + typename utils::conditional::type; + + struct pd_t : public base_pd_t { + using base_pd_t::base_pd_t; + + const char *impl_name() const { +#if DNNL_X64 + using namespace dnnl::impl::cpu::x64; + return rnn_.is_brgemm + ? JIT_IMPL_NAME_HELPER("brgemm:", rnn_.brgemm_isa, "") + : "ref"; +#else + return "ref"; +#endif + } + + DECLARE_COMMON_PD_T(impl_name(), class_name, USE_GLOBAL_SCRATCHPAD); + + status_t init_ref(engine_t *engine) { + using namespace prop_kind; + using namespace utils; + using namespace format_tag; + using namespace rnn_utils; + const alg_kind_t cell_kind = this->desc()->cell_kind; + + const data_type_t src_layer_dt + = this->desc()->src_layer_desc.data_type; + const data_type_t weights_iter_dt + = this->desc()->weights_iter_desc.data_type; + const data_type_t weights_layer_dt + = this->desc()->weights_layer_desc.data_type; + + bool ok = true + && one_of(cell_kind, alg_kind::vanilla_rnn, + alg_kind::vanilla_lstm, alg_kind::vanilla_gru, + alg_kind::lbr_gru, alg_kind::vanilla_augru, + alg_kind::lbr_augru) + && IMPLICATION(aprop == prop_kind::forward, + one_of(this->desc()->prop_kind, forward_training, + forward_inference)) + && IMPLICATION(aprop == backward, + one_of(this->desc()->prop_kind, backward)) + && src_layer_dt == src_type + && everyone_is( + weights_type, weights_iter_dt, weights_layer_dt) + && this->set_default_params() == status::success + && this->with_bias(); + + if (!ok) return status::unimplemented; + + rnn_ = zero(); + rnn_.is_brgemm = false; + ok = init_conf(rnn_, *this->desc(), *this->attr(), + this->src_md(0), this->src_md(1), this->src_md(2), + this->weights_md(0), this->weights_md(1), + this->arg_md(DNNL_ARG_WEIGHTS_PROJECTION), this->dst_md(0), + this->dst_md(1), this->dst_md(2), + this->arg_md(DNNL_ARG_BIAS)); + if (!ok) return status::unimplemented; + + if (rnn_.is_bf16_conf()) { + if (!utils::one_of( + rnn_.bias_dt, data_type::bf16, data_type::f32) + || rnn_.src_iter_c_dt != rnn_.dst_iter_c_dt + || !utils::one_of(rnn_.src_iter_c_dt, data_type::undef, + data_type::bf16, data_type::f32)) + return status::unimplemented; + } else if (rnn_.bias_dt != data_type::f32 + || !utils::one_of(rnn_.src_iter_c_dt, data_type::undef, + data_type::f32) + || rnn_.src_iter_c_dt != rnn_.dst_iter_c_dt) + return status::unimplemented; + + /* check that no data shift have been passed to s8s8 lstm */ + if (!IMPLICATION(rnn_.is_signed_int8_conf(), + this->attr()->rnn_data_qparams_.shift_ == 0.f)) + return status::unimplemented; + + /* check that only supported attr have been passed */ + primitive_attr_t::skip_mask_t attr_mask + = primitive_attr_t::skip_mask_t::rnn_tparams; + if (weights_layer_dt == data_type::s8) + attr_mask = attr_mask + | primitive_attr_t::skip_mask_t::rnn_data_qparams + | primitive_attr_t::skip_mask_t::rnn_weights_qparams + | primitive_attr_t::skip_mask_t:: + rnn_weights_projection_qparams; + ok = ok && this->attr()->has_default_values(attr_mask); + if (!ok) return status::unimplemented; + + // Set weights descriptors to desired format + memory_desc_t new_weights_layer_md = *this->weights_md(0); + CHECK(set_expected_desc(rnn_, new_weights_layer_md, + rnn_utils::weights_type_t::layer)); + if (this->weights_layer_md_.format_kind == format_kind::any) { + this->weights_layer_md_ = new_weights_layer_md; + } else if (this->weights_layer_md_.format_kind + == format_kind::rnn_packed) { + if (this->weights_layer_md_ != new_weights_layer_md) + return status::unimplemented; + } + + memory_desc_t new_weights_iter_md = *this->weights_md(1); + CHECK(set_expected_desc(rnn_, new_weights_iter_md, + rnn_utils::weights_type_t::iter)); + if (this->weights_iter_md_.format_kind == format_kind::any) { + this->weights_iter_md_ = new_weights_iter_md; + } else if (this->weights_iter_md_.format_kind + == format_kind::rnn_packed) { + if (this->weights_iter_md_ != new_weights_iter_md) + return status::unimplemented; + } + + if (rnn_.is_lstm_projection) { + memory_desc_t new_weights_projection_md + = *this->arg_md(DNNL_ARG_WEIGHTS_PROJECTION); + CHECK(set_expected_desc(rnn_, new_weights_projection_md, + rnn_utils::weights_type_t::projection)); + if (this->weights_projection_md_.format_kind + == format_kind::any) { + this->weights_projection_md_ = new_weights_projection_md; + } else if (this->weights_projection_md_.format_kind + == format_kind::rnn_packed) { + if (this->weights_projection_md_ + != new_weights_projection_md) + return status::unimplemented; + } + } + + CHECK(this->check_layout_consistency(false /*is_brgemm*/)); + + set_conf(rnn_, *this->desc(), this->weights_md(0), + this->weights_md(1), + this->arg_md(DNNL_ARG_WEIGHTS_PROJECTION), + this->diff_weights_md(0), this->diff_weights_md(1), + this->arg_md(DNNL_ARG_DIFF_WEIGHTS_PROJECTION)); + set_workspace_sizes(rnn_, *this->desc()); + return status::success; + } + + status_t init_brgemm(engine_t *engine) { + using namespace prop_kind; + using namespace utils; + using namespace format_tag; + using namespace rnn_utils; +#if DNNL_X64 + using namespace x64; + const alg_kind_t cell_kind = this->desc()->cell_kind; + + const data_type_t src_layer_dt + = this->desc()->src_layer_desc.data_type; + const data_type_t weights_iter_dt + = this->desc()->weights_iter_desc.data_type; + const data_type_t weights_layer_dt + = this->desc()->weights_layer_desc.data_type; + + bool ok = one_of(cell_kind, alg_kind::vanilla_rnn, + alg_kind::vanilla_lstm, alg_kind::vanilla_gru, + alg_kind::vanilla_augru) + && IMPLICATION(aprop == prop_kind::forward, + one_of(this->desc()->prop_kind, forward_training, + forward_inference)) + && IMPLICATION(aprop == backward, + one_of(this->desc()->prop_kind, backward)) + // TODO: Enable diff_weights_overwrite support + && IMPLICATION(aprop == backward, + this->diff_weights_overwrite() == false) + // cell_type (or src_type) and primitive data type should + // match, except for the bf32 case. + && IMPLICATION( + this->attr()->fpmath_mode_ == fpmath_mode::strict, + src_layer_dt == src_type + && everyone_is(weights_type, + weights_iter_dt, weights_layer_dt)) + && this->set_default_params() == status::success + && this->with_bias(); + + if (!ok) return status::unimplemented; + + rnn_ = zero(); + rnn_.is_brgemm = true; + ok = init_conf(rnn_, *this->desc(), *this->attr(), + this->src_md(0), this->src_md(1), this->src_md(2), + this->weights_md(0), this->weights_md(1), + this->arg_md(DNNL_ARG_WEIGHTS_PROJECTION), this->dst_md(0), + this->dst_md(1), this->dst_md(2), + this->arg_md(DNNL_ARG_BIAS)); + + ok = ok + && IMPLICATION(one_of(this->desc()->prop_kind, + forward_training, backward), + (rnn_.is_bf16_conf() || rnn_.is_f32_conf())); + + if (!ok) return status::unimplemented; + + // Support for GRU / AUGRU cell in BRGEMM-based implementation is + // limited by forward_inference pass for now, all_f32 is disabled + // due to performance degradation. + // TODO: Improve GRU / AUGRU coverage in BRGEMM-based implementation + ok = IMPLICATION(rnn_.is_orig_gru, + this->desc()->prop_kind == forward_inference + && !rnn_.is_cell_dt_f32()); + if (!ok) return status::unimplemented; + + if (rnn_.is_cell_dt_f32() + && utils::one_of(this->desc()->prop_kind, backward, + forward_training)) + return status::unimplemented; + + if (!(IMPLICATION((cell_kind == alg_kind::vanilla_lstm + && rnn_.is_lstm_projection), + this->desc()->prop_kind == forward_inference))) + return status::unimplemented; + + if (rnn_.is_bf16_conf()) { + if (!mayiuse(avx512_core_bf16) + || !utils::one_of( + rnn_.bias_dt, data_type::bf16, data_type::f32) + || rnn_.src_iter_c_dt != rnn_.dst_iter_c_dt + || !utils::one_of(rnn_.src_iter_c_dt, data_type::undef, + data_type::bf16, data_type::f32)) + return status::unimplemented; + } else if (rnn_.bias_dt != data_type::f32 + || !utils::one_of(rnn_.src_iter_c_dt, data_type::undef, + data_type::f32) + || rnn_.src_iter_c_dt != rnn_.dst_iter_c_dt) + return status::unimplemented; + const auto isa = get_max_cpu_isa(); + if (rnn_.is_signed_int8_conf() + && !is_superset(isa, avx512_core_amx)) + return status::unimplemented; + if (rnn_.is_int8_conf() && !is_superset(isa, avx512_core_vnni)) + return status::unimplemented; + if (rnn_.is_f32_conf() && !is_superset(isa, avx2)) + return status::unimplemented; + + /* check that no shift have been passed to s8s8 amx lstm */ + if (!IMPLICATION(rnn_.is_signed_int8_conf(), + this->attr()->rnn_data_qparams_.shift_ == 0)) + return status::unimplemented; + + /* check that only supported attr have been passed */ + primitive_attr_t::skip_mask_t attr_mask + = primitive_attr_t::skip_mask_t::rnn_tparams; + if (weights_layer_dt == data_type::s8) + attr_mask = attr_mask + | primitive_attr_t::skip_mask_t::rnn_data_qparams + | primitive_attr_t::skip_mask_t::rnn_weights_qparams + | primitive_attr_t::skip_mask_t:: + rnn_weights_projection_qparams; + ok = ok && this->attr()->has_default_values(attr_mask); + if (!ok) return status::unimplemented; + + set_conf(rnn_, *this->desc(), this->weights_md(0), + this->weights_md(1), + this->arg_md(DNNL_ARG_WEIGHTS_PROJECTION), + this->diff_weights_md(0), this->diff_weights_md(1), + this->arg_md(DNNL_ARG_DIFF_WEIGHTS_PROJECTION)); + + CHECK(ref_rnn_brgemm_t::configure_brgemm(rnn_, + this->desc()->cell_kind, sizeof(src_layer_t), + sizeof(scratch_t))); + + // must be called after configure_brgemm() + set_workspace_sizes(rnn_, *this->desc()); + + // Only AMX LSTM supports s8s8 now + if (rnn_.is_signed_int8_conf() && !rnn_.is_cell_int8_amx()) + return status::unimplemented; + + // Set weights descriptors to desired format + memory_desc_t new_weights_layer_md = *this->weights_md(0); + CHECK(set_expected_desc(rnn_, new_weights_layer_md, + rnn_utils::weights_type_t::layer)); + if (this->weights_layer_md_.format_kind == format_kind::any) { + this->weights_layer_md_ = new_weights_layer_md; + } else if (this->weights_layer_md_ != new_weights_layer_md) { + return status::unimplemented; + } + + memory_desc_t new_weights_iter_md = *this->weights_md(1); + CHECK(set_expected_desc(rnn_, new_weights_iter_md, + rnn_utils::weights_type_t::iter)); + if (this->weights_iter_md_.format_kind == format_kind::any) { + this->weights_iter_md_ = new_weights_iter_md; + } else if (this->weights_iter_md_ != new_weights_iter_md) { + return status::unimplemented; + } + if (rnn_.is_lstm_projection) { + memory_desc_t new_weights_projection_md + = *this->arg_md(DNNL_ARG_WEIGHTS_PROJECTION); + CHECK(set_expected_desc(rnn_, new_weights_projection_md, + rnn_utils::weights_type_t::projection)); + if (this->weights_projection_md_.format_kind + == format_kind::any) { + this->weights_projection_md_ = new_weights_projection_md; + } else if (this->weights_projection_md_ + != new_weights_projection_md) { + return status::unimplemented; + } + } + if (rnn_.is_unsigned_int8_conf()) { + const memory_desc_wrapper &weights_layer_d( + this->weights_layer_md_); + const memory_desc_wrapper &weights_iter_d( + this->weights_iter_md_); + const auto &pdims_l = weights_layer_d.padded_dims(); + const auto &pdims_i = weights_iter_d.padded_dims(); + rnn_.weights_layer_comp_offset = rnn_.n_layer * rnn_.n_dir + * rnn_.n_gates * pdims_l[2] * pdims_l[4]; + rnn_.weights_iter_comp_offset = rnn_.n_layer * rnn_.n_dir + * rnn_.n_gates * pdims_i[2] * pdims_i[4]; + if (rnn_.is_lstm_projection) { + const memory_desc_wrapper &weights_proj_d( + this->weights_projection_md_); + const auto &pdims_p = weights_proj_d.padded_dims(); + rnn_.weights_projection_comp_offset = rnn_.n_layer + * rnn_.n_dir * pdims_p[2] * pdims_p[3]; + } else { + rnn_.weights_projection_comp_offset = 0; + } + } + CHECK(this->check_layout_consistency(true /*is_brgemm*/)); + + if (rnn_.is_bf32()) { + const memory_desc_wrapper weights_layer_d( + this->weights_layer_md_); + memory_desc_t weights_layer_md; + const memory_desc_wrapper weights_iter_d( + this->weights_iter_md_); + memory_desc_t weights_iter_md; + + const auto bf16_tag = rnn_.n_block == 64 + ? format_tag::ldgOI64o2i + : format_tag::ldgOI32o2i; + CHECK(memory_desc_init_by_tag(weights_layer_md, + weights_layer_d.ndims(), weights_layer_d.dims(), + data_type::bf16, bf16_tag)); + CHECK(reorder_primitive_desc_create(bf32_wei_layer_reorder_pd_, + engine, weights_layer_d.md_, &weights_layer_md, + nullptr)); + + CHECK(memory_desc_init_by_tag(weights_iter_md, + weights_iter_d.ndims(), weights_iter_d.dims(), + data_type::bf16, bf16_tag)); + CHECK(reorder_primitive_desc_create(bf32_wei_iter_reorder_pd_, + engine, weights_iter_d.md_, &weights_iter_md, nullptr)); + } + + return status::success; +#else + return status::unimplemented; +#endif + } + + status_t init(engine_t *engine) { + status_t st = init_brgemm(engine); + if (st != status::success) { + rnn_.is_brgemm = false; + st = init_ref(engine); + } + if (st == status::success) { + size_t scratchpad_sz {0}, ws_sz {0}; + get_scratchpad_and_workspace_sizes(rnn_, scratchpad_sz, ws_sz); + + init_scratchpad(scratchpad_sz); + // initialize the workspace if needed + if (rnn_.is_training) { + dims_t ws_dims = {(dim_t)ws_sz}; + CHECK(memory_desc_init_by_tag(this->ws_md_, 1, ws_dims, + data_type::u8, format_tag::x)); + } + } + return st; + } + + rnn_utils::rnn_conf_t rnn_; +#if DNNL_X64 + std::shared_ptr bf32_wei_layer_reorder_pd_; + std::shared_ptr bf32_wei_iter_reorder_pd_; +#endif + private: + void init_scratchpad(size_t scratchpad_sz) { + using namespace memory_tracking::names; + auto scratchpad = this->scratchpad_registry().registrar(); + + { + static constexpr size_t data_size + = 1; // "true" data size already incorporated + static constexpr size_t data_align + = alignof(float); // "worst" case scenario + static constexpr size_t perf_align = 4096; + scratchpad.book(key_rnn_space, scratchpad_sz, data_size, + data_align, perf_align); + } + + const int max_nparts + = utils::one_of(this->cell_kind(), alg_kind::vanilla_gru, + alg_kind::vanilla_augru) + ? 2 + : 1; + const int ptr_wei_sz = rnn_.n_layer * rnn_.n_dir * max_nparts; + scratchpad.template book( + key_rnn_ptrs_wei_layer, ptr_wei_sz); + scratchpad.template book( + key_rnn_ptrs_wei_iter, ptr_wei_sz); + scratchpad.template book( + key_rnn_ptrs_wei_projection, ptr_wei_sz); + + const auto bias_dt_size = types::data_type_size( + this->arg_md(DNNL_ARG_BIAS)->data_type); + scratchpad.template book( + key_rnn_ptrs_bia, ptr_wei_sz * bias_dt_size); + + scratchpad.template book( + key_rnn_gates, rnn_.scratch_gates_size); + scratchpad.template book(key_rnn_ht, rnn_.scratch_ht_size); + scratchpad.template book( + key_rnn_diff_ht, rnn_.scratch_diff_ht_size); + scratchpad.template book( + key_rnn_cell, rnn_.scratch_cell_size); + +#if DNNL_X64 + if (rnn_.is_brgemm) { + ref_rnn_brgemm_t::init_scratchpad(rnn_, scratchpad, + sizeof(gemm_acc_t), alignof(gemm_acc_t)); + if (rnn_.is_bf32()) { + scratchpad.book(key_nested_multiple + 0, + bf32_wei_layer_reorder_pd_->scratchpad_registry()); + scratchpad.book(key_nested_multiple + 1, + bf32_wei_iter_reorder_pd_->scratchpad_registry()); + } + } +#endif + } + }; + + _ref_rnn_common_t(const pd_t *apd) + : primitive_t(apd), rnn_postgemm_(nullptr) {} + + status_t init(engine_t *engine) override { + /// @todo set max_feature_size assuming that we limit the number of + /// iterations and layer to one if slc != dhc and sic != dhc + /// respectively + + bias_preparation_func = &class_name::bias_prepare; + bias_finalization_func = &class_name::bias_finalize; + + const auto set_gemm_funcs + = [](bool packed_gemm, gemm_t &g, weights_assign_t &a, + bool is_brgemm) { + if (packed_gemm) { + g = &class_name::packed_gemm; + a = &class_name::assign_packed_weights; + } else { + g = (!is_brgemm) ? &class_name::gemm : nullptr; + a = &class_name::assign_weights; + } + }; + set_gemm_funcs(pd()->rnn_.use_iter_packed_gemm, gemm_iter_func, + weights_iter_assign_func, pd()->rnn_.is_brgemm); + + set_gemm_funcs(pd()->rnn_.use_layer_packed_gemm, gemm_layer_func, + weights_layer_assign_func, pd()->rnn_.is_brgemm); + + if (pd()->rnn_.is_lstm_projection) { + set_gemm_funcs(pd()->rnn_.use_projection_packed_gemm, + gemm_projection_func, weights_projection_assign_func, + pd()->rnn_.is_brgemm); + } + + rnn_postgemm_ = new rnn_postgemm_dispatcher(pd()->rnn_, pd()); + assert(rnn_postgemm_ != nullptr); + CHECK(rnn_postgemm_->init(pd()->rnn_)); + switch (pd()->cell_kind()) { + case alg_kind::vanilla_rnn: + case alg_kind::vanilla_lstm: + cell_func = (pd()->rnn_.is_brgemm) + ? (aprop == prop_kind::forward + ? &class_name::cell_execution_brgemm_fwd + : &class_name:: + cell_execution_brgemm_bwd) + : &class_name::cell_execution_ref; + break; + case alg_kind::vanilla_gru: + case alg_kind::vanilla_augru: + cell_func = (pd()->rnn_.is_brgemm) + ? &class_name::cell_execution_brgemm_fwd + : &class_name::cell_execution_gru; + break; + case alg_kind::lbr_augru: + case alg_kind::lbr_gru: + cell_func = &class_name::cell_execution_gru_lbr; + break; + default: break; + } + + merged_layer_func = pd()->rnn_.is_brgemm && pd()->rnn_.merge_gemm_layer + && aprop == prop_kind::forward + ? &class_name::merged_layer_brgemm_fwd + : &class_name::merged_layer_execution_ref; + grid_computation = &class_name::linear_execution; + + size_t scratchpad_size, workspace_size; + rnn_utils::set_offsets(pd()->rnn_, ws_gates_offset_, ws_ht_offset_, + ws_states_layer_offset_, ws_states_iter_offset_, + ws_states_iter_c_offset_, ws_diff_states_layer_offset_, + ws_diff_states_iter_offset_, ws_diff_states_iter_c_offset_, + ws_grid_comp_offset_, ws_bias_offset_, scratch_gates_offset_, + scratch_ht_offset_, scratch_diff_ht_offset_, + scratch_cell_offset_, scratchpad_size, workspace_size); +#if DNNL_X64 + const auto rnn = pd()->rnn_; + if (rnn.is_brgemm) { + if (rnn.is_bf32()) { + + CHECK(pd()->bf32_wei_layer_reorder_pd_->create_primitive( + bf32_wei_layer_reorder_, engine)); + + CHECK(pd()->bf32_wei_iter_reorder_pd_->create_primitive( + bf32_wei_iter_reorder_, engine)); + } + return rnn_brgemm_.init_kernels(rnn, src_type, weights_type); + } +#endif + return status::success; + } + + ~_ref_rnn_common_t() { delete rnn_postgemm_; } + + status_t execute(const exec_ctx_t &ctx) const override; + +private: +#if DNNL_X64 + ref_rnn_brgemm_t rnn_brgemm_; + std::shared_ptr bf32_wei_layer_reorder_; + std::shared_ptr bf32_wei_iter_reorder_; +#endif + + rnn_grid_execution_sig(linear_execution); + rnn_cell_execution_sig(cell_execution_ref); + rnn_merged_layer_execution_sig(merged_layer_execution_ref); + rnn_cell_execution_sig(cell_execution_brgemm_fwd); + rnn_merged_layer_execution_sig(merged_layer_brgemm_fwd); + rnn_cell_execution_sig(cell_execution_brgemm_bwd); + + rnn_cell_execution_sig(cell_execution_gru); + rnn_cell_execution_sig(cell_execution_gru_lbr); + rnn_gemm_sig(gemm); + rnn_gemm_sig(packed_gemm); + rnn_bias_prepare_sig(bias_prepare); + rnn_bias_finalize_sig(bias_finalize); + rnn_weights_assign_sig(assign_weights); + rnn_weights_assign_sig(assign_packed_weights); + + float (*activation_func)(float s, float alpha, float cliping); + + template + void copy_init_layer(const rnn_utils::rnn_conf_t &rnn, + src_layer_t *ws_states_layer_, gemm_acc_t *ws_diff_states_layer_, + const input_t *xt_, const gemm_acc_t *diff_dst_layer) const; + + template + void copy_init_iter(const rnn_utils::rnn_conf_t &rnn, + src_iter_t *ws_states_iter_, void *ws_states_iter_c_, + gemm_acc_t *ws_diff_states_iter_, + gemm_acc_t *ws_diff_states_iter_c_, const input_t *src_iter_, + const void *src_iter_c_, const gemm_acc_t *diff_dst_iter_, + const float *diff_dst_iter_c_) const; + + template + void copy_res_layer(const rnn_utils::rnn_conf_t &rnn, + dst_layer_dt *dst_layer_, gemm_acc_t *diff_src_layer_, + const dst_iter_dt *dst_iter_, const src_layer_t *ws_states_layer_, + const gemm_acc_t *ws_diff_states_layer_) const; + + template + void copy_res_iter(const rnn_utils::rnn_conf_t &rnn, + prim_dst_iter_t *dst_iter_, void *dst_iter_c_, + gemm_acc_t *diff_src_iter_, float *diff_src_iter_c_, + const prim_dst_layer_t *dst_layer_, + const src_iter_t *ws_states_iter_, const void *ws_states_iter_c, + const gemm_acc_t *ws_diff_states_iter_, + const gemm_acc_t *ws_diff_states_iter_c_) const; + + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + size_t ws_gates_offset_; + size_t ws_ht_offset_; + size_t ws_states_layer_offset_; + size_t ws_states_iter_offset_; + size_t ws_states_iter_c_offset_; + size_t ws_bias_offset_; + size_t ws_diff_states_layer_offset_; + size_t ws_diff_states_iter_offset_; + size_t ws_diff_states_iter_c_offset_; + size_t ws_grid_comp_offset_; + size_t scratch_gates_offset_; + size_t scratch_ht_offset_; + size_t scratch_diff_ht_offset_; + size_t scratch_cell_offset_; + rnn_postgemm_dispatcher + *rnn_postgemm_; + + grid_execution_f grid_computation; + cell_execution_f cell_func; + merged_layer_execution_f merged_layer_func; + + bias_prepare_t bias_preparation_func; + bias_finalize_t bias_finalization_func; + weights_assign_t weights_layer_assign_func; + weights_assign_t weights_iter_assign_func; + weights_assign_t weights_projection_assign_func; + + gemm_t gemm_layer_func; + gemm_t gemm_iter_func; + gemm_t gemm_projection_func; +}; + +using ref_rnn_fwd_f32_t = _ref_rnn_common_t; +using ref_rnn_bwd_f32_t = _ref_rnn_common_t; +using ref_rnn_fwd_bf16_t = _ref_rnn_common_t; +using ref_rnn_bwd_bf16_t = _ref_rnn_common_t; +using ref_rnn_fwd_u8s8_t = _ref_rnn_common_t; +using ref_rnn_fwd_s8s8_t = _ref_rnn_common_t; +} // namespace cpu +} // namespace impl +} // namespace dnnl +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/rnn/rnn_reorders.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/rnn/rnn_reorders.hpp new file mode 100644 index 0000000000000000000000000000000000000000..4132b285f159eb1382e52e4444e5e47630cf235a --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/rnn/rnn_reorders.hpp @@ -0,0 +1,975 @@ +/******************************************************************************* +* Copyright 2018-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_RNN_RNN_REORDERS_HPP +#define CPU_RNN_RNN_REORDERS_HPP + +#include + +#include "common/bfloat16.hpp" +#include "common/dnnl_thread.hpp" +#include "common/primitive.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/platform.hpp" +#include "cpu/reorder/cpu_reorder_pd.hpp" +#include "cpu/simple_q10n.hpp" + +#include "cpu/gemm/gemm_pack.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { + +static inline void init_dims(dim_t &L, dim_t &D, dim_t &I, dim_t &G, dim_t &O, + const memory_desc_wrapper &mdw) { + const auto dims = mdw.dims(); + const auto ndims = mdw.ndims(); + L = dims[0]; + D = dims[1]; + I = dims[2]; + G = 0; + O = 0; + // weights_layer/weights_iter case + if (ndims == 5) { + G = dims[3]; + O = dims[4]; + } + // projection weights case + if (ndims == 4) { + G = 1; + O = dims[3]; + } + assert(G != 0 && O != 0); +}; + +template +static inline void quantize_igo(int8_t *scratch_quantized, + const memory_desc_wrapper &src_d, const float *src, int mask, + float *scales) { + typedef typename prec_traits::type in_data_t; + + // TODO: trivial strides assumes here. + // Use proper strides where appropriate + dim_t L, D, I, G, O; + init_dims(L, D, I, G, O, src_d); + + assert(scales != nullptr); + parallel(0, [&](const int ithr, const int nthr) { + dim_t start {0}, end {0}; + balance211(L * D * I, nthr, ithr, start, end); + for (int ldi = start; ldi < end; ldi++) { + for (int go = 0; go < G * O; go++) { + const float s = scales[(mask == 0) ? 0 : go]; + scratch_quantized[ldi * G * O + go] + = qz_b0()(src[ldi * G * O + go], s); + } + } + }); +} + +template +static inline void quantize_goi(int8_t *scratch_quantized, + const memory_desc_wrapper &src_d, const float *src, int mask, + float *scales) { + typedef typename prec_traits::type in_data_t; + + // TODO: trivial strides assumes here. + // Use proper strides where appropriate + dim_t L, D, I, G, O; + init_dims(L, D, I, G, O, src_d); + + assert(scales != nullptr); + parallel_nd(L * D, G * O, [&](dim_t ld, dim_t go) { + const float s = scales[(mask == 0) ? 0 : go]; + PRAGMA_OMP_SIMD() + for (dim_t i = 0; i < I; i++) { + scratch_quantized[ld * I * G * O + i * G * O + go] + = qz_b0()( + src[ld * G * O * I + go * I + i], s); + } + }); +} + +static inline void compensate_igo(float *compensation, + const memory_desc_wrapper &src_d, int8_t *scratch_quantized, + int32_t *scratch_compensation, size_t scratch_comp_sz, int nthr) { + // TODO: trivial strides assumed here. + // Use proper strides where appropriate + dim_t L, D, I, G, O; + init_dims(L, D, I, G, O, src_d); + + // We parallelize on LD and GO + // TODO: maybe restrict parallelism as we might have large + // parallelisation overhead if dimensions are small + const int LD_nthr = nstl::min(L * D, dim_t(nthr)); + const int GO_nthr = nstl::min(G * O, dim_t(nthr / LD_nthr)); + parallel(nthr, [&](const int ithr, const int nthr) { + int LD_ithr = -1; + int GO_ithr = -1; + dim_t LD_s = -1, LD_e = -1; + dim_t GO_s = -1, GO_e = -1; + if (ithr < LD_nthr * GO_nthr) { + LD_ithr = ithr % LD_nthr; + GO_ithr = ithr / LD_nthr; + balance211(L * D, LD_nthr, LD_ithr, LD_s, LD_e); + balance211(G * O, GO_nthr, GO_ithr, GO_s, GO_e); + } + int32_t *compensation_s32 + = scratch_compensation + ithr * scratch_comp_sz; + for (int ld = LD_s; ld < LD_e; ld++) { + if (I == 1) { + PRAGMA_OMP_SIMD() + for (int go = GO_s; go < GO_e; go++) + compensation[ld * G * O + go] = saturate( + scratch_quantized[ld * I * G * O + go]); + } else { + // We split the loop on I in three to avoid conditionals or zeroing compensation + int i = 0; + PRAGMA_OMP_SIMD() + for (int go = GO_s; go < GO_e; go++) + compensation_s32[go] + = scratch_quantized[go + G * O * (i + I * (ld))]; + // 1 <= i < I-1 + for (i = 1; i < I - 1; i++) { + PRAGMA_OMP_SIMD() + for (int go = GO_s; go < GO_e; go++) + compensation_s32[go] += scratch_quantized[go + + G * O * (i + I * (ld))]; + } + // i = I-1 + PRAGMA_OMP_SIMD() + for (int go = GO_s; go < GO_e; go++) + compensation[ld * G * O + go] = saturate( + compensation_s32[go] + + scratch_quantized[go + G * O * (i + I * (ld))]); + } + } + }); +} + +static inline void compensate_goi(float *compensation, + const memory_desc_wrapper &src_d, int8_t *scratch_quantized) { + // TODO: trivial strides assumed here. + // Use proper strides where appropriate + dim_t L, D, I, G, O; + init_dims(L, D, I, G, O, src_d); + + parallel_nd(L * D, G * O, [&](dim_t ld, dim_t go) { + int32_t compensation_s32 = 0; + PRAGMA_OMP_SIMD() + for (dim_t i = 0; i < I; i++) { + compensation_s32 + += scratch_quantized[ld * I * G * O + i * G * O + go]; + } + // TODO: do not convert to f32 if this compensation is not + // going to be added to a bias (e.g. like in lstm + // projection where it is directly added to the s32 + // accumulators) + compensation[ld * G * O + go] = saturate(compensation_s32); + }); +} + +template +struct rnn_data_reorder_t : public primitive_t { + struct pd_t : public cpu_reorder_pd_t { + using cpu_reorder_pd_t::cpu_reorder_pd_t; + + DECLARE_COMMON_PD_T("rnn_data_reorder", rnn_data_reorder_t); + + private: + static status_t create(reorder_pd_t **reorder_pd, engine_t *engine, + const primitive_attr_t *attr, engine_t *src_engine, + const memory_desc_t *src_md, engine_t *dst_engine, + const memory_desc_t *dst_md) { + using namespace format_tag; + using namespace status; + const memory_desc_wrapper id(src_md), od(dst_md); + + bool args_ok = true; +#define PD_CHECK_ARG(x) args_ok = args_ok && (x) + PD_CHECK_ARG(id.data_type() == type_i); + PD_CHECK_ARG(od.data_type() == type_o); + PD_CHECK_ARG(utils::one_of(id.ndims(), 3, 4)); + PD_CHECK_ARG(!id.has_runtime_dims_or_strides()); + auto skip_mask = primitive_attr_t::skip_mask_t::rnn_data_qparams + | primitive_attr_t::skip_mask_t::rnn_weights_qparams + | primitive_attr_t::skip_mask_t:: + rnn_weights_projection_qparams; + PD_CHECK_ARG(attr->has_default_values(skip_mask)); + PD_CHECK_ARG(IMPLICATION(id.ndims() == 3, + id.matches_tag(tnc) && od.matches_tag(tnc))); + PD_CHECK_ARG(IMPLICATION(id.ndims() == 4, + id.matches_tag(ldnc) && od.matches_tag(ldnc))); +#undef PD_CHECK_ARG + if (!args_ok) return invalid_arguments; + + auto _pd = new pd_t(attr, src_engine->kind(), src_md, + dst_engine->kind(), dst_md); + if (_pd == nullptr) return out_of_memory; + if (_pd->init(engine, src_engine, dst_engine) != success) { + delete _pd; + return unimplemented; + } + CHECK(_pd->init_scratchpad_md()); + return safe_ptr_assign(*reorder_pd, _pd); + } + friend dnnl::impl::impl_list_item_t; + }; + + rnn_data_reorder_t(const pd_t *apd) : primitive_t(apd) {} + +private: + typedef typename prec_traits::type in_data_t; + typedef typename prec_traits::type out_data_t; + + bool is_dense() const { + const memory_desc_wrapper &input_d = pd()->src_md(); + const memory_desc_wrapper &output_d = pd()->dst_md(); + return utils::everyone_is(1, + input_d.blocking_desc().strides[input_d.ndims() - 1], + output_d.blocking_desc().strides[output_d.ndims() - 1]); + } + + /* This function assumes that only the innermost dimension (C) is + dense (that is to say, stride is 1). This is enough to have + good performance and allow non trivial strides on other + dimensions (to allow an "optimized" path for views for + example). + */ + status_t execute_dense(out_data_t *output, const in_data_t *input, + const float scale, const float shift) const { + assert(type_i == data_type::f32); + assert(type_o == data_type::u8 || type_o == data_type::s8); + + const memory_desc_wrapper &input_d = pd()->src_md(); + const memory_desc_wrapper &output_d = pd()->dst_md(); + const dim_t outer_dim + = utils::array_product(input_d.dims(), input_d.ndims() - 1); + const dim_t inner_dim = input_d.dims()[input_d.ndims() - 1]; + + parallel(0, [&](const int ithr, const int nthr) { + dim_t start {0}, end {0}; + balance211(outer_dim, nthr, ithr, start, end); + for (int i = start; i < end; ++i) { + const dim_t off_in = input_d.off_l(i * inner_dim); + const dim_t off_out = output_d.off_l(i * inner_dim); + const in_data_t *__restrict i_ = input + off_in; + out_data_t *__restrict o_ = output + off_out; + PRAGMA_OMP_SIMD() + for (int j = 0; j < inner_dim; ++j) { + const float in = (float)i_[j] * scale + shift; + o_[j] = qz_a1b0()(in); + } + } + }); + return status::success; + } + + status_t execute_generic(out_data_t *output, const in_data_t *input, + float scale, float shift) const { + assert(type_i == data_type::f32); + assert(type_o == data_type::u8 || type_o == data_type::s8); + + const memory_desc_wrapper &input_d = pd()->src_md(); + const memory_desc_wrapper &output_d = pd()->dst_md(); + const size_t nelems = input_d.nelems(); + parallel_nd(nelems, [&](size_t i) { + const float in = (float)input[input_d.off_l(i)] * scale + shift; + output[output_d.off_l(i)] = qz_a1b0()(in); + }); + return status::success; + } + + status_t execute(const exec_ctx_t &ctx) const override { + auto input = CTX_IN_MEM(const in_data_t *, DNNL_ARG_FROM); + auto output = CTX_OUT_MEM(out_data_t *, DNNL_ARG_TO); + const float scale = pd()->attr()->rnn_data_qparams_.scale_; + const float shift = pd()->attr()->rnn_data_qparams_.shift_; + + if (is_dense()) + return execute_dense(output, input, scale, shift); + else + return execute_generic(output, input, scale, shift); + } + + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } +}; + +template +struct rnn_weights_reorder_s8_t : public primitive_t { + struct pd_t : public cpu_reorder_pd_t { + using cpu_reorder_pd_t::cpu_reorder_pd_t; + typedef dnnl_status_t (*gemm_pack_f)(const char *identifier, + const char *transa, const char *transb, const dim_t *M, + const dim_t *N, const dim_t *K, const dim_t *lda, + const dim_t *ldb, const void *src, void *dst); + + DECLARE_COMMON_PD_T("rnn_weights_reorder_s8", rnn_weights_reorder_s8_t); + + status_t init( + engine_t *engine, engine_t *src_engine, engine_t *dst_engine) { + status_t status + = cpu_reorder_pd_t::init(engine, src_engine, dst_engine); + if (status != status::success) return status; + + nthr_ = dnnl_get_max_threads(); + init_scratchpad(); + + return status::success; + } + + format_tag_t itag_ = format_tag::undef; + format_tag_t otag_ = format_tag::undef; + size_t thr_scratch_comp_sz_ = 0; + int nthr_; // To not exceed the limit in execute used for set up. + gemm_pack_f gemm_pack; + + private: + static status_t create(reorder_pd_t **reorder_pd, engine_t *engine, + const primitive_attr_t *attr, engine_t *src_engine, + const memory_desc_t *src_md, engine_t *dst_engine, + const memory_desc_t *dst_md) { + using namespace format_tag; + using namespace rnn_packed_format; + using namespace status; + const memory_desc_wrapper id(src_md), od(dst_md); + + bool args_ok = true; +#define PD_CHECK_ARG(x) args_ok = args_ok && (x) + // Fast checks + PD_CHECK_ARG(id.data_type() == type_i); + PD_CHECK_ARG(od.data_type() == data_type::s8); + PD_CHECK_ARG(od.format_kind() == format_kind::rnn_packed); + PD_CHECK_ARG(utils::one_of( + od.rnn_packed_desc().format, ldigo_p, ldio_p)); + PD_CHECK_ARG(od.ndims() == id.ndims()); + // TODO: we have to skip projection qparam even for regular lstm + // as we use the same attr for regular weights and projection + auto skip_mask = primitive_attr_t::skip_mask_t::rnn_data_qparams + | primitive_attr_t::skip_mask_t::rnn_weights_qparams + | primitive_attr_t::skip_mask_t:: + rnn_weights_projection_qparams; + PD_CHECK_ARG(attr->has_default_values(skip_mask)); + if (!args_ok) return invalid_arguments; + + // Slower checks + PD_CHECK_ARG(id.is_dense()); + if (!args_ok) return invalid_arguments; + + format_tag_t itag = id.matches_one_of_tag(ldigo, ldgoi, ldio, ldoi); + if (itag == format_tag::undef) return invalid_arguments; + + // TODO: add support for layer and direction dimensions + // weights_layer and weights_iter + if (id.ndims() == 5 + && !utils::one_of(attr->rnn_weights_qparams_.mask_, 0, 24)) + return unimplemented; + // weights_projection + if (id.ndims() == 4 + && !utils::one_of( + attr->rnn_weights_projection_qparams_.mask_, 0, 8)) + return unimplemented; + + auto _pd = new pd_t(attr, src_engine->kind(), src_md, + dst_engine->kind(), dst_md); + if (_pd == nullptr) return out_of_memory; + _pd->itag_ = itag; + if (_pd->init(engine, src_engine, dst_engine) != success) { + delete _pd; + return unimplemented; + } + CHECK(_pd->init_scratchpad_md()); + const bool is_s8s8 = dst_md->extra.flags + & memory_extra_flags::rnn_s8s8_compensation; + _pd->gemm_pack = is_s8s8 ? &gemm_s8s8s32_pack : &gemm_s8u8s32_pack; + + return safe_ptr_assign(*reorder_pd, _pd); +#undef PD_CHECK_ARG + } + + void init_scratchpad() { + using namespace format_tag; + + const memory_desc_wrapper id(src_md()); + const size_t nelems = id.nelems(); + const auto &dims = id.dims(); + + using namespace memory_tracking::names; + auto scratchpad = scratchpad_registry().registrar(); + const size_t quantization_size = nelems; + // we do not use GO directly, as this can cause false + // sharing when parallelizing on I (2 threads writing to + // the same cache line) + thr_scratch_comp_sz_ = itag_ == ldigo ? dims[3] * dims[4] : dims[3]; + thr_scratch_comp_sz_ = utils::rnd_up(thr_scratch_comp_sz_, 16); + size_t reduction_size = 0; + if (utils::one_of(itag_, ldigo, ldio)) + reduction_size = nthr_ * thr_scratch_comp_sz_; + + scratchpad.template book( + key_reorder_rnn_weights_quantization, quantization_size); + scratchpad.template book( + key_reorder_rnn_weights_reduction, reduction_size); + } + + friend dnnl::impl::impl_list_item_t; + }; + + rnn_weights_reorder_s8_t(const pd_t *apd) : primitive_t(apd) {} + +private: + typedef typename prec_traits::type in_data_t; + + status_t execute(const exec_ctx_t &ctx) const override { + // TODO: trivial strides assumed here. + // Use proper strides where appropriate + + using namespace format_tag; + + auto src = CTX_IN_MEM(const in_data_t *, DNNL_ARG_FROM); + auto dst = CTX_OUT_MEM(char *, DNNL_ARG_TO); + const memory_desc_wrapper &src_d = pd()->src_md(); + const memory_desc_wrapper &dst_d = pd()->dst_md(); + if (src_d.has_zero_dim()) { + assert(dst_d.has_zero_dim()); + return status::success; + } + + dim_t L, D, I, G, O; + init_dims(L, D, I, G, O, src_d); + + /* Quantize src & compute compensation */ + auto scratch_quantized + = (int8_t * __restrict) ctx.get_scratchpad_grantor() + .template get(memory_tracking::names:: + key_reorder_rnn_weights_quantization); + auto scratch_compensation + = (int32_t * __restrict) ctx.get_scratchpad_grantor() + .template get(memory_tracking::names:: + key_reorder_rnn_weights_reduction); + float *comp = reinterpret_cast( + dst + dst_d.rnn_packed_desc().offset_compensation); + float *scales = nullptr; + int mask = 0; + if (src_d.ndims() == 5) { + scales = pd()->attr()->rnn_weights_qparams_.scales_; + mask = pd()->attr()->rnn_weights_qparams_.mask_; + } + if (src_d.ndims() == 4) { + scales = pd()->attr()->rnn_weights_projection_qparams_.scales_; + mask = pd()->attr()->rnn_weights_projection_qparams_.mask_; + } + /* Step 1: we quantize if we need to */ + if (type_i == data_type::f32) { + switch (pd()->itag_) { + case ldigo: + case ldio: + quantize_igo(scratch_quantized, src_d, (float *)src, + mask, scales); + break; + case ldgoi: + case ldoi: + quantize_goi(scratch_quantized, src_d, (float *)src, + mask, scales); + break; + default: assert(!"Unsupported reorder"); + } + } else + scratch_quantized = (int8_t * __restrict) src; + + /* Step 2: we pre-compute the compensation */ + switch (pd()->itag_) { + case ldigo: + case ldio: + compensate_igo(comp, src_d, scratch_quantized, + scratch_compensation, pd()->thr_scratch_comp_sz_, + pd()->nthr_); + break; + case ldgoi: + case ldoi: compensate_goi(comp, src_d, scratch_quantized); break; + default: assert(!"Unsupported reorder"); + } + + /* Step 3: we pack the matrix */ + const auto off_igo = [&](dim_t l, dim_t d, dim_t i, dim_t g, dim_t o) { + return o + O * (g + G * (i + I * (d + D * l))); + }; + const int n_parts = dst_d.rnn_packed_desc().n_parts; + const size_t *size_packed_cell = dst_d.rnn_packed_desc().part_pack_size; + const int *parts = dst_d.rnn_packed_desc().parts; + const dim_t n = dst_d.rnn_packed_desc().n; + const dim_t ldb = dst_d.rnn_packed_desc().ldb; + char *to_pack = dst; + + for (dim_t l = 0; l < L; l++) { + for (dim_t d = 0; d < D; d++) { + for (dim_t p = 0; p < n_parts; p++) { + dim_t g = (p > 0) ? parts[p - 1] : 0; + dim_t m_p = parts[p] * O; + dim_t k_p = I; + dim_t lda = (dim_t)G * O; + CHECK(pd()->gemm_pack("A", "N", "N", &m_p, &n, &k_p, &lda, + &ldb, scratch_quantized + off_igo(l, d, 0, g, 0), + to_pack)); + to_pack += size_packed_cell[p]; + } + } + } + return status::success; + } + + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } +}; + +template +struct rnn_weights_reorder_t : public primitive_t { + struct pd_t : public cpu_reorder_pd_t { + using cpu_reorder_pd_t::cpu_reorder_pd_t; + + DECLARE_COMMON_PD_T("rnn_weights_reorder", rnn_weights_reorder_t); + + format_tag_t itag_; + + status_t init( + engine_t *engine, engine_t *src_engine, engine_t *dst_engine) { + status_t status + = cpu_reorder_pd_t::init(engine, src_engine, dst_engine); + if (status != status::success) return status; + + init_scratchpad(); + + return status::success; + } + + private: + static status_t create(reorder_pd_t **reorder_pd, engine_t *engine, + const primitive_attr_t *attr, engine_t *src_engine, + const memory_desc_t *src_md, engine_t *dst_engine, + const memory_desc_t *dst_md) { + using namespace format_tag; + using namespace rnn_packed_format; + using namespace status; + + const memory_desc_wrapper id(src_md), od(dst_md); + bool args_ok = true; +#define PD_CHECK_ARG(x) args_ok = args_ok && (x) + PD_CHECK_ARG(id.data_type() == type_i); + PD_CHECK_ARG(od.data_type() == type_o); + PD_CHECK_ARG(od.format_kind() == format_kind::rnn_packed); + PD_CHECK_ARG(utils::one_of( + od.rnn_packed_desc().format, ldigo_p, ldgoi_p, ldio_p)); + PD_CHECK_ARG(attr->has_default_values()); +#undef PD_CHECK_ARG + if (!args_ok) return invalid_arguments; + + format_tag_t itag = id.matches_one_of_tag(ldigo, ldgoi, ldio, ldoi); + if (itag == format_tag::undef) return invalid_arguments; + + auto _pd = new pd_t(attr, src_engine->kind(), src_md, + dst_engine->kind(), dst_md); + if (_pd == nullptr) return out_of_memory; + if (_pd->init(engine, src_engine, dst_engine) != success) { + delete _pd; + return unimplemented; + } + _pd->itag_ = itag; + CHECK(_pd->init_scratchpad_md()); + return safe_ptr_assign(*reorder_pd, _pd); + } + + void init_scratchpad() { + using namespace format_tag; + using namespace rnn_packed_format; + + const memory_desc_wrapper id(src_md()); + const memory_desc_wrapper od(dst_md()); + const rnn_packed_desc_t &rnn_pdata = od.rnn_packed_desc(); + + format_tag_t itag = id.matches_one_of_tag(ldigo, ldgoi, ldio); + const bool layout_cross_case + = (itag == ldigo && rnn_pdata.format == ldgoi_p) + || (itag == ldgoi && rnn_pdata.format == ldigo_p) + || (itag == ldio && rnn_pdata.format == ldio_p), + dt_cross_case + = type_i == data_type::f32 && type_o == data_type::bf16; + const size_t sz = id.nelems(); + + using namespace memory_tracking::names; + auto scratchpad = scratchpad_registry().registrar(); + scratchpad.template book( + key_reorder_rnn_weights_transposition, + layout_cross_case ? sz : 0); + scratchpad.template book( + key_reorder_rnn_weights_bf16_cvt, dt_cross_case ? sz : 0); + } + friend dnnl::impl::impl_list_item_t; + }; + + rnn_weights_reorder_t(const pd_t *apd) : primitive_t(apd) {} + +private: + typedef typename prec_traits::type in_data_t; + typedef typename prec_traits::type out_data_t; + + status_t execute(const exec_ctx_t &ctx) const override { + // TODO: trivial strides assumed here. + // Use proper strides where appropriate + + using namespace format_tag; + using namespace rnn_packed_format; + + auto input = CTX_IN_MEM(const in_data_t *, DNNL_ARG_FROM); + auto output = CTX_OUT_MEM(out_data_t *, DNNL_ARG_TO); + const memory_desc_wrapper &input_d = pd()->src_md(); + const memory_desc_wrapper &output_d = pd()->dst_md(); + if (input_d.has_zero_dim()) { + assert(output_d.has_zero_dim()); + return status::success; + } + + const rnn_packed_desc_t &rnn_pdata = output_d.rnn_packed_desc(); + dim_t L, D, I, G, O; + init_dims(L, D, I, G, O, input_d); + + /* Pack */ + const bool from_igo = utils::one_of(pd()->itag_, ldigo, ldio); + const bool to_igo = utils::one_of(rnn_pdata.format, ldigo_p, ldio_p); + const int n_parts = rnn_pdata.n_parts; + const size_t *size_packed_cell = rnn_pdata.part_pack_size; + const int *parts = rnn_pdata.parts; + const dim_t n = rnn_pdata.n; + + /* Convert fp32 input to bf16 */ + out_data_t *input_cvt = (out_data_t *)input; + if (type_i == data_type::f32 && type_o == data_type::bf16) { + input_cvt + = (out_data_t *)ctx.get_scratchpad_grantor() + .template get(memory_tracking::names:: + key_reorder_rnn_weights_bf16_cvt); + parallel_nd(L * D, [&](dim_t ld) { + cvt_float_to_bfloat16((bfloat16_t *)input_cvt + ld * G * O * I, + (float *)input + ld * G * O * I, G * O * I); + }); + } + + /* Transpose weights prior to packing to ensure that packed GEMM + * algorithm will be dispatched */ + out_data_t *input_tr = input_cvt; + if (from_igo != to_igo) { + input_tr + = (out_data_t *)ctx.get_scratchpad_grantor().template get( + memory_tracking::names:: + key_reorder_rnn_weights_transposition); + const dim_t M = to_igo ? G * O : I; + const dim_t N = to_igo ? I : G * O; + parallel_nd(L * D, N, [&](dim_t ld, dim_t i) { + for (dim_t j = 0; j < M; j++) { + input_tr[ld * M * N + i * M + j] + = input_cvt[ld * M * N + j * N + i]; + } + }); + } + + const auto off_igo = [&](dim_t l, dim_t d, dim_t i, dim_t g, dim_t o) { + return l * D * I * G * O + d * I * G * O + i * G * O + g * O + o; + }; + const auto off_goi = [&](dim_t l, dim_t d, dim_t i, dim_t g, dim_t o) { + return l * D * G * O * I + d * G * O * I + g * O * I + o * I + i; + }; + const dim_t lda = to_igo ? G * O : I; + const dim_t ldb = rnn_pdata.ldb; + for (dim_t l = 0; l < L; l++) { + for (dim_t d = 0; d < D; d++) { + for (dim_t p = 0; p < n_parts; p++) { + const dim_t g = (p > 0) ? parts[p - 1] : 0; + const dim_t m_p = to_igo ? parts[p] * O : I; + const dim_t k_p = to_igo ? I : parts[p] * O; + if (type_o == data_type::bf16) { + CHECK(gemm_bf16bf16f32_pack("A", "N", "N", &m_p, &n, + &k_p, &lda, &ldb, + (bfloat16_t *)&input_tr[to_igo + ? off_igo(l, d, 0, g, 0) + : off_goi(l, d, 0, g, 0)], + (bfloat16_t *)output)); + } else { + CHECK(sgemm_pack("A", "N", "N", &m_p, &n, &k_p, &lda, + &ldb, + (float *)&input_tr[to_igo + ? off_igo(l, d, 0, g, 0) + : off_goi(l, d, 0, g, 0)], + (float *)output)); + } + output += size_packed_cell[p] / sizeof(out_data_t); + } + } + } + return status::success; + } + + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } +}; + +template +struct rnn_brgemm_weights_reorder_s8_t : public primitive_t { + struct pd_t : public cpu_reorder_pd_t { + using cpu_reorder_pd_t::cpu_reorder_pd_t; + + DECLARE_COMMON_PD_T("rnn_brgemm_weights_reorder_s8_t", + rnn_brgemm_weights_reorder_s8_t); + + format_tag_t itag_; + format_tag_t otag_; + int nthr_; // To not exceed the limit in execute used for set up. + size_t thr_scratch_comp_sz_ = 0; + + status_t init( + engine_t *engine, engine_t *src_engine, engine_t *dst_engine) { + status_t status + = cpu_reorder_pd_t::init(engine, src_engine, dst_engine); + if (status != status::success) return status; + + nthr_ = dnnl_get_max_threads(); + init_scratchpad(); + + return status::success; + } + + private: + static status_t create(reorder_pd_t **reorder_pd, engine_t *engine, + const primitive_attr_t *attr, engine_t *src_engine, + const memory_desc_t *src_md, engine_t *dst_engine, + const memory_desc_t *dst_md) { + using namespace status; + using namespace format_tag; + using namespace memory_extra_flags; + + const memory_desc_wrapper id(src_md), od(dst_md); + + const bool args_ok = true && id.data_type() == type_i + && od.data_type() == data_type::s8 && id.is_dense(); + if (!args_ok) return invalid_arguments; + + const auto skip_mask + = primitive_attr_t::skip_mask_t::rnn_data_qparams + | primitive_attr_t::skip_mask_t::rnn_weights_qparams + | primitive_attr_t::skip_mask_t:: + rnn_weights_projection_qparams; + if (!attr->has_default_values(skip_mask)) return invalid_arguments; + + // TODO: add support for layer and direction dimensions + // weights_layer and weights_iter + if (id.ndims() == 5 + && !utils::one_of(attr->rnn_weights_qparams_.mask_, 0, 24)) + return unimplemented; + // weights_projection + if (id.ndims() == 4 + && !utils::one_of( + attr->rnn_weights_projection_qparams_.mask_, 0, 8)) + return unimplemented; + + // Check the proper memory desc has been passed to u8s8 and s8s8 + // Note: currently rnn_u8s8_compensation and rnn_s8s8_compensation + // have common bit so we have to perform additional checks to + // separate these two cases + const bool check_u8s8 = (od.extra().flags & rnn_u8s8_compensation) + && !types::extra_flag_rnn_s8s8_compensation_is_set( + od.extra().flags) + && od.extra().compensation_mask + == ((id.ndims() == 5) ? 27 /* 11011 */ + : 13 /* 1101 */); + const bool check_s8s8 = od.extra().flags & rnn_s8s8_compensation + && od.extra().compensation_mask == 0; + if (!(check_u8s8 || check_s8s8)) return invalid_arguments; + + auto _pd = new pd_t(attr, src_engine->kind(), src_md, + dst_engine->kind(), dst_md); + if (_pd == nullptr) return out_of_memory; + if (_pd->init(engine, src_engine, dst_engine) != success) { + delete _pd; + return unimplemented; + } + + _pd->itag_ = format_tag::undef; + + format_tag_t otag, itag; + + itag = id.matches_one_of_tag(ldigo, ldio); + otag = od.matches_one_of_tag(ldgOI64o4i, ldgOI32o4i, ldOI32o4i); + if (itag != format_tag::undef && otag != format_tag::undef) { + _pd->itag_ = itag; + _pd->otag_ = otag; + } else { + delete _pd; + return invalid_arguments; + } + CHECK(_pd->init_scratchpad_md()); + return safe_ptr_assign(*reorder_pd, _pd); + } + + void init_scratchpad() { + using namespace format_tag; + + const memory_desc_wrapper id(src_md()); + const size_t nelems = id.nelems(); + const auto &dims = id.dims(); + const auto ndims = id.ndims(); + + using namespace memory_tracking::names; + auto scratchpad = scratchpad_registry().registrar(); + const size_t quantization_size = nelems; + // we do not use GO directly, as this can cause false + // sharing when parallelizing on I (2 threads writing to + // the same cache line) + thr_scratch_comp_sz_ = (ndims == 5) ? dims[3] * dims[4] : dims[3]; + thr_scratch_comp_sz_ = utils::rnd_up(thr_scratch_comp_sz_, 16); + const size_t reduction_size = nthr_ * thr_scratch_comp_sz_; + + scratchpad.template book( + key_reorder_rnn_weights_quantization, quantization_size); + scratchpad.template book( + key_reorder_rnn_weights_reduction, reduction_size); + } + friend dnnl::impl::impl_list_item_t; + }; + + rnn_brgemm_weights_reorder_s8_t(const pd_t *apd) : primitive_t(apd) {} + +private: + typedef typename prec_traits::type in_data_t; + typedef typename prec_traits::type out_data_t; + + status_t execute(const exec_ctx_t &ctx) const override { + using namespace format_tag; + using namespace data_type; + using namespace utils; + using namespace memory_extra_flags; + + auto src = CTX_IN_MEM(const in_data_t *, DNNL_ARG_FROM); + auto dst = CTX_OUT_MEM(out_data_t *, DNNL_ARG_TO); + const memory_desc_wrapper &src_d = pd()->src_md(); + const memory_desc_wrapper &dst_d = pd()->dst_md(); + if (src_d.has_zero_dim()) { + assert(dst_d.has_zero_dim()); + return status::success; + } + + const auto &blocked_d = dst_d; + const auto &pdims = blocked_d.padded_dims(); + + const int o_block = pd()->otag_ == ldgOI64o4i ? 64 : 32; + static constexpr int i_block = 4; + + dim_t L, D, I, G, O; + init_dims(L, D, I, G, O, src_d); + + const dim_t pI = pdims[2]; + const dim_t pO = (src_d.ndims() == 5) ? pdims[4] : pdims[3]; + const dim_t IB = pI / i_block; + const dim_t OB = pO / o_block; + + const size_t compensation_offset = (size_t)L * D * G * pI * pO; + + /* Quantize src & compute compensation */ + auto scratch_quantized + = (int8_t * __restrict) ctx.get_scratchpad_grantor() + .template get(memory_tracking::names:: + key_reorder_rnn_weights_quantization); + auto scratch_compensation + = (int32_t * __restrict) ctx.get_scratchpad_grantor() + .template get(memory_tracking::names:: + key_reorder_rnn_weights_reduction); + float *comp = reinterpret_cast(dst + compensation_offset); + const bool req_s8s8_comp = (dst_d.extra().flags & rnn_u8s8_compensation) + && !types::extra_flag_rnn_s8s8_compensation_is_set( + dst_d.extra().flags); + const auto mask_ok = [&](int mask) { + return mask + == ((src_d.ndims() == 5) ? 27 /* 11011 */ + : 13 /* 1101 */); + }; + + float *scales = nullptr; + int mask = 0; + if (src_d.ndims() == 5) { + scales = pd()->attr()->rnn_weights_qparams_.scales_; + mask = pd()->attr()->rnn_weights_qparams_.mask_; + } + if (src_d.ndims() == 4) { + scales = pd()->attr()->rnn_weights_projection_qparams_.scales_; + mask = pd()->attr()->rnn_weights_projection_qparams_.mask_; + } + if (type_i == data_type::f32) { + quantize_igo( + scratch_quantized, src_d, (float *)src, mask, scales); + } else + scratch_quantized = (int8_t * __restrict) src; + + if (req_s8s8_comp && mask_ok(dst_d.extra().compensation_mask)) + compensate_igo(comp, src_d, scratch_quantized, scratch_compensation, + pd()->thr_scratch_comp_sz_, pd()->nthr_); + + const auto off_plain + = [&](dim_t l, dim_t d, dim_t i, dim_t g, dim_t o) { + return ((((dim_t)l * D + d) * I + i) * G + g) * O + o; + }; + + const auto off_blk = [&](dim_t l, dim_t d, dim_t g, dim_t ob, + dim_t ib) { + return (((((dim_t)l * D + d) * G + g) * OB + ob) * IB + ib) + * i_block * o_block; + }; + const auto off_inner_blk = [&](int xdim, int y, int x, + int folding_factor) { + const int row = (xdim) * (y / folding_factor) * folding_factor; + const int col = x * folding_factor + (y % folding_factor); + return row + col; + }; + const auto kernel_plain_to_blocked + = [&](const out_data_t *inp, out_data_t *out, int ib, int ob) { + PRAGMA_OMP_SIMD() + for (int i = 0; i < i_block * o_block; i++) + out[i] = 0; + + for_(int i = 0; i < i_block; i++) + for (int o = 0; o < o_block; o++) { + if ((i + ib * i_block < I) && (o + ob * o_block < O)) + out[off_inner_blk(o_block, i, o, i_block)] + = inp[i * G * O + o]; + } + }; + + parallel_nd(L, D, G, OB, IB, + [&](dim_t l, dim_t d, dim_t g, dim_t ob, dim_t ib) { + auto inp = &scratch_quantized[off_plain( + l, d, ib * i_block, g, ob * o_block)]; + auto out = &dst[off_blk(l, d, g, ob, ib)]; + + kernel_plain_to_blocked(inp, out, ib, ob); + }); + + return status::success; + } + + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } +}; + +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/rnn/rnn_utils.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/rnn/rnn_utils.hpp new file mode 100644 index 0000000000000000000000000000000000000000..8af361d63a06c50cf2f3e0aabf6fce41cc95e72d --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/rnn/rnn_utils.hpp @@ -0,0 +1,1390 @@ +/******************************************************************************* +* Copyright 2018-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_RNN_RNN_UTILS_HPP +#define CPU_RNN_RNN_UTILS_HPP + +#include +#include + +#include "common/c_types_map.hpp" +#include "common/memory_desc_wrapper.hpp" +#include "common/primitive.hpp" +#include "common/utils.hpp" + +#include "cpu/platform.hpp" + +#include "cpu/gemm/gemm_pack.hpp" + +#if DNNL_X64 +#include "cpu/x64/cpu_isa_traits.hpp" +#endif + +#define rnn_postgemm_sig(f) \ + void f(const rnn_utils::rnn_conf_t &rnn, \ + rnn_utils::cell_position_t cell_position, gates_t *ws_gates_, \ + scratch_t *scratch_gates_, const dst_layer_t *augru_attention_, \ + dst_layer_t *dst_layer_, void *dst_iter_c_, \ + const src_iter_t *src_iter_, const void *src_iter_c_, \ + gemm_acc_t *diff_src_layer_, gemm_acc_t *diff_augru_attention_, \ + gemm_acc_t *diff_src_iter_, gemm_acc_t *diff_src_iter_c_, \ + gemm_acc_t *diff_dst_layer_, gemm_acc_t *diff_dst_iter_, \ + gemm_acc_t *diff_dst_iter_c_, const float *weights_peephole_, \ + const void *bias_, gates_t *ws_grid_, scratch_t *scratch_cell_, \ + dst_iter_t *dst_iter_, float *weights_scales_, int block_step) \ + const + +#if DNNL_X64 +#define rnn_merged_layer_execution_sig(f) \ + dnnl_status_t f(const exec_ctx_t &ctx, const rnn_utils::rnn_conf_t &rnn, \ + rnn_utils::cell_position_t cell_position, weights_t **w_layer_, \ + const src_layer_t *src_layer_, scratch_t *scratch_gates_, \ + gemm_acc_t *diff_src_layer_, gemm_acc_t *diff_w_layer_, \ + gemm_acc_t *amx_scratchpad, \ + x64::brgemm_batch_element_t *addr_batch_global) const + +#define rnn_cell_execution_sig(f) \ + dnnl_status_t f(const exec_ctx_t &ctx, const rnn_utils::rnn_conf_t &rnn, \ + rnn_utils::cell_position_t cell_position, dst_layer_t *dst_layer_, \ + void *dst_iter_c_, gemm_acc_t *diff_src_layer_, \ + gemm_acc_t *diff_augru_attention_, gemm_acc_t *diff_src_iter_, \ + gemm_acc_t *diff_src_iter_c_, weights_t **w_layer_, \ + weights_t **w_iter_, weights_t **w_projection_, \ + const float *weights_peephole_, const float *w_proj_comp, \ + void **bias_, const src_layer_t *src_layer_, \ + const src_layer_t *augru_attention_, const src_iter_t *src_iter_, \ + const void *src_iter_c_, gemm_acc_t *diff_dst_layer_, \ + gemm_acc_t *diff_dst_iter_, gemm_acc_t *diff_dst_iter_c_, \ + gemm_acc_t *diff_w_layer_, gemm_acc_t *diff_w_iter_, \ + float *diff_weights_projection_, float *diff_weights_peephole_, \ + float *diff_bias_, gates_t *ws_gates_, scratch_t *scratch_gates_, \ + ht_t *proj_ht_, gemm_acc_t *scratch_diff_ht_, gates_t *ws_grid_, \ + scratch_t *scratch_cell_, scratch_t *scratch_gates_blocked_, \ + scratch_t *scratch_src_layer_, scratch_t *scratch_src_iter_, \ + dst_iter_t *dst_iter_, gemm_acc_t *amx_scratchpad, \ + x64::brgemm_batch_element_t *addr_batch_global) const + +#define rnn_grid_execution_sig(f) \ + dnnl_status_t f(const exec_ctx_t &ctx, const rnn_utils::rnn_conf_t &rnn, \ + weights_t **weights_layer_, weights_t **weights_iter_, \ + weights_t **weights_projection_, const float *weights_peephole_, \ + const float *w_proj_comp, void **bias_, \ + const src_layer_t *src_layer_, \ + const src_layer_t *augru_attention_, const src_iter_t *src_iter_, \ + const void *src_iter_c_, dst_layer_t *dst_layer_, \ + dst_iter_t *dst_iter_, void *dst_iter_c_, \ + src_layer_t *ws_states_layer_, src_iter_t *ws_states_iter_, \ + void *ws_states_iter_c_, gemm_acc_t *ws_diff_states_layer_, \ + gemm_acc_t *ws_diff_states_iter_, \ + gemm_acc_t *ws_diff_states_iter_c_, gates_t *ws_gates_, \ + ht_t *ws_ht_, gates_t *ws_grid_, scratch_t *scratch_gates_, \ + ht_t *scratch_ht_, gemm_acc_t *scratch_diff_ht_, \ + scratch_t *scratch_cell_, scratch_t *scratch_gates_blocked_, \ + scratch_t *scratch_src_layer_, scratch_t *scratch_src_iter_, \ + gemm_acc_t *diff_augru_attention_, \ + gemm_acc_t *diff_weights_layer_, gemm_acc_t *diff_weights_iter_, \ + float *diff_weights_projection_, float *diff_weights_peephole_, \ + float *diff_bias_, gemm_acc_t *amx_scratchpad, \ + x64::brgemm_batch_element_t *addr_batch_global) const +#else +#define rnn_merged_layer_execution_sig(f) \ + dnnl_status_t f(const rnn_utils::rnn_conf_t &rnn, \ + rnn_utils::cell_position_t cell_position, weights_t **w_layer_, \ + const src_layer_t *src_layer_, scratch_t *scratch_gates_, \ + gemm_acc_t *diff_src_layer_, gemm_acc_t *diff_w_layer_) const + +#define rnn_cell_execution_sig(f) \ + dnnl_status_t f(const rnn_utils::rnn_conf_t &rnn, \ + rnn_utils::cell_position_t cell_position, dst_layer_t *dst_layer_, \ + void *dst_iter_c_, gemm_acc_t *diff_src_layer_, \ + gemm_acc_t *diff_augru_attention_, gemm_acc_t *diff_src_iter_, \ + gemm_acc_t *diff_src_iter_c_, weights_t **w_layer_, \ + weights_t **w_iter_, weights_t **w_projection_, \ + const float *weights_peephole_, const float *w_proj_comp, \ + void **bias_, const src_layer_t *src_layer_, \ + const src_layer_t *augru_attention_, const src_iter_t *src_iter_, \ + const void *src_iter_c_, gemm_acc_t *diff_dst_layer_, \ + gemm_acc_t *diff_dst_iter_, gemm_acc_t *diff_dst_iter_c_, \ + gemm_acc_t *diff_w_layer_, gemm_acc_t *diff_w_iter_, \ + float *diff_weights_projection_, float *diff_weights_peephole_, \ + float *diff_bias_, gates_t *ws_gates_, scratch_t *scratch_gates_, \ + ht_t *proj_ht_, gemm_acc_t *scratch_diff_ht_, gates_t *ws_grid_, \ + scratch_t *scratch_cell_, dst_iter_t *dst_iter_, \ + gemm_acc_t *amx_scratchpad) const + +#define rnn_grid_execution_sig(f) \ + dnnl_status_t f(const rnn_utils::rnn_conf_t &rnn, \ + weights_t **weights_layer_, weights_t **weights_iter_, \ + weights_t **weights_projection_, const float *weights_peephole_, \ + const float *w_proj_comp, void **bias_, \ + const src_layer_t *src_layer_, \ + const src_layer_t *augru_attention_, const src_iter_t *src_iter_, \ + const void *src_iter_c_, dst_layer_t *dst_layer_, \ + dst_iter_t *dst_iter_, void *dst_iter_c_, \ + src_layer_t *ws_states_layer_, src_iter_t *ws_states_iter_, \ + void *ws_states_iter_c_, gemm_acc_t *ws_diff_states_layer_, \ + gemm_acc_t *ws_diff_states_iter_, \ + gemm_acc_t *ws_diff_states_iter_c_, gates_t *ws_gates_, \ + ht_t *ws_ht_, gates_t *ws_grid_, scratch_t *scratch_gates_, \ + ht_t *scratch_ht_, gemm_acc_t *scratch_diff_ht_, \ + scratch_t *scratch_cell_, gemm_acc_t *diff_augru_attention_, \ + gemm_acc_t *diff_weights_layer_, gemm_acc_t *diff_weights_iter_, \ + float *diff_weights_projection_, float *diff_weights_peephole_, \ + float *diff_bias_, gemm_acc_t *amx_scratchpad) const +#endif + +#define rnn_gemm_sig(f) \ + dnnl_status_t f(const char transA, const char transB, dim_t m, dim_t n, \ + dim_t k, const float alpha, const weights_t *a_, const dim_t ldA, \ + const gemm_data_t *b_, const dim_t ldB, const float beta, \ + gemm_acc_t *c_, const dim_t ldC) const + +#define rnn_bias_prepare_sig(f) \ + void f(const rnn_utils::rnn_conf_t &rnn, void **bias_, const void *b_, \ + void *scratch_bias_) const + +#define rnn_bias_prepare_sig_templ(f) \ + template \ + static void f(const rnn_utils::rnn_conf_t &rnn, T **bias_, const T *b_, \ + T *scratch_bias_) + +#define rnn_bias_finalize_sig(f) \ + void f(const rnn_utils::rnn_conf_t &rnn, void *scratch_bias_, \ + const float *w_iter_comp, const float *w_layer_comp) const + +#define rnn_weights_assign_sig(f) \ + void f(const rnn_utils::rnn_conf_t &rnn, const memory_desc_t *md, \ + int n_parts, const int *gates_per_part, weights_t **weights_, \ + const weights_t *w_) const + +namespace dnnl { +namespace impl { +namespace cpu { + +namespace rnn_utils { + +enum execution_direction_t { + l2r, + r2l, + bi_concat, + bi_sum, +}; + +enum cell_position_t { + middle_cell = 0x0, + first_layer = 0x1, + first_iter = 0x2, + last_layer = 0x4, + last_iter = 0x8, + c_state_first_iter = 0x10, + c_state_last_iter = 0x20, + merged_iter = 0x40, + merged_layer = 0x80 +}; + +enum class weights_type_t { + layer, + iter, + projection, + peephole, +}; + +inline cell_position_t &operator|=(cell_position_t &lhs, cell_position_t rhs) { + lhs = static_cast( + static_cast(lhs) | static_cast(rhs)); + return lhs; +} + +inline cell_position_t operator|(cell_position_t lhs, cell_position_t rhs) { + return static_cast( + static_cast(lhs) | static_cast(rhs)); +} + +enum data_type_conf_t { + all_f32, + all_bf16, + u8u8u8f32, + f32u8f32f32, + u8u8u8u8, + f32u8f32u8, + s8s8s8f32, + f32s8f32f32, + s8s8s8s8, + f32s8f32s8 +}; + +enum brgemm_rnn_execute_loop_order_t { + // default for kernels w/o loop order choice + undefined = 0x0, + // m_blocking loop is outermost + mblk_nblk = 0x1, + // n_blocking loop is outermost + nblk_mblk = 0x2 +}; + +struct diff_src_brgemm_conf_t { + dim_t M = 0, N = 0, K = 0; + + dim_t n_block = 0, N_blocks = 0, n_tail = 0; + dim_t m_block = 0, M_blocks = 0; + + dim_t K_blocks = 0, k_block = 0, k_tail = 0; + dim_t Kpadded = 0; + + dim_t N_iter = 0, N_layer = 0; + dim_t N_layer_blocks = 0, n_layer_tail = 0; + dim_t N_iter_blocks = 0, n_iter_tail = 0; + dim_t LDA = 0, LDB = 0, LDC = 0; + +#if DNNL_X64 + x64::cpu_isa_t isa = x64::isa_undef; +#endif + + brgemm_rnn_execute_loop_order_t loop_order + = brgemm_rnn_execute_loop_order_t::undefined; + int gates_block; +}; + +struct diff_wei_brgemm_conf_t { + dim_t M = 0, M_layer = 0, M_iter = 0, N = 0, K = 0; + + dim_t n_block = 0, N_blocks = 0, n_tail = 0; + dim_t m_block = 0, M_blocks = 0; + dim_t K_blocks = 0, k_block = 0, k_tail = 0; + dim_t Kpadded = 0; + + dim_t LDA_layer = 0, LDA_iter = 0, LDB = 0, LDC_iter = 0, LDC_layer = 0; + + bool global_transpose = false; + +#if DNNL_X64 + x64::cpu_isa_t isa = x64::isa_undef; +#endif + + brgemm_rnn_execute_loop_order_t loop_order + = brgemm_rnn_execute_loop_order_t::undefined; +}; + +struct rnn_conf_t { + execution_direction_t exec_dir; + data_type_conf_t dt_conf; + data_type_t cell_dt = data_type::undef; // The data type used by cell + data_type_t bias_dt = data_type::undef; + data_type_t src_iter_c_dt = data_type::undef; + data_type_t dst_iter_c_dt = data_type::undef; + + int n_layer = 0, n_iter = 0, n_dir = 0, n_gates = 0, n_states = 0; + int mb = 0; + int slc = 0, sic = 0, dhc = 0, dic = 0, dlc = 0; + //int gates_ld, gates_nld, gates_ws_ld; + + int n_parts_weights_layer = 0; + int parts_weights_layer[DNNL_RNN_MAX_N_PARTS]; + size_t part_weights_layer_pack_size[DNNL_RNN_MAX_N_PARTS]; + + int n_parts_weights_iter = 0; + int parts_weights_iter[DNNL_RNN_MAX_N_PARTS]; + size_t part_weights_iter_pack_size[DNNL_RNN_MAX_N_PARTS]; + + int n_parts_weights_projection = 0; + int parts_weights_projection[DNNL_RNN_MAX_N_PARTS]; + size_t part_weights_projection_pack_size[DNNL_RNN_MAX_N_PARTS]; + + int n_bias = 0, n_parts_bias = 0, parts_bias[DNNL_RNN_MAX_N_PARTS]; + + /* Size of packed data in bytes */ + size_t weights_layer_comp_offset = 0, weights_layer_pack_size = 0; + size_t weights_iter_comp_offset = 0, weights_iter_pack_size = 0; + size_t weights_projection_comp_offset = 0, weights_projection_pack_size = 0; + + bool copy_bias = 0; + int weights_layer_ld = 0, weights_layer_nld = 0; + int diff_weights_layer_ld = 0, diff_weights_layer_nld = 0; + int weights_iter_ld = 0, weights_iter_nld = 0; + int diff_weights_iter_ld = 0, diff_weights_iter_nld = 0; + int weights_projection_ld = 0, weights_projection_nld = 0; + int diff_weights_projection_ld = 0, diff_weights_projection_nld = 0; + + int proj_ht_ld = 0, proj_ht_nld = 0; + + int ws_gates_ld = 0, ws_gates_nld = 0; + int ws_ht_ld = 0, ws_ht_nld = 0; + int ws_states_layer_ld = 0, ws_states_layer_nld = 0; + int ws_states_iter_ld = 0, ws_states_iter_nld = 0; + int ws_states_iter_c_ld = 0, ws_states_iter_c_nld = 0; + int ws_diff_states_layer_ld = 0, ws_diff_states_layer_nld = 0; + int ws_diff_states_iter_ld = 0, ws_diff_states_iter_nld = 0; + int ws_diff_states_iter_c_ld = 0, ws_diff_states_iter_c_nld = 0; + + int scratch_gates_ld = 0, scratch_gates_nld = 0; + int scratch_ht_ld = 0, scratch_ht_nld = 0; + int scratch_diff_ht_ld = 0, scratch_diff_ht_nld = 0; + + int src_layer_ld_ = 0, src_layer_nld_ = 0; + int src_iter_ld_ = 0, src_iter_nld_ = 0; + int src_iter_c_ld_ = 0, src_iter_c_nld_ = 0; + int dst_layer_ld_ = 0, dst_layer_nld_ = 0; + int dst_iter_ld_ = 0, dst_iter_nld_ = 0; + int dst_iter_c_ld_ = 0, dst_iter_c_nld_ = 0; + + int weights_iter_compensation_size = 0, weights_layer_compensation_size = 0; + bool is_fwd = 0, is_training = 0, is_lbr = 0, is_lstm_peephole = 0, + is_lstm_projection = 0, is_augru = 0, is_orig_gru = 0; + bool use_workspace = 0; + + // Size of workspace for each tensor in bytes + // Notes: + // 1. For non-LSTMP ws_states_iter_size == ws_states_layer_size. The corresponding + // pointers should point to the same places. + size_t ws_gates_size = 0; + size_t ws_ht_size = 0; + size_t ws_states_layer_size = 0; + size_t ws_states_iter_size = 0; + size_t ws_states_iter_c_size = 0; + size_t ws_diff_states_layer_size = 0; + size_t ws_diff_states_iter_size = 0; + size_t ws_diff_states_iter_c_size = 0; + size_t scratch_gates_size = 0; + + size_t scratch_gates_blocked_size = 0; + size_t scratch_gates_blocked_nested_reorder_size = 0; + size_t scratch_src_layer_size = 0; + size_t scratch_src_layer_nested_reorder_size = 0; + size_t scratch_src_iter_size = 0; + size_t scratch_src_iter_nested_reorder_size = 0; + + size_t scratch_ht_size = 0; + size_t scratch_diff_ht_size = 0; + size_t scratch_cell_size = 0; + size_t ws_grid_comp_size = 0; + size_t ws_per_cell = 0; + size_t ws_bias_size = 0; + + bool src_layer_is_trivial_stride = false; + bool merge_gemm_iter = false, merge_gemm_layer = false, + force_nocopy = false, use_layer_packed_gemm = false, + use_iter_packed_gemm = false, use_projection_packed_gemm = false; + int n_iter_scratch_gates = 0; + + bool diff_weights_overwrite = false; + + inline bool is_int8_conf() const { + return is_signed_int8_conf() || is_unsigned_int8_conf(); + } + inline bool is_signed_int8_conf() const { + return utils::one_of( + dt_conf, s8s8s8f32, f32s8f32f32, s8s8s8s8, f32s8f32s8); + } + inline bool is_unsigned_int8_conf() const { + return utils::one_of( + dt_conf, u8u8u8f32, f32u8f32f32, u8u8u8u8, f32u8f32u8); + } + + inline bool is_cell_dt_int8() const { + return is_cell_dt_signed_int8() || is_cell_dt_unsigned_int8(); + } + inline bool is_cell_dt_signed_int8() const { + return cell_dt == data_type::s8; + } + inline bool is_cell_dt_unsigned_int8() const { + return cell_dt == data_type::u8; + } + + inline bool is_cell_int8_amx() const { +#if DNNL_X64 + return brgemm_isa == x64::avx512_core_amx && is_cell_dt_int8(); +#else + return false; +#endif + } + + inline bool is_bf16_conf() const { return dt_conf == all_bf16; } + + inline bool is_f32_conf() const { return dt_conf == all_f32; } + + inline bool is_cell_dt_f32() const { return cell_dt == data_type::f32; } + inline bool is_cell_dt_bf16() const { return cell_dt == data_type::bf16; } + inline bool is_cell_bf16_amx() const { +#if DNNL_X64 + return brgemm_isa == x64::avx512_core_amx && is_cell_dt_bf16(); +#else + return false; +#endif + } + inline bool is_bf32() const { return is_cell_bf16_amx() && is_f32_conf(); } + + inline bool skip_src_layer_copy() const { + return (exec_dir == l2r) && !is_bf32() + && utils::one_of(dt_conf, s8s8s8f32, f32s8f32f32, s8s8s8s8, + f32s8f32s8, u8u8u8u8, u8u8u8f32, f32u8f32u8, + f32u8f32f32, all_f32, all_bf16); + } + inline bool skip_src_iter_copy() const { + return (exec_dir == l2r) && (src_iter_ld_ > 0) && !is_bf32() + && utils::one_of(dt_conf, s8s8s8s8, s8s8s8f32, u8u8u8u8, + u8u8u8f32, all_f32, all_bf16); + } + inline bool skip_dst_layer_copy() const { + return (exec_dir == l2r) && !is_bf32() + && utils::one_of(dt_conf, s8s8s8s8, f32s8f32s8, u8u8u8u8, + f32u8f32u8, all_f32, all_bf16); + } + inline bool skip_dst_iter_copy() const { + return (exec_dir == l2r) && (dst_iter_ld_ > 0) && !is_bf32() + && utils::one_of(dt_conf, s8s8s8s8, s8s8s8f32, u8u8u8u8, + u8u8u8f32, all_f32, all_bf16); + } + + inline dim_t src_layer_ld(cell_position_t cell_position) const { + return (cell_position & first_layer) && skip_src_layer_copy() + ? src_layer_ld_ + : (cell_position & last_iter) && skip_dst_iter_copy() + ? dst_iter_ld_ + : ws_states_layer_ld; + } + + inline dim_t src_iter_ld(cell_position_t cell_position) const { + return (cell_position & first_iter) && skip_src_iter_copy() + ? src_iter_ld_ + : ((cell_position & last_layer) && skip_dst_layer_copy() + && !(cell_position & first_iter) + ? dst_layer_ld_ + : ws_states_iter_ld); + } + + inline dim_t layer_brgemm_desc(cell_position_t cell_position) const { + return ((cell_position & first_layer) && skip_src_layer_copy()) ? 0 + : ((cell_position & last_iter) && skip_dst_iter_copy()) ? 1 + : 2; + } + + inline dim_t iter_brgemm_desc(cell_position_t cell_position) const { + return ((cell_position & first_iter) && skip_src_iter_copy()) ? 0 + : ((cell_position & last_layer) && skip_dst_layer_copy() + && !(cell_position & first_iter)) + ? 1 + : 2; + } + + // Returns index of brgemm kernel for 2nd part of iteration gemm in vanilla + // GRU cell for the current position. + // Note: this method must be aligned with dst_iter_part2_ld() and LDA2_2[] + // values initialization order + inline dim_t iter_part2_brgemm_desc(cell_position_t cell_position) const { + if (cell_position & last_layer) { + return (cell_position & last_layer) && skip_dst_layer_copy() ? 0 + : (cell_position & last_iter) && skip_dst_iter_copy() ? 1 + : 2; + } else { + return (cell_position & last_iter) && skip_dst_iter_copy() ? 1 : 3; + } + } + + inline dim_t src_iter_c_ld(cell_position_t cell_position) const { + return (cell_position & c_state_first_iter) ? src_iter_c_ld_ + : ws_states_iter_c_ld; + } + + inline dim_t dst_layer_ld( + cell_position_t cell_position, bool after_proj = false) const { + // We use scratch_ht and not dst_layer for lstmp + if (is_lstm_projection && !after_proj) return scratch_ht_ld; + + return (cell_position & last_layer) && skip_dst_layer_copy() + ? dst_layer_ld_ + : (cell_position & last_iter) && skip_dst_iter_copy() + ? dst_iter_ld_ + : ws_states_layer_ld; + } + + inline dim_t dst_brgemm_desc( + cell_position_t cell_position, bool after_proj = false) const { + // We use scratch_ht and not dst_layer for lstmp + if (is_lstm_projection && !after_proj) return 0; + + return (cell_position & last_layer) && skip_dst_layer_copy() ? 1 + : (cell_position & last_iter) && skip_dst_iter_copy() ? 2 + : 3; + } + + inline dim_t dst_iter_ld(cell_position_t cell_position) const { + return (cell_position & last_iter) && skip_dst_iter_copy() + ? dst_iter_ld_ + : ws_states_iter_ld; + } + + // Returns dst tensor leading dimension for 2nd part of iteration gemm in + // vanilla GRU cell for the current position + inline dim_t dst_iter_part2_ld(cell_position_t cell_position) const { + return (cell_position & last_layer) ? dst_layer_ld(cell_position) + : dst_iter_ld(cell_position); + } + + inline dim_t dst_iter_c_ld(cell_position_t cell_position) const { + return (cell_position & c_state_last_iter) ? dst_iter_c_ld_ + : ws_states_iter_c_ld; + } + + // // when skipping copy, the output ld can be states_ws_ld, + // // dst_iter_ld or dst_layer_ld depending on the cell position + // inline dim_t dst_ld(cell_position_t cell_position) const { + // return (cell_position & last_layer) ? dst_layer_ld(cell_position) + // : dst_iter_ld(cell_position); + // } + inline dim_t dst_copy_ld(cell_position_t cell_position) const { + return dst_iter_ld(cell_position); + } + + inline bool need_gemm_layer(cell_position_t cell_position) const { + // In case of merge_gemm_layer we might still need a layer gemm if we store + // the states of the last iteration in the destination memory. The + // exception of this rule is the first layer though, in which case all + // states are kept in user's src_layer, hence making full merged gemm + // possible. + return IMPLICATION(merge_gemm_layer, + skip_dst_iter_copy() && (cell_position & last_iter) + && !(cell_position & first_layer)); + } + + // get diff_weights_beta based on cell position + inline float diff_weights_beta(cell_position_t cell_position) const { + if (diff_weights_overwrite) { + // Initialize diff weights if needed + if (cell_position & merged_iter) return 0.0f; + if ((cell_position & merged_layer) + && !need_gemm_layer(cell_position | last_iter)) + return 0.0f; + if (cell_position & last_iter) return 0.0f; + } + return 1.0f; + } + + bool is_brgemm; + + diff_src_brgemm_conf_t diff_src_brgemm; + diff_wei_brgemm_conf_t diff_wei_brgemm; + + dim_t M, N, K1, K2; + + dim_t LDB1, LDB2; + dim_t LDA1[3]; + dim_t LDA2[3]; + // LDA for iter part2 gemm in vanilla gru cell + dim_t LDA2_2[4]; + dim_t LDC; + + dim_t m_block, M_blocks; + dim_t n_block, N_blocks, n_tail; + + dim_t k2_block, k1_block, k1_tail, k2_tail; + dim_t KB1_blocks, KB2_blocks; + dim_t K1padded, K2padded; + + dim_t Kproj, Kprojpadded; + dim_t kproj_block, KBproj_blocks, kproj_tail; + + dim_t Nproj, Nproj_blocks, nproj_tail; + dim_t LDAproj, LDBproj, LDCproj[4]; + int dhc_block_peephole, dhc_tail_peephole, dhc_blocks_peephole; + bool brgemm_fwd_iter_layer_fuse_possible = false; + + dim_t nthr; +#if DNNL_X64 + x64::cpu_isa_t brgemm_isa; +#endif + bool unfused_post_gemm; + brgemm_rnn_execute_loop_order_t loop_order + = brgemm_rnn_execute_loop_order_t::undefined; + + // for merged layer computation in brgemm + dim_t Mlayermerged; + dim_t mlayermerged_block, Mlayermerged_blocks; +}; + +bool is_ldigo(const memory_desc_wrapper &md); +bool is_ldgoi(const memory_desc_wrapper &md); +bool is_ldio(const memory_desc_wrapper &md); +bool is_ldoi(const memory_desc_wrapper &md); +bool is_ldigo_blocked(const memory_desc_wrapper &md); +bool is_ldgoi_blocked(const memory_desc_wrapper &md); +bool is_ldio_blocked(const memory_desc_wrapper &md); +bool is_ldoi_blocked(const memory_desc_wrapper &md); + +int get_good_ld(int dim, int sizeof_dt); + +template +bool init_conf(rnn_conf_t &rnn, const rnn_desc_t &rd, + const primitive_attr_t &attr, const memory_desc_wrapper &src_layer_d, + const memory_desc_wrapper &src_iter_d, + const memory_desc_wrapper &src_iter_c_d, + const memory_desc_wrapper &weights_layer_d, + const memory_desc_wrapper &weights_iter_d, + const memory_desc_wrapper &weights_projection_d, + const memory_desc_wrapper &dst_layer_d, + const memory_desc_wrapper &dst_iter_d, + const memory_desc_wrapper &dst_iter_c_d, + const memory_desc_wrapper &bias_d) { + rnn.is_fwd = utils::one_of(rd.prop_kind, prop_kind::forward_training, + prop_kind::forward_inference); + rnn.is_training = utils::one_of( + rd.prop_kind, prop_kind::forward_training, prop_kind::backward); + rnn.is_lbr = utils::one_of(rd.cell_kind, dnnl_lbr_gru, dnnl_lbr_augru); + rnn.is_lstm_peephole = rd.cell_kind == dnnl_vanilla_lstm + && !memory_desc_wrapper(rd.weights_peephole_desc).is_zero(); + rnn.is_lstm_projection = rd.cell_kind == dnnl_vanilla_lstm + && !memory_desc_wrapper(rd.weights_projection_desc).is_zero(); + rnn.is_augru + = utils::one_of(rd.cell_kind, dnnl_lbr_augru, dnnl_vanilla_augru); + rnn.bias_dt = bias_d.is_zero() ? data_type::f32 : bias_d.data_type(); + rnn.src_iter_c_dt = src_iter_c_d.is_zero() ? data_type::f32 + : src_iter_c_d.data_type(); + rnn.dst_iter_c_dt = dst_iter_c_d.is_zero() ? data_type::f32 + : dst_iter_c_d.data_type(); + + rnn.cell_dt = data_traits::data_type; + switch (rd.direction) { + case dnnl_unidirectional_left2right: rnn.exec_dir = l2r; break; + case dnnl_unidirectional_right2left: rnn.exec_dir = r2l; break; + case dnnl_bidirectional_concat: rnn.exec_dir = bi_concat; break; + case dnnl_bidirectional_sum: rnn.exec_dir = bi_sum; break; + default: break; + } + + if (utils::everyone_is(data_type::f32, src_layer_d.data_type(), + dst_layer_d.data_type(), weights_layer_d.data_type())) + rnn.dt_conf = all_f32; + else if (utils::everyone_is(data_type::bf16, src_layer_d.data_type(), + dst_layer_d.data_type(), weights_layer_d.data_type())) { + if (!platform::has_data_type_support(data_type::bf16)) return false; +#if DNNL_X64 + if (!x64::mayiuse(x64::avx512_core)) return false; +#endif + rnn.dt_conf = all_bf16; + } else if (dst_layer_d.data_type() == data_type::u8) { + if (IMPLICATION( + src_iter_d.md_, src_iter_d.data_type() == data_type::u8)) + rnn.dt_conf = u8u8u8u8; + else + rnn.dt_conf = f32u8f32u8; + } else if (dst_layer_d.data_type() == data_type::s8) { + if (IMPLICATION( + src_iter_d.md_, src_iter_d.data_type() == data_type::s8)) + rnn.dt_conf = s8s8s8s8; + else + rnn.dt_conf = f32s8f32s8; + + } else if (dst_layer_d.data_type() == data_type::f32) { + if (IMPLICATION( + src_iter_d.md_, src_iter_d.data_type() == data_type::u8)) + rnn.dt_conf = u8u8u8f32; + else if (IMPLICATION(src_iter_d.md_, + src_iter_d.data_type() == data_type::s8)) + rnn.dt_conf = s8s8s8f32; + else if (IMPLICATION(src_layer_d.md_, + src_layer_d.data_type() == data_type::s8)) + rnn.dt_conf = f32s8f32f32; + else + rnn.dt_conf = f32u8f32f32; + } + + // Set problem members defining problem sizes + rnn.n_layer = weights_layer_d.dims()[0]; + rnn.n_iter = src_layer_d.dims()[0]; + rnn.n_dir = weights_layer_d.dims()[1]; + rnn.n_gates = weights_layer_d.dims()[3]; + rnn.n_states = rd.cell_kind == dnnl_vanilla_lstm ? 2 : 1; + rnn.n_bias = rnn.n_gates + rnn.is_lbr; + rnn.mb = src_layer_d.dims()[1]; + rnn.sic = weights_iter_d.dims()[2]; + rnn.slc = weights_layer_d.dims()[2]; + rnn.dhc = weights_layer_d.dims()[4]; + rnn.dlc = rnn.is_lstm_projection ? weights_projection_d.dims()[3] : rnn.dhc; + // All supported cells have dic == dlc + rnn.dic = rnn.dlc; + + // set members with user memories leading dimensions + // Assumption: weights datatype size is the same as state datatype size + assert(types::data_type_size(weights_layer_d.data_type()) + == types::data_type_size(src_layer_d.data_type())); + + // set workspace leading dimensions (and non leading-dimensions) + + // the ws and scratch proj_ht need to match as we use them interchangeably + assert(IMPLICATION(rnn.is_lstm_projection, + sizeof(typename T::ht_t) == sizeof(typename T::dst_iter_t))); + rnn.proj_ht_nld = rnn.mb; + rnn.proj_ht_ld = get_good_ld(rnn.dhc, sizeof(typename T::ht_t)); + + rnn.ws_gates_nld = rnn.mb; + rnn.ws_gates_ld + = get_good_ld(rnn.dhc * rnn.n_gates, sizeof(typename T::gates_t)); + rnn.ws_ht_nld = rnn.proj_ht_nld; + rnn.ws_ht_ld = rnn.proj_ht_ld; + + rnn.ws_states_layer_nld = rnn.mb; + static_assert(std::is_same::value, + "src_layer_t and src_iter_t must be the same"); + rnn.ws_states_layer_ld + = get_good_ld(nstl::max(rnn.sic, nstl::max(rnn.slc, rnn.dlc)), + sizeof(typename T::src_layer_t)); + // there is no need for al separate ws_states_iter for now as all + // supported cell have dst_iter == dst_layer + rnn.ws_states_iter_nld = rnn.ws_states_layer_nld; + rnn.ws_states_iter_ld = rnn.ws_states_layer_ld; + + // we do not need a good ld for iter_c as it is not involved in GEMM + rnn.ws_states_iter_c_nld = rnn.mb; + rnn.ws_states_iter_c_ld = rnn.dhc; + + // TODO: be more restrictive on the leading dimensions + rnn.ws_diff_states_layer_nld = rnn.mb; + rnn.ws_diff_states_layer_ld = get_good_ld( + nstl::max(nstl::max(rnn.slc, rnn.dic), nstl::max(rnn.sic, rnn.dhc)), + sizeof(typename T::gemm_acc_t)); + + rnn.ws_diff_states_iter_nld = rnn.mb; + rnn.ws_diff_states_iter_ld = get_good_ld( + nstl::max(nstl::max(rnn.slc, rnn.dic), nstl::max(rnn.sic, rnn.dhc)), + sizeof(typename T::gemm_acc_t)); + + rnn.ws_diff_states_iter_c_nld = rnn.mb; + rnn.ws_diff_states_iter_c_ld = rnn.dhc; + + // set scratch (not)leading dimensions + // scratch gates is used to store intermediate gates before postgemm operation + // temporary: we also use it in lstmp as temporary scratchpad + // between projection and downconversion, hence the max with dlc + rnn.scratch_gates_nld = rnn.mb; + rnn.scratch_gates_ld + = get_good_ld(nstl::max(rnn.dlc, rnn.n_gates * rnn.dhc), + sizeof(typename T::scratch_t)); + rnn.scratch_ht_nld = rnn.proj_ht_nld; + rnn.scratch_ht_ld = rnn.proj_ht_ld; + + rnn.scratch_diff_ht_nld = rnn.mb; + rnn.scratch_diff_ht_ld + = get_good_ld(rnn.dlc, sizeof(typename T::gemm_acc_t)); + + // Assumption: {src,dst}_layer has tnc layout, {src,dst}_iter has ldnc, + rnn.src_layer_ld_ = src_layer_d.blocking_desc().strides[1]; + rnn.dst_layer_ld_ = dst_layer_d.blocking_desc().strides[1]; + rnn.src_iter_ld_ = types::is_zero_md(src_iter_d.md_) + ? 0 + : src_iter_d.blocking_desc().strides[2]; + rnn.dst_iter_ld_ = types::is_zero_md(dst_iter_d.md_) + ? 0 + : dst_iter_d.blocking_desc().strides[2]; + rnn.src_iter_c_ld_ = types::is_zero_md(src_iter_c_d.md_) + ? 0 + : src_iter_c_d.blocking_desc().strides[2]; + rnn.dst_iter_c_ld_ = types::is_zero_md(dst_iter_c_d.md_) + ? 0 + : dst_iter_c_d.blocking_desc().strides[2]; + + /* Set the correct number of weights parts */ + rnn.is_orig_gru = utils::one_of( + rd.cell_kind, alg_kind::vanilla_gru, alg_kind::vanilla_augru); + rnn.n_parts_weights_layer = 1; + rnn.parts_weights_layer[0] = rnn.n_gates; + rnn.parts_weights_layer[1] = 0; + + rnn.n_parts_weights_iter = rnn.is_orig_gru ? 2 : 1; + rnn.parts_weights_iter[0] = rnn.is_orig_gru ? 2 : rnn.n_gates; + rnn.parts_weights_iter[1] = rnn.is_orig_gru ? 1 : 0; + + rnn.n_parts_weights_projection = 1; + rnn.parts_weights_projection[0] = 1; + + rnn.n_parts_bias = 1; + rnn.parts_bias[0] = rnn.n_bias; + rnn.parts_bias[1] = 0; + + /* Decide which gemm implementation to use: packed/nonpacked jit/cblas + * and if to merge gemm across iterations */ + const bool is_f32 = rnn.dt_conf == all_f32, + is_bf16 = rnn.dt_conf == all_bf16; + const bool is_gru = utils::one_of(rd.cell_kind, alg_kind::vanilla_gru, + alg_kind::lbr_gru, alg_kind::vanilla_augru, alg_kind::lbr_augru); + const bool is_inference = !rnn.is_training; + + // To be able to merge the GEMM on the layer input when not + // copying, we need to have a trivial stride for the T dimension + rnn.src_layer_is_trivial_stride = src_layer_d.blocking_desc().strides[0] + == (rnn.src_layer_ld_ * rnn.mb); + const auto dst_layer_is_trivial_stride + = dst_layer_d.blocking_desc().strides[0] + == (rnn.dst_layer_ld_ * rnn.mb); + + rnn.merge_gemm_layer = (!rnn.is_brgemm) + ? ((rnn.is_fwd && rnn.src_layer_is_trivial_stride) + || ((rd.prop_kind == prop_kind::backward) + && dst_layer_is_trivial_stride)) + && (((rnn.is_fwd && rnn.mb < 128) || !rnn.is_fwd) + || rnn.is_int8_conf()) + : false; + rnn.merge_gemm_iter = (!rnn.is_brgemm) + ? dst_layer_is_trivial_stride && !(rnn.is_fwd || is_gru) + : false; + rnn.force_nocopy = false; +#if DNNL_X64 + rnn.force_nocopy = x64::mayiuse(x64::avx) + && ((is_inference && (rnn.n_layer > 1 || rnn.mb < 100)) + || (rnn.is_training && rnn.dhc < 500)); +#endif + + /* Decide to copy bias */ + rnn.copy_bias = rnn.is_int8_conf(); + + rnn.use_layer_packed_gemm = !rnn.is_brgemm + ? utils::one_of(weights_layer_d.format_kind(), format_kind::any, + format_kind::rnn_packed) + && is_inference + && ((is_f32 && pack_sgemm_supported() && rnn.n_iter == 1) + || rnn.is_int8_conf() || is_bf16) + : false; + rnn.use_iter_packed_gemm = !rnn.is_brgemm + ? utils::one_of(weights_iter_d.format_kind(), format_kind::any, + format_kind::rnn_packed) + && is_inference + && ((is_f32 && pack_sgemm_supported() && rnn.mb >= 16) + || rnn.is_int8_conf() || is_bf16) + : false; + rnn.use_projection_packed_gemm = !rnn.is_brgemm + ? utils::one_of(weights_projection_d.format_kind(), + format_kind::any, format_kind::rnn_packed) + && is_inference + && ((is_f32 && pack_sgemm_supported() && rnn.n_iter == 1) + || rnn.is_int8_conf() || is_bf16) + : false; + + rnn.diff_weights_overwrite = rd.flags & rnn_flags::diff_weights_overwrite; + +#if DNNL_CPU_RUNTIME == DNNL_RUNTIME_THREADPOOL + // XXX: Threadpool runtime may use different number of threads at execute + // and create stages. GEMM packed API is not aware of number of threads as + // of now. In order to synchronize all layers, GEMM pack API should be + // modified to accept number of threads instead of taking it from + // `dnnl_get_max_threads()`, and rnn_packed_desc_t should be updated with + // `nthr` member to pass this information between different parts of packed + // API, since `get_size` call happens on RNN side, while packing happens + // on reorder side. Consider enabling later. + // `test_iface_runtime_attr` was disabled for RNN with threadpool due to + // this is the only working approach for int8 computations in RNN for now. + // Consider enabling it once resolved. + rnn.use_layer_packed_gemm = false; + rnn.use_iter_packed_gemm = false; + rnn.use_projection_packed_gemm = false; +#endif + + /* Set packed gemm sizes */ + /* TODO: investigate the benefit of mixing packed and non-packed weights parts */ + const auto set_pack_sizes + = [&](bool merge, bool &do_pack, size_t &weights_pack_size, + int &n_parts, int *parts, size_t *parts_pack_size, + size_t &comp_offset, int ic, int oc, int weights_oc, + dim_t data_ld) -> bool { + bool pack = true; + weights_pack_size = 0; + for (int p = 0; p < n_parts; p++) { + const dim_t m_p = rnn.is_fwd ? (parts[p] * oc) : ic; + const dim_t k_p = rnn.is_fwd ? ic : (parts[p] * oc); + const dim_t n_p = merge ? rnn.mb * rnn.n_iter : rnn.mb; + bool pack_part = true; + + dnnl_status_t st = dnnl_success; + switch (rnn.dt_conf) { + case all_f32: + st = sgemm_pack_get_size("A", "N", "N", &m_p, &n_p, &k_p, + &m_p, &data_ld, &parts_pack_size[p], &pack_part); + break; + case s8s8s8f32: + case f32s8f32f32: + case s8s8s8s8: + case f32s8f32s8: + st = gemm_s8s8s32_pack_get_size("A", "N", "N", &m_p, &n_p, + &k_p, &m_p, &data_ld, &parts_pack_size[p], + &pack_part); + break; + case u8u8u8f32: + case f32u8f32f32: + case u8u8u8u8: + case f32u8f32u8: + st = gemm_s8u8s32_pack_get_size("A", "N", "N", &m_p, &n_p, + &k_p, &m_p, &data_ld, &parts_pack_size[p], + &pack_part); + break; + case all_bf16: + st = gemm_bf16bf16f32_pack_get_size("A", "N", "N", &m_p, + &n_p, &k_p, &m_p, &data_ld, &parts_pack_size[p], + &pack_part); + break; + default: assert(!"Unsupported configuration"); + } + if (st != dnnl_success) return false; + + pack = pack && pack_part; + weights_pack_size += rnn.n_layer * rnn.n_dir * parts_pack_size[p]; + } + + // NOTE: pack is updated only for f32. We force pack for int8 + do_pack = (rnn.dt_conf == all_f32) ? pack : true; + comp_offset = weights_pack_size; + const bool need_compensation = rnn.is_int8_conf(); + weights_pack_size += (need_compensation ? rnn.n_layer * rnn.n_dir : 0) + * weights_oc * sizeof(float); + + return true; + }; + // TODO: the activation leading dimension can vary for first layer/iteration + if (rnn.use_layer_packed_gemm) { + bool ok = set_pack_sizes(rnn.merge_gemm_layer, + rnn.use_layer_packed_gemm, rnn.weights_layer_pack_size, + rnn.n_parts_weights_layer, rnn.parts_weights_layer, + rnn.part_weights_layer_pack_size, rnn.weights_layer_comp_offset, + rnn.slc, rnn.dhc, rnn.n_gates * rnn.dhc, + rnn.ws_states_layer_ld); + if (!ok) return false; + } + + if (rnn.use_iter_packed_gemm) { + bool ok = set_pack_sizes(rnn.merge_gemm_iter, rnn.use_iter_packed_gemm, + rnn.weights_iter_pack_size, rnn.n_parts_weights_iter, + rnn.parts_weights_iter, rnn.part_weights_iter_pack_size, + rnn.weights_iter_comp_offset, rnn.sic, rnn.dhc, + rnn.n_gates * rnn.dhc, rnn.ws_states_iter_ld); + if (!ok) return false; + } + + if (rnn.use_projection_packed_gemm) { + bool ok = set_pack_sizes(false, rnn.use_projection_packed_gemm, + rnn.weights_projection_pack_size, + rnn.n_parts_weights_projection, rnn.parts_weights_projection, + rnn.part_weights_projection_pack_size, + rnn.weights_projection_comp_offset, rnn.dhc, rnn.dic, rnn.dic, + rnn.scratch_ht_ld); + if (!ok) return false; + } + + return true; +} + +template +void set_conf(rnn_conf_t &rnn, const rnn_desc_t &rd, + const memory_desc_wrapper &weights_layer_d, + const memory_desc_wrapper &weights_iter_d, + const memory_desc_wrapper &weights_projection_d, + const memory_desc_wrapper &diff_weights_layer_d, + const memory_desc_wrapper &diff_weights_iter_d, + const memory_desc_wrapper &diff_weights_projection_d) { + + // Set leading dimensions for input weights arrays depending on input format + const auto set_dims + = [&](const memory_desc_wrapper &md, int &ld, int &nld) { + ld = 0; + nld = 0; + if (md.is_blocking_desc()) { + if (is_ldigo(md)) { + ld = (int)md.blocking_desc().strides[2]; + nld = md.dims()[2]; + } else if (is_ldgoi(md)) { + ld = (int)md.blocking_desc().strides[4]; + nld = md.dims()[3] * md.dims()[4]; + } else if (is_ldoi(md)) { + ld = (int)md.blocking_desc().strides[3]; + nld = md.dims()[3]; + } else if (is_ldio(md)) { + ld = (int)md.blocking_desc().strides[2]; + nld = md.dims()[2]; + } else + assert(!"unsupported weights format"); + } + }; + set_dims(weights_layer_d, rnn.weights_layer_ld, rnn.weights_layer_nld); + set_dims(weights_iter_d, rnn.weights_iter_ld, rnn.weights_iter_nld); + set_dims(weights_projection_d, rnn.weights_projection_ld, + rnn.weights_projection_nld); + if (!rnn.is_fwd) { + set_dims(diff_weights_layer_d, rnn.diff_weights_layer_ld, + rnn.diff_weights_layer_nld); + set_dims(diff_weights_iter_d, rnn.diff_weights_iter_ld, + rnn.diff_weights_iter_nld); + set_dims(diff_weights_projection_d, rnn.diff_weights_projection_ld, + rnn.diff_weights_projection_nld); + } + + assert(weights_layer_d.data_type() == weights_iter_d.data_type()); + assert(IMPLICATION(diff_weights_layer_d.ndims() != 0, + (diff_weights_layer_d.data_type() + == diff_weights_iter_d.data_type()))); + + /* Set workspace sizes to store: + * states to compute a pass + * diff states to compute bwd pass (training onl)y + * intermediate results from the gates + */ + + assert(sizeof(typename T::src_layer_t) == sizeof(typename T::dst_layer_t)); + assert(sizeof(typename T::src_iter_t) == sizeof(typename T::dst_iter_t)); +} + +template +void set_workspace_sizes(rnn_conf_t &rnn, const rnn_desc_t &rd) { + rnn.use_workspace = rnn.is_training; + // TODO: for inference, we can make ws_states_* smaller, but + // dependant of the grid execution though + rnn.ws_states_layer_size = (size_t)(rnn.n_layer + 1) * rnn.n_dir + * (rnn.n_iter + 1) * rnn.mb * rnn.ws_states_layer_ld + * sizeof(typename T::src_layer_t); + rnn.ws_states_iter_size = (size_t)(rnn.n_layer + 1) * rnn.n_dir + * (rnn.n_iter + 1) * rnn.mb * rnn.ws_states_iter_ld + * sizeof(typename T::src_iter_t); + bool is_lstm = rd.cell_kind == dnnl_vanilla_lstm; + rnn.ws_states_iter_c_size = is_lstm ? (size_t)(rnn.n_layer + 1) * rnn.n_dir + * (rnn.n_iter + 1) * rnn.mb * rnn.ws_states_iter_c_ld + * types::data_type_size(rnn.src_iter_c_dt) + : 0; + + rnn.ws_diff_states_layer_size = rnn.is_training + ? (size_t)(rnn.n_layer + 1) * rnn.n_dir * (rnn.n_iter + 1) * rnn.mb + * rnn.ws_diff_states_layer_ld + * sizeof(typename T::gemm_acc_t) + : (size_t)0; + rnn.ws_diff_states_iter_size = rnn.is_training + ? (size_t)(rnn.n_layer + 1) * rnn.n_dir * (rnn.n_iter + 1) * rnn.mb + * rnn.ws_diff_states_iter_ld + * sizeof(typename T::gemm_acc_t) + : (size_t)0; + rnn.ws_diff_states_iter_c_size = rnn.is_training && is_lstm + ? (size_t)(rnn.n_layer + 1) * rnn.n_dir * (rnn.n_iter + 1) * rnn.mb + * rnn.ws_diff_states_iter_c_ld + * sizeof(typename T::gemm_acc_t) + : (size_t)0; + + rnn.ws_gates_size = rnn.is_training + ? (size_t)rnn.n_layer * rnn.n_dir * rnn.n_iter * rnn.ws_gates_nld + * rnn.ws_gates_ld * sizeof(typename T::gates_t) + : (size_t)0; + rnn.ws_ht_size = rnn.is_training + ? (size_t)rnn.n_layer * rnn.n_dir * rnn.n_iter * rnn.ws_ht_nld + * rnn.ws_ht_ld * sizeof(typename T::dst_iter_t) + : (size_t)0; + rnn.n_iter_scratch_gates + = (rnn.merge_gemm_layer || rnn.merge_gemm_iter) ? rnn.n_iter : 1; + rnn.scratch_gates_size = sizeof(typename T::scratch_t) + * rnn.n_iter_scratch_gates * rnn.scratch_gates_nld + * rnn.scratch_gates_ld; + rnn.scratch_ht_size + = sizeof(typename T::ht_t) * rnn.scratch_ht_nld * rnn.scratch_ht_ld; + rnn.scratch_diff_ht_size = rnn.is_training ? sizeof(typename T::gemm_acc_t) + * rnn.scratch_diff_ht_nld * rnn.scratch_diff_ht_ld + : (size_t)0; + + /* set other sizes */ + /// scratchpad buffer for each cell to hold intermediate data in gru/lbr_gru + rnn.scratch_cell_size = rnn.is_lbr + ? (size_t)rnn.scratch_gates_nld * rnn.scratch_gates_ld + * sizeof(typename T::gemm_acc_t) + : (utils::one_of(rd.cell_kind, alg_kind::vanilla_gru, + alg_kind::vanilla_augru) + ? (size_t)rnn.ws_states_layer_nld + * rnn.ws_states_layer_ld + * sizeof(typename T::gemm_acc_t) + : 0); + /// workspace needed for lbr GRU + rnn.ws_per_cell = (size_t)rnn.is_lbr * rnn.mb * rnn.dhc + * sizeof(typename T::gemm_acc_t); + rnn.ws_grid_comp_size = (size_t)rnn.is_lbr * rnn.is_training * rnn.n_layer + * rnn.n_dir * rnn.n_iter * rnn.ws_per_cell * sizeof(float); + /// bias ws needed to add compensation in int8 + rnn.ws_bias_size = (size_t)rnn.n_layer * rnn.n_dir * rnn.n_bias * rnn.dhc + * types::data_type_size(rnn.bias_dt); +} + +void set_offsets(const rnn_conf_t &rnn, size_t &ws_gates_offset, + size_t &ws_ht_offset, size_t &ws_state_layer_offset, + size_t &ws_states_iter_offset, size_t &ws_states_iter_c_offset, + size_t &ws_diff_states_layer_offset, size_t &ws_diff_states_iter_offset, + size_t &ws_diff_states_iter_c_offset, size_t &ws_grid_comp_offset, + size_t &ws_bias_offset, size_t &scratch_gates_offset, + size_t &scratch_ht_offset, size_t &scratch_diff_ht_offset, + size_t &scratch_cell_offset, size_t &scratchpad_size, + size_t &workspace_size); + +void get_scratchpad_and_workspace_sizes( + const rnn_conf_t &rnn, size_t &scratchpad_size, size_t &workspace_size); +status_t set_expected_desc(rnn_conf_t &rnn, memory_desc_t &weights_md, + weights_type_t weights_type); +status_t set_good_strides(memory_desc_t &weights_md, format_tag_t tag); + +using byte = unsigned char; +template +struct raw_array_offset_calculator_t { + template + raw_array_offset_calculator_t( + const byte *base, const dim_t dt_size, Targs... Fargs) + : base_ptr_(base), dt_size_(dt_size), dims_ {Fargs...} {} + + template + raw_array_offset_calculator_t(std::nullptr_t, Targs... Fargs) = delete; + + template + inline const void *operator()(Targs... Fargs) const { + assert(static_cast(base_ptr_)); + return base_ptr_ + (offset(1, Fargs...) * dt_size_); + } + +private: + template + inline size_t offset(size_t const dimension, size_t element) const { + return element; + } + template + inline size_t offset( + size_t const dimension, size_t theta, size_t element) const { + return element + (dims_[dimension] * theta); + } + + template + inline size_t offset(size_t const dimension, size_t theta, size_t element, + Targs... Fargs) const { + const size_t t_prime = element + (dims_[dimension] * theta); + return offset(dimension + 1, t_prime, Fargs...); + } + + const byte *const base_ptr_; + const dim_t dt_size_; + const int dims_[Tdims]; +}; + +template +raw_array_offset_calculator_t make_raw_aoc( + const void *base, const dim_t dt_size, Targs... Fargs) { + return raw_array_offset_calculator_t( + static_cast(base), dt_size, + std::forward(Fargs)...); +} + +template +struct ws_gates_aoc { + ws_gates_aoc(const rnn_conf_t &rnn, T *data) + : gates_(data, rnn.ws_gates_nld, rnn.ws_gates_ld), DHC_(rnn.dhc) {} + T &operator()(int batch, int gate, int dhc) const { + return gates_(batch, gate * DHC_ + dhc); + } + +private: + const dnnl::impl::utils::array_offset_calculator gates_; + const int DHC_; +}; +using ws_gates_aoc_t = ws_gates_aoc; +using ws_gates_aoc_s32_t = ws_gates_aoc; + +template +struct ws_ht_aoc { + ws_ht_aoc(const rnn_conf_t &rnn, T *data) + : ht_(data, rnn.ws_ht_nld, rnn.ws_ht_ld) {} + T &operator()(int batch, int dhc) const { return ht_(batch, dhc); } + +private: + const dnnl::impl::utils::array_offset_calculator ht_; +}; + +template +struct scratch_gates_aoc { + scratch_gates_aoc(const rnn_conf_t &rnn, T *data) + : gates_(data, rnn.scratch_gates_nld, rnn.scratch_gates_ld) + , DHC_(rnn.dhc) {} + T &operator()(int batch, int gate, int dhc) const { + return gates_(batch, gate * DHC_ + dhc); + } + +private: + const dnnl::impl::utils::array_offset_calculator gates_; + const int DHC_; +}; +using scratch_gates_aoc_t = scratch_gates_aoc; +using scratch_gates_aoc_s32_t = scratch_gates_aoc; + +template +struct scratch_ht_aoc { + scratch_ht_aoc(const rnn_conf_t &rnn, T *data) + : ht_(data, rnn.scratch_ht_nld, rnn.scratch_ht_ld) {} + T &operator()(int batch, int dhc) const { return ht_(batch, dhc); } + +private: + const dnnl::impl::utils::array_offset_calculator ht_; +}; +using scratch_ht_aoc_t = scratch_ht_aoc; +using scratch_ht_aoc_s32_t = scratch_ht_aoc; + +template +struct weights_peephole_aoc_t { + weights_peephole_aoc_t(const rnn_conf_t &rnn, T *data) + : weights_peephole_(data, 3, rnn.dhc) {} + T &operator()(int g, int dhc) const { return weights_peephole_(g, dhc); } + +private: + const utils::array_offset_calculator weights_peephole_; +}; + +float to_float(const void *data, const data_type_t dt); + +struct bias_linear_exec_aoc_t { + bias_linear_exec_aoc_t(const rnn_conf_t &rnn, void **bias) + : bias_dt_(rnn.bias_dt), bias_present_(static_cast(bias)) { + + if (bias_dt_ == data_type::f32) + new (std::addressof(bias_f32_aoc_)) + utils::array_offset_calculator( + reinterpret_cast(bias), rnn.n_layer, + rnn.n_dir, rnn.n_parts_bias); + else + new (std::addressof(bias_bf16_aoc_)) + utils::array_offset_calculator( + reinterpret_cast(bias), rnn.n_layer, + rnn.n_dir, rnn.n_parts_bias); + } + + void **operator()(int layer, int dir) const { + if (bias_present_) { + if (bias_dt_ == data_type::f32) + return reinterpret_cast( + &bias_f32_aoc_.operator()(layer, dir, 0)); + else if (bias_dt_ == data_type::bf16) + return reinterpret_cast( + &bias_bf16_aoc_.operator()(layer, dir, 0)); + } + + return nullptr; + } + + ~bias_linear_exec_aoc_t() { + if (bias_dt_ == data_type::f32) + bias_f32_aoc_.~array_offset_calculator(); + else + bias_bf16_aoc_.~array_offset_calculator(); + } + + DNNL_DISALLOW_COPY_AND_ASSIGN(bias_linear_exec_aoc_t); + bias_linear_exec_aoc_t(bias_linear_exec_aoc_t &&) = delete; + bias_linear_exec_aoc_t &operator=(bias_linear_exec_aoc_t &&) = delete; + +private: + data_type_t bias_dt_; + bool bias_present_; + union { + utils::array_offset_calculator bias_f32_aoc_; + utils::array_offset_calculator bias_bf16_aoc_; + }; +}; + +template +struct ws_states_layer_aoc { + ws_states_layer_aoc(const rnn_conf_t &rnn, T *data, int leading_dim) + : state_(data, rnn.ws_states_layer_nld, leading_dim) {} + ws_states_layer_aoc(const rnn_conf_t &rnn, T *data) + : state_(data, rnn.ws_states_layer_nld, rnn.ws_states_layer_ld) {} + T &operator()(int batch, int dhc) const { return state_(batch, dhc); } + +private: + const dnnl::impl::utils::array_offset_calculator state_; +}; + +template +struct ws_states_iter_aoc { + ws_states_iter_aoc(const rnn_conf_t &rnn, T *data, int leading_dim) + : state_(data, rnn.ws_states_iter_nld, leading_dim) {} + ws_states_iter_aoc(const rnn_conf_t &rnn, T *data) + : state_(data, rnn.ws_states_iter_nld, rnn.ws_states_iter_ld) {} + T &operator()(int batch, int dhc) const { return state_(batch, dhc); } + +private: + const dnnl::impl::utils::array_offset_calculator state_; +}; + +template +struct augru_attention_aoc { + augru_attention_aoc(const rnn_conf_t &rnn, T *data) + : state_(data, rnn.mb) {} + T &operator()(int batch) const { return state_(batch); } + +private: + const dnnl::impl::utils::array_offset_calculator state_; +}; + +template +struct ws_diff_states_layer_aoc { + ws_diff_states_layer_aoc(const rnn_conf_t &rnn, T *data) + : diff_states_layer_(data, rnn.ws_diff_states_layer_nld, + rnn.ws_diff_states_layer_ld) {} + T &operator()(int batch, int dhc) const { + return diff_states_layer_(batch, dhc); + } + +private: + const dnnl::impl::utils::array_offset_calculator diff_states_layer_; +}; + +template +struct ws_diff_states_iter_aoc { + ws_diff_states_iter_aoc(const rnn_conf_t &rnn, T *data) + : diff_states_iter_(data, rnn.ws_diff_states_iter_nld, + rnn.ws_diff_states_iter_ld) {} + T &operator()(int batch, int dhc) const { + return diff_states_iter_(batch, dhc); + } + +private: + const dnnl::impl::utils::array_offset_calculator diff_states_iter_; +}; + +template +struct ws_diff_states_iter_c_aoc { + ws_diff_states_iter_c_aoc(const rnn_conf_t &rnn, T *data) + : diff_states_iter_c_(data, rnn.ws_diff_states_iter_c_nld, + rnn.ws_diff_states_iter_c_ld) {} + T &operator()(int batch, int dhc) const { + return diff_states_iter_c_(batch, dhc); + } + +private: + const dnnl::impl::utils::array_offset_calculator diff_states_iter_c_; +}; + +struct ws_diff_w_iter_aoc_t { + ws_diff_w_iter_aoc_t(const rnn_conf_t &rnn, float *data) + : diff_weights_iter_( + data, rnn.diff_weights_iter_nld, rnn.diff_weights_iter_ld) + , DHC_(rnn.dhc) {} + float &operator()(int sic, int gate, int dhc) const { + return diff_weights_iter_(sic, gate * DHC_ + dhc); + } + +private: + const dnnl::impl::utils::array_offset_calculator + diff_weights_iter_; + const int DHC_; +}; + +const void *inc_ptr(const void *data, data_type_t data_type, int offset); +void *inc_ptr(void *data, data_type_t data_type, int offset); + +} // namespace rnn_utils +} // namespace cpu +} // namespace impl +} // namespace dnnl +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/rv64/rvv_nchw_pooling.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/rv64/rvv_nchw_pooling.hpp new file mode 100644 index 0000000000000000000000000000000000000000..ebb6f7b48741d68246a379f05310e78fd9c7873b --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/rv64/rvv_nchw_pooling.hpp @@ -0,0 +1,88 @@ +/****************************************************************************** +* Copyright 2023 KNS Group LLC (YADRO) +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef RV64_NCHW_POOLING_HPP +#define RV64_NCHW_POOLING_HPP + +#include "cpu/cpu_pooling_pd.hpp" +#include "cpu/primitive_attr_postops.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace rv64 { + +template +struct riscv_nchw_pooling_fwd_t : public primitive_t { + struct pd_t : public cpu_pooling_fwd_pd_t { + using cpu_pooling_fwd_pd_t::cpu_pooling_fwd_pd_t; + + DECLARE_COMMON_PD_T_("RISCV64GCV", riscv_nchw_pooling_fwd_t) + + status_t init(engine_t *engine) { + UNUSED(engine); + + const format_tag_t desired_fmt_tag = utils::pick(ndims() - 3, + format_tag::ncw, format_tag::nchw, format_tag::ncdhw); + + const bool is_training + = desc_.prop_kind == prop_kind::forward_training; + + const bool ok = is_fwd() + && utils::one_of(desc()->alg_kind, alg_kind::pooling_max) + && memory_desc_wrapper(dst_md()).is_dense(false) + && utils::everyone_is( + d_type, src_md()->data_type, dst_md()->data_type) + && platform::has_data_type_support(d_type) + && !has_zero_dim_memory() && !is_dilated() + && attr()->has_default_values( + primitive_attr_t::skip_mask_t::post_ops, d_type) + && set_default_params() == status::success + && memory_desc_matches_tag(*src_md(), desired_fmt_tag) + && memory_desc_matches_tag(*dst_md(), desired_fmt_tag) + && attr_.set_default_formats(dst_md(0)) == status::success + && attr()->post_ops_.len() == 0 && !is_training + && KW() < riscv_nchw_pooling_fwd_t< + d_type>::max_kernel_width; + + if (!ok) return status::unimplemented; + + return status::success; + } + }; + + riscv_nchw_pooling_fwd_t(const pd_t *apd); + + using data_t = typename prec_traits::type; + + status_t execute(const exec_ctx_t &ctx) const override { + return execute_forward(ctx); + } + + constexpr static int max_kernel_width = 32; + +private: + status_t execute_forward(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + const ref_post_ops_t ref_post_ops_; +}; + +} // namespace rv64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/s390x/kernel_s16s16s32.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/s390x/kernel_s16s16s32.hpp new file mode 100644 index 0000000000000000000000000000000000000000..a88c4551d7bb3e8821d8543981f4a301e5b6dd88 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/s390x/kernel_s16s16s32.hpp @@ -0,0 +1,247 @@ +/******************************************************************************* +* Copyright 2023 IBM Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ +#ifndef CPU_S390X_KERNELS_S16S16S32_HPP +#define CPU_S390X_KERNELS_S16S16S32_HPP + +#include +#include "common/utils.hpp" +#include "cpu/s390x/helpers.h" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace s390x { + +constexpr int MR = 16; +constexpr int NR = 4; + +constexpr int fullVectored(int N, int size) { + return (N % (VLEN_BYTES / size)) == 0; +} + +constexpr int kernelType(int ROWS, int COLS, int elementSize) { + return fullVectored(ROWS, elementSize) ? 1 : 2; +} + +template +inline typename utils::enable_if::type +gbp(dim_t k, const int16_t *__restrict MP_A, const int16_t *__restrict MP_B, + int32_t *__restrict C, dim_t ldC) { + using vType = typename vec_type_t::Type; + constexpr int VLEN = vec_type_t::size(); + const int32_t *MT_A = reinterpret_cast(MP_A); + const int32_t *MT_B = reinterpret_cast(MP_B); + + vec_type_t Caux[ROWS / VLEN][COLS] = {}; + dim_t real_k = k / 2; + dim_t real_k_4 = real_k & (-4); + + if (real_k & 3) { + for (dim_t p = 0; p < (real_k & 3); p++) { + for (int i = 0; i < ROWS / VLEN; i++) { + auto Ak = cast( + vec_type_t::load_hinted(&MT_A[i * VLEN])); + + for (int j = 0; j < COLS; j++) { + auto BkI = cast(vec_type_t {MT_B[j]}); + + Caux[i][j] = multiplyAdd(Ak, BkI, Caux[i][j]); + } + } + MT_A += ROWS; + MT_B += COLS; + } + } + + asm(""); + + for (dim_t p = 0; p < real_k_4; p += 4) { + for (int i = 0; i < ROWS / VLEN; i++) { + auto Ak0 = cast( + vec_type_t::load_hinted(&MT_A[i * VLEN])); + auto Ak1 = cast( + vec_type_t::load_hinted(&MT_A[i * VLEN + ROWS])); + auto Ak2 = cast(vec_type_t::load_hinted( + &MT_A[i * VLEN + 2 * ROWS])); + auto Ak3 = cast(vec_type_t::load_hinted( + &MT_A[i * VLEN + 3 * ROWS])); + for (int j = 0; j < COLS; j++) { + auto BkI0 = cast(vec_type_t {MT_B[j]}); + auto BkI1 = cast(vec_type_t {MT_B[j + COLS]}); + auto BkI2 = cast( + vec_type_t {MT_B[j + 2 * COLS]}); + auto BkI3 = cast( + vec_type_t {MT_B[j + 3 * COLS]}); + + Caux[i][j] = multiplyAdd(Ak0, BkI0, Caux[i][j]); + Caux[i][j] = multiplyAdd(Ak1, BkI1, Caux[i][j]); + Caux[i][j] = multiplyAdd(Ak2, BkI2, Caux[i][j]); + Caux[i][j] = multiplyAdd(Ak3, BkI3, Caux[i][j]); + } + } + + MT_A += 4 * ROWS; + MT_B += 4 * COLS; + } + + asm(""); + for (int j = 0; j < COLS; j++) { + for (int i = 0; i < ROWS / VLEN; i++) { + vType *C_ij = (vType *)&gPtr(i * VLEN, j); + *C_ij += (vType)Caux[i][j]; + } + } +} + +template +inline typename utils::enable_if::type +gbp(dim_t k, const int16_t *__restrict MP_A, const int16_t *__restrict MP_B, + int32_t *__restrict C, dim_t ldC) { + + const int32_t *MT_A = reinterpret_cast(MP_A); + const int32_t *MT_B = reinterpret_cast(MP_B); + + vec_type_t Caux[COLS] = {}; + dim_t real_k = k / 2; + dim_t real_k_4 = real_k & (-4); + constexpr int BYTE_INDEX = ROWS * 2 * sizeof(int16_t) - 1; + + if (real_k & 3) { + for (dim_t p = 0; p < (real_k & 3); p++) { + + auto Ak = cast( + vec_type_t::loadLen(MT_A, BYTE_INDEX)); + + for (int j = 0; j < COLS; j++) { + auto BkI = cast(vec_type_t {MT_B[j]}); + + Caux[j] = multiplyAdd(Ak, BkI, Caux[j]); + } + + MT_A += ROWS; + MT_B += COLS; + } + } + + asm(""); + + for (dim_t p = 0; p < real_k_4; p += 4) { + + auto Ak0 = cast( + vec_type_t::loadLen(&MT_A[0], BYTE_INDEX)); + auto Ak1 = cast( + vec_type_t::loadLen(&MT_A[ROWS], BYTE_INDEX)); + auto Ak2 = cast( + vec_type_t::loadLen(&MT_A[2 * ROWS], BYTE_INDEX)); + auto Ak3 = cast( + vec_type_t::loadLen(&MT_A[3 * ROWS], BYTE_INDEX)); + for (int j = 0; j < COLS; j++) { + auto BkI0 = cast(vec_type_t {MT_B[j]}); + auto BkI1 = cast(vec_type_t {MT_B[j + COLS]}); + auto BkI2 = cast(vec_type_t {MT_B[j + 2 * COLS]}); + auto BkI3 = cast(vec_type_t {MT_B[j + 3 * COLS]}); + + Caux[j] = multiplyAdd(Ak0, BkI0, Caux[j]); + Caux[j] = multiplyAdd(Ak1, BkI1, Caux[j]); + Caux[j] = multiplyAdd(Ak2, BkI2, Caux[j]); + Caux[j] = multiplyAdd(Ak3, BkI3, Caux[j]); + } + MT_A += 4 * ROWS; + MT_B += 4 * COLS; + } + + asm(""); + for (int j = 0; j < COLS; j++) { + auto C_ij = vec_type_t::loadLen(&gPtr(0, j), BYTE_INDEX); + C_ij += Caux[j]; + C_ij.storeLen(&gPtr(0, j), BYTE_INDEX); + } +} + +template +typename utils::enable_if<(M >= ROWS), void>::type LoopOne_TAIL(dim_t m, + dim_t k, const int16_t *Apacked, const int16_t *Bpacked, int32_t *C, + dim_t ldC) { + // end of the roll +} + +template +typename utils::enable_if<(M < ROWS), void>::type LoopOne_TAIL(dim_t m, dim_t k, + const int16_t *Apacked, const int16_t *Bpacked, int32_t *C, dim_t ldC) { + if (m & M) { + gbp(k, Apacked, Bpacked, C, ldC); + Apacked = &Apacked[M * k]; + C = &gPtr(M, 0); + } + LoopOne_TAIL<2 * M, ROWS, COLS>(m, k, Apacked, Bpacked, C, ldC); +} + +template +inline void LoopOne(dim_t m, dim_t k, const int16_t *Apacked, + const int16_t *Bpacked, int32_t *C, dim_t ldC) { + for (dim_t i = 0; i < m / ROWS; i++) { + gbp( + k, &Apacked[i * ROWS * k], Bpacked, &gPtr(i * ROWS, 0), ldC); + } + dim_t II = m - m % ROWS; + if (m > II) + LoopOne_TAIL<1, ROWS, COLS>( + m - II, k, &Apacked[II * k], Bpacked, &gPtr(II, 0), ldC); +} + +template +typename utils::enable_if<(N >= COLS), void>::type LoopTwo_TAIL(dim_t m, + dim_t n, dim_t k, const int16_t *Apacked, const int16_t *Bpacked, + int32_t *C, dim_t ldC) { + // end of the roll +} + +template +typename utils::enable_if<(N < COLS), void>::type LoopTwo_TAIL(dim_t m, dim_t n, + dim_t k, const int16_t *Apacked, const int16_t *Bpacked, int32_t *C, + dim_t ldC) { + if (n & N) { + LoopOne(m, k, Apacked, Bpacked, C, ldC); + Bpacked = &Bpacked[N * k]; + C = &gPtr(0, N); + } + LoopTwo_TAIL<2 * N, COLS>(m, n, k, Apacked, Bpacked, C, ldC); +} + +template +void __attribute__((noinline)) LoopTwo(dim_t m, dim_t n, dim_t k, + const int16_t *Apacked, const int16_t *Bpacked, int32_t *C, dim_t ldC) { + for (dim_t j = 0; j < n / COLS; j++) { + LoopOne( + m, k, Apacked, &Bpacked[j * COLS * k], &gPtr(0, j * COLS), ldC); + } + // tails , should be unrolled + // for example n&1, n&2 and et cetera + // actually its possible to combine tail JJ) + LoopTwo_TAIL<1, COLS>( + m, n - JJ, k, Apacked, &Bpacked[JJ * k], &gPtr(0, JJ), ldC); +} + +} // namespace s390x +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/s390x/pack.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/s390x/pack.hpp new file mode 100644 index 0000000000000000000000000000000000000000..dc01e98347e8a1d375910a80fb23b39354f31ec1 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/s390x/pack.hpp @@ -0,0 +1,112 @@ +/******************************************************************************* +* Copyright 2023 IBM Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ +#ifndef CPU_S390X_KERNELS_PACK_HPP +#define CPU_S390X_KERNELS_PACK_HPP +#include "common/utils.hpp" +#include "cpu/s390x/helpers.h" +namespace dnnl { +namespace impl { +namespace cpu { +namespace s390x { + +template +typename utils::enable_if<(KK == 2), void>::type pack_G_KK(int k, + const T *__restrict src, int srcLD, DT *__restrict dst, + DT add_val = 0) { + auto Src = matrix_ptr_t {src, srcLD}; + + for (int p = 0; p < k / 2; p++) { + for (int j = 0; j < G; j++) { + dst[0] = (DT)Src(2 * p, j) + add_val; + dst[1] = (DT)Src(2 * p + 1, j) + add_val; + dst += 2; + } + } + int k_2 = k & (-2); + if ((k & 1) == 1) { + for (int j = 0; j < G; j++) { + dst[0] = (DT)Src(k_2, j) + add_val; + dst[1] = (DT)add_val; + dst += 2; + } + } +} + +template +typename utils::enable_if<(KK == 1), void>::type pack_G_KK( + int k, const T *src, int srcLD, T *dst, DT add_val) { + auto Src = matrix_ptr_t {src, srcLD}; + + for (int p = 0; p < k; p++) { + for (int j = 0; j < G; j++) { + *dst++ = (DT)Src(p, j) + add_val; + } + } +} + +template +typename utils::enable_if<(N >= G), void>::type pack_KK_TAILS(const int k, + const int n, const T *__restrict src, int srcLD, DT *__restrict dst, + DT add_val = 0) { + // no need to unroll +} + +template +typename utils::enable_if<(N < G), void>::type pack_KK_TAILS(const int k, + const int n, const T *__restrict src, int srcLD, DT *__restrict dst, + DT add_val = 0) { + if (n & N) { + + // for example n&1, n&2 and et cetera + pack_G_KK(k, src, srcLD, dst, add_val); + int kk = (k + KK - 1) & (-KK); + auto Src = matrix_ptr_t {src, srcLD}; + src = Src.ptr(0, N); + dst += N * kk; + } + + pack_KK_TAILS(k, n, src, srcLD, dst, add_val); +} + +template +void __attribute__((noinline)) +pack_K(const int k, const int n, const T *__restrict src, int srcLD, + DT *__restrict dst, DT add_val = 0) { + + // if k is not divisible by 4 , the rest will be 0-ed + constexpr bool accessSide = trans ? (!ISLASTINDEX_FAST) : ISLASTINDEX_FAST; + int kk = (k + KK - 1) & (-KK); + int nn = n - n % G; // n & (-G); G should be power of 2, so let the + // compiler to decide + auto Src = matrix_ptr_t {src, srcLD}; + for (int j = 0; j < nn; j += G) { + pack_G_KK(k, Src.ptr(0, j), srcLD, dst, add_val); + // last dst will not be accessed + dst += G * kk; + } + + // if not padded fully + // unroll with those conditions: + // k&1 k&2 k&4 k&8 and so on + pack_KK_TAILS<1, G, KK, accessSide>( + k, n - nn, Src.ptr(0, nn), srcLD, dst, add_val); +} + +} // namespace s390x +} // namespace cpu +} // namespace impl +} // namespace dnnl +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/simple_layer_normalization.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/simple_layer_normalization.hpp new file mode 100644 index 0000000000000000000000000000000000000000..827fafb015cce4482aec76bf2f59db62aeb4e096 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/simple_layer_normalization.hpp @@ -0,0 +1,225 @@ +/******************************************************************************* +* Copyright 2019-2022 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_SIMPLE_LAYER_NORMALIZATION_HPP +#define CPU_SIMPLE_LAYER_NORMALIZATION_HPP + +#include + +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/memory_tracking.hpp" +#include "common/primitive.hpp" +#include "common/reorder_pd.hpp" +#include "common/stream.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_layer_normalization_pd.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { + +struct simple_layer_normalization_fwd_t : public primitive_t { + struct pd_t : public cpu_layer_normalization_fwd_pd_t { + using cpu_layer_normalization_fwd_pd_t:: + cpu_layer_normalization_fwd_pd_t; + + DECLARE_COMMON_PD_T("simple:any", simple_layer_normalization_fwd_t); + + status_t init(engine_t *engine); + + bool use_tmp_stats() const { return reorder_pd_ || stats_are_tmp(); } + + std::shared_ptr reorder_pd_; + memory_desc_t reordered_stat_md_; + + private: + void init_scratchpad() { + using namespace memory_tracking::names; + auto scratchpad = scratchpad_registry().registrar(); + if (use_tmp_stats()) { + scratchpad.template book( + key_lnorm_tmp_mean, across_axis()); + scratchpad.template book( + key_lnorm_tmp_var, across_axis()); + } + if (reordered_stat_md_ != *stat_md() && !stats_are_tmp()) { + scratchpad.book(key_nested, reorder_pd_->scratchpad_registry()); + } + } + }; + + status_t init(engine_t *engine) override { + if (pd()->reorder_pd_) + pd()->reorder_pd_->create_primitive(reorder_, engine); + return status::success; + } + + simple_layer_normalization_fwd_t(const pd_t *apd) : primitive_t(apd) {} + + void reorder_stat(const exec_ctx_t &ctx, engine_t *engine, + const memory_arg_t &in, const memory_arg_t &out) const { + using namespace memory_tracking::names; + exec_args_t r_args; + r_args[DNNL_ARG_SRC] = in; + r_args[DNNL_ARG_DST] = out; + exec_ctx_t r_ctx(ctx, std::move(r_args)); + + nested_scratchpad_t ns(ctx, key_nested, reorder_); + r_ctx.set_scratchpad_grantor(ns.grantor()); + reorder_->execute(r_ctx); + } + + status_t execute(const exec_ctx_t &ctx) const override { + /* LN supports arbitrary layout for input/output statistics. + * For best performance we compute LN with statistics in the same format + * as data tensor (i.e. data in abcd, stats in abc) and user's + * input/output statistics are reordered if necessary */ + using namespace memory_tracking::names; + engine_t *engine = ctx.stream()->engine(); + auto scratchpad = ctx.get_scratchpad_grantor(); + auto mean_mem = scratchpad.get_memory_storage(key_lnorm_tmp_mean); + auto variance_mem = scratchpad.get_memory_storage(key_lnorm_tmp_var); + memory_t mean(engine, &(pd()->reordered_stat_md_), std::move(mean_mem)); + memory_t variance( + engine, &(pd()->reordered_stat_md_), std::move(variance_mem)); + + // reorder input stats + if (pd()->stats_are_src() && reorder_) { + reorder_stat( + ctx, engine, ctx.args().at(DNNL_ARG_MEAN), {&mean, false}); + reorder_stat(ctx, engine, ctx.args().at(DNNL_ARG_VARIANCE), + {&variance, false}); + } + status_t status = execute_forward(ctx); + if (status != status::success) return status; + // reorder output stats + if (!pd()->stats_are_src() && reorder_) { + reorder_stat( + ctx, engine, {&mean, true}, ctx.args().at(DNNL_ARG_MEAN)); + reorder_stat(ctx, engine, {&variance, true}, + ctx.args().at(DNNL_ARG_VARIANCE)); + } + + return status::success; + } + +private: + status_t execute_forward(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::shared_ptr reorder_; +}; + +struct simple_layer_normalization_bwd_t : public primitive_t { + struct pd_t : public cpu_layer_normalization_bwd_pd_t { + using cpu_layer_normalization_bwd_pd_t:: + cpu_layer_normalization_bwd_pd_t; + + DECLARE_COMMON_PD_T("simple:any", simple_layer_normalization_bwd_t); + + status_t init(engine_t *engine); + + bool use_tmp_stats() const { return reorder_pd_.get(); } + + std::shared_ptr reorder_pd_; + memory_desc_t reordered_stat_md_; + int nthr_; // To not exceed the limit in execute used for set up. + + private: + void init_scratchpad() { + using namespace memory_tracking::names; + auto scratchpad = scratchpad_registry().registrar(); + if (use_tmp_stats()) { + scratchpad.template book( + key_lnorm_tmp_mean, across_axis()); + scratchpad.template book( + key_lnorm_tmp_var, across_axis()); + } + scratchpad.template book( + key_lnorm_reduction, 2 * norm_axis() * nthr_); + scratchpad.template book( + key_lnorm_tmp_diff_ss, 2 * norm_axis()); + if (reordered_stat_md_ != *stat_md() && !stats_are_tmp()) { + scratchpad.book(key_nested, reorder_pd_->scratchpad_registry()); + } + scratchpad.template book( + key_lnorm_inv_sqrtvar, across_axis()); + } + }; + + status_t init(engine_t *engine) override { + if (pd()->reorder_pd_) + pd()->reorder_pd_->create_primitive(reorder_, engine); + return status::success; + } + + simple_layer_normalization_bwd_t(const pd_t *apd) : primitive_t(apd) {} + + void reorder_stat(const exec_ctx_t &ctx, engine_t *engine, + const memory_arg_t &in, const memory_arg_t &out) const { + using namespace memory_tracking::names; + exec_args_t r_args; + r_args[DNNL_ARG_SRC] = in; + r_args[DNNL_ARG_DST] = out; + exec_ctx_t r_ctx(ctx, std::move(r_args)); + + nested_scratchpad_t ns(ctx, key_nested, reorder_); + r_ctx.set_scratchpad_grantor(ns.grantor()); + reorder_->execute(r_ctx); + } + + status_t execute(const exec_ctx_t &ctx) const override { + using namespace memory_tracking::names; + /* LN supports arbitrary layout for input/output statistics. + * For best performance we compute LN with statistics in the same format + * as data tensor (i.e. data in abcd, stats in abc) and user's + * input/output statistics are reordered if necessary */ + + if (reorder_) { + engine_t *engine = ctx.stream()->engine(); + auto scratchpad = ctx.get_scratchpad_grantor(); + auto mean_mem = scratchpad.get_memory_storage(key_lnorm_tmp_mean); + auto variance_mem + = scratchpad.get_memory_storage(key_lnorm_tmp_var); + memory_t mean( + engine, &(pd()->reordered_stat_md_), std::move(mean_mem)); + memory_t variance(engine, &(pd()->reordered_stat_md_), + std::move(variance_mem)); + reorder_stat( + ctx, engine, ctx.args().at(DNNL_ARG_MEAN), {&mean, false}); + reorder_stat(ctx, engine, ctx.args().at(DNNL_ARG_VARIANCE), + {&variance, false}); + } + + return execute_backward(ctx); + } + +private: + status_t execute_backward(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::shared_ptr reorder_; +}; + +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino^=l0,\:0,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/simple_q10n.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/simple_q10n.hpp new file mode 100644 index 0000000000000000000000000000000000000000..09c478dec9087e836f4d942747f1dd363c402f47 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/simple_q10n.hpp @@ -0,0 +1,176 @@ +/******************************************************************************* +* Copyright 2017-2020 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_SIMPLE_Q10N_HPP +#define CPU_SIMPLE_Q10N_HPP + +#include + +#include "common/c_types_map.hpp" +#include "common/math_utils.hpp" +#include "common/nstl.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { + +template +inline typename utils::enable_if::value, + typename utils::remove_reference::type>::type +saturate(const acc_t &x) { + acc_t v = x; + return v; +} + +template +inline typename utils::enable_if::value, + typename utils::remove_reference::type>::type +saturate(const acc_t &x) { + acc_t v = x; + acc_t lbound = (acc_t)nstl::numeric_limits::lowest(); + // Pick up a modified version of max value when do f32 -> s32. + acc_t ubound = types::max_value(data_traits::data_type); + if (v < lbound) v = lbound; + if (v > ubound) v = ubound; + return v; +} + +template <> +inline uint8_t saturate(const uint8_t &x) { + return x <= 127u ? x : 127; +} + +template <> +inline int8_t saturate(const int8_t &x) { + return x >= 0 ? x : 0; +} + +template +inline typename utils::enable_if::value, + typename utils::remove_reference::type>::type +out_round(float v) { + return (out_t)math::mxcsr_cvt(v); +} + +template +inline typename utils::enable_if::value, + typename utils::remove_reference::type>::type +out_round(float v) { + return v; +} + +template +inline out_t saturate_and_round(acc_t f) { + return out_round(saturate(f)); +} + +/* Quantization with alpha == 1 and beta == 0 */ +template +struct qz_a1b0 { + out_t operator()(in_t in) { return saturate_and_round((float)in); } +}; + +template +struct qz_a1b0::value + && !is_subset::value>::type> { + out_t operator()(in_t in) { return saturate(in); } +}; + +template +struct qz_a1b0::value>::type> { + out_t operator()(in_t in) { return (out_t)in; } +}; + +/* Quantization with alpha == 1 */ +template +struct qz_a1 { + out_t operator()(in_t in, out_t out, float beta) { + return saturate_and_round((float)in + beta * out); + } +}; + +template +struct qz_a1 { + float operator()(in_t in, float out, float beta) { + return (float)in + beta * out; + } +}; + +/* Quantization with beta == 0 */ +template +struct qz_b0 { + out_t operator()(in_t in, float alpha) { + return saturate_and_round(alpha * in); + } +}; + +template +struct qz_b0 { + float operator()(in_t in, float alpha) { return alpha * in; } +}; + +/* Quantization */ +template +struct qz { + out_t operator()(in_t in, out_t out, float alpha, float beta) { + return saturate_and_round(alpha * in + (beta ? beta * out : 0)); + } +}; + +template +struct qz { + float operator()(in_t in, float out, float alpha, float beta) { + return alpha * in + (beta ? beta * out : 0); + } +}; + +template <> +struct qz { + float operator()(bfloat16_t in, bfloat16_t out, float alpha, float beta) { + return (bfloat16_t)(alpha * (float)in + (beta ? beta * (float)out : 0)); + } +}; + +template <> +struct qz { + float operator()(float in, bfloat16_t out, float alpha, float beta) { + return (bfloat16_t)(alpha * in + (beta ? beta * out : 0)); + } +}; + +template <> +struct qz { + float operator()(float16_t in, float16_t out, float alpha, float beta) { + return (float16_t)(alpha * (float)in + (beta ? beta * (float)out : 0)); + } +}; + +template <> +struct qz { + float operator()(float in, float16_t out, float alpha, float beta) { + return (float16_t)(alpha * in + (beta ? beta * out : 0)); + } +}; + +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/simple_resampling.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/simple_resampling.hpp new file mode 100644 index 0000000000000000000000000000000000000000..331aec4c0a6bc4aaaff2939855a35ae5015da4ed --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/simple_resampling.hpp @@ -0,0 +1,148 @@ +/******************************************************************************* +* Copyright 2019-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_SIMPLE_RESAMPLING_HPP +#define CPU_SIMPLE_RESAMPLING_HPP + +#include +#include + +#include "common/c_types_map.hpp" +#include "common/primitive.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/platform.hpp" +#include "cpu/primitive_attr_postops.hpp" + +#include "cpu/cpu_resampling_pd.hpp" +#include "cpu/resampling_utils.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { + +struct simple_resampling_base_t { + simple_resampling_base_t(const resampling_pd_t *pd) : pd_(pd) {} + virtual ~simple_resampling_base_t() = default; + + virtual status_t init() = 0; + virtual status_t execute(const exec_ctx_t &ctx) const = 0; + +protected: + const resampling_pd_t *pd_; + + dim_t nsp_outer_ = 0; + dim_t stride_d_ = 0; + dim_t stride_h_ = 0; + dim_t stride_w_ = 0; + dim_t inner_stride_ = 0; + dim_t tail_size_ = 0; +}; + +struct simple_resampling_fwd_t : public primitive_t { + struct pd_t : public cpu_resampling_fwd_pd_t { + using cpu_resampling_fwd_pd_t::cpu_resampling_fwd_pd_t; + + DECLARE_COMMON_PD_T("simple:any", simple_resampling_fwd_t); + + status_t init(engine_t *engine) { + using namespace format_tag; + using namespace data_type; + using sm = primitive_attr_t::skip_mask_t; + + const bool ok = is_fwd() && !has_zero_dim_memory() + && platform::has_data_type_support(src_md()->data_type) + && platform::has_data_type_support(dst_md()->data_type) + && set_default_params() == status::success + && attr()->has_default_values( + sm::post_ops, dst_md()->data_type) + && attr_.set_default_formats(dst_md(0)) == status::success; + if (!ok) return status::unimplemented; + + const bool has_binary + = attr()->post_ops_.find(primitive_kind::binary) >= 0; + if (has_binary) { + if (memory_desc_matches_one_of_tag(*dst_md(0), ncw, nchw, ncdhw) + == format_tag::undef) + return status::unimplemented; + } + + format_tag_t dat_tag = memory_desc_matches_one_of_tag(*src_md(), + nCw8c, nChw8c, nCdhw8c, nCw16c, nChw16c, nCdhw16c, ncw, + nchw, ncdhw, nwc, nhwc, ndhwc); + if (!memory_desc_matches_tag(*dst_md(), dat_tag)) + return status::unimplemented; + + return status::success; + } + }; + + simple_resampling_fwd_t(const pd_t *apd); + status_t init(engine_t *engine) override; + ~simple_resampling_fwd_t() = default; + + status_t execute(const exec_ctx_t &ctx) const override; + +private: + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr kernel_; +}; + +struct simple_resampling_bwd_t : public primitive_t { + struct pd_t : public cpu_resampling_bwd_pd_t { + using cpu_resampling_bwd_pd_t::cpu_resampling_bwd_pd_t; + + DECLARE_COMMON_PD_T("simple:any", simple_resampling_bwd_t); + + status_t init(engine_t *engine) { + using namespace format_tag; + using namespace data_type; + const bool ok = !is_fwd() && !has_zero_dim_memory() + && platform::has_data_type_support(diff_dst_md()->data_type) + && platform::has_data_type_support(diff_src_md()->data_type) + && set_default_params() == status::success + && attr()->has_default_values(); + if (!ok) return status::unimplemented; + + format_tag_t dat_tag = memory_desc_matches_one_of_tag( + *diff_src_md(), nCw8c, nChw8c, nCdhw8c, nCw16c, nChw16c, + nCdhw16c, ncw, nchw, ncdhw, nwc, nhwc, ndhwc); + if (!memory_desc_matches_tag(*diff_dst_md(), dat_tag)) + return status::unimplemented; + + return status::success; + } + }; + + simple_resampling_bwd_t(const pd_t *apd); + status_t init(engine_t *engine) override; + ~simple_resampling_bwd_t() = default; + + status_t execute(const exec_ctx_t &ctx) const override; + +private: + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr kernel_; +}; + +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/simple_sum.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/simple_sum.hpp new file mode 100644 index 0000000000000000000000000000000000000000..5ad91efdbd301a4bafe4e742cc4ed3c7183b083d --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/simple_sum.hpp @@ -0,0 +1,135 @@ +/******************************************************************************* +* Copyright 2017-2022 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_SIMPLE_SUM_HPP +#define CPU_SIMPLE_SUM_HPP + +#include "common/dnnl_thread.hpp" +#include "common/primitive.hpp" +#include "common/type_helpers.hpp" + +#include "cpu/cpu_sum_pd.hpp" +#include "cpu/platform.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { + +struct sum_xf16_params_t { + dim_t ws_cvt_elements_per_thread_; + dim_t ws_acc_elements_per_thread_; + dim_t ws_elements_per_thread_; + dim_t acc_loop_step_; +}; + +template +struct simple_sum_t : public primitive_t { + struct pd_t : public cpu_sum_pd_t { + using cpu_sum_pd_t::cpu_sum_pd_t; + + DECLARE_SUM_PD_T("simple:any", simple_sum_t); + + status_t init(engine_t *engine) { + const int n = n_inputs(); + + bool ok = platform::has_data_type_support(src_data_type) + && platform::has_data_type_support(dst_data_type) + && cpu_sum_pd_t::init(engine) == status::success + && n <= max_num_arrs; + if (!ok) return status::unimplemented; + + const memory_desc_wrapper o_d(dst_md()); + ok = ok && o_d.data_type() == dst_data_type && o_d.is_dense(); + if (!ok) return status::unimplemented; + + for (int i = 0; i < n; ++i) { + const memory_desc_wrapper i_d(src_md(i)); + ok = true && utils::everyone_is(src_data_type, i_d.data_type()) + && o_d.similar_to(i_d, true, false, 0) + && i_d.is_dense(); + if (!ok) return status::unimplemented; + } + nthr_ = dnnl_get_max_threads(); + compute_blocking(); + init_scratchpad(); + return status::success; + } + int nthr_ = 1; + sum_xf16_params_t xf16_params_; + dim_t block_size_ = 0, nelems_ = 0, blocks_number_ = 0, tail_ = 0; + + private: + void compute_blocking() { + const int block_size_bytes + = utils::one_of( + src_data_type, data_type::bf16, data_type::f16) + ? 16 * platform::get_cache_line_size() + : platform::get_per_core_cache_size(1) / 2; + block_size_ = block_size_bytes / (int)sizeof(src_data_type); + const memory_desc_wrapper o_d(dst_md()); + nelems_ = o_d.nelems(); + blocks_number_ = nelems_ / block_size_; + tail_ = nelems_ % block_size_; + } + + void init_scratchpad() { + if (utils::one_of(src_data_type, data_type::bf16, data_type::f16)) { + const bool is_dst_xf16 = utils::one_of( + dst_data_type, data_type::bf16, data_type::f16); + xf16_params_.ws_cvt_elements_per_thread_ + = platform::get_cache_line_size() + / (int)sizeof(acc_data_t); + + xf16_params_.ws_acc_elements_per_thread_ = is_dst_xf16 + ? xf16_params_.ws_cvt_elements_per_thread_ + : 0; + + xf16_params_.acc_loop_step_ = is_dst_xf16 + ? xf16_params_.ws_cvt_elements_per_thread_ + : 1; + + xf16_params_.ws_elements_per_thread_ + = xf16_params_.ws_cvt_elements_per_thread_ + + xf16_params_.ws_acc_elements_per_thread_; + const dim_t cvt_buf_sz + = xf16_params_.ws_elements_per_thread_ * nthr_; + auto scratchpad = scratchpad_registry().registrar(); + scratchpad.template book( + memory_tracking::names::key_sum_srcs_cvt, cvt_buf_sz); + } + } + }; + + simple_sum_t(const pd_t *apd) : primitive_t(apd) {} + + status_t execute(const exec_ctx_t &ctx) const override; + + enum { max_num_arrs = 16 }; + typedef typename prec_traits::type src_data_t; + typedef typename prec_traits::type dst_data_t; + typedef typename prec_traits::type acc_data_t; + +private: + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } +}; + +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/amx_tile_configure.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/amx_tile_configure.hpp new file mode 100644 index 0000000000000000000000000000000000000000..5dbd7b2411a4938ba1cacc0298373e0628a9071b --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/amx_tile_configure.hpp @@ -0,0 +1,36 @@ +/******************************************************************************* +* Copyright 2020-2021 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_AMX_TILE_CONFIGURE_HPP +#define CPU_X64_AMX_TILE_CONFIGURE_HPP + +#include "common/type_helpers.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +static constexpr size_t AMX_PALETTE_SIZE = 64; +status_t DNNL_API amx_tile_configure(const char palette[AMX_PALETTE_SIZE]); +status_t DNNL_API amx_tile_release(); + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/brgemm/brgemm.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/brgemm/brgemm.hpp new file mode 100644 index 0000000000000000000000000000000000000000..b0a4af878548101ac33ec668331de6be88fa690e --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/brgemm/brgemm.hpp @@ -0,0 +1,271 @@ +/******************************************************************************* +* Copyright 2020-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_BRGEMM_BRGEMM_HPP +#define CPU_X64_BRGEMM_BRGEMM_HPP + +#include "cpu/x64/brgemm/brgemm_types.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { +/// Initializes a BRGEMM descriptor +/// +/// @param brg Output BRGEMM descriptor +/// @param isa Target ISA of BRGEMM kernel +/// If isa is equal to 'isa_undef' maximum supported ISA on current +/// hardware will be used for BRGEMM kernel generation +/// @param type Type of batch +/// @param dt_a Data type of A matrix, can be +/// AVX512: f32, u8(row-major layout), s8(column-major layout), bf16, f16 +/// AMX: u8, s8, bf16, f16 +/// @param dt_b Data type of B matrix +/// AVX512: f32, s8(row-major layout), u8(column-major layout), bf16, f16 +/// AMX: u8, s8, bf16, f16 +/// @note +/// Data type of matrix C depends on data types of matrices A and B +/// If A and B have integer u8/s8 data type, C has int32 data type +/// If A and B have bf16 or f16 or f32 data type, C has f32 data type +/// @param transA Specifies the form of A used in the matrix multiplication +/// 'false' - A is not transposed, 'true' - A is transposed +/// @param transB Specifies the form of B used in the matrix multiplication +/// 'false' - B is not transposed, 'true' - B is transposed +/// @param layout Specifies whether two-dimensional array storage is row-major +/// (brgemm_row_major) or column-major (brgemm_col_major). +/// @param alpha Specifies the scalar alpha +/// @param beta Specifies the scalar beta +/// @param LDA Specifies the leading dimension of matrix A. +/// LDA must be at least max(1, K) +/// @param LDB Specifies the leading dimension of matrix B. +/// LDB must be at least max(1, N) +/// @param LDC Specifies the leading dimension of matrix C. +/// LDC must be at least max(1, N) +/// @param M Specifies the number of rows of the matrix A and of the matrix C. +/// @param N Specifies the number of columns of the matrix B and +/// the number of columns of the matrix C +/// @param K Specifies the number of columns of the matrix A and +/// the number of rows of the matrix B +/// @param strides Strides between the matrices in the batch. Can be nullptr. +/// +status_t DNNL_API brgemm_desc_init(brgemm_t *brg, cpu_isa_t isa, + brgemm_batch_kind_t type, impl::data_type_t dt_a, + impl::data_type_t dt_b, bool transA, bool transB, + brgemm_layout_t layout, float alpha, float beta, dim_t LDA, dim_t LDB, + dim_t LDC, dim_t M, dim_t N, dim_t K, + const brgemm_strides_t *strides = nullptr); + +/// Initializes a BRGEMM descriptor with B matrix as a diagonal matrix +/// represented in packed vector format. +/// +/// @param brg Output BRGEMM descriptor +/// @param isa Target ISA of BRGEMM kernel +/// If isa is equal to 'isa_undef' maximum supported ISA on current +/// hardware will be used for BRGEMM kernel generation +/// @param type Type of batch +/// @param dt_a Data type of A matrix can be: f32, u8, bf16, f16 +/// @param dt_b Data type of B vector can be: f32, s8, bf16, f16 +/// @note +/// Data type of matrix C depends on data types of matrices A and vector B +/// If A and B have integer u8/s8 data type, C has int32 data type +/// If A and B have bf16 or f16 or f32 data type, C has f32 data type +/// @param transA Specifies the form of A used in the matrix multiplication +/// 'false' - A is not transposed, 'true' - A is transposed +/// @param layout Specifies whether two-dimensional array storage is row-major +/// (brgemm_row_major) or column-major (brgemm_col_major). +/// @param alpha Specifies the scalar alpha +/// @param beta Specifies the scalar beta +/// @param LDA Specifies the leading dimension of matrix A. +/// LDA must be at least max(1, N) +/// @param LDC Specifies the leading dimension of matrix C. +/// LDC must be at least max(1, N) +/// @param M Specifies the number of rows of the matrix A and C. +/// @param N Specifies the number of columns of the matrix A and C. +/// +status_t DNNL_API brdgmm_desc_init(brgemm_t *brg, cpu_isa_t isa, + brgemm_batch_kind_t type, impl::data_type_t dt_a, + impl::data_type_t dt_b, bool transA, brgemm_layout_t layout, + float alpha, float beta, dim_t LDA, dim_t LDC, dim_t M, dim_t N, + const brgemm_strides_t *strides = nullptr); + +/// Adds post-operations to BRGEMM descriptor +/// +/// @param brg Output BRGEMM descriptor +/// @param attr Primitive attributes (can be nullptr). Specifies post-ops +/// operations +/// @param dst_md Specifies the memory descriptor of the destination tensor, +/// needed for binary postops to determine broadcast type, as well as to +/// determine dst data type. +/// @param LDD Specifies the leading dimension of matrix D +/// LDD must be at least max(1, N) +/// @param dt_bias Specifies the data type Bias +/// Can be u8, s8, s32, bf16, f16 or fp32 +/// +status_t DNNL_API brgemm_desc_set_postops(brgemm_t *brg, + const primitive_attr_t *attr, const memory_desc_t *dst_md, int LDD, + impl::data_type_t dt_bias = impl::data_type::undef); + +/// Adds BRGEMM attributes to BRGEMM descriptor +/// +/// @param brg Output BRGEMM descriptor +/// @param brgattr Specifies kernel attributes and hints: virtual padding, +/// maximum batch size, kernel loop order etc. +/// +status_t DNNL_API brgemm_desc_set_attr( + brgemm_t *brg, const brgemm_attr_t &brgattr); + +/// Generates a BRGEMM kernel based on descriptor +/// +/// @param brg_kernel Output BRGEMM kernel +/// @param brg BRGEMM descriptor +/// +status_t DNNL_API brgemm_kernel_create( + brgemm_kernel_t **brg_kernel, const brgemm_t &brg); + +/// Destroys a BRGEMM kernel +/// +/// @param brg_kernel BRGEMM kernel +/// +status_t DNNL_API brgemm_kernel_destroy(brgemm_kernel_t *brg_kernel); + +/// Execute BRGEMM kernel (brgemm_addr version) +/// +/// @note +/// Only BRGEMM kernel will be executed even if post-ops are added to BRGEMM +/// descriptor +/// +/// @note +/// In row major mode matrix B (matrix A for column major) is expected to be +/// in a VNNI-friendly format, which requires 4 consecutive elements of K +/// dimension for int8 data type, 2 elements for bfloat16 data type and no +/// requirements for f32 and f16 data types. +/// +/// @param brg_kernel BRGEMM kernel +/// @param bs Specifies the size of batch +/// @param batch Array of batch elements containing pointers to matrices +/// A,B and virtual padding for matrices A +/// @param ptr_C Pointer to destination matrix C +/// @param scratch Scratchpad memory needed in several scenarios: +/// * Where: AMX+ hardware; When: always; For: buffer for tiles store. +/// * In rest scenarios is not used. +/// +void DNNL_API brgemm_kernel_execute(const brgemm_kernel_t *brg_kernel, int bs, + const brgemm_batch_element_t *batch, void *ptr_C, + void *scratch = nullptr); + +/// Execute BRGEMM kernel (brgemm_offs and brgemm_strd version) +/// +/// @note +/// Only BRGEMM kernel will be executed even if post-ops are added to BRGEMM +/// descriptor +/// +/// @note +/// See the second note for `brgemm_kernel_execute` API. +/// +/// @param brg_kernel BRGEMM kernel +/// @param bs Specifies the size of batch +/// @param addr_A Pointer to first matrix A in the batch +/// @param addr_B Pointer to first matrix B in the batch +/// @param batch Array of batch elements containing offsets to matrices A,B +/// and virtual padding for matrix A. This parameter is ignored when +/// using fixed offsets. +/// @param ptr_C Pointer to destination matrix C +/// @param scratch Scratchpad memory needed in several scenarios: +/// * Where: AMX+ hardware; When: always; For: buffer for tiles store. +/// * In rest scenarios is not used. +/// +void brgemm_kernel_execute(const brgemm_kernel_t *brg_kernel, int bs, + const void *addr_A, const void *addr_B, + const brgemm_batch_element_t *batch, void *ptr_C, + void *scratch = nullptr); + +/// Execute BRGEMM kernel (brgemm_addr version) +/// +/// @note +/// BRGEMM kernel and post-operations will be executed +/// +/// @note +/// See the second note for `brgemm_kernel_execute` API. +/// +/// @param brg_kernel BRGEMM kernel +/// @param bs Specifies the size of batch +/// @param batch Array of batch elements containing pointers to matrices A,B +/// and virtual padding for matrices A +/// @param ptr_C Pointer to matrix C +/// @param ptr_D Pointer to destination matrix D +/// @param post_ops_data Specifies tensors and data used in post processing +/// phase +/// @param scratch Scratchpad memory needed in several scenarios: +/// * Where: AMX+ hardware; When: always; For: buffer for tiles store. +/// * Where: pre-VNNI hardware; When: s8s8 kernel; For: compensation buffer. +/// * In rest scenarios is not used. +/// +void DNNL_API brgemm_kernel_execute_postops(const brgemm_kernel_t *brg_kernel, + int bs, const brgemm_batch_element_t *batch, void *ptr_C, void *ptr_D, + const brgemm_post_ops_data_t &post_ops_data, void *scratch = nullptr); + +/// Execute BRGEMM kernel (brgemm_offs and brgemm_strd version) +/// +/// @note +/// BRGEMM kernel and post-operations will be executed +/// +/// @note +/// See the second note for `brgemm_kernel_execute` API. +/// +/// @param brg_kernel BRGEMM kernel +/// @param bs Specifies the size of batch +/// @param addr_A Pointer to first matrix A in the batch +/// @param addr_B Pointer to first matrix B in the batch +/// @param batch Array of batch elements containing offsets to matrices A,B +/// and virtual padding for matrices A. This parameter is ignored when +/// using fixed offsets. +/// @param ptr_C Pointer to destination matrix C +/// @param ptr_D Pointer to destination matrix D +/// @param post_ops_data Specifies tensors and data used in post processing +/// phase +/// @param scratch Scratchpad memory needed in several scenarios: +/// * Where: AMX+ hardware; When: always; For: buffer for tiles store. +/// * Where: pre-VNNI hardware; When: s8s8 kernel; For: compensation buffer. +/// * In rest scenarios is not used. +/// +void brgemm_kernel_execute_postops(const brgemm_kernel_t *brg_kernel, int bs, + const void *addr_A, const void *addr_B, + const brgemm_batch_element_t *batch, void *ptr_C, void *ptr_D, + const brgemm_post_ops_data_t &post_ops_data, void *scratch = nullptr); + +/// AMX utilities: Creates a palette based on BRGEMM descriptor +/// +/// @note +/// This call expects brgemm_t object completely set up, thus, used after +/// `brgemm_desc_set_attr` call for non-empty attributes. +/// +/// @note +/// Caller is expected to subsequently configure AMX tiles by calling +/// amx_tile_configure(palette). +/// +/// @param brg BRGEMM descriptor +/// @param palette 64 bytes array contains tiles configuration +/// +status_t DNNL_API brgemm_init_tiles(const brgemm_t &brg, char palette[64]); + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +//vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/brgemm/brgemm_containers.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/brgemm/brgemm_containers.hpp new file mode 100644 index 0000000000000000000000000000000000000000..209e69ae3b2aabeac28908cd33e200564fe17f57 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/brgemm/brgemm_containers.hpp @@ -0,0 +1,131 @@ +/******************************************************************************* +* Copyright 2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_BRGEMM_BRGEMM_CONTAINERS_HPP +#define CPU_X64_BRGEMM_BRGEMM_CONTAINERS_HPP + +#include +#include "common/rw_mutex.hpp" +#include "cpu/x64/amx_tile_configure.hpp" +#include "cpu/x64/brgemm/brgemm.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +namespace brgemm_containers { + +// These containers are intended to be used as local objects in brgemm +// primitives to ensure that references are unique and correct. + +struct brgemm_desc_container_t { +public: + brgemm_desc_container_t() {} + brgemm_desc_container_t(size_t ns) { resize(ns); } + void resize(size_t ns) { refs_.resize(ns); } + inline const brgemm_t *operator[](int idx) const { return refs_[idx]; } + + bool insert(int idx, brgemm_t &brg) { + std::vector dummy_bd_mask; + std::vector dummy_static_offsets; + return insert(idx, brg, dummy_bd_mask, dummy_static_offsets); + } + + bool insert(int idx, brgemm_t &brg, const std::vector &bd_mask, + const std::vector &static_offsets); + +private: + std::vector refs_; + + std::set set_; + std::vector> bd_mask_list_; + std::vector> static_offsets_list_; +}; + +#define BRGEMM_KERNEL_GLOBAL_STORAGE + +struct brgemm_kernel_container_t { + brgemm_kernel_container_t() {} + brgemm_kernel_container_t(size_t ns) { resize(ns); } + void resize(size_t ns) { refs_.resize(ns); } + inline const brgemm_kernel_t *operator[](int idx) const { + return refs_[idx]; + } + + status_t insert(int idx, const brgemm_t *brg); + static bool brgemm_kernel_cmp(const std::shared_ptr &lhs, + const std::shared_ptr &rhs); + +private: + std::vector refs_; +#ifdef BRGEMM_KERNEL_GLOBAL_STORAGE + static std::set, + decltype(brgemm_kernel_container_t::brgemm_kernel_cmp) *> + set_; + + static utils::rw_mutex_t &rw_mutex() { + static utils::rw_mutex_t mutex; + return mutex; + } + + void lock_write() { rw_mutex().lock_write(); } + void unlock_write() { rw_mutex().unlock_write(); } + +#else + std::set, + decltype(brgemm_kernel_container_t::brgemm_kernel_cmp) *> + set_; + void lock_write() {} + void unlock_write() {} +#endif + std::map brgemm_map_; +}; + +struct brgemm_palette_container_t { + typedef std::array S_t; + + brgemm_palette_container_t() {} + brgemm_palette_container_t(size_t ns) { resize(ns); } + void resize(size_t ns) { refs_.resize(ns); } + + inline const char *operator[](int idx) const { return refs_[idx]->data(); } + + bool insert(int idx, const brgemm_t *brg); + bool insert(int idx, const brgemm_t &brg) { return insert(idx, &brg); } + + inline void maybe_tile_configure(bool is_amx, int &idx, int new_idx) const { + if (idx == new_idx) return; + if (is_amx && (idx < 0 || refs_[idx] != refs_[new_idx])) + amx_tile_configure(refs_[new_idx]->data()); + idx = new_idx; + } + +private: + std::vector refs_; + std::set set_; +}; + +} // namespace brgemm_containers + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif // CPU_X64_BRGEMM_BRGEMM_CONTAINERS_HPP + +//vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/brgemm/brgemm_types.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/brgemm/brgemm_types.hpp new file mode 100644 index 0000000000000000000000000000000000000000..b9ee70b6608f6e672b19580b13e9098fb2ed5196 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/brgemm/brgemm_types.hpp @@ -0,0 +1,544 @@ +/******************************************************************************* +* Copyright 2020-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_BRGEMM_BRGEMM_TYPES_HPP +#define CPU_X64_BRGEMM_BRGEMM_TYPES_HPP + +#include "common/primitive_attr.hpp" +#include "cpu/platform.hpp" +#include "cpu/x64/cpu_isa_traits.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +// The type defines organization of batch of matrices +typedef enum { + // A and B arrays of pointers + brgemm_addr = 1, + // Base address and array of offsets from base address. + brgemm_offs = 2, + // Base address and fixed stride between matrices. + brgemm_strd = 3, + // Base address and static array of fixed offsets. + brgemm_static_offs = 4, +} brgemm_batch_kind_t; + +// The type defines the storage format of matrix +typedef enum { + brgemm_layout_undef = 0, + brgemm_col_major = 1, + brgemm_row_major = 2, +} brgemm_layout_t; + +typedef enum { + none = 0, + per_tensor = 1, + per_m = 2, + per_n = 3, + per_k = 4, +} brgemm_broadcast_t; + +struct brgemm_strides_t { + // Stride between A matrices + dim_t stride_a; + // Stride between B matrices + dim_t stride_b; +}; + +typedef enum { + brgemm_lo_default = 0, + brgemm_lo_bl_1load, + brgemm_lo_bl_1bcst, +} brgemm_kernel_loop_order_t; + +typedef enum { + brgemm_prf_default = 1, + brgemm_prf1, + brgemm_prf2, +} brgemm_kernel_prefetching_t; + +typedef enum { + brgemm_innermost_undef = 0, + brgemm_bd_loop_innermost, + brgemm_ld_loop_innermost, +} brgemm_kernel_innermost_loop_t; + +typedef enum { + brgemm_hint_nt_undef = 0, + brgemm_hint_nt_false, + brgemm_hint_nt_true, +} brgemm_kernel_hint_nt_t; + +struct brgemm_prf_t { + int dist1 = -1; + int dist2 = -1; +}; + +struct brgemm_batch_element_t { + brgemm_batch_element_t() { + ptr.A = ptr.B = nullptr; + vvpad.top = vvpad.bottom = 0; + } + union { + struct { + const void *A; + const void *B; + } ptr; + struct { + dim_t A; + dim_t B; + } offset; + }; + union { + struct { + dim_t top; + dim_t bottom; + } vvpad; + struct { + dim_t left; + dim_t right; + } hvpad; + }; +}; + +struct DNNL_API brgemm_attr_t { + brgemm_attr_t(); + // if unrolled kernel is used (use_uker == true) + // then "max_bs" is the the only batch size that can be used on kernel call + // else "max_bs" is the maximum batch size that can be used + int max_bs; + int max_top_vpad, max_bottom_vpad; + dim_t hint_expected_A_size, hint_expected_B_size, hint_expected_C_size; + brgemm_kernel_innermost_loop_t hint_innermost_loop + = brgemm_ld_loop_innermost; + brgemm_kernel_loop_order_t hint_loop_order; + brgemm_kernel_prefetching_t hint_prefetching + = brgemm_kernel_prefetching_t::brgemm_prf_default; + brgemm_prf_t hint_prfA, hint_prfB, hint_prfC; + + bool wary_tail_read; + bool generate_skip_accumulation; + // Value of bd_mask_level specifies how bd_mask is used in brgemm kernel + // 0 – bd_mask is not used + // 1 – bd_mask is used on storing stage only + // 2 – bd_mask used both on reading and storing stages + int bd_mask_level; + // use_uker is a boolean value that determines whether to use the unrolled + // kernel or not + bool use_uker; + // use_interleave_stores is a value that determines whether to use the + // interleave stores or not + bool use_interleave_stores; + impl::fpmath_mode_t fpmath_mode = fpmath_mode::strict; + // Second level leading dimension describing distance between 16-line + // blocks in case of blocked layout. Used to calculate address of next + // bd block. By default are equal to regular leading dimension parameters + // specified on brgemm creation. + // Supported by brgemm unrolled kernel for now. + int LDA2 {0}, LDB2 {0}, LDC2_M {0}, LDC2_N {0}; + // If "true" then batchsize is allowed to change on each kernel call + // and there is no unrolling by batchsize in kernel + bool var_bs {false}; + bool postops_only {false}; + + int hint_bd_block {0}; + int hint_ld_block {0}; + int hint_bd_block2 {0}; + int hint_ld_block2 {0}; + bool hint_ununroll_bd_loop {false}; + + brgemm_kernel_hint_nt_t hint_load_nt_A {brgemm_hint_nt_undef}; + brgemm_kernel_hint_nt_t hint_load_nt_B {brgemm_hint_nt_undef}; + // this variable is used in tile decomposition heuristics + // to calculate "effective" K value which may be different from just + // K * batch_size for non-1x1 convolutions due to data overlap + float K_koef = 1.f; + // this flag may be used to omit some actions on calling from blocking + // in convolutions init_conf + bool test_call = false; + // bd_mask is char array in which each element is a boolean value that + // determines whether to write this row to the result matrix or skip + const char *bd_mask; + // static_offsets is a static array of fixed offsets used for + // brgemm_static_offs batch kind + const brgemm_batch_element_t *static_offsets; +}; + +struct brgemm_t { + // Note: new added parameters must be taken into account in the brgemm + // comparison function + int bcast_dim = 0; // M; + int load_dim = 0; // N; + int reduce_dim = 0; // K; + int LDA = 0; + int LDB = 0; + int LDC = 0; + int LDD = 0; + // we use two isa_ variables + // isa_user to store the user provided isa value + // isa_impl to store actual implementation. This can change until the kernel + // is created, as calls to set_attr can affect this variable. Ex: bf32 + impl::cpu::x64::cpu_isa_t isa_user = isa_undef; + impl::cpu::x64::cpu_isa_t isa_impl = isa_undef; + float alpha = 0.0f; + float beta = 0.0f; + + impl::data_type_t dt_a = data_type::undef; + impl::data_type_t dt_c = data_type::undef; + impl::data_type_t dt_b = data_type::undef; + impl::data_type_t dt_d = data_type::undef; + impl::data_type_t dt_bias = data_type::undef; + + dim_t stride_a = 0; // Offset in bytes + dim_t stride_b = 0; + + brgemm_layout_t layout = brgemm_layout_undef; + brgemm_batch_kind_t type; + bool is_dgmm = false; // set to true in brdgmm_desc_init + bool with_sum = false; + bool req_cal_comp_pads = false; + + float sum_scale = 0.0f; + int32_t sum_zp = 0; + impl::data_type_t sum_dt; + bool with_eltwise = false; + bool with_binary = false; + bool with_scales = false; + + brgemm_broadcast_t zp_type_a = brgemm_broadcast_t::none; + brgemm_broadcast_t zp_type_b = brgemm_broadcast_t::none; + brgemm_broadcast_t zp_type_c = brgemm_broadcast_t::none; + + int is_oc_scale = 0; + bool with_dst_scales = false; + + brgemm_attr_t brgattr; + + // Derived parameters + int LDA2 {0}, LDB2 {0}, LDC2_M {0}, LDC2_N {0}; + bool is_blocked = false; + + int bdb = 0, bd_block = 0, bdb_tail = 0; + int bdb2 = 0, bd_block2 = 0, bdb2_tail = 0; + int ldb = 0, ld_block = 0, ldb_tail = 0; + int ldb2 = 0, ld_block2 = 0, ldb2_tail = 0; + int rdb = 0, rd_block = 0, rdb_tail = 0; + int rd_step = 0, ld_step = 0; + + int typesize_A = 0; + int typesize_B = 0; + int typesize_C = 0; + int typesize_D = 0; + int typesize_bias = 0; + + bool is_ymm = false; + bool is_zmm = false; + bool is_tmm = false; + bool is_int8 = false, is_int8_tmm = false; + bool is_bf16 = false, is_bf16_tmm = false, is_bf16_emu = false; + bool is_f16 = false, is_f16_tmm = false; + bool is_f32 = false; + bool is_bf32 = false; + + bool has_int8_vnni = false; + + bool load_nt_A = false; + bool load_nt_B = false; + + bool embd_bcst = false; + bool with_bias = false; + bool req_s8s8_compensation = false; + bool with_weights_scale_adjust = false; + brgemm_kernel_innermost_loop_t innermost_loop = brgemm_ld_loop_innermost; + int is_M_tail; + bool interleave_tilestores_ = false; + brgemm_prf_t prfA, prfB, prfC; + + static constexpr int MAX_VPAD = 100; + static constexpr int AMX_TILES_NUM = 8; + + const primitive_attr_t *attr = nullptr; + const memory_desc_t *dst_md = nullptr; + + bool is_row_major() const { + assert(layout != brgemm_layout_undef); + return layout == brgemm_row_major; + } + + // Tile register decomposition + int get_bd_block2() const noexcept { + auto res = (bdb <= bd_block2) ? bdb : (bd_block2 + (bdb_tail ? 1 : 0)); + return res; + } + + int get_ld_block2() const noexcept { + auto res = (ldb <= ld_block2) ? ldb : (ld_block2 + (ldb_tail ? 1 : 0)); + return res; + } + + int get_num_C_tiles() const noexcept { + return get_bd_block2() * get_ld_block2(); + } + int get_C_tensor(int m, int n, bool m_tail = false, + bool n_tail = false) const noexcept { + auto M = m_tail ? get_bd_block2() - 1 : m; + auto N = n_tail ? get_ld_block2() - 1 : n; + return (M * get_ld_block2() + N); + } + + int get_num_A_tiles() const noexcept { + const auto req_tiles = (bdb_tail && bdb > 1) ? 2 : 1; + const auto max_tiles = AMX_TILES_NUM - get_num_C_tiles() - 1; + const auto n_tiles = nstl::min(get_bd_block2(), max_tiles); + assert(n_tiles >= req_tiles); + return nstl::max(req_tiles, n_tiles); + } + + int get_A_tensor(int m, bool m_tail = false) const noexcept { + const auto full_A_tiles = get_num_A_tiles() - (bdb_tail ? 1 : 0); + auto M = m_tail ? get_num_A_tiles() - 1 : m % full_A_tiles; + return (get_num_C_tiles() + M); + } + + int get_num_B_tiles() const noexcept { + const auto req_tiles = (ldb_tail && ldb > 1) ? 2 : 1; + const auto max_tiles + = AMX_TILES_NUM - get_num_C_tiles() - get_num_A_tiles(); + const auto n_tiles = nstl::min(get_ld_block2(), max_tiles); + assert(n_tiles >= req_tiles); + return nstl::max(req_tiles, n_tiles); + } + + int get_B_tensor(int n, bool n_tail = false) const noexcept { + const auto full_B_tiles = get_num_B_tiles() - (ldb_tail ? 1 : 0); + auto N = n_tail ? get_num_B_tiles() - 1 : n % full_B_tiles; + return (get_num_C_tiles() + get_num_A_tiles() + N); + } + + int get_wsp_buffer_size() const noexcept { + int sz = 0; + if (is_tmm) { + constexpr int tilesize = 1024; + sz = get_num_C_tiles() * tilesize; // postops buffer + if (is_bf32) { + const int n_bdb = bd_block2; + const int n_rdb = rdb + (rdb_tail != 0); + const int n_ldb = ldb + (ldb_tail != 0); + const int downcvt_tiles + = brgattr.max_bs * n_rdb * (n_bdb + n_ldb); + sz += downcvt_tiles * tilesize; + } + } + return sz; + } + + bool is_b_data_layout_vnni() { + // True in general, only exception is f16 with avx512_core_fp16. + // We also return `true` for bf32 (brgattr.fpmath_mode_ = bf16), + // because the data transformation to vnni layout is internal + // and transparent to user. + return !(dt_b == data_type::f16 && isa_impl == avx512_core_fp16); + } + bool is_xf16() const noexcept { return is_bf16 || is_f16; } + + bool operator==(const brgemm_t &rhs) const; + bool operator<(const brgemm_t &rhs) const; +}; + +struct brgemm_kernel_params_t { + const void *ptr_A; + const void *ptr_B; + const brgemm_batch_element_t *batch; + void *ptr_C; + + const void *ptr_bias; + void *ptr_D; + + /* kernel takes single pointer scales, but configuration relies on a + * combination of arg scales. This helps to reuse attributes from + * primitives, but requires them to pre-compute + * scales = src_scale * wei_scale[:] + */ + const void *ptr_scales; + void *ptr_buf; + + size_t do_post_ops; + size_t do_apply_comp; + size_t BS; + + /* + * ptr to table of void * elements that are pointers to post_op binary + * src1 tensors + */ + const void *post_ops_binary_rhs_arg_vec; + size_t oc_logical_off; + size_t first_mb_matrix_addr_off; + size_t dst_row_logical_off; + + const char *data_C_ptr_; + + const void *a_zp_compensations = nullptr; + const void *b_zp_compensations = nullptr; + const void *c_zp_values = nullptr; + size_t skip_accm = 0; + int32_t zp_a_val = 1; + const void *ptr_dst_scales = nullptr; +}; + +template +struct jit_brgemm_kernel_t; +struct jit_brgemm_amx_uker_base_t; +template +struct jit_brdgmm_kernel_base_t; +class jit_generator; + +struct brgemm_kernel_t { + brgemm_kernel_t() {}; + virtual ~brgemm_kernel_t() {}; + virtual status_t create_kernel() = 0; + virtual void operator()(brgemm_kernel_params_t *) const = 0; + virtual const jit_generator *get_jit_generator() const = 0; +}; + +template +struct brgemm_kernel_common_t : public brgemm_kernel_t { + brgemm_kernel_common_t(const brgemm_t abrd); + ~brgemm_kernel_common_t(); + + status_t create_kernel(); + void operator()(brgemm_kernel_params_t *) const; + virtual const jit_generator *get_jit_generator() const; + +private: + jit_brgemm_kernel_t *brgemm_kernel_ = nullptr; + + DNNL_DISALLOW_COPY_AND_ASSIGN(brgemm_kernel_common_t); +}; + +struct brgemm_amx_uker_t : public brgemm_kernel_t { + brgemm_amx_uker_t(const brgemm_t abrd); + ~brgemm_amx_uker_t(); + + status_t create_kernel(); + void operator()(brgemm_kernel_params_t *) const; + virtual const jit_generator *get_jit_generator() const; + +private: + jit_brgemm_amx_uker_base_t *brgemm_kernel_ = nullptr; + + DNNL_DISALLOW_COPY_AND_ASSIGN(brgemm_amx_uker_t); +}; + +template +struct brdgmm_kernel_t : public brgemm_kernel_t { + brdgmm_kernel_t(const brgemm_t abrd); + ~brdgmm_kernel_t(); + + status_t create_kernel(); + void operator()(brgemm_kernel_params_t *) const; + virtual const jit_generator *get_jit_generator() const; + +private: + jit_brdgmm_kernel_base_t *brgemm_kernel_ = nullptr; + + DNNL_DISALLOW_COPY_AND_ASSIGN(brdgmm_kernel_t); +}; + +/// @param bias Vector of bias (vector length is N) +/// @param scales - Vector of scale factor values which represents combination +/// scale factors for matrixes A and B. If brgemm_t::is_oc_scale = true +/// vector length is N otherwise it must be broadcasted to vector of simd +/// width length +/// @param binary_post_ops_rhs - Ptr to table of pointers to tensors used as rhs +/// in binary post-operation { void* binary_op_tensor1, ..., +/// void* binary_op_tensor_n} +/// @param oc_logical_off - Used in binary postops in per_oc bcast strategy. +/// Offset to start oc processed by given thread in elements. +/// @param dst_row_logical_off - Used in binary postops in per_oc bcast +/// strategy. Offset to start oc processed by given thread in elements. +/// @param a_zp_compensations - Pre-computed compensations for A matrix zero +/// point values. +/// @param b_zp_compensations - Pre-computed compensations for B matrix zero +/// point values. +/// @param c_zp_values - C matrix zero point values. +/// @param skip_accumulation - specifies whether to skip accumulation when +/// computing post-ops. `Beta` value from descriptor affects final +/// accumulator values taken. +/// @param do_only_comp - specifies whether to perform accumulation only and skip +/// post-ops. +/// @param do_only_zp_a_val - specifies to apply pre-calculated compensation for +/// A zero point only and skip the rest post-ops. +/// @param zp_a_val - zero point value for A, required to adjust compensation +/// values if do_only_zp_a_val = true. +/// @param dst_scales - Vector of inverted scale factor values for matix C, +/// common scale vector type only is supported, it must be broadcasted to +/// vector of simd width length. +/// +struct brgemm_post_ops_data_t { + brgemm_post_ops_data_t() = default; + brgemm_post_ops_data_t(const void *bias, const float *scales, + const void *binary_post_ops_rhs, size_t oc_logical_off, + const size_t dst_row_logical_off = 0, + const char *data_C_ptr_ = nullptr, + const size_t first_mb_matrix_addr_off = 0, + const void *a_zp_compensations = nullptr, + const void *b_zp_compensations = nullptr, + const void *c_zp_values = nullptr, bool skip_accumulation = false, + int32_t zp_a_val = 1, bool do_only_comp = false, + bool do_only_zp_a_val = false, const float *dst_scales = nullptr) + : bias(bias) + , scales(scales) + , binary_post_ops_rhs(binary_post_ops_rhs) + , oc_logical_off(oc_logical_off) + , dst_row_logical_off(dst_row_logical_off) + , data_C_ptr_(data_C_ptr_) + , first_mb_matrix_addr_off(first_mb_matrix_addr_off) + , a_zp_compensations(a_zp_compensations) + , b_zp_compensations(b_zp_compensations) + , c_zp_values(c_zp_values) + , skip_accumulation(skip_accumulation) + , zp_a_val {zp_a_val} + , do_only_comp {do_only_comp} + , do_only_zp_a_val {do_only_zp_a_val} + , dst_scales(dst_scales) {} + + const void *bias = nullptr; + const float *scales = nullptr; + const void *binary_post_ops_rhs = nullptr; + size_t oc_logical_off = 0; + size_t dst_row_logical_off = 0; + const char *data_C_ptr_ = nullptr; + size_t first_mb_matrix_addr_off = 0; + const void *a_zp_compensations = nullptr; + const void *b_zp_compensations = nullptr; + const void *c_zp_values = nullptr; + const bool skip_accumulation = false; + int32_t zp_a_val = 1; + const bool do_only_comp = false; + const bool do_only_zp_a_val = false; + const float *dst_scales = nullptr; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +//vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/brgemm/brgemm_utils.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/brgemm/brgemm_utils.hpp new file mode 100644 index 0000000000000000000000000000000000000000..2c98bc40392eaa36b19c9090528efaaec2a7d22e --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/brgemm/brgemm_utils.hpp @@ -0,0 +1,71 @@ +/******************************************************************************* +* Copyright 2022 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_BRGEMM_BRGEMM_UTILS_HPP +#define CPU_X64_BRGEMM_BRGEMM_UTILS_HPP + +#include "cpu/x64/brgemm/brgemm.hpp" + +#include "cpu/x64/cpu_isa_traits.hpp" + +#include "common/c_types_map.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +namespace brgemm_utils { + +bool can_dispatch_uker(const brgemm_t *brg); + +void maybe_try_bf32(brgemm_t *brg); + +status_t brgemm_blocking(brgemm_t *brg); + +status_t brdgmm_blocking(brgemm_t *brg); + +/* The purpose of this function is to enable initialization of brgemm values + * and then call additional functions like blocking heuristics without + * having to depend on BRGeMM's API. An additional feature is that this + * function can be modified depending on needs without requiring changes + * at the API level. */ +void init_brgemm_conf(brgemm_t *brg, cpu_isa_t isa, brgemm_batch_kind_t type, + impl::data_type_t dt_a, impl::data_type_t dt_b, brgemm_layout_t layout, + float alpha, float beta, dim_t LDA, dim_t LDB, dim_t LDC, dim_t M, + dim_t N, dim_t K, const brgemm_strides_t *strides = nullptr, + bool is_bf32 = false); + +/* The purpose of this function is to enable initialization of brgemm values + * and then call additional functions like blocking heuristics without + * having to depend on BRDGeMM's API. An additional feature is that this + * function can be modified depending on needs without requiring changes + * at the API level. */ +void init_brdgmm_conf(brgemm_t *brg, cpu_isa_t isa, brgemm_batch_kind_t type, + impl::data_type_t dt_a, impl::data_type_t dt_b, brgemm_layout_t layout, + float alpha, float beta, dim_t LDA, dim_t LDC, dim_t M, dim_t N, + const brgemm_strides_t *strides = nullptr); + +} // namespace brgemm_utils + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif // CPU_X64_BRGEMM_BRGEMM_UTILS_HPP + +//vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/brgemm/jit_brdgmm_kernel.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/brgemm/jit_brdgmm_kernel.hpp new file mode 100644 index 0000000000000000000000000000000000000000..8c1f192337f4dc9a286190e72c54071a0d5d1a17 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/brgemm/jit_brdgmm_kernel.hpp @@ -0,0 +1,234 @@ +/******************************************************************************* +* Copyright 2021-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_BRDGMM_KERNEL_HPP +#define CPU_X64_JIT_BRDGMM_KERNEL_HPP + +#include "common/c_types_map.hpp" +#include "common/nstl.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/x64/brgemm/brgemm_types.hpp" +#include "cpu/x64/cpu_barrier.hpp" +#include "cpu/x64/injectors/jit_uni_postops_injector.hpp" +#include "cpu/x64/jit_avx512_core_bf16cvt.hpp" +#include "cpu/x64/jit_generator.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +template +struct jit_brdgmm_kernel_base_t : public jit_generator { + jit_brdgmm_kernel_base_t(const brgemm_t &abrd); + + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_brdgmm_kernel_base_t) + + brgemm_t brg; + + static bool is_fast_vnni_int8(const brgemm_t &brg) { + return brg.is_dgmm && brg.is_int8 && brg.isa_impl == avx512_core_vnni + && brg.ldb_tail /*n_vlen_tail*/ == 0; + } + +private: + // note: this kernel doesn't yet support TMM's. We differentiate Wmm and Vmm + // just to follow same template style as brgemm_kernel. + using Vmm = + typename utils::conditional::value, + Xbyak::Zmm, Wmm>::type; + using Vmm_low_t = typename vreg_traits::Vmm_lower_t; + static constexpr cpu_isa_t po_isa_t = utils::map(isa, avx512_core, avx2, + avx2, avx2_vnni_2, avx2_vnni_2, avx512_core_fp16, avx512_core_fp16); + using po_injector_t = injector::jit_uni_postops_injector_t; + std::unique_ptr postops_injector_; + std::unique_ptr bf16_emu_; + + Xbyak::Label permute_index_table; + + using reg64_t = const Xbyak::Reg64; + // Register decomposition + const reg64_t param1 = abi_param1; + const reg64_t reg_A = abi_not_param1; + const reg64_t reg_B = r8; + const reg64_t reg_aux_batch_addr = r15; + const reg64_t reg_BS = rsi; + + // loop variables + const reg64_t reg_BS_loop = r12; + const reg64_t reg_aux_M = r13; + const reg64_t reg_aux_D = rbx; + const reg64_t reg_aux_C = rdx; + const reg64_t reg_aux_A = r10; + const reg64_t reg_aux_B = abi_param1; + const reg64_t reg_aux1_A = reg_A; // brgemm_strd + const reg64_t reg_aux1_B = reg_B; // brgemm_strd + const reg64_t reg_a_offset = r9; + const reg64_t reg_aux_N = r11; + + const reg64_t reg_aux_A_vpad_top = r14; + const reg64_t reg_aux_A_vpad_bottom = rbp; + + const reg64_t reg_table_base = rax; + const reg64_t reg_tmp = reg_table_base; + const reg64_t reg_total_padding = reg_table_base; + const reg64_t reg_aux_bias = reg_table_base; + const reg64_t reg_aux_scales = reg_table_base; + const reg64_t reg_aux_dst_scales = reg_table_base; + const reg64_t reg_binary_params = abi_param1; // default for binary ops + const reg64_t reg_ptr_sum_scale = reg_aux_A_vpad_top; + const reg64_t reg_ptr_sum_zp = reg_aux_A_vpad_bottom; + + Xbyak::Opmask k_mask = Xbyak::Opmask(2); + Xbyak::Opmask k_tail_mask = Xbyak::Opmask(3); + Xbyak::Opmask kblend_mask = Xbyak::Opmask(4); + + /* used for bfloat16 */ + reg64_t bf16_emu_scratch = reg_table_base; + Xbyak::Zmm bf16_emu_reserv_1 = Xbyak::Zmm(0); + Xbyak::Zmm bf16_emu_reserv_2 = Xbyak::Zmm(1); + Xbyak::Zmm bf16_emu_reserv_3 = Xbyak::Zmm(2); + Xbyak::Zmm bf16_emu_reserv_4 = Xbyak::Zmm(3); + // note 1: zmm reserv_5 is not necessary since it's only used for + // 'vdpbf16ps' + // note 2: zmm0 collides with vmm_permute, hence need to write this value + // before every loop. + + const int simd_w_; + const int max_vmms_; + constexpr static int reg_batch0_addr_offs_ = 0; + constexpr static int reg_bias_offs_ = 8; + constexpr static int reg_scales_offs_ = 16; + constexpr static int reg_A_offs_ = 24; // brgemm_strd + constexpr static int reg_B_offs_ = 32; // brgemm_strd + constexpr static int abi_param1_offs_ = 40; + constexpr static int reg_dst_scales_offs_ = 48; + constexpr static int stack_space_needed_ = 56; + + bool with_binary_non_scalar_bcast_ = false; + + inline int M() { return brg.bcast_dim; } + inline int N() { return brg.load_dim; } + inline int m_block1() { return brg.bd_block; } + inline int nb_m_block1() { return brg.bdb; } + inline int m_block1_tail() { return brg.bdb_tail; } + inline int m_block2() { return brg.bd_block2; } + inline int nb_m_block2() { return brg.bdb2; } + inline int m_block2_tail() { return brg.bdb2_tail; } + + inline int n_block1() { return brg.ld_block; } + inline int nb_n_block1() { return brg.ldb; } + inline int n_block1_tail() { return brg.ldb_tail; } + inline int n_block2() { return brg.ld_block2; } + inline int nb_n_block2() { return brg.ldb2; } + inline int n_block2_tail() { return brg.ldb2_tail; } + + int tail_length() { return n_block1_tail() % simd_w_; } + bool is_fma_embd() { return brg.is_f32 && is_superset(isa, avx512_core); } + bool is_fast_vnni_int8() { return is_fast_vnni_int8(brg); } + int vnni_substep() { + return brg.isa_impl == avx2_vnni_2 && brg.is_xf16() ? 2 : 1; + } + int get_substep_simd(int n_i, int v_i, bool has_n_tail) { + const int last_n_block_sz + = n_block2_tail() > 0 ? n_block2_tail() : n_block2(); + if (has_n_tail && n_i + 1 == last_n_block_sz) { + return nstl::min(simd_w_, n_block1_tail() - v_i * simd_w_); + } else { + return simd_w_; + } + } + Vmm vmm_permute() { return Vmm(0); } // used in fast_vnni_int8 + Vmm vmm_a() { return Vmm(is_fast_vnni_int8()); } + Vmm vmm_b(int bi = 0) { + return Vmm(is_fast_vnni_int8() + !is_fma_embd() + bi); + } + Vmm accm(int m_blocks, int n_blocks, int m, int n, int vnni_idx) { + assert(m_blocks <= m_block2() && m < m_blocks); + assert(n_blocks <= n_block2() && n < n_blocks); + const int accm_start = max_vmms_ - m_blocks * n_blocks * vnni_substep(); + const int accm_rel_idx + = m * n_blocks * vnni_substep() + n * vnni_substep() + vnni_idx; + const int idx = accm_start + accm_rel_idx; + assert(idx < max_vmms_ && idx > vmm_b(0).getIdx()); + return Vmm(idx); + } + Vmm vmm_tmp(int i) { + const int idx + = max_vmms_ - m_block2() * n_block2() * vnni_substep() - 1 - i; + assert(idx > (is_fast_vnni_int8() - 1)); + return Vmm(idx); + } + + template + U maybe_mask(const U umm_in, bool mask_flag, bool store); + void init_masks(); + void read_params(); + void load_accumulators(int m_blocks, int n_blocks); + void restore_A_B_matrices(); + void set_A_B_matrices(); + void advance_A_B_matrices(); + void load_a(Vmm vmma, int m_i, int n_i, int v_i, bool has_n_tail); + void load_b(Vmm vmmb, int n_i, int v_i, bool has_n_tail); + void brdgmm_microkernel(int m_blocks, int n_blocks, bool has_top_padding, + bool has_bottom_padding, bool has_tail = false); + void compute_loop(); + void batch_loop(const int m_blocks, const int n_blocks, bool has_n_tail); + void cvt2ps(data_type_t type_in, const Vmm vmm_in, const Xbyak::Operand &op, + bool mask_flag, bool store); + void apply_post_ops(int m_blocks, int n_blocks, bool has_n_tail); + void maybe_transpose_interleaved_vnni_to_plain( + int m_blocks, int n_blocks, bool has_n_tail); + void store_accumulators(int m_blocks, int n_blocks, bool has_n_tail); + void store_accumulators_without_post_ops( + int m_blocks, int n_blocks, bool has_n_tail); + void store_accumulators_apply_post_ops( + int m_blocks, int n_blocks, bool has_n_tail); + + bool has_vpad() { + return brg.brgattr.max_top_vpad > 0 || brg.brgattr.max_bottom_vpad > 0; + } + bool check_effective_padding() { return has_vpad() && M() > m_block2(); } + + int oc_logical_offset(int n) { return n * n_block1(); } + int A_offset(int m, int n) { + return brg.typesize_A * (m * brg.LDA + n * n_block1()); + } + int B_offset(int n) { return brg.typesize_B * n * n_block1(); } + int C_offset(int m, int n, int v) { + return brg.typesize_C * (m * brg.LDC + n * n_block1() + v * simd_w_); + } + int D_offset(int m, int n, int v) { + return brg.typesize_D * (m * brg.LDD + n * n_block1() + v * simd_w_); + } + int bias_offset(int n, int v) { + return brg.typesize_bias * (n * n_block1() + v * simd_w_); + } + int scales_offset(int n, int v) { + return sizeof(float) * brg.is_oc_scale * (n * n_block1() + v * simd_w_); + } + + void generate() override; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/cpu_barrier.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/cpu_barrier.hpp new file mode 100644 index 0000000000000000000000000000000000000000..c76d57911af54d285e189ca16826830e6d4d180a --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/cpu_barrier.hpp @@ -0,0 +1,86 @@ +/******************************************************************************* +* Copyright 2017-2020 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_CPU_BARRIER_HPP +#define CPU_X64_CPU_BARRIER_HPP + +#include + +#include "common/utils.hpp" +#include "cpu/x64/jit_generator.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +namespace simple_barrier { + +#ifdef _WIN32 +#define CTX_ALIGNMENT 64 +#else +#define CTX_ALIGNMENT 4096 +#endif + +STRUCT_ALIGN( + CTX_ALIGNMENT, struct ctx_t { + enum { CACHE_LINE_SIZE = 64 }; + volatile size_t ctr; + char pad1[CACHE_LINE_SIZE - 1 * sizeof(size_t)]; + volatile size_t sense; + char pad2[CACHE_LINE_SIZE - 1 * sizeof(size_t)]; + }); + +/* TODO: remove ctx_64_t once batch normalization switches to barrier-less + * implementation. + * Different alignments of context structure affect performance differently for + * convolution and batch normalization. Convolution performance becomes more + * stable with page alignment compared to cache line size alignment. + * Batch normalization (that creates C / simd_w barriers) degrades with page + * alignment due to significant overhead of ctx_init in case of mb=1. */ +STRUCT_ALIGN( + 64, struct ctx_64_t { + enum { CACHE_LINE_SIZE = 64 }; + volatile size_t ctr; + char pad1[CACHE_LINE_SIZE - 1 * sizeof(size_t)]; + volatile size_t sense; + char pad2[CACHE_LINE_SIZE - 1 * sizeof(size_t)]; + }); + +template +inline void ctx_init(ctx_t *ctx) { + *ctx = utils::zero(); +} +void barrier(ctx_t *ctx, int nthr); + +/** injects actual barrier implementation into another jitted code + * @params: + * code -- jit_generator object where the barrier is to be injected + * reg_ctx -- read-only register with pointer to the barrier context + * reg_nnthr -- read-only register with the # of synchronizing threads + */ +void generate(jit_generator &code, Xbyak::Reg64 reg_ctx, Xbyak::Reg64 reg_nthr); + +} // namespace simple_barrier + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/cpu_isa_traits.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/cpu_isa_traits.hpp new file mode 100644 index 0000000000000000000000000000000000000000..5d5e3e0690be0f66300fb0442b2d0bc2bfdb4f04 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/cpu_isa_traits.hpp @@ -0,0 +1,471 @@ +/******************************************************************************* +* Copyright 2018-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_CPU_ISA_TRAITS_HPP +#define CPU_X64_CPU_ISA_TRAITS_HPP + +#include +#include +#include + +#include "oneapi/dnnl/dnnl_types.h" + +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#define XBYAK64 +#define XBYAK_NO_OP_NAMES +/* in order to make selinux happy memory that would be marked with X-bit should + * be obtained with mmap */ +#define XBYAK_USE_MMAP_ALLOCATOR + +#define XBYAK_NO_EXCEPTION +#ifndef NDEBUG +#undef XBYAK_NO_EXCEPTION +#endif + +#if defined(_MSC_VER) && !defined(__INTEL_COMPILER) +/* turn off `size_t to other-type implicit casting` warning + * currently we have a lot of jit-generated instructions that + * take uint32_t, but we pass size_t (e.g. due to using sizeof). + * FIXME: replace size_t parameters with the appropriate ones */ +#pragma warning(disable : 4267) +#endif +#include "common/compiler_workarounds.hpp" +#include "cpu/x64/xbyak/xbyak.h" +#include "cpu/x64/xbyak/xbyak_util.h" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +// Maximum number of features + hints that can be specified via bits +static constexpr int cpu_isa_total_bits = sizeof(unsigned) * 8; + +enum cpu_isa_bit_t : unsigned { + // Fill in features from least significant bit to most significant bit + sse41_bit = 1u << 0, + avx_bit = 1u << 1, + avx2_bit = 1u << 2, + avx_vnni_bit = 1u << 3, + avx_vnni_2_bit = 1u << 4, + avx512_core_bit = 1u << 5, + avx512_core_vnni_bit = 1u << 6, + avx512_core_bf16_bit = 1u << 7, + avx512_core_fp16_bit = 1u << 8, + amx_tile_bit = 1u << 9, + amx_int8_bit = 1u << 10, + amx_bf16_bit = 1u << 11, + amx_fp16_bit = 1u << 12, + // Fill in hints from most significant bit to least significant bit + prefer_ymm_bit = 1u << (cpu_isa_total_bits - 1), +}; + +dnnl_cpu_isa_hints_t DNNL_API get_cpu_isa_hints(bool soft = false); +status_t set_cpu_isa_hints(dnnl_cpu_isa_hints_t isa_hints); + +namespace cpu_isa_hints_utils { +/* hints_1 | hints_2 | ... | hints_n where hints_i are hint specific + bits declared inside the cpu_isa_bit_t */ +static constexpr unsigned hints_mask = prefer_ymm_bit; + +static unsigned cvt2mask(dnnl_cpu_isa_hints_t hints) { + static const std::unordered_map> + hints_map = {{dnnl_cpu_isa_no_hints, 0}, + {dnnl_cpu_isa_prefer_ymm, prefer_ymm_bit}}; + + auto iter = hints_map.find(hints); + if (iter != hints_map.end()) + return iter->second; + else { + assert(!"unexpected CPU ISA hint"); + return 0; + } +} + +static bool is_hints_bit_set(cpu_isa_bit_t hint_bit, bool soft) { + const dnnl_cpu_isa_hints_t hints = get_cpu_isa_hints(soft); + const unsigned cur_hints_mask = cpu_isa_hints_utils::cvt2mask(hints); + return (cur_hints_mask & hint_bit) == hint_bit; +} +} // namespace cpu_isa_hints_utils + +enum cpu_isa_t : unsigned { + isa_undef = 0u, + sse41 = sse41_bit, + avx = avx_bit | sse41, + avx2 = avx2_bit | avx, + avx2_vnni = avx_vnni_bit | avx2, + avx2_vnni_2 = avx2_vnni | avx_vnni_2_bit, + avx512_core = avx512_core_bit | avx2, + avx512_core_vnni = avx512_core_vnni_bit | avx512_core, + avx512_core_bf16 = avx512_core_bf16_bit | avx512_core_vnni, + avx512_core_bf16_ymm = prefer_ymm_bit | avx512_core_bf16, + amx_tile = amx_tile_bit, + amx_int8 = amx_int8_bit | amx_tile, + amx_bf16 = amx_bf16_bit | amx_tile, + amx_fp16 = amx_fp16_bit | amx_tile, + avx512_core_fp16 = avx512_core_fp16_bit | avx512_core_bf16 | avx_vnni_bit, + avx512_core_amx = avx512_core_fp16 | amx_int8 | amx_bf16, + avx512_core_amx_fp16 = avx512_core_amx | amx_fp16, + // NOTES: 1. isa_all by default has no isa specific hints + // 2. avx2_vnni_2 is under preview support and turned off by default + // 3. avx512_core_amx_fp16 is under preview support and turned off + // by default + isa_all + = ~0u & ~avx_vnni_2_bit & ~amx_fp16_bit & ~cpu_isa_hints_utils::hints_mask, +}; + +enum class cpu_isa_cmp_t { + // List of infix comparison relations between two cpu_isa_t + // where we take isa_1 and isa_2 to be two cpu_isa_t instances. + + // isa_1 SUBSET isa_2 if all feature flags supported by isa_1 + // are supported by isa_2 as well (equality allowed) + SUBSET, + + // isa_1 SUPERSET isa_2 if all feature flags supported by isa_2 + // are supported by isa_1 as well (equality allowed) + SUPERSET, + + // Few more options that (depending upon need) can be enabled in future + + // 1. PROPER_SUBSET: isa_1 SUBSET isa_2 and isa_1 != isa_2 + // 2. PROPER_SUPERSET: isa_1 SUPERSET isa_2 and isa_1 != isa_2 +}; + +const char *get_isa_info(); + +cpu_isa_t get_max_cpu_isa(); +cpu_isa_t DNNL_API get_max_cpu_isa_mask(bool soft = false); +status_t set_max_cpu_isa(dnnl_cpu_isa_t isa); +dnnl_cpu_isa_t get_effective_cpu_isa(); + +static inline bool compare_isa( + cpu_isa_t isa_1, cpu_isa_cmp_t cmp, cpu_isa_t isa_2) { + assert(isa_1 != isa_all); + assert(isa_2 != isa_all); + // Comparison with `isa_all` is illegal. + if (utils::one_of(isa_all, isa_1, isa_2)) return false; + + // By default, comparison between ISA ignores ISA specific hints + unsigned mask_1 + = static_cast(isa_1) & ~cpu_isa_hints_utils::hints_mask; + unsigned mask_2 + = static_cast(isa_2) & ~cpu_isa_hints_utils::hints_mask; + unsigned mask_common = mask_1 & mask_2; + + switch (cmp) { + case cpu_isa_cmp_t::SUBSET: return mask_1 == mask_common; + case cpu_isa_cmp_t::SUPERSET: return mask_2 == mask_common; + default: assert(!"unsupported comparison of isa"); return false; + } +} + +static inline bool is_subset(cpu_isa_t isa_1, cpu_isa_t isa_2) { + return compare_isa(isa_1, cpu_isa_cmp_t::SUBSET, isa_2); +} + +static inline bool is_superset(cpu_isa_t isa_1, cpu_isa_t isa_2) { + return compare_isa(isa_1, cpu_isa_cmp_t::SUPERSET, isa_2); +} + +template +struct vreg_traits {}; + +template <> +struct vreg_traits { + typedef Xbyak::Ymm Vmm_lower_t; + static constexpr size_t vlen = 64; +}; + +template <> +struct vreg_traits { + typedef Xbyak::Xmm Vmm_lower_t; + static constexpr size_t vlen = 32; +}; + +template <> +struct vreg_traits { + typedef Xbyak::Xmm Vmm_lower_t; + static constexpr size_t vlen = 16; +}; + +template +struct cpu_isa_traits {}; /* ::vlen -> 32 (for avx2) */ + +// pack struct so it can fit into a single 64-byte cache line +#pragma pack(push, 1) +struct palette_config_t { + uint8_t palette_id; + uint8_t startRow; + uint8_t reserved[14]; + uint16_t cols[16]; + uint8_t rows[16]; +}; +#pragma pack(pop) + +template <> +struct cpu_isa_traits { + static constexpr dnnl_cpu_isa_t user_option_val = dnnl_cpu_isa_default; + static constexpr const char *user_option_env = "default"; +}; + +template <> +struct cpu_isa_traits { + typedef Xbyak::Xmm Vmm; + static constexpr int vlen_shift = 4; + static constexpr int vlen = vreg_traits::vlen; + static constexpr int n_vregs = 16; + static constexpr dnnl_cpu_isa_t user_option_val = dnnl_cpu_isa_sse41; + static constexpr const char *user_option_env = "sse41"; +}; + +template <> +struct cpu_isa_traits { + typedef Xbyak::Ymm Vmm; + static constexpr int vlen_shift = 5; + static constexpr int vlen = vreg_traits::vlen; + static constexpr int n_vregs = 16; + static constexpr dnnl_cpu_isa_t user_option_val = dnnl_cpu_isa_avx; + static constexpr const char *user_option_env = "avx"; +}; + +template <> +struct cpu_isa_traits : public cpu_isa_traits { + static constexpr dnnl_cpu_isa_t user_option_val = dnnl_cpu_isa_avx2; + static constexpr const char *user_option_env = "avx2"; +}; + +template <> +struct cpu_isa_traits : public cpu_isa_traits { + static constexpr dnnl_cpu_isa_t user_option_val = dnnl_cpu_isa_avx2_vnni; + static constexpr const char *user_option_env = "avx2_vnni"; +}; + +template <> +struct cpu_isa_traits : public cpu_isa_traits { + static constexpr dnnl_cpu_isa_t user_option_val = dnnl_cpu_isa_avx2_vnni_2; + static constexpr const char *user_option_env = "avx2_vnni_2"; +}; + +template <> +struct cpu_isa_traits { + typedef Xbyak::Zmm Vmm; + static constexpr int vlen_shift = 6; + static constexpr int vlen = vreg_traits::vlen; + static constexpr int n_vregs = 32; + static constexpr dnnl_cpu_isa_t user_option_val = dnnl_cpu_isa_avx512_core; + static constexpr const char *user_option_env = "avx512_core"; +}; + +template <> +struct cpu_isa_traits : public cpu_isa_traits { + static constexpr dnnl_cpu_isa_t user_option_val + = dnnl_cpu_isa_avx512_core_vnni; + static constexpr const char *user_option_env = "avx512_core_vnni"; +}; + +template <> +struct cpu_isa_traits : public cpu_isa_traits { + static constexpr dnnl_cpu_isa_t user_option_val + = dnnl_cpu_isa_avx512_core_bf16; + static constexpr const char *user_option_env = "avx512_core_bf16"; +}; + +template <> +struct cpu_isa_traits { + static constexpr dnnl_cpu_isa_t user_option_val + = dnnl_cpu_isa_avx512_core_amx; + static constexpr const char *user_option_env = "avx512_core_amx"; +}; + +template <> +struct cpu_isa_traits : public cpu_isa_traits { + static constexpr dnnl_cpu_isa_t user_option_val + = dnnl_cpu_isa_avx512_core_fp16; + static constexpr const char *user_option_env = "avx512_core_fp16"; +}; + +template <> +struct cpu_isa_traits { + static constexpr dnnl_cpu_isa_t user_option_val + = dnnl_cpu_isa_avx512_core_amx_fp16; + static constexpr const char *user_option_env = "avx512_core_amx_fp16"; +}; + +inline const Xbyak::util::Cpu &cpu() { + const static Xbyak::util::Cpu cpu_; + return cpu_; +} + +namespace amx { + +// Return the target palette for AMX instructions. Currently this is `0` if AMX +// instructions are not supported, and `1` if they are. +int get_target_palette(); + +int get_max_tiles(int palette); +int get_max_column_bytes(int palette); +int get_max_rows(int palette); +bool DNNL_API is_available(); + +} // namespace amx + +namespace { + +static inline bool mayiuse(const cpu_isa_t cpu_isa, bool soft = false) { + using namespace Xbyak::util; + + unsigned cpu_isa_mask = x64::get_max_cpu_isa_mask(soft); + unsigned cpu_isa_no_hints = cpu_isa & ~cpu_isa_hints_utils::hints_mask; + + if ((cpu_isa_mask & cpu_isa_no_hints) != cpu_isa_no_hints) return false; + + switch (cpu_isa) { + case sse41: return cpu().has(Cpu::tSSE41); + case avx: return cpu().has(Cpu::tAVX); + case avx2: return cpu().has(Cpu::tAVX2); + case avx2_vnni: return mayiuse(avx2, soft) && cpu().has(Cpu::tAVX_VNNI); + case avx2_vnni_2: + return mayiuse(avx2_vnni, soft) && cpu().has(Cpu::tAVX_VNNI_INT8) + && cpu().has(Cpu::tAVX_NE_CONVERT); + case avx512_core: + return cpu().has(Cpu::tAVX512F) && cpu().has(Cpu::tAVX512BW) + && cpu().has(Cpu::tAVX512VL) && cpu().has(Cpu::tAVX512DQ); + case avx512_core_vnni: + return cpu().has(Cpu::tAVX512F) && cpu().has(Cpu::tAVX512BW) + && cpu().has(Cpu::tAVX512VL) && cpu().has(Cpu::tAVX512DQ) + && cpu().has(Cpu::tAVX512_VNNI); + case avx512_core_bf16: + return mayiuse(avx512_core_vnni, soft) + && cpu().has(Cpu::tAVX512_BF16); + case avx512_core_bf16_ymm: + return mayiuse(avx512_core_bf16, soft) + && cpu_isa_hints_utils::is_hints_bit_set( + prefer_ymm_bit, soft); + case avx512_core_fp16: + return cpu().has(Cpu::tAVX512_FP16) + && mayiuse(avx512_core_bf16, soft) + && mayiuse(avx2_vnni, soft); + case amx_tile: + return cpu().has(Cpu::tAMX_TILE) && x64::amx::is_available(); + case amx_int8: + return mayiuse(amx_tile, soft) && cpu().has(Cpu::tAMX_INT8); + case amx_bf16: + return mayiuse(amx_tile, soft) && cpu().has(Cpu::tAMX_BF16); + case amx_fp16: + return mayiuse(amx_tile, soft) && cpu().has(Cpu::tAMX_FP16); + case avx512_core_amx: + return mayiuse(amx_int8, soft) && mayiuse(amx_bf16, soft) + && mayiuse(avx512_core_fp16, soft); + case avx512_core_amx_fp16: + return mayiuse(avx512_core_amx, soft) && mayiuse(amx_fp16, soft); + case isa_undef: return true; + case isa_all: return false; + } + return false; +} + +static inline bool isa_has_int8_vnni(cpu_isa_t isa) { + return is_superset(isa, avx512_core_vnni) || is_superset(isa, avx2_vnni); +} + +static inline bool isa_has_s8s8(cpu_isa_t isa) { + return is_superset(isa, amx_int8) || is_superset(isa, avx2_vnni_2); +} + +static inline bool isa_has_bf16(cpu_isa_t isa) { + return is_superset(isa, avx512_core_bf16); +} + +static inline bool isa_has_masks(cpu_isa_t isa) { + return is_superset(isa, avx512_core); +} + +static inline int isa_max_vlen(cpu_isa_t isa) { + if (is_superset(isa, avx512_core)) + return cpu_isa_traits::vlen; + else if (is_superset(isa, avx2)) + return cpu_isa_traits::vlen; + else if (is_superset(isa, sse41)) + return cpu_isa_traits::vlen; + else + return 0; +} + +static inline int isa_num_vregs(cpu_isa_t isa) { + if (is_superset(isa, avx512_core)) + return cpu_isa_traits::n_vregs; + else if (is_superset(isa, avx2)) + return cpu_isa_traits::n_vregs; + else if (is_superset(isa, sse41)) + return cpu_isa_traits::n_vregs; + else + return 0; +} + +} // namespace + +/* whatever is required to generate string literals... */ +#include "common/z_magic.hpp" +/* clang-format off */ +#define JIT_IMPL_NAME_HELPER(prefix, isa, suffix_if_any) \ + ((isa) == isa_undef ? prefix STRINGIFY(undef) : \ + (isa) == sse41 ? prefix STRINGIFY(sse41) : \ + (isa) == avx ? prefix STRINGIFY(avx) : \ + (isa) == avx2 ? prefix STRINGIFY(avx2) : \ + (isa) == avx2_vnni ? prefix STRINGIFY(avx2_vnni) : \ + (isa) == avx2_vnni_2 ? prefix STRINGIFY(avx2_vnni_2) : \ + (isa) == avx512_core ? prefix STRINGIFY(avx512_core) : \ + (isa) == avx512_core_vnni ? prefix STRINGIFY(avx512_core_vnni) : \ + (isa) == avx512_core_bf16 ? prefix STRINGIFY(avx512_core_bf16) : \ + (isa) == avx512_core_fp16 ? prefix STRINGIFY(avx512_core_fp16) : \ + (isa) == avx512_core_amx ? prefix STRINGIFY(avx512_core_amx) : \ + (isa) == avx512_core_amx_fp16 ? prefix STRINGIFY(avx512_core_amx_fp16) : \ + prefix suffix_if_any) +/* clang-format on */ + +inline size_t data_type_vnni_granularity(data_type_t data_type) { + using namespace data_type; + switch (data_type) { + case f32: + case s32: return size_t(1); + case f16: + case bf16: return size_t(2); + case s8: + case u8: return size_t(4); + case data_type::undef: + default: assert(!"unknown data_type"); + } + return size_t(0); /* should not be reachable */ +} + +template +inline size_t data_type_vnni_simd_elems(data_type_t data_type) { + const size_t dt_size = types::data_type_size(data_type); + assert(dt_size > 0); + return cpu_isa_traits::vlen / dt_size; +} + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/cpu_reducer.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/cpu_reducer.hpp new file mode 100644 index 0000000000000000000000000000000000000000..2ecf022b859959f390b2c0c0bc53d78c8595bd40 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/cpu_reducer.hpp @@ -0,0 +1,356 @@ +/******************************************************************************* +* Copyright 2017-2020 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_CPU_REDUCER_HPP +#define CPU_X64_CPU_REDUCER_HPP + +#include + +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/memory_tracking.hpp" +#include "common/nstl.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" +#include "oneapi/dnnl/dnnl_types.h" + +#include "cpu/x64/cpu_barrier.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +/** class to perform balancing over 3D array + * + * Conceptually the reduction happens according to the picture below: + * + * <--job_size-> + * +-----------+ +-----------+ +-----------+ ^ + * | | | | | | | + * | | | | | | | + * | 1 | | 2 | . . . | njobs | | reduction_size + * | | | | | | | + * | | | | | | | + * +-----------+ +-----------+ +-----------+ v + * + * | | | | | | | | | + * v v v v v v v v v + * ===================================================== vertical reduction + * + * +-----------+ +-----------+ . . . +-----------+ result + * + * In a simple case the result must be contiguous in memory. + * @class cpu_reducer_t is an implementation. + * + * Threads are divided into groups. The groups are independent of each other. + * Each group may work on several jobs (the distribution is not uniform, since + * njobs might be not a multiple of groups). Threads within a group work on + * different parts of the reduction dimension. Thread 0 in each group is called + * master (@sa reduce_balancer_t::master()). + * + * If threading driver does not allow sync between sub-group of threads (e.g. + * TBB) the # of thread per group is enforced to be 1. + */ +struct reduce_balancer_t { + reduce_balancer_t() { init(1, 1, 1, 1, 0); } /* trivial balance */ + reduce_balancer_t(int nthr, int job_size, int njobs, int reduction_size, + size_t max_buffer_size, bool lock_free = false) { + init(nthr, job_size, njobs, reduction_size, max_buffer_size, lock_free); + } + + reduce_balancer_t &init(int nthr, int job_size, int njobs, + int reduction_size, size_t max_buffer_size, + bool lock_free = false) { + allow_nthr_in_group_ = lock_free ? true : dnnl_thr_syncable(); + nthr_ = nthr; + job_size_ = job_size; + njobs_ = njobs; + reduction_size_ = reduction_size; + max_buffer_size_ = max_buffer_size; + balance(); + return *this; + } + + bool allow_nthr_in_group_; + int nthr_; + int job_size_, njobs_, reduction_size_; + + int ngroups_; /** number of independent work (thread) groups */ + int nthr_per_group_; /** number of threads within a single work group */ + int njobs_per_group_ub_; /** the max # of jobs within a work group */ + + bool master(int ithr) const { return id_in_group(ithr) == 0; } + bool idle(int ithr) const { return ithr >= nthr_per_group_ * ngroups_; } + + int group_id(int ithr) const { return ithr / nthr_per_group_; } + int id_in_group(int ithr) const { return ithr % nthr_per_group_; } + + int grp_njobs(int grp) const { + if (grp >= ngroups_) return 0; + return njobs_ / ngroups_ + (grp < njobs_ % ngroups_); + } + int grp_job_off(int grp) const { + if (grp >= ngroups_) return njobs_; + return njobs_ / ngroups_ * grp + nstl::min(grp, njobs_ % ngroups_); + } + + int ithr_njobs(int ithr) const { return grp_njobs(group_id(ithr)); } + int ithr_job_off(int ithr) const { return grp_job_off(group_id(ithr)); } + +private: + size_t max_buffer_size_; + void balance(); +}; + +/** forward declaration of reduce driver */ +template +struct reducer_2d_driver_t; + +/** class to perform a reduction over 3D array + * + * Balancing is based on @class reduce_balancer_t. + * Restrictions: the result of the reduction must be contiguous in memory. * + * The reduction happens according to the picture below (once more): + * + * <--job_size-> + * +-----------+ +-----------+ +-----------+ ^ + * | | | | | | | + * | | | | | | | + * | 1 | | 2 | . . . | njobs | | reduction_size + * | | | | | | | + * | | | | | | | + * +-----------+ +-----------+ +-----------+ v + * + * | | | | | | | | | + * v v v v v v v v v + * ===================================================== vertical reduction + * + * +-----------+ +-----------+ . . . +-----------+ (contiguous) result + * + * An example how work might be shared is shown below. + * + * In this example group 0 owns 2 (independent) jobs -- 2 big squares. + * The number of threads per group is also 2 (thread 0 of group 0 and thread 1 + * of group 0). Master threads (i.e. threads with id 0 in corresponding group) + * from each group put the partial result directly into destination memory, + * while all the other threads with-in the group use workspace (on the picture + * the only thread 1). Once intermediate results obtained each group reduces + * corresponding part (own jobs) to the destination memory. + * + * <------- group 0 -------> + * + * +-----------+ +-----------+ ^ + * | | | | | thread 0 of reduces to the dest-memory + * | | | | | group 0 +-----------+ +-----------+ + * |- - - - - -| |- - - - - -| X + * | | | | | thread 1 of reduces to workspace[tid=1]: + * | | | | | group 0 +-----------+ +-----------+ + * +-----------+ +-----------+ v + * | | | | | | + * v v v v v v + * ((barrier)) ============================= + * + * dest-memory: +-----------+ +-----------+ + */ +template +struct cpu_reducer_t { + typedef typename prec_traits::type data_t; + + struct conf_t { + conf_t() = default; + conf_t &init(const reduce_balancer_t &balancer) { + balancer_ = balancer; + return *this; + } + + void init_scratchpad(memory_tracking::registrar_t &scratchpad) const; + + reduce_balancer_t balancer_; + }; + + status_t create_kernel(); + + cpu_reducer_t(const conf_t &conf); + ~cpu_reducer_t(); + + /** initializes reducer. + * Must be called from a single thread prior to actual usage */ + void init(const memory_tracking::grantor_t &scratchpad) const { + if (balancer().nthr_per_group_ == 1 || !dnnl_thr_syncable()) return; + + auto bctx = scratchpad.template get( + memory_tracking::names::key_reducer_space_bctx); + for (int i = 0; i < balancer().ngroups_; ++i) + simple_barrier::ctx_init(&bctx[i]); + } + + /** for given thread returns the pointer where to put partial results. + * Reduction destination @p dst must be provided as well (master threads + * from each group will use it for partial result to reduce memory + * pressure). + * + * @note: job offset is already applied by get_local_ptr(), which means all + * threads should start writing from the very beginning of returned + * address. + */ + data_t *get_local_ptr(int ithr, data_t *dst, + const memory_tracking::grantor_t &scratchpad) const; + + /** performs the reduction with built-in synchronization. */ + void reduce(int ithr, data_t *dst, + const memory_tracking::grantor_t &scratchpad) const { + bool redundant_reduction + = balancer().nthr_per_group_ == 1 || balancer().idle(ithr); + if (redundant_reduction) return; + + auto bctx = scratchpad.template get( + memory_tracking::names::key_reducer_space_bctx); + simple_barrier::barrier( + &bctx[balancer().group_id(ithr)], balancer().nthr_per_group_); + + reduce_nolock(ithr, dst, scratchpad); + } + + void reduce_nolock(int ithr, data_t *dst, + const memory_tracking::grantor_t &scratchpad) const; + + const reduce_balancer_t &balancer() const { return conf_.balancer_; } + +private: + static size_t space_per_thread(const reduce_balancer_t &balancer) { + return balancer.njobs_per_group_ub_ * balancer.job_size_; + } + + /* The scratchpad is organized as follows: + * + * data_t space[nthr_][njobs_per_group_ub_][jobs_size_]; + * simple_barrier::ctx_t barriers[groups_]; */ + + const conf_t conf_; + reducer_2d_driver_t *drv_; + + DNNL_DISALLOW_COPY_AND_ASSIGN(cpu_reducer_t); +}; + +template +struct cpu_reducer_2d_t { + typedef typename prec_traits::type data_t; + + struct conf_t { + conf_t() = default; + conf_t &init(const reduce_balancer_t &balancer, int job_size_x, + int job_size_y, int x_block, int dst_x, int dst_y) { + balancer_ = balancer; + job_size_x_ = job_size_x; + job_size_y_ = job_size_y; + x_block_ = x_block; + dst_x_ = dst_x; + dst_y_ = dst_y; + return *this; + } + + void init_scratchpad(memory_tracking::registrar_t &scratchpad) const; + + reduce_balancer_t balancer_; + int job_size_x_, job_size_y_, x_block_, dst_x_, dst_y_; + }; + + status_t create_kernel(); + + cpu_reducer_2d_t(const conf_t &conf); + ~cpu_reducer_2d_t(); + + /** initializes reducer. + * Must be called from a single thread prior to actual usage */ + void init(const memory_tracking::grantor_t &scratchpad) const { + if (balancer().nthr_per_group_ == 1 || !dnnl_thr_syncable()) return; + + auto bctx = scratchpad.template get( + memory_tracking::names::key_reducer_space_bctx); + for (int i = 0; i < balancer().ngroups_; ++i) + simple_barrier::ctx_init(&bctx[i]); + } + + /** for given thread returns the pointer where to put partial results */ + data_t *get_local_ptr( + int ithr, const memory_tracking::grantor_t &scratchpad) const; + + /** performs the reduction with built-in synchronization. */ + void reduce(int ithr, data_t *dst, + const memory_tracking::grantor_t &scratchpad) const { + bool redundant_reduction + = balancer().nthr_per_group_ == 1 || balancer().idle(ithr); + if (redundant_reduction) return; + + auto bctx = scratchpad.template get( + memory_tracking::names::key_reducer_space_bctx); + simple_barrier::barrier( + &bctx[balancer().group_id(ithr)], balancer().nthr_per_group_); + + reduce_nolock(ithr, dst, scratchpad); + } + + void reduce_nolock(int ithr, data_t *dst, + const memory_tracking::grantor_t &scratchpad) const; + + const reduce_balancer_t &balancer() const { return conf_.balancer_; } + +private: + static size_t space_per_thread(const reduce_balancer_t &balancer) { + return balancer.njobs_per_group_ub_ * balancer.job_size_; + } + + /* The scratchpad is organized as follows: + * + * data_t space[nthr_][njobs_per_group_ub_][jobs_size_]; + * simple_barrier::ctx_t barriers[groups_]; */ + + const conf_t conf_; + reducer_2d_driver_t *drv_; + + int choose_x_blocking(int nx, int ny, int nthr_per_grp) const; + void reduce_block(const data_t *space_base, data_t *dst, int job, + int start_y, int start_x, int ny_start, int nx_start, int ny_step, + int nx_step) const; + + DNNL_DISALLOW_COPY_AND_ASSIGN(cpu_reducer_2d_t); +}; + +/** simple 1d accumulator: y[:] += x[:] */ +template +struct cpu_accumulator_1d_t { + typedef typename prec_traits::type data_t; + + cpu_accumulator_1d_t(); + ~cpu_accumulator_1d_t(); + void accumulate(data_t *dst, const data_t *src, size_t size); + + status_t create_kernel(); + + reducer_2d_driver_t *drv_; + + DNNL_DISALLOW_COPY_AND_ASSIGN(cpu_accumulator_1d_t); +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/amx/jit_avx512_core_amx_copy_kern.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/amx/jit_avx512_core_amx_copy_kern.hpp new file mode 100644 index 0000000000000000000000000000000000000000..76d830f97505dacf4f6c60ffd50bc9879e902944 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/amx/jit_avx512_core_amx_copy_kern.hpp @@ -0,0 +1,104 @@ +/******************************************************************************* +* Copyright 2020-2021 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_GEMM_AMX_JIT_AVX512_CORE_AMX_COPY_KERN_HPP +#define CPU_X64_GEMM_AMX_JIT_AVX512_CORE_AMX_COPY_KERN_HPP + +#include "cpu/x64/jit_generator.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +class jit_avx512_core_amx_copy_kern : public jit_generator { +public: + jit_avx512_core_amx_copy_kern(bool is_a, bool is_trans, int isize); + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_amx_copy_kern); + +protected: + bool is_a_; + bool is_trans_; + int lscale_, lsize_; + + int size_; + int isize_; + + int unroll_k_; + + void load(const Xbyak::Xmm &dst, const Xbyak::Address &src, bool corner); + void store(const Xbyak::Address &dst, const Xbyak::Xmm &src); + + void transpose(int s, const Xbyak::Ymm &dst1, const Xbyak::Ymm &dst2, + const Xbyak::Ymm &src1, const Xbyak::Ymm &src2); + + void amxtrans8(const Xbyak::Ymm &dst1, const Xbyak::Ymm &dst2, + const Xbyak::Ymm &src1, const Xbyak::Ymm &src2, + const Xbyak::Ymm &src3, const Xbyak::Ymm &src4); + void amxtrans16(const Xbyak::Ymm &dst1, const Xbyak::Ymm &dst2, + const Xbyak::Ymm &src1, const Xbyak::Ymm &src2); + + void kernel(int unroll_x, int unroll_y, int step, Xbyak::Reg64 A, + Xbyak::Reg64 B, bool corner); + void kernel_AN(int unroll_x, int unroll_y, int step, Xbyak::Reg64 A, + Xbyak::Reg64 B, bool corner); + void kernel_BN(int unroll_x, int unroll_y, int step, Xbyak::Reg64 A, + Xbyak::Reg64 B, bool corner); + void kernel_AT(int unroll_x, int unroll_y, int step, Xbyak::Reg64 A, + Xbyak::Reg64 B, bool corner); + void kernel_BT(int unroll_x, int unroll_y, int step, Xbyak::Reg64 A, + Xbyak::Reg64 B, bool corner); + + void copy_m(int unroll_m, int unroll_n); + void copy_n(int unroll_n, Xbyak::Label &epilogue); + void copy_ns(int unroll_n, Xbyak::Label &epilogue); + + void generate() override ATTRIBUTE_OPTIMIZE; + +private: + static const int offset_a_ = 0, offset_b_ = 0; + + static const int ntiles_m_ = 2; + static const int unroll_m_ = 16 * ntiles_m_; + static const int max_unroll_ = 32; + static const int nstages_ = 4; + + const int idx_[nstages_][2][9] = { + {{16, 0, 1, 2, 3, 4, 5, 6, 7}, {17, 8, 9, 10, 11, 12, 13, 14, 15}}, + {{7, 16, 0, 1, 2, 17, 8, 9, 10}, {15, 3, 4, 5, 6, 11, 12, 13, 14}}, + {{10, 7, 16, 15, 3, 2, 17, 6, 11}, {14, 0, 1, 4, 5, 8, 9, 12, 13}}, + {{11, 10, 14, 16, 1, 3, 5, 17, 9}, {13, 7, 0, 15, 4, 2, 8, 6, 12}}}; + + // Integer register assignments + Xbyak::Reg64 M_, N_, B_, A_, LDA_; + Xbyak::Reg64 B1_, BB_, A1_, A2_, LDA3_; + Xbyak::Reg64 I_, T_, STRIDE_; + + // Vector register assignments + Xbyak::Ymm src_[16], vecs_[nstages_][2][8 + 1]; + Xbyak::Ymm tmp1_, tmp2_; + + // Stack variable assignments + int stack_alloc_size_; + Xbyak::Address arg_b_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif // CPU_X64_GEMM_AMX_JIT_AVX512_CORE_AMX_COPY_KERN_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/amx/jit_avx512_core_amx_gemm_kern.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/amx/jit_avx512_core_amx_gemm_kern.hpp new file mode 100644 index 0000000000000000000000000000000000000000..08987d8afc1e6e94a6bfa0fc8ea864fa12422d37 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/amx/jit_avx512_core_amx_gemm_kern.hpp @@ -0,0 +1,46 @@ +/******************************************************************************* +* Copyright 2020-2021 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_GEMM_AMX_JIT_AVX512_CORE_AMX_GEMM_KERN_HPP +#define CPU_X64_GEMM_AMX_JIT_AVX512_CORE_AMX_GEMM_KERN_HPP + +#include "cpu/x64/jit_generator.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +class jit_avx512_core_amx_gemm_kern : public jit_generator { +public: + jit_avx512_core_amx_gemm_kern( + int typea, int typeb, int typec, int betaZero); + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_amx_gemm_kern); + +protected: + void generate() override ATTRIBUTE_OPTIMIZE; + const int typea; + const int typeb; + const int typec; + const int isBetaZero; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif // CPU_X64_GEMM_AMX_JIT_AVX512_CORE_AMX_GEMM_KERN_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/bf16/common_s16.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/bf16/common_s16.hpp new file mode 100644 index 0000000000000000000000000000000000000000..eb0de3a9be90040af4281684c77af3bb33d90943 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/bf16/common_s16.hpp @@ -0,0 +1,97 @@ +/******************************************************************************* +* Copyright 2019-2021 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_GEMM_BF16_COMMON_S16_HPP +#define CPU_X64_GEMM_BF16_COMMON_S16_HPP + +#include "cpu/x64/jit_generator.hpp" + +#define S16_COPY_KERNEL_CODE_SIZE (4096L * 8) + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +class jit_avx512_core_s16_48x8_copy_an_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_s16_48x8_copy_an_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx512_core_s16_48x8_copy_an_kern(); +}; + +class jit_avx512_core_s16_48x8_copy_at_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_s16_48x8_copy_at_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx512_core_s16_48x8_copy_at_kern(); +}; + +class jit_avx512_core_s16_48x8_copy_bn_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_s16_48x8_copy_bn_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx512_core_s16_48x8_copy_bn_kern(); +}; + +class jit_avx512_core_s16_48x8_copy_bt_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_s16_48x8_copy_bt_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx512_core_s16_48x8_copy_bt_kern(); +}; + +class jit_avx512_core_s16_24x8_copy_an_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_s16_24x8_copy_an_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx512_core_s16_24x8_copy_an_kern(); +}; + +class jit_avx512_core_s16_24x8_copy_at_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_s16_24x8_copy_at_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx512_core_s16_24x8_copy_at_kern(); +}; + +class jit_avx512_core_s16_24x8_copy_bn_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_s16_24x8_copy_bn_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx512_core_s16_24x8_copy_bn_kern(); +}; + +class jit_avx512_core_s16_24x8_copy_bt_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_s16_24x8_copy_bt_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx512_core_s16_24x8_copy_bt_kern(); +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl +#endif // CPU_X64_GEMM_BF16_COMMON_S16_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/bf16/jit_avx512_core_gemm_bf16bf16f32_kern.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/bf16/jit_avx512_core_gemm_bf16bf16f32_kern.hpp new file mode 100644 index 0000000000000000000000000000000000000000..5362409a44d35163b3d9fac889fd1ac3fa3b45a4 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/bf16/jit_avx512_core_gemm_bf16bf16f32_kern.hpp @@ -0,0 +1,107 @@ +/******************************************************************************* +* Copyright 2019-2021 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_GEMM_BF16_JIT_AVX512_CORE_GEMM_BF16BF16F32_KERN_HPP +#define CPU_X64_GEMM_BF16_JIT_AVX512_CORE_GEMM_BF16BF16F32_KERN_HPP + +#include "cpu/x64/jit_avx512_core_bf16cvt.hpp" +#include "cpu/x64/jit_generator.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +class jit_avx512_core_gemm_bf16bf16f32_kern : public jit_generator { +public: + jit_avx512_core_gemm_bf16bf16f32_kern( + bool beta_zero, bool alpha_one, bool use_zmm); + ~jit_avx512_core_gemm_bf16bf16f32_kern(); + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_gemm_bf16bf16f32_kern); + +protected: + bool beta_zero_; + bool alpha_one_; + bool bfloat16_; + + int UNROLL_M_; + + int a_nelems_; + int b_nelems_; + int c_nelems_; + + void prefetch_a(const Xbyak::Address &src) { prefetcht0(src); } + void prefetch_b(const Xbyak::Address &src) { prefetcht0(src); } + void prefetch_c(const Xbyak::Address &src) { prefetchw(src); } + void prefetch_x(const Xbyak::Address &src) { prefetcht0(src); } + + void c_load(const Xbyak::Xmm &dst, const Xbyak::Address &src, int nelems); + void c_store(const Xbyak::Address &dst, const Xbyak::Xmm &src, int nelems); + + void dot_product(const Xbyak::Xmm &dst, const Xbyak::Xmm &src1, + const Xbyak::Xmm &src2); + void kernel_loop(int unroll_m, int unroll_n, bool cfetch); + void remainder_kernel(int unroll_m, int unroll_n, int unroll_k, int bwidth); + void innerloop(int unroll_m, int unroll_n); + void outerloop(int unroll_x, int unroll_y, Xbyak::Label *&outerloop_label); + + void generate() override ATTRIBUTE_OPTIMIZE; + +private: + static const int UNROLL_N_ = 8; + + static const int isize_ = 2; + static const int size_ = 4; + + // Prefetch configuration + static const int prefetch_size_a_ = 32 * 5; + static const int prefetch_size_b_ = 32 * 4; + + static const int offset_a_ = 256, offset_b_ = 256; + static const int max_unroll_m_ = 48, max_unroll_n_ = 8; + + // Integer register assignments + Xbyak::Reg64 M_, N_, K_, ALPHA_, A_, B_, C_, LDC_, I_, J_, LoopCount_; + Xbyak::Reg64 AO_, BO_, CO1_, CO2_, AA_; + + // Vector register assignments + Xbyak::Xmm alpha_, a_regs_[max_unroll_m_ >> 4], b_regs_[2]; + Xbyak::Xmm c_regs_[max_unroll_m_ >> 4][max_unroll_n_]; + + // Kind of vector register (Zmm or Ymm) + Xbyak::Operand::Kind kind_; + + // Stack variable assignments + int stack_alloc_size_; + Xbyak::Address arg_a_, arg_b_, arg_c_, arg_ldc_, arg_coffset_c_, + arg_coffset_r_; + + // For bfloat16 emulation on avx512 and avx512_vnni ISAs + bf16_emulation_t *bf16_emu_; + Xbyak::Reg64 scratch_; + Xbyak::Zmm one_; + Xbyak::Zmm even_; + Xbyak::Zmm selector_; + Xbyak::Zmm zmm_tmp0_; + Xbyak::Zmm zmm_tmp1_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif // CPU_X64_GEMM_BF16_JIT_AVX512_CORE_GEMM_BF16BF16F32_KERN_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/bf16/jit_avx512_core_gemv_bf16bf16f32_kern.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/bf16/jit_avx512_core_gemv_bf16bf16f32_kern.hpp new file mode 100644 index 0000000000000000000000000000000000000000..c7418ce7642d3beae221e4a05193671382c21114 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/bf16/jit_avx512_core_gemv_bf16bf16f32_kern.hpp @@ -0,0 +1,101 @@ +/******************************************************************************* +* Copyright 2020-2021 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_GEMM_BF16_JIT_AVX512_CORE_GEMV_BF16BF16F32_KERN_HPP +#define CPU_X64_GEMM_BF16_JIT_AVX512_CORE_GEMV_BF16BF16F32_KERN_HPP + +#include "cpu/x64/jit_avx512_core_bf16cvt.hpp" +#include "cpu/x64/jit_generator.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +class jit_avx512_core_gemv_bf16bf16f32_kern : public jit_generator { +public: + jit_avx512_core_gemv_bf16bf16f32_kern(bool trans); + ~jit_avx512_core_gemv_bf16bf16f32_kern(); + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_gemv_bf16bf16f32_kern); + +protected: + bool trans_; + bool bfloat16_; + + void prefetch_a(const Xbyak::Address &src) { prefetcht0(src); } + void prefetch_x(const Xbyak::Address &src) { prefetcht0(src); } + void prefetch_y(const Xbyak::Address &src) { prefetcht0(src); } + + void y_load(const Xbyak::Xmm &dst, const Xbyak::Address &src, int nelems); + void y_store(const Xbyak::Address &dst, const Xbyak::Xmm &src, int nelems); + void v_load(const Xbyak::Xmm &dst, const Xbyak::Address &src, int nelems); + + void dot_product(const Xbyak::Xmm &dst, const Xbyak::Xmm &src1, + const Xbyak::Xmm &src2); + void kernel_loop_t(int unroll_m, int unroll_n, bool fetch, bool last); + void kernel_loop_n(int unroll_m, int unroll_n, bool cfetch, bool last); + void innerloop_t(int unroll_n); + void innerloop_n(int unroll_n); + void outerloop(int unroll_y, Xbyak::Label *&cur_outerloop_label, + Xbyak::Label *&outerloop_end_label); + + void generate() override ATTRIBUTE_OPTIMIZE; + +private: + static const int UNROLL_M_ = 64; + static const int UNROLL_N_ = 8; + + static const int size_a_ = 2; + static const int size_x_ = 2; + static const int size_y_ = 4; + + // Prefetch configuration + static const int prefetch_size_a_ = 32; + static const int prefetch_size_x_ = 32; + static const int prefetch_size_y_ = 32; + + static const int offset_a_ = 32; + static const int offset_x_ = 32; + static const int offset_y_ = 32; + + // Integer register assignments + Xbyak::Reg64 M_, N_, ALPHA_, A_, LDA_, X_, INCX_, Y_, INCY_, I_; + Xbyak::Reg64 A1_, A2_, X1_, Y1_, LDA3_; + + // Vector register assignments + Xbyak::Zmm alpha_, a_[UNROLL_N_], a_pack_[2]; + Xbyak::Zmm x_[2], x_pack_[UNROLL_N_ >> 1]; + Xbyak::Zmm y_[UNROLL_M_ >> 4], acc_[UNROLL_N_]; + Xbyak::Zmm scratch_[4]; + // Stack variable assignments + Xbyak::Address arg_lda_, arg_x_, arg_incx_, arg_y_, arg_incy_; + + // For bfloat16 emulation on avx512 and avx512_vnni ISAs + bf16_emulation_t *bf16_emu_; + Xbyak::Reg64 gpr_; + Xbyak::Zmm one_; + Xbyak::Zmm even_; + Xbyak::Zmm selector_; + Xbyak::Zmm zmm_tmp0_; + Xbyak::Zmm zmm_tmp1_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif // CPU_X64_GEMM_BF16_JIT_AVX512_CORE_GEMV_BF16BF16F32_KERN_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/f32/common_f32.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/f32/common_f32.hpp new file mode 100644 index 0000000000000000000000000000000000000000..ee2e0d554a21b849f7ef9fdb27d9b031b6cdf4d2 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/f32/common_f32.hpp @@ -0,0 +1,206 @@ +/******************************************************************************* +* Copyright 2019-2021 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_GEMM_F32_COMMON_F32_HPP +#define CPU_X64_GEMM_F32_COMMON_F32_HPP + +#include "cpu/x64/jit_generator.hpp" + +#define F32_COPY_KERNEL_CODE_SIZE (4096L * 5) +#define F32_COMPUTE_KERNEL_CODE_SIZE (4096L * 32) + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +class jit_avx512_core_f32_copy_an_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_f32_copy_an_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx512_core_f32_copy_an_kern(); +}; + +class jit_avx512_core_f32_copy_at_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_f32_copy_at_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + void generate_part1(const Xbyak::Label &, const Xbyak::Label &, + const Xbyak::Label &, const Xbyak::Label &) ATTRIBUTE_OPTIMIZE; + void generate_part2(Xbyak::Label, Xbyak::Label, Xbyak::Label, + Xbyak::Label) ATTRIBUTE_OPTIMIZE; + +public: + jit_avx512_core_f32_copy_at_kern(); +}; + +class jit_avx512_core_f32_copy_bn_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_f32_copy_bn_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx512_core_f32_copy_bn_kern(); +}; + +class jit_avx512_core_f32_copy_bt_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_f32_copy_bt_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx512_core_f32_copy_bt_kern(); +}; + +class jit_avx2_f32_copy_an_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx2_f32_copy_an_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx2_f32_copy_an_kern(); +}; + +class jit_avx2_f32_copy_at_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx2_f32_copy_at_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx2_f32_copy_at_kern(); +}; + +class jit_avx2_f32_copy_bn_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx2_f32_copy_bn_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx2_f32_copy_bn_kern(); +}; + +class jit_avx2_f32_copy_bt_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx2_f32_copy_bt_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx2_f32_copy_bt_kern(); +}; + +class jit_avx_f32_copy_an_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx_f32_copy_an_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx_f32_copy_an_kern(); +}; + +class jit_avx_f32_copy_at_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx_f32_copy_at_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx_f32_copy_at_kern(); +}; + +class jit_avx_f32_copy_bn_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx_f32_copy_bn_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx_f32_copy_bn_kern(); +}; + +class jit_avx_f32_copy_bt_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx_f32_copy_bt_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx_f32_copy_bt_kern(); +}; + +class jit_avx_kernel_b0_sgemm_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx_kernel_b0_sgemm_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + void generate_part1(const Xbyak::Label &, const Xbyak::Label &, + const Xbyak::Label &, const Xbyak::Label &) ATTRIBUTE_OPTIMIZE; + void generate_part2(Xbyak::Label, Xbyak::Label, Xbyak::Label, + Xbyak::Label) ATTRIBUTE_OPTIMIZE; + +public: + jit_avx_kernel_b0_sgemm_kern(); +}; + +class jit_avx_kernel_sgemm_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx_kernel_sgemm_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + void generate_part1(const Xbyak::Label &, const Xbyak::Label &, + const Xbyak::Label &) ATTRIBUTE_OPTIMIZE; + void generate_part2( + Xbyak::Label &, Xbyak::Label &, Xbyak::Label &) ATTRIBUTE_OPTIMIZE; + +public: + jit_avx_kernel_sgemm_kern(); +}; + +class jit_sse41_f32_copy_an_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_sse41_f32_copy_an_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_sse41_f32_copy_an_kern(); +}; + +class jit_sse41_f32_copy_at_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_sse41_f32_copy_at_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_sse41_f32_copy_at_kern(); +}; + +class jit_sse41_f32_copy_bn_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_sse41_f32_copy_bn_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_sse41_f32_copy_bn_kern(); +}; + +class jit_sse41_f32_copy_bt_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_sse41_f32_copy_bt_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_sse41_f32_copy_bt_kern(); +}; + +class jit_sse41_kernel_b0_sgemm_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_sse41_kernel_b0_sgemm_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_sse41_kernel_b0_sgemm_kern(); +}; + +class jit_sse41_kernel_sgemm_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_sse41_kernel_sgemm_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_sse41_kernel_sgemm_kern(); +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl +#endif // CPU_X64_GEMM_F32_COMMON_F32_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/f32/jit_avx2_kernel_sgemm_kern.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/f32/jit_avx2_kernel_sgemm_kern.hpp new file mode 100644 index 0000000000000000000000000000000000000000..766b07bc5c965f871e63b9c119611f9706fabf51 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/f32/jit_avx2_kernel_sgemm_kern.hpp @@ -0,0 +1,683 @@ +/******************************************************************************* +* Copyright 2019-2022 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_GEMM_F32_JIT_AVX2_KERNEL_SGEMM_KERN_HPP +#define CPU_X64_GEMM_F32_JIT_AVX2_KERNEL_SGEMM_KERN_HPP + +#include "cpu/x64/jit_generator.hpp" + +#define MAX_UNROLL_M 48 +#define MAX_UNROLL_N_BIN 3 + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +class jit_avx2_kernel_sgemm_kern : public jit_generator { + + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx2_kernel_sgemm_kern); + const int elt_size_ = 4; + const int elt_size_bin_ = 2; + int nelt_per_vecreg_ = mayiuse(avx512_core) ? 16 : 8; + const int unroll_m_reg_ = 3; + int unroll_m_ = unroll_m_reg_ * nelt_per_vecreg_; + const int unroll_n_ = mayiuse(avx512_core) ? 8 : 4; + const int unroll_k_ = 4; + const int unroll_k_bin_ = 2; + const int unroll_m_bin_ = mayiuse(avx512_core) ? 6 : 5; + const int second_fetch_ = mayiuse(avx512_core) ? 32 : 34; + unsigned int unroll_n_bin_ = mayiuse(avx512_core) ? 3 : 2; + bool beta_zero_; + + Xbyak::Reg64 M_ = rdi, N_ = rsi, K_ = rdx, A_ = r8, B_ = r9, C_ = r10, + LDC_ = r11; + Xbyak::Reg64 I_ = r12, J_ = r13, AA_ = rcx, KK_ = K_, BO_ = rbp, CO1_ = r14, + CO2_ = r15; + Xbyak::Reg64 AO_ = rbx, LL_ = rax; + int zmm_a_idx_ = 0, zmm_b_idx_ = mayiuse(avx512_core) ? 6 : 3, + zmm_acc_idx_ = mayiuse(avx512_core) ? 8 : 4; + int nb_zmm_a_ = mayiuse(avx512_core) ? unroll_m_reg_ * 2 : unroll_m_reg_, + nb_zmm_b_ = mayiuse(avx512_core) ? 2 : 1; + + int addr_off_ = mayiuse(avx512_core) ? 128 : 32; + int PREFETCHSIZEB_ = mayiuse(avx512_core) ? (-128 + 16 * 8) : 64; + int PREFETCHSIZEA_ = mayiuse(avx512_core) ? (-128 + 16 * 2) + : (PREFETCHSIZEB_ * 2 + 16); + int off_ = 0, offb_ = 0; + + int next_acc(int idx, int um, int un) const; + void prefetchB_beforeBload(int um, int un, int k_idx, int n_idx); + void prefetchB_beforeFMA(int um, int un, int k_idx, int n_idx, int m_idx); + void prefetchA_afterFMA(int um, int un, int k_idx, int n_idx, int m_idx); + void prefetchA_afterBload(int um, int un, int k_idx, int n_idx); + void prefetchB_afterFMA(int k_idx, int n_idx, int m_idx); + void prefetchA_beforeFMA(int um, int un, int k_idx, int n_idx, int m_idx); + void prefetchC_afterBload(int um, int un, int k_idx, int n_idx); + void prefetchC_beforeKloop(int um); + void generate() override ATTRIBUTE_OPTIMIZE; + + template + void loadA_betweenFMAs(int um, int un, int k_idx, int n_idx, int m_idx, + void (Xbyak::CodeGenerator::*aload)( + const T_desta &, const T_srca &)) { + int next_zmm_a = mayiuse(avx512_core) + ? unroll_m_reg_ + : std::max(1, um / nelt_per_vecreg_); + if (!(mayiuse(avx512_core) || (um <= 8) || ((um == 16) && (un == 4)))) { + if (n_idx == un - 1) { + (this->*aload)(T_reg(zmm_a_idx_ + m_idx + + (k_idx % (nb_zmm_a_ / unroll_m_reg_)) + * next_zmm_a), + ptr[AO_ + + elt_size_ + * (m_idx * nelt_per_vecreg_ + + um + * (k_idx + + nb_zmm_a_ + / unroll_m_reg_) + - addr_off_)]); + } + } + } + + template + void loadA_after(int um, int un, int k_idx, + void (Xbyak::CodeGenerator::*aload)( + const T_desta &, const T_srca &)) { + + int i; + int next_zmm_a = mayiuse(avx512_core) + ? unroll_m_reg_ + : std::max(1, um / nelt_per_vecreg_); + if (mayiuse(avx512_core) || (um <= 8) || ((um == 16) && (un == 4))) { + for (i = 0; i < std::max(um / nelt_per_vecreg_, 1); i++) { + (this->*aload)(T_reg(zmm_a_idx_ + i + + (k_idx % (nb_zmm_a_ / unroll_m_reg_)) + * next_zmm_a), + ptr[AO_ + + elt_size_ + * (i * nelt_per_vecreg_ + + um + * (k_idx + + nb_zmm_a_ + / unroll_m_reg_) + - addr_off_)]); + } + } + } + + template + void k_loop_body(int cfetch, int um, int un, + void (Xbyak::CodeGenerator::*aload)( + const T_desta &, const T_srca &), + void (Xbyak::CodeGenerator::*bload)( + const T_destb &, const T_srcb &)) { + + Xbyak::Label K_loop_body_label; + int i, j, p, b_idx; + int addb_off = ((!mayiuse(avx512_core)) && (nb_zmm_b_ == 2)) ? 1 : 0; + + int next_zmm_a = mayiuse(avx512_core) + ? unroll_m_reg_ + : std::max(1, um / nelt_per_vecreg_); + + off_ = 0, offb_ = 0; + + if (mayiuse(avx512_core)) L_aligned(K_loop_body_label); + + if (cfetch) prefetchC_beforeKloop(um); + + if (!mayiuse(avx512_core)) L_aligned(K_loop_body_label); + + for (p = 0; p < unroll_k_; p++) { + if (mayiuse(avx512_core)) { + if ((um == unroll_m_) && (p == unroll_k_ - 1)) { + prefetcht2(ptr[AA_ - elt_size_ * 128]); + } + } + for (j = 0; j < un; j++) { + + b_idx = mayiuse(avx512_core) ? j % nb_zmm_b_ : p % nb_zmm_b_; + + if (!mayiuse(avx512_core)) { + if ((um == unroll_m_) && (un == unroll_n_)) { + if ((j == un - 1) && (p == unroll_k_ - 1)) + sub(BO_, -un * unroll_k_ * elt_size_); + } + } + + for (i = 0; i < std::max(um / nelt_per_vecreg_, 1); i++) { + + prefetchA_beforeFMA(um, un, p, j, i); + prefetchB_beforeFMA(um, un, p, j, i); + + vfmadd231ps(T_reg(zmm_acc_idx_ + i * unroll_n_ + j), + T_reg(zmm_b_idx_ + b_idx), + T_reg(i + + (p % (nb_zmm_a_ / unroll_m_reg_)) + * next_zmm_a + + zmm_a_idx_)); + + loadA_betweenFMAs( + um, un, p, j, i, aload); + + prefetchB_afterFMA(p, j, i); + prefetchA_afterFMA(um, un, p, j, i); + } + + prefetchB_beforeBload(um, un, p, j); + + if (!mayiuse(avx512_core) && (um == unroll_m_) + && (un == unroll_n_) && (j == un - 1) + && (p == unroll_k_ - 1)) { + (this->*bload)(T_reg(zmm_b_idx_ + b_idx), + ptr[BO_ + + elt_size_ + * (un * p - addr_off_ + + std::min(nb_zmm_b_, un) + + j + addb_off) + - un * unroll_k_ * elt_size_]); + } else { + (this->*bload)(T_reg(zmm_b_idx_ + b_idx), + ptr[BO_ + + elt_size_ + * (un * p - addr_off_ + + std::min(nb_zmm_b_, un) + + j + addb_off)]); + } + + prefetchA_afterBload(um, un, p, j); + + if (cfetch) prefetchC_afterBload(um, un, p, j); + + if (mayiuse(avx512_core)) { + if ((um == unroll_m_) && (p == unroll_k_ - 1) + && (j == std::min(un - 1, 3))) + lea(AA_, ptr[AA_ + elt_size_ * unroll_n_]); + } + } + + if (mayiuse(avx512_core)) { + for (j = un; j < unroll_n_; j++) { + if (um < unroll_m_) { + if (((p % (nb_zmm_a_ / unroll_m_reg_) == 0) + && (j % 6 == 0)) + || ((p % (nb_zmm_a_ / unroll_m_reg_) == 1) + && (j == 3))) { + off_ += 16; + } + } + } + } + + loadA_after(um, un, p, aload); + } + + if (mayiuse(avx512_core)) { + lea(AO_, ptr[AO_ + um * unroll_k_ * elt_size_]); + lea(BO_, ptr[BO_ + un * unroll_k_ * elt_size_]); + } else { + if ((um != unroll_m_) || (un != unroll_n_)) + sub(BO_, -un * unroll_k_ * elt_size_); + sub(AO_, -um * unroll_k_ * elt_size_); + } + sub(LL_, 1); + + jg(K_loop_body_label, T_NEAR); + } + + template + void k_loop_remainder(int um, int un, + void (Xbyak::CodeGenerator::*aload)( + const T_desta &, const T_srca &), + void (Xbyak::CodeGenerator::*bload)( + const T_destb &, const T_srcb &)) { + + Xbyak::Label K_loop_remainder_label; + int i, j, off_ = 0; + + L_aligned(K_loop_remainder_label); + + for (j = 0; j < un; j++) { + + for (i = 0; i < std::max(um / nelt_per_vecreg_, 1); i++) { + vfmadd231ps(T_reg(zmm_acc_idx_ + i * unroll_n_ + j), + T_reg(zmm_b_idx_ + (j % nb_zmm_b_)), + T_reg(i + zmm_a_idx_)); + + if (mayiuse(avx512_core)) { + if (i == 0) { + if (j % 3 == 0) { + prefetcht0(ptr[AO_ + + elt_size_ * (PREFETCHSIZEA_ + off_)]); + off_ += 16; + } + if (j == 1) + prefetcht0(ptr[BO_ + elt_size_ * (PREFETCHSIZEB_)]); + } + } else { + if ((um > nelt_per_vecreg_) && (j == un - 1)) { + (this->*aload)(T_reg(zmm_a_idx_ + i), + ptr[AO_ + + elt_size_ + * (um - addr_off_ + + nelt_per_vecreg_ + * i)]); + } + } + } + + (this->*bload)(T_reg(zmm_b_idx_ + (j % nb_zmm_b_)), + ptr[BO_ + - elt_size_ + * (addr_off_ - std::min(nb_zmm_b_, un) + - j)]); + } + + if (mayiuse(avx512_core) && (un < 2)) + prefetcht0(ptr[BO_ + elt_size_ * (PREFETCHSIZEB_)]); + + if (mayiuse(avx512_core)) { + for (i = un; i < 8; i += 4) { + prefetcht0(ptr[AO_ + elt_size_ * (PREFETCHSIZEA_ + off_)]); + off_ += 16; + } + } + + if (mayiuse(avx512_core) || (um <= nelt_per_vecreg_)) { + for (i = 0; i < std::max(um / nelt_per_vecreg_, 1); i++) { + (this->*aload)(T_reg(zmm_a_idx_ + i), + ptr[AO_ + + elt_size_ + * (um - addr_off_ + + nelt_per_vecreg_ * i)]); + } + } + + if (mayiuse(avx512_core)) { + lea(AO_, ptr[AO_ + um * elt_size_]); + lea(BO_, ptr[BO_ + un * elt_size_]); + } else { + sub(AO_, -um * elt_size_); + sub(BO_, -un * elt_size_); + } + sub(LL_, 1); + + jg(K_loop_remainder_label, T_NEAR); + } + + template + void loop(int um, int un, + void (Xbyak::CodeGenerator::*aload)( + const T_desta &, const T_srca &), + void (Xbyak::CodeGenerator::*bload)( + const T_destb &, const T_srcb &)) { + + int i, j, k, acc_idx; + Xbyak::Label end_K_loop_label, end_main_K_loop_label; + Xbyak::Label K_loop_with_prefetch_label, K_loop_with_prefetch_rem_label; + + Xbyak::Reg64 A_reg = (mayiuse(avx512_core)) ? AO_ + : ((um == unroll_m_) && (un == unroll_n_)) ? A_ + : AO_; + + if (mayiuse(avx512_core) || (unroll_m_ != um) || (unroll_n_ != un)) + mov(AO_, A_); + + if (!mayiuse(avx512_core)) { + + nb_zmm_a_ = unroll_m_reg_; + nb_zmm_b_ = 1; + zmm_a_idx_ = 0; + zmm_b_idx_ = zmm_a_idx_ + nb_zmm_a_; + + if (((um == 16) && (un == 4)) + || ((um <= nelt_per_vecreg_) && (un != 2))) { + nb_zmm_a_ = unroll_m_reg_ * 2; + zmm_b_idx_ + = zmm_a_idx_ + std::max(1, um / nelt_per_vecreg_) * 2; + } else { + zmm_b_idx_ = zmm_a_idx_ + unroll_m_reg_; + } + + if (un == 1) + nb_zmm_b_ = 2; + else + nb_zmm_b_ = 1; + } + + zmm_acc_idx_ = zmm_b_idx_ + nb_zmm_b_; + acc_idx = 0; + + if (!mayiuse(avx512_core)) { + j = zmm_b_idx_; + for (k = 0; k < nb_zmm_b_; k++) { + if (!mayiuse(avx512_core) && (un > 1)) { + acc_idx = next_acc(acc_idx, um, un); + vxorps(T_reg(zmm_acc_idx_ + acc_idx), + T_reg(zmm_acc_idx_ + acc_idx), + T_reg(zmm_acc_idx_ + acc_idx)); + acc_idx++; + } + (this->*bload)( + T_reg(j), ptr[BO_ - (addr_off_ - k) * elt_size_]); + j++; + } + } + + for (k = 0; k < nb_zmm_a_ / unroll_m_reg_; k++) { + if (mayiuse(avx512_core)) + j = zmm_a_idx_ + k * unroll_m_reg_; + else + j = zmm_a_idx_ + k * std::max(1, um / nelt_per_vecreg_); + + for (i = nelt_per_vecreg_; i <= std::max(um, nelt_per_vecreg_); + i += nelt_per_vecreg_) { + if (!mayiuse(avx512_core)) { + acc_idx = next_acc(acc_idx, um, un); + vxorps(T_reg(zmm_acc_idx_ + acc_idx), + T_reg(zmm_acc_idx_ + acc_idx), + T_reg(zmm_acc_idx_ + acc_idx)); + acc_idx++; + } + (this->*aload)(T_reg(j), + ptr[A_reg + + (um * k - addr_off_ + i - nelt_per_vecreg_) + * elt_size_]); + j++; + } + } + + if (mayiuse(avx512_core)) { + j = zmm_b_idx_; + for (k = 0; k < nb_zmm_b_; k++) { + if (!mayiuse(avx512_core) && (un > 1)) { + acc_idx = next_acc(acc_idx, um, un); + vxorps(T_reg(zmm_acc_idx_ + acc_idx), + T_reg(zmm_acc_idx_ + acc_idx), + T_reg(zmm_acc_idx_ + acc_idx)); + acc_idx++; + } + (this->*bload)( + T_reg(j), ptr[BO_ - (addr_off_ - k) * elt_size_]); + j++; + } + } + + if (!mayiuse(avx512_core)) { + + if (un > 1) { + if ((um == unroll_m_) + || ((um <= nelt_per_vecreg_) && (un == unroll_n_) + && (um > 1))) { + acc_idx = next_acc(acc_idx, um, un); + vxorps(T_reg(zmm_acc_idx_ + acc_idx), + T_reg(zmm_acc_idx_ + acc_idx), + T_reg(zmm_acc_idx_ + acc_idx)); + acc_idx++; + acc_idx = next_acc(acc_idx, um, un); + vxorps(T_reg(zmm_acc_idx_ + acc_idx), + T_reg(zmm_acc_idx_ + acc_idx), + T_reg(zmm_acc_idx_ + acc_idx)); + acc_idx++; + } + prefetcht0(ptr[CO1_ + elt_size_ * ((um - 1) % 16)]); + if ((un < unroll_n_) && (um == unroll_m_)) { + acc_idx = next_acc(acc_idx, um, un); + vxorps(T_reg(zmm_acc_idx_ + acc_idx), + T_reg(zmm_acc_idx_ + acc_idx), + T_reg(zmm_acc_idx_ + acc_idx)); + acc_idx++; + acc_idx = next_acc(acc_idx, um, un); + vxorps(T_reg(zmm_acc_idx_ + acc_idx), + T_reg(zmm_acc_idx_ + acc_idx), + T_reg(zmm_acc_idx_ + acc_idx)); + acc_idx++; + } + prefetcht0(ptr[CO1_ + LDC_ + elt_size_ * ((um - 1) % 16)]); + if (un == unroll_n_) { + if ((um == unroll_m_) + || ((um <= nelt_per_vecreg_) && (un == unroll_n_) + && (um > 1))) { + acc_idx = next_acc(acc_idx, um, un); + vxorps(T_reg(zmm_acc_idx_ + acc_idx), + T_reg(zmm_acc_idx_ + acc_idx), + T_reg(zmm_acc_idx_ + acc_idx)); + acc_idx++; + } + prefetcht0(ptr[CO2_ + elt_size_ * ((um - 1) % 16)]); + if ((um == unroll_m_) + || ((um <= nelt_per_vecreg_) && (un == unroll_n_) + && (um > 1))) { + acc_idx = next_acc(acc_idx, um, un); + vxorps(T_reg(zmm_acc_idx_ + acc_idx), + T_reg(zmm_acc_idx_ + acc_idx), + T_reg(zmm_acc_idx_ + acc_idx)); + acc_idx++; + } + prefetcht0(ptr[CO2_ + LDC_ + elt_size_ * ((um - 1) % 16)]); + } + + } else { + prefetcht0(ptr[CO1_ + ((um - 1) % 16) * elt_size_]); + if (um == unroll_m_) prefetcht0(ptr[CO1_ + 23 * elt_size_]); + } + + for (i = zmm_acc_idx_ + acc_idx; + i <= std::min(15, + zmm_acc_idx_ + + (std::max(1, um / nelt_per_vecreg_) - 1) + * unroll_n_ + + un - 1); + i++) + vxorps(T_reg(i), T_reg(i), T_reg(i)); + } + + if (!((mayiuse(avx512_core) || (unroll_m_ != um) || (unroll_n_ != un)))) + mov(AO_, A_); + + mov(LL_, KK_); + sar(LL_, unroll_k_bin_); + jle(end_main_K_loop_label, T_NEAR); + + if (mayiuse(avx512_core) + || (!mayiuse(avx512_core) && (un == unroll_n_) + && (um == unroll_m_))) { + sub(LL_, second_fetch_); + jle(K_loop_with_prefetch_label, T_NEAR); + } + + k_loop_body( + 0, um, un, aload, bload); + + if (mayiuse(avx512_core) + || (!mayiuse(avx512_core) && (un == unroll_n_) + && (um == unroll_m_))) { + L_aligned(K_loop_with_prefetch_label); + } + + if (mayiuse(avx512_core)) { + lea(CO2_, ptr[CO1_ + (nelt_per_vecreg_ - 1) * elt_size_]); + add(LL_, un); + jle(K_loop_with_prefetch_rem_label, T_NEAR); + } + + if (mayiuse(avx512_core) + || (!mayiuse(avx512_core) && (un == unroll_n_) + && (um == unroll_m_))) { + k_loop_body( + 1, um, un, aload, bload); + } + + if (mayiuse(avx512_core)) { + L_aligned(K_loop_with_prefetch_rem_label); + add(LL_, second_fetch_ - un); + jle(end_main_K_loop_label, T_NEAR); + + k_loop_body( + 0, um, un, aload, bload); + } + + L_aligned(end_main_K_loop_label); + + if (!mayiuse(avx512_core)) { + if ((un == unroll_n_) && ((um == 16) || (um == 8))) { + prefetcht2(ptr[AA_ - 16 * elt_size_]); + } + } + + mov(LL_, KK_); + and_(LL_, 3); + je(end_K_loop_label, T_NEAR); + + k_loop_remainder( + um, un, aload, bload); + + L_aligned(end_K_loop_label); + } + + template + void update(int um, int un, int sepload, bool is_beta_zero, + void (Xbyak::CodeGenerator::*load)(const Xbyak::Xmm &, + const Xbyak::Operand &, const Xbyak::Operand &), + void (Xbyak::CodeGenerator::*store)( + const Xbyak::Address &, const Xbyak::Xmm &), + void (Xbyak::CodeGenerator::*sload)( + const Xbyak::Xmm &, const T_src &)) { + + int i, j, offAA = 16; + Xbyak::Reg64 reg_C; + + if ((um < unroll_m_) && (um >= nelt_per_vecreg_)) + offAA = 32 - (un / 2) * 16; + + if (mayiuse(avx512_core)) + lea(CO2_, ptr[CO1_ + LDC_]); + else { + if ((um == nelt_per_vecreg_) && (un == unroll_n_)) { + prefetcht2(ptr[AA_ + elt_size_ * offAA]); + offAA += 16; + } + } + for (j = 0; j < un; j++) { + + if (mayiuse(avx512_core)) { + reg_C = (j == 0) ? CO1_ : CO2_; + if (j >= 2) { add(CO2_, LDC_); } + } else + reg_C = (j < 2) ? CO1_ : CO2_; + + // if beta == 1 load C_ and add to accumulator + if (!is_beta_zero) { + if (sepload) { + for (i = 0; i < std::max(um / nelt_per_vecreg_, 1); i++) { + if (!mayiuse(avx512_core) && (j % 2 == 1)) { + (this->*sload)(vec_reg_t(i), + ptr[reg_C + LDC_ + + elt_size_ * i + * nelt_per_vecreg_]); + } else { + (this->*sload)(vec_reg_t(i), + ptr[reg_C + + elt_size_ * i + * nelt_per_vecreg_]); + } + (this->*load)( + vec_reg_t(zmm_acc_idx_ + j + i * unroll_n_), + vec_reg_t(zmm_acc_idx_ + j + i * unroll_n_), + Xbyak::Xmm(i)); + } + } else { + for (i = 0; i < std::max(um / nelt_per_vecreg_, 1); i++) { + (this->*load)( + vec_reg_t(zmm_acc_idx_ + j + i * unroll_n_), + vec_reg_t(zmm_acc_idx_ + j + i * unroll_n_), + ptr[reg_C + elt_size_ * i * nelt_per_vecreg_]); + } + } + } + + if (!mayiuse(avx512_core)) { + if (j > 0) { + prefetcht2(ptr[AA_ + elt_size_ * offAA]); + offAA += 16; + } + } + + // store accumulated value in C_ + for (i = 0; i < std::max(um / nelt_per_vecreg_, 1); i++) { + if (!mayiuse(avx512_core) && (j % 2 == 1)) { + (this->*store)(ptr[reg_C + LDC_ + + elt_size_ * i * nelt_per_vecreg_], + vec_reg_t(zmm_acc_idx_ + j + i * unroll_n_)); + } else { + (this->*store)( + ptr[reg_C + elt_size_ * i * nelt_per_vecreg_], + vec_reg_t(zmm_acc_idx_ + j + i * unroll_n_)); + } + if (mayiuse(avx512_core)) { + vpxorq(vec_reg_t(zmm_acc_idx_ + j + i * unroll_n_), + vec_reg_t(zmm_acc_idx_ + j + i * unroll_n_), + vec_reg_t(zmm_acc_idx_ + j + i * unroll_n_)); + } + } + + if (!mayiuse(avx512_core)) { + if ((um == unroll_m_) && (un == 1)) { + prefetcht2(ptr[AA_ + elt_size_ * offAA]); + offAA += 16; + } + } + + if (!mayiuse(avx512_core)) { + if (j == std::min(1, un - 1)) { + if (j == 0) + add(CO1_, LDC_); + else + lea(CO1_, ptr[CO1_ + LDC_ * un]); + } + if (j == (un - 1)) { + if (j == 0) + add(CO2_, LDC_); + else + lea(CO2_, ptr[CO2_ + LDC_ * un]); + } + } + } + + if (mayiuse(avx512_core)) lea(CO1_, ptr[CO2_ + LDC_]); + + if (!mayiuse(avx512_core)) { + if ((um >= nelt_per_vecreg_) && (un < unroll_n_)) { + prefetcht2(ptr[AA_ + elt_size_ * offAA]); + offAA += 16; + } + } + } + +public: + jit_avx2_kernel_sgemm_kern(bool beta_zero); +}; +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif // CPU_X64_GEMM_F32_JIT_AVX2_KERNEL_SGEMM_KERN_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/f32/jit_avx512_common_gemm_f32.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/f32/jit_avx512_common_gemm_f32.hpp new file mode 100644 index 0000000000000000000000000000000000000000..a12033e668c70e9906787d73daa10f78cf3b8666 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/f32/jit_avx512_common_gemm_f32.hpp @@ -0,0 +1,48 @@ +/******************************************************************************* +* Copyright 2017-2021 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_GEMM_F32_JIT_AVX512_COMMON_GEMM_F32_HPP +#define CPU_X64_GEMM_F32_JIT_AVX512_COMMON_GEMM_F32_HPP + +#include "oneapi/dnnl/dnnl_types.h" + +#include "cpu/gemm/f32/gemm_utils_f32.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +dnnl_status_t jit_avx512_common_gemm_f32(int nthrs, const char *transa, + const char *transb, const dim_t *M, const dim_t *N, const dim_t *K, + const float *alpha, const float *A, const dim_t *lda, const float *B, + const dim_t *ldb, const float *beta, float *C, const dim_t *ldc, + const float *bias = nullptr); + +namespace avx512_common_gemm_f32 { + +dnnl_status_t sgemm_nocopy_driver(const char *transa, const char *transb, + dim_t m, dim_t n, dim_t k, const float *alpha, const float *a, + dim_t lda, const float *b, dim_t ldb, const float *beta, float *c, + dim_t ldc, const float *bias); +} + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif // CPU_X64_GEMM_F32_JIT_AVX512_COMMON_GEMM_F32_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/f32/jit_avx512_core_f32_copy_at_kern_autogen.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/f32/jit_avx512_core_f32_copy_at_kern_autogen.hpp new file mode 100644 index 0000000000000000000000000000000000000000..309125c607273476c03f77ce301272e0c0e7539f --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/f32/jit_avx512_core_f32_copy_at_kern_autogen.hpp @@ -0,0 +1,50 @@ +/******************************************************************************* +* Copyright 2019-2021 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_GEMM_F32_JIT_AVX512_CORE_F32_COPY_AT_KERN_AUTOGEN_HPP +#define CPU_X64_GEMM_F32_JIT_AVX512_CORE_F32_COPY_AT_KERN_AUTOGEN_HPP + +#ifndef _WIN32 +#define M rdi +#define N rsi +#define A rdx +#define LDA rcx +#define ALPHA r8 +#define B r9 + +#define I rax +#define A1 r10 +#define A2 r8 +#define LDA3 r11 + +#else +#define M rcx +#define N rdx +#define A r8 +#define LDA r9 +#define ALPHA rsi +#define B rdi +#define I rax +#define A1 rsi +#define A2 r10 +#define LDA3 r11 + +#define ARG_ALPHA 40 + stacksize + rsp +#define ARG_B 48 + stacksize + rsp + +#endif + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/f32/jit_avx512_core_gemm_smalln_tn_f32_kern.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/f32/jit_avx512_core_gemm_smalln_tn_f32_kern.hpp new file mode 100644 index 0000000000000000000000000000000000000000..3ca2ee6d5fa7f843b14388b4b1b2d4673d65dd4f --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/f32/jit_avx512_core_gemm_smalln_tn_f32_kern.hpp @@ -0,0 +1,43 @@ +/******************************************************************************* +* Copyright 2020 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_GEMM_F32_JIT_AVX512_CORE_GEMM_SMALLN_TN_F32_KERN_HPP +#define CPU_X64_GEMM_F32_JIT_AVX512_CORE_GEMM_SMALLN_TN_F32_KERN_HPP + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +template +struct gemm_info_t; + +template +dnnl_status_t jump_to_gemm_smalln_tn( + const gemm_info_t *arg); + +dnnl_status_t jit_avx512_core_gemm_smalln_tn_f32(const char *transa, + const char *transb, const dim_t *p_m, const dim_t *p_n, + const dim_t *p_k, const float *p_alpha, const float *A, + const dim_t *p_lda, const float *B, const dim_t *p_ldb, + const float *p_beta, float *C, const dim_t *p_ldc); + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif // CPU_X64_GEMM_F32_JIT_AVX512_CORE_GEMM_SMALLN_TN_F32_KERN_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/f32/jit_avx_gemm_f32.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/f32/jit_avx_gemm_f32.hpp new file mode 100644 index 0000000000000000000000000000000000000000..0041b75b6d411f2ccf6e7b13b9e3695a8b224223 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/f32/jit_avx_gemm_f32.hpp @@ -0,0 +1,48 @@ +/******************************************************************************* +* Copyright 2016-2021 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_GEMM_F32_JIT_AVX_GEMM_F32_HPP +#define CPU_X64_GEMM_F32_JIT_AVX_GEMM_F32_HPP + +#include "oneapi/dnnl/dnnl_types.h" + +#include "cpu/gemm/f32/gemm_utils_f32.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +dnnl_status_t jit_avx_gemm_f32(int nthrs, const char *transa, + const char *transb, const dim_t *M, const dim_t *N, const dim_t *K, + const float *alpha, const float *A, const dim_t *lda, const float *B, + const dim_t *ldb, const float *beta, float *C, const dim_t *ldc, + const float *bias = nullptr); + +namespace avx_gemm_f32 { + +dnnl_status_t sgemm_nocopy_driver(const char *transa, const char *transb, + dim_t m, dim_t n, dim_t k, const float *alpha, const float *a, + dim_t lda, const float *b, dim_t ldb, const float *beta, float *c, + dim_t ldc, const float *bias); +} + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif // CPU_X64_GEMM_F32_JIT_AVX_GEMM_F32_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/f32/jit_avx_gemv_t_f32_kern.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/f32/jit_avx_gemv_t_f32_kern.hpp new file mode 100644 index 0000000000000000000000000000000000000000..1ed21b708ff9d10d579d47586e60795dc2ce0fef --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/f32/jit_avx_gemv_t_f32_kern.hpp @@ -0,0 +1,70 @@ +/******************************************************************************* +* Copyright 2019-2021 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_GEMM_F32_JIT_AVX_GEMV_T_F32_KERN_HPP +#define CPU_X64_GEMM_F32_JIT_AVX_GEMV_T_F32_KERN_HPP + +#include "cpu/x64/jit_generator.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +class jit_avx_gemv_t_f32_kern : public jit_generator { +public: + jit_avx_gemv_t_f32_kern(void); + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx_gemv_t_f32_kern); + +protected: + bool is_avx2_; + + void v_load(const Xbyak::Xmm &dst, const Xbyak::Address &src, int nelems); + void v_store(const Xbyak::Address &dst, const Xbyak::Xmm &src, int nelems); + + void dot_product(const Xbyak::Xmm &dst, const Xbyak::Xmm &src1, + const Xbyak::Xmm &src2); + void innerloop(int unroll_m, int unroll_n); + void outerloop(int unroll_x, int unroll_y, Xbyak::Label *&outerloop_label); + + void generate() override ATTRIBUTE_OPTIMIZE; + +private: + static const int M_UNROLL_ = 16; + static const int N_UNROLL_ = 4; + + static const int size_ = 4; + + static const int offset_a_ = 128, offset_x_ = 128; + + // Integer register assignments + Xbyak::Reg64 M_, N_, A_, LDA_, X_, INCY_, Y_, ALPHA_, I_, J_; + Xbyak::Reg64 AO_, XO_, YO_, YO2_; + + // Vector register assignments + Xbyak::Ymm scratch_, alpha_, a_regs_[M_UNROLL_ >> 3][N_UNROLL_]; + Xbyak::Ymm x_regs_[M_UNROLL_ >> 3], y_regs_[N_UNROLL_], acc_[N_UNROLL_]; + + // Stack variable assignments + Xbyak::Address arg_lda_, arg_x_, arg_incx_, arg_y_, arg_incy_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif // CPU_X64_GEMM_F32_JIT_AVX_GEMV_T_F32_KERN_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/f32/jit_avx_kernel_b0_sgemm_kern_autogen.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/f32/jit_avx_kernel_b0_sgemm_kern_autogen.hpp new file mode 100644 index 0000000000000000000000000000000000000000..41d0e651e1709ff5baf52a94ef6b9eb8813234f8 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/f32/jit_avx_kernel_b0_sgemm_kern_autogen.hpp @@ -0,0 +1,67 @@ +/******************************************************************************* +* Copyright 2019-2021 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_GEMM_F32_JIT_AVX_KERNEL_B0_SGEMM_KERN_AUTOGEN_HPP +#define CPU_X64_GEMM_F32_JIT_AVX_KERNEL_B0_SGEMM_KERN_AUTOGEN_HPP + +#ifndef _WIN32 + +#define M rdi +#define N rsi +#define K rdx +#define A r8 +#define B r9 +#define C rcx +#define LDC r10 + +#define AA r15 +#define I r11 +#define J r12 +#define H rax +#define AO rbx +#define BO rbp +#define CO1 r13 +#define CO2 r14 + +#define OLD_C (8 + stacksize + rsp) +#define OLD_LDC (16 + stacksize + rsp) + +#else + +#define M rcx +#define N rdx +#define K r8 +#define A rdi +#define B rsi +#define C r9 +#define LDC r10 +#define AA r15 +#define I r11 +#define J r12 +#define H rax +#define AO rbx +#define BO rbp +#define CO1 r13 +#define CO2 r14 + +#define OLD_A 40 + stacksize + rsp +#define OLD_B 48 + stacksize + rsp +#define OLD_C 56 + stacksize + rsp +#define OLD_LDC 64 + stacksize + rsp + +#endif + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/f32/jit_avx_kernel_sgemm_kern_autogen.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/f32/jit_avx_kernel_sgemm_kern_autogen.hpp new file mode 100644 index 0000000000000000000000000000000000000000..1866a42b12a82c2309d2ec4ca948c03177a6f822 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/f32/jit_avx_kernel_sgemm_kern_autogen.hpp @@ -0,0 +1,66 @@ +/******************************************************************************* +* Copyright 2021 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_GEMM_F32_JIT_AVX_KERNEL_SGEMM_KERN_AUTOGEN_HPP +#define CPU_X64_GEMM_F32_JIT_AVX_KERNEL_SGEMM_KERN_AUTOGEN_HPP +#ifndef _WIN32 + +#define M rdi +#define N rsi +#define K rdx +#define A r8 +#define B r9 +#define C rcx +#define LDC r10 + +#define AA r15 +#define I r11 +#define J r12 +#define H rax +#define AO rbx +#define BO rbp +#define CO1 r13 +#define CO2 r14 + +#define OLD_C (8 + stacksize + rsp) +#define OLD_LDC (16 + stacksize + rsp) + +#else + +#define M rcx +#define N rdx +#define K r8 +#define A rdi +#define B rsi +#define C r9 +#define LDC r10 +#define AA r15 +#define I r11 +#define J r12 +#define H rax +#define AO rbx +#define BO rbp +#define CO1 r13 +#define CO2 r14 + +#define OLD_A 40 + stacksize + rsp +#define OLD_B 48 + stacksize + rsp +#define OLD_C 56 + stacksize + rsp +#define OLD_LDC 64 + stacksize + rsp + +#endif + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/f32/jit_sse41_gemv_n_f32_kern.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/f32/jit_sse41_gemv_n_f32_kern.hpp new file mode 100644 index 0000000000000000000000000000000000000000..89886aed9395d98eeff711dad4351280d84dc8be --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/f32/jit_sse41_gemv_n_f32_kern.hpp @@ -0,0 +1,102 @@ +/******************************************************************************* +* Copyright 2021 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_GEMM_F32_JIT_SSE41_GEMV_N_F32_KERN_HPP +#define CPU_X64_GEMM_F32_JIT_SSE41_GEMV_N_F32_KERN_HPP + +#include "cpu/x64/jit_generator.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +class jit_sse41_gemv_n_f32_kern : public jit_generator { +public: + jit_sse41_gemv_n_f32_kern(); + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_sse41_gemv_n_f32_kern); + +protected: + bool has_avx512_; + bool has_avx2_; + bool has_avx_; + bool has_sse41_; + + int unroll_m_, unroll_n_; + + int v_nelems_; // Max number of elements in a vector register. + + bool fetch_; + void prefetch_a(const Xbyak::Address &src) { + if (fetch_) prefetcht0(src); + } + void prefetch_x(const Xbyak::Address &src) { + if (fetch_) prefetcht0(src); + } + void prefetch_y(const Xbyak::Address &src) { + if (fetch_) prefetcht0(src); + } + + void v_load(const Xbyak::Xmm &dst, const Xbyak::Address &src, int nelems); + void v_store(const Xbyak::Address &dst, const Xbyak::Xmm &src, int nelems); + void dot_product(const Xbyak::Xmm &dst, const Xbyak::Xmm &src1, + const Xbyak::Xmm &src2); + + void kernel_loop(int unroll_m, int unroll_n, bool fetch, bool last); + void innerloop(int unroll_m, int unroll_n); + void outerloop(int unroll_x, int unroll_y, + Xbyak::Label *&cur_outerloop_label, + Xbyak::Label *&outerloop_end_label); + + void generate() override ATTRIBUTE_OPTIMIZE; + +private: + static const int max_um_vecs_ = 16; + static const int max_unroll_n_ = 8; + + static const int size_ = 4; + + static const int offset_a_ = 32; + static const int offset_x_ = 32; + static const int offset_y_ = 32; + + // Prefetch configuration + static const int prefetch_size_a_ = 16; + static const int prefetch_size_x_ = 16; + static const int prefetch_size_y_ = 32; + + // Integer register assignments + Xbyak::Reg64 M_, N_, A_, LDA_, X_, INCX_, Y_, ALPHA_; + Xbyak::Reg64 A1_, A2_, Y1_, LDA3_, I_; + + // Vector register assignments + Xbyak::Xmm scratch_, alpha_; + Xbyak::Xmm a_, x_[max_unroll_n_], y_[max_um_vecs_]; + Xbyak::Xmm acc_[max_um_vecs_]; + + // Kind of vector register (Zmm, Ymm, Xmm) + Xbyak::Operand::Kind kind_; + + // Stack variable assignments + Xbyak::Address arg_lda_, arg_x_, arg_incx_, arg_y_, arg_incy_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif // CPU_X64_GEMM_F32_JIT_SSE41_GEMV_N_F32_KERN_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/f32/jit_sse41_gemv_t_f32_kern.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/f32/jit_sse41_gemv_t_f32_kern.hpp new file mode 100644 index 0000000000000000000000000000000000000000..8a32fb4beff7666a544674004523be7b6bf232b9 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/f32/jit_sse41_gemv_t_f32_kern.hpp @@ -0,0 +1,68 @@ +/******************************************************************************* +* Copyright 2019-2021 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_GEMM_F32_JIT_SSE41_GEMV_T_F32_KERN_HPP +#define CPU_X64_GEMM_F32_JIT_SSE41_GEMV_T_F32_KERN_HPP + +#include "cpu/x64/jit_generator.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +class jit_sse41_gemv_t_f32_kern : public jit_generator { +public: + jit_sse41_gemv_t_f32_kern(void); + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_sse41_gemv_t_f32_kern); + +protected: + void v_load(const Xbyak::Xmm &dst, const Xbyak::Address &src, int nelems); + void v_store(const Xbyak::Address &dst, const Xbyak::Xmm &src, int nelems); + + void dot_product(const Xbyak::Xmm &dst, const Xbyak::Xmm &src1, + const Xbyak::Xmm &src2); + void innerloop(int unroll_m, int unroll_n); + void outerloop(int unroll_x, int unroll_y, Xbyak::Label *&outerloop_label); + + void generate() override ATTRIBUTE_OPTIMIZE; + +private: + static const int M_UNROLL_ = 8; + static const int N_UNROLL_ = 4; + + static const int size_ = 4; + + static const int offset_a_ = 128, offset_x_ = 128; + + // Integer register assignments + Xbyak::Reg64 M_, N_, A_, LDA_, X_, INCY_, Y_, ALPHA_, I_, J_; + Xbyak::Reg64 AO_, XO_, YO_, YO2_; + + // Vector register assignments + Xbyak::Xmm scratch_, alpha_, a_regs_[M_UNROLL_ >> 2][N_UNROLL_]; + Xbyak::Xmm x_regs_[M_UNROLL_ >> 2], y_regs_[N_UNROLL_], acc_[N_UNROLL_]; + + // Stack variable assignments + Xbyak::Address arg_lda_, arg_x_, arg_incx_, arg_y_, arg_incy_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif // CPU_X64_GEMM_F32_JIT_SSE41_GEMV_T_F32_KERN_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/gemm_driver.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/gemm_driver.hpp new file mode 100644 index 0000000000000000000000000000000000000000..650d1775a01047b4e9d5b1eec9a24fb1357327a1 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/gemm_driver.hpp @@ -0,0 +1,52 @@ +/******************************************************************************* +* Copyright 2018-2020 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_GEMM_GEMM_DRIVER_HPP +#define CPU_X64_GEMM_GEMM_DRIVER_HPP + +#include "oneapi/dnnl/dnnl_types.h" + +#include "common/c_types_map.hpp" + +#include "cpu/x64/gemm/gemm_info.hpp" +#include "cpu/x64/gemm/gemm_pack_storage.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +template +dnnl_status_t gemm_driver(const char *transA, const char *transB, + const char *offsetC, const dim_t *m, const dim_t *n, const dim_t *k, + const float *alpha, const a_type *a, const dim_t *lda, const a_type *oa, + const b_type *b, const dim_t *ldb, const b_type *ob, const float *beta, + c_type *c, const dim_t *ldc, const c_type *oc, + const bool force_jit_nocopy_gemm, pack_type packing = pack_type::none, + gemm_pack_storage_t *pack_dst = NULL, bool measure_only = false); + +void prep_ref_gemm_s8u8s32_pack( + bool do_a, dim_t rows, dim_t cols, gemm_pack_storage_t *pack_dst); + +dnnl_status_t ref_gemm_s8u8s32_pack(const void *src, dim_t ld_src, dim_t rows, + dim_t cols, int trans, gemm_pack_storage_t *dst_pack); + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif // CPU_X64_GEMM_GEMM_DRIVER_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/gemm_info.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/gemm_info.hpp new file mode 100644 index 0000000000000000000000000000000000000000..2f12693d5048c9ea581c7c47a05d0c600b18d151 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/gemm_info.hpp @@ -0,0 +1,229 @@ +/******************************************************************************* +* Copyright 2019-2020 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_GEMM_GEMM_INFO_HPP +#define CPU_X64_GEMM_GEMM_INFO_HPP + +#include +#include + +#include "common/c_types_map.hpp" + +#include "cpu/x64/gemm/gemm_pack_storage.hpp" +#include "cpu/x64/gemm/gemm_threading.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +enum class pack_type { none, pack_a, pack_b }; + +enum class offset_type { + none, + fixed, + column, + row, +}; + +// Indices for kernel arrays. TODO Is it okay to place this here? +enum { no_sum = 0, do_sum = 1 }; +enum { no_trans = 0, do_trans = 1, packed = 2 }; +enum { no_beta0 = 0, do_beta0 = 1 }; +enum { no_alpha1 = 0, do_alpha1 = 1 }; + +template +struct gemm_info_t { + + // Interface arguments. + int transa, transb; + offset_type offsetc; + dim_t m, n, k; + dim_t lda, ldb, ldc; + const a_t *a; + const b_t *b; + c_t *c; + float alpha, beta; + + int32_t ao; + int32_t bo; + const c_t *co; + + pack_type packing; + gemm_pack_storage_t *pack_dst; + bool measure_only; + std::shared_ptr a_packed, b_packed; + + // Kernel parameters. + dim_t um, un, uk, bm, bn, bk; + dim_t bn_small_k, bk_traditional, blocking_small_k; + + // Gemv parameters + int swap; + + using copy_a_fptr_t = void (*)(const dim_t *m, const dim_t *n, + const a_t *src, const dim_t *ldsrc, const float *alpha, a_t *dst, + const dim_t *dummy1, const dim_t *dummy2, c_t *row_col_sum); + + using copy_b_fptr_t = void (*)(const dim_t *m, const dim_t *n, + const b_t *src, const dim_t *ldsrc, const float *alpha, b_t *dst, + const dim_t *dummy1, const dim_t *dummy2, c_t *row_col_sum); + + using gemm_fptr_t = void (*)(const dim_t *, const dim_t *, const dim_t *, + const float *, const a_t *, const b_t *, c_t *, const dim_t, + const c_t *, const c_t *); + + using gemv_fptr_t = void (*)(const dim_t *, const dim_t *, const float *, + const a_t *, const dim_t *, const b_t *, const dim_t *, c_t *, + const dim_t *); + + using gemv_s8s8s32_fptr_t + = void (*)(const dim_t, const dim_t, const float, const int8_t *, + const dim_t, const int8_t *, const float, int32_t *); + + using gemv_s8u8s32_fptr_t + = void (*)(const dim_t, const dim_t, const float, const int8_t *, + const dim_t, const uint8_t *, const float, int32_t *); + + using gemv_u8s8s32_fptr_t + = void (*)(const dim_t, const dim_t, const float, const uint8_t *, + const dim_t, const int8_t *, const float, int32_t *); + + // gemm kernels + copy_a_fptr_t copyA = nullptr; + copy_b_fptr_t copyB = nullptr; + gemm_fptr_t kernel[2][2][2] = {{{nullptr}}}; + + // gemv kernels + gemv_fptr_t gemv_kernel[2] = {nullptr}; + gemv_s8s8s32_fptr_t gemv_s8s8s32_kernel = nullptr; + gemv_s8u8s32_fptr_t gemv_s8u8s32_kernel = nullptr; + gemv_u8s8s32_fptr_t gemv_u8s8s32_kernel = nullptr; + + // copyA[trans][sum] + static copy_a_fptr_t copy_a_kern[2][2]; + + // copyB[trans][sum] + static copy_b_fptr_t copy_b_kern[2][2]; + + // kern[beta0][alpha1][col_off][row_off] + static gemm_fptr_t kern[2][2][2][2]; + + // gemv_kern[trans] + static gemv_fptr_t gemv_kern[2]; + + static gemv_s8s8s32_fptr_t gemv_s8s8s32_kern; + static gemv_s8u8s32_fptr_t gemv_s8u8s32_kern; + static gemv_u8s8s32_fptr_t gemv_u8s8s32_kern; + + template + static void copy_a_sum_ref(const dim_t *p_k, const dim_t *p_m, + const a_t *src, const dim_t *p_ld, const float *p_alpha, a_t *dst, + const dim_t *dummy1, const dim_t *dummy2, c_t *a_row_sum) { + + copy_a_kern[is_trans][no_sum]( + p_k, p_m, src, p_ld, p_alpha, dst, dummy1, dummy2, a_row_sum); + + dim_t k = *p_k; + dim_t m = *p_m; + dim_t ld = *p_ld; + + // Calculate op(A) row sum. + if (!is_trans) { + PRAGMA_OMP_SIMD() + for (dim_t i = 0; i < m; i++) + a_row_sum[i] = 0; + + for (dim_t j = 0; j < k; j++) { + PRAGMA_OMP_SIMD() + for (dim_t i = 0; i < m; i++) { + a_row_sum[i] += src[i + j * ld]; + } + } + } else { + for (dim_t i = 0; i < m; i++) { + c_t acc = 0; + + PRAGMA_OMP_SIMD(reduction(+ : acc)) + for (dim_t j = 0; j < k; j++) { + acc += src[j + i * ld]; + } + + a_row_sum[i] = acc; + } + } + } + + template + static void copy_b_sum_ref(const dim_t *p_k, const dim_t *p_n, + const b_t *src, const dim_t *p_ld, const float *alpha, b_t *dst, + const dim_t *dummy1, const dim_t *dummy2, c_t *b_col_sum) { + + copy_b_kern[is_trans][no_sum]( + p_k, p_n, src, p_ld, alpha, dst, dummy1, dummy2, b_col_sum); + + dim_t k = *p_k; + dim_t n = *p_n; + dim_t ld = *p_ld; + + // Calculate op(B) column sum. + if (!is_trans) { + for (dim_t j = 0; j < n; j++) { + c_t acc = 0; + + PRAGMA_OMP_SIMD(reduction(+ : acc)) + for (dim_t i = 0; i < k; i++) + acc += src[i + j * ld]; + + b_col_sum[j] = acc; + } + } else { + PRAGMA_OMP_SIMD() + for (dim_t j = 0; j < n; j++) + b_col_sum[j] = 0; + + for (dim_t i = 0; i < k; i++) { + PRAGMA_OMP_SIMD() + for (dim_t j = 0; j < n; j++) + b_col_sum[j] += src[j + i * ld]; + } + } + } + + bool force_nocopy; + + gemm_info_t(const char *transA, const char *transB, const char *offsetC, + const dim_t *m, const dim_t *n, const dim_t *k, const float *alpha, + const a_t *a, const dim_t *lda, const a_t *oa, const b_t *b, + const dim_t *ldb, const b_t *ob, const float *beta, c_t *c, + const dim_t *ldc, const c_t *oc, bool force_nocopy, + pack_type packing, gemm_pack_storage_t *pack_dst, + bool measure_only); + + bool hasKernels(void); + + void update_blocking(const gemm_threading_t &thread_info); + +private: + void jit_init(void); +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif // CPU_X64_GEMM_GEMM_INFO_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/gemm_pack.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/gemm_pack.hpp new file mode 100644 index 0000000000000000000000000000000000000000..3d801c4deeb43eef63fd7230d25fec24cf8e2acc --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/gemm_pack.hpp @@ -0,0 +1,94 @@ +/******************************************************************************* +* Copyright 2019-2020 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_GEMM_GEMM_PACK_HPP +#define CPU_X64_GEMM_GEMM_PACK_HPP + +#include "oneapi/dnnl/dnnl_config.h" +#include "oneapi/dnnl/dnnl_types.h" + +#include "common/bfloat16.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +bool pack_sgemm_supported(); +bool pack_gemm_bf16bf16f32_supported(); + +dnnl_status_t sgemm_pack_get_size(const char *identifier, const char *transa, + const char *transb, const dim_t *M, const dim_t *N, const dim_t *K, + const dim_t *lda, const dim_t *ldb, size_t *size, bool *pack); + +dnnl_status_t gemm_bf16bf16f32_pack_get_size(const char *identifier, + const char *transa, const char *transb, const dim_t *M, const dim_t *N, + const dim_t *K, const dim_t *lda, const dim_t *ldb, size_t *size, + bool *pack); + +dnnl_status_t gemm_s8u8s32_pack_get_size(const char *identifier, + const char *transa, const char *transb, const dim_t *M, const dim_t *N, + const dim_t *K, const dim_t *lda, const dim_t *ldb, size_t *size, + bool *pack); + +dnnl_status_t gemm_s8s8s32_pack_get_size(const char *identifier, + const char *transa, const char *transb, const dim_t *M, const dim_t *N, + const dim_t *K, const dim_t *lda, const dim_t *ldb, size_t *size, + bool *pack); + +dnnl_status_t sgemm_pack(const char *identifier, const char *transa, + const char *transb, const dim_t *M, const dim_t *N, const dim_t *K, + const dim_t *lda, const dim_t *ldb, const float *src, float *dst); + +dnnl_status_t gemm_bf16bf16f32_pack(const char *identifier, const char *transa, + const char *transb, const dim_t *M, const dim_t *N, const dim_t *K, + const dim_t *lda, const dim_t *ldb, const bfloat16_t *src, + bfloat16_t *dst); + +dnnl_status_t gemm_s8u8s32_pack(const char *identifier, const char *transa, + const char *transb, const dim_t *M, const dim_t *N, const dim_t *K, + const dim_t *lda, const dim_t *ldb, const void *src, void *dst); + +dnnl_status_t gemm_s8s8s32_pack(const char *identifier, const char *transa, + const char *transb, const dim_t *M, const dim_t *N, const dim_t *K, + const dim_t *lda, const dim_t *ldb, const void *src, void *dst); + +dnnl_status_t sgemm_compute(const char *transa, const char *transb, + const dim_t *M, const dim_t *N, const dim_t *K, const float *A, + const dim_t *lda, const float *B, const dim_t *ldb, const float *beta, + float *C, const dim_t *ldc); + +dnnl_status_t gemm_bf16bf16f32_compute(const char *transa, const char *transb, + const dim_t *M, const dim_t *N, const dim_t *K, const bfloat16_t *A, + const dim_t *lda, const bfloat16_t *B, const dim_t *ldb, + const float *beta, float *C, const dim_t *ldc); + +dnnl_status_t gemm_s8u8s32_compute(const char *transa, const char *transb, + const char *offsetc, const dim_t *M, const dim_t *N, const dim_t *K, + const int8_t *A, const dim_t *lda, const uint8_t *B, const dim_t *ldb, + const float *beta, int32_t *C, const dim_t *ldc, const int32_t *co); + +dnnl_status_t gemm_s8s8s32_compute(const char *transa, const char *transb, + const char *offsetc, const dim_t *M, const dim_t *N, const dim_t *K, + const int8_t *A, const dim_t *lda, const int8_t *B, const dim_t *ldb, + const float *beta, int32_t *C, const dim_t *ldc, const int32_t *co); + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif // CPU_X64_GEMM_GEMM_PACK_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/gemm_pack_storage.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/gemm_pack_storage.hpp new file mode 100644 index 0000000000000000000000000000000000000000..88ad3ab1ba765571144730f908595ba25ff5db33 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/gemm_pack_storage.hpp @@ -0,0 +1,391 @@ +/******************************************************************************* +* Copyright 2019-2021 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_GEMM_GEMM_PACK_STORAGE_HPP +#define CPU_X64_GEMM_GEMM_PACK_STORAGE_HPP + +#include + +#include "common/dnnl_thread.hpp" +#include "common/utils.hpp" + +#include "cpu/x64/gemm/gemm_threading.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +enum struct matrix_id { a, b }; + +struct gemm_pack_storage_t { + gemm_threading_t &threading() { return header->threading; } + matrix_id &which() { return header->which; } + bool &has_row_sums() { return header->has_row_sums; } + bool &has_col_sums() { return header->has_col_sums; } + + const gemm_threading_t &threading() const { return header->threading; } + const matrix_id &which() const { return header->which; } + const bool &has_row_sums() const { return header->has_row_sums; } + const bool &has_col_sums() const { return header->has_col_sums; } + + size_t size() const { return header->size; } + void *get() const { return static_cast(base); } + void set(void *data) { + base = static_cast(data); + header = static_cast(data); + } + + bool single_nocopy() const { + return (threading().copy == copy_type::no_copy); + } + + int nthr() const { return single_nocopy() ? 1 : threading().nthrs(); } + + int nslice() const { + return (which() == matrix_id::a) + ? threading().nthrs_m * threading().nthrs_k + : threading().nthrs_n * threading().nthrs_k; + } + + template + gemm_pack_storage_t(data_type *data_, bool header_set_ = true) + : base(nullptr), header_set(header_set_) { + reset((void *)data_); + } + + gemm_pack_storage_t() + : base(nullptr) + , header(nullptr) + , matrix_header(nullptr) + , sums_header(nullptr) + , header_set(true) {} + + std::tuple thread_slice_info(int ithr) const { + assert(ithr < nthr()); + + bool is_a = (which() == matrix_id::a); + auto nthr_inner = is_a ? threading().nthrs_m : threading().nthrs_n; + + auto ithr_i = ithr % threading().nthrs_m; + auto ithr_jk = ithr / threading().nthrs_m; + auto ithr_j = ithr_jk % threading().nthrs_n; + auto ithr_k = ithr_jk / threading().nthrs_n; + + auto ithr_inner = is_a ? ithr_i : ithr_j; + auto ithr_outer = ithr_k; + auto ithr_slice = is_a ? ithr_j : ithr_i; + + auto id = ithr_outer * nthr_inner + ithr_inner; + + return std::make_tuple(id, ithr_slice); + } + + int thread_to_slice(int ithr) const { + return std::get<0>(thread_slice_info(ithr)); + } + + bool is_first_thread_in_slice(int ithr) const { + return (std::get<1>(thread_slice_info(ithr)) == 0); + } + + template + data_type *row_sums(int ithr, dim_t r0, dim_t cblock) const { + if (!has_row_sums()) return NULL; + auto id = thread_to_slice(ithr); + return get_block(sums_header->slice[id], r0, cblock); + } + + template + data_type *col_sums(int ithr, dim_t rblock, dim_t c0) const { + if (!has_col_sums()) return NULL; + auto id = thread_to_slice(ithr); + return get_block(sums_header->slice[id], rblock, c0); + } + + template + data_type *matrix(int ithr, dim_t r0, dim_t c0) const { + auto id = thread_to_slice(ithr); + return get_block(matrix_header->slice[id], r0, c0); + } + + template + data_type *matrix(int ithr) const { + assert(!matrix_header->slice[thread_to_slice(ithr)].packed); + return matrix(ithr, 0, 0); + } + + template + data_type *matrix() const { + assert(single_nocopy()); + return matrix(0); + } + + bool get_nocopy(int ithr, int &trans, dim_t &ld, dim_t &td) const { + auto id = thread_to_slice(ithr); + return matrix_header->slice[id].get_nocopy(trans, ld, td); + } + + bool get_nocopy(int &trans, dim_t &ld, dim_t &td) const { + if (!single_nocopy()) return false; + return get_nocopy(0, trans, ld, td); + } + + void get_blocking(int ithr, dim_t &block_r, dim_t &block_c) const { + auto id = thread_to_slice(ithr); + matrix_header->slice[id].get_blocking(block_r, block_c); + } + + void set_blocking( + int ithr, dim_t rows, dim_t cols, dim_t block_r, dim_t block_c) { + + auto id = thread_to_slice(ithr); + auto nblk_r = (block_r == 0) ? 0 : utils::div_up(rows, block_r); + auto nblk_c = (block_c == 0) ? 0 : utils::div_up(cols, block_c); + + matrix_header->slice[id].set_blocking(nblk_r, nblk_c, block_r, block_c); + + if (has_row_sums()) + sums_header->slice[id].set_blocking(nblk_r, nblk_c, block_r, 1); + else + sums_header->slice[id].set_blocking(nblk_r, nblk_c, 1, block_c); + } + + void set_nocopy(int ithr, int trans, dim_t ld, dim_t td) { + auto id = thread_to_slice(ithr); + matrix_header->slice[id].set_nocopy(trans, ld, td); + } + + void setup(int max_nthr, bool has_row_sums = false, + bool has_col_sums = false) { + + assert(!(has_row_sums && has_col_sums)); + + auto sz_mh = matrix_header_size(max_nthr); + auto sz_h = header_size(); + + header->has_row_sums = has_row_sums; + header->has_col_sums = has_col_sums; + header->off_matrix = sz_h; + header->off_sums = sz_h + sz_mh; + total_header_size = sz_h + sz_mh * 2; + + header->size = 0; + + header_set = true; + + reset(get()); + + for (int id = 0; id < max_nthr; id++) { + matrix_header->slice[id].set_blocking(0, 0, 0, 0); + sums_header->slice[id].set_blocking(0, 0, 0, 0); + } + } + + template + void finalize() { + assert(total_header_size > 0); + size_t cur_off = total_header_size; + + matrix_header->finalize(cur_off, nslice()); + if (has_row_sums() || has_col_sums()) + sums_header->finalize(cur_off, nslice()); + + header->size = cur_off; + + /* Compute kernels overrun to preload data. */ + header->size += align_data; + } + +protected: + char *base; + + struct header_t { + matrix_id which; + bool has_row_sums; + bool has_col_sums; + size_t off_matrix, off_sums; + size_t size; + gemm_threading_t threading; /* if packed */ + } * header; + + struct slice_header_t { + bool packed; + int trans; + int nblk_r, nblk_c; + dim_t block_r, block_c; + size_t off_data; + + template + size_t block_size() const { + return utils::rnd_up( + block_r * block_c * sizeof(data_type), align_data); + } + + template + size_t block_offset(dim_t r0, dim_t c0, bool col_major) const { + assert((r0 % block_r) == 0); + assert((c0 % block_c) == 0); + + auto rb = r0 / block_r; + auto cb = c0 / block_c; + auto mb = col_major ? rb + cb * nblk_r : cb + rb * nblk_c; + + return block_size() * mb; + } + + template + size_t size() const { + return block_size() * nblk_r * nblk_c; + } + + void set_blocking( + int nblk_r_, int nblk_c_, dim_t block_r_, dim_t block_c_) { + packed = true; + nblk_r = nblk_r_; + nblk_c = nblk_c_; + block_r = block_r_; + block_c = block_c_; + } + + void set_nocopy(int trans_, dim_t ld, dim_t td) { + packed = false; + trans = trans_; + block_r = ld; + block_c = td; + nblk_r = 1; + nblk_c = 1; + } + + void get_blocking(dim_t &block_r_, dim_t &block_c_) const { + block_r_ = block_r; + block_c_ = block_c; + } + + bool get_nocopy(int &trans_, dim_t &ld, dim_t &td) const { + if (!packed) { + trans_ = trans; + ld = block_r; + td = block_c; + } + return !packed; + } + + template + void finalize(size_t &cur_off) { + cur_off = utils::rnd_up(cur_off, align_data); + off_data = cur_off; + cur_off += size(); + } + }; + + struct matrix_header_t { + dim_t ld; /* if not packed */ + slice_header_t slice[1]; /* array of size nthr, if packed */ + + template + void finalize(size_t &cur_off, int nslices) { +#if DNNL_CPU_THREADING_RUNTIME == DNNL_RUNTIME_THREADPOOL + // This, I hope, is a temporary workaround... + // The reason for this special case is that in case of threadpool + // threading this function may be called to estimate the amount of + // memory needed when no threading information is actually + // available. Hence, it needs to provide an upper bound. + size_t max_off = cur_off; + for (int id = 0; id < nslices; id++) { + slice[id].finalize(cur_off); + if (id == 0) { + // Assume that slice[0] is the largest one. + size_t slice0_size = cur_off - max_off; + max_off += slice0_size * dnnl_get_max_threads(); + } + } + if (!threadpool_utils::get_active_threadpool() && nslices) + // The std::max is a paranoid check for the case when slice[0] + // is not actually the largest one. Probably a crash will + // happen anyways... + cur_off = std::max(cur_off, max_off); +#else + for (int id = 0; id < nslices; id++) + slice[id].finalize(cur_off); +#endif + } + } * matrix_header, *sums_header; + + size_t total_header_size = 0; + + static constexpr auto align_headers = 0x20; + static constexpr auto align_data = 0x1000; + + static size_t header_size() { + return utils::rnd_up(sizeof(header_t), align_headers); + } + + static size_t matrix_header_size(int max_nthr) { + auto sz = sizeof(matrix_header_t) + + sizeof(slice_header_t) * (max_nthr - 1); + + return utils::rnd_up(sz, align_headers); + } + + template + data_type *get_block( + const slice_header_t &slice, dim_t r0, dim_t c0) const { + return reinterpret_cast(base + slice.off_data + + slice.block_offset(r0, c0, col_major())); + } + + bool col_major() const { return (which() == matrix_id::a); } + + void reset(void *data) { + set(data); + + if (!header_set) return; + + matrix_header = reinterpret_cast( + base + header->off_matrix); + sums_header + = reinterpret_cast(base + header->off_sums); + } + + bool header_set = true; +}; + +struct gemm_pack_storage_shell_t : public gemm_pack_storage_t { + + gemm_pack_storage_shell_t(int max_nthr, bool has_row_sums = false, + bool has_col_sums = false) { + void *ptr = malloc(shell_size(max_nthr), 64); + if (ptr) { + set(ptr); + setup(max_nthr, has_row_sums, has_col_sums); + } + } + + ~gemm_pack_storage_shell_t() { free(get()); } + +private: + static size_t shell_size(int max_nthr) { + return header_size() + matrix_header_size(max_nthr) * 2; + } +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/gemm_partition.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/gemm_partition.hpp new file mode 100644 index 0000000000000000000000000000000000000000..f8ae440b39be92586dbbfc71bdc51e34b588a776 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/gemm_partition.hpp @@ -0,0 +1,279 @@ +/******************************************************************************* +* Copyright 2019-2020 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_GEMM_GEMM_PARTITION_HPP +#define CPU_X64_GEMM_GEMM_PARTITION_HPP + +#include +#include +#include + +#include "common/nstl.hpp" +#include "common/utils.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +static inline void partition_1d(const int ithr, const int nthrs, const dim_t n, + dim_t &t_offset, dim_t &t_block) { + + dim_t band = n / nthrs; + + dim_t tail = n - (nthrs - 1) * band; + if (tail > (band + 1)) band++; + tail = n - (nthrs - 1) * band; + + if (ithr < (nthrs - 1)) + t_block = band; + else + t_block = tail; + + t_offset = ithr * band; + + if (t_offset >= n) { + t_block = 0; + t_offset = 0; + } else if ((t_offset + t_block) > n) { + t_block = n - t_offset; + } +} + +static inline void partition_2d(const int ithr, int *nthrs, const int ithr_i, + const int ithr_j, const int nthrs_m, const int nthrs_n, const dim_t m, + const dim_t n, dim_t &out_m_disp, dim_t &out_m_band, dim_t &out_n_disp, + dim_t &out_n_band) { + + dim_t m_disp = 0, n_disp = 0; + dim_t m_band = 0, n_band = 0; + + int m_div = nthrs_m; + int n_div = nthrs_n; + + dim_t m_bandt = m / m_div; /* size per thread */ + dim_t n_bandt = n / n_div; /* size per thread */ + int first_m_group = m_div - 1; + int first_n_group = n_div - 1; + dim_t first_m_val = m_bandt; + dim_t first_n_val = n_bandt; + + int mthr_used = m_div; + if (m - (m_div - 1) * m_bandt > m_bandt + 1) { + if (m - (m_div - 1) * m_bandt > m_div) ++m_bandt; + + first_m_val = m_bandt + 1; + mthr_used = (int)(m / first_m_val); + + if (mthr_used * first_m_val < m) ++mthr_used; + + first_m_group = mthr_used - 1; + } + + int nthr_used = n_div; + if (n - (n_div - 1) * n_bandt > n_bandt + 1) { + first_n_val = n_bandt + 1; + nthr_used = (int)(n / first_n_val); + + if (nthr_used * first_n_val < n) ++nthr_used; + + first_n_group = nthr_used - 1; + } + + *nthrs = mthr_used * nthr_used; + + if (ithr < *nthrs) { + if (ithr_i < first_m_group) { + m_band = first_m_val; + m_disp = ithr_i * first_m_val; + } else if (ithr_i <= mthr_used - 2) { + m_band = m_bandt; + m_disp = first_m_group * first_m_val + + (ithr_i - first_m_group) * m_bandt; + } else { + m_disp = first_m_group * first_m_val + + (mthr_used - 1 - first_m_group) * m_bandt; + m_band = nstl::max(dim_t(0), m - m_disp); + } + + if (ithr_j < first_n_group) { + n_band = first_n_val; + n_disp = ithr_j * first_n_val; + } else if (ithr_j <= nthr_used - 2) { + n_band = n_bandt; + n_disp = first_n_group * first_n_val + + (ithr_j - first_n_group) * n_bandt; + } else { + n_disp = first_n_group * first_n_val + + (nthr_used - 1 - first_n_group) * n_bandt; + n_band = nstl::max(dim_t(0), n - n_disp); + } + m_disp = nstl::max(nstl::min(m_disp, m - 1), dim_t(0)); + n_disp = nstl::max(nstl::min(n_disp, n - 1), dim_t(0)); + } + + if (ithr < *nthrs) { + out_m_disp = m_disp; + out_n_disp = n_disp; + out_m_band = m_band; + out_n_band = n_band; + } else { + out_m_disp = 0; + out_n_disp = 0; + out_m_band = 0; + out_n_band = 0; + } + + return; +} + +static inline std::tuple partition_2d_minblk_with_primes(dim_t m, + dim_t n, dim_t block_m, dim_t block_n, dim_t min_m, dim_t min_n, + dim_t um, dim_t un, int nthr, bool use_aspect_ratio) { + + auto part_m = nstl::max(dim_t(1), m / block_m); + auto part_n = nstl::max(dim_t(1), n / block_n); + + // Quick exit if there are enough partitions in one direction + // and there is only 1 partition in the other one + if (part_m == 1 && part_n >= nthr) + return std::make_tuple(1, nstl::min((int)part_n, nthr)); + + if (part_n == 1 && part_m >= nthr) + return std::make_tuple(nstl::min((int)part_m, nthr), 1); + + auto num_parts = part_m * part_n; + + int nthr_ite = nthr; + int nthr_m = 1, nthr_n = 1; + dim_t band_m = m, band_n = n; + + for (auto p : {2, 3, 5, 7, 11, 13, 17, 19, 23, 29}) { + bool finished = false; + + while ((nthr_ite % p) == 0 && !finished) { + nthr_ite /= p; + auto nthr_m_ite = nthr_m * p; + auto nthr_n_ite = nthr_n * p; + + auto band_m_ite = band_m / p; + auto band_n_ite = band_n / p; + + // Try partitioning with block size bm x bn + auto try_partition = [&](dim_t bm, dim_t bn, bool pick_small) { + float ratio_m = (float)band_m_ite / bm; + float ratio_n = (float)band_n_ite / bn; + bool do_m = false, do_n = false; + + if (ratio_m < 1. && ratio_n >= 1.) + do_n = true; + else if (ratio_m >= 1. && ratio_n < 1.) + do_m = true; + else if (ratio_m >= 1. && ratio_n >= 1.) { + if (use_aspect_ratio) { + float ratio_goal = (float)um / un; + float try_ratio_m = (float)band_m_ite / band_n + * (1. / ratio_goal); + float try_ratio_n = (float)band_m / band_n_ite + * (1. / ratio_goal); + if (pick_small) { + // Pick either the smaller or larger ratio as appropriate. + ((ratio_m < ratio_n) ? do_m : do_n) = true; + } else { + // Pick the dimension that will keep as close as possible + // to best ratio between m and n. + ((nstl::abs(try_ratio_m - 1.) + < nstl::abs(try_ratio_n - 1)) + ? do_m + : do_n) + = true; + } + } else { + (((ratio_m < ratio_n) == pick_small) ? do_m : do_n) + = true; + } + } + + if (do_m) { + // Partition m. + nthr_m = nthr_m_ite; + band_m = band_m_ite; + } else if (do_n) { + // Partition n. + nthr_n = nthr_n_ite; + band_n = band_n_ite; + } + + return do_m || do_n; + }; + + // If we will need min based partitioning do it now + if (num_parts < nthr) { + num_parts *= p; + if (try_partition(min_m, min_n, true)) continue; + } + + if (try_partition(block_m, block_n, false)) continue; + if (try_partition(min_m, min_n, true)) continue; + + // Both band_m/n are smaller than min_m/n + // exit the loops, nothing to partition + finished = true; + } + + if (finished) break; + } + + return std::make_tuple(nthr_m, nthr_n); +} + +static inline std::tuple partition_2d_minblk(dim_t m, dim_t n, + dim_t block_m, dim_t block_n, dim_t min_m, dim_t min_n, dim_t um, + dim_t un, int nthr, bool use_aspect_ratio) { + + auto part_m = nstl::max(dim_t(1), m / min_m); + auto part_n = nstl::max(dim_t(1), n / min_n); + + // Quick exit if one of the dimensions is too small to partition. + if (part_m == 1) { + part_n = nstl::max(dim_t(1), utils::div_up(n, min_n)); + return std::make_tuple(1, nstl::min((int)part_n, nthr)); + } + + if (part_n == 1) { + part_m = nstl::max(dim_t(1), utils::div_up(m, min_m)); + return std::make_tuple(nstl::min((int)part_m, nthr), 1); + } + + int nthr_m = 0, nthr_n = 0; + auto nthr_thresh = nstl::min(0.95 * nthr, (double)(part_m * part_n)); + + for (int nthr_new = nthr; nthr_new > nthr / 2; nthr_new--) { + if (nthr_m * nthr_n >= nthr_thresh) break; + std::tie(nthr_m, nthr_n) + = partition_2d_minblk_with_primes(m, n, block_m, block_n, min_m, + min_n, um, un, nthr_new, use_aspect_ratio); + } + + return std::make_tuple(nthr_m, nthr_n); +} + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/gemm_threading.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/gemm_threading.hpp new file mode 100644 index 0000000000000000000000000000000000000000..3915dd54f12a5f975b42c7207d8ac814289f718c --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/gemm_threading.hpp @@ -0,0 +1,124 @@ +/******************************************************************************* +* Copyright 2019-2022 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_GEMM_GEMM_THREADING_HPP +#define CPU_X64_GEMM_GEMM_THREADING_HPP + +#include + +#include "common/c_types_map.hpp" + +#include "cpu/x64/gemm/gemm_partition.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +enum class partition_type { row_1d, col_1d, col_major_2d, mnk_3d }; + +enum class copy_type { + nonshared, + shared_a, + no_copy, +}; + +struct gemm_slice_t { + dim_t off_m, off_n, off_k; + dim_t m, n, k; + int ithr_m, ithr_n, ithr_k; +}; + +struct gemm_threading_t { + gemm_threading_t() {}; + + int nthrs_m, nthrs_n, nthrs_k; + dim_t block_m, block_n, block_k; // Blocking sizes (-1 = default) + dim_t thread_m, thread_n, thread_k; // Thread matrix sizes (-1 = default) + partition_type partition; + copy_type copy; + + int nthrs() const { return nthrs_m * nthrs_n * nthrs_k; } + + friend bool operator==( + const gemm_threading_t &t1, const gemm_threading_t &t2) { + return (t1.nthrs_m == t2.nthrs_m && t1.nthrs_n == t2.nthrs_n + && t1.nthrs_k == t2.nthrs_k && t1.partition == t2.partition + && t1.copy == t2.copy); + } + + friend bool operator!=( + const gemm_threading_t &t1, const gemm_threading_t &t2) { + return !(t1 == t2); + } + + gemm_slice_t get_thread_slice(int ithr, dim_t m, dim_t n, dim_t k) const { + + dim_t off_m = 0, off_n = 0, off_k = 0; + dim_t size_m = m, size_n = n, size_k = k; + int ithr_m = 0, ithr_n = 0, ithr_k = 0; + + switch (partition) { + case partition_type::row_1d: + ithr_m = ithr; + partition_1d(ithr, nthrs(), m, off_m, size_m); + break; + + case partition_type::col_1d: + ithr_n = ithr; + partition_1d(ithr, nthrs(), n, off_n, size_n); + break; + + case partition_type::col_major_2d: { + int nthr_eff = nthrs(); + ithr_m = ithr % nthrs_m; + ithr_n = ithr / nthrs_m; + + partition_2d(ithr, &nthr_eff, ithr_m, ithr_n, nthrs_m, nthrs_n, + m, n, off_m, size_m, off_n, size_n); + break; + } + + case partition_type::mnk_3d: { + assert(thread_m > 0 && thread_n > 0 && thread_k > 0); + ithr_m = ithr % nthrs_m; + ithr_n = (ithr / nthrs_m) % nthrs_n; + ithr_k = (ithr / nthrs_m) / nthrs_n; + + off_m = ithr_m * thread_m; + off_n = ithr_n * thread_n; + off_k = ithr_k * thread_k; + + size_m = nstl::min(thread_m, m - off_m); + size_n = nstl::min(thread_n, n - off_n); + size_k = nstl::min(thread_k, k - off_k); + break; + } + } + + return {off_m, off_n, off_k, size_m, size_n, size_k, ithr_m, ithr_n, + ithr_k}; + } + + int thr_k_stride() const { return nthrs_m * nthrs_n; } +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/gemm_utils.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/gemm_utils.hpp new file mode 100644 index 0000000000000000000000000000000000000000..b839b7d7c5f3054fc40b6b3f275d9b99296292dc --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/gemm_utils.hpp @@ -0,0 +1,221 @@ +/******************************************************************************* +* Copyright 2020 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_GEMM_GEMM_UTILS_HPP +#define CPU_X64_GEMM_GEMM_UTILS_HPP + +#include + +#include "common/dnnl_thread.hpp" +#include "common/dnnl_traits.hpp" +#include "common/utils.hpp" + +#include "cpu/x64/gemm/gemm_pack_storage.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { +namespace gemm_utils { + +static inline std::tuple calc_nthr_2d(int nthrs, dim_t m, dim_t n, + dim_t block_m, dim_t block_n, dim_t small_m, dim_t small_n, + dim_t &thread_m, dim_t &thread_n) { + + int nthr_m = utils::div_up(m, block_m); + int nthr_n = utils::div_up(n, block_n); + + if (nthr_m < 1) nthr_m = 1; + if (nthr_n < 1) nthr_n = 1; + + float ratio_float = (float)nthr_m / nthr_n; + + int ratio = 0; + if (nthr_m > nthr_n) + ratio = (int)ratio_float; + else + ratio = (int)(1. / ratio_float); + + // scale down nthr_m and nthr_n if they are too large + while (nthr_m * nthr_n > 4 * nthrs) { + nthr_m /= 2; + nthr_n /= 2; + } + + if (nthr_m < 1) nthr_m = 1; + if (nthr_n < 1) nthr_n = 1; + + // Simple partition reduction + int counter = 0; + while (nthr_m * nthr_n > nthrs) { + if (nthr_m > nthr_n) { + if (counter < ratio) + nthr_m--; + else { + nthr_n--; + counter = -1; + } + } else { + if (counter < ratio) + nthr_n--; + else { + nthr_m--; + counter = -1; + } + } + counter++; + } + + // Simple partition increment + counter = 0; + while (nthr_m * nthr_n < 0.95 * nthrs) { + if (nthr_m > nthr_n) { + if (counter < ratio) + nthr_m++; + else { + nthr_n++; + counter = -1; + } + } else { + if (counter < ratio) + nthr_n++; + else { + nthr_m++; + counter = -1; + } + } + counter++; + } + + // if nothing works out, then this should work + if ((nthr_m * nthr_n > nthrs)) { + + if (nthr_m <= nthr_n) { + nthr_m = (int)sqrt((double)nthrs); + if (nthr_m > utils::div_up(m, small_m)) + nthr_m = utils::div_up(m, small_m); + nthr_n = nthrs / nthr_m; + + while ((nthr_m > 1) && (nthr_m * nthr_n != nthrs)) { + nthr_m--; + nthr_n = nthrs / nthr_m; + } + } else { + nthr_n = (int)sqrt((double)nthrs); + if (nthr_n > utils::div_up(n, small_n)) + nthr_n = utils::div_up(n, small_n); + nthr_m = nthrs / nthr_n; + + while ((nthr_n > 1) && (nthr_m * nthr_n != nthrs)) { + nthr_n--; + nthr_m = nthrs / nthr_n; + } + } + } + + thread_m = utils::div_up(m, nthr_m) + small_m - 1; + thread_n = utils::div_up(n, nthr_n) + small_n - 1; + thread_m -= thread_m % small_m; + thread_n -= thread_n % small_n; + + if (thread_m * nthr_m > m) nthr_m = utils::div_up(m, thread_m); + if (thread_n * nthr_n > n) nthr_n = utils::div_up(n, thread_n); + + return std::make_tuple(nthr_m, nthr_n); +} + +template +static inline dim_t get_ld_padd(const dim_t x) { + return x != 1 ? utils::rnd_up(x, 2048 / sizeof(T)) + (64 / sizeof(T)) : 1; +} + +template +void prep_gemm_pack(bool do_a, int is_trans, dim_t nrows, dim_t ncols, + gemm_pack_storage_t *pack_dst) { + + auto ld = !is_trans ? get_ld_padd(nrows) : get_ld_padd(ncols); + auto td = !is_trans ? ncols : nrows; + + // TODO Do we need to use only one thread? + pack_dst->which() = do_a ? matrix_id::a : matrix_id::b; + pack_dst->setup(1); + pack_dst->threading().copy = copy_type::no_copy; + pack_dst->threading().nthrs_m = 1; + pack_dst->threading().nthrs_n = 1; + pack_dst->threading().nthrs_k = 1; + pack_dst->set_nocopy(0, is_trans, ld, td); + pack_dst->finalize(); +} + +template +dnnl_status_t pack_no_copy(const T *src, dim_t ld_src, dim_t nrows, dim_t ncols, + int trans_src, float alpha, gemm_pack_storage_t *dst_pack) { + + auto dst = dst_pack->matrix(0); + int trans_dst; + dim_t nrows_dst, ncols_dst; + dim_t ld_dst, td_dst; + + constexpr bool is_f32 = data_traits::data_type == data_type::f32; + + if (!dst_pack->get_nocopy(0, trans_dst, ld_dst, td_dst)) + return dnnl_invalid_arguments; + + if (!trans_dst) { + nrows_dst = nrows; + ncols_dst = ncols; + } else { + nrows_dst = ncols; + ncols_dst = nrows; + } + + if (trans_src == trans_dst) { + parallel_nd(ncols_dst, [=](dim_t j) { + auto src_col = src + j * ld_src; + auto dst_col = dst + j * ld_dst; + + PRAGMA_OMP_SIMD() + for (dim_t i = 0; i < nrows_dst; i++) + if (is_f32) + dst_col[i] = alpha * src_col[i]; + else + dst_col[i] = src_col[i]; + }); + } else { + // Naive code for now. + parallel_nd(ncols_dst, [=](dim_t j) { + auto src_col = src + j; + auto dst_col = dst + j * ld_dst; + + PRAGMA_OMP_SIMD() + for (dim_t i = 0; i < nrows_dst; i++) + if (is_f32) + dst_col[i] = alpha * src_col[i * ld_src]; + else + dst_col[i] = src_col[i * ld_src]; + }); + } + + return dnnl_success; +} + +} // namespace gemm_utils +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif // CPU_X64_GEMM_GEMM_UTILS_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/gemv_driver.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/gemv_driver.hpp new file mode 100644 index 0000000000000000000000000000000000000000..a556e43b6184bd65a0ede1ef76791d491c7dc67b --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/gemv_driver.hpp @@ -0,0 +1,37 @@ +/******************************************************************************* +* Copyright 2019-2020 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_GEMM_GEMV_DRIVER_HPP +#define CPU_X64_GEMM_GEMV_DRIVER_HPP + +#include "oneapi/dnnl/dnnl_types.h" + +#include "cpu/x64/gemm/gemm_info.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +template +dnnl_status_t jump_to_gemv(const gemm_info_t *arg); + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif // CPU_X64_GEMM_GEMV_DRIVER_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/s8x8s32/common_u8.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/s8x8s32/common_u8.hpp new file mode 100644 index 0000000000000000000000000000000000000000..1ab525df69713a2bc0f55bf50cb2384495908528 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/s8x8s32/common_u8.hpp @@ -0,0 +1,492 @@ +/******************************************************************************* +* Copyright 2019-2021 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_GEMM_S8X8S32_COMMON_U8_HPP +#define CPU_X64_GEMM_S8X8S32_COMMON_U8_HPP + +#include "cpu/platform.hpp" + +#include "cpu/x64/jit_generator.hpp" + +#define U8_COPY_KERNEL_CODE_SIZE (4096L * 4) +#define S8U8S32_COMPUTE_KERNEL_CODE_SIZE (4096L * 32) + +#define PADD_BYTESIZE_ONPAGE(x, size) \ + (((x) * (size) + PAGE_4K - 1) / PAGE_4K) * PAGE_4K +#define NEXT_THR_STRIDE(x, size) (PADD_BYTESIZE_ONPAGE(x, size)) / size + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +class jit_avx512_core_u8_copy_an_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_u8_copy_an_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx512_core_u8_copy_an_kern(); +}; + +class jit_avx512_core_u8_copy_at_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_u8_copy_at_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx512_core_u8_copy_at_kern(); +}; + +class jit_avx512_core_u8_copy_bn_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_u8_copy_bn_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + bool s8_case; + +public: + jit_avx512_core_u8_copy_bn_kern(bool s8 = false); +}; + +class jit_avx512_core_u8_copy_bt_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_u8_copy_bt_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + bool s8_case; + +public: + jit_avx512_core_u8_copy_bt_kern(bool s8 = false); +}; + +class jit_avx512_core_u8_copy_sum_an_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_u8_copy_sum_an_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx512_core_u8_copy_sum_an_kern(); +}; + +class jit_avx512_core_u8_copy_sum_at_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_u8_copy_sum_at_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx512_core_u8_copy_sum_at_kern(); +}; + +class jit_avx512_core_u8_copy_sum_bn_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_u8_copy_sum_bn_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + bool s8_case; + +public: + jit_avx512_core_u8_copy_sum_bn_kern(bool s8 = false); +}; + +class jit_avx512_core_u8_copy_sum_bt_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_u8_copy_sum_bt_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + bool s8_case; + +public: + jit_avx512_core_u8_copy_sum_bt_kern(bool s8 = false); +}; + +class jit_avx2_vnni_u8_copy_an_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx2_vnni_u8_copy_an_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx2_vnni_u8_copy_an_kern(); +}; + +class jit_avx2_vnni_u8_copy_at_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx2_vnni_u8_copy_at_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx2_vnni_u8_copy_at_kern(); +}; + +class jit_avx2_vnni_u8_copy_bn_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx2_vnni_u8_copy_bn_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx2_vnni_u8_copy_bn_kern(); +}; + +class jit_avx2_vnni_u8_copy_bt_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx2_vnni_u8_copy_bt_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx2_vnni_u8_copy_bt_kern(); +}; + +class jit_avx2_vnni_u8_copy_sum_an_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx2_vnni_u8_copy_sum_an_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx2_vnni_u8_copy_sum_an_kern(); +}; + +class jit_avx2_vnni_u8_copy_sum_at_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx2_vnni_u8_copy_sum_at_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx2_vnni_u8_copy_sum_at_kern(); +}; + +class jit_avx2_vnni_u8_copy_sum_bn_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx2_vnni_u8_copy_sum_bn_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx2_vnni_u8_copy_sum_bn_kern(); +}; + +class jit_avx2_vnni_u8_copy_sum_bt_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx2_vnni_u8_copy_sum_bt_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx2_vnni_u8_copy_sum_bt_kern(); +}; + +class jit_avx2_u8_copy_an_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx2_u8_copy_an_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx2_u8_copy_an_kern(); +}; + +class jit_avx2_u8_copy_at_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx2_u8_copy_at_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx2_u8_copy_at_kern(); +}; + +class jit_avx2_u8_copy_bn_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx2_u8_copy_bn_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx2_u8_copy_bn_kern(); +}; + +class jit_avx2_u8_copy_bt_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx2_u8_copy_bt_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx2_u8_copy_bt_kern(); +}; + +class jit_avx2_u8_copy_sum_an_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx2_u8_copy_sum_an_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx2_u8_copy_sum_an_kern(); +}; + +class jit_avx2_u8_copy_sum_at_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx2_u8_copy_sum_at_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx2_u8_copy_sum_at_kern(); +}; + +class jit_avx2_u8_copy_sum_bn_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx2_u8_copy_sum_bn_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx2_u8_copy_sum_bn_kern(); +}; + +class jit_avx2_u8_copy_sum_bt_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx2_u8_copy_sum_bt_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx2_u8_copy_sum_bt_kern(); +}; + +class jit_avx_u8_copy_an_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx_u8_copy_an_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx_u8_copy_an_kern(); +}; + +class jit_avx_u8_copy_at_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx_u8_copy_at_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx_u8_copy_at_kern(); +}; + +class jit_avx_u8_copy_bn_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx_u8_copy_bn_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx_u8_copy_bn_kern(); +}; + +class jit_avx_u8_copy_bt_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx_u8_copy_bt_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx_u8_copy_bt_kern(); +}; + +class jit_avx_u8_copy_sum_an_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx_u8_copy_sum_an_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx_u8_copy_sum_an_kern(); +}; + +class jit_avx_u8_copy_sum_at_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx_u8_copy_sum_at_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx_u8_copy_sum_at_kern(); +}; + +class jit_avx_u8_copy_sum_bn_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx_u8_copy_sum_bn_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx_u8_copy_sum_bn_kern(); +}; + +class jit_avx_u8_copy_sum_bt_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx_u8_copy_sum_bt_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx_u8_copy_sum_bt_kern(); +}; + +class jit_avx_kernel_b0_gemm_s8u8s32_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx_kernel_b0_gemm_s8u8s32_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx_kernel_b0_gemm_s8u8s32_kern(); +}; + +class jit_avx_kernel_b0_b_gemm_s8u8s32_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx_kernel_b0_b_gemm_s8u8s32_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx_kernel_b0_b_gemm_s8u8s32_kern(); +}; + +class jit_avx_kernel_b0_r_gemm_s8u8s32_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx_kernel_b0_r_gemm_s8u8s32_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx_kernel_b0_r_gemm_s8u8s32_kern(); +}; + +class jit_avx_kernel_b0_c_gemm_s8u8s32_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx_kernel_b0_c_gemm_s8u8s32_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx_kernel_b0_c_gemm_s8u8s32_kern(); +}; + +class jit_avx_kernel_gemm_s8u8s32_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx_kernel_gemm_s8u8s32_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx_kernel_gemm_s8u8s32_kern(); +}; + +class jit_avx_kernel_b_gemm_s8u8s32_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx_kernel_b_gemm_s8u8s32_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx_kernel_b_gemm_s8u8s32_kern(); +}; + +class jit_avx_kernel_r_gemm_s8u8s32_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx_kernel_r_gemm_s8u8s32_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx_kernel_r_gemm_s8u8s32_kern(); +}; + +class jit_avx_kernel_c_gemm_s8u8s32_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx_kernel_c_gemm_s8u8s32_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_avx_kernel_c_gemm_s8u8s32_kern(); +}; + +class jit_sse41_u8_copy_an_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_sse41_u8_copy_an_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_sse41_u8_copy_an_kern(); +}; + +class jit_sse41_u8_copy_at_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_sse41_u8_copy_at_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_sse41_u8_copy_at_kern(); +}; + +class jit_sse41_u8_copy_bn_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_sse41_u8_copy_bn_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_sse41_u8_copy_bn_kern(); +}; + +class jit_sse41_u8_copy_bt_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_sse41_u8_copy_bt_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_sse41_u8_copy_bt_kern(); +}; + +class jit_sse41_u8_copy_sum_an_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_sse41_u8_copy_sum_an_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_sse41_u8_copy_sum_an_kern(); +}; + +class jit_sse41_u8_copy_sum_at_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_sse41_u8_copy_sum_at_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_sse41_u8_copy_sum_at_kern(); +}; + +class jit_sse41_u8_copy_sum_bn_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_sse41_u8_copy_sum_bn_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_sse41_u8_copy_sum_bn_kern(); +}; + +class jit_sse41_u8_copy_sum_bt_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_sse41_u8_copy_sum_bt_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_sse41_u8_copy_sum_bt_kern(); +}; + +class jit_sse41_kernel_b0_gemm_s8u8s32_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_sse41_kernel_b0_gemm_s8u8s32_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_sse41_kernel_b0_gemm_s8u8s32_kern(); +}; + +class jit_sse41_kernel_b0_b_gemm_s8u8s32_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_sse41_kernel_b0_b_gemm_s8u8s32_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_sse41_kernel_b0_b_gemm_s8u8s32_kern(); +}; + +class jit_sse41_kernel_b0_r_gemm_s8u8s32_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_sse41_kernel_b0_r_gemm_s8u8s32_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_sse41_kernel_b0_r_gemm_s8u8s32_kern(); +}; + +class jit_sse41_kernel_b0_c_gemm_s8u8s32_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_sse41_kernel_b0_c_gemm_s8u8s32_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_sse41_kernel_b0_c_gemm_s8u8s32_kern(); +}; + +class jit_sse41_kernel_gemm_s8u8s32_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_sse41_kernel_gemm_s8u8s32_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_sse41_kernel_gemm_s8u8s32_kern(); +}; + +class jit_sse41_kernel_b_gemm_s8u8s32_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_sse41_kernel_b_gemm_s8u8s32_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_sse41_kernel_b_gemm_s8u8s32_kern(); +}; + +class jit_sse41_kernel_r_gemm_s8u8s32_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_sse41_kernel_r_gemm_s8u8s32_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_sse41_kernel_r_gemm_s8u8s32_kern(); +}; + +class jit_sse41_kernel_c_gemm_s8u8s32_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_sse41_kernel_c_gemm_s8u8s32_kern); + void generate() override ATTRIBUTE_OPTIMIZE; + +public: + jit_sse41_kernel_c_gemm_s8u8s32_kern(); +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl +#endif // CPU_X64_GEMM_S8X8S32_COMMON_U8_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/s8x8s32/jit_avx2_gemm_s8u8s32_kern.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/s8x8s32/jit_avx2_gemm_s8u8s32_kern.hpp new file mode 100644 index 0000000000000000000000000000000000000000..eb61a0eca22b404d2aebaee04c6b380b73894ed0 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/s8x8s32/jit_avx2_gemm_s8u8s32_kern.hpp @@ -0,0 +1,91 @@ +/******************************************************************************* +* Copyright 2018-2021 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_GEMM_S8X8S32_JIT_AVX2_GEMM_S8U8S32_KERN_HPP +#define CPU_X64_GEMM_S8X8S32_JIT_AVX2_GEMM_S8U8S32_KERN_HPP + +#include "cpu/x64/jit_generator.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +class jit_avx2_gemm_s8u8s32_kern : public jit_generator { +public: + jit_avx2_gemm_s8u8s32_kern(bool beta_zero, bool enable_offset_c, + bool enable_offset_r, int unroll_m); + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx2_gemm_s8u8s32_kern); + +protected: + bool beta_zero_; + bool enable_offset_c_, enable_offset_r_; + bool vnni_; + int unroll_m_; + + void prefetch_a(const Xbyak::Address &src) { prefetcht0(src); } + void prefetch_b(const Xbyak::Address &src) { prefetcht0(src); } + void prefetch_c(const Xbyak::Address &src) { prefetchw(src); } + void prefetch_x(const Xbyak::Address &src) { prefetcht1(src); } + + void c_load(const Xbyak::Xmm &dst, const Xbyak::Address &src, int nelems); + void c_store(const Xbyak::Address &dst, const Xbyak::Xmm &src, int nelems); + + void dot_product(const Xbyak::Xmm &dst, const Xbyak::Xmm &src1, + const Xbyak::Xmm &src2); + void kernel_loop(int unroll_m, int unroll_n, bool cfetch); + void remainder_kernel(int unroll_m, int unroll_n, int unroll_k, int bwidth); + void innerloop(int unroll_m, int unroll_n); + void outerloop(int unroll_x, int unroll_y, Xbyak::Label *&outerloop_label); + + void generate() override ATTRIBUTE_OPTIMIZE; + +private: + static const int IGEMM_UNROLL_N_ = 4; + + static const int size_ = 4; + static const int isize_ = 1; + + // Prefetch configuration + static const int prefetch_size_a_ = 704; + static const int prefetch_size_b_ = 384; + + static const int offset_a_ = 128, offset_b_ = 128; + static const int max_unroll_m_ = 24, max_unroll_n_ = 4; + + // Integer register assignments + Xbyak::Reg64 M_, N_, K_, A_, B_, C_, LDC_, I_, J_, LoopCount_; + Xbyak::Reg64 AO_, BO_, CO1_, CO2_, AA_; + + // Vector register assignments + Xbyak::Ymm dp_scratch_, ones_; + Xbyak::Ymm a_regs_[max_unroll_m_ >> 3], b_regs_[2]; + Xbyak::Ymm c_regs_[max_unroll_m_ >> 3][max_unroll_n_]; + + // Stack variable assignments + int stack_alloc_size_; + Xbyak::Address arg_a_, arg_b_, arg_c_, arg_ldc_, arg_coffset_c_, + arg_coffset_r_; + Xbyak::Address coffset_cx_, coffset_cy_, coffset_rx_, coffset_ry_; + Xbyak::Address bcast_k2_, bcast_k1_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif // CPU_X64_GEMM_S8X8S32_JIT_AVX2_GEMM_S8U8S32_KERN_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/s8x8s32/jit_avx512_core_gemm_s8u8s32_kern.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/s8x8s32/jit_avx512_core_gemm_s8u8s32_kern.hpp new file mode 100644 index 0000000000000000000000000000000000000000..80d6afd3653d1e883e941b304afa99f0de982871 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/s8x8s32/jit_avx512_core_gemm_s8u8s32_kern.hpp @@ -0,0 +1,89 @@ +/******************************************************************************* +* Copyright 2018-2021 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_GEMM_S8X8S32_JIT_AVX512_CORE_GEMM_S8U8S32_KERN_HPP +#define CPU_X64_GEMM_S8X8S32_JIT_AVX512_CORE_GEMM_S8U8S32_KERN_HPP + +#include "cpu/x64/jit_generator.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +class jit_avx512_core_gemm_s8u8s32_kern : public jit_generator { +public: + jit_avx512_core_gemm_s8u8s32_kern( + bool beta_zero, bool enable_offset_c, bool enable_offset_r); + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_gemm_s8u8s32_kern); + +protected: + bool beta_zero_; + bool enable_offset_c_, enable_offset_r_; + bool vnni_; + + void prefetch_a(const Xbyak::Address &src) { prefetcht0(src); } + void prefetch_b(const Xbyak::Address &src) { prefetcht0(src); } + void prefetch_c(const Xbyak::Address &src) { prefetchw(src); } + void prefetch_x(const Xbyak::Address &src) { prefetcht0(src); } + + void c_load(const Xbyak::Xmm &dst, const Xbyak::Address &src, int nelems); + void c_store(const Xbyak::Address &dst, const Xbyak::Xmm &src, int nelems); + + void dot_product(const Xbyak::Xmm &dst, const Xbyak::Xmm &src1, + const Xbyak::Xmm &src2); + void kernel_loop(int unroll_m, int unroll_n, bool cfetch); + void remainder_kernel(int unroll_m, int unroll_n, int unroll_k, int bwidth); + void innerloop(int unroll_m, int unroll_n); + void outerloop(int unroll_x, int unroll_y, Xbyak::Label *&outerloop_label); + + void generate() override ATTRIBUTE_OPTIMIZE; + +private: + static const int IGEMM_UNROLL_M_ = 48; + static const int IGEMM_UNROLL_N_ = 8; + + static const int isize_ = 2; + static const int size_ = 4; + + // Prefetch configuration + static const int prefetch_size_a_ = 32 * 5; + static const int prefetch_size_b_ = 32 * 4; + + static const int offset_a_ = 256, offset_b_ = 256; + static const int max_unroll_m_ = 48, max_unroll_n_ = 8; + + // Integer register assignments + Xbyak::Reg64 M_, N_, K_, A_, B_, C_, LDC_, I_, J_, LoopCount_; + Xbyak::Reg64 AO_, BO_, CO1_, CO2_, AA_; + + // Vector register assignments + Xbyak::Zmm dp_scratch_, ones_, a_regs_[max_unroll_m_ >> 4], b_regs_[2]; + Xbyak::Zmm c_regs_[max_unroll_m_ >> 4][max_unroll_n_]; + + // Stack variable assignments + int stack_alloc_size_; + Xbyak::Address arg_a_, arg_b_, arg_c_, arg_ldc_, arg_coffset_c_, + arg_coffset_r_; + Xbyak::Address coffset_cx_, coffset_cy_, coffset_rx_, coffset_ry_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif // CPU_X64_GEMM_S8X8S32_JIT_AVX512_CORE_GEMM_S8U8S32_KERN_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/s8x8s32/jit_avx512_core_gemv_s8x8s32.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/s8x8s32/jit_avx512_core_gemv_s8x8s32.hpp new file mode 100644 index 0000000000000000000000000000000000000000..15edccb960ad6b5c3b13a976f24613ba2783fc2b --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/s8x8s32/jit_avx512_core_gemv_s8x8s32.hpp @@ -0,0 +1,37 @@ +/******************************************************************************* +* Copyright 2019-2020 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_GEMM_S8X8S32_JIT_AVX512_CORE_GEMV_S8X8S32_HPP +#define CPU_X64_GEMM_S8X8S32_JIT_AVX512_CORE_GEMV_S8X8S32_HPP + +#include + +#include "cpu/x64/gemm/gemm_info.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +template +int jump_to_gemv_s8x8s32(T *arg); + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif // CPU_X64_GEMM_S8X8S32_JIT_AVX512_CORE_GEMV_S8X8S32_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/s8x8s32/jit_avx512_core_kernel_gemv_s8x8s32_kern.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/s8x8s32/jit_avx512_core_kernel_gemv_s8x8s32_kern.hpp new file mode 100644 index 0000000000000000000000000000000000000000..7a35dd0896df1a4233a514ce69e90796065e0b5a --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm/s8x8s32/jit_avx512_core_kernel_gemv_s8x8s32_kern.hpp @@ -0,0 +1,90 @@ +/******************************************************************************* +* Copyright 2019-2022 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_GEMM_S8X8S32_JIT_AVX512_CORE_KERNEL_GEMV_S8X8S32_KERN_HPP +#define CPU_X64_GEMM_S8X8S32_JIT_AVX512_CORE_KERNEL_GEMV_S8X8S32_KERN_HPP + +#include + +#include "cpu/x64/cpu_isa_traits.hpp" +#include "cpu/x64/jit_generator.hpp" + +#include "cpu/x64/gemm/gemm_info.hpp" + +#include "cpu/x64/gemm/s8x8s32/common_u8.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +enum class ver_t { undef, s8s8, s8u8, u8s8 }; + +class jit_avx512_core_gemv_s8x8s32_kern : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_gemv_s8x8s32_kern); + + enum class vnni_op_t { add, sub }; + + void vnni(Xbyak::Zmm acc, Xbyak::Zmm b, Xbyak::Zmm a, vnni_op_t op); + void n_loop_body(int nreg_acc, Xbyak::Reg64 A, Xbyak::Reg64 lda, + Xbyak::Reg64 X, int use_mask, Xbyak::Opmask mask_n); + void shuffle_and_add( + Xbyak::Zmm, Xbyak::Zmm, Xbyak::Zmm, Xbyak::Zmm, Xbyak::Zmm); + void update_c(int, Xbyak::Reg64, int, Xbyak::Opmask); + void generate() override ATTRIBUTE_OPTIMIZE; + + cpu_isa_t isa = isa_undef; + ver_t ver = ver_t::undef; + + // Assumes unroll_{m,n} are a power of 2. + static constexpr unsigned int unroll_m_ = 4; // Unrolling is 2^unroll_m_. + static constexpr unsigned int unroll_n_ = 6; // Unrolling is 2^unroll_n_. + + enum { + zmm_a_idx_start = 5, + zmm_a_idx_count = 1 << (unroll_m_ - 1), // nreg_A + zmm_acc_idx_start = zmm_a_idx_start + zmm_a_idx_count, + zmm_acc_idx_count = 1 << unroll_m_, // nreg_acc + }; + + Xbyak::Zmm zmm_tmp = Xbyak::Zmm(0); + Xbyak::Xmm xmm_beta = Xbyak::Xmm(1); + + Xbyak::Zmm zmm_1_s16 = Xbyak::Zmm(2); // avx512_core + Xbyak::Zmm zmm_1_u1 = Xbyak::Zmm(2); // s8s8, avx512_core_vnni + Xbyak::Zmm zmm_128_u8 = Xbyak::Zmm(3); // s8s8 + + Xbyak::Zmm zmm_b = Xbyak::Zmm(4); // x-vector + Xbyak::Zmm zmm_a(int idx) { // matrix + assert(idx < zmm_a_idx_count); + return Xbyak::Zmm(zmm_a_idx_start + idx); + } + Xbyak::Zmm zmm_acc(int idx) { // y-vector + assert(idx < zmm_acc_idx_count); + return Xbyak::Zmm(zmm_acc_idx_start + idx); + } + +public: + jit_avx512_core_gemv_s8x8s32_kern(ver_t ver) + : jit_generator(jit_name(), nullptr, 32 * 1024), ver(ver) {} +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif // CPU_X64_GEMM_S8X8S32_JIT_AVX512_CORE_KERNEL_GEMV_S8X8S32_KERN_HPP diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm_bf16_convolution.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm_bf16_convolution.hpp new file mode 100644 index 0000000000000000000000000000000000000000..538fbb58191097791b17ad330b3e4879a1ac507d --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm_bf16_convolution.hpp @@ -0,0 +1,363 @@ +/******************************************************************************* +* Copyright 2019-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_GEMM_BF16_CONVOLUTION_HPP +#define CPU_X64_GEMM_BF16_CONVOLUTION_HPP + +#include "common/c_types_map.hpp" +#include "common/memory_tracking.hpp" +#include "common/primitive.hpp" + +#include "cpu/cpu_convolution_pd.hpp" +#include "cpu/cpu_engine.hpp" +#include "cpu/gemm/gemm.hpp" +#include "cpu/gemm_convolution_utils.hpp" +#include "cpu/x64/cpu_reducer.hpp" +#include "cpu/x64/injectors/jit_uni_postops_injector.hpp" +#include "cpu/x64/jit_avx512_core_bf16cvt.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +template +struct gemm_bf16_convolution_fwd_t : public primitive_t { + struct pd_t : public cpu_convolution_fwd_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const typename pd_t::base_class *hint_fwd_pd) + : cpu_convolution_fwd_pd_t(adesc, attr, hint_fwd_pd), jcp_() {} + + DECLARE_COMMON_PD_T(GEMM_IMPL_STR, gemm_bf16_convolution_fwd_t, + USE_GLOBAL_SCRATCHPAD); + + status_t init(engine_t *engine) { + bool ok = true && is_fwd() && mayiuse(avx512_core) + && set_default_alg_kind(alg_kind::convolution_direct) + && expect_data_types(data_type::bf16, data_type::bf16, + data_type::undef, dst_data_type, data_type::f32) + && IMPLICATION(with_bias(), + utils::one_of(desc()->bias_desc.data_type, + data_type::bf16, data_type::f32)) + && !has_zero_dim_memory() + && attr()->has_default_values( + primitive_attr_t::skip_mask_t::post_ops, + dst_data_type); + { + using namespace x64::injector; + static constexpr bool sum_at_pos_0_only = true; + static constexpr bool sum_requires_scale_one = true; + static constexpr bool sum_requires_zp_zero = true; + const auto dst_md = memory_desc_wrapper(dst_md_); + ok &= post_ops_ok( + post_ops_ok_args_t(avx512_core, {binary, eltwise, sum}, + attr()->post_ops_, &dst_md, sum_at_pos_0_only, + sum_requires_scale_one, sum_requires_zp_zero)); + } + if (!ok) return status::unimplemented; + + auto scratchpad = scratchpad_registry().registrar(); + return jit_gemm_convolution_utils::init_conf(jcp_, scratchpad, + *desc(), src_md_, weights_md_, dst_md_, bias_md_, attr_, + dnnl_get_max_threads()); + } + + bool is_postprocess_required() const { + bool post_ops_sum_only_for_dst_f32 = true + && dst_data_type == data_type::f32 + && attr()->post_ops_.len() == 1 + && attr()->post_ops_.contain(primitive_kind::sum, 0); + bool is_pp_for_post_ops_required = true + && attr()->post_ops_.len() > 0 + && !post_ops_sum_only_for_dst_f32; + return dst_data_type == data_type::bf16 || with_bias() + || is_pp_for_post_ops_required; + } + + conv_gemm_conf_t jcp_; + }; + + gemm_bf16_convolution_fwd_t(const pd_t *apd) + : primitive_t(apd), pp_ker_(nullptr) {} + + typedef typename prec_traits::type dst_data_t; + typedef typename prec_traits::type acc_data_t; + typedef typename prec_traits::type src_data_t; + typedef typename prec_traits::type wei_data_t; + + status_t init(engine_t *engine) override { + const auto &post_ops = pd()->attr()->post_ops_; + const acc_data_t one = 1.0, zero = 0.0; + beta_ = dst_data_type == data_type::f32 + && post_ops.find(primitive_kind::sum) >= 0 + ? one + : zero; + + if (this->pd()->is_postprocess_required()) { + CHECK(safe_ptr_assign(pp_ker_, new pp_ker_t(this->pd()))); + return pp_ker_->create_kernel(); + } + return status::success; + } + + status_t execute(const exec_ctx_t &ctx) const override { + const bool is_nspc = pd()->jcp_.is_nspc; + return is_nspc ? execute_forward_nspc(ctx) : execute_forward_ncsp(ctx); + } + +private: + status_t execute_forward_ncsp(const exec_ctx_t &ctx) const; + status_t execute_forward_nspc(const exec_ctx_t &ctx) const; + status_t execute_forward_thr_nspc(const int ithr, const int nthr, + const src_data_t *src_base, const wei_data_t *wei_base, + const float *bia_base, dst_data_t *dst_base, + const memory_tracking::grantor_t &scratchpad, + const void *post_ops_binary_rhs_arg_vec) const; + + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + class pp_ker_t : public jit_generator { + public: + DECLARE_CPU_JIT_AUX_FUNCTIONS(gemm_bf16_convolution_fwd_t::pp_kernel); + pp_ker_t(const pd_t *pd); + + void operator()(dst_data_t *dst, const acc_data_t *acc, + const acc_data_t *bias, float sum_scale, size_t oc_work, + const void *post_ops_binary_rhs_arg_vec, const void *dst_orig, + const size_t g_oc_offset); + void operator()(dst_data_t *dst, const acc_data_t *acc, + const acc_data_t *bias, float sum_scale, size_t dst_str, + size_t acc_str, size_t sp_len, size_t oc, + const void *post_ops_binary_rhs_arg_vec, const void *dst_orig, + const size_t g_oc_offset); + + private: + struct ker_args { + dst_data_t *dst; + const acc_data_t *acc; + const acc_data_t *bias; + float sum_scale; + size_t dst_stride_in_bytes; + size_t acc_stride_in_bytes; + size_t spatial_length; + size_t oc_work; + + size_t g_oc_offset; + const void *post_ops_binary_rhs_arg_vec; + const void *dst_orig; + }; + + enum { default_unroll_2_pow_ = 2 }; + + Xbyak::Reg64 reg_param = rdi; + Xbyak::Reg64 reg_dst_base = rdx; + Xbyak::Reg64 reg_acc_base = rax; + Xbyak::Reg64 reg_dst = rsi; + Xbyak::Reg64 reg_acc = rbp; + Xbyak::Reg64 reg_bias = rbx; + + Xbyak::Reg64 reg_len = r8; + Xbyak::Reg64 reg_tmp = rcx; // intentional for shifting purposes + Xbyak::Reg64 reg_rem_mask = r9; + Xbyak::Opmask kreg_rem_mask = k1; + Xbyak::Reg64 reg_oc_iter = r11; + Xbyak::Reg64 reg_len_iter = r12; + Xbyak::Reg64 reg_dst_str = r13; + Xbyak::Reg64 reg_acc_str = r14; + + Xbyak::Reg64 reserved_eltwise_gpr = r10; + Xbyak::Opmask reserved_eltwise_maskr = k2; + + Xbyak::Zmm vreg_sum_scale, vreg_bias; + + Xbyak::Zmm bf16_emu_reserv_1 = Xbyak::Zmm(27); + Xbyak::Zmm bf16_emu_reserv_2 = Xbyak::Zmm(28); + Xbyak::Zmm bf16_emu_reserv_3 = Xbyak::Zmm(29); + Xbyak::Reg64 bf16_emu_reserv_4 = r15; + Xbyak::Zmm bf16_emu_reserv_5 = Xbyak::Zmm(30); + Xbyak::Zmm bf16_emu_reserv_6 = Xbyak::Zmm(31); + + const conv_gemm_conf_t &jcp_; + const bool do_sum_; + int max_data_reg_idx_, max_unroll_, compute_reg_step_; + int data_reg_base_idx_; + size_t vlen_; + cpu_isa_t isa_; + std::unique_ptr bf16_emu_; + std::unique_ptr> + postops_injector_; + + void apply_postops(const bool apply_mask, const size_t out_offset, + const int vmm_idx); + void generate() override; + int vreg_dst_idx(int iter) { + int idx = data_reg_base_idx_ + iter * compute_reg_step_ + 0; + assert(idx <= max_data_reg_idx_); + return idx; + } + int vreg_prev_dst_idx(int iter) { + int idx = data_reg_base_idx_ + iter * compute_reg_step_ + 1; + assert(idx <= max_data_reg_idx_); + return idx; + } + + Xbyak::Zmm vreg_dst(int iter) { + return Xbyak::Zmm(vreg_dst_idx(iter)); + }; + + Xbyak::Ymm vreg_dst_ymm(int iter) { + return Xbyak::Ymm(vreg_dst_idx(iter)); + }; + + Xbyak::Zmm vreg_prev_dst(int iter) { + return Xbyak::Zmm(vreg_prev_dst_idx(iter)); + }; + + Xbyak::Ymm vreg_prev_dst_ymm(int iter) { + return Xbyak::Ymm(vreg_prev_dst_idx(iter)); + }; + }; + + acc_data_t beta_; + std::unique_ptr pp_ker_; +}; + +template +struct gemm_bf16_convolution_bwd_data_t : public primitive_t { + struct pd_t : public cpu_convolution_bwd_data_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const convolution_fwd_pd_t *hint_fwd_pd) + : cpu_convolution_bwd_data_pd_t(adesc, attr, hint_fwd_pd), jcp_() {} + + DECLARE_COMMON_PD_T(GEMM_IMPL_STR, gemm_bf16_convolution_bwd_data_t, + USE_GLOBAL_SCRATCHPAD); + + status_t init(engine_t *engine) { + bool ok = true && mayiuse(avx512_core) + && desc()->prop_kind == prop_kind::backward_data + && set_default_alg_kind(alg_kind::convolution_direct) + && expect_data_types(diff_src_data_type, data_type::bf16, + data_type::undef, data_type::bf16, data_type::f32) + && !has_zero_dim_memory() && attr()->has_default_values(); + if (!ok) return status::unimplemented; + + auto scratchpad = scratchpad_registry().registrar(); + return jit_gemm_convolution_utils::init_conf(jcp_, scratchpad, + *desc(), diff_src_md_, weights_md_, diff_dst_md_, bias_md_, + attr_, dnnl_get_max_threads()); + } + + conv_gemm_conf_t jcp_; + }; + + gemm_bf16_convolution_bwd_data_t(const pd_t *apd) : primitive_t(apd) {} + + typedef typename prec_traits::type diff_dst_data_t; + typedef typename prec_traits::type acc_data_t; + typedef typename prec_traits::type diff_src_data_t; + typedef typename prec_traits::type wei_data_t; + + status_t execute(const exec_ctx_t &ctx) const override { + const bool is_nspc = pd()->jcp_.is_nspc; + return is_nspc ? execute_backward_data_nspc(ctx) + : execute_backward_data_ncsp(ctx); + } + +private: + status_t execute_backward_data_ncsp(const exec_ctx_t &ctx) const; + status_t execute_backward_data_nspc(const exec_ctx_t &ctx) const; + status_t execute_backward_data_thr_nspc(const int ithr, const int nthr, + diff_src_data_t *diff_src_base, const wei_data_t *wei_base, + const diff_dst_data_t *diff_dst_base, + const memory_tracking::grantor_t &scratchpad) const; + + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } +}; + +template +struct gemm_bf16_convolution_bwd_weights_t : public primitive_t { + struct pd_t : public cpu_convolution_bwd_weights_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const convolution_fwd_pd_t *hint_fwd_pd) + : cpu_convolution_bwd_weights_pd_t(adesc, attr, hint_fwd_pd) + , jcp_() {} + + DECLARE_COMMON_PD_T(GEMM_IMPL_STR, gemm_bf16_convolution_bwd_weights_t, + USE_GLOBAL_SCRATCHPAD); + + status_t init(engine_t *engine) { + bool ok = true && mayiuse(avx512_core) + && desc()->prop_kind == prop_kind::backward_weights + && set_default_alg_kind(alg_kind::convolution_direct) + && expect_data_types(data_type::bf16, diff_wei_data_type, + data_type::undef, data_type::bf16, data_type::f32) + && IMPLICATION(with_bias(), + utils::one_of(desc()->diff_bias_desc.data_type, + data_type::bf16, data_type::f32)) + && !has_zero_dim_memory() && attr()->has_default_values(); + if (!ok) return status::unimplemented; + + auto scratchpad = scratchpad_registry().registrar(); + return jit_gemm_convolution_utils::init_conf(jcp_, scratchpad, + *desc(), src_md_, diff_weights_md_, diff_dst_md_, + diff_bias_md_, attr_, dnnl_get_max_threads()); + } + + conv_gemm_conf_t jcp_; + }; + + gemm_bf16_convolution_bwd_weights_t(const pd_t *apd) + : primitive_t(apd), acc_ker_(nullptr) {} + + typedef typename prec_traits::type diff_dst_data_t; + typedef typename prec_traits::type acc_data_t; + typedef typename prec_traits::type src_data_t; + typedef typename prec_traits::type diff_wei_data_t; + + status_t init(engine_t *engine) override { + CHECK(safe_ptr_assign( + acc_ker_, new cpu_accumulator_1d_t())); + return acc_ker_->create_kernel(); + } + + status_t execute(const exec_ctx_t &ctx) const override { + const bool is_nspc = pd()->jcp_.is_nspc; + return is_nspc ? execute_backward_weights_nspc(ctx) + : execute_backward_weights_ncsp(ctx); + } + +private: + void bf16_bwd_weights_reduction_par_ncsp(int ithr_mb, int nthr_mb, + const conv_gemm_conf_t &jcp, const acc_data_t *weights_reduce_base, + diff_wei_data_t *weights_base) const; + void bf16_bwd_weights_reduction_par_nspc(int ithr_mb, int nthr_mb, + size_t g_start, size_t g_end, const conv_gemm_conf_t &jcp, + const acc_data_t *weights_reduce_base, + diff_wei_data_t *weights_base) const; + + status_t execute_backward_weights_ncsp(const exec_ctx_t &ctx) const; + status_t execute_backward_weights_nspc(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr> acc_ker_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm_bf16_inner_product.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm_bf16_inner_product.hpp new file mode 100644 index 0000000000000000000000000000000000000000..33248bacc4e35c559c81f491bd39965f5da2b1ca --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/gemm_bf16_inner_product.hpp @@ -0,0 +1,307 @@ +/******************************************************************************* +* Copyright 2019-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_GEMM_BF16_INNER_PRODUCT_HPP +#define CPU_X64_GEMM_BF16_INNER_PRODUCT_HPP + +#include + +#include + +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/memory_tracking.hpp" +#include "common/primitive.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_engine.hpp" +#include "cpu/gemm/gemm.hpp" +#include "cpu/gemm_inner_product_utils.hpp" + +#include "cpu/x64/jit_uni_convert_xf16.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +template +struct gemm_bf16_inner_product_fwd_t : public primitive_t { + struct pd_t : public cpu_inner_product_fwd_pd_t { + using cpu_inner_product_fwd_pd_t::cpu_inner_product_fwd_pd_t; + + DECLARE_COMMON_PD_T(GEMM_IMPL_STR, gemm_bf16_inner_product_fwd_t); + + status_t init(engine_t *engine) { + using namespace utils; + using namespace data_type; + + bool ok = true && mayiuse(avx512_core) && is_fwd() + && !has_zero_dim_memory() + && everyone_is( + bf16, src_md()->data_type, weights_md()->data_type) + && dst_data_type == dst_md()->data_type + && IMPLICATION(with_bias(), + one_of(weights_md(1)->data_type, f32, bf16)) + && attr()->has_default_values( + primitive_attr_t::skip_mask_t::post_ops, + dst_md()->data_type) + && attr()->post_ops_.check_sum_consistency( + dst_md()->data_type, /* is_int8 */ false) + && inner_product_utils::post_ops_ok( + attr()->post_ops_, &dst_md_) + && set_default_params() == status::success + && dense_gemm_consitency_check( + src_md(), weights_md(), dst_md()) + && attr_.set_default_formats(dst_md(0)) == status::success; + if (!ok) return status::unimplemented; + + dst_is_acc_ = dst_data_type == f32; + + init_scratchpad(); + + return status::success; + } + + bool dst_is_acc_; + + protected: + void init_scratchpad() { + if (!dst_is_acc_) { + auto scratchpad = scratchpad_registry().registrar(); + scratchpad.template book( + memory_tracking::names::key_iprod_int_dat_in_acc_dt, + MB() * OC()); + } + } + }; + + gemm_bf16_inner_product_fwd_t(const pd_t *apd) : primitive_t(apd) {} + + typedef typename prec_traits::type dst_data_t; + typedef typename prec_traits::type acc_data_t; + typedef typename prec_traits::type src_data_t; + typedef typename prec_traits::type wei_data_t; + + status_t init(engine_t *engine) override { + const bool has_bias = pd()->with_bias(); + const bool has_eltwise + = pd()->attr()->post_ops_.find(primitive_kind::eltwise) >= 0; + const bool has_binary + = pd()->attr()->post_ops_.find(primitive_kind::binary) >= 0; + const bool has_sum_as_postops = !pd()->dst_is_acc_; + postops_in_ip_ = false + || !pd()->dst_is_acc_ /* includes has_sum_as_postops */ + || has_bias || has_eltwise || has_binary; + if (postops_in_ip_) + CHECK(safe_ptr_assign(pp_kernel_, + inner_product_utils::pp_kernel_t::create( + pd(), !has_sum_as_postops))); + + auto sum_idx = pd()->attr()->post_ops_.find(primitive_kind::sum); + beta_ = sum_idx >= 0 && !has_sum_as_postops + ? pd()->attr()->post_ops_.entry_[sum_idx].sum.scale + : 0.0; + + return (pp_kernel_) ? pp_kernel_->create_kernel() : status::success; + } + + status_t execute(const exec_ctx_t &ctx) const override { + return execute_forward(ctx); + } + +private: + std::unique_ptr pp_kernel_; + bool postops_in_ip_; + float beta_; + + status_t execute_forward(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } +}; + +template +struct gemm_bf16_inner_product_bwd_data_t : public primitive_t { + struct pd_t : public cpu_inner_product_bwd_data_pd_t { + using cpu_inner_product_bwd_data_pd_t::cpu_inner_product_bwd_data_pd_t; + + DECLARE_COMMON_PD_T(GEMM_IMPL_STR, gemm_bf16_inner_product_bwd_data_t); + + status_t init(engine_t *engine) { + using namespace data_type; + + bool ok = true && mayiuse(avx512_core) + && desc()->prop_kind == prop_kind::backward_data + && !has_zero_dim_memory() + && utils::everyone_is(bf16, weights_md()->data_type, + diff_dst_md()->data_type) + && diff_src_data_type == diff_src_md()->data_type + && attr()->has_default_values() + && this->set_default_params() == status::success + && dense_gemm_consitency_check( + diff_src_md(), weights_md(), diff_dst_md()); + if (!ok) return status::unimplemented; + + diff_src_is_acc_ = diff_src_data_type == data_type::f32; + + init_scratchpad(); + + return status::success; + } + + bool diff_src_is_acc_; + + private: + void init_scratchpad() { + if (!diff_src_is_acc_) { + auto scratchpad = scratchpad_registry().registrar(); + scratchpad.template book( + memory_tracking::names::key_iprod_int_dat_in_acc_dt, + MB() * IC_total_padded()); + } + } + }; + + gemm_bf16_inner_product_bwd_data_t(const pd_t *apd) : primitive_t(apd) {} + + typedef typename prec_traits::type diff_dst_data_t; + typedef typename prec_traits::type acc_data_t; + typedef typename prec_traits::type diff_src_data_t; + typedef typename prec_traits::type wei_data_t; + + status_t execute(const exec_ctx_t &ctx) const override { + return execute_backward_data(ctx); + } + +private: + status_t execute_backward_data(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } +}; + +template +struct gemm_bf16_inner_product_bwd_weights_t : public primitive_t { + struct pd_t : public cpu_inner_product_bwd_weights_pd_t { + using cpu_inner_product_bwd_weights_pd_t:: + cpu_inner_product_bwd_weights_pd_t; + + DECLARE_COMMON_PD_T( + GEMM_IMPL_STR, gemm_bf16_inner_product_bwd_weights_t); + + status_t init(engine_t *engine) { + using namespace utils; + using namespace data_type; + + bool ok = true && mayiuse(avx512_core) + && desc()->prop_kind == prop_kind::backward_weights + && !has_zero_dim_memory() + && everyone_is( + bf16, src_md()->data_type, diff_dst_md()->data_type) + && diff_wei_data_type == diff_weights_md()->data_type + && IMPLICATION(with_bias(), + one_of(diff_weights_md(1)->data_type, f32, bf16)) + && attr()->has_default_values() + && set_default_params() == status::success + && dense_gemm_consitency_check( + src_md(), diff_weights_md(), diff_dst_md()); + + if (!ok) return status::unimplemented; + + diff_wei_is_acc_ = diff_wei_data_type == f32; + bias_reduction_nthr_ = dnnl_get_max_threads(); + + init_scratchpad(); + + return status::success; + } + + bool diff_wei_is_acc_; + int bias_reduction_nthr_; + static const dim_t bias_blksize = 32; + + void get_bias_partitioning( + dim_t &OC_per_thread, int &nthr_OCB, int &nthr_MB) const { + dim_t OCB = utils::div_up(OC(), bias_blksize); + dim_t OCB_per_thread = utils::div_up(OCB, bias_reduction_nthr_); + + OC_per_thread = OCB_per_thread * bias_blksize; + nthr_OCB = utils::div_up(OCB, OCB_per_thread); + nthr_MB = bias_reduction_nthr_ / nthr_OCB; + + assert(nthr_OCB * nthr_MB <= bias_reduction_nthr_); + } + + private: + void init_scratchpad() { + using namespace memory_tracking; + auto scratchpad = scratchpad_registry().registrar(); + + if (!diff_wei_is_acc_) + scratchpad.template book( + names::key_iprod_int_dat_in_acc_dt, + OC() * IC_total_padded()); + + if (with_bias()) { + dim_t OC_per_thread {0}; + int nthr_OCB {0}, nthr_MB {0}; + get_bias_partitioning(OC_per_thread, nthr_OCB, nthr_MB); + + const bool diff_bias_is_acc = nthr_MB == 1 + && diff_weights_md(1)->data_type == data_type::f32; + + if (!diff_bias_is_acc) + scratchpad.template book( + names::key_iprod_bias_bf16_convert_wsp, + nthr_OCB * nthr_MB * OC_per_thread); + } + } + }; + + gemm_bf16_inner_product_bwd_weights_t(const pd_t *apd) : primitive_t(apd) {} + + status_t init(engine_t *engine) override { + if (pd()->with_bias()) + CHECK(safe_ptr_assign(bias_reduction_, + new jit_cvt_xf16_to_ps_t( + data_type::bf16, true, (size_t)pd()->OC()))); + return status::success; + } + + typedef typename prec_traits::type diff_dst_data_t; + typedef typename prec_traits::type acc_data_t; + typedef typename prec_traits::type src_data_t; + typedef typename prec_traits::type diff_wei_data_t; + + status_t execute(const exec_ctx_t &ctx) const override { + return execute_backward_weights(ctx); + } + +private: + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + status_t execute_backward_weights(const exec_ctx_t &ctx) const; + void execute_backward_bias(const exec_ctx_t &ctx) const; + + std::unique_ptr bias_reduction_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/injectors/injector_utils.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/injectors/injector_utils.hpp new file mode 100644 index 0000000000000000000000000000000000000000..6498f814b67aadac29146be091aea5851a3d27b0 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/injectors/injector_utils.hpp @@ -0,0 +1,88 @@ +/******************************************************************************* +* Copyright 2020-2022 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_INJECTOR_UTILS_HPP +#define CPU_X64_JIT_INJECTOR_UTILS_HPP + +#include +#include +#include +#include + +#include "cpu/x64/jit_generator.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { +namespace injector_utils { + +using vmm_index_set_t = typename std::set; +using vmm_index_set_iterator_t = typename std::set::iterator; + +enum class layout_t { ncsp, c_blocked, nspc, cspn, unsupported }; + +inline layout_t get_layout_type(const memory_desc_wrapper &dst_d) { + const auto strides = dst_d.blocking_desc().strides; + if (!dst_d.is_plain()) return layout_t::c_blocked; + if (strides[0] >= strides[1] + && IMPLICATION(dst_d.ndims() >= 3, strides[1] >= strides[2])) + return layout_t::ncsp; + if (strides[1] == 1) return layout_t::nspc; + if (strides[0] == 1) return layout_t::cspn; + return layout_t::unsupported; +} + +/* + * Scope guard for general purpose register and vector registers preservation. + * Pushes registers to stack during construction and pops during destruction. + */ +class register_preserve_guard_t { + +public: + register_preserve_guard_t(jit_generator *host, + std::initializer_list reg64_to_preserve, + std::initializer_list vmm_to_preserve = {}); + register_preserve_guard_t(register_preserve_guard_t &&other) = default; + register_preserve_guard_t &operator=(register_preserve_guard_t &&other) + = default; + DNNL_DISALLOW_COPY_AND_ASSIGN(register_preserve_guard_t); + ~register_preserve_guard_t(); + size_t stack_space_occupied() const; + +private: + jit_generator *host_; + std::stack reg64_stack_; + std::stack vmm_stack_; + size_t vmm_to_preserve_size_bytes_; +}; + +class conditional_register_preserve_guard_t : public register_preserve_guard_t { +public: + conditional_register_preserve_guard_t(bool condition_to_be_met, + jit_generator *host, + std::initializer_list reg64_to_preserve, + std::initializer_list vmm_to_preserve = {}); + DNNL_DISALLOW_COPY_AND_ASSIGN(conditional_register_preserve_guard_t); +}; + +} // namespace injector_utils +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/injectors/jit_uni_binary_injector.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/injectors/jit_uni_binary_injector.hpp new file mode 100644 index 0000000000000000000000000000000000000000..4938b1dc9e0e12cd57f79517ab9156dafa548a98 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/injectors/jit_uni_binary_injector.hpp @@ -0,0 +1,532 @@ +/******************************************************************************* +* Copyright 2020-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_UNI_BINARY_INJECTOR_HPP +#define CPU_X64_JIT_UNI_BINARY_INJECTOR_HPP + +#include +#include +#include +#include +#include +#include +#include + +#include "common/broadcast_strategy.hpp" +#include "common/c_types_map.hpp" +#include "common/primitive_attr.hpp" +#include "common/primitive_exec_types.hpp" +#include "cpu/binary_injector_utils.hpp" +#include "cpu/x64/cpu_isa_traits.hpp" +#include "cpu/x64/injectors/injector_utils.hpp" +#include "cpu/x64/jit_generator.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { +namespace binary_injector { +using dnnl::impl::cpu::binary_injector_utils::get_src1_desc; +using dnnl::impl::cpu::binary_injector_utils::prepare_binary_args; + +bool binary_args_broadcast_supported(const post_ops_t &post_ops, + const memory_desc_wrapper &dst_d, + const bcast_set_t &supported_strategy_set); + +bool any_binary_postop_rhs_non_scalar_broadcast( + const post_ops_t &post_ops, const memory_desc_wrapper &dst_d); +bool any_binary_postop_rhs_per_oc_broadcast(const post_ops_t &post_ops, + const memory_desc_wrapper &dst_d, + const bcast_set_t &supported_strategy_set); + +bool all_binary_postop_rhs_per_oc_broadcast(const post_ops_t &post_ops, + const memory_desc_wrapper &dst_d, + const bcast_set_t &supported_strategy_set, + const std::function &predicate); + +/* + * Represents params related to all binary post-ops right-hand side arguments + * (arg1) that don't change during jit_uni_binary_injector_t object lifetime + * and between compute_vector_range calls. + * + * @param rhs_dt_helper_vmm_idx - index of vmm helper used when loading data for + * calculations. Treated as hint from user. If inside compute_vector_range hint + * turns out to be invalid, it will be overwriten by register preserving logic inside + * binary injector. + * @param rhs_addr_reg - gpr register, used as the currently processed address of + * rhs tensor slice. Data of rhs(arg1) for the binary operation is loaded from address + * stored inside rhs_addr_reg. + * @param rhs_helper_reg - gpr register used as helper for calculations during data + * loading phase. + * @param rhs_addr_cache_reg - gpr register used for caching part of calculated + * offset, this register is always preserved. + * @param preserve_gpr_helpers - determines whether gpr registers specified above + * should be preserved (pushed to stack and poped back afterwords) between + * compute_vector_range calls. + * @param preserve_vmm_helper - determines whether vmm helper register specified + * above should be preserved between compute_vector_range calls. + * @param abi_param_offset - offset to rhs tensor from first binary post-op operation + * specified by user from runtime structure passed to kernel as abi param 1. + * @param dst_orig_offset - offset 0 to destination tensor + * @param dst_d - descriptor of destination tensor (result after applying all post-ops + * operations). + * @param tail_opmask - register with loaded by user mask, used in avx512 for load with + * tail handling. + * @param tail_size - size of processed tail in elements. + * @param use_exact_tail_scalar_bcast - in case of scalar broadcast user can disable + * loading data with tail, usually bcast through entire vector is faster (usually 1 instruction) + * vs. broadcasting limited by tail size (potentially several instructions). In case + * when user during storing ignores values from vmm above tail size, setting this option to + * false can result in better performance. + * @param reg_tail_size - register with loaded size of tail, used in sse41/avx/avx2 + * for load with tail in runtime. + */ +struct rhs_arg_static_params_t { + rhs_arg_static_params_t(std::size_t rhs_dt_helper_vmm_idx, + const Xbyak::Reg64 &rhs_addr_reg, + const Xbyak::Reg64 &rhs_helper_reg, + const Xbyak::Reg64 &rhs_addr_cache_reg, bool preserve_gpr_helpers, + bool preserve_vmm_helper, std::size_t abi_param_offset, + std::size_t dst_orig_offset, const memory_desc_wrapper &dst_d, + std::size_t tail_size = 0u, + bool use_exact_tail_scalar_bcast = false); + rhs_arg_static_params_t(std::size_t rhs_dt_helper_vmm_idx, + const Xbyak::Reg64 &rhs_addr_reg, + const Xbyak::Reg64 &rhs_helper_reg, + const Xbyak::Reg64 &rhs_addr_cache_reg, bool preserve_gpr_helpers, + bool preserve_vmm_helper, std::size_t abi_param_offset, + std::size_t dst_orig_offset, const memory_desc_wrapper &dst_d, + std::size_t tail_size, const Xbyak::Opmask &tail_opmask, + bool use_exact_tail_scalar_bcast); + rhs_arg_static_params_t(std::size_t rhs_dt_helper_vmm_idx, + const Xbyak::Reg64 &rhs_addr_reg, + const Xbyak::Reg64 &rhs_helper_reg, + const Xbyak::Reg64 &rhs_addr_cache_reg, bool preserve_gpr_helpers, + bool preserve_vmm_helper, std::size_t abi_param_offset, + std::size_t dst_orig_offset, const memory_desc_wrapper &dst_d, + std::size_t tail_size, const Xbyak::Opmask &tail_opmask, + const Xbyak::Reg64 ®_tail_size, + bool use_exact_tail_scalar_bcast); + + bool is_opmask_set() const noexcept { return is_opmask_set_; } + + mutable std::size_t rhs_dt_helper_vmm_idx; + Xbyak::Reg64 rhs_addr_reg; + Xbyak::Reg64 rhs_helper_reg; + Xbyak::Reg64 rhs_addr_cache_reg; + bool preserve_gpr_helpers; + bool preserve_vmm_helper; + std::size_t abi_param_offset; + std::size_t dst_orig_offset; + memory_desc_wrapper dst_d; + std::size_t tail_size; + Xbyak::Opmask tail_opmask; + bool use_exact_tail_scalar_bcast; + Xbyak::Reg64 reg_tail_size; + bool is_tail; + +private: + rhs_arg_static_params_t(std::size_t rhs_dt_helper_vmm_idx, + const Xbyak::Reg64 &rhs_addr_reg, + const Xbyak::Reg64 &rhs_helper_reg, + const Xbyak::Reg64 &rhs_addr_cache_reg, bool preserve_gpr_helpers, + bool preserve_vmm_helper, std::size_t abi_param_offset, + std::size_t dst_orig_offset, const memory_desc_wrapper &dst_d, + std::size_t tail_size, const Xbyak::Opmask &tail_opmask, + bool use_exact_tail_scalar_bcast, const Xbyak::Reg64 ®_tail_size, + bool is_opmask_set); + + bool is_opmask_set_; +}; + +/* + * Represents params required by jit_uni_binary_injector_t that don't change + * during it's entire lifetime. + * + * @param param1 - register storing abi param1. At the moment of calling + * compute_vector_range method can be different than the default one defined + * inside jit_generator. + * @param bcast_set_t supported_strategy_set - set allowing disabling particular + * bcast strategies + * @param rhs_arg_static_params - params related to all binary post-ops right-hand side + * arguments that don't change during entire lifetime of jit_uni_binary_injector_t + * object. + */ +struct static_params_t { + static_params_t(const Xbyak::Reg64 ¶m1, + const bcast_set_t &supported_strategy_set, + const rhs_arg_static_params_t &rhs_arg_static_params); + static_params_t(const Xbyak::Reg64 ¶m1, + const rhs_arg_static_params_t &rhs_arg_static_params); + + Xbyak::Reg64 param1; + const bcast_set_t supported_strategy_set; + rhs_arg_static_params_t rhs_arg_static_params; +}; + +/* + * Mode of data load with tail for rhs: + * STATIC - load based on given integer. + * DYNAMIC - load based on opmask or 64-bit register. + * DEFAULT - DYNAMIC for avx512, STATIC for others. + */ + +enum class tail_lode_mode_t { STATIC, DYNAMIC, DEFAULT }; + +/* + * Represents params passed to compute_vector_range method of + * jit_uni_binary_injector_t that can be different for each call. + * Contains configurable std::maps where key is vmm index and value is + * offset in elements. The offset value identifies tensor slice in particular + * vmm. This is utilized by broadcasting mechanism. Offset, depending on the + * implementation particular kernels, can be passed as value (usually during + * unrolling), inside operand, under memory address. + * + * @param vmm_idx_to_out_addr - vmm mapped to address of destination tensor with offset, + * used to calculate offset in no_broadcast strategy, but also in other strategies whose + * calculations are based on no_broadcast strategy. + * @param vmm_idx_to_out_reg - vmm mapped to register containing address of destination + * with offset, used to calculate offset in no_broadcast strategy, but also in other + * strategies whose calculations are based on no_broadcast strategy. + * @param vmm_idx_to_out_elem_off_val - vmm mapped to offset in elements passed as raw + * value intended to use in no_broadcast strategy, but also in other + * strategies whose calculations are based on no_broadcast strategy. + * @param vmm_tail_idx - vmm indices that contains data don't fill the whole vector (tail). + * @param is_dynamic_tail_load - determines whether to load with tail in + * runtime (based on the value from reg_tail_size or opmask) or based on given + * integer. + */ + +struct rhs_arg_dynamic_params_t { + std::map vmm_idx_to_out_addr; + std::map vmm_idx_to_out_reg; + std::map vmm_idx_to_out_elem_off_val; + + std::unordered_set vmm_tail_idx_; + tail_lode_mode_t tail_load_mode = tail_lode_mode_t::DEFAULT; +}; + +/* + * Checks if src1 data type is supported by binary injector. + */ +bool is_data_supported(cpu_isa_t isa, data_type_t data_type); + +/* + * Checks if broadcast of src1 is supported by binary injector. + */ +bool is_bcast_supported(const dnnl::impl::memory_desc_t &src1_desc, + const memory_desc_wrapper &dst_d, + const bcast_set_t &supported_strategy_set); + +/* + * Checks if binary injection for given args is supported. + */ +bool is_supported(cpu_isa_t isa, const dnnl::impl::memory_desc_t &src1_desc, + const memory_desc_wrapper &dst_d, + const bcast_set_t &supported_strategy_set); + +/* + * Main mechanism responsible for injecting binary postops supporting various + * isa: sse41, avx, avx2, avx512 with core, bf16 extensions as well as data + * types: f32, bf16, s32, u8, s8. + */ +template ::Vmm> +class jit_uni_binary_injector_t { +public: + jit_uni_binary_injector_t( + jit_generator *host, const static_params_t &static_params); + + /* + * Generates code of binary post_op injected to host primitive. Applied to + * ordered set of vector registers' indexes. Function loads appropriate + * slice of rhs tensor for computations based on internally determined + * broadcast strategy and information about stored data in particular vmm + * described inside rhs_arg_params. + */ + void compute_vector_range(const injector_utils::vmm_index_set_t &vmm_idxs, + std::size_t rhs_arg_idx, const dnnl_post_ops::entry_t &post_op, + const rhs_arg_dynamic_params_t &rhs_arg_params) const; + + /* + * Generates code of binary post_op injected to host primitive. Applied to + * range ). If not it returns new vmm idx value that will be + * used as temporary vmm in future computations. + */ + int adjust_temp_vmm_hint( + int user_hint, int start_idx, int end_idx, int max_vmm_idx) const; + /* + * Taking into account rhs_broadcasting_strategy and information from user + * about tensor slice (rhs_arg_params) stored in Vmm(vmm_idx) calculates + * address of rhs tensor slice needed for binary operation and returns + * ptr to it. + */ + Xbyak::Address prepare_rhs_arg_addr(std::size_t vmm_idx, + std::size_t rhs_arg_idx, const dnnl_post_ops::entry_t &post_op, + const rhs_arg_dynamic_params_t &rhs_arg_params, + const broadcasting_strategy_t rhs_broadcasting_strategy, + bool is_first) const; + /* + * Loads data and applies particular binary operation. + */ + void inject_binary(const dnnl_post_ops::entry_t &post_op, Vmm dst, + const Xbyak::Address &rhs_addr, bool with_tail, + const tail_lode_mode_t tail_load_mode) const; + + /* + * Helper functions responsible for preparing rhs tensor slice address. + */ + void append_no_broadcast_offset( + const std::map &vmm_idx_to_out_addr, + const std::map &vmm_idx_to_out_reg, + const std::map &vmm_idx_to_out_elem_off_val, + int vmm_idx, const Xbyak::Reg64 &addr_reg, + const Xbyak::Reg64 &tmp_reg, std::size_t elem_size_bytes, + bool is_first) const; + void calculate_no_broadcast_base( + Xbyak::Address addr, const Xbyak::Reg64 &out_reg) const; + void calculate_no_broadcast_partial(const std::size_t offset, + const Xbyak::Reg64 &out_reg, std::size_t elem_size_bytes) const; + + void append_oc_offset( + const std::map &vmm_idx_to_out_addr, + const std::map &vmm_idx_to_out_reg, + const std::map &vmm_idx_to_out_elem_off_val, + int vmm_idx, const Xbyak::Reg64 &addr_reg, + const Xbyak::Reg64 &tmp_reg, std::size_t elem_size_bytes, + bool is_first) const; + void calculate_oc_ncsp_base( + const dim_t *strides, const Xbyak::Reg64 &tmp_reg) const; + void calculate_oc_ncsp_partial(const dim_t *strides, + const std::size_t offset, const Xbyak::Reg64 &tmp_reg, + std::size_t elem_size_bytes) const; + void calculate_oc_blocked_base( + const dim_t *strides, const Xbyak::Reg64 &tmp_reg) const; + void calculate_oc_blocked_partial(const dim_t *strides, + const std::size_t offset, const Xbyak::Reg64 &tmp_reg, + std::size_t elem_size_bytes) const; + void calculate_oc_nspc_base( + const dim_t *strides, const Xbyak::Reg64 &tmp_reg) const; + void calculate_oc_nspc_partial(const dim_t *strides, + const std::size_t offset, const Xbyak::Reg64 &tmp_reg, + std::size_t elem_size_bytes) const; + void calculate_oc_cspn_base( + const dim_t *strides, const Xbyak::Reg64 &tmp_reg) const; + void calculate_oc_cspn_partial(const dim_t *strides, + const std::size_t offset, const Xbyak::Reg64 &tmp_reg, + std::size_t elem_size_bytes) const; + + void append_mb_sp_offset( + const std::map &vmm_idx_to_out_addr, + const std::map &vmm_idx_to_out_reg, + const std::map &vmm_idx_to_out_elem_off_val, + int vmm_idx, const Xbyak::Reg64 &addr_reg, + const Xbyak::Reg64 &tmp_reg, std::size_t elem_size_bytes, + bool is_first) const; + void calculate_mb_sp_ncsp_base( + const dim_t *strides, const Xbyak::Reg64 &tmp_reg) const; + void calculate_mb_sp_ncsp_partial(const dim_t *strides, + const std::size_t offset, const Xbyak::Reg64 &tmp_reg, + std::size_t elem_size_bytes) const; + void calculate_mb_sp_blocked_base( + const dim_t *strides, const Xbyak::Reg64 &tmp_reg) const; + void calculate_mb_sp_blocked_partial(const dim_t *strides, + const std::size_t offset, const Xbyak::Reg64 &tmp_reg, + std::size_t elem_size_bytes) const; + void calculate_mb_sp_nspc_base( + const dim_t *strides, const Xbyak::Reg64 &tmp_reg) const; + void calculate_mb_sp_nspc_partial(const dim_t *strides, + const std::size_t offset, const Xbyak::Reg64 &tmp_reg, + std::size_t elem_size_bytes) const; + void calculate_mb_sp_cspn_base( + const dim_t *strides, const Xbyak::Reg64 &tmp_reg) const; + void calculate_mb_sp_cspn_partial(const dim_t *strides, + const std::size_t offset, const Xbyak::Reg64 &tmp_reg, + std::size_t elem_size_bytes) const; + + void append_mb_w_offset( + const std::map &vmm_idx_to_out_addr, + const std::map &vmm_idx_to_out_reg, + const std::map &vmm_idx_to_out_elem_off_val, + int vmm_idx, const Xbyak::Reg64 &addr_reg, + const Xbyak::Reg64 &tmp_reg, std::size_t elem_size_bytes, + bool is_first) const; + void calculate_mb_w_ncsp_base( + const dim_t *strides, const Xbyak::Reg64 &tmp_reg) const; + void calculate_mb_w_ncsp_partial(const dim_t *strides, + const std::size_t offset, const Xbyak::Reg64 &tmp_reg, + std::size_t elem_size_bytes) const; + void calculate_mb_w_blocked_base( + const dim_t *strides, const Xbyak::Reg64 &tmp_reg) const; + void calculate_mb_w_blocked_partial(const dim_t *strides, + const std::size_t offset, const Xbyak::Reg64 &tmp_reg, + std::size_t elem_size_bytes) const; + void calculate_mb_w_nspc_base( + const dim_t *strides, const Xbyak::Reg64 &tmp_reg) const; + void calculate_mb_w_nspc_partial(const dim_t *strides, + const std::size_t offset, const Xbyak::Reg64 &tmp_reg, + std::size_t elem_size_bytes) const; + void calculate_mb_w_cspn_base( + const dim_t *strides, const Xbyak::Reg64 &tmp_reg) const; + void calculate_mb_w_cspn_partial(const dim_t *strides, + const std::size_t offset, const Xbyak::Reg64 &tmp_reg, + std::size_t elem_size_bytes) const; + + void append_w_offset( + const std::map &vmm_idx_to_out_addr, + const std::map &vmm_idx_to_out_reg, + const std::map &vmm_idx_to_out_elem_off_val, + int vmm_idx, const Xbyak::Reg64 &addr_reg, + const Xbyak::Reg64 &tmp_reg, std::size_t elem_size_bytes, + bool is_first) const; + void calculate_w_ncsp_base( + const dim_t *strides, const Xbyak::Reg64 &tmp_reg) const; + void calculate_w_ncsp_partial(const dim_t *strides, + const std::size_t offset, const Xbyak::Reg64 &tmp_reg, + std::size_t elem_size_bytes) const; + void calculate_w_blocked_base( + const dim_t *strides, const Xbyak::Reg64 &tmp_reg) const; + void calculate_w_blocked_partial(const dim_t *strides, + const std::size_t offset, const Xbyak::Reg64 &tmp_reg, + std::size_t elem_size_bytes) const; + void calculate_w_nspc_base( + const dim_t *strides, const Xbyak::Reg64 &tmp_reg) const; + void calculate_w_nspc_partial(const dim_t *strides, + const std::size_t offset, const Xbyak::Reg64 &tmp_reg, + std::size_t elem_size_bytes) const; + void calculate_w_cspn_base( + const dim_t *strides, const Xbyak::Reg64 &tmp_reg) const; + void calculate_w_cspn_partial(const dim_t *strides, + const std::size_t offset, const Xbyak::Reg64 &tmp_reg, + std::size_t elem_size_bytes) const; + + template + typename std::enable_if::value + || std::is_same::value>::type + execute_cmp_binary(const Vmm &dst, const Vmm &lhs, const T &rhs, + const unsigned int cmp_predicate) const; + template + typename std::enable_if::value + || std::is_same::value)>::type + execute_cmp_binary(const Vmm &dst, const Vmm &lhs, const T &rhs, + const unsigned int cmp_predicate) const; + template + void execute_binary(alg_kind_t binary_alg, const Vmm &dst, const Vmm &lhs, + const T &rhs) const; + void execute_prelu(const Vmm &dst, const Xbyak::Operand &rhs) const; + + /* + * Used in scalar broadcast strategy, broadcasting single value of given + * data type over entire vector Vmm register. + */ + void execute_broadcast(const data_type_t &data_type, const Vmm &tmp_reg, + const Xbyak::Address &rhs_addr, + const tail_lode_mode_t tail_load_mode, + bool with_tail = false) const; + void load_rhs(const data_type_t &data_type, const Vmm &tmp_reg, + const Xbyak::Address &rhs_addr, + const tail_lode_mode_t tail_load_mode, + bool with_tail = false) const; + void execute_broadcast_tail_with_opmask(const data_type_t &data_type, + const Vmm &tmp_reg, const Xbyak::Address &rhs_addr) const; + void execute_broadcast_tail_statically(const data_type_t &data_type, + const Vmm &tmp_reg, const Xbyak::Address &rhs_addr, + const std::size_t tail_size) const; + void execute_broadcast_tail_with_gpr(const data_type_t &data_type, + const Vmm &tmp_reg, const Xbyak::Address &rhs_addr) const; + void load_rhs_tail_dynamically_with_opmask(const data_type_t &data_type, + const Vmm &tmp_vmm, const Xbyak::Address &rhs_addr) const; + void load_rhs_tail_dynamically_with_gpr( + const data_type_t &data_type, const Vmm &tmp_vmm) const; + void load_rhs_tail_statically(const data_type_t &data_type, + const Vmm &tmp_vmm, const Xbyak::Address &rhs_addr) const; + void execute_broadcast_no_tail(const data_type_t &data_type, + const Vmm &tmp_vmm, const Xbyak::Address &rhs_addr) const; + void execute_broadcast_s8u8_no_tail(const data_type_t &data_type, + const Vmm &tmp_vmm, const Xbyak::Address &rhs_addr) const; + void load_rhs_no_tail(const data_type_t &data_type, const Vmm &tmp_reg, + const Xbyak::Address &rhs_addr) const; + void load_rhs_i8_no_tail(const data_type_t &data_type, const Vmm &tmp_reg, + const Xbyak::Address &rhs_addr) const; + void cvt_to_f32(const Vmm &tmp_reg) const; + /* + * Returns pair consisting of flag indication preservation is needed for vmm + * index in second member that should be used as temporary vmm inside inject + * binary. + */ + std::pair should_preserve_vmm(int curr_idx, int vmm_hint, + int max_vmm_idx, bool dt_helper_vmm_needed) const; + /* + * Used in isa != avx512 where m32bcst is not supported, replaces ptr_b + * with ptr. + */ + Xbyak::Address remove_bcast_bit(const Xbyak::Address &rhs_addr) const; + + /* + * Returns an Opmask register, that can be used from temporary use. + * The returned register will be different from tail_opmask. + * Note: The Opmask register returned may need to be preserved. + */ + Xbyak::Opmask get_aux_kmask() const; + + jit_generator *host_; + const rhs_arg_static_params_t rhs_arg_static_params_; + const Xbyak::Reg64 param1_; + const bcast_set_t supported_strategy_set_; + const bool is_avx512_ = is_superset(isa, avx512_core); + const bool is_avx512_core_fp16_ = is_superset(isa, avx512_core_fp16); + + static constexpr int sizeof_reg64 = 8; + /* + * Instructions from SSE/AVX used to compute binary result like vaddps where + * second operand is memory, require mem operand to be 16/32 byte explicitly + * aligned. (Intel Manual chapter 2.4). + * Rule is relaxed from AVX2 (Intel Manual chapter 14.9). + * When using benchdnn zmalloc_protect doesn't guarantee that tensor memory + * address is 64 byte aligned, which can cause segmentation fault. + */ + static constexpr bool binary_op_with_unaligned_mem_operand_allowed_ + = !utils::one_of(isa, avx, sse41); +}; + +} // namespace binary_injector +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/injectors/jit_uni_eltwise_injector.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/injectors/jit_uni_eltwise_injector.hpp new file mode 100644 index 0000000000000000000000000000000000000000..251dcab504cf0c25f87e6fdc4b4f2e92913f3aea --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/injectors/jit_uni_eltwise_injector.hpp @@ -0,0 +1,348 @@ +/******************************************************************************* +* Copyright 2019-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_UNI_ELTWISE_INJECTOR_HPP +#define CPU_X64_JIT_UNI_ELTWISE_INJECTOR_HPP + +#include +#include + +#include "common/c_types_map.hpp" +#include "common/primitive_attr.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/x64/injectors/injector_utils.hpp" +#include "cpu/x64/jit_generator.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +namespace eltwise_injector { +struct static_params_t { + + static_params_t(bool save_state = true, + Xbyak::Reg64 p_table = Xbyak::util::rax, + Xbyak::Opmask k_mask = Xbyak::Opmask(1), bool is_fwd = true, + bool use_dst = false, bool preserve_vmm = true, + bool preserve_p_table = true) + : save_state(save_state) + , p_table(p_table) + , k_mask(k_mask) + , is_fwd(is_fwd) + , use_dst(use_dst) + , preserve_vmm(preserve_vmm) + , preserve_p_table(preserve_p_table) {} + + bool save_state; + Xbyak::Reg64 p_table; + Xbyak::Opmask k_mask; + bool is_fwd; + bool use_dst; + bool preserve_vmm; + bool preserve_p_table; +}; + +/* + * Checks if isa is supported by eltwise injector. + */ +bool is_isa_supported(cpu_isa_t isa); + +/* + * Checks if eltwise algorithm is supported by eltwise injector. + */ +bool is_alg_supported(alg_kind_t alg); + +/* + * Checks if eltwise injection for given args is supported. + */ +bool is_supported(cpu_isa_t isa, alg_kind_t alg); + +} // namespace eltwise_injector + +template ::Vmm> +struct jit_uni_eltwise_injector_f32 { + using Vmm = Wmm; + + // Arguments description: + // host - jit generator which is filled with instructions + // alg, alpha, beta, scale - user eltwise arguments + // save_state - when true, preserves on stack vmm_aux registers preventing + // results spoiling. Restores them when done in injector_postamble(). + // p_table - GPR where table label is stored to get access for pre-defined + // constants used in alg codes. + // k_mask - k_register to operate with masks in alg codes. + // is_fwd - when true, computes d = alg(s), otherwise, computes ds = alg'(s) + // - algorithm derivative. + // use_dst - defines whether source or destination point is passed to alg + // code. Depends on algorithm. See `_use_dst_for_bwd` algs definition. + jit_uni_eltwise_injector_f32(jit_generator *host, alg_kind_t alg, + float alpha, float beta, float scale, bool save_state = true, + Xbyak::Reg64 p_table = Xbyak::util::rax, + Xbyak::Opmask k_mask = Xbyak::Opmask(1), bool is_fwd = true, + bool use_dst = false, bool preserve_vmm = true, + bool preserve_p_table = true) + : alg_(alg) + , alpha_(alpha) + , beta_(beta) + , scale_(scale) + , h(host) + , save_state_(save_state) + , p_table(p_table) + , k_mask(k_mask) + , is_fwd_(is_fwd) + , use_dst_(use_dst) + , preserve_vmm_(preserve_vmm) + , preserve_p_table_(preserve_p_table) { + assert(eltwise_injector::is_supported(isa, alg_)); + + register_table_entries(); + } + + jit_uni_eltwise_injector_f32(jit_generator *host, + const post_ops_t::entry_t::eltwise_t &eltwise, + bool save_state = true, Xbyak::Reg64 p_table = Xbyak::util::rax, + Xbyak::Opmask k_mask = Xbyak::Opmask(1), bool is_fwd = true, + bool use_dst = false, bool preserve_vmm = true, + bool preserve_p_table = true) + : jit_uni_eltwise_injector_f32(host, eltwise.alg, eltwise.alpha, + eltwise.beta, eltwise.scale, save_state, p_table, k_mask, + is_fwd, use_dst, preserve_vmm, preserve_p_table) {} + + void compute_vector_range(size_t start_idx, size_t end_idx); + void compute_vector_range(const injector_utils::vmm_index_set_t &vmm_idxs); + void compute_vector(size_t idx) { compute_vector_range({idx}); } + void prepare_table(bool gen_table = true); + void load_table_addr() { h->mov(p_table, l_table); } + +private: + const alg_kind_t alg_; + const float alpha_; + const float beta_; + const float scale_; + + jit_generator *const h; + + const bool save_state_; + const Xbyak::Reg64 p_table; + const Xbyak::Opmask k_mask; + const bool is_fwd_; + const bool use_dst_; + const bool preserve_vmm_; + const bool preserve_p_table_; + + Xbyak::Label l_table; + + // if only the injector was inherited from jit_generator... + enum { + _cmp_eq_oq = jit_generator::_cmp_eq_oq, + _cmp_neq_uq = jit_generator::_cmp_neq_uq, + _cmp_lt_os = jit_generator::_cmp_lt_os, + _cmp_le_os = jit_generator::_cmp_le_os, + _cmp_ge_os = jit_generator::_cmp_nlt_us, + _cmp_gt_os = jit_generator::_cmp_nle_us, + _op_floor = jit_generator::_op_floor, + _op_mxcsr = jit_generator::_op_mxcsr + }; + + const bool is_avx512 = is_superset(isa, avx512_core); + + static constexpr size_t vlen = vreg_traits::vlen; + static constexpr size_t preserved_vecs_max = 6; + static constexpr size_t preserved_gprs_max = 5; + static constexpr size_t vecs_count = cpu_isa_traits::n_vregs; + static constexpr int n_mantissa_bits = 23; + static constexpr int k_mask_size = 8; + + bool preserve_vec_for_avx = false; + + size_t vecs_to_preserve = 0; + size_t preserved_vecs_count = 0; + size_t preserved_vec_idxs[preserved_vecs_max] = {0}; + size_t preserved_gpr_idxs[preserved_gprs_max] = {0}; + injector_utils::vmm_index_set_iterator_t start_idx_tail; + + Vmm vmm_mask, vmm_aux0, vmm_aux1, vmm_aux2, vmm_aux3, vmm_aux4, vmm_tmp; + Xbyak::Ymm ymm_tmp; + Xbyak::Xmm xmm_tmp; + + size_t aux_vecs_count(); + size_t aux_gprs_count(); + + void compute_body( + const injector_utils::vmm_index_set_iterator_t &start_idx_it, + const injector_utils::vmm_index_set_iterator_t &end_idx_it); + void injector_preamble(const injector_utils::vmm_index_set_t &vmm_idxs); + void injector_preamble_tail( + const injector_utils::vmm_index_set_iterator_t &start_idx_it); + void injector_postamble(); + void assign_regs(); + void vec_shift(const Vmm &vmm_dst, const Vmm &vmm_src, bool shift_left, + const int imm); + void compute_cmp_mask(const Vmm &vmm_src, + const Xbyak::Operand &compare_operand, int cmp_predicate); + void blend_with_mask(const Vmm &vmm_dst, const Xbyak::Operand &src); + void test_mask(); + + void exp_compute_vector_fwd(const Vmm &vmm_src); + void relu_compute_vector_fwd(const Vmm &vmm_src); + void relu_zero_ns_compute_vector_fwd(const Vmm &vmm_src); + void elu_compute_vector_fwd(const Vmm &vmm_src); + void tanh_compute_vector_fwd(const Vmm &vmm_src); + void square_compute_vector_fwd(const Vmm &vmm_src); + void abs_compute_vector_fwd(const Vmm &vmm_src); + void sqrt_compute_vector_fwd(const Vmm &vmm_src); + void linear_compute_vector_fwd(const Vmm &vmm_src); + void soft_relu_compute_vector_fwd(const Vmm &vmm_src); + void mish_compute_vector_fwd(const Vmm &vmm_src); + void logistic_compute_vector_fwd(const Vmm &vmm_src); + void gelu_tanh_compute_vector_fwd(const Vmm &vmm_src); + void swish_compute_vector_fwd(const Vmm &vmm_src); + void log_compute_vector_fwd(const Vmm &vmm_src); + void clip_compute_vector_fwd(const Vmm &vmm_src); + void pow_compute_vector_fwd(const Vmm &vmm_src); + void gelu_erf_compute_vector_fwd(const Vmm &vmm_src); + void gelu_erf_minimax_approx_compute_vector_fwd(const Vmm &vmm_src); + void round_compute_vector_fwd(const Vmm &vmm_src); + void hardswish_compute_vector_fwd(const Vmm &vmm_src); + void hardsigmoid_compute_vector_fwd(const Vmm &vmm_src); + + void exp_compute_vector_bwd(const Vmm &vmm_src); + void relu_compute_vector_bwd(const Vmm &vmm_src); + void elu_compute_vector_bwd(const Vmm &vmm_src); + void tanh_compute_vector_bwd(const Vmm &vmm_src); + void square_compute_vector_bwd(const Vmm &vmm_src); + void abs_compute_vector_bwd(const Vmm &vmm_src); + void sqrt_compute_vector_bwd(const Vmm &vmm_src); + void linear_compute_vector_bwd(const Vmm &vmm_src); + void soft_relu_compute_vector_bwd(const Vmm &vmm_src); + void logistic_compute_vector_bwd(const Vmm &vmm_src); + void mish_compute_vector_bwd(const Vmm &vmm_src); + void gelu_tanh_compute_vector_bwd(const Vmm &vmm_src); + void swish_compute_vector_bwd(const Vmm &vmm_src); + void log_compute_vector_bwd(const Vmm &vmm_src); + void clip_compute_vector_bwd(const Vmm &vmm_src); + void pow_compute_vector_bwd(const Vmm &vmm_src); + void gelu_erf_compute_vector_bwd(const Vmm &vmm_src); + void hardswish_compute_vector_bwd(const Vmm &vmm_src); + void hardsigmoid_compute_vector_bwd(const Vmm &vmm_src); + + enum key_t { + scale = 0, // scale argument + alpha, // alpha argument + beta, // beta argument + zero, // 0.f + half, // 0.5f + one, // 1.f or mask for exponent bits + two, // 2.f + three, // 3.f + six, // 6.f + minus_one, // -1.f or changes sign to opposite + minus_two, // -2.f + minus_three, // -3.f + ln2f, // 0.69314718f + positive_mask, // changes sign to positive + sign_mask, // gets sign value + exponent_bias, // (127 = 2^7 - 1), gets exponent bits + exp_log2ef, // 1.44269502f - formula-based for approx + exp_ln_flt_max_f, // logf(FLT_MAX) - max normal value + exp_ln_flt_min_f, // logf(FLT_MIN) - min normal value + exp_pol, // see correspondent table for float values + // e^(2*x)+2*e^x+2 = FLT_MAX; x =~ 44.36141952603634 + fwd_mish_max_x_for_equation_f, + // e^x(e^3x+4e^2x+e^x*(6+4*x)+4*(1+x)) = FLT_MAX; x =~ 22.18070976278534 + bwd_mish_max_x_for_equation_f, + tanh_idx_bias, // bias applied during index computation + tanh_idx_mask, // mask applied to extract index + tanh_linear_ubound, // arg below which tanh(x) = x + tanh_saturation_lbound, // arg after which tanh(x) = 1.f + tanh_pol_table, // table of polynomial coefficients + soft_relu_one_twenty_six, // 126.f + soft_relu_mantissa_sign_mask, // mask for mantissa bits and sign + soft_relu_pol, // see correspondent table for float values + gelu_tanh_fitting_const, // 0.044715f + gelu_tanh_fitting_const_times_three, // 0.134145f + gelu_tanh_sqrt_two_over_pi, // sqrtf(2.f/pi) = 0.797884f + // 0.3275911f - implementation based for approx + gelu_erf_Abramowitz_Stegun_approx_const, + gelu_erf_Abramowitz_Stegun_one_over_sqrt_two, // 1.f / sqrtf(2.f) + // 1.f / sqrtf(pi) = 0.564190f + gelu_erf_Abramowitz_Stegun_one_over_sqrt_pi, + // see correspondent table for float values + gelu_erf_Abramowitz_Stegun_pol, + gelu_erf_minimax_pol, // see correspondent table for float values + gelu_erf_idx_bias, // bias applied to compute table index + gelu_erf_rbound, // upper bound at which we clamp erf at 1 + gelu_erf_one, // just the integer value 1, used for index clamping + gelu_erf_twenty_three, // just the integer value 23, used for index clamping + gelu_erf_twenty_four, // just the integer value 24, used for index clamping + log_inf, // inf + log_minus_inf, // -inf + log_qnan, // qnan + log_mantissa_mask, // gets mantissa bits + log_full_k_reg_mask, // sets k_register with all bits of 1 + log_full_vector_reg_mask, // sets vector register will all bits of 1 + log_five_bit_offset, // 5 bits off (31 = 2^5 - 1) + log_pol, // see correspondent table for float values + log_predefined_vals, // see correspondent table for float values + undef_key, + }; + + size_t table_off(key_t key, size_t key_off_val_shift = 0) { + // assumption: all table entries sharing the same key also + // share their broadcast property + // TODO: enforce through data structure + const auto it = entry_map_.find(key); // search an entry for a key + assert(it != entry_map_.end()); + const auto &te = (*it).second; + const auto scale = te.bcast ? vlen : sizeof(table_entry_val_t); + return te.off + key_off_val_shift * scale; + } + Xbyak::Address table_val(key_t key, size_t key_off_val_shift = 0) { + auto off = table_off(key, key_off_val_shift); + return h->ptr[p_table + off]; + } + + // we accept only 32bit hexadecimal table values to avoid any rounding + using table_entry_val_t = uint32_t; + using table_entry_offset_t = size_t; // offsets are in bytes wrt p_table + using table_entry_bcast_t = bool; // true => bcast value + + struct table_entry_t { + table_entry_val_t val; + table_entry_bcast_t bcast; + }; + struct mapped_table_entry_t { + table_entry_offset_t off; + table_entry_val_t val; + table_entry_bcast_t bcast; + }; + + using table_t = std::multimap; + using mapped_table_t = std::multimap; + + void register_table_entries(); + mapped_table_t entry_map_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/injectors/jit_uni_postops_injector.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/injectors/jit_uni_postops_injector.hpp new file mode 100644 index 0000000000000000000000000000000000000000..491b674f62253fcd706a127ac68d7bf39a052013 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/injectors/jit_uni_postops_injector.hpp @@ -0,0 +1,167 @@ +/******************************************************************************* +* Copyright 2020-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ +#ifndef CPU_X64_JIT_UNI_POSTOPS_INJECTOR_HPP +#define CPU_X64_JIT_UNI_POSTOPS_INJECTOR_HPP + +#include +#include +#include + +#include "common/c_types_map.hpp" +#include "common/primitive_attr.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" +#include "cpu/x64/injectors/injector_utils.hpp" +#include "cpu/x64/injectors/jit_uni_binary_injector.hpp" +#include "cpu/x64/injectors/jit_uni_eltwise_injector.hpp" +#include "cpu/x64/jit_generator.hpp" +#include + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { +namespace injector { + +/* + * Allows specifying custom injector function for given post-op type - one + * function per primitive. There are post-ops type (example: sum) that don't + * have specialized injector. They heavily rely on kernel specific intrnals, + * which makes the generalization unreasonable. As so user can prepare internal + * kernel lambda and pass it explicitly to injector. + */ +using lambda_jit_injectors_t + = std::map>; + +struct post_ops_ok_args_t; +/* + * Checks if postops injection for given args is supported. + */ +bool is_supported(const post_ops_ok_args_t &post_ops_ok_args); + +/* + * Main mechanism of handling various post-ops types. It utilizes internally + * specialized injectors to generate post-ops code to host primitive. Random + * order of post-ops is supported. + */ +template ::Vmm> +class jit_uni_postops_injector_t { +public: + /* + * @param host - user primitive where post-ops generated code is + * injected + * @param post_ops - struct representing requested post-ops chain + * @binary_static_params - static params needed for binary_injector. + * see: jit_uni_binary_injector.hpp for more info. + * @param eltwise_static_params - allows user specify non default + * params for eltwise_injector + * @param lambda_jit_injectors - allows user specify custom injector + * function for given post-op type + */ + jit_uni_postops_injector_t(jit_generator *host, const post_ops_t &post_ops, + const binary_injector::static_params_t &binary_static_params); + jit_uni_postops_injector_t(jit_generator *host, const post_ops_t &post_ops, + const binary_injector::static_params_t &binary_static_params, + const lambda_jit_injectors_t &lambda_jit_injectors); + jit_uni_postops_injector_t(jit_generator *host, const post_ops_t &post_ops, + const binary_injector::static_params_t &binary_static_params, + const eltwise_injector::static_params_t &eltwise_static_params); + jit_uni_postops_injector_t(jit_generator *host, const post_ops_t &post_ops, + const binary_injector::static_params_t &binary_static_params, + const eltwise_injector::static_params_t &eltwise_static_params, + const lambda_jit_injectors_t &lambda_jit_injectors); + + /* + * Generates code of post_ops chain injected to host primitive. Applied to + * ordered set of vector registers' indexes. + * + * @rhs_arg_params: see jit_uni_binary_injector description + */ + void compute_vector_range(const injector_utils::vmm_index_set_t &vmm_idxs, + const binary_injector::rhs_arg_dynamic_params_t &rhs_arg_params); + + void compute_vector_range(const injector_utils::vmm_index_set_t &vmm_idxs); + + /* + * Generates code of post_ops chain injected to host primitive. Applied to + * range > + alg_to_eltwise_injector_; + std::unique_ptr> + binary_injector_; + lambda_jit_injectors_t lambda_jit_injectors_; +}; + +enum post_op_type { sum = 0, eltwise, binary, prelu }; + +struct post_ops_ok_args_t { + post_ops_ok_args_t(const cpu_isa_t isa, + const std::vector &accepted_post_op_types, + const post_ops_t &post_ops, const memory_desc_wrapper *dst_d, + const bool sum_at_pos_0_only, const bool sum_requires_scale_one, + const bool sum_requires_zp_zero = true, + const bool sum_requires_same_params = true, + const bcast_set_t &enabled_bcast_strategy = default_strategies()); + + const cpu_isa_t isa; + const std::vector &accepted_post_op_types; + const post_ops_t &post_ops; + const memory_desc_wrapper *dst_d; + const bool sum_at_pos_0_only; + const bool sum_requires_scale_one; + const bool sum_requires_zp_zero; + const bool sum_requires_same_params; + const bcast_set_t enabled_bcast_strategy; +}; + +bool post_ops_ok(const post_ops_ok_args_t &args); + +} // namespace injector +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/ip_convolution.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/ip_convolution.hpp new file mode 100644 index 0000000000000000000000000000000000000000..0416443120e6f61af45889e3766d3ec021ac3533 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/ip_convolution.hpp @@ -0,0 +1,458 @@ +/******************************************************************************* +* Copyright 2021-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_IP_CONVOLUTION_HPP +#define CPU_X64_IP_CONVOLUTION_HPP + +#include + +#include "common/c_types_map.hpp" +#include "common/primitive.hpp" +#include "common/primitive_desc_iterator.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_convolution_pd.hpp" +#include "cpu/cpu_inner_product_pd.hpp" + +#include "cpu/x64/cpu_isa_traits.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +namespace { + +status_t reshape_dst(memory_desc_t *o_md, const memory_desc_t *i_md) { + dims_t reduce {}; + const dim_t ndims = 2; // dst is always nc for inner product + // conv to ip: remove spatial + for (int d = 0; d < ndims; ++d) + reduce[d] = i_md->dims[d]; + + return memory_desc_reshape(*o_md, *i_md, ndims, reduce); +} + +status_t maybe_reshape_weights(memory_desc_t *o_md, const memory_desc_t *i_md, + bool with_groups, bool to_ip = false) { + dims_t reduce {}; + const dim_t ndims = i_md->ndims + (to_ip ? -1 : +1) * with_groups; + if (to_ip) { + // conv to ip: maybe remove groups + for (int d = 0; d < ndims; ++d) + reduce[d] = i_md->dims[d + with_groups]; + } else { + // ip to conv: maybe restore groups + if (with_groups) reduce[0] = 1; + for (int d = 0; d < ndims; ++d) + reduce[d + with_groups] = i_md->dims[d]; + } + + return memory_desc_reshape(*o_md, *i_md, ndims, reduce); +} + +status_t check_conv_ip(convolution_pd_t *self) { + // Check if convolution is equivalent to inner product + const bool is_ip_applicable = true + // no dilations + && utils::everyone_is(0, self->KDD(), self->KDH(), self->KDW()) + // no "left" padding + && utils::everyone_is( + 0, self->padFront(), self->padT(), self->padL()) + // no "right" padding + && utils::everyone_is( + 0, self->padBack(), self->padB(), self->padR()) + // no non-trivial groups or output spatial + && utils::everyone_is( + 1, self->G(), self->OD(), self->OH(), self->OW()) + // only unit stride + && utils::everyone_is(1, self->KSD(), self->KSH(), self->KSW()); + if (!is_ip_applicable) return status::unimplemented; + + // Simple heuristic to only target arches and shapes that benefit. + // TODO: Extend to other arches and shapes as performance allows. + const dim_t ks = self->KD() * self->KH() * self->KW(); + const dim_t ks_threshold = 27; // empirical + const bool is_performant + = 1 < self->MB() && ks > ks_threshold && mayiuse(avx512_core); + if (!is_performant) return status::unimplemented; + + return status::success; +} + +status_t check_tag(memory_desc_t &md, const format_tag_t tag) { + const memory_desc_wrapper mdw(&md); + if (mdw.matches_one_of_tag(tag) == format_tag::undef) + return status::unimplemented; + return status::success; +} + +status_t set_and_or_check_formats(const convolution_desc_t &desc, + memory_desc_t &src_md, memory_desc_t &weights_md, memory_desc_t &dst_md, + memory_desc_t &bias_md, primitive_attr_t &attr) { + using namespace format_tag; + auto atag = utils::pick(src_md.ndims - 3, nwc, nhwc, ndhwc); + const bool is_fwd = utils::one_of(desc.prop_kind, + prop_kind::forward_training, prop_kind::forward_inference); + const bool with_bias = desc.prop_kind != prop_kind::backward_data; + + // Check that nspc is the default layout for convolutions, + // or that expected performance gain outweights potential + // cost of extra reorders. + // Currently this means: + // - int8 with any forward prop_kind on any isa + // - fp32/bf16 with any prop_kind on avx512_core and higher + // - f16 + const auto wei_dt = weights_md.data_type; + const bool is_set_allowed = false + || (utils::one_of(wei_dt, data_type::f32, data_type::bf16) + && mayiuse(avx512_core)) + || (is_fwd && wei_dt == data_type::s8) + || (wei_dt == data_type::f16 && mayiuse(avx512_core_fp16)); + + // NOTE: Only plain layouts should be supported since the dims of + // dst_md_ must be reshaped from {N, C, H, W} to {N, C}. If the + // conv layout is blocked by channel, then the ip layout will also + // be blocked by channel (eg nChw16c -> nC16c). This can lead to + // deployment of reference ip as well as strange weights layouts. + if (is_set_allowed && src_md.format_kind == format_kind::any) + CHECK(memory_desc_init_by_tag(src_md, atag)); + else + CHECK(check_tag(src_md, atag)); + if (is_set_allowed && dst_md.format_kind == format_kind::any) + CHECK(memory_desc_init_by_tag(dst_md, atag)); + else + CHECK(check_tag(dst_md, atag)); + if (with_bias && bias_md.format_kind != format_kind::undef) { + auto btag = x; + if (bias_md.format_kind == format_kind::any) + CHECK(memory_desc_init_by_tag(bias_md, btag)); + else + CHECK(check_tag(bias_md, btag)); + } + return attr.set_default_formats(&dst_md); +} + +} // namespace + +struct ip_convolution_fwd_t : public primitive_t { + struct pd_t : public cpu_convolution_fwd_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const convolution_fwd_pd_t *hint_fwd_pd) + : cpu_convolution_fwd_pd_t(adesc, attr, hint_fwd_pd) {} + + pd_t(const pd_t &other) + : cpu_convolution_fwd_pd_t(other) + , ip_pd_(other.ip_pd_->clone()) + , name_(other.name_) {} + + ~pd_t() = default; + + DECLARE_COMMON_PD_T(name_.c_str(), ip_convolution_fwd_t); + + status_t init_ip(engine_t *engine) { + inner_product_desc_t ipd; + CHECK(ip_desc_create(&ipd)); + primitive_desc_iterator_t it( + engine, (op_desc_t *)&ipd, attr(), nullptr); + if (!it.is_initialized()) return status::out_of_memory; + + while (++it != it.end()) { + ip_pd_ = *it; + const bool ok = ip_pd_->weights_md()->extra.flags == 0; + if (ok) return status::success; + } + return status::unimplemented; + } + + status_t init(engine_t *engine) { + using namespace format_tag; + using smask_t = primitive_attr_t::skip_mask_t; + + const bool ok = is_fwd() + && set_default_alg_kind(alg_kind::convolution_direct) + && attr()->has_default_values( + smask_t::scales_runtime | smask_t::post_ops); + if (!ok) return status::unimplemented; + + CHECK(check_conv_ip(this)); + + CHECK(set_and_or_check_formats( + *desc(), src_md_, weights_md_, dst_md_, bias_md_, attr_)); + + CHECK(init_ip(engine)); + + if (weights_md_.format_kind == format_kind::any) + CHECK(maybe_reshape_weights( + &weights_md_, ip_pd_->weights_md(), with_groups())); + + init_name(); + init_scratchpad(); + return status::success; + } + + std::shared_ptr ip_pd_; + + private: + std::string name_ = "ip:any+"; + + void init_name() { + const std::string ips(ip_pd_->name()); + const std::string prefix = "x64:"; + const size_t pos = ips.find(prefix); + name_.append(ips, pos + prefix.length(), std::string::npos); + } + + void init_scratchpad() { + using namespace memory_tracking::names; + auto scratchpad = scratchpad_registry().registrar(); + scratchpad.book(key_nested, ip_pd_->scratchpad_registry()); + } + + status_t ip_desc_create(inner_product_desc_t *ipd) { + const bool to_ip = true; + + // reinterpret dst without spatial + memory_desc_t ip_dst_d; + CHECK(reshape_dst(&ip_dst_d, &dst_md_)); + + // reinterpret weights without groups + memory_desc_t ip_weights_d; + CHECK(maybe_reshape_weights( + &ip_weights_d, &weights_md_, with_groups(), to_ip)); + + return ip_desc_init(ipd, desc()->prop_kind, &src_md_, &ip_weights_d, + &bias_md_, &ip_dst_d); + } + }; + + ip_convolution_fwd_t(const pd_t *apd) : primitive_t(apd) {} + + status_t init(engine_t *engine) override { + CHECK(pd()->ip_pd_->create_primitive(ip_p_, engine)); + return status::success; + } + + status_t execute(const exec_ctx_t &ctx) const override; + +private: + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + std::shared_ptr ip_p_; +}; + +struct ip_convolution_bwd_data_t : public primitive_t { + struct pd_t : public cpu_convolution_bwd_data_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const convolution_fwd_pd_t *hint_fwd_pd) + : cpu_convolution_bwd_data_pd_t(adesc, attr, hint_fwd_pd) {} + + pd_t(const pd_t &other) + : cpu_convolution_bwd_data_pd_t(other) + , ip_pd_(other.ip_pd_->clone()) + , name_(other.name_) {} + + ~pd_t() = default; + + DECLARE_COMMON_PD_T(name_.c_str(), ip_convolution_bwd_data_t); + + status_t init_ip(engine_t *engine) { + inner_product_desc_t ipd; + CHECK(ip_desc_create(&ipd)); + primitive_desc_iterator_t it( + engine, (op_desc_t *)&ipd, attr(), nullptr); + if (!it.is_initialized()) return status::out_of_memory; + while (++it != it.end()) { + ip_pd_ = *it; + const bool ok = ip_pd_->weights_md()->extra.flags == 0; + if (ok) return status::success; + } + return status::unimplemented; + } + + status_t init(engine_t *engine) { + using namespace format_tag; + + const bool ok = desc()->prop_kind == prop_kind::backward_data + && set_default_alg_kind(alg_kind::convolution_direct) + && attr()->has_default_values(); + if (!ok) return status::unimplemented; + + CHECK(check_conv_ip(this)); + + CHECK(set_and_or_check_formats(*desc(), diff_src_md_, weights_md_, + diff_dst_md_, bias_md_, attr_)); + + CHECK(init_ip(engine)); + + if (weights_md_.format_kind == format_kind::any) + CHECK(maybe_reshape_weights( + &weights_md_, ip_pd_->weights_md(), with_groups())); + + init_name(); + init_scratchpad(); + return status::success; + } + + std::shared_ptr ip_pd_; + + private: + std::string name_ = "ip:any+"; + + void init_name() { name_.append(ip_pd_->name()); } + + void init_scratchpad() { + using namespace memory_tracking::names; + auto scratchpad = scratchpad_registry().registrar(); + scratchpad.book(key_nested, ip_pd_->scratchpad_registry()); + } + + status_t ip_desc_create(inner_product_desc_t *ipd) { + const bool to_ip = true; + + // reinterpret dst without spatial + memory_desc_t ip_diff_dst_d; + CHECK(reshape_dst(&ip_diff_dst_d, &diff_dst_md_)); + + // reinterpret weights without groups + memory_desc_t ip_weights_d; + CHECK(maybe_reshape_weights( + &ip_weights_d, &weights_md_, with_groups(), to_ip)); + + return ip_desc_init(ipd, desc()->prop_kind, &diff_src_md_, + &ip_weights_d, nullptr, &ip_diff_dst_d); + } + }; + + ip_convolution_bwd_data_t(const pd_t *apd) : primitive_t(apd) {} + + status_t init(engine_t *engine) override { + CHECK(pd()->ip_pd_->create_primitive(ip_p_, engine)); + return status::success; + } + + status_t execute(const exec_ctx_t &ctx) const override; + +private: + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + std::shared_ptr ip_p_; +}; + +struct ip_convolution_bwd_weights_t : public primitive_t { + struct pd_t : public cpu_convolution_bwd_weights_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const convolution_fwd_pd_t *hint_fwd_pd) + : cpu_convolution_bwd_weights_pd_t(adesc, attr, hint_fwd_pd) {} + + pd_t(const pd_t &other) + : cpu_convolution_bwd_weights_pd_t(other) + , ip_pd_(other.ip_pd_->clone()) + , name_(other.name_) {} + + ~pd_t() = default; + + DECLARE_COMMON_PD_T(name_.c_str(), ip_convolution_bwd_weights_t); + + status_t init_ip(engine_t *engine) { + inner_product_desc_t ipd; + CHECK(ip_desc_create(&ipd)); + primitive_desc_iterator_t it( + engine, (op_desc_t *)&ipd, attr(), nullptr); + if (!it.is_initialized()) return status::out_of_memory; + + while (++it != it.end()) { + ip_pd_ = *it; + const bool ok = ip_pd_->weights_md()->extra.flags == 0; + if (ok) return status::success; + } + return status::unimplemented; + } + + status_t init(engine_t *engine) { + using namespace format_tag; + + const bool ok = desc()->prop_kind == prop_kind::backward_weights + && set_default_alg_kind(alg_kind::convolution_direct) + && attr()->has_default_values(); + if (!ok) return status::unimplemented; + + CHECK(check_conv_ip(this)); + + CHECK(set_and_or_check_formats(*desc(), src_md_, diff_weights_md_, + diff_dst_md_, diff_bias_md_, attr_)); + + CHECK(init_ip(engine)); + + if (diff_weights_md_.format_kind == format_kind::any) + CHECK(maybe_reshape_weights(&diff_weights_md_, + ip_pd_->diff_weights_md(), with_groups())); + + init_name(); + init_scratchpad(); + return status::success; + } + + std::shared_ptr ip_pd_; + + private: + std::string name_ = "ip:any+"; + + void init_name() { name_.append(ip_pd_->name()); } + + void init_scratchpad() { + using namespace memory_tracking::names; + auto scratchpad = scratchpad_registry().registrar(); + scratchpad.book(key_nested, ip_pd_->scratchpad_registry()); + } + + status_t ip_desc_create(inner_product_desc_t *ipd) { + const bool to_ip = true; + + // reinterpret dst without spatial + memory_desc_t ip_diff_dst_d; + CHECK(reshape_dst(&ip_diff_dst_d, &diff_dst_md_)); + + // reinterpret weights without groups + memory_desc_t ip_diff_weights_d; + CHECK(maybe_reshape_weights(&ip_diff_weights_d, &diff_weights_md_, + with_groups(), to_ip)); + + return ip_desc_init(ipd, desc()->prop_kind, &src_md_, + &ip_diff_weights_d, &diff_bias_md_, &ip_diff_dst_d); + } + }; + + ip_convolution_bwd_weights_t(const pd_t *apd) : primitive_t(apd) {} + + status_t init(engine_t *engine) override { + CHECK(pd()->ip_pd_->create_primitive(ip_p_, engine)); + return status::success; + } + + status_t execute(const exec_ctx_t &ctx) const override; + +private: + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + std::shared_ptr ip_p_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx2_1x1_conv_kernel_f32.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx2_1x1_conv_kernel_f32.hpp new file mode 100644 index 0000000000000000000000000000000000000000..b7d429e00e47b45c7495a8559d079d7780ac243c --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx2_1x1_conv_kernel_f32.hpp @@ -0,0 +1,105 @@ +/******************************************************************************* +* Copyright 2016-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_AVX2_1X1_CONV_KERNEL_F32_HPP +#define CPU_X64_JIT_AVX2_1X1_CONV_KERNEL_F32_HPP + +#include "common/c_types_map.hpp" +#include "common/memory.hpp" +#include "common/memory_tracking.hpp" + +#include "cpu/x64/injectors/jit_uni_postops_injector.hpp" +#include "cpu/x64/jit_generator.hpp" +#include "cpu/x64/jit_primitive_conf.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +struct jit_avx2_1x1_conv_kernel_f32 : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx2_1x1_conv_kernel_f32) + + jit_avx2_1x1_conv_kernel_f32(const jit_1x1_conv_conf_t &ajcp, + const primitive_attr_t &attr, const memory_desc_t &dst_md); + + static status_t init_conf(jit_1x1_conv_conf_t &jcp, + const convolution_desc_t &cd, const memory_desc_wrapper &src_d, + const memory_desc_wrapper &weights_d, + const memory_desc_wrapper &dst_d, const primitive_attr_t &attr); + + static void init_scratchpad(memory_tracking::registrar_t &scratchpad, + const jit_1x1_conv_conf_t &jcp); + + jit_1x1_conv_conf_t jcp; + const primitive_attr_t &attr_; + +private: + std::unique_ptr> + postops_injector_; + + constexpr static int isa_simd_width_ + = cpu_isa_traits::vlen / sizeof(float); + using reg64_t = const Xbyak::Reg64; + using ymm_t = const Xbyak::Ymm; + + reg64_t reg_bcast_data = rax; + reg64_t reg_load_data = rsi; + reg64_t reg_output_data = rbx; + reg64_t aux_reg_bcast_data = rdx; + reg64_t aux1_reg_bcast_data = abi_not_param1; + reg64_t aux_reg_load_data = abi_param1; + reg64_t aux_reg_output_data = rbp; + reg64_t reg_load_loop_work = r9; + reg64_t reg_bcast_loop_work = r10; + reg64_t reg_reduce_loop_work = r11; + reg64_t load_loop_iter = r13; + reg64_t bcast_loop_iter = r14; + reg64_t reduce_loop_iter = r15; + reg64_t reg_reduce_pos_flag = r8; + reg64_t reg_output_stride = r12; + reg64_t reg_bias_data = r12; + reg64_t reg_diff_bias_data = bcast_loop_iter; + reg64_t reg_tmp_output_stride = reg_bcast_data; + reg64_t reg_tmp = aux_reg_bcast_data; + reg64_t reg_output_stride_scale = load_loop_iter; + reg64_t reg_long_offt = reg_bcast_data; + + constexpr static int reg64_size_ = sizeof(int64_t); + constexpr static int reg_diff_bias_data_stack_offt = 0; + constexpr static int reg_abi_param1_backup = 1 * reg64_size_; + constexpr static int reg_bcast_data_off = 2 * reg64_size_; + constexpr static int reg_dw_binary_output_off = 3 * reg64_size_; + constexpr static int stack_space_needed = 4 * reg64_size_; + + ymm_t vreg_bcast = ymm_t(15); + ymm_t vtmp = ymm_t(14); + + void apply_postops( + const int load_loop_blk, const int ur, const int load_dim_tail); + void generate_bcast_loop(int load_loop_blk); + void generate_reduce_loop(int load_loop_blk, int ur); + void generate_diff_bias_loop(int load_loop_blk); + + void generate() override; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx2_1x1_convolution.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx2_1x1_convolution.hpp new file mode 100644 index 0000000000000000000000000000000000000000..3f56765bd3032ae92ebe3c45a4fd681ec03e2113 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx2_1x1_convolution.hpp @@ -0,0 +1,595 @@ +/******************************************************************************* +* Copyright 2016-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_AVX2_1X1_CONVOLUTION_HPP +#define CPU_X64_JIT_AVX2_1X1_CONVOLUTION_HPP + +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/memory_tracking.hpp" +#include "common/primitive.hpp" +#include "common/primitive_hashing.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_convolution_pd.hpp" +#include "cpu/dw_convolution_utils.hpp" +#include "cpu/platform.hpp" + +#include "cpu/x64/cpu_reducer.hpp" +#include "cpu/x64/jit_avx2_1x1_conv_kernel_f32.hpp" +#include "cpu/x64/jit_uni_1x1_conv_utils.hpp" +#include "cpu/x64/jit_uni_dw_convolution.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +struct jit_avx2_1x1_convolution_fwd_t : public primitive_t { + // TODO: (Roma) Code duplication duplication! Remove with templates + // (maybe...)! + struct pd_t : public cpu_convolution_fwd_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const typename pd_t::base_class *hint_fwd_pd) + : cpu_convolution_fwd_pd_t(adesc, attr, hint_fwd_pd) + , jcp_() + , rtus_() + , jcp_dw_(nullptr) {} + + pd_t(const pd_t &other) : cpu_convolution_fwd_pd_t(other) { + if (copy(other) != status::success) is_initialized_ = false; + } + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit_1x1:", jcp_.isa, ""), + jit_avx2_1x1_convolution_fwd_t); + + status_t init(engine_t *engine) { + bool ok = true && is_fwd() + && set_default_alg_kind(alg_kind::convolution_direct) + && expect_data_types(data_type::f32, data_type::f32, + data_type::f32, data_type::f32, data_type::f32) + && attr()->has_default_values( + primitive_attr_t::skip_mask_t::post_ops, + data_type::f32) + && !has_zero_dim_memory() && set_default_formats() + && attr_.set_default_formats(dst_md(0)) == status::success; + if (!ok) return status::unimplemented; + + const convolution_desc_t *conv_d = desc(); + const memory_desc_t *src_d = src_md(); + rtus_prepare(this, conv_d, src_d, dst_md(), weights_md()); + + CHECK(jit_avx2_1x1_conv_kernel_f32::init_conf( + jcp_, *conv_d, *src_d, *weights_md(), *dst_md(), *attr())); + if (jcp_.with_dw_conv) CHECK(depthwise_po_init(engine)); + + auto scratchpad = scratchpad_registry().registrar(); + jit_avx2_1x1_conv_kernel_f32::init_scratchpad(scratchpad, jcp_); + + rtus_prepare_space_info(this, scratchpad, jcp_.nthr); + + return status::success; + } + + const memory_desc_t *dst_1x1_md(int index = 0) const { + return cpu_convolution_fwd_pd_t::dst_md(index); + } + + const memory_desc_t *dst_md( + int index = 0, bool user_input = false) const override { + return jcp_.with_dw_conv + ? dw_conv_pd_->dst_md(index, user_input) + : cpu_convolution_fwd_pd_t::dst_md(index, user_input); + } + + const memory_desc_t *arg_md( + int arg, bool user_input = false) const override { + if (jcp_.with_dw_conv) { + switch (arg) { + case DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_SRC: + return cpu_convolution_fwd_pd_t::dst_md(0, user_input); + case DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_WEIGHTS: + return dw_conv_pd_->weights_md(0); + case DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_BIAS: + return dw_conv_pd_->weights_md(1); + default: break; + } + } + return convolution_fwd_pd_t::arg_md(arg, user_input); + } + + arg_usage_t arg_usage(int arg) const override { + if (arg == (DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_WEIGHTS)) + return arg_usage_t::input; + + if (arg == (DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_BIAS) + && attr_post_op_dw_inputs() > 1) + return arg_usage_t::input; + + return convolution_fwd_pd_t::arg_usage(arg); + } + + jit_1x1_conv_conf_t jcp_; + reduce_to_unit_stride_t rtus_; + jit_conv_conf_t *jcp_dw_; + std::unique_ptr dw_conv_pd_; + + protected: + template + using dw_pd_t = typename jit_uni_dw_convolution_fwd_t::pd_t; + + bool set_default_formats() { + using namespace format_tag; + + const memory_desc_wrapper src_d(&src_md_); + const memory_desc_wrapper dst_d(&dst_md_); + + const auto dat_tag_nxc = utils::pick(ndims() - 3, nwc, nhwc, ndhwc); + const auto dat_tag_nCx8c + = utils::pick(ndims() - 3, nCw8c, nChw8c, nCdhw8c); + const auto curr_src_tag + = src_d.matches_one_of_tag(dat_tag_nxc, dat_tag_nCx8c); + const auto curr_dst_tag + = dst_d.matches_one_of_tag(dat_tag_nxc, dat_tag_nCx8c); + const auto is_data_layout_nxc + = IMPLICATION(curr_src_tag != dat_tag_nxc, + src_d.format_kind() == format_kind::any) + && IMPLICATION(curr_dst_tag != dat_tag_nxc, + dst_d.format_kind() == format_kind::any) + && utils::one_of(dat_tag_nxc, curr_src_tag, curr_dst_tag); + auto dat_tag = is_data_layout_nxc ? dat_tag_nxc : dat_tag_nCx8c; + auto wei_tag = with_groups() + ? utils::pick(ndims() - 3, gOIw8i8o, gOIhw8i8o, gOIdhw8i8o) + : utils::pick(ndims() - 3, OIw8i8o, OIhw8i8o, OIdhw8i8o); + + return set_default_formats_common(dat_tag, wei_tag, dat_tag); + } + + status_t copy(const pd_t &other) { + jcp_ = other.jcp_; + rtus_ = other.rtus_; + jcp_dw_ = nullptr; + if (other.dw_conv_pd_) { + dw_conv_pd_.reset(static_cast( + other.dw_conv_pd_->clone())); + if (!dw_conv_pd_) return status::out_of_memory; + if (jcp_.isa == avx2) { + jcp_dw_ = &(static_cast *>(dw_conv_pd_.get()) + ->jcp_); + } else { // sse41 + jcp_dw_ = &(static_cast *>(dw_conv_pd_.get()) + ->jcp_); + } + } + + return status::success; + } + + status_t depthwise_po_init(engine_t *engine) { + + using namespace memory_tracking; + auto &jcp_1x1 = jcp_; + primitive_attr_t attr_1x1(*attr()); + if (!attr_1x1.is_initialized()) return status::out_of_memory; + jit_conv_conf_t *jcp_dw = nullptr; + + const auto &src_md = dst_md_; + const memory_desc_wrapper src_d(src_md); + const auto nthr = dnnl_get_max_threads(); + auto l2_cache = platform::get_per_core_cache_size(2) * nthr; + + // Note: A robust fusion implementation would be to check if both + // 1x1 conv and dw conv that are considered here for fusion are + // optimal independently. This would require creating a new + // primitive_desc through primitive_iterator & check if they match. + // Due to concern that these creations and/or checks could be heavy, + // for 1x1: Check that no better ISA is available. + // for dw: Always fuse with same ISA. + // Caveat: May be a better dw conv exists. + + bool ok = true && (!mayiuse(avx512_core)) + && (attr_1x1.post_ops_.find(primitive_kind::sum) == -1) + // TODO: Below may be further tuned. + && (l2_cache * 2 < src_d.size()) + // load_grp_count check can be redundant due to l2 check + // above. Adding it explicitly as the current driver doesn't + // work if this condition fails. + && (jcp_1x1.load_grp_count < 2); + if (!ok) return status::unimplemented; + + int dw_po_index + = attr_1x1.post_ops_.find(primitive_kind::convolution); + + convolution_desc_t cd_dw; + primitive_attr_t attr_dw; + + CHECK(get_depthwise_conv_desc( + cd_dw, src_md, attr_1x1, attr_dw, dw_po_index)); + + if (jcp_1x1.isa == avx2) { + std::unique_ptr> fusable_pd( + new dw_pd_t(&cd_dw, &attr_dw, nullptr)); + CHECK(fusable_pd->init(engine)); + jcp_dw = &(fusable_pd->jcp_); + dw_conv_pd_ = std::move(fusable_pd); + } else { + // Special case for this primitive, as we dont have dw. + // In this case fuse with sse41 depthwise conv + // NOTE: Currently dw f32 kernel is similar for all ISA and can + // be fused regardless of ISA if inter-connecting md_ matches. + std::unique_ptr> fusable_pd( + new dw_pd_t(&cd_dw, &attr_dw, nullptr)); + CHECK(fusable_pd->init(engine)); + jcp_dw = &(fusable_pd->jcp_); + dw_conv_pd_ = std::move(fusable_pd); + } + + ok = true + && (dnnl_memory_desc_equal(&src_md, dw_conv_pd_->src_md(0))) + && (jcp_1x1.oc_without_padding % jcp_1x1.oc_block == 0) + && IMPLICATION( + jcp_dw->ow_block, jcp_dw->ow_block == jcp_dw->ow); + if (!ok) return status::unimplemented; + + assert(dw_conv_pd_->dst_md(0)->format_kind != format_kind::any); + assert(dw_conv_pd_->weights_md(0)->format_kind != format_kind::any); + assert(IMPLICATION( + dw_conv_pd_->weights_md(1)->data_type != data_type::undef, + dw_conv_pd_->weights_md(1)->format_kind + != format_kind::any)); + + jcp_dw->is_fused_conv = true; + // TODO: Support/experiment arbitary oc_work in dw conv. + // Until then we keep oc_work perfectly divisible. + while (jcp_1x1.nb_load % jcp_1x1.nb_load_blocking != 0) + --jcp_1x1.nb_load_blocking; + jcp_1x1.nb_load_blocking_max = jcp_1x1.nb_load_blocking; + + while (jcp_1x1.nb_load_blocking % jcp_dw->nb_ch_blocking != 0) + --jcp_dw->nb_ch_blocking; + + jcp_dw->dw_conv_buffer_oc + = jcp_1x1.nb_load_blocking * jcp_1x1.oc_block; + + const auto dat_tag_nxc = utils::pick(ndims() - 3, format_tag::nwc, + format_tag::nhwc, format_tag::ndhwc); + const bool is_data_nxc = utils::everyone_is( + dat_tag_nxc, jcp_1x1.src_tag, jcp_1x1.dst_tag); + if (!is_data_nxc) + jcp_1x1.bcast_loop_output_step = jcp_1x1.ur * jcp_1x1.load_block + * jcp_1x1.typesize_out; + + registrar_t scratchpad(scratchpad_registry_); + registrar_t dw_scratchpad(scratchpad, names::prefix_fusion); + + size_t dw_conv_buffer_size_ = (size_t)nthr * jcp_dw->kh * jcp_dw->iw + * jcp_dw->dw_conv_buffer_oc; + assert(dw_conv_buffer_size_); + dw_scratchpad.book(memory_tracking::names::key_fusion_inout_buffer, + dw_conv_buffer_size_, + types::data_type_size(dw_conv_pd_->src_md()->data_type)); + + if (jcp_1x1.isa == avx2) + dw_conv_kernel_t::init_scratchpad(dw_scratchpad, *jcp_dw); + else + dw_conv_kernel_t::init_scratchpad( + dw_scratchpad, *jcp_dw); + + return status::success; + } + }; + + template + friend status_t init_rtus_driver(conv_t *self); + + jit_avx2_1x1_convolution_fwd_t(const pd_t *apd) : primitive_t(apd) {} + + status_t init(engine_t *engine) override { + CHECK(safe_ptr_assign(kernel_, + new jit_avx2_1x1_conv_kernel_f32( + pd()->jcp_, *pd()->attr(), *pd()->dst_1x1_md(0)))); + CHECK(kernel_->create_kernel()); + CHECK(init_rtus_driver(this)); + if (pd()->jcp_.with_dw_conv) { + auto &isa = pd()->jcp_.isa; + + if (isa == avx2) { + CHECK(safe_ptr_assign(kernel_dw_avx2, + new dw_conv_kernel_t( + *(pd()->jcp_dw_), *pd()->dst_md(0)))); + CHECK(kernel_dw_avx2->create_kernel()); + } else { + CHECK(safe_ptr_assign(kernel_dw_sse41, + new dw_conv_kernel_t( + *(pd()->jcp_dw_), *pd()->dst_md(0)))); + CHECK(kernel_dw_sse41->create_kernel()); + } + } + + return status::success; + } + + typedef typename prec_traits::type data_t; + + status_t execute(const exec_ctx_t &ctx) const override { + execute_forward(ctx); + return status::success; + } + +private: + void execute_forward(const exec_ctx_t &ctx) const; + void execute_forward_thr(const int ithr, const int nthr, const data_t *src, + const data_t *weights, const data_t *bias, const data_t *weights_dw, + const data_t *bias_dw, data_t *dst, + const memory_tracking::grantor_t &scratchpad, + const void *post_ops_binary_rhs_arg_vec, + const void *post_ops_binary_rhs_arg_vec_dw) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr kernel_; + std::unique_ptr> rtus_driver_; + + template + using dw_conv_kernel_t = jit_uni_dw_conv_fwd_kernel; + + std::unique_ptr> kernel_dw_avx2; + std::unique_ptr> kernel_dw_sse41; +}; + +struct jit_avx2_1x1_convolution_bwd_data_t : public primitive_t { + struct pd_t : public cpu_convolution_bwd_data_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const convolution_fwd_pd_t *hint_fwd_pd) + : cpu_convolution_bwd_data_pd_t(adesc, attr, hint_fwd_pd) + , jcp_() + , rtus_() {} + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit_1x1:", avx2, ""), + jit_avx2_1x1_convolution_bwd_data_t); + + status_t init(engine_t *engine) { + bool ok = true && desc()->prop_kind == prop_kind::backward_data + && set_default_alg_kind(alg_kind::convolution_direct) + && expect_data_types(data_type::f32, data_type::f32, + data_type::undef, data_type::f32, data_type::f32) + && attr()->has_default_values() && !has_zero_dim_memory() + && set_default_formats(); + if (!ok) return status::unimplemented; + + const convolution_desc_t *conv_d = desc(); + const memory_desc_t *diff_src_d = diff_src_md(); + rtus_prepare(this, conv_d, diff_src_d, diff_dst_md(), weights_md()); + + status_t status = jit_avx2_1x1_conv_kernel_f32::init_conf(jcp_, + *conv_d, *diff_src_d, *weights_md(), *diff_dst_md(), + *attr()); + if (status != status::success) return status; + + auto scratchpad = scratchpad_registry().registrar(); + jit_avx2_1x1_conv_kernel_f32::init_scratchpad(scratchpad, jcp_); + + rtus_prepare_space_info(this, scratchpad, jcp_.nthr); + + return status::success; + } + + jit_1x1_conv_conf_t jcp_; + reduce_to_unit_stride_t rtus_; + + protected: + bool set_default_formats() { + using namespace format_tag; + + const memory_desc_wrapper diff_src_d(&diff_src_md_); + const memory_desc_wrapper diff_dst_d(&diff_dst_md_); + + const auto dat_tag_nxc = utils::pick(ndims() - 3, nwc, nhwc, ndhwc); + const auto dat_tag_nCx8c + = utils::pick(ndims() - 3, nCw8c, nChw8c, nCdhw8c); + const auto curr_src_tag + = diff_src_d.matches_one_of_tag(dat_tag_nxc, dat_tag_nCx8c); + const auto curr_dst_tag + = diff_dst_d.matches_one_of_tag(dat_tag_nxc, dat_tag_nCx8c); + const auto is_data_layout_nxc + = IMPLICATION(curr_src_tag != dat_tag_nxc, + diff_src_d.format_kind() == format_kind::any) + && IMPLICATION(curr_dst_tag != dat_tag_nxc, + diff_dst_d.format_kind() == format_kind::any) + && utils::one_of(dat_tag_nxc, curr_src_tag, curr_dst_tag); + auto dat_tag = is_data_layout_nxc ? dat_tag_nxc : dat_tag_nCx8c; + auto wei_tag = with_groups() + ? utils::pick(ndims() - 3, gOIw8o8i, gOIhw8o8i, gOIdhw8o8i) + : utils::pick(ndims() - 3, OIw8o8i, OIhw8o8i, OIdhw8o8i); + + return set_default_formats_common(dat_tag, wei_tag, dat_tag); + } + }; + + template + friend status_t init_rtus_driver(conv_t *self); + + jit_avx2_1x1_convolution_bwd_data_t(const pd_t *apd) : primitive_t(apd) {} + + typedef typename prec_traits::type data_t; + + status_t init(engine_t *engine) override { + CHECK(safe_ptr_assign(kernel_, + new jit_avx2_1x1_conv_kernel_f32( + pd()->jcp_, *pd()->attr(), *pd()->dst_md(0)))); + CHECK(kernel_->create_kernel()); + CHECK(init_rtus_driver(this)); + return status::success; + } + + status_t execute(const exec_ctx_t &ctx) const override { + execute_backward_data(ctx); + return status::success; + } + +private: + void execute_backward_data(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr kernel_; + std::unique_ptr> rtus_driver_; +}; + +struct jit_avx2_1x1_convolution_bwd_weights_t : public primitive_t { + struct pd_t : public cpu_convolution_bwd_weights_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const convolution_fwd_pd_t *hint_fwd_pd) + : cpu_convolution_bwd_weights_pd_t(adesc, attr, hint_fwd_pd) + , jcp_() + , rtus_() {} + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit_1x1:", avx2, ""), + jit_avx2_1x1_convolution_bwd_weights_t); + + status_t init(engine_t *engine) { + bool ok = true && desc()->prop_kind == prop_kind::backward_weights + && set_default_alg_kind(alg_kind::convolution_direct) + && expect_data_types(data_type::f32, data_type::f32, + data_type::f32, data_type::f32, data_type::f32) + && attr()->has_default_values() && !has_zero_dim_memory() + && set_default_formats(); + if (!ok) return status::unimplemented; + + const convolution_desc_t *conv_d = desc(); + const memory_desc_t *src_d = src_md(); + rtus_prepare(this, conv_d, src_d, diff_dst_md(), diff_weights_md()); + + status_t status = jit_avx2_1x1_conv_kernel_f32::init_conf(jcp_, + *conv_d, *src_d, *diff_weights_md(), *diff_dst_md(), + *attr()); + if (status != status::success) return status; + + init_balancers(); + + auto scratchpad = scratchpad_registry().registrar(); + jit_avx2_1x1_conv_kernel_f32::init_scratchpad(scratchpad, jcp_); + + rtus_prepare_space_info(this, scratchpad, jcp_.nthr); + + auto reducer_bia_scratchpad = memory_tracking::registrar_t( + scratchpad, memory_tracking::names::prefix_reducer_bia); + reducer_bia_conf_.init_scratchpad(reducer_bia_scratchpad); + + auto reducer_wei_scratchpad = memory_tracking::registrar_t( + scratchpad, memory_tracking::names::prefix_reducer_wei); + reducer_wei_conf_.init_scratchpad(reducer_wei_scratchpad); + + return status::success; + } + + jit_1x1_conv_conf_t jcp_; + cpu_reducer_t::conf_t reducer_bia_conf_; + cpu_reducer_2d_t::conf_t reducer_wei_conf_; + reduce_to_unit_stride_t rtus_; + + protected: + bool set_default_formats() { + using namespace format_tag; + + const memory_desc_wrapper src_d(&src_md_); + const memory_desc_wrapper diff_dst_d(&diff_dst_md_); + + const auto dat_tag_nxc = utils::pick(ndims() - 3, nwc, nhwc, ndhwc); + const auto dat_tag_nCx8c + = utils::pick(ndims() - 3, nCw8c, nChw8c, nCdhw8c); + const auto curr_src_tag + = src_d.matches_one_of_tag(dat_tag_nxc, dat_tag_nCx8c); + const auto curr_dst_tag + = diff_dst_d.matches_one_of_tag(dat_tag_nxc, dat_tag_nCx8c); + const auto is_data_layout_nxc + = IMPLICATION(curr_src_tag != dat_tag_nxc, + src_d.format_kind() == format_kind::any) + && IMPLICATION(curr_dst_tag != dat_tag_nxc, + diff_dst_d.format_kind() == format_kind::any) + && utils::one_of(dat_tag_nxc, curr_src_tag, curr_dst_tag); + + auto dat_tag = is_data_layout_nxc ? dat_tag_nxc : dat_tag_nCx8c; + auto wei_tag = with_groups() + ? utils::pick(ndims() - 3, gOIw8i8o, gOIhw8i8o, gOIdhw8i8o) + : utils::pick(ndims() - 3, OIw8i8o, OIhw8i8o, OIdhw8i8o); + + return set_default_formats_common(dat_tag, wei_tag, dat_tag); + } + + private: + void init_balancers() { + const int ic_block = jcp_.bcast_block; + const int nb_ic = jcp_.nb_bcast; + const int nb_ic_blocking = jcp_.nb_bcast_blocking; + const int bcast_work = utils::div_up(nb_ic, nb_ic_blocking); + + const int oc_block = jcp_.load_block; + const int nb_oc = jcp_.nb_load; + const int nb_oc_blocking = jcp_.nb_load_blocking; + const int load_work = utils::div_up(nb_oc, nb_oc_blocking); + + const int job_size + = nb_oc_blocking * nb_ic_blocking * ic_block * oc_block; + const int njobs_x = bcast_work; + const int njobs_y = jcp_.ngroups * load_work; + + const int max_threads = dnnl_get_max_threads(); + const size_t max_buffer_size = (size_t)max_threads * job_size * 8; + + if (with_bias()) { + reducer_bia_conf_.init(reduce_balancer_t(max_threads, oc_block, + jcp_.ngroups * nb_oc, jcp_.mb, max_buffer_size, true)); + } + + reducer_wei_conf_.init( + reduce_balancer_t(max_threads, job_size, njobs_y * njobs_x, + jcp_.mb * jcp_.nb_reduce, max_buffer_size, true), + job_size / nb_oc_blocking, nb_oc_blocking, ic_block, + nb_ic * ic_block * oc_block, nb_oc); + } + }; + + template + friend status_t init_rtus_driver(conv_t *self); + + jit_avx2_1x1_convolution_bwd_weights_t(const pd_t *apd) + : primitive_t(apd) {} + + typedef typename prec_traits::type data_t; + + status_t init(engine_t *engine) override; + + status_t execute(const exec_ctx_t &ctx) const override { + execute_backward_weights(ctx); + return status::success; + } + +private: + void execute_backward_weights(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr kernel_; + std::unique_ptr> reducer_weights_; + std::unique_ptr> reducer_bias_; + std::unique_ptr> rtus_driver_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx2_conv_kernel_f32.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx2_conv_kernel_f32.hpp new file mode 100644 index 0000000000000000000000000000000000000000..c62b4be7b7102e94e85203c107521d9ae7d9360d --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx2_conv_kernel_f32.hpp @@ -0,0 +1,344 @@ +/******************************************************************************* +* Copyright 2016-2022 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_AVX2_CONV_KERNEL_F32_HPP +#define CPU_X64_JIT_AVX2_CONV_KERNEL_F32_HPP + +#include "common/c_types_map.hpp" +#include "common/memory.hpp" +#include "common/memory_tracking.hpp" + +#include "cpu/x64/injectors/jit_uni_postops_injector.hpp" +#include "cpu/x64/jit_generator.hpp" +#include "cpu/x64/jit_primitive_conf.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +struct jit_avx2_conv_fwd_kernel_f32 : public jit_generator { + jit_avx2_conv_fwd_kernel_f32(const jit_conv_conf_t &ajcp, + const primitive_attr_t &attr, const memory_desc_t &dst_md); + + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx2_conv_fwd_kernel_f32) + + static status_t init_conf(jit_conv_conf_t &jcp, + const convolution_desc_t &cd, const memory_desc_wrapper &src_d, + const memory_desc_wrapper &weights_d, + const memory_desc_wrapper &dst_d, const primitive_attr_t &attr); + static void init_scratchpad(memory_tracking::registrar_t &scratchpad, + const jit_conv_conf_t &jcp); + + jit_conv_conf_t jcp; + const primitive_attr_t &attr_; + +private: + std::unique_ptr> + postops_injector_; + + constexpr static int isa_simd_width_ + = cpu_isa_traits::vlen / sizeof(float); + using reg64_t = const Xbyak::Reg64; + reg64_t reg_input = rax; + reg64_t aux_reg_input = r8; + reg64_t reg_kernel = rdx; + reg64_t aux_reg_kernel = r9; + reg64_t reg_output = rsi; + reg64_t reg_bias = rbx; + + reg64_t aux_reg_inp_d = r11; + reg64_t aux_reg_ker_d = abi_not_param1; + + reg64_t reg_ki = rsi; + reg64_t kj = r10; + reg64_t oi_iter = r11; + reg64_t ki_iter = r12; + reg64_t reg_channel = ki_iter; + reg64_t reg_kh = abi_not_param1; + reg64_t reg_oc_blocks = r14; + reg64_t imm_addr64 = r15; + reg64_t reg_long_offt = r15; + Xbyak::Reg32 reg_ci_flag = r13d; + Xbyak::Reg32 reg_oc_flag = r14d; + + /* binary post-ops operand */ + reg64_t temp_offset_reg = r12; + + Xbyak::Ymm ytmp = Xbyak::Ymm(14); + + inline void oh_step_unroll_kw( + int ur_w, int pad_l, int pad_r, int oc_blocks); + inline void oh_step_nopad(int ur_w, int pad_l, int pad_r, int oc_blocks); + void apply_postops(const int oc_blocks, const int ur_w, const int oc_tail); + inline void width_blk_step(int ur_w, int pad_l, int pad_r, int oc_blocks); + inline void solve_common(int oc_blocks); + + inline dim_t filter_w_to_input(int ki, int oi = 0, int pad_l = 0) { + return ki * (jcp.dilate_w + 1) + oi * jcp.stride_w - pad_l; + }; + inline dim_t filter_h_to_input(int ki) { + return ki * (jcp.dilate_h + 1) * jcp.iw; + }; + inline dim_t filter_d_to_input(int ki) { + return ki * (jcp.dilate_d + 1) * jcp.iw * jcp.ih; + }; + + inline dim_t get_input_offset(int i_ic, int i_iw) { + dim_t offset; + if (utils::one_of(jcp.src_tag, format_tag::ncw, format_tag::nchw, + format_tag::ncdhw)) { + offset = static_cast(i_ic) * jcp.id * jcp.ih * jcp.iw + i_iw; + } else if (utils::one_of(jcp.src_tag, format_tag::nwc, format_tag::nhwc, + format_tag::ndhwc)) { + offset = static_cast(i_iw) * jcp.ic * jcp.ngroups + i_ic; + } else { + offset = static_cast(i_iw) * jcp.ic_block + i_ic; + } + return sizeof(float) * offset; + } + + inline dim_t get_output_offset(int i_oc_block, int i_ow) { + dim_t offset; + if (utils::one_of(jcp.dst_tag, format_tag::nwc, format_tag::nhwc, + format_tag::ndhwc)) { + offset = static_cast(i_ow) * jcp.oc * jcp.ngroups + + i_oc_block * jcp.oc_block; + } else { + offset = static_cast(i_oc_block) * jcp.od * jcp.oh * jcp.ow + * jcp.oc_block + + i_ow * jcp.oc_block; + } + return sizeof(float) * offset; + } + + inline dim_t get_kernel_offset(int i_oc_block, int ki, int i_ic) { + dim_t block_step_size = jcp.ic_block * jcp.oc_block; + dim_t ic_block_step_size = static_cast(jcp.kd) * jcp.kh * jcp.kw + * block_step_size; + dim_t oc_block_step_size + = static_cast(jcp.nb_ic) * ic_block_step_size; + dim_t offset = static_cast(i_oc_block) * oc_block_step_size + + ki * block_step_size + i_ic * jcp.oc_block; + return sizeof(float) * offset; + } + + inline bool is_src_layout_nxc() { + return utils::one_of(jcp.src_tag, format_tag::ndhwc, format_tag::nhwc, + format_tag::nwc); + } + + void generate() override; +}; + +struct jit_avx2_conv_bwd_data_kernel_f32 : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx2_conv_bwd_data_kernel_f32) + + jit_avx2_conv_bwd_data_kernel_f32(const jit_conv_conf_t &ajcp) + : jit_generator(jit_name()), jcp(ajcp) {} + + static status_t init_conf(jit_conv_conf_t &jcp, + const convolution_desc_t &cd, const memory_desc_wrapper &diff_src_d, + const memory_desc_wrapper &weights_d, + const memory_desc_wrapper &diff_dst_d); + static void init_scratchpad(memory_tracking::registrar_t &scratchpad, + const jit_conv_conf_t &jcp); + + jit_conv_conf_t jcp; + +private: + using reg64_t = const Xbyak::Reg64; + + reg64_t reg_ddst = rax; + reg64_t aux_reg_ddst = r8; + reg64_t reg_kernel = rdx; + reg64_t aux_reg_kernel = r10; + reg64_t reg_dsrc = rsi; + reg64_t aux_reg_ddst_oc_loop = rbx; // used in ndims < 5 case only + reg64_t aux_reg_kernel_oc_loop = abi_not_param1; /* used in ndims < 5 + case only */ + + reg64_t aux_reg_dst_d = r12; // used in ndims == 5 case only + reg64_t aux_reg_ker_d = r14; // used in ndims == 5 case only + + reg64_t reg_ki = abi_not_param1; // used in ndims == 5 case only + reg64_t kj = r11; + reg64_t oi_iter = r12; + reg64_t reg_kh = r14; + reg64_t reg_channel = r13; // used in ndims < 5 case only + reg64_t reg_channel_work = r9; // used in ndims < 5 case only + reg64_t reg_long_offt = r15; + reg64_t reg_reduce_work = reg_long_offt; + Xbyak::Reg32 reg_ci_flag = r13d; // used for nxc tails + + inline void compute_loop(int ur_w, int l_overflow, int r_overflow); + + void generate() override; + + inline int get_iw_start(int ki, int l_overflow) { + int res = (jcp.iw - 1 + jcp.r_pad) % jcp.stride_w + + l_overflow * jcp.stride_w + - (jcp.kw - 1 - ki) * (jcp.dilate_w + 1); + while (res < 0) + res += jcp.stride_w; + + return res; + } + + inline int get_iw_end(int ur_w, int ki, int r_overflow) { + if (utils::one_of(ur_w, jcp.iw, jcp.ur_w_tail)) + ur_w += nstl::min(0, jcp.r_pad); // remove negative padding + int res = (ur_w - 1 + jcp.l_pad) % jcp.stride_w + + r_overflow * jcp.stride_w - ki * (jcp.dilate_w + 1); + while (res < 0) + res += jcp.stride_w; + + return ur_w - res; + } + + inline dim_t filter_w_to_ddst(int ki, int oi = 0, int pad_l = 0) { + return (oi + pad_l - ki * (jcp.dilate_w + 1)) / jcp.stride_w; + } + + inline dim_t get_ddst_offset(int i_oc_block, int i_ow, int i_oc) { + dim_t offset; + if (utils::one_of(jcp.dst_tag, format_tag::nwc, format_tag::nhwc, + format_tag::ndhwc)) { + offset = static_cast(i_ow) * jcp.oc * jcp.ngroups + + i_oc_block * jcp.oc_block + i_oc; + } else { + offset = static_cast(i_oc_block) * jcp.od * jcp.oh * jcp.ow + * jcp.oc_block + + i_ow * jcp.oc_block + i_oc; + } + return sizeof(float) * offset; + } + + inline dim_t get_dsrc_offset(int i_ic_block, int i_iw) { + dim_t offset; + if (utils::one_of(jcp.src_tag, format_tag::nwc, format_tag::nhwc, + format_tag::ndhwc)) { + offset = static_cast(i_iw) * jcp.ic * jcp.ngroups + + i_ic_block * jcp.ic_block; + } else { + offset = static_cast(i_ic_block) * jcp.id * jcp.ih * jcp.iw + * jcp.ic_block + + i_iw * jcp.ic_block; + } + return sizeof(float) * offset; + } + + inline dim_t get_kernel_offset( + int i_oc_block, int i_ic_block, int ki, int i_oc) { + dim_t block_step_size = jcp.ic_block * jcp.oc_block; + dim_t ic_block_step_size = static_cast(jcp.kd) * jcp.kh * jcp.kw + * block_step_size; + dim_t oc_block_step_size + = static_cast(jcp.nb_ic) * ic_block_step_size; + dim_t offset = static_cast(i_oc_block) * oc_block_step_size + + i_ic_block * ic_block_step_size + ki * block_step_size + + i_oc * jcp.ic_block; + return sizeof(float) * offset; + } +}; + +struct jit_avx2_conv_bwd_weights_kernel_f32 : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx2_conv_bwd_weights_kernel_f32) + + jit_avx2_conv_bwd_weights_kernel_f32(const jit_conv_conf_t &ajcp) + : jit_generator(jit_name()), jcp(ajcp) {} + + static status_t init_conf(jit_conv_conf_t &jcp, + const convolution_desc_t &cd, const memory_desc_wrapper &src_d, + const memory_desc_wrapper &diff_weights_d, + const memory_desc_wrapper &diff_dst_d); + static void init_scratchpad(memory_tracking::registrar_t &scratchpad, + const jit_conv_conf_t &jcp); + + jit_conv_conf_t jcp; + +private: + using reg64_t = const Xbyak::Reg64; + reg64_t reg_input = rax; + reg64_t reg_kernel = rdx; + reg64_t reg_output = rsi; + reg64_t b_ic = abi_not_param1; + reg64_t kj = r8; + reg64_t reg_kh = r9; + reg64_t reg_ur_w_trips = r10; + reg64_t reg_tmp = r11; + reg64_t reg_oj = r15; + reg64_t reg_ih_count = rbx; + reg64_t aux_reg_input = r12; + reg64_t aux_reg_kernel = r13; + reg64_t ki = r14; + reg64_t reg_long_offt = r11; + reg64_t reg_channel = reg_ih_count; // used for nxc tails + Xbyak::Reg32 reg_ci_flag = r9d; // used for nxc tails + + inline void od_step_comeback_pointers(); + inline void oh_step_comeback_pointers(); + inline void compute_ic_block_step(int ur_w, int pad_l, int pad_r, + int ic_block_step, int input_offset, int kernel_offset, + int output_offset); + inline void compute_oh_step_disp(); + inline void compute_oh_step_unroll_ow(int ic_block_step, int max_ur_w); + inline void compute_oh_step_common(int ic_block_step, int max_ur_w); + inline void compute_oh_loop_common(); + + inline dim_t get_input_offset(int i_ic, int i_iw) { + dim_t offset; + if (utils::one_of(jcp.src_tag, format_tag::ncw, format_tag::nchw, + format_tag::ncdhw)) { + offset = static_cast(i_ic) * jcp.id * jcp.ih * jcp.iw + i_iw; + } else if (utils::one_of(jcp.src_tag, format_tag::nwc, format_tag::nhwc, + format_tag::ndhwc)) { + offset = static_cast(i_iw) * jcp.ic * jcp.ngroups + i_ic; + } else { + offset = static_cast(i_iw) * jcp.ic_block + i_ic; + } + return sizeof(float) * offset; + } + + inline dim_t get_output_offset(int i_oc_block, int i_ow) { + dim_t offset; + if (utils::one_of(jcp.dst_tag, format_tag::nwc, format_tag::nhwc, + format_tag::ndhwc)) { + offset = static_cast(i_ow) * jcp.oc * jcp.ngroups + + i_oc_block * jcp.oc_block; + } else { + offset = static_cast(i_oc_block) * jcp.od * jcp.oh * jcp.ow + * jcp.oc_block + + i_ow * jcp.oc_block; + } + return sizeof(float) * offset; + } + + inline dim_t get_kernel_offset(int ki, int i_ic) { + dim_t block_step_size = jcp.ic_block * jcp.oc_block; + dim_t offset = static_cast(ki) * block_step_size + + i_ic * jcp.oc_block; + return sizeof(float) * offset; + } + void generate() override; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx2_convolution.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx2_convolution.hpp new file mode 100644 index 0000000000000000000000000000000000000000..a21b80572ee1dfb1961e074073760b74e802d19e --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx2_convolution.hpp @@ -0,0 +1,348 @@ +/******************************************************************************* +* Copyright 2016-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_AVX2_CONVOLUTION_HPP +#define CPU_X64_JIT_AVX2_CONVOLUTION_HPP + +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/memory_tracking.hpp" +#include "common/primitive.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_convolution_pd.hpp" +#include "cpu/x64/cpu_reducer.hpp" + +#include "cpu/x64/jit_avx2_conv_kernel_f32.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +struct jit_avx2_convolution_fwd_t : public primitive_t { + struct pd_t : public cpu_convolution_fwd_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const typename pd_t::base_class *hint_fwd_pd) + : cpu_convolution_fwd_pd_t(adesc, attr, hint_fwd_pd), jcp_() {} + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit:", jcp_.isa, ""), + jit_avx2_convolution_fwd_t); + + status_t init(engine_t *engine) { + bool ok = true && is_fwd() + && set_default_alg_kind(alg_kind::convolution_direct) + && expect_data_types(data_type::f32, data_type::f32, + data_type::f32, data_type::f32, data_type::f32) + && attr()->has_default_values( + primitive_attr_t::skip_mask_t::post_ops, + data_type::f32) + && !has_zero_dim_memory() && set_default_formats() + && attr_.set_default_formats(dst_md(0)) == status::success; + if (!ok) return status::unimplemented; + + CHECK(jit_avx2_conv_fwd_kernel_f32::init_conf( + jcp_, *desc(), src_md(), weights_md(), dst_md(), *attr())); + + auto scratchpad = scratchpad_registry().registrar(); + jit_avx2_conv_fwd_kernel_f32::init_scratchpad(scratchpad, jcp_); + + return status::success; + } + + jit_conv_conf_t jcp_; + + protected: + bool set_default_formats() { + using namespace format_tag; + + const memory_desc_wrapper src_d(&src_md_); + const memory_desc_wrapper dst_d(&dst_md_); + + const auto dat_tag_nxc = utils::pick(ndims() - 3, nwc, nhwc, ndhwc); + const auto dat_tag_ncx = utils::pick(ndims() - 3, ncw, nchw, ncdhw); + const auto dat_tag_nCx8c + = utils::pick(ndims() - 3, nCw8c, nChw8c, nCdhw8c); + const auto curr_src_tag = src_d.matches_one_of_tag( + dat_tag_nxc, dat_tag_ncx, dat_tag_nCx8c); + const auto curr_dst_tag = dst_d.matches_one_of_tag( + dat_tag_nxc, dat_tag_ncx, dat_tag_nCx8c); + const auto is_data_layout_nxc + = IMPLICATION(curr_src_tag != dat_tag_nxc, + src_d.format_kind() == format_kind::any) + && IMPLICATION(curr_dst_tag != dat_tag_nxc, + dst_d.format_kind() == format_kind::any) + && utils::one_of(dat_tag_nxc, curr_src_tag, curr_dst_tag); + + const bool flat = IC() < 8; + auto src_tag = is_data_layout_nxc ? dat_tag_nxc + : flat ? dat_tag_ncx + : dat_tag_nCx8c; + auto dst_tag = is_data_layout_nxc ? dat_tag_nxc : dat_tag_nCx8c; + auto wei_tag = with_groups() + ? utils::pick(2 * ndims() - 6 + flat, gOIw8i8o, gOwi8o, + gOIhw8i8o, gOhwi8o, gOIdhw8i8o, gOdhwi8o) + : utils::pick(2 * ndims() - 6 + flat, OIw8i8o, Owi8o, + OIhw8i8o, Ohwi8o, OIdhw8i8o, Odhwi8o); + + return set_default_formats_common(src_tag, wei_tag, dst_tag); + } + }; + + jit_avx2_convolution_fwd_t(const pd_t *apd) : primitive_t(apd) {} + + typedef typename prec_traits::type data_t; + + status_t init(engine_t *engine) override { + CHECK(safe_ptr_assign(kernel_, + new jit_avx2_conv_fwd_kernel_f32( + pd()->jcp_, *pd()->attr(), *pd()->dst_md(0)))); + return kernel_->create_kernel(); + } + + status_t execute(const exec_ctx_t &ctx) const override { + execute_forward(ctx); + return status::success; + } + +private: + void execute_forward(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr kernel_; +}; + +struct jit_avx2_convolution_bwd_data_t : public primitive_t { + struct pd_t : public cpu_convolution_bwd_data_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const convolution_fwd_pd_t *hint_fwd_pd) + : cpu_convolution_bwd_data_pd_t(adesc, attr, hint_fwd_pd), jcp_() {} + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit:", avx2, ""), + jit_avx2_convolution_bwd_data_t); + + status_t init(engine_t *engine) { + bool ok = true && desc()->prop_kind == prop_kind::backward_data + && set_default_alg_kind(alg_kind::convolution_direct) + && expect_data_types(data_type::f32, data_type::f32, + data_type::undef, data_type::f32, data_type::f32) + && attr()->has_default_values() && !has_zero_dim_memory() + && set_default_formats(); + if (!ok) return status::unimplemented; + + status_t status = jit_avx2_conv_bwd_data_kernel_f32::init_conf(jcp_, + *desc(), *diff_src_md(), *weights_md(), *diff_dst_md()); + if (status != status::success) return status; + + auto scratchpad = scratchpad_registry().registrar(); + jit_avx2_conv_bwd_data_kernel_f32::init_scratchpad( + scratchpad, jcp_); + + return status::success; + } + + jit_conv_conf_t jcp_; + + protected: + bool set_default_formats() { + using namespace format_tag; + + const memory_desc_wrapper diff_src_d(&diff_src_md_); + const memory_desc_wrapper diff_dst_d(&diff_dst_md_); + + const auto dat_tag_nxc = utils::pick(ndims() - 3, nwc, nhwc, ndhwc); + const auto dat_tag_nCx8c + = utils::pick(ndims() - 3, nCw8c, nChw8c, nCdhw8c); + const auto curr_src_tag + = diff_src_d.matches_one_of_tag(dat_tag_nxc, dat_tag_nCx8c); + const auto curr_dst_tag + = diff_dst_d.matches_one_of_tag(dat_tag_nxc, dat_tag_nCx8c); + const auto is_data_layout_nxc + = IMPLICATION(curr_src_tag != dat_tag_nxc, + diff_src_d.format_kind() == format_kind::any) + && IMPLICATION(curr_dst_tag != dat_tag_nxc, + diff_dst_d.format_kind() == format_kind::any) + && utils::one_of(dat_tag_nxc, curr_src_tag, curr_dst_tag); + + auto dat_tag = is_data_layout_nxc ? dat_tag_nxc : dat_tag_nCx8c; + auto wei_tag = with_groups() + ? utils::pick(ndims() - 3, gOIw8o8i, gOIhw8o8i, gOIdhw8o8i) + : utils::pick(ndims() - 3, OIw8o8i, OIhw8o8i, OIdhw8o8i); + + return set_default_formats_common(dat_tag, wei_tag, dat_tag); + } + }; + + jit_avx2_convolution_bwd_data_t(const pd_t *apd) : primitive_t(apd) {} + + typedef typename prec_traits::type data_t; + + status_t init(engine_t *engine) override { + CHECK(safe_ptr_assign( + kernel_, new jit_avx2_conv_bwd_data_kernel_f32(pd()->jcp_))); + return kernel_->create_kernel(); + } + + status_t execute(const exec_ctx_t &ctx) const override { + execute_backward_data(ctx); + return status::success; + } + +private: + void execute_backward_data(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr kernel_; +}; + +struct jit_avx2_convolution_bwd_weights_t : public primitive_t { + struct pd_t : public cpu_convolution_bwd_weights_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const convolution_fwd_pd_t *hint_fwd_pd) + : cpu_convolution_bwd_weights_pd_t(adesc, attr, hint_fwd_pd) + , jcp_() {} + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit:", avx2, ""), + jit_avx2_convolution_bwd_weights_t); + + status_t init(engine_t *engine) { + bool ok = true && desc()->prop_kind == prop_kind::backward_weights + && set_default_alg_kind(alg_kind::convolution_direct) + && expect_data_types(data_type::f32, data_type::f32, + data_type::f32, data_type::f32, data_type::f32) + && attr()->has_default_values() && !has_zero_dim_memory() + && set_default_formats(); + if (!ok) return status::unimplemented; + + status_t status = jit_avx2_conv_bwd_weights_kernel_f32::init_conf( + jcp_, *desc(), *src_md(), *diff_weights_md(), + *diff_dst_md()); + if (status != status::success) return status; + + init_balancers(); + + auto scratchpad = scratchpad_registry().registrar(); + jit_avx2_conv_bwd_weights_kernel_f32::init_scratchpad( + scratchpad, jcp_); + + auto reducer_bia_scratchpad = memory_tracking::registrar_t( + scratchpad, memory_tracking::names::prefix_reducer_bia); + reducer_bia_conf_.init_scratchpad(reducer_bia_scratchpad); + + auto reducer_wei_scratchpad = memory_tracking::registrar_t( + scratchpad, memory_tracking::names::prefix_reducer_wei); + reducer_wei_conf_.init_scratchpad(reducer_wei_scratchpad); + + return status::success; + } + + jit_conv_conf_t jcp_; + cpu_reducer_t::conf_t reducer_bia_conf_; + cpu_reducer_t::conf_t reducer_wei_conf_; + + protected: + bool set_default_formats() { + using namespace format_tag; + const bool flat = IC() == 3; + + const memory_desc_wrapper src_d(&src_md_); + const memory_desc_wrapper diff_dst_d(&diff_dst_md_); + + const auto dat_tag_nxc = utils::pick(ndims() - 3, nwc, nhwc, ndhwc); + const auto dat_tag_ncx = utils::pick(ndims() - 3, ncw, nchw, ncdhw); + const auto dat_tag_nCx8c + = utils::pick(ndims() - 3, nCw8c, nChw8c, nCdhw8c); + const auto curr_src_tag = src_d.matches_one_of_tag( + dat_tag_nxc, dat_tag_ncx, dat_tag_nCx8c); + const auto curr_dst_tag = diff_dst_d.matches_one_of_tag( + dat_tag_nxc, dat_tag_ncx, dat_tag_nCx8c); + const auto is_data_layout_nxc + = IMPLICATION(curr_src_tag != dat_tag_nxc, + src_d.format_kind() == format_kind::any) + && IMPLICATION(curr_dst_tag != dat_tag_nxc, + diff_dst_d.format_kind() == format_kind::any) + && utils::one_of(dat_tag_nxc, curr_src_tag, curr_dst_tag); + + auto src_tag = is_data_layout_nxc ? dat_tag_nxc + : flat ? dat_tag_ncx + : dat_tag_nCx8c; + auto dst_tag = is_data_layout_nxc ? dat_tag_nxc : dat_tag_nCx8c; + auto wei_tag = with_groups() + ? utils::pick(2 * ndims() - 6 + flat, gOIw8i8o, gOwi8o, + gOIhw8i8o, gOhwi8o, gOIdhw8i8o, gOdhwi8o) + : utils::pick(2 * ndims() - 6 + flat, OIw8i8o, Owi8o, + OIhw8i8o, Ohwi8o, OIdhw8i8o, Odhwi8o); + + return set_default_formats_common(src_tag, wei_tag, dst_tag); + } + + private: + void init_balancers() { + const int max_threads = dnnl_get_max_threads(); + const size_t max_buffer_size = 1 << 21; /* just a heuristic */ + + if (with_bias()) { + reducer_bia_conf_.init(reduce_balancer_t(max_threads, + jcp_.oc_block, jcp_.ngroups * jcp_.nb_oc, jcp_.mb, + max_buffer_size, true)); + } + + reducer_wei_conf_.init(reduce_balancer_t(max_threads, + jcp_.kd * jcp_.kh * jcp_.kw * jcp_.ic_block * jcp_.oc_block, + jcp_.ngroups * jcp_.nb_ic * jcp_.nb_oc, jcp_.mb * jcp_.od, + max_buffer_size, true)); + } + }; + + jit_avx2_convolution_bwd_weights_t(const pd_t *apd) : primitive_t(apd) {} + + typedef typename prec_traits::type data_t; + + status_t init(engine_t *engine) override { + CHECK(safe_ptr_assign( + kernel_, new jit_avx2_conv_bwd_weights_kernel_f32(pd()->jcp_))); + CHECK(safe_ptr_assign(reducer_bias_, + new cpu_reducer_t(pd()->reducer_bia_conf_))); + CHECK(safe_ptr_assign(reducer_weights_, + new cpu_reducer_t(pd()->reducer_wei_conf_))); + CHECK(kernel_->create_kernel()); + CHECK(reducer_weights_->create_kernel()); + CHECK(reducer_bias_->create_kernel()); + return status::success; + } + + status_t execute(const exec_ctx_t &ctx) const override { + execute_backward_weights(ctx); + return status::success; + } + +private: + void execute_backward_weights(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr kernel_; + std::unique_ptr> reducer_weights_, + reducer_bias_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_common_1x1_conv_kernel.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_common_1x1_conv_kernel.hpp new file mode 100644 index 0000000000000000000000000000000000000000..9a926841fc0b13a92e34da8409d31e3f51e3aaa1 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_common_1x1_conv_kernel.hpp @@ -0,0 +1,117 @@ +/******************************************************************************* +* Copyright 2017-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_AVX512_COMMON_1X1_CONV_KERNEL_HPP +#define CPU_X64_JIT_AVX512_COMMON_1X1_CONV_KERNEL_HPP + +#include "common/c_types_map.hpp" +#include "common/memory_tracking.hpp" + +#include "cpu/x64/injectors/jit_uni_postops_injector.hpp" +#include "cpu/x64/jit_generator.hpp" +#include "cpu/x64/jit_primitive_conf.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +struct jit_avx512_common_1x1_conv_kernel : public jit_generator { + jit_avx512_common_1x1_conv_kernel(const jit_1x1_conv_conf_t &ajcp, + const primitive_attr_t &attr, const memory_desc_t &dst_md); + + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_common_1x1_conv_kernel) + + static status_t init_conf(jit_1x1_conv_conf_t &jcp, + const convolution_desc_t &cd, const memory_desc_wrapper &src_d, + const memory_desc_wrapper &weights_d, + const memory_desc_wrapper &dst_d, const primitive_attr_t &attr, + int nthreads, bool reduce_src); + + static void init_scratchpad(memory_tracking::registrar_t &scratchpad, + const jit_1x1_conv_conf_t &jcp); + + jit_1x1_conv_conf_t jcp; + const primitive_attr_t &attr_; + +private: + std::unique_ptr> + postops_injector_; + + constexpr static int isa_simd_width_ + = cpu_isa_traits::vlen / sizeof(float); + using reg64_t = const Xbyak::Reg64; + using zmm_t = const Xbyak::Zmm; + + reg64_t reg_bcast_data = r8; + reg64_t reg_load_data = r10; + reg64_t reg_output_data = r9; + reg64_t aux_reg_bcast_data = r14; + reg64_t aux1_reg_bcast_data = rbx; + reg64_t aux_reg_load_data = r15; + reg64_t imm_addr64 = aux_reg_load_data; + reg64_t aux_reg_output_data = abi_not_param1; + reg64_t reg_load_loop_work = rsi; + reg64_t reg_reduce_loop_work = r11; + reg64_t reg_bcast_loop_iter = rdx; + reg64_t reduce_loop_iter = abi_param1; + reg64_t reg_reduce_pos_flag = rax; + reg64_t reg_output_stride = r13; + reg64_t reg_bias_data = r12; + reg64_t reg_relu_ns = r13; + reg64_t reg_bcast_loop_work = aux1_reg_bcast_data; + reg64_t reg_load_dim_tail_mask = aux_reg_load_data; + reg64_t reg_long_offt = reg_bcast_data; + + Xbyak::Zmm vreg_bcast = Xbyak::Zmm(31); + Xbyak::Opmask k_load_dim_mask = Xbyak::Opmask(2); + Xbyak::Opmask k_load_dim_tail_mask = Xbyak::Opmask(3); + + constexpr static int reg64_size_ = sizeof(int64_t); + constexpr static int reg_bcast_loop_work_offt = 0; + constexpr static int reg_abi_param1_backup = 1 * reg64_size_; + constexpr static int reg_bcast_data_off = 2 * reg64_size_; + constexpr static int reg_dw_binary_output_off = 3 * reg64_size_; + constexpr static int stack_space_needed = 4 * reg64_size_; + + void bcast_loop(int load_loop_blk); + void reduce_loop(int load_loop_blk, int ur, int substep, bool wraparound); + + inline size_t get_output_offset(const bool is_out_layout_nxc, + const int i_load, const int i_ur, bool ignore_dw_conv = false) { + const size_t i_load_shift = is_out_layout_nxc + ? jcp.load_block + : (!ignore_dw_conv && jcp.with_dw_conv ? jcp.ow : jcp.bcast_dim) + * jcp.load_block; + const size_t i_ur_shift + = is_out_layout_nxc ? jcp.load_dim : jcp.load_block; + return jcp.typesize_out * (i_load * i_load_shift + i_ur * i_ur_shift); + } + + Xbyak::Address output_ptr( + const bool out_layout_nxc, const int i_load, const int i_ur); + void apply_postops(const bool is_out_layout_nxc, const int load_loop_blk, + const int ur); + void generate() override; + static void balance(jit_1x1_conv_conf_t &jcp); +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_common_1x1_convolution.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_common_1x1_convolution.hpp new file mode 100644 index 0000000000000000000000000000000000000000..2d60363915bd695a465b025a7de0158c4905276c --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_common_1x1_convolution.hpp @@ -0,0 +1,546 @@ +/******************************************************************************* +* Copyright 2017-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_AVX512_COMMON_1X1_CONVOLUTION_HPP +#define CPU_X64_JIT_AVX512_COMMON_1X1_CONVOLUTION_HPP + +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/memory_tracking.hpp" +#include "common/primitive.hpp" +#include "common/primitive_hashing.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_convolution_pd.hpp" +#include "cpu/dw_convolution_utils.hpp" +#include "cpu/platform.hpp" + +#include "cpu/x64/cpu_reducer.hpp" +#include "cpu/x64/jit_avx512_common_1x1_conv_kernel.hpp" +#include "cpu/x64/jit_transpose_utils.hpp" +#include "cpu/x64/jit_uni_1x1_conv_utils.hpp" +#include "cpu/x64/jit_uni_dw_convolution.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +template +struct jit_avx512_common_1x1_convolution_fwd_t : public primitive_t { + struct pd_t : public cpu_convolution_fwd_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const typename pd_t::base_class *hint_fwd_pd) + : cpu_convolution_fwd_pd_t(adesc, attr, hint_fwd_pd) + , jcp_() + , rtus_() {} + + pd_t(const pd_t &other) : cpu_convolution_fwd_pd_t(other) { + if (copy(other) != status::success) is_initialized_ = false; + } + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit_1x1:", avx512_core, ""), + jit_avx512_common_1x1_convolution_fwd_t); + + status_t init(engine_t *engine) { + using namespace utils; + bool ok = true && is_fwd() + && set_default_alg_kind(alg_kind::convolution_direct) + && expect_data_types(src_type, wei_type, dst_type, dst_type, + data_type::undef) + && attr()->has_default_values( + primitive_attr_t::skip_mask_t::post_ops, dst_type) + && !has_zero_dim_memory() && set_default_formats() + && attr_.set_default_formats(dst_md(0)) == status::success; + if (!ok) return status::unimplemented; + + const convolution_desc_t *conv_d = desc(); + const memory_desc_t *src_d = src_md(); + rtus_prepare(this, conv_d, src_d, dst_md(), weights_md()); + + CHECK(jit_avx512_common_1x1_conv_kernel::init_conf(jcp_, *conv_d, + *src_d, *weights_md(), *dst_md(), *attr(), + dnnl_get_max_threads(), rtus_.reduce_src_)); + if (jcp_.with_dw_conv) CHECK(depthwise_po_init(engine)); + + auto scratchpad = scratchpad_registry().registrar(); + jit_avx512_common_1x1_conv_kernel::init_scratchpad( + scratchpad, jcp_); + + rtus_prepare_space_info(this, scratchpad, jcp_.nthr); + + return status::success; + } + + const memory_desc_t *dst_1x1_md(int index = 0) const { + return cpu_convolution_fwd_pd_t::dst_md(index); + } + + const memory_desc_t *dst_md( + int index = 0, bool user_input = false) const override { + return jcp_.with_dw_conv + ? dw_conv_pd_->dst_md(index, user_input) + : cpu_convolution_fwd_pd_t::dst_md(index, user_input); + } + + const memory_desc_t *arg_md( + int arg, bool user_input = false) const override { + if (jcp_.with_dw_conv) { + switch (arg) { + case DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_SRC: + return cpu_convolution_fwd_pd_t::dst_md(0, user_input); + case DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_WEIGHTS: + return dw_conv_pd_->weights_md(0); + case DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_BIAS: + return dw_conv_pd_->weights_md(1); + default: break; + } + } + return convolution_fwd_pd_t::arg_md(arg, user_input); + } + + arg_usage_t arg_usage(int arg) const override { + if (arg == (DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_WEIGHTS)) + return arg_usage_t::input; + + if (arg == (DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_BIAS) + && attr_post_op_dw_inputs() > 1) + return arg_usage_t::input; + + return convolution_fwd_pd_t::arg_usage(arg); + } + + jit_1x1_conv_conf_t jcp_; + reduce_to_unit_stride_t rtus_; + using dw_pd_t = jit_avx512_common_dw_convolution_fwd_t::pd_t; + std::unique_ptr dw_conv_pd_; + + protected: + bool set_default_formats() { + using namespace format_tag; + + const memory_desc_wrapper src_d(&src_md_); + const memory_desc_wrapper dst_d(&dst_md_); + + const auto dat_tag_nxc = utils::pick(ndims() - 3, nwc, nhwc, ndhwc); + const auto dat_tag_nCx16c + = utils::pick(ndims() - 3, nCw16c, nChw16c, nCdhw16c); + const auto curr_src_tag + = src_d.matches_one_of_tag(dat_tag_nxc, dat_tag_nCx16c); + const auto curr_dst_tag + = dst_d.matches_one_of_tag(dat_tag_nxc, dat_tag_nCx16c); + const auto is_data_layout_nxc + = IMPLICATION(curr_src_tag != dat_tag_nxc, + src_d.format_kind() == format_kind::any) + && IMPLICATION(curr_dst_tag != dat_tag_nxc, + dst_d.format_kind() == format_kind::any) + && utils::one_of(dat_tag_nxc, curr_src_tag, curr_dst_tag); + auto dat_tag = is_data_layout_nxc ? dat_tag_nxc : dat_tag_nCx16c; + auto wei_tag = utils::pick(2 * ndims() - 6 + with_groups(), + OIw16i16o, gOIw16i16o, OIhw16i16o, gOIhw16i16o, OIdhw16i16o, + gOIdhw16i16o); + + return set_default_formats_common(dat_tag, wei_tag, dat_tag); + } + + status_t copy(const pd_t &other) { + jcp_ = other.jcp_; + rtus_ = other.rtus_; + if (other.dw_conv_pd_) { + dw_conv_pd_.reset(other.dw_conv_pd_->clone()); + if (!dw_conv_pd_) return status::out_of_memory; + } + return status::success; + } + + status_t depthwise_po_init(engine_t *engine) { + + using namespace memory_tracking; + auto &jcp_1x1 = jcp_; + primitive_attr_t attr_1x1(*attr()); + if (!attr_1x1.is_initialized()) return status::out_of_memory; + const auto &src_md = dst_md_; + const memory_desc_wrapper src_d(src_md); + const auto nthr = dnnl_get_max_threads(); + auto l2_cache = platform::get_per_core_cache_size(2) * nthr; + + // Note: A robust fusion implementation would be to check if both + // 1x1 conv and dw conv that are considered here for fusion are + // optimal independently. This would require creating a new + // primitive_desc through primitive_iterator & check if they match. + // Due to concern that these creations and/or checks could be heavy, + // for 1x1: Check that no better ISA is available. + // for dw: Always fuse with same ISA. + // Caveat: May be a better dw conv exists. + + // TODO: Add a check if better ISA exists following above note. + bool ok = true + && (attr_1x1.post_ops_.find(primitive_kind::sum) == -1) + // TODO: Below may be further tuned. + && (l2_cache * 2 < src_d.size()) + // load_grp_count check can be redundant due to l2 check + // above. Adding it explicitly as the current driver doesn't + // work if this condition fails. + && (jcp_1x1.load_grp_count < 2); + if (!ok) return status::unimplemented; + + int dw_po_index + = attr_1x1.post_ops_.find(primitive_kind::convolution); + convolution_desc_t cd_dw; + primitive_attr_t attr_dw; + CHECK(get_depthwise_conv_desc( + cd_dw, src_md, attr_1x1, attr_dw, dw_po_index)); + + CHECK(safe_ptr_assign( + dw_conv_pd_, new dw_pd_t(&cd_dw, &attr_dw, nullptr))); + CHECK(dw_conv_pd_->init(engine)); + auto &jcp_dw = dw_conv_pd_->jcp_; + + ok = true + && (dnnl_memory_desc_equal(&src_md, dw_conv_pd_->src_md(0))) + && (jcp_1x1.oc_without_padding % jcp_1x1.oc_block == 0) + && IMPLICATION( + jcp_dw.ow_block, jcp_dw.ow_block == jcp_dw.ow); + if (!ok) return status::unimplemented; + + assert(dw_conv_pd_->dst_md(0)->format_kind != format_kind::any); + assert(dw_conv_pd_->weights_md(0)->format_kind != format_kind::any); + assert(IMPLICATION( + dw_conv_pd_->weights_md(1)->data_type != data_type::undef, + dw_conv_pd_->weights_md(1)->format_kind + != format_kind::any)); + + jcp_dw.is_fused_conv = true; + // TODO: Support/experiment arbitary oc_work in dw conv. + // Until then we keep oc_work perfectly divisible. + while (jcp_1x1.nb_load % jcp_1x1.nb_load_blocking != 0) + --jcp_1x1.nb_load_blocking; + jcp_1x1.nb_load_blocking_max = jcp_1x1.nb_load_blocking; + + while (jcp_1x1.nb_load_blocking % jcp_dw.nb_ch_blocking != 0) + --jcp_dw.nb_ch_blocking; + + jcp_dw.dw_conv_buffer_oc + = jcp_1x1.nb_load_blocking * jcp_1x1.oc_block; + + const auto dat_tag_nxc = utils::pick(ndims() - 3, format_tag::nwc, + format_tag::nhwc, format_tag::ndhwc); + const bool is_data_nxc = utils::everyone_is( + dat_tag_nxc, jcp_1x1.src_tag, jcp_1x1.dst_tag); + if (!is_data_nxc) + jcp_1x1.bcast_loop_output_step = jcp_1x1.ur * jcp_1x1.load_block + * jcp_1x1.typesize_out; + + registrar_t scratchpad(scratchpad_registry_); + registrar_t dw_scratchpad(scratchpad, names::prefix_fusion); + + size_t dw_conv_buffer_size_ = (size_t)nthr * jcp_dw.kh * jcp_dw.iw + * jcp_dw.dw_conv_buffer_oc; + assert(dw_conv_buffer_size_); + dw_scratchpad.book(memory_tracking::names::key_fusion_inout_buffer, + dw_conv_buffer_size_, + types::data_type_size(dw_conv_pd_->src_md()->data_type)); + + jit_uni_dw_conv_fwd_kernel::init_scratchpad(dw_scratchpad, jcp_dw); + + return status::success; + } + }; + + template + friend status_t init_rtus_driver(conv_t *self); + + jit_avx512_common_1x1_convolution_fwd_t(const pd_t *apd) + : primitive_t(apd) {} + + typedef typename prec_traits::type src_data_t; + typedef typename prec_traits::type wei_data_t; + typedef typename prec_traits::type dst_data_t; + + status_t init(engine_t *engine) override { + CHECK(safe_ptr_assign(kernel_, + new jit_avx512_common_1x1_conv_kernel( + pd()->jcp_, *pd()->attr(), *pd()->dst_1x1_md(0)))); + CHECK(kernel_->create_kernel()); + + if (pd()->jcp_.with_dw_conv) { + CHECK(safe_ptr_assign(kernel_dw_, + new dw_conv_kernel_t( + pd()->dw_conv_pd_->jcp_, *pd()->dst_md(0)))); + CHECK(kernel_dw_->create_kernel()); + } + + CHECK(init_rtus_driver(this)); + return status::success; + } + + status_t execute(const exec_ctx_t &ctx) const override { + execute_forward(ctx); + return status::success; + } + +private: + void execute_forward(const exec_ctx_t &ctx) const; + void execute_forward_thr(const int ithr, const int nthr, + const src_data_t *src, const wei_data_t *weights, + const dst_data_t *bias, const wei_data_t *weights_dw, + const dst_data_t *bias_dw, dst_data_t *dst, + const memory_tracking::grantor_t &scratchpad, + const void *post_ops_binary_rhs_arg_vec, + const void *post_ops_binary_rhs_arg_vec_dw) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr kernel_; + std::unique_ptr> rtus_driver_; + using dw_conv_kernel_t = jit_uni_dw_conv_fwd_kernel_f32; + std::unique_ptr kernel_dw_; +}; + +using jit_avx512_common_1x1_convolution_fwd_f32_t + = jit_avx512_common_1x1_convolution_fwd_t; + +template +struct jit_avx512_common_1x1_convolution_bwd_data_t : public primitive_t { + struct pd_t : public cpu_convolution_bwd_data_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const convolution_fwd_pd_t *hint_fwd_pd) + : cpu_convolution_bwd_data_pd_t(adesc, attr, hint_fwd_pd) + , jcp_() + , rtus_() {} + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit_1x1:", avx512_core, ""), + jit_avx512_common_1x1_convolution_bwd_data_t); + + status_t init(engine_t *engine) { + bool ok = true && desc()->prop_kind == prop_kind::backward_data + && set_default_alg_kind(alg_kind::convolution_direct) + && expect_data_types(diff_src_type, wei_type, + data_type::undef, diff_dst_type, data_type::undef) + && attr()->has_default_values() && !has_zero_dim_memory() + && set_default_formats(); + if (!ok) return status::unimplemented; + + const convolution_desc_t *conv_d = desc(); + const memory_desc_t *diff_src_d = diff_src_md(); + rtus_prepare(this, conv_d, diff_src_d, diff_dst_md(), weights_md()); + + status_t status = jit_avx512_common_1x1_conv_kernel::init_conf(jcp_, + *conv_d, *diff_src_d, *weights_md(), *diff_dst_md(), + *attr(), dnnl_get_max_threads(), rtus_.reduce_src_); + if (status != status::success) return status; + + auto scratchpad = scratchpad_registry().registrar(); + jit_avx512_common_1x1_conv_kernel::init_scratchpad( + scratchpad, jcp_); + + rtus_prepare_space_info(this, scratchpad, jcp_.nthr); + + return status::success; + } + + // TODO (Roma): structs conf header cleanup + jit_1x1_conv_conf_t jcp_; + reduce_to_unit_stride_t rtus_; + + protected: + bool set_default_formats() { + using namespace format_tag; + + const memory_desc_wrapper diff_src_d(&diff_src_md_); + const memory_desc_wrapper diff_dst_d(&diff_dst_md_); + + const auto dat_tag_nxc = utils::pick(ndims() - 3, nwc, nhwc, ndhwc); + const auto dat_tag_nCx16c + = utils::pick(ndims() - 3, nCw16c, nChw16c, nCdhw16c); + const auto curr_src_tag = diff_src_d.matches_one_of_tag( + dat_tag_nxc, dat_tag_nCx16c); + const auto curr_dst_tag = diff_dst_d.matches_one_of_tag( + dat_tag_nxc, dat_tag_nCx16c); + const auto is_data_layout_nxc + = IMPLICATION(curr_src_tag != dat_tag_nxc, + diff_src_d.format_kind() == format_kind::any) + && IMPLICATION(curr_dst_tag != dat_tag_nxc, + diff_dst_d.format_kind() == format_kind::any) + && utils::one_of(dat_tag_nxc, curr_src_tag, curr_dst_tag); + auto dat_tag = is_data_layout_nxc ? dat_tag_nxc : dat_tag_nCx16c; + auto wei_tag = utils::pick(2 * ndims() - 6 + with_groups(), + IOw16o16i, gIOw16o16i, IOhw16o16i, gIOhw16o16i, IOdhw16o16i, + gIOdhw16o16i); + + return set_default_formats_common(dat_tag, wei_tag, dat_tag); + } + }; + + template + friend status_t init_rtus_driver(conv_t *self); + + jit_avx512_common_1x1_convolution_bwd_data_t(const pd_t *apd) + : primitive_t(apd) {} + + typedef typename prec_traits::type diff_dst_data_t; + typedef typename prec_traits::type wei_data_t; + typedef typename prec_traits::type diff_src_data_t; + + status_t init(engine_t *engine) override { + CHECK(safe_ptr_assign(kernel_, + new jit_avx512_common_1x1_conv_kernel( + pd()->jcp_, *pd()->attr(), *pd()->dst_md(0)))); + CHECK(kernel_->create_kernel()); + CHECK(init_rtus_driver(this)); + return status::success; + } + + status_t execute(const exec_ctx_t &ctx) const override { + execute_backward_data(ctx); + return status::success; + } + +private: + void execute_backward_data(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr kernel_; + std::unique_ptr> rtus_driver_; +}; + +using jit_avx512_common_1x1_convolution_bwd_data_f32_t + = jit_avx512_common_1x1_convolution_bwd_data_t; + +struct jit_avx512_common_1x1_convolution_bwd_weights_t : public primitive_t { + struct pd_t : public cpu_convolution_bwd_weights_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const convolution_fwd_pd_t *hint_fwd_pd) + : cpu_convolution_bwd_weights_pd_t(adesc, attr, hint_fwd_pd) + , jcp_() + , rtus_() {} + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit_1x1:", avx512_core, ""), + jit_avx512_common_1x1_convolution_bwd_weights_t); + + status_t init(engine_t *engine) { + bool ok = true && desc()->prop_kind == prop_kind::backward_weights + && set_default_alg_kind(alg_kind::convolution_direct) + && expect_data_types(data_type::f32, data_type::f32, + data_type::f32, data_type::f32, data_type::f32) + && attr()->has_default_values() && !has_zero_dim_memory() + && set_default_formats(); + if (!ok) return status::unimplemented; + + const convolution_desc_t *conv_d = desc(); + const memory_desc_t *src_d = src_md(); + rtus_prepare(this, conv_d, src_d, diff_dst_md(), diff_weights_md()); + + status_t status = jit_avx512_common_1x1_conv_kernel::init_conf(jcp_, + *conv_d, *src_d, *diff_weights_md(), *diff_dst_md(), + *attr(), dnnl_get_max_threads(), rtus_.reduce_src_); + if (status != status::success) return status; + + init_balancers(); + + auto scratchpad = scratchpad_registry().registrar(); + jit_avx512_common_1x1_conv_kernel::init_scratchpad( + scratchpad, jcp_); + + auto reducer_bia_scratchpad = memory_tracking::registrar_t( + scratchpad, memory_tracking::names::prefix_reducer_bia); + reducer_bia_conf_.init_scratchpad(reducer_bia_scratchpad); + + rtus_prepare_space_info(this, scratchpad, jcp_.nthr); + + return status::success; + } + + // TODO (Roma): structs conf header cleanup + jit_1x1_conv_conf_t jcp_; + cpu_reducer_t::conf_t reducer_bia_conf_; + reduce_to_unit_stride_t rtus_; + + protected: + bool set_default_formats() { + using namespace format_tag; + + const memory_desc_wrapper src_d(&src_md_); + const memory_desc_wrapper diff_dst_d(&diff_dst_md_); + + const auto dat_tag_nxc = utils::pick(ndims() - 3, nwc, nhwc, ndhwc); + const auto dat_tag_nCx16c + = utils::pick(ndims() - 3, nCw16c, nChw16c, nCdhw16c); + const auto curr_src_tag + = src_d.matches_one_of_tag(dat_tag_nxc, dat_tag_nCx16c); + const auto curr_dst_tag = diff_dst_d.matches_one_of_tag( + dat_tag_nxc, dat_tag_nCx16c); + const auto is_data_layout_nxc + = IMPLICATION(curr_src_tag != dat_tag_nxc, + src_d.format_kind() == format_kind::any) + && IMPLICATION(curr_dst_tag != dat_tag_nxc, + diff_dst_d.format_kind() == format_kind::any) + && utils::one_of(dat_tag_nxc, curr_src_tag, curr_dst_tag); + + auto dat_tag = is_data_layout_nxc ? dat_tag_nxc : dat_tag_nCx16c; + auto wei_tag = utils::pick(2 * ndims() - 6 + with_groups(), + OIw16i16o, gOIw16i16o, OIhw16i16o, gOIhw16i16o, OIdhw16i16o, + gOIdhw16i16o); + + return set_default_formats_common(dat_tag, wei_tag, dat_tag); + } + + private: + void init_balancers() { + const size_t max_buffer_size = jcp_.nthr * 3 * 5 * 5 * 16 * 16; + if (with_bias()) { + reducer_bia_conf_.init(reduce_balancer_t(jcp_.nthr, + jcp_.oc_block, jcp_.ngroups * jcp_.nb_load, jcp_.mb, + max_buffer_size, true)); + } + } + }; + + template + friend status_t init_rtus_driver(conv_t *self); + + jit_avx512_common_1x1_convolution_bwd_weights_t(const pd_t *apd) + : primitive_t(apd) {} + + typedef typename prec_traits::type data_t; + + status_t init(engine_t *engine) override; + + status_t execute(const exec_ctx_t &ctx) const override { + execute_backward_weights(ctx); + return status::success; + } + +private: + void execute_backward_weights(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr kernel_; + std::unique_ptr> acc_ker_; + std::unique_ptr> reducer_bias_; + std::unique_ptr trans_kernel_; + std::unique_ptr> rtus_driver_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_common_conv_kernel.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_common_conv_kernel.hpp new file mode 100644 index 0000000000000000000000000000000000000000..af21ae99799c24f3b1619bd0cf3f811fed7f70bf --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_common_conv_kernel.hpp @@ -0,0 +1,505 @@ +/******************************************************************************* +* Copyright 2016-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_AVX512_COMMON_CONV_KERNEL_HPP +#define CPU_X64_JIT_AVX512_COMMON_CONV_KERNEL_HPP + +#include "common/c_types_map.hpp" +#include "common/memory_tracking.hpp" + +#include "cpu/x64/injectors/jit_uni_postops_injector.hpp" +#include "cpu/x64/jit_generator.hpp" +#include "cpu/x64/jit_primitive_conf.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +template +struct _jit_avx512_common_conv_fwd_kernel : public jit_generator { + + _jit_avx512_common_conv_fwd_kernel(const jit_conv_conf_t &ajcp, + const primitive_attr_t &attr, const memory_desc_t &dst_md); + + DECLARE_CPU_JIT_AUX_FUNCTIONS(_jit_avx512_common_conv_fwd_kernel) + + jit_conv_conf_t jcp; + const primitive_attr_t &attr_; + +private: + constexpr static int isa_simd_width_ + = cpu_isa_traits::vlen / sizeof(float); + using reg64_t = const Xbyak::Reg64; + enum { + typesize = sizeof(float), + ker_reg_base_idx = 28, + }; + + reg64_t param = abi_param1; + reg64_t reg_inp = r8; + reg64_t reg_ker = r9; + reg64_t reg_out = r10; + + reg64_t reg_owb = r12; + + reg64_t aux_reg_inp = r14; + reg64_t aux_reg_ker = r15; + + reg64_t reg_channel = rsi; + reg64_t reg_bias = rdx; + + reg64_t aux_reg_ker_d = r9; + reg64_t aux_reg_inp_d = rbx; + reg64_t reg_ki = r10; + + reg64_t reg_kj = rax; + reg64_t reg_relu_ns = rax; + reg64_t reg_oi = rbx; + reg64_t reg_kh = abi_not_param1; + + reg64_t reg_tmp = rbp; + + reg64_t reg_long_offt = r11; + reg64_t reg_out_long_offt = r14; + reg64_t reg_ker_long_offt = r11; + reg64_t reg_tail = aux_reg_ker; + reg64_t reg_load_work = reg_tail; + + /* binary post-ops operand */ + reg64_t temp_offset_reg = r12; + + Xbyak::Opmask k_oc_tail_mask = Xbyak::Opmask(2); + const Xbyak::Opmask postops_mask = Xbyak::Opmask(3); + + inline Vmm vmm_ker(int i_ic) { + assert(i_ic < 4); + return Vmm(ker_reg_base_idx + i_ic); + } + + inline int vmm_out_idx(int i_ur, int i_oc) { + const int idx = i_ur * jcp.nb_oc_blocking + i_oc; + assert(idx < ker_reg_base_idx); + return idx; + } + + inline Vmm vmm_out(int i_ur, int i_oc) { + return Vmm(vmm_out_idx(i_ur, i_oc)); + } + + inline Vmm vmm_inp(int i_ic, int nb_x_blocking) { + int idx = i_ic + nb_x_blocking * jcp.ur_w; + assert(idx < 31); + return Vmm(idx); + } + + Xbyak::Reg64 imm_addr64 = r15; + Vmm vmm_wei = Vmm(31); + + std::unique_ptr> + postops_injector_; + + inline void prepare_output(int ur_w); + inline void apply_postops(int ur_w); + inline void store_output(int ur_w); + inline void compute_loop_fma(int ur_w, int pad_l, int pad_r); + inline void compute_loop_fma_core(int ur_w, int pad_l, int pad_r); + inline void compute_loop(int ur_w, int pad_l, int pad_r); + + void generate() override; + + inline size_t get_output_offset(int oi, int n_oc_block) { + const bool is_nxc_layout = is_dst_layout_nxc(); + size_t ow_str = is_nxc_layout ? jcp.ngroups * jcp.oc : jcp.oc_block; + size_t ocb_str = is_nxc_layout + ? jcp.oc_block + : (size_t)jcp.od * jcp.oh * jcp.ow * jcp.oc_block; + + return jcp.typesize_out * (n_oc_block * ocb_str + oi * ow_str); + } + + inline size_t get_input_offset(int ki, int ic, int oi, int pad_l) { + const bool is_nxc_layout = is_src_layout_nxc(); + size_t iw_str = is_nxc_layout ? jcp.ngroups * jcp.ic + : (!jcp.is_1stconv ? jcp.ic_block : 1); + size_t ic_str = !jcp.is_1stconv || is_nxc_layout + ? 1 + : (size_t)jcp.iw * jcp.ih * jcp.id; + size_t iw_idx = ki * (jcp.dilate_w + 1) + oi * jcp.stride_w - pad_l; + + return jcp.typesize_in * (iw_idx * iw_str + ic * ic_str); + } + + inline int get_kernel_offset( + int ki, int ic, int n_oc_block, int ker_number) { + return jcp.typesize_in * jcp.oc_block + * (n_oc_block * jcp.nb_ic * jcp.ic_block * jcp.kh * jcp.kw + * jcp.kd + + (ic + ker_number) + ki * jcp.ic_block); + } + + inline int get_ow_start(int ki, int pad_l) { + return nstl::max(0, + utils::div_up(pad_l - ki * (jcp.dilate_w + 1), jcp.stride_w)); + } + + inline int get_ow_end(int ur_w, int ki, int pad_r) { + return ur_w + - nstl::max(0, + utils::div_up( + pad_r - (jcp.kw - 1 - ki) * (jcp.dilate_w + 1), + jcp.stride_w)); + } + inline bool is_src_layout_nxc() { + return utils::one_of(jcp.src_tag, format_tag::ndhwc, format_tag::nhwc, + format_tag::nwc); + } + inline bool is_dst_layout_nxc() { + return utils::one_of(jcp.dst_tag, format_tag::ndhwc, format_tag::nhwc, + format_tag::nwc); + } +}; + +struct jit_avx512_common_conv_fwd_kernel { + + jit_avx512_common_conv_fwd_kernel(const jit_conv_conf_t &ajcp, + const primitive_attr_t &attr, const memory_desc_t &dst_md) + : kernel_(nullptr) { + switch (ajcp.oc_block) { + case 16: + kernel_ = new _jit_avx512_common_conv_fwd_kernel( + ajcp, attr, dst_md); + return; + case 8: + kernel_ = new _jit_avx512_common_conv_fwd_kernel( + ajcp, attr, dst_md); + return; + case 4: + kernel_ = new _jit_avx512_common_conv_fwd_kernel( + ajcp, attr, dst_md); + return; + default: assert(!"invalid channel blocking"); + } + } + + status_t create_kernel() { + if (kernel_) return kernel_->create_kernel(); + return status::out_of_memory; + } + + ~jit_avx512_common_conv_fwd_kernel() { delete kernel_; } + + enum { typesize = sizeof(float) }; + + static status_t init_conf(jit_conv_conf_t &jcp, + const convolution_desc_t &cd, memory_desc_t &src_pd, + memory_desc_t &weights_pd, memory_desc_t &dst_pd, + memory_desc_t &bias_pd, primitive_attr_t &attr, int nthreads); + static void init_scratchpad(memory_tracking::registrar_t &scratchpad, + const jit_conv_conf_t &jcp); + + void operator()(jit_conv_call_s *p) const { (*kernel_)(p); } + + const Xbyak::uint8 *jit_ker() const { return kernel_->jit_ker(); } + +private: + DNNL_DISALLOW_COPY_AND_ASSIGN(jit_avx512_common_conv_fwd_kernel); + jit_generator *kernel_; +}; + +template +struct _jit_avx512_common_conv_bwd_data_kernel_f32 : public jit_generator { + + _jit_avx512_common_conv_bwd_data_kernel_f32(const jit_conv_conf_t &ajcp) + : jit_generator(jit_name()), jcp(ajcp) {} + + DECLARE_CPU_JIT_AUX_FUNCTIONS(_jit_avx512_common_conv_bwd_data_kernel_f32) + jit_conv_conf_t jcp; + +private: + using reg64_t = const Xbyak::Reg64; + enum { + typesize = sizeof(float), + ker_reg_base_idx = 28, + }; + + reg64_t param = abi_param1; + reg64_t reg_dst = r8; + reg64_t reg_ker = r9; + reg64_t reg_src = r10; + + reg64_t reg_iwb = r14; + + reg64_t aux_reg_dst = r14; + reg64_t aux_reg_ker = r15; + + reg64_t aux_reg_dst_d = rbx; + reg64_t aux_reg_ker_d = r9; + reg64_t reg_ki = r10; + + reg64_t reg_kj = rax; + reg64_t reg_oi = rbx; + reg64_t reg_kh = abi_not_param1; + + reg64_t reg_channel = rsi; + + reg64_t reg_tmp = rbp; + reg64_t reg_long_offt = r14; + + reg64_t reg_tail = aux_reg_ker; + reg64_t reg_load_work = reg_tail; + + Xbyak::Opmask k_ic_tail_mask = Xbyak::Opmask(1); + + inline Vmm vmm_ker(int i_ic) { + assert(i_ic < 4); + return Vmm(ker_reg_base_idx + i_ic); + } + inline Vmm vmm_inp(int i_ic, int nb_x_blocking) { + int idx = i_ic + nb_x_blocking * jcp.ur_w; + assert(idx < 31); + return Vmm(idx); + } + inline Vmm vmm_out(int i_ur, int i_oc) { + int idx = i_ur + i_oc * jcp.ur_w; + assert(idx < ker_reg_base_idx); + return Vmm(idx); + } + + Vmm vmm_wei = Vmm(31); + + inline void prepare_output(int ur_w); + inline void store_output(int ur_w); + inline void compute_loop_fma(int ur_w, int l_overflow, int r_overflow); + inline void compute_loop_fma_core( + int ur_w, int l_overflow, int r_overflow, int k_offset); + inline void compute_loop( + int ur_w, int l_overflow, int r_overflow, int k_offset = 0); + void generate() override; + + inline int get_iw_start(int ki, int l_overflow) { + int res = (jcp.iw - 1 + jcp.r_pad) % jcp.stride_w + + l_overflow * jcp.stride_w + - (jcp.kw - 1 - ki) * (jcp.dilate_w + 1); + while (res < 0) + res += jcp.stride_w; + + return res; + } + + inline int get_iw_end(int ur_w, int ki, int r_overflow) { + if (utils::one_of(ur_w, jcp.iw, jcp.ur_w_tail)) + ur_w += nstl::min(0, jcp.r_pad); // remove negative padding + int res = (ur_w - 1 + jcp.l_pad) % jcp.stride_w + + r_overflow * jcp.stride_w - ki * (jcp.dilate_w + 1); + while (res < 0) + res += jcp.stride_w; + + return ur_w - res; + } + + inline size_t get_diff_src_offset(int iw, int icb) { + const bool is_nxc_layout = is_dsrc_layout_nxc(); + size_t iw_str = is_nxc_layout ? jcp.ngroups * jcp.ic : jcp.ic_block; + size_t icb_str = is_nxc_layout + ? jcp.ic_block + : (size_t)jcp.id * jcp.ih * jcp.iw * jcp.ic_block; + + return typesize * (icb * icb_str + iw * iw_str); + } + + inline ptrdiff_t get_dst_offset(int iw, int oc, int kw) { + ptrdiff_t ow + = (iw + jcp.l_pad - kw * (jcp.dilate_w + 1)) / jcp.stride_w; + ptrdiff_t ow_str + = is_ddst_layout_nxc() ? jcp.ngroups * jcp.oc : jcp.oc_block; + + return typesize * (ow * ow_str + oc); + }; + + inline bool is_dsrc_layout_nxc() { + return utils::one_of(jcp.src_tag, format_tag::ndhwc, format_tag::nhwc, + format_tag::nwc); + } + inline bool is_ddst_layout_nxc() { + return utils::one_of(jcp.dst_tag, format_tag::ndhwc, format_tag::nhwc, + format_tag::nwc); + } +}; + +struct jit_avx512_common_conv_bwd_data_kernel_f32 { + + jit_avx512_common_conv_bwd_data_kernel_f32(const jit_conv_conf_t &ajcp) + : kernel_(nullptr) { + switch (ajcp.ic_block) { + case 16: + kernel_ = new _jit_avx512_common_conv_bwd_data_kernel_f32< + Xbyak::Zmm>(ajcp); + return; + case 8: + kernel_ = new _jit_avx512_common_conv_bwd_data_kernel_f32< + Xbyak::Ymm>(ajcp); + return; + case 4: + kernel_ = new _jit_avx512_common_conv_bwd_data_kernel_f32< + Xbyak::Xmm>(ajcp); + return; + default: assert(!"invalid channel blocking"); + } + } + + status_t create_kernel() { + if (kernel_) return kernel_->create_kernel(); + return status::out_of_memory; + } + + ~jit_avx512_common_conv_bwd_data_kernel_f32() { delete kernel_; } + + enum { typesize = sizeof(float) }; + + static status_t init_conf(jit_conv_conf_t &jcp, + const convolution_desc_t &cd, memory_desc_t &diff_src_d, + memory_desc_t &weights_d, memory_desc_t &diff_dst_d, int nthreads); + static void init_scratchpad(memory_tracking::registrar_t &scratchpad, + const jit_conv_conf_t &jcp); + + void operator()(const jit_conv_call_s *p) const { (*kernel_)(p); } + const Xbyak::uint8 *jit_ker() const { return kernel_->jit_ker(); } + +private: + DNNL_DISALLOW_COPY_AND_ASSIGN(jit_avx512_common_conv_bwd_data_kernel_f32); + jit_generator *kernel_; +}; + +struct jit_avx512_common_conv_bwd_weights_kernel_f32 : public jit_generator { + + jit_avx512_common_conv_bwd_weights_kernel_f32(const jit_conv_conf_t &ajcp) + : jit_generator(jit_name()), jcp(ajcp) {} + + void generate() override { + if (jcp.harness != harness_nxc) + generate_kernel(); + else + generate_microkernel(); + } + + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_common_conv_bwd_weights_kernel_f32) + + static status_t init_conf(jit_conv_conf_t &jcp, + const convolution_desc_t &cd, memory_desc_t &src_md, + memory_desc_t &diff_weights_md, memory_desc_t &diff_bias_md, + memory_desc_t &diff_dst_md, int nthreads); + static void init_scratchpad(memory_tracking::registrar_t &scratchpad, + const jit_conv_conf_t &jcp); + + jit_conv_conf_t jcp; + +private: + using reg64_t = const Xbyak::Reg64; + enum { typesize = sizeof(float) }; + static const int max_ur_w; + static const int min_oh_reduce; + + reg64_t param = abi_param1; + reg64_t reg_input = rax; + reg64_t reg_kernel = rdx; + reg64_t reg_output = rsi; + reg64_t b_ic = abi_not_param1; + reg64_t kj = r8; + reg64_t reg_kh = r9; + reg64_t reg_ur_w_trips = r10; + reg64_t reg_oj = r15; + reg64_t reg_tmp = r14; + reg64_t reg_long_offt = r14; + reg64_t reg_icb = rbx; + + reg64_t ki = r11; + reg64_t reg_kd_count = r12; + reg64_t reg_oi = r12; + reg64_t reg_d_index = r13; + reg64_t reg_input_d = r15; + reg64_t reg_output_d = rbx; + reg64_t aux_reg_input = r12; + reg64_t aux_reg_kernel = r13; + reg64_t reg_bias = rbx; + reg64_t reg_oc_tail = r14; + + Xbyak::Opmask k_oc_mask = Xbyak::Opmask(2); + + inline void bias_kernel_2d(); + inline void bias_kernel_3d(); + inline void maybe_zero_kernel(); + inline void compute_oh_step_unroll_ow_icblock( + int ic_block_step, int max_ur_w); + inline void od_step_comeback_pointers(); + inline void oh_step_comeback_pointers(); + inline void compute_oh_step_unroll_ow(int ic_block_step, int max_ur_w); + inline void compute_ic_block_step(int ur_w, int pad_l, int pad_r, + int ic_block_step, int input_offset, int kernel_offset, + int output_offset, bool input_wraparound = false); + inline void compute_ic_block_step_fma(int ur_w, int pad_l, int pad_r, + int ic_block_step, int input_offset, int kernel_offset, + int output_offset, bool input_wraparound); + inline void compute_ic_block_step_fma_expl(int ur_w, int pad_l, int pad_r, + int ic_block_step, int input_offset, int kernel_offset, + int output_offset, bool input_wraparound); + inline void compute_oh_step_common(int ic_block_step, int max_ur_w); + inline void compute_oh_step_disp(); + inline void compute_oh_loop_common(); + inline void compute_oh_loop_partial(); + inline void compute_od_loop_partial(); + + inline void compute_loop(); + inline bool is_src_layout_nxc() { + return utils::one_of(jcp.src_tag, format_tag::ndhwc, format_tag::nhwc, + format_tag::nwc); + } + inline bool is_ddst_layout_nxc() { + return utils::one_of(jcp.dst_tag, format_tag::ndhwc, format_tag::nhwc, + format_tag::nwc); + } + + inline ptrdiff_t get_full_src_offset( + int i_iw, int i_ic, ptrdiff_t input_offset) { + const bool is_nxc_layout = is_src_layout_nxc(); + const size_t w_shift_st = (jcp.is_hw_transp ? jcp.iw : 1) + * (jcp.is_1stconv ? 1 : jcp.ic_block); + ptrdiff_t w_shift = is_nxc_layout ? jcp.ngroups * jcp.ic : w_shift_st; + ptrdiff_t ic_shift = jcp.is_1stconv && !is_nxc_layout + ? (ptrdiff_t)jcp.ih * jcp.iw * jcp.id + : 1; + + ptrdiff_t local_input_offset = i_iw * w_shift + i_ic * ic_shift; + return input_offset + typesize * local_input_offset; + }; + + inline int get_iw_idx(int ow, int kw, int l_pad) { + return ow * jcp.stride_w + kw * (jcp.dilate_w + 1) - l_pad; + } + + void generate_kernel(); + void generate_microkernel(); + + static void balance(const jit_conv_conf_t &j, int &nthr, int &nthr_mb, + int &nthr_g, int &nthr_oc_b, int &nthr_ic_b, int nthreads); +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_common_convolution.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_common_convolution.hpp new file mode 100644 index 0000000000000000000000000000000000000000..b241cade391ebdf7d89e26cc842bbb2597fa6cdf --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_common_convolution.hpp @@ -0,0 +1,279 @@ +/******************************************************************************* +* Copyright 2016-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_AVX512_COMMON_CONVOLUTION_HPP +#define CPU_X64_JIT_AVX512_COMMON_CONVOLUTION_HPP + +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/memory_tracking.hpp" +#include "common/primitive.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_convolution_pd.hpp" +#include "cpu/x64/cpu_barrier.hpp" +#include "cpu/x64/cpu_reducer.hpp" + +#include "cpu/x64/jit_avx512_common_conv_kernel.hpp" +#include "cpu/x64/jit_transpose_utils.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +template +struct jit_avx512_common_convolution_fwd_t : public primitive_t { + struct pd_t : public cpu_convolution_fwd_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const typename pd_t::base_class *hint_fwd_pd) + : cpu_convolution_fwd_pd_t(adesc, attr, hint_fwd_pd), jcp_() {} + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit:", avx512_core, ""), + jit_avx512_common_convolution_fwd_t); + + status_t init(engine_t *engine) { + bool ok = true && is_fwd() + && set_default_alg_kind(alg_kind::convolution_direct) + && expect_data_types(src_type, wei_type, dst_type, dst_type, + data_type::undef) + && attr()->has_default_values( + primitive_attr_t::skip_mask_t::post_ops, dst_type) + && !has_zero_dim_memory(); + if (!ok) return status::unimplemented; + + CHECK(jit_avx512_common_conv_fwd_kernel::init_conf(jcp_, *desc(), + src_md_, weights_md_, dst_md_, bias_md_, attr_, + dnnl_get_max_threads())); + + auto scratchpad = scratchpad_registry().registrar(); + jit_avx512_common_conv_fwd_kernel::init_scratchpad( + scratchpad, jcp_); + + return status::success; + } + + jit_conv_conf_t jcp_; + }; + + jit_avx512_common_convolution_fwd_t(const pd_t *apd) : primitive_t(apd) {} + + typedef typename prec_traits::type src_data_t; + typedef typename prec_traits::type wei_data_t; + typedef typename prec_traits::type dst_data_t; + + status_t init(engine_t *engine) override { + CHECK(safe_ptr_assign(kernel_, + new jit_avx512_common_conv_fwd_kernel( + pd()->jcp_, *pd()->attr(), *pd()->dst_md(0)))); + return kernel_->create_kernel(); + } + + status_t execute(const exec_ctx_t &ctx) const override { + if (pd()->ndims() == 3) + execute_forward_1d(ctx); + else if (pd()->ndims() == 4) + execute_forward_2d(ctx); + else if (pd()->ndims() == 5) + execute_forward_3d(ctx); + else + assert(false); + + if (pd()->wants_zero_pad_dst()) ctx.zero_pad_output(DNNL_ARG_DST); + return status::success; + } + +private: + void prepare_padded_bias(const dst_data_t *&bias, + const memory_tracking::grantor_t &scratchpad) const; + void execute_forward_1d(const exec_ctx_t &ctx) const; + void execute_forward_2d(const exec_ctx_t &ctx) const; + void execute_forward_3d(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr kernel_; +}; + +template +struct jit_avx512_common_convolution_bwd_data_t : public primitive_t { + struct pd_t : public cpu_convolution_bwd_data_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const convolution_fwd_pd_t *hint_fwd_pd) + : cpu_convolution_bwd_data_pd_t(adesc, attr, hint_fwd_pd), jcp_() {} + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit:", avx512_core, ""), + jit_avx512_common_convolution_bwd_data_t); + + status_t init(engine_t *engine) { + bool ok = true && desc()->prop_kind == prop_kind::backward_data + && set_default_alg_kind(alg_kind::convolution_direct) + && expect_data_types(diff_src_type, wei_type, + data_type::undef, diff_dst_type, data_type::undef) + && attr()->has_default_values() && !has_zero_dim_memory(); + if (!ok) return status::unimplemented; + + status_t status + = jit_avx512_common_conv_bwd_data_kernel_f32::init_conf( + jcp_, *desc(), diff_src_md_, weights_md_, + diff_dst_md_, dnnl_get_max_threads()); + if (status != status::success) return status; + + auto scratchpad = scratchpad_registry().registrar(); + jit_avx512_common_conv_bwd_data_kernel_f32::init_scratchpad( + scratchpad, jcp_); + + return status::success; + } + + jit_conv_conf_t jcp_; + }; + + jit_avx512_common_convolution_bwd_data_t(const pd_t *apd) + : primitive_t(apd) {} + + typedef typename prec_traits::type diff_dst_data_t; + typedef typename prec_traits::type wei_data_t; + typedef typename prec_traits::type diff_src_data_t; + + status_t init(engine_t *engine) override { + CHECK(safe_ptr_assign(kernel_, + new jit_avx512_common_conv_bwd_data_kernel_f32(pd()->jcp_))); + return kernel_->create_kernel(); + } + + status_t execute(const exec_ctx_t &ctx) const override { + if (pd()->ndims() == 3) + execute_backward_data_1d(ctx); + else if (pd()->ndims() == 4) + execute_backward_data_2d(ctx); + else if (pd()->ndims() == 5) + execute_backward_data_3d(ctx); + else + assert(false); + return status::success; + } + +private: + void execute_backward_data_1d(const exec_ctx_t &ctx) const; + void execute_backward_data_2d(const exec_ctx_t &ctx) const; + void execute_backward_data_3d(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr kernel_; +}; + +template +struct jit_avx512_common_convolution_bwd_weights_t : public primitive_t { + struct pd_t : public cpu_convolution_bwd_weights_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const convolution_fwd_pd_t *hint_fwd_pd) + : cpu_convolution_bwd_weights_pd_t(adesc, attr, hint_fwd_pd) + , jcp_() {} + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit:", avx512_core, ""), + jit_avx512_common_convolution_bwd_weights_t); + + status_t init(engine_t *engine) { + bool ok = true && desc()->prop_kind == prop_kind::backward_weights + && set_default_alg_kind(alg_kind::convolution_direct) + && expect_data_types(src_type, diff_weights_type, + diff_weights_type, diff_dst_type, data_type::undef) + && attr()->has_default_values() && !has_zero_dim_memory(); + if (!ok) return status::unimplemented; + + status_t status + = jit_avx512_common_conv_bwd_weights_kernel_f32::init_conf( + jcp_, *desc(), src_md_, diff_weights_md_, + diff_bias_md_, diff_dst_md_, + dnnl_get_max_threads()); + if (status != status::success) return status; + + init_balancers(); + + auto scratchpad = scratchpad_registry().registrar(); + jit_avx512_common_conv_bwd_weights_kernel_f32::init_scratchpad( + scratchpad, jcp_); + + auto reducer_bia_scratchpad = memory_tracking::registrar_t( + scratchpad, memory_tracking::names::prefix_reducer_bia); + reducer_bia_conf_.init_scratchpad(reducer_bia_scratchpad); + + return status; + } + + jit_conv_conf_t jcp_; + typename cpu_reducer_t::conf_t reducer_bia_conf_; + + private: + void init_balancers() { + const size_t max_buffer_size = jcp_.nthr * 3 * 5 * 5 * 16 * 16; + if (with_bias()) { + reducer_bia_conf_.init(reduce_balancer_t(jcp_.nthr, + jcp_.oc_block, jcp_.ngroups * jcp_.nb_oc, jcp_.mb, + max_buffer_size, true)); + } + } + }; + + jit_avx512_common_convolution_bwd_weights_t(const pd_t *apd) + : primitive_t(apd) {} + + typedef typename prec_traits::type src_data_t; + typedef typename prec_traits::type diff_dst_data_t; + typedef typename prec_traits::type diff_weights_data_t; + + status_t init(engine_t *engine) override; + + status_t execute(const exec_ctx_t &ctx) const override { + execute_backward_weights(ctx); + return status::success; + } + +private: + void execute_backward_weights(const exec_ctx_t &ctx) const; + void prepare_scratchpad_data(const exec_ctx_t &ctx) const; + struct thread_info_t; + void compute_diff_weights_nxc(const thread_info_t *) const; + void compute_diff_weights(const thread_info_t *) const; + void compute_diff_weights_2d(const thread_info_t *) const; + void compute_diff_weights_3d(const thread_info_t *) const; + void reduce_diff_weights(const thread_info_t *) const; + void reduce_diff_weights_3d(const thread_info_t *) const; + void compute_diff_bias(const thread_info_t *) const; + void reduce_diff_bias(const thread_info_t *) const; + + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + int nthr_, nthr_mb_, nthr_g_, nthr_oc_b_, nthr_ic_b_; + + std::unique_ptr kernel_; + std::unique_ptr> acc_ker_; + std::unique_ptr> reducer_bias_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_amx_1x1_conv_kernel.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_amx_1x1_conv_kernel.hpp new file mode 100644 index 0000000000000000000000000000000000000000..1fa1ba63d2a071bad6b5bb464dc2d964ac673f8e --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_amx_1x1_conv_kernel.hpp @@ -0,0 +1,178 @@ +/******************************************************************************* +* Copyright 2020-2022 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_AVX512_CORE_AMX_1X1_CONV_KERNEL_HPP +#define CPU_X64_JIT_AVX512_CORE_AMX_1X1_CONV_KERNEL_HPP + +#include "common/c_types_map.hpp" +#include "common/memory_tracking.hpp" + +#include "cpu/x64/injectors/jit_uni_postops_injector.hpp" +#include "cpu/x64/jit_generator.hpp" +#include "cpu/x64/jit_primitive_conf.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +struct jit_avx512_core_amx_1x1_fwd_kernel_t : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_amx_1x1_fwd_kernel_t) + + jit_avx512_core_amx_1x1_fwd_kernel_t(const jit_conv_conf_t &ajcp, + const primitive_attr_t &attr, const memory_desc_t &dst_md); + + static status_t init_conf(jit_conv_conf_t &jcp, + const convolution_desc_t &cd, memory_desc_t &src_pd, + memory_desc_t &weights_pd, memory_desc_t &dst_pd, + memory_desc_t &bias_pd, primitive_attr_t &attr, int nthreads); + static void init_scratchpad(memory_tracking::registrar_t &scratchpad, + const jit_conv_conf_t &jcp, const primitive_attr_t &attr); + + // Tile-registers decomposition + enum { C_BASE = 0, W_BASE = 6, I_BASE = 4 }; + + void tile_configure(char *tcgf_buff); + + jit_conv_conf_t jcp; + const primitive_attr_t &attr_; + +private: + constexpr static int isa_simd_width_ + = cpu_isa_traits::vlen / sizeof(float); + std::unique_ptr> + postops_injector_; + + enum { + zmm_idx_limit_bf16 = 29, + zmm_idx_limit_int8 = 27, + }; + + int row_count_ = 0; + int buf_count_ = 0; + bool is_store_done_ = false; + bool is_buffer_empty_ = true; + bool check_last_sb_ = false; + bool last_oc_block_flag_ = false; + + /* data regs */ + const Xbyak::Reg64 inp_ptr = r15; + const Xbyak::Reg64 wei_ptr = r14; + const Xbyak::Reg64 out_ptr = r13; + const Xbyak::Reg64 wsp_ptr = r12; + + const Xbyak::Reg64 reg_bias = r11; + const Xbyak::Reg64 reg_ptr_scales = r10; + const Xbyak::Reg64 reg_ptr_sum_scale = r9; + const Xbyak::Reg64 reg_ptr_sum_zp = rax; + const Xbyak::Reg64 aux_reg_saturation = reg_ptr_sum_scale; + const Xbyak::Reg64 reg_last_h = r8; + + const Xbyak::Reg64 stride_seq = rbx; + const Xbyak::Reg64 stride_nhwc = rsi; + const Xbyak::Reg64 reg_tmp = abi_not_param1; + + const Xbyak::Reg64 reg_oc_blocks = rdx; + const Xbyak::Reg64 reg_is_osb = rsi; + const Xbyak::Reg64 reg_postop = abi_not_param1; + const Xbyak::Reg64 reg_scratch = reg_bias; + const Xbyak::Reg64 reg_tilebuff = reg_ptr_scales; + /* zero-point */ + const Xbyak::Reg64 reg_zp_compensation = reg_last_h; + const Xbyak::Reg64 reg_src_zero_point = reg_oc_blocks; + const Xbyak::Reg64 reg_dst_zero_point = rax; + + /* scale */ + const Xbyak::Reg64 reg_ptr_dst_scale = reg_ptr_scales; + + const Xbyak::Zmm zmm_bias = zmm31; + const Xbyak::Zmm zmm_saturation = zmm_bias; + const Xbyak::Zmm zmm_zero = zmm30; + const Xbyak::Zmm zmm_prev_dst = zmm29; + const Xbyak::Zmm zmm_sum_zp = zmm26; + /* zero-point */ + const Xbyak::Zmm zmm_zp = zmm29; + const Xbyak::Zmm zmm_src_zp = zmm28; + const Xbyak::Zmm zmm_dst_zp = zmm27; + + const Xbyak::Reg64 bin_injector_helper_reg_1 = r14; + const Xbyak::Reg64 bin_injector_helper_reg_2 = r15; + const Xbyak::Reg64 bin_injector_helper_reg_3 = r11; + + const Xbyak::Opmask ktail_mask = k2; + + bool is_bf16() const; + + void init_runtime_counters(); + + int get_out_tensor(int h, int i) const; + int get_inp_tensor(int h) const; + int get_wei_tensor(int i) const; + int get_ic_tail() const; + + size_t out_h_shift() const; + size_t out_w_shift() const; + size_t inp_offset(int ih, int iw, int icb) const; + size_t out_row_offset(int h, int w, int ocb) const; + + void prepare_output(); + + void cvt2ps(data_type_t type_in, const Xbyak::Zmm ymm_in, + const Xbyak::Operand &op, bool mask_flag); + Xbyak::Zmm zmm_out(const int idx) { + const int upper_limit + = is_bf16() ? zmm_idx_limit_bf16 : zmm_idx_limit_int8; + assert(upper_limit > idx); + MAYBE_UNUSED(upper_limit); + return Xbyak::Zmm(idx); + } + Xbyak::Zmm zmm_mask( + const Xbyak::Zmm zmm_in, bool mask_flag, bool store = false); + Xbyak::Ymm ymm_mask( + const Xbyak::Ymm ymm_in, bool mask_flag, bool store = false); + + void update_buffer_pointers(); + void interleave_store(); + void apply_sum(const Xbyak::Zmm zmm_out, const float *p_sum_scale, + const int32_t *p_sum_zp, const Xbyak::Address &addr, + const bool mask_flag); + void apply_postops(const Xbyak::Zmm zmm_out, const float *p_sum_scale, + const int32_t *p_sum_zp, const Xbyak::Address &addr, + const size_t off, const bool mask_flag); + static bool is_fast_postops(const jit_conv_conf_t &jcp); + void store_output_vectors_int8(int ocb, int osb); + void store_output_vector_int8( + const Xbyak::Zmm zmm_out, int ocb, int h, int w); + inline void store_output_ymm_bf16( + const int idx, const Xbyak::Address &addr, const bool mask_flag); + void store_output_vectors_bf16(int ocb, int osb); + void store_output_vector_bf16( + const Xbyak::Zmm zmm_out, int ocb, int h, int w); + void store_output_vectors(int ocb, int osb); + void store_output_vector(const Xbyak::Zmm zmm_out, int ocb, int h, int w); + void store_output(bool do_store, bool is_tail); + void icb_loop(bool do_store); + void osb_loop(int nb_os = 1); + + void generate() override; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_amx_1x1_convolution.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_amx_1x1_convolution.hpp new file mode 100644 index 0000000000000000000000000000000000000000..6be172595c8cacb0950cde95d7d0ca152f8be19c --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_amx_1x1_convolution.hpp @@ -0,0 +1,135 @@ +/******************************************************************************* +* Copyright 2020-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_AVX512_CORE_AMX_1x1_CONVOLUTION_HPP +#define CPU_X64_JIT_AVX512_CORE_AMX_1x1_CONVOLUTION_HPP + +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/memory_tracking.hpp" +#include "common/primitive.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_convolution_pd.hpp" + +#include "cpu/x64/amx_tile_configure.hpp" +#include "cpu/x64/jit_avx512_core_amx_1x1_conv_kernel.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +struct jit_avx512_core_amx_1x1_convolution_fwd_t : public primitive_t { + struct pd_t : public cpu_convolution_fwd_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const typename pd_t::base_class *hint_fwd_pd) + : cpu_convolution_fwd_pd_t(adesc, attr, hint_fwd_pd), jcp_() {} + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit_1x1:", jcp_.isa, ""), + jit_avx512_core_amx_1x1_convolution_fwd_t); + + status_t init(engine_t *engine) { + using namespace data_type; + using smask_t = primitive_attr_t::skip_mask_t; + bool is_bf16_convolution + = (src_md(0)->data_type == bf16 + && weights_md(0)->data_type == bf16 + && utils::one_of(dst_md(0)->data_type, f32, bf16)) + && IMPLICATION(with_bias(), + utils::one_of(weights_md(1)->data_type, f32, bf16)) + && attr()->has_default_values(smask_t::post_ops); + bool is_int8_convolution + = utils::one_of(src_md(0)->data_type, s8, u8) + && weights_md(0)->data_type == s8 + && utils::one_of( + dst_md(0)->data_type, s8, u8, s32, f32, bf16) + && IMPLICATION(with_bias(), + utils::one_of( + weights_md(1)->data_type, f32, s32, s8, u8)) + && attr()->has_default_values(smask_t::scales_runtime + | smask_t::post_ops + | smask_t::zero_points_runtime + | smask_t::sum_dt, + dst_md(0)->data_type); + + bool ok = is_fwd() + && set_default_alg_kind(alg_kind::convolution_direct) + && (is_bf16_convolution || is_int8_convolution) + && !has_zero_dim_memory() && attr_scales_ok() + && attr()->post_ops_.check_sum_consistency( + dst_md(0)->data_type, + /* is_int8 */ is_int8_convolution) + && zero_points_ok(); + if (!ok) return status::unimplemented; + + CHECK(jit_avx512_core_amx_1x1_fwd_kernel_t::init_conf(jcp_, *desc(), + src_md_, weights_md_, dst_md_, bias_md_, attr_, + dnnl_get_max_threads())); + + auto scratchpad = scratchpad_registry().registrar(); + jit_avx512_core_amx_1x1_fwd_kernel_t::init_scratchpad( + scratchpad, jcp_, *attr()); + + return status::success; + } + + jit_conv_conf_t jcp_; + + protected: + bool zero_points_ok() const { + // Only common zero points are supported -> mask should only be 0 + int mask_src = 0, mask_dst = 0; + attr()->zero_points_.get(DNNL_ARG_SRC, &mask_src); + attr()->zero_points_.get(DNNL_ARG_DST, &mask_dst); + return attr()->zero_points_.has_default_values(DNNL_ARG_WEIGHTS) + && mask_src == 0 && mask_dst == 0; + } + }; + + jit_avx512_core_amx_1x1_convolution_fwd_t(const pd_t *apd) + : primitive_t(apd) {} + + status_t init(engine_t *engine) override { + CHECK(safe_ptr_assign(kernel_, + new jit_avx512_core_amx_1x1_fwd_kernel_t( + pd()->jcp_, *pd()->attr(), *pd()->dst_md(0)))); + return kernel_->create_kernel(); + } + + status_t execute(const exec_ctx_t &ctx) const override { + const auto &_pd = pd(); + if (_pd->jcp_.is_depthwise) return status::unimplemented; + return execute_forward(ctx); + } + +private: + status_t execute_forward(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + void prepare_padded_bias(const char *&bias, + const memory_tracking::grantor_t &scratchpad) const; + + std::unique_ptr kernel_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino^=l0,\:0,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_amx_conv_kernel.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_amx_conv_kernel.hpp new file mode 100644 index 0000000000000000000000000000000000000000..689ddc488fcb7ef0773e9b18475691f6b8001880 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_amx_conv_kernel.hpp @@ -0,0 +1,805 @@ +/******************************************************************************* +* Copyright 2020-2022 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_AVX512_CORE_AMX_CONV_KERNEL_HPP +#define CPU_X64_JIT_AVX512_CORE_AMX_CONV_KERNEL_HPP + +#include + +#include "common/c_types_map.hpp" +#include "common/memory_tracking.hpp" + +#include "cpu/x64/injectors/jit_uni_postops_injector.hpp" +#include "cpu/x64/jit_avx512_core_bf16cvt.hpp" +#include "cpu/x64/jit_generator.hpp" +#include "cpu/x64/jit_primitive_conf.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +/* This struct computes the compensation for src_zero_point related to + * padding */ +struct jit_avx512_core_amx_compute_zp_pbuff_t : public jit_generator { + + using reg64_t = const Xbyak::Reg64; + + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_amx_compute_zp_pbuff_t) + + jit_avx512_core_amx_compute_zp_pbuff_t(const jit_conv_conf_t &ajcp) + : jit_generator( + jit_name(), nullptr, MAX_CODE_SIZE, true, avx512_core_amx) + , jcp(ajcp) {} + + static const int max_regs_ur = 30; + +private: + jit_conv_conf_t jcp; + + typedef enum { no_last_block, last_ic_block } ic_block_t; + const int ic_inner_block = 4; + + Xbyak::Label permb_idx_label; + Xbyak::Label ic_mask_label; + + const reg64_t reg_zp_pbuff = r8; + const reg64_t reg_src_zero_point = r9; + const reg64_t reg_filt = r10; + const reg64_t aux_reg_filt = r11; + const reg64_t aux_reg_filt_d = r15; + + const reg64_t reg_oc_blocks = r12; + const reg64_t reg_icb = r13; + const reg64_t reg_oi = r14; + const reg64_t reg_kj = rax; + const reg64_t reg_ki = rbx; + const reg64_t reg_overflow = reg_kj; + const reg64_t reg_scratch = rsi; + + const Xbyak::Zmm zmm_one = Xbyak::Zmm(31); + const Xbyak::Zmm zmm_permb = Xbyak::Zmm(30); + + const Xbyak::Opmask kmask_ic_block = Xbyak::Opmask(1); + const Xbyak::Opmask ktail_mask = Xbyak::Opmask(2); + + void prepare_output(int ur_w); + void store_output(int ur_w, bool last_oc_block_flag); + void compute_ker(int ur_w, int pad_l, int pad_r, + ic_block_t last_ic_block_flag, bool padded); + void kh_loop(int ur_w, int pad_l, int pad_r, ic_block_t last_ic_block_flag, + bool handle_h_pad); + void kd_loop(int ur_w, int pad_l, int pad_r, ic_block_t last_ic_block_flag, + bool handle_h_pad); + void icb_loop(int ur_w, int pad_l, int pad_r, bool handle_h_pad); + void unroll_width(const bool h_padding); + + void generate() override; + + Xbyak::Zmm zmm_out(int i_ur, int i_oc) { + int idx = i_ur * jcp.nb_oc_blocking + i_oc; + assert(idx < max_regs_ur); + return Xbyak::Zmm(idx); + } + int get_ow_start(int ki, int pad_l) { + return nstl::max(0, + utils::div_up(pad_l - ki * (jcp.dilate_w + 1), jcp.stride_w)); + } + int get_ow_end(int ur_w, int ki, int pad_r) { + int filter_overlap = pad_r - (jcp.kw - 1 - ki) * (jcp.dilate_w + 1); + return ur_w - nstl::max(0, utils::div_up(filter_overlap, jcp.stride_w)); + } +}; + +struct jit_avx512_core_amx_copy_to_wbuffer_t : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_amx_copy_to_wbuffer_t) + + using reg64_t = Xbyak::Reg64; + + jit_avx512_core_amx_copy_to_wbuffer_t(const jit_conv_conf_t &ajcp) + : jit_generator( + jit_name(), nullptr, MAX_CODE_SIZE, true, avx512_core_amx) + , jcp(ajcp) {} + +private: + jit_conv_conf_t jcp; + + const reg64_t reg_src = rax; + const reg64_t reg_dst = rbx; + const reg64_t reg_tmp = rdx; + + const Xbyak::Opmask kmask_load = k2; + + const Xbyak::Zmm zmm_src = zmm0; + const Xbyak::Zmm zmm_dst = zmm1; + const Xbyak::Zmm zmm_idx = zmm2; + const Xbyak::Zmm zmm_zero = zmm3; + + void generate() override; +}; + +struct jit_avx512_core_amx_copy_to_pbuffer_t : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_amx_copy_to_pbuffer_t) + + using reg64_t = Xbyak::Reg64; + + jit_avx512_core_amx_copy_to_pbuffer_t(const jit_conv_conf_t &ajcp) + : jit_generator( + jit_name(), nullptr, MAX_CODE_SIZE, true, avx512_core_amx) + , jcp(ajcp) {} + +private: + jit_conv_conf_t jcp; + + const reg64_t reg_inp_ptr = r15; + const reg64_t reg_out_ptr = r14; + + const reg64_t reg_aux_inp_ptr = r13; + const reg64_t reg_aux_out_ptr = r12; + + const reg64_t reg_khp = r10; + + /* relow stuff */ + const reg64_t reg_kht = r11; + const reg64_t reg_tov = r9; + const reg64_t reg_bov = r8; + const reg64_t reg_kwp = rax; + const reg64_t reg_lov = reg_aux_inp_ptr; + const reg64_t reg_rov = rbx; + const reg64_t reg_save_out_ptr = rdx; + const reg64_t reg_cnt = rbp; + /* relow stuff */ + + /* non-relow stuff */ + const reg64_t reg_kdp = abi_not_param1; + const reg64_t reg_kdc = rbp; + const reg64_t reg_khc = r11; + + const reg64_t reg_kh_over = r8; + const reg64_t reg_tover = rax; + const reg64_t reg_bover = rbx; + + const reg64_t reg_owb = rdx; + /* non-relow stuff */ + + const reg64_t reg_tmp = rsi; + + const Xbyak::Opmask &ktail_mask = k2; + + const Xbyak::Ymm &ymm_tmp = ymm0; + const Xbyak::Zmm &zmm_tmp = zmm0; + const Xbyak::Zmm &zmm_zero = zmm1; + + void generate() override; + void copy_row(int icb); + void copy_row_body(int lpad, int iw_len, int icb); + void copy_row_reduced_lowering(); +}; + +struct jit_avx512_core_amx_fwd_kernel_t : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_amx_fwd_kernel_t) + + jit_avx512_core_amx_fwd_kernel_t(const jit_conv_conf_t &ajcp, + const primitive_attr_t &attr, const memory_desc_t &dst_md); + + status_t create_kernel() override; + + static status_t init_conf(jit_conv_conf_t &jcp, + const convolution_desc_t &cd, memory_desc_t &src_pd, + memory_desc_t &weights_pd, memory_desc_t &dst_pd, + memory_desc_t &bias_pd, primitive_attr_t &attr, int nthreads); + static status_t init_scratchpad(memory_tracking::registrar_t &scratchpad, + const jit_conv_conf_t &jcp, const primitive_attr_t &attr); + + inline int accum_with_upper_bound( + int upper_bound, int lower_value, int upper_value) { + return nstl::min(upper_bound, + nstl::min(upper_bound, lower_value) + + nstl::max(0, upper_bound - upper_value)); + } + + /* Calculate and store the limits relevant to 'ow_block'. These limits + * allow the driver code to determine which 'ow_block' is currently being + * executed. There can be at most 5 different 'ow_block', each corresponding + * to: + * - l_pad block + * - middle block (no padding) + * - middle & r_pad shift block + * - r_pad (full) block + * - r_pad tail + * */ + static void set_ow_blk_limits(jit_conv_conf_t &jcp); + + /* Calculate and store the limits relevant to each 'oh_block'. Each + * 'oh_block' size is 'nb_oh_blocking * oh_per_tile'. These limits allow + * the driver code to determine which 'oh_block' is currently being + * executed, and what is the oh value required to advance the limits index. + * + * There can be at most 6 different 'oh_blk', depending on the sizes of + * 't_pad_output', 'b_pad_output' and their overlap with + * 'nb_oh_blocking * oh_per_tile'. + * + * For example, given the following input dimensions of {height_size = 12, + * oh_blk_size = 2, top_padding = 5 (t_pad), bottom_padding = 2 (b_pad)}, + * the 4 output height blocks and limits are: + * + * H: _ H_blks:_ Limits: + * 0 | | 0|X| + * 1 | | |X|_4 + * 2 | | t_pad + * 3 | | _ + * 4 |_| 1|X| + * 5 | | |_|_5 + * 6 | | 2| | + * 7 | | |_|_9 + * 8 | | + * 9 |_| _ + * 10| | b_pad 3|X| + * 11|_| |X|_11 + * + * -where 'x' represents + * an 'h_blk' with output + * padding. + * */ + static void set_oh_blk_limits(jit_conv_conf_t &jcp); + + void tile_configure(char *tcfg_buff); + + jit_conv_conf_t jcp; + const primitive_attr_t &attr_; + + const jit_avx512_core_amx_copy_to_pbuffer_t ©_to_pbuffer() const { + return *copy_to_pbuffer_; + } + const jit_avx512_core_amx_copy_to_wbuffer_t ©_to_wbuffer() const { + return *copy_to_wbuffer_; + } + const jit_avx512_core_amx_compute_zp_pbuff_t &zp_pbuff_kernel() const { + return *zp_pbuff_kernel_; + } + +private: + constexpr static int isa_simd_width_ + = cpu_isa_traits::vlen / sizeof(float); + std::unique_ptr> + postops_injector_; + std::unique_ptr copy_to_pbuffer_; + std::unique_ptr copy_to_wbuffer_; + std::unique_ptr zp_pbuff_kernel_; + + enum { + zmm_idx_limit_bf16 = 29, + zmm_idx_limit_int8 = 27, + }; + + int prv_width_ = 0; + int row_count_ = 0; + bool is_store_done_ = false; + bool is_buffer_empty_ = true; + + struct w_pad_output { + int l_pad_output; + int r_pad_output; + w_pad_output(int l_, int r_) : l_pad_output(l_), r_pad_output(r_) {} + }; + std::queue w_padding; + + /* data regs */ + const Xbyak::Reg64 reg_inp_ptr = r15; + const Xbyak::Reg64 reg_wei_ptr = r14; + const Xbyak::Reg64 reg_out_ptr = r13; + const Xbyak::Reg64 reg_wsp_ptr = r12; + + const Xbyak::Reg64 reg_kd = r9; + + const Xbyak::Reg64 reg_bias = r11; + const Xbyak::Reg64 reg_ptr_scales = r10; + const Xbyak::Reg64 reg_ptr_sum_scale = r9; + const Xbyak::Reg64 reg_ptr_sum_zp = abi_not_param1; + const Xbyak::Reg64 reg_aux_saturation = reg_ptr_sum_scale; + + const Xbyak::Reg64 reg_inp_stride = rbx; + const Xbyak::Reg64 reg_wei_stride = rdx; + // zero-point computation + const Xbyak::Reg64 reg_zp_compensation = rax; + const Xbyak::Reg64 reg_src_zero_point = r8; + const Xbyak::Reg64 reg_zero_point_pbuff = rsi; + const Xbyak::Reg64 reg_dst_zero_point = abi_not_param1; + const Xbyak::Reg64 reg_dst_scale = reg_dst_zero_point; + + // rbp - reserved for EVEX compression + const Xbyak::Reg64 reg_last_h = abi_not_param1; + const Xbyak::Reg64 reg_jmp_blk = reg_last_h; + + // temporary, used in generate() function only + const Xbyak::Reg64 reg_oc_blocks = rax; + const Xbyak::Reg64 reg_tmp = r8; + + const Xbyak::Opmask &ktail_mask = k2; + + const Xbyak::Zmm &zmm_bias = zmm31; + const Xbyak::Zmm &zmm_saturation = zmm_bias; + const Xbyak::Zmm &zmm_zero = zmm30; + const Xbyak::Zmm &zmm_prev_dst = zmm29; + const Xbyak::Zmm &zmm_sum_zp = zmm26; + /* zero-point */ + const Xbyak::Zmm &zmm_zp = zmm29; + const Xbyak::Zmm &zmm_src_zp = zmm28; + const Xbyak::Zmm &zmm_dst_zp = zmm27; + /* dst scale */ + const Xbyak::Zmm &zmm_dst_scale = zmm25; + + const Xbyak::Reg64 bin_injector_helper_reg_1 = r14; + const Xbyak::Reg64 bin_injector_helper_reg_2 = r15; + const Xbyak::Reg64 bin_injector_helper_reg_3 = r11; + + // AUX: Steps, shifts and offsets + size_t get_inp_icb_step() const; + size_t get_wei_icb_step() const; + size_t get_inp_d_step() const; + size_t get_inp_h_step() const; + size_t get_wei_d_step() const; + size_t get_wei_h_step() const; + size_t get_out_ocb_offset(int ohb, int ocb, size_t typesize) const; + size_t get_out_row_offset(int ohb, int ocb, int j, size_t typesize) const; + size_t get_out_shift(int width, size_t typesize) const; + size_t get_wsp_ocb_offset(int ohb, int ocb) const; + size_t get_wsp_row_offset(int ohb, int ocb, int j) const; + size_t get_wsp_shift() const; + size_t get_wei_offset(int ocb, int kw) const; + size_t get_inp_shift() const; + size_t get_inp_offset(int ohb, int kw) const; + size_t get_zp_comp_offset(int ocb, int zp_h, int zp_w) const; + int get_zp_index_offset( + int index, int mid, int s_pad_output, int e_pad_output); + + int get_out_tensor(int h, int i, bool is_h_tail = false) const; + int get_inp_tensor(int h, bool is_h_tail = false) const; + int get_wei_tensor(int i) const; + + void prepare_output(int tail); + void init_runtime_counters(bool start_with_last_tile_block); + size_t reduce_to_block(const int block_size, const int pad_output); + size_t reduce_to_blocked_dims(const int dim_size, const int block_size, + const int s_pad_output, const int e_pad_output); + void cvt2ps(data_type_t type_in, const Xbyak::Zmm &ymm_in, + const Xbyak::Operand &op, bool mask_flag = false); + Xbyak::Zmm zmm_out(const int idx) { + const int upper_limit = jcp.src_dt == data_type::bf16 + ? zmm_idx_limit_bf16 + : zmm_idx_limit_int8; + assert(upper_limit > idx); + MAYBE_UNUSED(upper_limit); + return Xbyak::Zmm(idx); + } + Xbyak::Ymm ymm_mask( + const Xbyak::Ymm &zmm_in, bool mask_flag, bool store = false); + Xbyak::Zmm zmm_mask( + const Xbyak::Zmm &zmm_in, bool mask_flag, bool store = false); + void apply_sum(const Xbyak::Zmm &zmm_out, const float *p_sum_scale, + const int32_t *p_sum_zp, const Xbyak::Address &addr, + const bool mask_flag); + void apply_postops(const Xbyak::Zmm &zmm_out, const float *p_sum_scale, + const int32_t *p_sum_zp, const Xbyak::Address &addr, + const size_t off, const bool mask_flag); + inline void store_output_ymm_bf16( + const int idx, const Xbyak::Address &addr, const bool mask_flag); + void store_output_vector_bf16( + const Xbyak::Zmm &zmm_out, int ocb, int h, int w); + void store_output_vector_int8(const Xbyak::Zmm &zmm_out, int ocb, int h, + int w, const bool compute_zp, const int zp_h, const int zp_w); + void store_output_vector(const Xbyak::Zmm &zmm_out, int ocb, int h, int w, + const bool compute_zp = false, const int zp_h = 0, + const int zp_w = 0); + void store_output(int width, int tail, bool do_store, + const bool handle_h_block, const int t_pad_output, + const int b_pad_output, const int l_pad_output, + const int r_pad_output, const bool is_last_oh_block, + const bool zp_3d_pad = false); + void interleave_store(int width, int const t_pad_output, + int const b_pad_output, const bool zp_3d_pad = false); + void compute_icb_loop(int width, bool do_store, const bool handle_h_block, + const int t_pad_output, const int b_pad_output, + const int l_pad_output, const int r_pad_output, + const bool zp_3d_pad, const bool is_last_oh_block = false); + void dispatch_icb_loop(int width, bool do_store, const int l_pad_output, + const int r_pad_output, const bool zp_3d_pad); + void dispatch_zp_3d_compute(int width, bool do_store, + const int l_pad_output, const int r_pad_output); + void compute_ow_loop(); + + void generate() override; +}; + +struct jit_avx512_core_amx_bwd_data_copy_kernel_t : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_amx_bwd_data_copy_kernel_t) + + using reg64_t = Xbyak::Reg64; + + jit_avx512_core_amx_bwd_data_copy_kernel_t(jit_conv_conf_t ajcp) + : jit_generator( + jit_name(), nullptr, MAX_CODE_SIZE, true, avx512_core_amx) + , jcp(ajcp) {} + +private: + jit_conv_conf_t jcp; + + // pointers + const reg64_t reg_ptr_inp = r15; + const reg64_t reg_ptr_out = r14; + + // auxiliary pointers + const reg64_t reg_ptr_aux_inp_h = r13; + const reg64_t reg_ptr_aux_inp_w = r12; + const reg64_t reg_ptr_aux_out = r11; + + // variables + const reg64_t reg_khp = r10; // kh padding + const reg64_t reg_tov = r9; // top overflow + const reg64_t reg_bov = reg_tov; // bottom overflow + const reg64_t reg_kwp = rax; // kw padding + const reg64_t reg_lov = rbx; // left overflow + const reg64_t reg_rov = abi_not_param1; // right overflow + const reg64_t reg_kd = r8; // 3d filter + + // counters + const reg64_t reg_cnt_khp = rdx; + const reg64_t reg_cnt_tmp = rbp; + const reg64_t reg_cnt_ocb = rsi; + + const reg64_t reg_tmp = reg_cnt_tmp; + + const Xbyak::Opmask ktail_mask = k2; + + const Xbyak::Zmm zmm_tmp = zmm1; + const Xbyak::Zmm zmm_zero = zmm0; + + void generate() override; + void copy_row(bool is_masked); + void kd_loop(bool is_masked); +}; + +struct jit_avx512_core_amx_bwd_data_kernel_t : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_amx_bwd_data_kernel_t) + + jit_avx512_core_amx_bwd_data_kernel_t( + const jit_conv_conf_t ajcp, const primitive_attr_t &attr) + : jit_generator( + jit_name(), nullptr, MAX_CODE_SIZE, true, avx512_core_amx) + , jcp(ajcp) + , attr_(attr) + , eltwise_injector_(nullptr) { + if (jcp.with_eltwise) + eltwise_injector_ = new jit_uni_eltwise_injector_f32( + this, jcp.eltwise); + bwd_data_copy_kernel_ + = new jit_avx512_core_amx_bwd_data_copy_kernel_t(jcp); + } + status_t create_kernel() override { + CHECK(jit_generator::create_kernel()); + CHECK(bwd_data_copy_kernel_->create_kernel()); + return status::success; + } + ~jit_avx512_core_amx_bwd_data_kernel_t() { + delete eltwise_injector_; + delete bwd_data_copy_kernel_; + } + + static bool post_ops_ok(const jit_conv_conf_t &jcp, primitive_attr_t &attr); + + static status_t init_conf(jit_conv_conf_t &jcp, + const convolution_desc_t &cd, memory_desc_t &diff_src_pd, + memory_desc_t &weights_pd, memory_desc_t &diff_dst_pd, + memory_desc_t *bias_pd, primitive_attr_t &attr, int nthreads); + static void init_scratchpad(memory_tracking::registrar_t &scratchpad, + const jit_conv_conf_t &jcp, const primitive_attr_t &attr); + + void tile_configure(char *tcfg_buff); + + jit_conv_conf_t jcp; + const primitive_attr_t &attr_; + + const jit_avx512_core_amx_bwd_data_copy_kernel_t & + bwd_data_copy_kernel() const { + return *bwd_data_copy_kernel_; + } + +private: + jit_uni_eltwise_injector_f32 *eltwise_injector_; + jit_avx512_core_amx_bwd_data_copy_kernel_t *bwd_data_copy_kernel_; + + int prv_width_ = 0; + int row_count_ = 0; + bool is_store_done_ = false; + bool is_buffer_empty_ = true; + + bool is_store_done_save_ = false; + int prv_width_save_ = 0; + + /* data regs */ + const Xbyak::Reg64 reg_inp_ptr = r15; + const Xbyak::Reg64 reg_wei_ptr = r14; + const Xbyak::Reg64 reg_out_ptr = r13; + const Xbyak::Reg64 reg_wsp_ptr = r12; + + const Xbyak::Reg64 reg_bias = r11; + const Xbyak::Reg64 reg_ptr_scales = r10; + const Xbyak::Reg64 reg_ptr_dst_scales = r10; + const Xbyak::Reg64 reg_ptr_sum_scale = r9; + const Xbyak::Reg64 reg_ptr_sum_zp = abi_not_param1; + const Xbyak::Reg64 reg_aux_saturation = reg_ptr_sum_scale; + + const Xbyak::Reg64 reg_aux_inp_ptr = r8; + const Xbyak::Reg64 reg_inp_stride = rbx; + const Xbyak::Reg64 reg_wei_stride = rdx; + + // rbp - reserved for EVEX compression + const Xbyak::Reg64 reg_last_h = abi_not_param1; + const Xbyak::Reg64 reg_kd = rsi; + + // temporary, used in generate() function only + const Xbyak::Reg64 reg_ic_blocks = rax; + const Xbyak::Reg64 reg_tmp = reg_aux_inp_ptr; + + const Xbyak::Opmask ktail_mask = k2; + + const Xbyak::Zmm zmm_bias = zmm31; + const Xbyak::Zmm zmm_saturation = zmm_bias; + const Xbyak::Zmm zmm_zero = zmm30; + const Xbyak::Zmm zmm_prev_dst = zmm29; + const Xbyak::Zmm zmm_sum_zp = zmm28; + /* dst scale */ + const Xbyak::Zmm &zmm_dst_scale = zmm27; + + // AUX: Steps, shifts and offsets + size_t get_inp_ocb_step() const; + size_t get_inp_offset(int ihb, int kh, int kw) const; + size_t get_inp_shift() const; + size_t get_inp_d_step() const; + size_t get_out_icb_offset(int ihb, int icb) const; + size_t get_out_row_offset(int ihb, int icb, int j) const; + size_t get_out_shift(int width) const; + size_t get_wei_kh_step() const; + size_t get_wei_ocb_step() const; + size_t get_wei_offset(int icb, int kh, int kw) const; + size_t get_wei_d_step() const; + size_t get_wsp_icb_offset(int ihb, int icb) const; + size_t get_wsp_row_offset(int ihb, int icb, int j) const; + size_t get_wsp_shift() const; + + int get_out_tensor(int h, int i) const; + int get_inp_tensor(int h) const; + int get_wei_tensor(int i) const; + + inline bool gaps_in_store() { + const int gen_kd = (jcp.kd - 1) * (jcp.dilate_d + 1) + 1; + return gen_kd < jcp.stride_d || jcp.dilate_d > 0; + } + + void prepare_output(); + void init_runtime_counters(bool start_with_last_tile_block); + + bool maybe_eltwise(int position); + void cvt2ps(data_type_t type_in, const Xbyak::Zmm &ymm_in, + const Xbyak::Operand &op, bool mask_flag = false); + Xbyak::Ymm ymm_mask( + const Xbyak::Ymm &zmm_in, bool mask_flag, bool store = false); + Xbyak::Zmm zmm_mask( + const Xbyak::Zmm &zmm_in, bool mask_flag, bool store = false); + + void store_output_vector_bf16( + const Xbyak::Zmm &zmm_out, int icb, int ihb, int iw); + void store_output_vector_int8( + const Xbyak::Zmm &zmm_out, int icb, int ihb, int iw); + void store_output_vector( + const Xbyak::Zmm &zmm_out, int icb, int ih, int iw); + void store_output(int width, bool do_store); + void skipped_interleave_store(); + void interleave_store(int width); + void compute_ocb_loop(int width, bool do_interleave_store); + void compute_kd_loop(int width, bool do_store, bool handle_skipped_stores); + void compute_iw_loop(); + + void generate() override; +}; + +struct jit_avx512_core_amx_bwd_weights_kernel_t : public jit_generator { + + jit_avx512_core_amx_bwd_weights_kernel_t(const jit_conv_conf_t &ajcp) + : jit_generator( + jit_name(), nullptr, MAX_CODE_SIZE, true, avx512_core_amx) + , jcp(ajcp) {} + + ~jit_avx512_core_amx_bwd_weights_kernel_t() {} + + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_amx_bwd_weights_kernel_t) + + static status_t init_conf(jit_conv_conf_t &jcp, + const convolution_desc_t &cd, memory_desc_t &src_md, + memory_desc_t &diff_weights_md, memory_desc_t &diff_bias_md, + memory_desc_t &diff_dst_md, int nthreads); + static status_t init_scratchpad(memory_tracking::registrar_t &scratchpad, + const jit_conv_conf_t &jcp, memory_desc_t &src_md, + memory_desc_t &diff_weights_md, memory_desc_t &diff_dst_md); + + void tile_configure(char *tcfg_buff); + + const jit_conv_conf_t &jcp; + +private: + int get_wei_tensor(int ocb, int icb) const; + int get_src_tensor(int icb) const; + int get_ddst_tensor(int ocb) const; + + using reg64_t = const Xbyak::Reg64; + static const int max_ur_w; + + reg64_t param = abi_param1; + reg64_t reg_src = rax; + reg64_t reg_kernel = rdx; + reg64_t reg_ddst = rsi; + reg64_t b_ic = abi_not_param1; + reg64_t kj = r8; + reg64_t reg_kh = r9; + reg64_t reg_oj = r15; + reg64_t reg_tmp = r14; + reg64_t reg_ih_shift = reg_tmp; + reg64_t reg_long_offt = r14; + reg64_t reg_icb = rbx; + + reg64_t ki = r11; + reg64_t reg_oj_setup = r11; + reg64_t reg_kd_count = r12; + reg64_t reg_oi = r12; + reg64_t reg_d_index = r13; + reg64_t reg_src_d = r15; + reg64_t reg_ddst_d = rbx; + reg64_t aux_reg_src = r12; + reg64_t aux_reg_kernel = r13; + + reg64_t reg_b_stride = reg_icb; + reg64_t reg_a_stride = r10; + + Xbyak::Zmm vreg_bias_acc = Xbyak::Zmm(0); + Xbyak::Zmm vreg_bias_unit = Xbyak::Zmm(1); + Xbyak::Zmm vreg_bias_ddst = Xbyak::Zmm(2); + + enum { + full_spat_opt_working_set_size = 48 * 1024, + full_spat_max_working_set_size = 128 * 1024, + }; + + inline void maybe_zero_kernel(int nb_ic_blocking, int nb_oc_blocking); + inline void od_step_comeback_pointers(); + inline void oh_step_comeback_pointers(); + inline void compute_ic_loop( + int ic_block, int nb_ic_blocking, int nb_oc_blocking); + inline void compute_full_spat_loop(int nb_ic_blocking, int nb_oc_blocking); + inline void compute_oh_step_common(int nb_ic_blocking, int nb_oc_blocking); + inline void compute_loop(int nb_ic_blocking, int nb_oc_blocking); + inline void compute_oh_loop_common( + int nb_ic_blocking, int nb_oc_blocking, bool partial = false); + inline void compute_od_loop_common( + int nb_ic_blocking, int nb_oc_blocking, bool partial = false); + void compute_diff_bias_init(int ocb = 0); + void compute_diff_bias_row(bool is_partial, int ocb); + void maybe_compute_diff_bias(int nb_oc_blocking); + void may_be_set_oc_tail_mask(); + void may_be_reset_oc_tail_mask(); + + void generate() override; + + static void balance(const jit_conv_conf_t &j, int &nthr, int &nthr_mb, + int &nthr_g, int &nthr_oc_b, int &nthr_ic_b); + + inline dim_t filter_w_to_src(int kw, int ow = 0, int pad_l = 0) { + return kw * (jcp.dilate_w + 1) + ow - pad_l; + } + inline dim_t filter_h_to_src(int kh) { return kh * (jcp.dilate_h + 1); } + inline dim_t filter_d_to_src(int kd) { + return kd * (jcp.dilate_d + 1) * jcp.ih; + } + + inline dim_t get_src_offset(dim_t ic_idx, dim_t w_idx, dim_t hd_idx = 0) { + return jcp.typesize_in + * (hd_idx * jcp.tr_iw * jcp.ic_block + jcp.tr_iw * ic_idx + + w_idx); + } + + inline dim_t get_ddst_offset(dim_t w_idx, dim_t hd_idx = 0) { + int ow_per_oc = 2; + dim_t w_off = w_idx / ow_per_oc * ow_per_oc * jcp.oc_block + + w_idx % ow_per_oc; + return jcp.typesize_in * (w_off + jcp.tr_ow * jcp.oc_block * hd_idx); + } + + inline dim_t get_kernel_offset(int ic_idx, dim_t ksp_idx) { + return jcp.typesize_out * jcp.oc_block + * (ksp_idx * jcp.ic_block + ic_idx); + } + inline dim_t get_full_kernel_offset(int ocb, int icb, int kh, int kw) { + return jcp.typesize_out + * (ocb * jcp.nb_ic * jcp.kd * jcp.kh * jcp.kw * jcp.ic_block + * jcp.oc_block + + icb * jcp.kd * jcp.kh * jcp.kw * jcp.ic_block + * jcp.oc_block + + kh * jcp.kw * jcp.ic_block * jcp.oc_block + + kw * jcp.ic_block * jcp.oc_block); + }; + + inline void setup_stack_space(); + int ic_block_step_stack_size = 0; + int stack_space_needed = 0; + int kd_count_offset = 0; + int src_d_offset = 0; + int ddst_d_offset = 0; + int d_index_offset = 0; + int ih_dilate_offset = 0; + int src_save_offset = 0; + int ddst_save_offset = 0; +}; + +struct jit_avx512_core_amx_bwd_bias_kernel_t : public jit_generator { + + jit_avx512_core_amx_bwd_bias_kernel_t(const jit_conv_conf_t &ajcp) + : jit_generator( + jit_name(), nullptr, MAX_CODE_SIZE, true, avx512_core_amx) + , jcp(ajcp) {} + + ~jit_avx512_core_amx_bwd_bias_kernel_t() {} + + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_amx_bwd_bias_kernel_t) + + const jit_conv_conf_t &jcp; + +private: + using reg64_t = const Xbyak::Reg64; + + reg64_t param = abi_param1; + reg64_t reg_ddst = rsi; + reg64_t reg_oj = r15; + reg64_t reg_tmp = r14; + reg64_t reg_bias = r13; + reg64_t reg_initial = r12; + reg64_t reg_nrows = r11; + + Xbyak::Zmm vreg_bias_acc = Xbyak::Zmm(0); + Xbyak::Zmm vreg_bias_unit = Xbyak::Zmm(1); + Xbyak::Zmm vreg_bias_ddst = Xbyak::Zmm(2); + Xbyak::Ymm yreg_bias_acc0 = Xbyak::Ymm(0); + Xbyak::Ymm yreg_bias_acc1 = Xbyak::Ymm(3); + Xbyak::Ymm yreg_bias_ddst0 = Xbyak::Ymm(2); + Xbyak::Ymm yreg_bias_ddst1 = Xbyak::Ymm(4); + + void compute_diff_bias_row(int ocb); + void compute_diff_bias(int nb_oc_blocking); + + void generate() override; + + inline dim_t get_ddst_offset(dim_t w_idx, dim_t hd_idx = 0) { + int ow_per_oc = 2; + dim_t w_off = w_idx / ow_per_oc * ow_per_oc * jcp.oc_block + + w_idx % ow_per_oc; + return jcp.typesize_in * (w_off + jcp.tr_ow * jcp.oc_block * hd_idx); + } +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_amx_conv_utils.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_amx_conv_utils.hpp new file mode 100644 index 0000000000000000000000000000000000000000..9578db8ef7b8ab524e52bfb4f7a9064a29d1ece4 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_amx_conv_utils.hpp @@ -0,0 +1,312 @@ +/******************************************************************************* +* Copyright 2021-2022 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include "common/dnnl_thread.hpp" +#include "common/utils.hpp" + +#include "cpu/x64/jit_avx512_core_amx_convolution.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { +namespace amx_utils { + +using namespace dnnl::impl::memory_tracking::names; +using namespace dnnl::impl::utils; + +#define wht_blk_off(d, g, ...) \ + (with_groups ? (d).blk_off((g), __VA_ARGS__) : (d).blk_off(__VA_ARGS__)) + +struct spatial_features_3d { + + spatial_features_3d(const jit_conv_conf_t &jcp) + : input_size_(jcp.id) + , filter_size_(jcp.kd) + , dilate_(jcp.dilate_d + 1) + , stride_(jcp.stride_d) + , init_pad_(jcp.f_pad) + , end_pad_(jcp.back_pad) + , is_fast_path_(dilate_ == 1 && stride_ == 1) + , compute_extended_features_(!(is_fast_path_ || dilate_ != 1)) + , filter_(0) + , lower_offset_(0) + , output_offset_(0) + , init_overflow_(0) + , end_overflow_(0) {} + + inline int get_init_overflow(const int in) { + if (is_fast_path_) + return nstl::max(0, filter_size_ - 1 - in - init_pad_); + if (dilate_ != 1) + return div_up( + nstl::max(0, (filter_size_ - 1) * dilate_ - in - init_pad_), + dilate_); + return nstl::max(0, (filter_size_ - 1 - in - init_pad_) / stride_); + } + + inline int get_end_overflow(const int in) { + if (is_fast_path_) + return nstl::max(0, filter_size_ - input_size_ + in - end_pad_); + if (dilate_ != 1) + return div_up(nstl::max(0, + (filter_size_ - 1) * dilate_ + 1 - input_size_ + + in - end_pad_), + dilate_); + return nstl::max( + 0, (filter_size_ - input_size_ + in - end_pad_) / stride_); + } + + void update_params(const int in) { + + init_overflow_ = get_init_overflow(in); + end_overflow_ = get_end_overflow(in); + + // overflow_kd_hi + const int overflow_filter_hi_ = compute_extended_features_ + ? filter_size_ - 1 + - nstl::modulo(input_size_ - 1 + end_pad_ - in, stride_) + : 0; + // overflow_kd_lo + const int overflow_filter_lo_ + = compute_extended_features_ ? (in + init_pad_) % stride_ : 0; + + filter_ = compute_extended_features_ + ? (overflow_filter_hi_ - overflow_filter_lo_) / stride_ + 1 + : filter_size_; + + lower_offset_ = compute_extended_features_ + ? overflow_filter_lo_ + end_overflow_ * stride_ + : end_overflow_; + + output_offset_ = compute_extended_features_ + ? (in + init_pad_ - lower_offset_) / stride_ + : in + init_pad_ - end_overflow_ * dilate_; + } + + inline int get_filter_padding() { + return filter_ - init_overflow_ - end_overflow_; + } + + inline int get_lower_offset() { return lower_offset_; } + + inline int get_output_offset() { return output_offset_; } + +private: + const int input_size_; + const int filter_size_; + const int dilate_; + const int stride_; + const int init_pad_; // f_pad + const int end_pad_; // back_pad + const bool is_fast_path_; // 'dilate_ == 1 && stride_ == 1' + const bool + compute_extended_features_; // eq. '(!is_fast_path_) && dilate_ == 1' + + int filter_; + int lower_offset_; // d_lo + int output_offset_; // d_oj + + int init_overflow_; // d_t_overflow + int end_overflow_; // d_b_overflow +}; + +inline void execute_backward_convolution_body(const exec_ctx_t &ctx, + const jit_conv_conf_t &jcp, + const std::unique_ptr &kernel, + const char *diff_dst, const char *weights, const char *bias, + const float *oscales, const float *dst_scales, char *diff_src, + const memory_desc_wrapper &diff_dst_d, + const memory_desc_wrapper &weights_d, const memory_desc_wrapper &bias_d, + const memory_desc_wrapper &diff_src_d) { + assert(jcp.nb_ic % jcp.nb_ic_blocking == 0); + + const bool is_deconv = jcp.prop_kind != prop_kind::backward_data; + const bool with_groups = weights_d.ndims() == diff_src_d.ndims() + 1; + + const size_t diff_dst_dt_size = jcp.typesize_in; + const size_t wei_dt_size = jcp.typesize_in; + const size_t bia_dt_size = jcp.typesize_bia; + const size_t diff_src_dt_size = jcp.typesize_out; + + const dim_t wei_g_shift = wht_blk_off(weights_d, 1, 0); + const dim_t wei_ic_shift = is_deconv + ? wht_blk_off(weights_d, 0, jcp.nb_ic_blocking) + : wht_blk_off(weights_d, 0, 0, jcp.nb_ic_blocking); + const size_t wht_d_stride = wht_blk_off(weights_d, 0, 0, 0, 1); + + auto inp_p_buffer = ctx.get_scratchpad_grantor().template get( + key_conv_amx_inp_buffer); + auto wsp = ctx.get_scratchpad_grantor().template get( + key_conv_amx_wsp_buffer); + auto tcfg = ctx.get_scratchpad_grantor().template get( + key_conv_amx_tilecfg); + + const int ic_chunks = jcp.nb_ic / jcp.nb_ic_blocking; + const int ih_chunks = utils::div_up(jcp.ih, jcp.ih_blk_size); + const int work_amount + = jcp.mb * jcp.ngroups * jcp.id * ih_chunks * jcp.nb_iw * ic_chunks; + + // Initialize the tile configuration in memory, so that each thread can + // load this configuration from memory via `amx_tile_configure(tcfg)`. + if (tcfg) kernel->tile_configure(tcfg); + const bool is_1d = jcp.ndims == 3; + const bool is_3d = jcp.ndims == 5; + + parallel(jcp.nthr, [&](const int ithr, const int nthr) { + int start {0}, end {0}; + balance211(work_amount, nthr, ithr, start, end); + + auto p = jit_conv_call_s(); + amx_tile_configure(tcfg); + spatial_features_3d sfd(jcp); + + int mb {0}, g {0}, id_s {0}, ihc {0}, iwb {0}, icc {0}; + nd_iterator_init(start, mb, jcp.mb, g, jcp.ngroups, id_s, jcp.id, ihc, + ih_chunks, iwb, jcp.nb_iw, icc, ic_chunks); + int last_copied_mb = -1; + int last_copied_id = -1; + int last_copied_ihc = -1; + int last_copied_iwb = -1; + int last_copied_g = -1; + while (start < end) { + char *inp_buffer = inp_p_buffer + + ithr * jcp.inp_buffer_size * diff_dst_dt_size; + + assert(IMPLICATION( + jcp.ngroups > 1, jcp.ic == jcp.ic_without_padding)); + int ic = g * jcp.ic + icc * jcp.nb_ic_blocking * jcp.ic_block; + int icb = jcp.is_nspc ? ic : ic / jcp.ic_block; + assert(IMPLICATION( + jcp.ngroups > 1, jcp.oc == jcp.oc_without_padding)); + const int ocb = g * (jcp.is_nspc ? jcp.oc : jcp.nb_oc); + auto bias_w = bias ? bias + (bias_d.blk_off(ic) * bia_dt_size) + : nullptr; + + const int ih_b = ihc * jcp.ih_blk_size; + const int ih_e = nstl::min(jcp.ih, ih_b + jcp.ih_blk_size); + const int iw = iwb * jcp.iw_block; + bool is_inp_buffer_relevant = true && last_copied_mb == mb + && last_copied_id == id_s && last_copied_ihc == ihc + && last_copied_iwb == iwb && last_copied_g == g; + + sfd.update_params(id_s); + p.kd_padding = sfd.get_filter_padding(); + const int d_lo = sfd.get_lower_offset(); + const int d_oj = sfd.get_output_offset(); + + int ih_step = jcp.nb_ih_blocking; + for (int ih = ih_b; ih < ih_e; ih += ih_step) { + if (!is_inp_buffer_relevant) { + const int gen_kh = (jcp.kh - 1) * (jcp.dilate_h + 1) + 1; + const int gen_kw = (jcp.kw - 1) * (jcp.dilate_w + 1) + 1; + // dox: x-index dilated by strides (dox = ox * stride_x) + const int doh = ih + jcp.t_pad - (gen_kh - 1); + const int dow = iw + jcp.l_pad - (gen_kw - 1); + const int doh_b = ih_b + jcp.t_pad - (gen_kh - 1); + const int doh_l = (jcp.oh - 1) * jcp.stride_h; // last oh + const int dow_l = (jcp.ow - 1) * jcp.stride_w; // last ow + + // dox_{s,f}: start and finish indices for copy kernel + const int doh_s = doh + (ih == ih_b ? 0 : gen_kh - 1); + const int doh_f = doh + (ih_step - 1) + (gen_kh - 1); + const int delta_h = doh_f - doh_s + 1; + const int doh_t_overflow = 0 < doh_s && doh_s < doh_l + ? nstl::additive_inverse_modulo(doh_s, jcp.stride_h) + : nstl::max(0, -doh_s); + const int doh_b_overflow = 0 < doh_f && doh_f < doh_l + ? nstl::modulo(doh_f, jcp.stride_h) + : nstl::max(0, nstl::min(delta_h, doh_f - doh_l)); + int dow_s = dow; + int dow_f = dow + jcp.owp - 1; + const int delta_w = dow_f - dow_s + 1; + const int dow_l_overflow = 0 < dow_s && dow_s < dow_l + ? nstl::additive_inverse_modulo(dow_s, jcp.stride_w) + : nstl::max(0, -dow_s); + const int dow_r_overflow = 0 < dow_f && dow_f < dow_l + ? nstl::modulo(dow_f, jcp.stride_w) + : nstl::max(0, nstl::min(delta_w, dow_f - dow_l)); + const int oh_s + = nstl::max(0, utils::div_up(doh_s, jcp.stride_h)); + const int ow_s + = nstl::max(0, utils::div_up(dow_s, jcp.stride_w)); + // how many real data rows to copy (including padding) + p.t_overflow = nstl::min(delta_h, doh_t_overflow); + p.b_overflow = nstl::min( + delta_h - p.t_overflow, doh_b_overflow); + p.kh_padding = nstl::max( + 0, delta_h - p.t_overflow - p.b_overflow); + p.l_overflow = nstl::min(delta_w, dow_l_overflow); + p.kw_padding = nstl::max( + 0, delta_w - dow_l_overflow - dow_r_overflow); + p.r_overflow = nstl::min( + delta_w - dow_l_overflow, dow_r_overflow); + size_t inp_offset = is_1d + ? diff_dst_d.blk_off(mb, ocb, ow_s) + : is_3d + ? diff_dst_d.blk_off(mb, ocb, d_oj, oh_s, ow_s) + : diff_dst_d.blk_off(mb, ocb, oh_s, ow_s); + p.src = diff_dst + diff_dst_dt_size * inp_offset; + p.dst = inp_buffer + + (size_t)(doh_s - doh_b) * jcp.owp + * jcp.oc_block_int * diff_dst_dt_size; + + kernel->bwd_data_copy_kernel()(&p); + } + + size_t diff_src_offset = is_1d ? diff_src_d.blk_off(mb, icb, iw) + : is_3d ? diff_src_d.blk_off(mb, icb, id_s, ih, iw) + : diff_src_d.blk_off(mb, icb, ih, iw); + p.dst = inp_buffer + + (size_t)(ih - ih_b) * jcp.owp * jcp.oc_block_int + * diff_dst_dt_size; + p.src = diff_src + diff_src_dt_size * diff_src_offset; + p.filt = weights + + wei_dt_size + * (g * wei_g_shift + icc * wei_ic_shift + + d_lo * wht_d_stride); + p.bias = bias_w; + p.scales = &oscales[jcp.is_ic_scale * ic]; + p.dst_scale = &dst_scales[0]; + p.acc_s32 = wsp + ithr * jcp.wsp_buffer_size; + p.last_h = (ih + ih_step <= ih_e); + p.iwb = iwb; + p.ic_blocks = icc * jcp.nb_ic_blocking; + + (*kernel)(&p); + } + last_copied_mb = mb; + last_copied_id = id_s; + last_copied_ihc = ihc; + last_copied_iwb = iwb; + last_copied_g = g; + ++start; + nd_iterator_step(mb, jcp.mb, g, jcp.ngroups, id_s, jcp.id, ihc, + ih_chunks, iwb, jcp.nb_iw, icc, ic_chunks); + } + amx_tile_release(); + }); +} + +#undef wht_blk_off + +} // namespace amx_utils +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +// vim: et ts=4 sw=4 cindent cino^=l0,\:0,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_amx_convolution.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_amx_convolution.hpp new file mode 100644 index 0000000000000000000000000000000000000000..63b93419e2a17300d9a511c94f8eb06e32376881 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_amx_convolution.hpp @@ -0,0 +1,320 @@ +/******************************************************************************* +* Copyright 2020-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_AVX512_CORE_AMX_CONVOLUTION_HPP +#define CPU_X64_JIT_AVX512_CORE_AMX_CONVOLUTION_HPP + +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/memory_tracking.hpp" +#include "common/primitive.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_convolution_pd.hpp" + +#include "cpu/x64/amx_tile_configure.hpp" +#include "cpu/x64/cpu_barrier.hpp" +#include "cpu/x64/cpu_reducer.hpp" +#include "cpu/x64/jit_avx512_core_amx_conv_kernel.hpp" +#include "cpu/x64/jit_transpose_utils.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +struct jit_avx512_core_amx_convolution_fwd_t : public primitive_t { + struct pd_t : public cpu_convolution_fwd_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const typename pd_t::base_class *hint_fwd_pd) + : cpu_convolution_fwd_pd_t(adesc, attr, hint_fwd_pd), jcp_() {} + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit:", jcp_.isa, ""), + jit_avx512_core_amx_convolution_fwd_t); + + status_t init(engine_t *engine) { + using namespace data_type; + using smask_t = primitive_attr_t::skip_mask_t; + bool is_bf16_convolution + = (src_md(0)->data_type == bf16 + && weights_md(0)->data_type == bf16 + && utils::one_of(dst_md(0)->data_type, f32, bf16)) + && IMPLICATION(with_bias(), + utils::one_of(weights_md(1)->data_type, f32, bf16)) + && attr()->has_default_values(smask_t::post_ops); + bool is_int8_convolution + = utils::one_of(src_md(0)->data_type, s8, u8) + && weights_md(0)->data_type == s8 + && utils::one_of( + dst_md(0)->data_type, s8, u8, s32, f32, bf16) + && IMPLICATION(with_bias(), + utils::one_of( + weights_md(1)->data_type, f32, s32, s8, u8)) + && attr()->has_default_values(smask_t::scales_runtime + | smask_t::post_ops + | smask_t::zero_points_runtime + | smask_t::sum_dt, + dst_md(0)->data_type); + + bool ok = is_fwd() + && set_default_alg_kind(alg_kind::convolution_direct) + && (is_bf16_convolution || is_int8_convolution) + && !has_zero_dim_memory() && attr_scales_ok() + && attr()->post_ops_.check_sum_consistency( + dst_md(0)->data_type, + /* is_int8 */ is_int8_convolution) + && zero_points_ok(); + if (!ok) return status::unimplemented; + + CHECK(jit_avx512_core_amx_fwd_kernel_t::init_conf(jcp_, *desc(), + src_md_, weights_md_, dst_md_, bias_md_, attr_, + dnnl_get_max_threads())); + + auto scratchpad = scratchpad_registry().registrar(); + CHECK(jit_avx512_core_amx_fwd_kernel_t::init_scratchpad( + scratchpad, jcp_, *attr())); + + return status::success; + } + + jit_conv_conf_t jcp_; + + protected: + bool zero_points_ok() const { + // Only common zero points are supported -> mask should only be 0 + int mask_src = 0, mask_dst = 0; + attr()->zero_points_.get(DNNL_ARG_SRC, &mask_src); + attr()->zero_points_.get(DNNL_ARG_DST, &mask_dst); + return attr()->zero_points_.has_default_values(DNNL_ARG_WEIGHTS) + && mask_src == 0 && mask_dst == 0; + } + }; + + jit_avx512_core_amx_convolution_fwd_t(const pd_t *apd) : primitive_t(apd) {} + + status_t init(engine_t *engine) override { + CHECK(safe_ptr_assign(kernel_, + new jit_avx512_core_amx_fwd_kernel_t( + pd()->jcp_, *pd()->attr(), *pd()->dst_md(0)))); + return kernel_->create_kernel(); + } + + status_t execute(const exec_ctx_t &ctx) const override { + const auto &_pd = pd(); + if (_pd->jcp_.is_depthwise) + return status::unimplemented; + else if (_pd->jcp_.is_relo) + return execute_forward_reduced_lowering(ctx); + return execute_forward(ctx); + } + +private: + status_t execute_forward_reduced_lowering(const exec_ctx_t &ctx) const; + status_t execute_forward(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + void prepare_padded_bias(const char *&bias, + const memory_tracking::grantor_t &scratchpad) const; + + std::unique_ptr kernel_; +}; + +template +struct jit_avx512_core_amx_convolution_bwd_data_t : public primitive_t { + struct pd_t : public cpu_convolution_bwd_data_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const convolution_fwd_pd_t *hint_fwd_pd) + : cpu_convolution_bwd_data_pd_t(adesc, attr, hint_fwd_pd), jcp_() {} + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit:", jcp_.isa, ""), + jit_avx512_core_amx_convolution_bwd_data_t); + + status_t init(engine_t *engine) { + bool is_bf16_convolution = true + && (diff_dst_md_.data_type == data_type::bf16 + && weights_md_.data_type == data_type::bf16 + && utils::one_of(diff_src_md_.data_type, + data_type::f32, data_type::bf16)) + && attr()->has_default_values(); + + bool ok = true && desc()->prop_kind == prop_kind::backward_data + && set_default_alg_kind(alg_kind::convolution_direct) + && is_bf16_convolution && !has_zero_dim_memory(); + if (!ok) return status::unimplemented; + + status_t status = jit_avx512_core_amx_bwd_data_kernel_t::init_conf( + jcp_, *desc(), diff_src_md_, weights_md_, diff_dst_md_, + nullptr /* no bias */, attr_, dnnl_get_max_threads()); + if (status != status::success) return status; + + auto scratchpad = scratchpad_registry().registrar(); + jit_avx512_core_amx_bwd_data_kernel_t::init_scratchpad( + scratchpad, jcp_, *attr()); + + return status; + } + + jit_conv_conf_t jcp_; + }; + + jit_avx512_core_amx_convolution_bwd_data_t(const pd_t *apd) + : primitive_t(apd) {} + + typedef typename prec_traits::type diff_src_data_t; + typedef typename prec_traits::type wei_data_t; + typedef typename prec_traits::type diff_dst_data_t; + + status_t init(engine_t *engine) override { + CHECK(safe_ptr_assign(kernel_, + new jit_avx512_core_amx_bwd_data_kernel_t( + pd()->jcp_, *pd()->attr()))); + return kernel_->create_kernel(); + } + + status_t execute(const exec_ctx_t &ctx) const override { + const auto &_pd = pd(); + if (_pd->jcp_.is_depthwise) { + assert(!"_pd->jcp_.is_depthwise not implemented"); + return status::unimplemented; + } else + return execute_backward(ctx); + } + +private: + status_t execute_backward(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr kernel_; +}; + +struct jit_avx512_core_amx_convolution_bwd_weights_t : public primitive_t { + struct pd_t : public cpu_convolution_bwd_weights_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const convolution_fwd_pd_t *hint_fwd_pd) + : cpu_convolution_bwd_weights_pd_t(adesc, attr, hint_fwd_pd) + , jcp_() {} + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit:", jcp_.isa, ""), + jit_avx512_core_amx_convolution_bwd_weights_t); + + status_t init(engine_t *engine) { + bool ok = true && is_bwd_w() + && set_default_alg_kind(alg_kind::convolution_direct) + && (expect_data_types(data_type::bf16, data_type::bf16, + data_type::undef, data_type::bf16, + data_type::undef) + || expect_data_types(data_type::bf16, + data_type::f32, data_type::undef, + data_type::bf16, data_type::undef)) + && IMPLICATION(with_bias(), + utils::one_of(diff_bias_md_.data_type, + data_type::f32, data_type::bf16)) + && attr()->has_default_values() && !has_zero_dim_memory(); + if (!ok) return status::unimplemented; + + status_t status + = jit_avx512_core_amx_bwd_weights_kernel_t::init_conf(jcp_, + *desc(), src_md_, diff_weights_md_, diff_bias_md_, + diff_dst_md_, dnnl_get_max_threads()); + if (status != status::success) return status; + + auto scratchpad = scratchpad_registry().registrar(); + status = jit_avx512_core_amx_bwd_weights_kernel_t::init_scratchpad( + scratchpad, jcp_, src_md_, diff_weights_md_, diff_dst_md_); + if (status != status::success) return status; + + return status; + } + + jit_conv_conf_t jcp_; + }; + + jit_avx512_core_amx_convolution_bwd_weights_t(const pd_t *apd) + : primitive_t(apd) {} + + typedef typename prec_traits::type src_data_t; + typedef typename prec_traits::type diff_dst_data_t; + + status_t init(engine_t *engine) override; + + status_t execute(const exec_ctx_t &ctx) const override { + execute_backward_weights(ctx); + return status::success; + } + +private: + struct thread_info_t; + + void execute_backward_weights(const exec_ctx_t &ctx) const; + void prepare_scratchpad_data(const exec_ctx_t &ctx) const; + void compute_diff_weights_2d(const thread_info_t *) const; + void compute_diff_weights_3d(const thread_info_t *) const; + void compute_diff_weights(const thread_info_t *) const; + void reduce_and_convert_diff_weights_and_bias(const thread_info_t *) const; + void store_in_vnni_format(const thread_info_t *) const; + + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + size_t tr_src_buf_number(const thread_info_t *ti, int g, int ic) const; + size_t tr_diff_dst_buf_number(const thread_info_t *ti, int g, int oc) const; + void trans_src_nxc(src_data_t *tr_src, const src_data_t *src_base, + int spatial_start, dim_t spatial_start_offset, int icb_start, + dim_t chb_stride, int my_work) const; + void trans_dst_nxc(diff_dst_data_t *tr_diff_dst, + const diff_dst_data_t *diff_dst_base, int spatial_start, + dim_t spatial_start_offset, int ocb_start, dim_t chb_stride, + int my_work) const; + + int nthr_ = 0, nthr_mb_ = 0, nthr_g_ = 0, nthr_oc_b_ = 0, nthr_ic_b_ = 0; + + std::unique_ptr kernel_; + + std::unique_ptr> acc_ker_; + + std::unique_ptr diff_wei_trans_kernel_; + std::unique_ptr trans_kernel_; + std::unique_ptr trans_dst_kernel_; + + inline dim_t wei_offset_int(int g, int oc_b, int ic_b, int kX) const { + const auto &jcp = kernel_->jcp; + const dim_t const_extra_offset = jcp.kw * jcp.ic_block * jcp.oc_block; + dim_t extra_offset = (jcp.ndims == 5) ? kX * jcp.kh * const_extra_offset + : kX * const_extra_offset; + return (dim_t)((g * jcp.nb_oc + oc_b) * jcp.nb_ic + ic_b) * jcp.kd + * jcp.kh * jcp.kw * jcp.ic_block * jcp.oc_block + + extra_offset; + } + inline dim_t wei_offset_ext(int g, int oc_b, int ic_b, int kX) const { + const auto &jcp = kernel_->jcp; + const int nb_ic = utils::div_up(jcp.ic, 2 * jcp.ic_block); + const dim_t const_extra_offset + = jcp.kw * jcp.ic_block * jcp.oc_block * 2; + dim_t extra_offset = (jcp.ndims == 5) ? kX * jcp.kh * const_extra_offset + : kX * const_extra_offset; + return (dim_t)((g * jcp.nb_oc + oc_b) * nb_ic + ic_b) * jcp.kd * jcp.kh + * jcp.kw * jcp.ic_block * jcp.oc_block * 2 + + extra_offset; + } +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino^=l0,\:0,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_amx_deconvolution.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_amx_deconvolution.hpp new file mode 100644 index 0000000000000000000000000000000000000000..949ca9e1f2b1df1ba68f4e468e42474b1f8cdbb1 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_amx_deconvolution.hpp @@ -0,0 +1,123 @@ +/******************************************************************************* +* Copyright 2021-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_AVX512_CORE_AMX_DECONVOLUTION_HPP +#define CPU_X64_JIT_AVX512_CORE_AMX_DECONVOLUTION_HPP + +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/memory_tracking.hpp" +#include "common/primitive.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_deconvolution_pd.hpp" + +#include "cpu/x64/amx_tile_configure.hpp" +#include "cpu/x64/jit_avx512_core_amx_conv_kernel.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +struct jit_avx512_core_amx_deconvolution_fwd_t : public primitive_t { + struct pd_t : public cpu_deconvolution_fwd_pd_t { + pd_t(const deconvolution_desc_t *adesc, const primitive_attr_t *attr, + const typename pd_t::base_class *hint_fwd_pd) + : cpu_deconvolution_fwd_pd_t(adesc, attr, hint_fwd_pd), jcp_() {} + + DECLARE_COMMON_PD_T( + JIT_IMPL_NAME_HELPER("jit_deconvolution:", jcp_.isa, ""), + jit_avx512_core_amx_deconvolution_fwd_t); + + status_t init(engine_t *engine) { + using namespace data_type; + using smask_t = primitive_attr_t::skip_mask_t; + bool is_bf16_deconvolution = true + && utils::everyone_is(true, + utils::one_of(src_md_.data_type, bf16), + weights_md_.data_type == bf16, + utils::one_of(dst_md_.data_type, f32, bf16)) + && IMPLICATION(with_bias(), + utils::one_of(bias_md_.data_type, f32, bf16)) + && attr()->has_default_values(smask_t::post_ops); + bool is_int8_deconvolution = true + && utils::everyone_is(true, + utils::one_of(src_md_.data_type, s8, u8), + weights_md_.data_type == s8, + utils::one_of(dst_md_.data_type, f32, s32, s8, u8)) + && IMPLICATION(with_bias(), + utils::one_of(bias_md_.data_type, f32, s32, s8, u8)) + && attr()->has_default_values( + smask_t::scales_runtime | smask_t::post_ops) + && attr_scales_ok(); + + bool ok = is_fwd() + && (desc()->alg_kind & alg_kind::deconvolution_direct) + && (is_bf16_deconvolution || is_int8_deconvolution) + && !has_zero_dim_memory(); + if (!ok) return status::unimplemented; + + CHECK(jit_avx512_core_amx_bwd_data_kernel_t::init_conf(jcp_, + *desc(), dst_md_, weights_md_, src_md_, &bias_md_, attr_, + dnnl_get_max_threads())); + + auto scratchpad = scratchpad_registry().registrar(); + jit_avx512_core_amx_bwd_data_kernel_t::init_scratchpad( + scratchpad, jcp_, *attr()); + + return status::success; + } + + jit_conv_conf_t jcp_; + }; + + jit_avx512_core_amx_deconvolution_fwd_t(const pd_t *apd) + : primitive_t(apd) {} + + status_t init(engine_t *engine) override { + CHECK(safe_ptr_assign(kernel_, + new jit_avx512_core_amx_bwd_data_kernel_t( + pd()->jcp_, *pd()->attr()))); + return kernel_->create_kernel(); + } + + status_t execute(const exec_ctx_t &ctx) const override { + const auto &_pd = pd(); + if (_pd->jcp_.is_depthwise) { + assert(!"_pd->jcp_.is_depthwise not implemented"); + return status::unimplemented; + } else + return execute_forward(ctx); + } + +private: + status_t execute_forward(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + void prepare_padded_bias(const char *&bias, + const memory_tracking::grantor_t &scratchpad) const; + + std::unique_ptr kernel_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino^=l0,\:0,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_bf16_1x1_conv_kernel.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_bf16_1x1_conv_kernel.hpp new file mode 100644 index 0000000000000000000000000000000000000000..bf4059357ec711351ee45e124694860c813ffbc7 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_bf16_1x1_conv_kernel.hpp @@ -0,0 +1,207 @@ +/******************************************************************************* +* Copyright 2019-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_AVX512_CORE_BF16_1X1_CONV_KERNEL_HPP +#define CPU_X64_JIT_AVX512_CORE_BF16_1X1_CONV_KERNEL_HPP + +#include "common/c_types_map.hpp" + +#include "cpu/x64/injectors/jit_uni_postops_injector.hpp" +#include "cpu/x64/jit_avx512_core_bf16cvt.hpp" +#include "cpu/x64/jit_generator.hpp" +#include "cpu/x64/jit_primitive_conf.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +struct jit_avx512_core_bf16_1x1_conv_kernel : public jit_generator { + jit_avx512_core_bf16_1x1_conv_kernel(const jit_1x1_conv_conf_t &ajcp, + const primitive_attr_t &attr, const memory_desc_t &dst_md); + + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_bf16_1x1_conv_kernel) + + static status_t init_conf(jit_1x1_conv_conf_t &jcp, + const convolution_desc_t &cd, const memory_desc_wrapper &src_d, + const memory_desc_wrapper &weights_d, + const memory_desc_wrapper &dst_d, primitive_attr_t &attr, + int nthreads, bool reduce_src); + + static status_t init_scratchpad(memory_tracking::registrar_t &scratchpad, + const jit_1x1_conv_conf_t &jcp); + + const jit_1x1_conv_conf_t &jcp; + const primitive_attr_t &attr_; + +private: + constexpr static int isa_simd_width_ + = cpu_isa_traits::vlen / sizeof(float); + std::unique_ptr> + postops_injector_; + + using reg64_t = const Xbyak::Reg64; + using zmm_t = const Xbyak::Zmm; + using mask_t = const Xbyak::Opmask; + enum { + ker_code_size = 1024 * 1024, + }; + + reg64_t aux_reg_load_data = r15; + reg64_t aux_reg_bcast_data = r14; + reg64_t reg_output_stride = rsi; + reg64_t reg_bias_data = r12; + reg64_t reg_reduce_loop_work = r11; + reg64_t reg_load_data = r10; + reg64_t reg_output_data = r9; + reg64_t reg_bcast_data = r8; + reg64_t reg_reduce_pos_flag = rax; + reg64_t aux1_reg_bcast_data = rbx; + reg64_t aux_reg_output_data = abi_not_param1; + reg64_t reg_bcast_loop_iter = rdx; + reg64_t reg_load_loop_work = r13; + reg64_t reduce_loop_iter = abi_param1; + reg64_t reg_load_dim_tail_mask = aux_reg_load_data; + + reg64_t imm_addr64 = aux_reg_load_data; + reg64_t reg_bcast_loop_work = aux1_reg_bcast_data; + reg64_t reg_trans_tmp = reg_reduce_pos_flag; + reg64_t reg_store_buf + = reg_output_stride; // reg_output_stride used only in BWD/WU + reg64_t aux_reg_store_buf = reg_load_loop_work; + reg64_t reg_tmp = r12; + + mask_t vmask = k7; + // Used for axb tail handling. + // k_load_dim_mask is dynamically updated with k_load_mask_tail_mask + // whenever tail is detected + mask_t k_load_dim_mask = Xbyak::Opmask(2); + mask_t k_load_dim_mask_extended = Xbyak::Opmask(3); + mask_t k_load_dim_tail_mask = Xbyak::Opmask(4); + mask_t k_load_dim_tail_mask_extended = Xbyak::Opmask(5); + + Xbyak::Xmm xmm_relu_ns = Xbyak::Xmm(30); + Xbyak::Zmm zmm_relu_ns = Xbyak::Zmm(30); + Xbyak::Zmm zmm_zero = Xbyak::Zmm(31); + Xbyak::Zmm vreg_bcast = Xbyak::Zmm(31); + + Xbyak::Zmm bf16_emu_reserv_1 = Xbyak::Zmm(25); + Xbyak::Zmm bf16_emu_reserv_2 = Xbyak::Zmm(26); + Xbyak::Zmm bf16_emu_reserv_3 = Xbyak::Zmm(27); + reg64_t bf16_emu_reserv_4 = imm_addr64; + Xbyak::Zmm bf16_emu_reserv_5 = Xbyak::Zmm(28); + Xbyak::Zmm bf16_emu_reserv_6 = Xbyak::Zmm(29); + + Xbyak::Zmm zmm_tmp2 = Xbyak::Zmm(30); + + Xbyak::Opmask full_mask = Xbyak::Opmask(7); + Xbyak::Opmask half_mask = Xbyak::Opmask(6); + Xbyak::Opmask half_mask_hi = Xbyak::Opmask(5); + Xbyak::Label dst_prm_table; + + constexpr static int reg64_size_ = sizeof(int64_t); + constexpr static int bcast_loop_work_offt = 0; + constexpr static int reg_load_loop_work_off = 1 * reg64_size_; + constexpr static int perm_reg_offset = 2 * reg64_size_; + constexpr static int broadcast_space = 3 * reg64_size_; + constexpr static int reg_abi_param1_backup = 4 * reg64_size_; + constexpr static int reg_dw_binary_output_off = 5 * reg64_size_; + constexpr static int stack_space_needed = 376; + + void bcast_loop(int load_loop_blk); + void reduce_loop(int load_loop_blk, int ur, int substep, bool wraparound); + void compute_diff_bias(int load_loop_blk); + + Xbyak::Address output_ptr(const int i_load, const int i_ur); + void apply_postops(const int load_loop_blk, const int ur); + void generate() override; + static void balance(jit_1x1_conv_conf_t &jcp, int nthreads); + inline bool is_bcast_layout_nxc() { + switch (jcp.prop_kind) { + case prop_kind::forward_training: + case prop_kind::forward_inference: + return utils::one_of(jcp.src_tag, format_tag::ndhwc, + format_tag::nhwc, format_tag::nwc); + case prop_kind::backward_data: + return utils::one_of(jcp.dst_tag, format_tag::ndhwc, + format_tag::nhwc, format_tag::nwc); + case prop_kind::backward_weights: + return jcp.uses_permw_transposition + && utils::one_of(jcp.src_tag, format_tag::ndhwc, + format_tag::nhwc, format_tag::nwc); + default: assert(!"invalid prop_kind"); return false; + } + } + inline bool is_load_layout_nxc() { + return jcp.prop_kind == prop_kind::backward_weights + && jcp.uses_permw_transposition + && utils::one_of(jcp.dst_tag, format_tag::ndhwc, + format_tag::nhwc, format_tag::nwc); + } + inline bool is_out_layout_nxc() { + switch (jcp.prop_kind) { + case prop_kind::forward_training: + case prop_kind::forward_inference: + return utils::one_of(jcp.dst_tag, format_tag::ndhwc, + format_tag::nhwc, format_tag::nwc); + case prop_kind::backward_data: + return utils::one_of(jcp.src_tag, format_tag::ndhwc, + format_tag::nhwc, format_tag::nwc); + case prop_kind::backward_weights: return false; + default: assert(!"invalid prop_kind"); return false; + } + } + + inline Xbyak::Zmm may_be_mask_zmm(Xbyak::Zmm zmm, bool mask_flag, + bool zero_mask, bool use_extended_mask = false) { + if (mask_flag) { + zmm = zmm + | (use_extended_mask ? k_load_dim_mask_extended + : k_load_dim_mask); + if (zero_mask) zmm = zmm | T_z; + } + return zmm; + } + + inline Xbyak::Ymm may_be_mask_ymm( + Xbyak::Ymm ymm, bool mask_flag, bool zero_mask = false) { + if (mask_flag) { + ymm = ymm | k_load_dim_mask; + if (zero_mask) ymm = ymm | T_z; + } + return ymm; + } + + inline size_t get_output_offset( + const int i_load, const int i_ur, bool ignore_dw_conv) { + const bool is_output_layout_nxc = is_out_layout_nxc(); + const size_t i_load_shift = is_output_layout_nxc + ? jcp.load_block + : (!ignore_dw_conv && jcp.with_dw_conv ? jcp.ow : jcp.bcast_dim) + * jcp.load_block; + const size_t i_ur_shift + = is_output_layout_nxc ? jcp.load_dim : jcp.load_block; + return jcp.typesize_out * (i_load * i_load_shift + i_ur * i_ur_shift); + } + + std::unique_ptr bf16_emu_; +}; +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_bf16_1x1_convolution.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_bf16_1x1_convolution.hpp new file mode 100644 index 0000000000000000000000000000000000000000..33599bb7c38d2633ca2712653971253972802095 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_bf16_1x1_convolution.hpp @@ -0,0 +1,577 @@ +/******************************************************************************* +* Copyright 2019-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_AVX512_CORE_BF16_1X1_CONVOLUTION_HPP +#define CPU_X64_JIT_AVX512_CORE_BF16_1X1_CONVOLUTION_HPP + +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/primitive.hpp" +#include "common/primitive_hashing.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_convolution_pd.hpp" +#include "cpu/cpu_engine.hpp" +#include "cpu/dw_convolution_utils.hpp" +#include "cpu/platform.hpp" + +#include "cpu/x64/cpu_reducer.hpp" +#include "cpu/x64/jit_avx512_core_bf16_1x1_conv_kernel.hpp" +#include "cpu/x64/jit_transpose_utils.hpp" +#include "cpu/x64/jit_uni_1x1_conv_utils.hpp" +#include "cpu/x64/jit_uni_dw_convolution.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +template +struct jit_avx512_core_bf16_1x1_convolution_fwd_t : public primitive_t { + struct pd_t : public cpu_convolution_fwd_pd_t { + using dw_conv_pd_type = cpu_convolution_fwd_pd_t; + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const typename pd_t::base_class *hint_fwd_pd) + : cpu_convolution_fwd_pd_t(adesc, attr, hint_fwd_pd) + , jcp_() + , rtus_() + , jcp_dw_(nullptr) {} + + pd_t(const pd_t &other) : cpu_convolution_fwd_pd_t(other) { + if (copy(other) != status::success) is_initialized_ = false; + } + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit_bf16_1x1:", jcp_.isa, ""), + jit_avx512_core_bf16_1x1_convolution_fwd_t); + + status_t init(engine_t *engine) { + bool ok = true && mayiuse(avx512_core) && is_fwd() + && set_default_alg_kind(alg_kind::convolution_direct) + && expect_data_types(data_type::bf16, data_type::bf16, + data_type::undef, dst_type, data_type::undef) + && IMPLICATION(with_bias(), + utils::one_of(weights_md(1)->data_type, + data_type::f32, data_type::bf16)) + && attr()->has_default_values( + primitive_attr_t::skip_mask_t::post_ops, dst_type) + && !has_zero_dim_memory() && set_default_formats() + && attr_.set_default_formats(dst_md(0)) == status::success; + if (!ok) return status::unimplemented; + + const convolution_desc_t *conv_d = desc(); + const memory_desc_t *src_d = src_md(); + rtus_prepare(this, conv_d, src_d, dst_md(), weights_md()); + + CHECK(jit_avx512_core_bf16_1x1_conv_kernel::init_conf(jcp_, *conv_d, + *src_d, *weights_md(), *dst_md(), attr_, + dnnl_get_max_threads(), rtus_.reduce_src_)); + + if (jcp_.with_dw_conv) CHECK(depthwise_po_init(engine)); + + auto scratchpad = scratchpad_registry().registrar(); + CHECK(jit_avx512_core_bf16_1x1_conv_kernel::init_scratchpad( + scratchpad, jcp_)); + + rtus_prepare_space_info(this, scratchpad, jcp_.nthr); + + return status::success; + } + + const memory_desc_t *dst_1x1_md(int index = 0) const { + return cpu_convolution_fwd_pd_t::dst_md(index); + } + + const memory_desc_t *dst_md( + int index = 0, bool user_input = false) const override { + return jcp_.with_dw_conv + ? dw_conv_pd_->dst_md(index, user_input) + : cpu_convolution_fwd_pd_t::dst_md(index, user_input); + } + + const memory_desc_t *arg_md( + int arg, bool user_input = false) const override { + if (jcp_.with_dw_conv) { + switch (arg) { + case DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_SRC: + return cpu_convolution_fwd_pd_t::dst_md(0, user_input); + case DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_WEIGHTS: + return dw_conv_pd_->weights_md(0); + case DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_BIAS: + return dw_conv_pd_->weights_md(1); + default: break; + } + } + return convolution_fwd_pd_t::arg_md(arg, user_input); + } + + arg_usage_t arg_usage(int arg) const override { + if (arg == (DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_WEIGHTS)) + return arg_usage_t::input; + + if (arg == (DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_BIAS) + && attr_post_op_dw_inputs() > 1) + return arg_usage_t::input; + + return convolution_fwd_pd_t::arg_usage(arg); + } + + jit_1x1_conv_conf_t jcp_; + reduce_to_unit_stride_t rtus_; + jit_conv_conf_t *jcp_dw_; // doesn't own a resource + std::unique_ptr dw_conv_pd_; + + protected: + template + using dw_pd_t = typename jit_uni_dw_convolution_fwd_t::pd_t; + + bool set_default_formats() { + using namespace format_tag; + + const memory_desc_wrapper src_d(&src_md_); + const memory_desc_wrapper dst_d(&dst_md_); + + const auto dat_tag_nxc = utils::pick(ndims() - 3, nwc, nhwc, ndhwc); + const auto dat_tag_nCx16c + = utils::pick(ndims() - 3, nCw16c, nChw16c, nCdhw16c); + const auto curr_src_tag + = src_d.matches_one_of_tag(dat_tag_nxc, dat_tag_nCx16c); + const auto curr_dst_tag + = dst_d.matches_one_of_tag(dat_tag_nxc, dat_tag_nCx16c); + const auto is_data_layout_nxc + = IMPLICATION(curr_src_tag != dat_tag_nxc, + src_d.format_kind() == format_kind::any) + && IMPLICATION(curr_dst_tag != dat_tag_nxc, + dst_d.format_kind() == format_kind::any) + && utils::one_of(dat_tag_nxc, curr_src_tag, curr_dst_tag); + + auto dat_tag = is_data_layout_nxc ? dat_tag_nxc : dat_tag_nCx16c; + auto wei_tag = utils::pick(2 * ndims() - 6 + with_groups(), + OIw8i16o2i, gOIw8i16o2i, OIhw8i16o2i, gOIhw8i16o2i, + OIdhw8i16o2i, gOIdhw8i16o2i); + + return set_default_formats_common(dat_tag, wei_tag, dat_tag); + } + + status_t copy(const pd_t &other) { + jcp_ = other.jcp_; + rtus_ = other.rtus_; + jcp_dw_ = nullptr; + using namespace data_type; + if (other.dw_conv_pd_) { + dw_conv_pd_.reset(static_cast( + other.dw_conv_pd_->clone())); + if (!dw_conv_pd_) return status::out_of_memory; + auto dw_dst_dt = dw_conv_pd_->dst_md()->data_type; + + switch (dw_dst_dt) { + case bf16: + jcp_dw_ = &( + static_cast *>(dw_conv_pd_.get()) + ->jcp_); + break; + case f32: + jcp_dw_ = &( + static_cast *>(dw_conv_pd_.get()) + ->jcp_); + break; + default: assert(!"unreachable"); + } + } + return status::success; + } + + status_t depthwise_po_init(engine_t *engine) { + using namespace memory_tracking; + auto &jcp_1x1 = jcp_; + jit_conv_conf_t *jcp_dw = nullptr; + primitive_attr_t attr_1x1(*attr()); + if (!attr_1x1.is_initialized()) return status::out_of_memory; + + const auto &src_md = dst_md_; + const memory_desc_wrapper src_d(src_md); + const auto nthr = dnnl_get_max_threads(); + auto l2_cache = platform::get_per_core_cache_size(2) * nthr; + + // Note: A robust fusion implementation would be to check if both + // 1x1 conv and dw conv that are considered here for fusion are + // optimal independently. This would require creating a new + // primitive_desc through primitive_iterator & check if they match. + // Due to concern that these creations and/or checks could be heavy, + // for 1x1: Check that no better ISA is available. + // for dw: Always fuse with same ISA. + // Caveat: May be a better dw conv exists. + + bool ok = !mayiuse(avx512_core_amx) + && (attr_1x1.post_ops_.find(primitive_kind::sum) == -1) + // TODO: Below may be further tuned. + && (l2_cache * 2 < src_d.size()) + // load_grp_count check can be redundant due to l2 check + // above. Adding it explicitly as the current driver doesn't + // work if this condition fails. + && (jcp_1x1.load_grp_count < 2); + if (!ok) return status::unimplemented; + + int dw_po_index + = attr_1x1.post_ops_.find(primitive_kind::convolution); + + convolution_desc_t cd_dw; + primitive_attr_t attr_dw; + CHECK(get_depthwise_conv_desc( + cd_dw, src_md, attr_1x1, attr_dw, dw_po_index)); + + auto dw_dst_dt = cd_dw.dst_desc.data_type; + +#define CASE(dt) \ + case dt: { \ + std::unique_ptr> fusable_pd( \ + new dw_pd_t
(&cd_dw, &attr_dw, nullptr)); \ + CHECK(fusable_pd->init(engine)); \ + jcp_dw = &(fusable_pd->jcp_); \ + dw_conv_pd_ = std::move(fusable_pd); \ + break; \ + } + if (jcp_1x1.dst_dt == data_type::bf16) { + switch (dw_dst_dt) { + CASE(data_type::bf16); + CASE(data_type::f32); + default: return status::unimplemented; + } + } else + return status::unimplemented; +#undef CASE + + ok = true + && (dnnl_memory_desc_equal(&src_md, dw_conv_pd_->src_md(0))) + && (jcp_1x1.oc_without_padding % jcp_1x1.oc_block == 0) + && IMPLICATION( + jcp_dw->ow_block, jcp_dw->ow_block == jcp_dw->ow); + if (!ok) return status::unimplemented; + + assert(dw_conv_pd_->dst_md(0)->format_kind != format_kind::any); + assert(dw_conv_pd_->weights_md(0)->format_kind != format_kind::any); + assert(IMPLICATION( + dw_conv_pd_->weights_md(1)->data_type != data_type::undef, + dw_conv_pd_->weights_md(1)->format_kind + != format_kind::any)); + + jcp_dw->is_fused_conv = true; + // TODO: Support/experiment arbitary oc_work in dw conv. + // Until then we keep ch_work perfectly divisible. + while (jcp_1x1.nb_load % jcp_1x1.nb_load_blocking != 0) + --jcp_1x1.nb_load_blocking; + jcp_1x1.nb_load_blocking_max = jcp_1x1.nb_load_blocking; + + while (jcp_1x1.nb_load_blocking % jcp_dw->nb_ch_blocking != 0) + --jcp_dw->nb_ch_blocking; + + jcp_dw->dw_conv_buffer_oc + = jcp_1x1.nb_load_blocking * jcp_1x1.oc_block; + + registrar_t scratchpad(scratchpad_registry_); + registrar_t dw_scratchpad(scratchpad, names::prefix_fusion); + + size_t dw_conv_buffer_size_ = (size_t)nthr * jcp_dw->kh * jcp_dw->iw + * jcp_dw->dw_conv_buffer_oc; + assert(dw_conv_buffer_size_); + dw_scratchpad.book(memory_tracking::names::key_fusion_inout_buffer, + dw_conv_buffer_size_, + types::data_type_size(dw_conv_pd_->src_md()->data_type)); + + dw_conv_kernel_t::init_scratchpad(dw_scratchpad, *jcp_dw); + + return status::success; + } + }; + + template + friend status_t init_rtus_driver(conv_t *self); + jit_avx512_core_bf16_1x1_convolution_fwd_t(const pd_t *apd) + : primitive_t(apd) {} + + typedef typename prec_traits::type src_data_t; + typedef typename prec_traits::type wei_data_t; + typedef typename prec_traits::type dst_data_t; + // Note: In case of fused depthwise convolution, the final output datatype + // may not be dst_data_t. + typedef typename prec_traits::type dw_wei_data_t; + + status_t init(engine_t *engine) override { + CHECK(safe_ptr_assign(kernel_, + new jit_avx512_core_bf16_1x1_conv_kernel( + pd()->jcp_, *pd()->attr(), *pd()->dst_1x1_md(0)))); + CHECK(kernel_->create_kernel()); + + if (pd()->jcp_.with_dw_conv) { + CHECK(safe_ptr_assign(kernel_dw_, + new dw_conv_kernel_t(*(pd()->jcp_dw_), *pd()->dst_md(0)))); + CHECK(kernel_dw_->create_kernel()); + } + + CHECK(init_rtus_driver(this)); + return status::success; + } + + status_t execute(const exec_ctx_t &ctx) const override { + execute_forward(ctx); + return status::success; + } + +private: + void execute_forward(const exec_ctx_t &ctx) const; + void execute_forward_thr(const int ithr, const int nthr, + const src_data_t *src, const wei_data_t *weights, const char *bias, + const dw_wei_data_t *weights_dw, const float *bias_dw, + const char *dst, const memory_tracking::grantor_t &scratchpad, + const void *post_ops_binary_rhs_arg_vec, + const void *post_ops_binary_rhs_arg_vec_dw) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr kernel_; + std::unique_ptr> rtus_driver_; + using dw_conv_kernel_t + = jit_uni_dw_conv_fwd_kernel; + std::unique_ptr kernel_dw_; +}; + +template +struct jit_avx512_core_bf16_1x1_convolution_bwd_data_t : public primitive_t { + struct pd_t : public cpu_convolution_bwd_data_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const convolution_fwd_pd_t *hint_fwd_pd) + : cpu_convolution_bwd_data_pd_t(adesc, attr, hint_fwd_pd) + , jcp_() + , rtus_() {} + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit_bf16_1x1:", jcp_.isa, ""), + jit_avx512_core_bf16_1x1_convolution_bwd_data_t); + + status_t init(engine_t *engine) { + bool ok = true && mayiuse(avx512_core) && is_bwd_d() + && set_default_alg_kind(alg_kind::convolution_direct) + && expect_data_types(diff_src_type, data_type::bf16, + data_type::undef, data_type::bf16, data_type::undef) + && attr()->has_default_values() && !has_zero_dim_memory() + && set_default_formats(); + if (!ok) return status::unimplemented; + + const convolution_desc_t *conv_d = desc(); + const memory_desc_t *diff_src_d = diff_src_md(); + rtus_prepare(this, conv_d, diff_src_d, diff_dst_md(), weights_md()); + + status_t status = jit_avx512_core_bf16_1x1_conv_kernel::init_conf( + jcp_, *conv_d, *diff_src_d, *weights_md(), *diff_dst_md(), + attr_, dnnl_get_max_threads(), rtus_.reduce_src_); + if (status != status::success) return status; + + auto scratchpad = scratchpad_registry().registrar(); + status = jit_avx512_core_bf16_1x1_conv_kernel::init_scratchpad( + scratchpad, jcp_); + if (status != status::success) return status; + rtus_prepare_space_info(this, scratchpad, jcp_.nthr); + + return status::success; + } + + // TODO (Roma): structs conf header cleanup + jit_1x1_conv_conf_t jcp_; + reduce_to_unit_stride_t rtus_; + + protected: + bool set_default_formats() { + using namespace format_tag; + + const memory_desc_wrapper diff_src_d(&diff_src_md_); + const memory_desc_wrapper diff_dst_d(&diff_dst_md_); + + const auto dat_tag_nxc = utils::pick(ndims() - 3, nwc, nhwc, ndhwc); + const auto dat_tag_nCx16c + = utils::pick(ndims() - 3, nCw16c, nChw16c, nCdhw16c); + const auto curr_src_tag = diff_src_d.matches_one_of_tag( + dat_tag_nxc, dat_tag_nCx16c); + const auto curr_dst_tag = diff_dst_d.matches_one_of_tag( + dat_tag_nxc, dat_tag_nCx16c); + const auto is_data_layout_nxc + = IMPLICATION(curr_src_tag != dat_tag_nxc, + diff_src_d.format_kind() == format_kind::any) + && IMPLICATION(curr_dst_tag != dat_tag_nxc, + diff_dst_d.format_kind() == format_kind::any) + && utils::one_of(dat_tag_nxc, curr_src_tag, curr_dst_tag); + auto dat_tag = is_data_layout_nxc ? dat_tag_nxc : dat_tag_nCx16c; + auto wei_tag = utils::pick(2 * ndims() - 6 + with_groups(), + IOw8o16i2o, gIOw8o16i2o, IOhw8o16i2o, gIOhw8o16i2o, + IOdhw8o16i2o, gIOdhw8o16i2o); + + return set_default_formats_common(dat_tag, wei_tag, dat_tag); + } + }; + + template + friend status_t init_rtus_driver(conv_t *self); + + jit_avx512_core_bf16_1x1_convolution_bwd_data_t(const pd_t *apd) + : primitive_t(apd) {} + + typedef typename prec_traits::type diff_dst_data_t; + typedef typename prec_traits::type wei_data_t; + typedef typename prec_traits::type diff_src_data_t; + + status_t init(engine_t *engine) override { + CHECK(safe_ptr_assign(kernel_, + new jit_avx512_core_bf16_1x1_conv_kernel( + pd()->jcp_, *pd()->attr(), *pd()->dst_md(0)))); + CHECK(kernel_->create_kernel()); + CHECK(init_rtus_driver(this)); + return status::success; + } + + status_t execute(const exec_ctx_t &ctx) const override { + execute_backward_data(ctx); + return status::success; + } + +private: + void execute_backward_data(const exec_ctx_t &ctx) const; + void execute_backward_data_thr(const int, const int, + const diff_dst_data_t *, const wei_data_t *, diff_src_data_t *, + const memory_tracking::grantor_t &scratchpad) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr kernel_; + /* reduction to unit stride */ + std::unique_ptr> rtus_driver_; +}; + +template +struct jit_avx512_core_bf16_1x1_convolution_bwd_weights_t : public primitive_t { + struct pd_t : public cpu_convolution_bwd_weights_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const convolution_fwd_pd_t *hint_fwd_pd) + : cpu_convolution_bwd_weights_pd_t(adesc, attr, hint_fwd_pd) + , jcp_() + , rtus_() {} + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit_bf16_1x1:", jcp_.isa, ""), + jit_avx512_core_bf16_1x1_convolution_bwd_weights_t); + + status_t init(engine_t *engine) { + using namespace prop_kind; + assert(engine->kind() == engine_kind::cpu); + bool ok = true && mayiuse(avx512_core) && is_bwd_w() + && set_default_alg_kind(alg_kind::convolution_direct) + && expect_data_types(data_type::bf16, diff_weights_type, + data_type::undef, data_type::bf16, data_type::undef) + && IMPLICATION(with_bias(), + utils::one_of(diff_weights_md(1)->data_type, + data_type::f32, data_type::bf16)) + && attr()->has_default_values() && !has_zero_dim_memory() + && set_default_formats(); + if (!ok) return status::unimplemented; + + const convolution_desc_t *conv_d = desc(); + const memory_desc_t *src_d = src_md(); + rtus_prepare( + this, conv_d, src_d, diff_dst_md(), diff_weights_md(0)); + + status_t status = jit_avx512_core_bf16_1x1_conv_kernel::init_conf( + jcp_, *conv_d, *src_d, *diff_weights_md(0), *diff_dst_md(), + attr_, dnnl_get_max_threads(), rtus_.reduce_src_); + if (status != status::success) return status; + + auto scratchpad = scratchpad_registry().registrar(); + status = jit_avx512_core_bf16_1x1_conv_kernel::init_scratchpad( + scratchpad, jcp_); + if (status != status::success) return status; + + rtus_prepare_space_info(this, scratchpad, jcp_.nthr); + + return status::success; + } + + // TODO (Roma): structs conf header cleanup + jit_1x1_conv_conf_t jcp_; + reduce_to_unit_stride_t rtus_; + + protected: + bool set_default_formats() { + using namespace format_tag; + + const memory_desc_wrapper src_d(&src_md_); + const memory_desc_wrapper diff_dst_d(&diff_dst_md_); + + const auto dat_tag_nxc = utils::pick(ndims() - 3, nwc, nhwc, ndhwc); + const auto dat_tag_nCx16c + = utils::pick(ndims() - 3, nCw16c, nChw16c, nCdhw16c); + const auto curr_src_tag + = src_d.matches_one_of_tag(dat_tag_nxc, dat_tag_nCx16c); + const auto curr_dst_tag = diff_dst_d.matches_one_of_tag( + dat_tag_nxc, dat_tag_nCx16c); + const auto is_data_layout_nxc + = IMPLICATION(curr_src_tag != dat_tag_nxc, + src_d.format_kind() == format_kind::any) + && IMPLICATION(curr_dst_tag != dat_tag_nxc, + diff_dst_d.format_kind() == format_kind::any) + && utils::one_of(dat_tag_nxc, curr_src_tag, curr_dst_tag); + auto dat_tag = is_data_layout_nxc ? dat_tag_nxc : dat_tag_nCx16c; + auto wei_tag = utils::pick(2 * ndims() - 6 + with_groups(), + OIw16i16o, gOIw16i16o, OIhw16i16o, gOIhw16i16o, OIdhw16i16o, + gOIdhw16i16o); + + bool ok = set_default_formats_common(dat_tag, wei_tag, dat_tag); + return ok; + } + }; + + template + friend status_t init_rtus_driver(conv_t *self); + + jit_avx512_core_bf16_1x1_convolution_bwd_weights_t(const pd_t *apd) + : primitive_t(apd) {} + + status_t init(engine_t *engine) override; + + status_t execute(const exec_ctx_t &ctx) const override { + execute_backward_weights(ctx); + return status::success; + } + + typedef typename prec_traits::type src_data_t; + typedef typename prec_traits::type diff_dst_data_t; + + typedef typename prec_traits::type diff_wei_data_t; + +private: + void execute_backward_weights(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr kernel_; + std::unique_ptr> acc_ker_; + + /* reduction to unit stride */ + std::unique_ptr> rtus_driver_; + + std::unique_ptr tr_reorder_; + std::unique_ptr + tr_reorder_nhwc_src_; + std::unique_ptr + tr_reorder_nhwc_ddst_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_bf16_conv_kernel.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_bf16_conv_kernel.hpp new file mode 100644 index 0000000000000000000000000000000000000000..a2ef17973630ac5c8cd92cda527f8f8c7e94161f --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_bf16_conv_kernel.hpp @@ -0,0 +1,733 @@ +/******************************************************************************* +* Copyright 2019-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_AVX512_CORE_BF16_CONV_KERNEL_HPP +#define CPU_X64_JIT_AVX512_CORE_BF16_CONV_KERNEL_HPP + +#include "common/c_types_map.hpp" +#include "common/memory_tracking.hpp" + +#include "cpu/x64/injectors/jit_uni_postops_injector.hpp" +#include "cpu/x64/jit_avx512_core_bf16cvt.hpp" +#include "cpu/x64/jit_generator.hpp" +#include "cpu/x64/jit_primitive_conf.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +template +struct _jit_avx512_core_bf16_fwd_kernel : public jit_generator { + _jit_avx512_core_bf16_fwd_kernel(const jit_conv_conf_t &ajcp, + const primitive_attr_t &attr, const memory_desc_t &dst_md); + + DECLARE_CPU_JIT_AUX_FUNCTIONS(_jit_avx512_core_bf16_fwd_kernel) + + const jit_conv_conf_t &jcp; + const primitive_attr_t &attr_; + +private: + constexpr static int isa_simd_width_ + = cpu_isa_traits::vlen / sizeof(float); + using Vmm_down_t = + typename utils::conditional::value, + Xbyak::Ymm, Xbyak::Xmm>::type; + using reg64_t = const Xbyak::Reg64; + enum { + ker_reg_base_idx = 28, + ker_code_size = 1024 * 1024, + }; + + reg64_t param = abi_param1; //L: RDI, W: RCX + + reg64_t reg_src = r8; + reg64_t reg_ker = r9; + reg64_t reg_dst = r10; + reg64_t reg_owb = r11; + + reg64_t aux_reg_src = r12; + reg64_t aux_reg_ker = r13; + + reg64_t reg_ic = rax; + reg64_t reg_oc = r15; + reg64_t reg_bias = rbx; + + reg64_t reg_kj = abi_not_param1; + reg64_t reg_ki = reg_bias; + reg64_t reg_oi = rdx; + reg64_t reg_kh = rsi; + + reg64_t reg_long_offt = r14; + + /* binary post-ops operand */ + reg64_t temp_offset_reg = r12; + + int vmm_dst_idx(const int i_ur, const int i_oc) const; + Vmm vmm_dst(const int i_ur, const int i_oc) const; + + Vmm vmm_src(int i_ic, int nb_x_blocking) { + int idx = i_ic + nb_x_blocking * jcp.ur_w; + assert(idx < 31); + return Vmm(idx); + } + + Vmm_down_t vmm_src_down(int i_ic, int nb_x_blocking) { + int idx = i_ic + nb_x_blocking * jcp.ur_w; + assert(idx < 31); + return Vmm_down_t(idx); + } + + inline Vmm may_be_mask_vmm(Vmm vmm, bool mask_flag, bool zero_mask, + bool use_extended_mask = false) { + if (mask_flag) { + vmm = vmm + | (use_extended_mask ? k_oc_tail_mask_extended + : k_oc_tail_mask); + if (zero_mask) vmm = vmm | T_z; + } + return vmm; + } + + inline Vmm_down_t may_be_mask_vmm(Vmm_down_t vmm, bool mask_flag) { + return (mask_flag) ? vmm | k_oc_tail_mask : vmm; + } + + Vmm vmm_wei = Vmm(31); + Vmm vmm_prev_dst = Vmm(31); + Vmm vmm_bias = Vmm(31); + + Xbyak::Zmm bf16_emu_reserv_1 = Xbyak::Zmm(26); + Xbyak::Zmm bf16_emu_reserv_2 = Xbyak::Zmm(27); + Xbyak::Zmm bf16_emu_reserv_3 = Xbyak::Zmm(28); + reg64_t bf16_emu_scratch = reg_ic; + Xbyak::Zmm bf16_emu_reserv_4 = Xbyak::Zmm(29); + Xbyak::Zmm bf16_emu_reserv_5 = Xbyak::Zmm(30); + + Xbyak::Opmask odd_load_mask = Xbyak::Opmask(2); + Xbyak::Opmask even_load_mask = Xbyak::Opmask(3); + Xbyak::Opmask k_oc_tail_mask = Xbyak::Opmask(4); + Xbyak::Opmask k_oc_tail_mask_extended = Xbyak::Opmask(5); + const Xbyak::Opmask postops_mask = Xbyak::Opmask(6); + + constexpr static int off_reg_src_ = 0; + constexpr static int off_reg_ker_ = 8; + constexpr static int stack_space_needed_ = 16; + + std::unique_ptr> + postops_injector_; + std::unique_ptr bf16_emu_; + + inline void prepare_dst(int ur_w); + void apply_postops(int ur_w); + inline void store_dst(int ur_w); + inline void compute_loop(int ur_w, int pad_l, int pad_r); + + void generate() override; + + inline dim_t get_dst_offset(dim_t sp_idx, int ocb) { + const bool is_layout_nxc = is_dst_layout_nxc(); + dim_t sp_str = is_layout_nxc ? jcp.ngroups * jcp.oc : jcp.oc_block; + dim_t ocb_str = jcp.oc_block + * (is_layout_nxc ? 1 : (dim_t)jcp.od * jcp.oh * jcp.ow); + return jcp.typesize_out * (ocb_str * ocb + sp_str * sp_idx); + } + + inline dim_t filter_w_to_src(int kw, int ow = 0, int pad_l = 0) { + return kw * (jcp.dilate_w + 1) + ow * jcp.stride_w - pad_l; + } + inline dim_t filter_h_to_src(int kh) { + return kh * (jcp.dilate_h + 1) * jcp.iw; + } + inline dim_t filter_d_to_src(int kd) { + return kd * (jcp.dilate_d + 1) * jcp.iw * jcp.ih; + } + + inline dim_t get_src_offset(dim_t ic_idx, dim_t isp) { + int icb = ic_idx / jcp.ic_block; + int ic = ic_idx % jcp.ic_block; + dim_t isp_str = is_src_layout_nxc() + ? jcp.ngroups * jcp.ic + : (jcp.is_1stconv ? 1 : jcp.ic_block); + dim_t full_spatial_size = (dim_t)jcp.iw * jcp.ih * jcp.id; + dim_t ic_str = jcp.is_1stconv && !is_src_layout_nxc() + ? full_spatial_size + : 1; + dim_t icb_str + = (is_src_layout_nxc() ? 1 : full_spatial_size) * jcp.ic_block; + return jcp.typesize_in * (isp_str * isp + icb_str * icb + ic_str * ic); + } + + inline dim_t get_kernel_offset( + int ocb, int ic_idx, int kw, int kh = 0, int kd = 0) { + int scale = 2; //bf16 vnni is used + int rnd_ic_block = utils::rnd_up(jcp.ic_block, scale); + int icb = ic_idx / jcp.ic_block; + int ic = ic_idx % jcp.ic_block; + dim_t ksp_str = rnd_ic_block * jcp.oc_block; + dim_t ksp_idx = kd * jcp.kh * jcp.kw + kh * jcp.kw + kw; + + dim_t icb_str = jcp.kd * jcp.kh * jcp.kw * ksp_str; + dim_t ocb_str = jcp.nb_ic * icb_str; + dim_t ic_off = (ic / scale) * jcp.oc_block * scale + (ic % scale); + return jcp.typesize_in + * (ocb * ocb_str + icb * icb_str + ksp_idx * ksp_str + ic_off); + } + + int get_ow_start(int ki, int pad_l) { + return nstl::max(0, + utils::div_up(pad_l - ki * (jcp.dilate_w + 1), jcp.stride_w)); + } + + int get_ow_end(int ur_w, int ki, int pad_r) { + return ur_w + - nstl::max(0, + utils::div_up( + pad_r - (jcp.kw - 1 - ki) * (jcp.dilate_w + 1), + jcp.stride_w)); + } + inline bool is_src_layout_nxc() { + return utils::one_of(jcp.src_tag, format_tag::ndhwc, format_tag::nhwc, + format_tag::nwc); + } + inline bool is_dst_layout_nxc() { + return utils::one_of(jcp.dst_tag, format_tag::ndhwc, format_tag::nhwc, + format_tag::nwc); + } +}; + +struct jit_avx512_core_bf16_fwd_kernel { + jit_avx512_core_bf16_fwd_kernel(const jit_conv_conf_t &ajcp, + const primitive_attr_t &attr, const memory_desc_t &dst_md) + : kernel_(nullptr) { + switch (ajcp.oc_block) { + case 16: + kernel_ = new _jit_avx512_core_bf16_fwd_kernel( + ajcp, attr, dst_md); + return; + case 8: + kernel_ = new _jit_avx512_core_bf16_fwd_kernel( + ajcp, attr, dst_md); + return; + case 4: + kernel_ = new _jit_avx512_core_bf16_fwd_kernel( + ajcp, attr, dst_md); + return; + default: assert(!"invalid channel blocking"); + } + } + + status_t create_kernel() { + if (kernel_) return kernel_->create_kernel(); + return status::out_of_memory; + } + + ~jit_avx512_core_bf16_fwd_kernel() { delete kernel_; } + + static status_t init_conf(jit_conv_conf_t &jcp, + const convolution_desc_t &cd, memory_desc_t &src_pd, + memory_desc_t &weights_pd, memory_desc_t &dst_pd, + memory_desc_t &bias_pd, primitive_attr_t &attr, int nthreads); + static void init_scratchpad(memory_tracking::registrar_t &scratchpad, + const jit_conv_conf_t &jcp); + + void operator()(const jit_conv_call_s *p) const { (*kernel_)(p); } + const Xbyak::uint8 *jit_ker() const { return kernel_->jit_ker(); } + +private: + DNNL_DISALLOW_COPY_AND_ASSIGN(jit_avx512_core_bf16_fwd_kernel); + jit_generator *kernel_; +}; + +template +struct _jit_avx512_core_bf16_bwd_data_kernel : public jit_generator { + + _jit_avx512_core_bf16_bwd_data_kernel(const jit_conv_conf_t &ajcp) + : jit_generator( + jit_name(), nullptr, ker_code_size, true, avx512_core_bf16) + , jcp(ajcp) + , bf16_emu_(nullptr) { + if (!isa_has_bf16(jcp.isa)) + bf16_emu_ = utils::make_unique(this, + bf16_emu_reserv_1, bf16_emu_reserv_2, bf16_emu_reserv_3, + bf16_emu_scratch, bf16_emu_reserv_4, bf16_emu_reserv_5); + } + + DECLARE_CPU_JIT_AUX_FUNCTIONS(_jit_avx512_core_bf16_bwd_data_kernel_f32) + + const jit_conv_conf_t &jcp; + +private: + using Vmm_down_t = + typename utils::conditional::value, + Xbyak::Ymm, Xbyak::Xmm>::type; + using reg64_t = const Xbyak::Reg64; + enum { + ker_reg_base_idx = 31, + ker_code_size = 1024 * 1024, + }; + + reg64_t param = abi_param1; + reg64_t reg_dst = r8; + reg64_t reg_ker = r9; + reg64_t reg_src = r10; + + reg64_t reg_iwb = rdx; + + reg64_t aux_reg_dst = r14; + reg64_t aux_reg_ker = r15; + + reg64_t aux_reg_dst_d = r12; + reg64_t aux_reg_ker_d = r13; + reg64_t reg_ki = rsi; + + reg64_t reg_kj = rax; + reg64_t reg_oi = rbx; + reg64_t reg_kh = abi_not_param1; + + reg64_t reg_oc = r11; + reg64_t reg_ic = aux_reg_ker_d; + + Xbyak::Opmask k_ic_tail_mask = Xbyak::Opmask(2); + Xbyak::Opmask k_ic_tail_mask_extended = Xbyak::Opmask(3); + + Vmm vmm_ddst(int i_ic) { + int idx = i_ic + jcp.nb_ic_blocking * jcp.ur_w; + assert(idx < ker_reg_base_idx); + return Vmm(idx); + } + + Vmm_down_t vmm_ddst_down(int i_ic) { + int idx = i_ic + jcp.nb_ic_blocking * jcp.ur_w; + assert(idx < ker_reg_base_idx); + return Vmm_down_t(idx); + } + + Vmm vmm_dsrc(int i_ur, int i_oc) { + int idx = i_ur + i_oc * jcp.ur_w; + assert(idx < ker_reg_base_idx); + return Vmm(idx); + } + + inline Vmm may_be_mask_vmm(Vmm vmm, bool mask_flag, bool zero_mask, + bool use_extended_mask = false) { + if (mask_flag) { + vmm = vmm + | (use_extended_mask ? k_ic_tail_mask_extended + : k_ic_tail_mask); + if (zero_mask) vmm = vmm | T_z; + } + return vmm; + } + + inline Vmm_down_t may_be_mask_vmm(Vmm_down_t vmm, bool mask_flag) { + return mask_flag ? vmm | k_ic_tail_mask : vmm; + } + + Xbyak::Zmm bf16_emu_reserv_1 = Xbyak::Zmm(26); + Xbyak::Zmm bf16_emu_reserv_2 = Xbyak::Zmm(27); + Xbyak::Zmm bf16_emu_reserv_3 = Xbyak::Zmm(28); + reg64_t bf16_emu_scratch = reg_kj; + Xbyak::Zmm bf16_emu_reserv_4 = Xbyak::Zmm(29); + Xbyak::Zmm bf16_emu_reserv_5 = Xbyak::Zmm(30); + + Vmm vmm_wei = Vmm(31); + std::unique_ptr bf16_emu_; + + inline void prepare_output(int ur_w); + inline void store_output(int ur_w); + inline void compute_loop(int ur_w, int l_overflow, int r_overflow); + void generate() override; + + int get_iw_start(int ki, int l_overflow) { + int res = (jcp.iw - 1 + jcp.r_pad) % jcp.stride_w + + l_overflow * jcp.stride_w + - (jcp.kw - 1 - ki) * (jcp.dilate_w + 1); + while (res < 0) + res += jcp.stride_w; + + return res; + } + + int get_iw_end(int ur_w, int ki, int r_overflow) { + if (utils::one_of(ur_w, jcp.iw, jcp.ur_w_tail)) + ur_w += nstl::min(0, jcp.r_pad); // remove negative padding + int res = (ur_w - 1 + jcp.l_pad) % jcp.stride_w + + r_overflow * jcp.stride_w - ki * (jcp.dilate_w + 1); + while (res < 0) + res += jcp.stride_w; + + return ur_w - res; + } + + inline int filter_h_to_dst(int kh) { + return kh * (jcp.dilate_h + 1) * jcp.ow; + } + inline int filter_d_to_dst(int kd) { + return kd * (jcp.dilate_d + 1) * jcp.ow * jcp.oh; + } + + inline size_t get_diff_src_offset(int iw_idx, int n_ic_block) { + const bool is_nxc_layout = is_dsrc_layout_nxc(); + size_t iw_str = is_nxc_layout ? jcp.ngroups * jcp.ic : jcp.ic_block; + size_t icb_str = jcp.ic_block + * (is_nxc_layout ? 1 : (size_t)jcp.id * jcp.ih * jcp.iw); + return jcp.typesize_out * (iw_str * iw_idx + icb_str * n_ic_block); + } + + inline size_t get_diff_dst_offset( + int osp_idx, int oc_within_block_idx, int oc_block_idx = 0) { + const bool is_nxc_layout = is_ddst_layout_nxc(); + size_t osp_str = is_nxc_layout ? jcp.ngroups * jcp.oc : jcp.oc_block; + size_t ocb_str = jcp.oc_block + * (is_nxc_layout ? 1 : (size_t)jcp.od * jcp.oh * jcp.ow); + return jcp.typesize_in + * (osp_str * osp_idx + ocb_str * oc_block_idx + + oc_within_block_idx); + } + + inline size_t get_kernel_offset( + int icb, int oc_idx, int kw, int kh = 0, int kd = 0) { + int scale = 2; //bf16 vnni is used + int ocb = oc_idx / jcp.oc_block; + int oc = oc_idx % jcp.oc_block; + size_t ksp_str = jcp.ic_block * jcp.oc_block; + size_t ksp_idx = kd * jcp.kh * jcp.kw + kh * jcp.kw + kw; + + size_t icb_str = jcp.kd * jcp.kh * jcp.kw * ksp_str; + size_t ocb_str = jcp.nb_ic * icb_str; + size_t oc_off = (oc / scale) * jcp.ic_block * scale + (oc % scale); + return jcp.typesize_in + * (ocb * ocb_str + icb * icb_str + ksp_idx * ksp_str + oc_off); + } + + inline bool is_dsrc_layout_nxc() { + return utils::one_of(jcp.src_tag, format_tag::ndhwc, format_tag::nhwc, + format_tag::nwc); + } + inline bool is_ddst_layout_nxc() { + return utils::one_of(jcp.dst_tag, format_tag::ndhwc, format_tag::nhwc, + format_tag::nwc); + } +}; + +struct jit_avx512_core_bf16_bwd_data_kernel { + + jit_avx512_core_bf16_bwd_data_kernel(const jit_conv_conf_t &ajcp) + : kernel_(nullptr) { + switch (ajcp.ic_block) { + case 16: + kernel_ = new _jit_avx512_core_bf16_bwd_data_kernel( + ajcp); + return; + case 8: + kernel_ = new _jit_avx512_core_bf16_bwd_data_kernel( + ajcp); + return; + case 4: + kernel_ = new _jit_avx512_core_bf16_bwd_data_kernel( + ajcp); + return; + default: assert(!"invalid channel blocking"); + } + } + + status_t create_kernel() { + if (kernel_) return kernel_->create_kernel(); + return status::out_of_memory; + } + + ~jit_avx512_core_bf16_bwd_data_kernel() { delete kernel_; } + + static status_t init_conf(jit_conv_conf_t &jcp, + const convolution_desc_t &cd, memory_desc_t &diff_src_md, + memory_desc_t &weights_md, memory_desc_t &diff_dst_md, + int nthreads); + void operator()(const jit_conv_call_s *p) const { (*kernel_)(p); } + const Xbyak::uint8 *jit_ker() const { return kernel_->jit_ker(); } + +private: + DNNL_DISALLOW_COPY_AND_ASSIGN(jit_avx512_core_bf16_bwd_data_kernel); + jit_generator *kernel_; +}; + +struct jit_avx512_core_bf16_conv_bwd_weights_kernel_f32 : public jit_generator { + + jit_avx512_core_bf16_conv_bwd_weights_kernel_f32( + const jit_conv_conf_t &ajcp) + : jit_generator( + jit_name(), nullptr, ker_code_size, true, avx512_core_bf16) + , jcp(ajcp) + , bf16_emu_(nullptr) { + if (!isa_has_bf16(jcp.isa)) { + bf16_emu_ = utils::make_unique( + this, one, even, selector, scratch, tmp0, tmp1); + } + } + + ~jit_avx512_core_bf16_conv_bwd_weights_kernel_f32() = default; + + DECLARE_CPU_JIT_AUX_FUNCTIONS( + jit_avx512_core_bf16_conv_bwd_weights_kernel_f32) + + static status_t init_conf(jit_conv_conf_t &jcp, + const convolution_desc_t &cd, memory_desc_t &src_md, + memory_desc_t &diff_weights_md, memory_desc_t &diff_bias_md, + memory_desc_t &diff_dst_md, int nthreads); + static void init_scratchpad(memory_tracking::registrar_t &scratchpad, + const jit_conv_conf_t &jcp); + + const jit_conv_conf_t &jcp; + +private: + Xbyak::Label dst_prm_table; + // Used by compute_ic_block_step_{vpermw, interleave} + Xbyak::Opmask m_ffffffff = Xbyak::Opmask(1); + // Used by compute_ic_block_step_vpermw + Xbyak::Opmask m_0000ffff = Xbyak::Opmask(2); + Xbyak::Opmask m_ffff0000 = Xbyak::Opmask(3); + Xbyak::Opmask m_0000_oc_tail = Xbyak::Opmask(4); + Xbyak::Opmask m_oc_tail_0000 = Xbyak::Opmask(5); + Xbyak::Opmask m_0000_ic_tail = Xbyak::Opmask(6); + Xbyak::Opmask m_ic_tail_0000 = Xbyak::Opmask(7); + // Used by compute_ic_block_step_extern (1st_conv only) + Xbyak::Opmask everyother_mask = Xbyak::Opmask(6); + Xbyak::Opmask everyother_shift_mask = Xbyak::Opmask(7); + // Used by compute_ic_block_step_interleave (1st_conv only) + Xbyak::Opmask underflow_mask = Xbyak::Opmask(4); + Xbyak::Opmask overflow_mask = Xbyak::Opmask(5); + Xbyak::Opmask underflow_stride_mask = Xbyak::Opmask(6); + Xbyak::Opmask overflow_stride_mask = Xbyak::Opmask(7); + + using reg64_t = const Xbyak::Reg64; + enum { + sizeof_cacheline = 64, + full_spat_opt_working_set_size = 48 * 1024, + full_spat_max_working_set_size = 128 * 1024, + ker_code_size = 1024 * 1024, + }; + static const int max_ur_w; + + reg64_t param = abi_param1; + reg64_t reg_src = rax; + reg64_t reg_kernel = rdx; + reg64_t reg_ddst = rsi; + reg64_t b_ic = abi_not_param1; + reg64_t kj = r8; + reg64_t reg_kh = r9; + reg64_t reg_ur_w_trips = r10; + reg64_t reg_oj = r15; + reg64_t reg_tmp = r14; + reg64_t reg_ih_shift = reg_tmp; + reg64_t reg_long_offt = r14; + reg64_t reg_icb = rbx; + + reg64_t ki = r11; + reg64_t reg_oj_setup = r11; + reg64_t reg_kd_count = r12; + reg64_t reg_oi = r12; + reg64_t reg_d_index = r13; + reg64_t reg_src_d = r15; + reg64_t reg_ddst_d = rbx; + reg64_t aux_reg_src = r12; + reg64_t aux_reg_kernel = r13; + + Xbyak::Zmm vreg_bias_acc = Xbyak::Zmm(0); + Xbyak::Zmm vreg_bias_unit = Xbyak::Zmm(1); + Xbyak::Zmm vreg_bias_ddst = Xbyak::Zmm(2); + + Xbyak::Zmm one = Xbyak::Zmm(27); + Xbyak::Zmm even = Xbyak::Zmm(28); + Xbyak::Zmm selector = Xbyak::Zmm(29); + Xbyak::Zmm tmp0 = Xbyak::Zmm(30); + Xbyak::Zmm tmp1 = Xbyak::Zmm(31); + reg64_t scratch = r11; + + inline void maybe_zero_kernel(); + inline void get_ur_w(int &ur_w, int &ur_w_tail, int &ur_w_trips); + inline void compute_oh_step_unroll_ow_icblock(int ic_block_step); + inline void od_step_comeback_pointers(); + inline void oh_step_comeback_pointers(); + inline void compute_oh_step_unroll_ow(int ic_block_step); + inline void compute_ic_block_step(int ur_w, int pad_l, int pad_r, + int ic_block_step, int src_offset, int kernel_offset, + int ddst_offset, bool is_tail = false); + inline void compute_ic_block_step_extern(int ur_w, int pad_l, int pad_r, + int ic_block_step, int src_offset, int kernel_offset, + int ddst_offset, bool is_tail = false); + inline void compute_ic_block_step_interleave(int ur_w, int pad_l, int pad_r, + int ic_block_step, int src_offset, int kernel_offset, + int ddst_offset, bool is_tail = false); + inline void compute_ic_block_step_vpermw(int ur_w, int pad_l, int pad_r, + int ic_block_step, int src_offset, int kernel_offset, + int ddst_offset, bool is_tail = false); + inline void compute_oh_step_common(int ic_block_step); + inline void compute_oh_step_disp(); + inline void compute_loop(); + inline void compute_oh_loop_common(bool partial = false); + inline void compute_od_loop_common(bool partial = false); + void compute_full_spat_loop(); + void compute_diff_bias_init(); + void compute_diff_bias_row(bool is_partial = true); + void maybe_compute_diff_bias(); + void convert_src_to_vnni_format( + int ur_w, int pad_l, int pad_r, int src_offset); + void may_be_set_oc_tail_mask(); + void may_be_reset_oc_tail_mask(); + inline void compute_ic_block_step_vpermw_expl(int ur_w, int pad_l, + int pad_r, int ic_block_step, int src_offset, int kernel_offset, + int ddst_offset, bool is_tail = false); + inline bool is_src_layout_nxc() { + return jcp.uses_permw_transposition + && utils::one_of(jcp.src_tag, format_tag::ndhwc, + format_tag::nhwc, format_tag::nwc); + } + inline bool is_ddst_layout_nxc() { + return jcp.uses_permw_transposition + && utils::one_of(jcp.dst_tag, format_tag::ndhwc, + format_tag::nhwc, format_tag::nwc); + } + + void generate() override; + + static void balance(const jit_conv_conf_t &j, int &nthr, int &nthr_mb, + int &nthr_g, int &nthr_oc_b, int &nthr_ic_b); + + void get_w_positions(int ur_w, int pad_l, int pad_r, int i_ur, int i_kw, + int &iw_0, int &iw_1) { + auto get_w_position = [&](int idx) { + int iw = i_ur + idx; + if (iw >= ur_w) return -1; + iw += i_kw; + if (iw - pad_l < 0 || iw > (ur_w - 1) + (jcp.kw - 1) - pad_r) + return -1; + return iw - pad_l; + }; + iw_0 = get_w_position(0); + iw_1 = get_w_position(1); + } + bool check_borders(int ur_w, int pad_l, int pad_r, int i_ur, int i_kw) { + int iw_1, iw_2; + get_w_positions(ur_w, pad_l, pad_r, i_ur, i_kw, iw_1, iw_2); + + return (iw_1 == -1 && iw_2 == -1) ? false : true; + } + bool get_load_mask(int ur_w, int pad_l, int pad_r, int i_ur, int i_kw, + Xbyak::Opmask &load_mask) { + int iw_1, iw_2; + get_w_positions(ur_w, pad_l, pad_r, i_ur, i_kw, iw_1, iw_2); + + bool rt = true; + if (iw_1 != -1 && iw_2 != -1) + load_mask = m_ffffffff; + else if (iw_1 != -1 && iw_2 == -1) + load_mask = m_0000ffff; + else if (iw_1 == -1 && iw_2 != -1) + load_mask = m_ffff0000; + else + rt = false; + + return rt; + } + + inline dim_t filter_w_to_src(int kw, int ow = 0, int pad_l = 0) { + int stride_w = jcp.transpose_src ? 1 : jcp.stride_w; + return kw * (jcp.dilate_w + 1) + ow * stride_w - pad_l; + } + inline dim_t filter_h_to_src(int kh) { return kh * (jcp.dilate_h + 1); } + inline dim_t filter_d_to_src(int kd) { + return kd * (jcp.dilate_d + 1) * jcp.ih; + } + + inline dim_t get_src_offset(dim_t ic_idx, dim_t w_idx, dim_t hd_idx = 0) { + // For is_src_layout_nxc() the ic_idx index inside the block + // is supported only ic_idx == jcp.ic_block is considered as a shift + // within one block and not as moving to the next ic block. + assert(IMPLICATION(!is_src_layout_nxc(), ic_idx <= jcp.ic_block)); + dim_t icb = is_src_layout_nxc() ? ic_idx / jcp.ic_block : 0; + dim_t ic = is_src_layout_nxc() ? ic_idx % jcp.ic_block : ic_idx; + dim_t iw_str = jcp.is_1stconv || jcp.transpose_src + ? 1 + : (is_src_layout_nxc() ? jcp.ngroups * jcp.ic : jcp.ic_block); + dim_t ihid_str + = jcp.tr_iw * (jcp.transpose_src ? jcp.ic_block : iw_str); + // jcp.transpose_src w_idx might be greater than jcp.tr_iw as right zero + // padding memory is shared with left zero padding of the next block + dim_t isp_off = hd_idx * ihid_str + w_idx * iw_str; + dim_t full_spatial_size = (dim_t)jcp.tr_iw * jcp.ih * jcp.id; + dim_t ic_str = jcp.transpose_src + ? jcp.tr_iw + : (jcp.is_1stconv ? full_spatial_size : 1); + dim_t icb_str + = jcp.ic_block * (is_src_layout_nxc() ? 1 : full_spatial_size); + return jcp.typesize_in * (isp_off + icb_str * icb + ic_str * ic); + } + + inline dim_t get_ddst_offset(dim_t w_idx, dim_t hd_idx = 0) { + int ow_per_oc = jcp.transpose_dst ? 2 : 1; + int ch_mult + = is_ddst_layout_nxc() ? jcp.ngroups * jcp.oc : jcp.oc_block; + dim_t hd_off = jcp.tr_ow * ch_mult * hd_idx; + dim_t w_off + = w_idx / ow_per_oc * ow_per_oc * ch_mult + w_idx % ow_per_oc; + return jcp.typesize_in * (w_off + hd_off); + } + + inline dim_t get_kernel_offset(int ic_idx, dim_t ksp_idx) { + // Only the ic_idx index inside the block is supported, + // ic_idx == jcp.ic_block is considered as a shift inside one block + // and not as moving to the next ic block. + // Negative values are supported for negative shift. + assert(nstl::abs(ic_idx) <= jcp.ic_block); + return jcp.typesize_out * jcp.oc_block + * (ksp_idx * jcp.ic_block + ic_idx); + } + + Xbyak::Zmm get_perm_reg() { + int idx = !(jcp.uses_permw_transposition + && jcp.kernel_kind == expl_bcast) + ? 24 + : ((!isa_has_bf16(jcp.isa)) ? 26 : 31); + return Xbyak::Zmm(idx); + } + std::unique_ptr bf16_emu_; + + inline int interleave_w_reorder_size(int ur_w) const; + inline int interleave_w_reorder_bytes(int ur_w); + inline int interleave_stack_size(int ur_w, int ic_block_step); + inline int permw_stack_size(int ur_w) { + return (ur_w + jcp.kw - 1) * sizeof_cacheline; + } + + inline void setup_stack_space(); + static const int extern_ic_block_step_stack_size = 0; + int ic_block_step_stack_size = 0; + int stack_space_needed = 0; + int permw_buffer_start = 0; + int kd_count_offset = 0; + int src_d_offset = 0; + int ddst_d_offset = 0; + int d_index_offset = 0; + int trans_tmp_offset = 0; + int ih_dilate_shift = 0; + int icb_loop_ker_ptr = 0; + int icb_loop_src_ptr = 0; +}; +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_bf16_convolution.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_bf16_convolution.hpp new file mode 100644 index 0000000000000000000000000000000000000000..ad01130718f0e307ada55abe1f651542856dd735 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_bf16_convolution.hpp @@ -0,0 +1,271 @@ +/******************************************************************************* +* Copyright 2019-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_AVX512_CORE_BF16_CONVOLUTION_HPP +#define CPU_X64_JIT_AVX512_CORE_BF16_CONVOLUTION_HPP + +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/memory_tracking.hpp" +#include "common/primitive.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_convolution_pd.hpp" +#include "cpu/x64/cpu_barrier.hpp" +#include "cpu/x64/cpu_reducer.hpp" + +#include "cpu/x64/jit_avx512_core_bf16_conv_kernel.hpp" +#include "cpu/x64/jit_transpose_utils.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +struct jit_avx512_core_bf16_convolution_fwd_t : public primitive_t { + struct pd_t : public cpu_convolution_fwd_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const typename pd_t::base_class *hint_fwd_pd) + : cpu_convolution_fwd_pd_t(adesc, attr, hint_fwd_pd), jcp_() {} + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit_bf16:", jcp_.isa, ""), + jit_avx512_core_bf16_convolution_fwd_t); + + status_t init(engine_t *engine) { + using namespace data_type; + bool ok = mayiuse(avx512_core) && is_fwd() + && set_default_alg_kind(alg_kind::convolution_direct) + && (expect_data_types(bf16, bf16, data_type::undef, bf16, + data_type::undef) + || expect_data_types(bf16, bf16, data_type::undef, + f32, data_type::undef)) + && IMPLICATION(with_bias(), + utils::one_of(weights_md(1)->data_type, f32, bf16)) + && attr()->has_default_values( + primitive_attr_t::skip_mask_t::post_ops, + dst_md()->data_type) + && !has_zero_dim_memory(); + if (!ok) return status::unimplemented; + + CHECK(jit_avx512_core_bf16_fwd_kernel::init_conf(jcp_, *desc(), + src_md_, weights_md_, dst_md_, bias_md_, attr_, + dnnl_get_max_threads())); + + auto scratchpad = scratchpad_registry().registrar(); + jit_avx512_core_bf16_fwd_kernel::init_scratchpad(scratchpad, jcp_); + + return status::success; + } + + jit_conv_conf_t jcp_; + }; + + jit_avx512_core_bf16_convolution_fwd_t(const pd_t *apd) + : primitive_t(apd) {} + + typedef typename prec_traits::type src_data_t; + typedef typename prec_traits::type wei_data_t; + + status_t init(engine_t *engine) override { + CHECK(safe_ptr_assign(kernel_, + new jit_avx512_core_bf16_fwd_kernel( + pd()->jcp_, *pd()->attr(), *pd()->dst_md(0)))); + return kernel_->create_kernel(); + } + + status_t execute(const exec_ctx_t &ctx) const override { + if (pd()->ndims() == 3) + execute_forward_1d(ctx); + else if (pd()->ndims() == 4) + execute_forward_2d(ctx); + else if (pd()->ndims() == 5) + execute_forward_3d(ctx); + else + return status::unimplemented; + + if (pd()->wants_zero_pad_dst()) ctx.zero_pad_output(DNNL_ARG_DST); + return status::success; + } + +private: + void prepare_padded_bias(const char *&bias, + const memory_tracking::grantor_t &scratchpad) const; + void execute_forward_1d(const exec_ctx_t &ctx) const; + void execute_forward_2d(const exec_ctx_t &ctx) const; + void execute_forward_3d(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr kernel_; +}; + +struct jit_avx512_core_bf16_convolution_bwd_data_t : public primitive_t { + struct pd_t : public cpu_convolution_bwd_data_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const convolution_fwd_pd_t *hint_fwd_pd) + : cpu_convolution_bwd_data_pd_t(adesc, attr, hint_fwd_pd), jcp_() {} + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit_bf16:", jcp_.isa, ""), + jit_avx512_core_bf16_convolution_bwd_data_t); + + status_t init(engine_t *engine) { + using namespace prop_kind; + bool ok = true && mayiuse(avx512_core) && is_bwd_d() + && set_default_alg_kind(alg_kind::convolution_direct) + && (expect_data_types(data_type::f32, data_type::bf16, + data_type::undef, data_type::bf16, + data_type::undef) + || expect_data_types(data_type::bf16, + data_type::bf16, data_type::undef, + data_type::bf16, data_type::undef)) + && attr()->has_default_values() && !has_zero_dim_memory(); + if (!ok) return status::unimplemented; + + status_t status = jit_avx512_core_bf16_bwd_data_kernel::init_conf( + jcp_, *desc(), diff_src_md_, weights_md_, diff_dst_md_, + dnnl_get_max_threads()); + return status; + } + + jit_conv_conf_t jcp_; + }; + + jit_avx512_core_bf16_convolution_bwd_data_t(const pd_t *apd) + : primitive_t(apd) {} + + typedef typename prec_traits::type diff_dst_data_t; + typedef typename prec_traits::type wei_data_t; + + status_t init(engine_t *engine) override { + CHECK(safe_ptr_assign( + kernel_, new jit_avx512_core_bf16_bwd_data_kernel(pd()->jcp_))); + return kernel_->create_kernel(); + } + + status_t execute(const exec_ctx_t &ctx) const override { + if (pd()->ndims() < 5) + execute_backward_data(ctx); + else if (pd()->ndims() == 5) + execute_backward_data_3d(ctx); + else + assert(!"invalid dimension"); + + return status::success; + } + +private: + void execute_backward_data(const exec_ctx_t &ctx) const; + void execute_backward_data_3d(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + std::unique_ptr kernel_; +}; + +struct jit_avx512_core_bf16_convolution_bwd_weights_t : public primitive_t { + struct pd_t : public cpu_convolution_bwd_weights_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const convolution_fwd_pd_t *hint_fwd_pd) + : cpu_convolution_bwd_weights_pd_t(adesc, attr, hint_fwd_pd) + , jcp_() {} + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit_bf16:", jcp_.isa, ""), + jit_avx512_core_bf16_convolution_bwd_weights_t); + + status_t init(engine_t *engine) { + bool ok = true && mayiuse(avx512_core) && is_bwd_w() + && set_default_alg_kind(alg_kind::convolution_direct) + && (expect_data_types(data_type::bf16, data_type::bf16, + data_type::undef, data_type::bf16, + data_type::undef) + || expect_data_types(data_type::bf16, + data_type::f32, data_type::undef, + data_type::bf16, data_type::undef)) + && IMPLICATION(with_bias(), + utils::one_of(diff_bias_md_.data_type, + data_type::f32, data_type::bf16)) + && attr()->has_default_values() && !has_zero_dim_memory(); + if (!ok) return status::unimplemented; + + status_t status = jit_avx512_core_bf16_conv_bwd_weights_kernel_f32:: + init_conf(jcp_, *desc(), src_md_, diff_weights_md_, + diff_bias_md_, diff_dst_md_, + dnnl_get_max_threads()); + if (status != status::success) return status; + + auto scratchpad = scratchpad_registry().registrar(); + jit_avx512_core_bf16_conv_bwd_weights_kernel_f32::init_scratchpad( + scratchpad, jcp_); + + return status; + } + + jit_conv_conf_t jcp_; + }; + + jit_avx512_core_bf16_convolution_bwd_weights_t(const pd_t *apd) + : primitive_t(apd) {} + + typedef typename prec_traits::type src_data_t; + typedef typename prec_traits::type diff_dst_data_t; + + status_t init(engine_t *engine) override; + + status_t execute(const exec_ctx_t &ctx) const override { + execute_backward_weights(ctx); + return status::success; + } + +private: + void execute_backward_weights(const exec_ctx_t &ctx) const; + void prepare_scratchpad_data(const exec_ctx_t &ctx) const; + struct thread_info_t; + void compute_diff_weights_2d(const thread_info_t *) const; + void compute_diff_weights_3d(const thread_info_t *) const; + void compute_diff_weights(const thread_info_t *) const; + void reduce_and_convert_diff_weights_and_bias(const thread_info_t *) const; + + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + size_t tr_src_buf_number(const thread_info_t *ti, int g, int ic) const; + size_t tr_diff_dst_buf_number(const thread_info_t *ti, int g, int oc) const; + void trans_src( + src_data_t *tr_src1, const src_data_t *src1, int my_work) const; + void trans_dst(diff_dst_data_t *tr_diff_dst1, + const diff_dst_data_t *diff_dst1, int my_work) const; + void trans_src_nxc(src_data_t *tr_src, const src_data_t *src_base, + int spatial_start, dim_t spatial_start_offset, int icb_start, + dim_t chb_stride, int my_work) const; + void trans_dst_nxc(diff_dst_data_t *tr_diff_dst, + const diff_dst_data_t *diff_dst_base, int spatial_start, + dim_t spatial_start_offset, int ocb_start, dim_t chb_stride, + int my_work) const; + + int nthr_ = 0, nthr_mb_ = 0, nthr_g_ = 0, nthr_oc_b_ = 0, nthr_ic_b_ = 0; + + std::unique_ptr kernel_; + + std::unique_ptr> acc_ker_; + + std::unique_ptr trans_kernel_; + std::unique_ptr trans_dst_kernel_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_bf16_dw_conv_kernel.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_bf16_dw_conv_kernel.hpp new file mode 100644 index 0000000000000000000000000000000000000000..7ec11eeed79c68a4997b01fe8f282d2e5d65be20 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_bf16_dw_conv_kernel.hpp @@ -0,0 +1,334 @@ +/******************************************************************************* +* Copyright 2019-2021 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_AVX512_CORE_BF16_DW_CONV_KERNEL_HPP +#define CPU_X64_JIT_AVX512_CORE_BF16_DW_CONV_KERNEL_HPP + +#include "common/c_types_map.hpp" +#include "common/memory_tracking.hpp" + +#include "cpu/x64/injectors/jit_uni_postops_injector.hpp" +#include "cpu/x64/jit_generator.hpp" +#include "cpu/x64/jit_primitive_conf.hpp" + +#include "cpu/x64/jit_avx512_core_bf16cvt.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +struct jit_avx512_dw_conv_fwd_kernel_bf16 : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_dw_conv_fwd_kernel_bf16) + + jit_avx512_dw_conv_fwd_kernel_bf16( + const jit_conv_conf_t &ajcp, const memory_desc_t &dst_md); + + jit_conv_conf_t jcp; + +private: + using reg64_t = const Xbyak::Reg64; + using mask_t = const Xbyak::Opmask; + const Xbyak::AddressFrame &vmmword = zword; + + const int acc_idx_start = 2; + inline int get_max_regs() const { return isa_has_bf16(jcp.isa) ? 30 : 25; }; + + // dw convolution + reg64_t reg_input = r8; + reg64_t aux_reg_input = r9; + reg64_t reg_kernel = r10; + reg64_t aux_reg_kernel = r11; + reg64_t reg_ch_blocks = r12; + reg64_t reg_output = r13; + reg64_t reg_bias = r14; + reg64_t reg_kh = r15; + reg64_t iter_kh = rax; + reg64_t reg_oi = rbx; + + reg64_t reg_tmp = reg_ch_blocks; + + // fused convolution + reg64_t reg_input_buffer_ptr = rdx; + reg64_t aux_reg_input_buffer_ptr = rsi; + reg64_t reg_iw_offset = reg_input; //Hack: clear reg_input early in kernel + reg64_t reg_tail = rax; + mask_t k_oc_tail_mask = Xbyak::Opmask(2); + mask_t ktail_mask = k_oc_tail_mask; + mask_t k_ch_tail_mask_extended = Xbyak::Opmask(3); + + Xbyak::Zmm zmm_ker_reg = Xbyak::Zmm(0); + Xbyak::Zmm zmm_src_reg = Xbyak::Zmm(1); + Xbyak::Zmm zmm_prev_dst = Xbyak::Zmm(31); + + /* Registers used for bfloat16 emulation */ + Xbyak::Zmm bf16_emu_reserv_1 = Xbyak::Zmm(26); + Xbyak::Zmm bf16_emu_reserv_2 = Xbyak::Zmm(27); + Xbyak::Zmm bf16_emu_reserv_3 = Xbyak::Zmm(28); + reg64_t bf16_emu_reserv_4 = abi_not_param1; + Xbyak::Zmm bf16_emu_reserv_5 = Xbyak::Zmm(29); + Xbyak::Zmm bf16_emu_reserv_6 = Xbyak::Zmm(30); + + int get_acc_reg_idx(int idx) const; + + Xbyak::Zmm get_acc_reg(int idx); + + int get_ow_start(int ki, int pad_l) { + return nstl::max(0, + utils::div_up(pad_l - ki * (jcp.dilate_w + 1), jcp.stride_w)); + } + + int get_ow_end(int ur_w, int ki, int pad_r) { + return ur_w + - nstl::max(0, + utils::div_up( + pad_r - (jcp.kw - 1 - ki) * (jcp.dilate_w + 1), + jcp.stride_w)); + } + + inline bool is_src_layout_nxc() { + return utils::one_of(jcp.src_tag, format_tag::ndhwc, format_tag::nhwc, + format_tag::nwc); + } + + inline bool is_dst_layout_nxc() { + return utils::one_of(jcp.dst_tag, format_tag::ndhwc, format_tag::nhwc, + format_tag::nwc); + } + + inline void load_src(int ur_ch_blocks, int ur_w, bool last_ch_block_flag); + inline void compute_loop(int ur_w, int ur_ch_blocks, int pad_l, int pad_r); + inline void loop_ow(int ur_ch_blocks); + inline void apply_filter_unrolled(int ur_ch_blocks, int ur_w, int pad_l, + int pad_r, bool last_ch_block_flag); + inline void apply_postops( + int ur_ch_blocks, int ur_w, bool last_ch_block_flag); + inline void store_dst(int ur_ch_blocks, int ur_w, bool last_ch_block_flag); + + std::unique_ptr> + postops_injector_; + + std::unique_ptr bf16_emu_; + + void generate() override; +}; + +struct jit_avx512_dw_conv_bwd_data_kernel_bf16 : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_dw_conv_bwd_data_kernel_bf16) + + jit_avx512_dw_conv_bwd_data_kernel_bf16(const jit_conv_conf_t &ajcp) + : jit_generator(jit_name()), jcp(ajcp), bf16_emu_(nullptr) { + + if (!isa_has_bf16(jcp.isa)) + bf16_emu_ = new bf16_emulation_t(this, bf16_emu_reserv_1, + bf16_emu_reserv_2, bf16_emu_reserv_3, bf16_emu_reserv_4, + bf16_emu_reserv_5, bf16_emu_reserv_6); + } + + ~jit_avx512_dw_conv_bwd_data_kernel_bf16() { delete bf16_emu_; } + + jit_conv_conf_t jcp; + +private: + using reg64_t = const Xbyak::Reg64; + + const int acc_idx_start = 2; + inline int get_max_regs() { return isa_has_bf16(jcp.isa) ? 30 : 25; }; + + Xbyak::Zmm zmm_ker_reg = Xbyak::Zmm(0); + Xbyak::Zmm zmm_dst_reg = Xbyak::Zmm(1); + + inline Xbyak::Zmm get_acc_reg(int idx) { + assert(idx + acc_idx_start <= get_max_regs()); + return Xbyak::Zmm(idx + acc_idx_start); + } + + reg64_t reg_ddst = rax; + reg64_t aux_reg_ddst = r8; + reg64_t aux1_reg_ddst = abi_not_param1; + reg64_t reg_kernel = rdx; + reg64_t aux_reg_kernel = r10; + reg64_t aux1_reg_kernel = rbp; + reg64_t reg_dsrc = rsi; + + reg64_t reg_ur_str_w = r9; + reg64_t reg_ch_blocks = rbx; + + reg64_t iter_kh = r11; + reg64_t iter_kw = r12; + reg64_t reg_kh = r13; + reg64_t reg_kw = r14; + + reg64_t aux_reg_ch_blocks = r15; + reg64_t reg_tmp = r15; + Xbyak::Opmask k_ch_tail_mask = Xbyak::Opmask(1); + + Xbyak::Zmm bf16_emu_reserv_1 = Xbyak::Zmm(26); + Xbyak::Zmm bf16_emu_reserv_2 = Xbyak::Zmm(27); + Xbyak::Zmm bf16_emu_reserv_3 = Xbyak::Zmm(28); + reg64_t bf16_emu_reserv_4 = iter_kw; + Xbyak::Zmm bf16_emu_reserv_5 = Xbyak::Zmm(29); + Xbyak::Zmm bf16_emu_reserv_6 = Xbyak::Zmm(30); + + bf16_emulation_t *bf16_emu_; + + inline void ch_loop_body(int ur_ch_blocks, int unroll_w); + inline void unroll_width_body(int ur_ch_blocks); + inline void load_ddst(int ur_ch_blocks, int ur_str_w); + inline void apply_filter(int ur_ch_blocks, int ur_str_w, bool is_last_ch); + inline void store_dsrc(int ur_ch_blocks, int ur_str_w, bool is_last_ch); + + void generate() override; + inline bool is_dsrc_layout_nxc() { + return utils::one_of(jcp.src_tag, format_tag::ndhwc, format_tag::nhwc, + format_tag::nwc); + } + inline bool is_ddst_layout_nxc() { + return utils::one_of(jcp.dst_tag, format_tag::ndhwc, format_tag::nhwc, + format_tag::nwc); + } +}; + +struct jit_avx512_dw_conv_bwd_weights_kernel_bf16 : public jit_generator { + + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_dw_conv_bwd_weights_kernel_bf16) + + jit_avx512_dw_conv_bwd_weights_kernel_bf16(const jit_conv_conf_t &ajcp) + : jit_generator(jit_name()), jcp(ajcp), bf16_emu_(nullptr) { + + if (!isa_has_bf16(jcp.isa)) + bf16_emu_ = new bf16_emulation_t(this, bf16_emu_reserv_1, + bf16_emu_reserv_2, bf16_emu_reserv_3, bf16_emu_reserv_4, + bf16_emu_reserv_5, bf16_emu_reserv_6); + } + + ~jit_avx512_dw_conv_bwd_weights_kernel_bf16() { delete bf16_emu_; } + + jit_conv_conf_t jcp; + +private: + using reg64_t = const Xbyak::Reg64; + const Xbyak::AddressFrame &vmmword = zword; + + const int max_unroll_w_ = 30; + const int block_size_ = 15; + + const int idx_start = 2; + inline int get_max_regs() const { return isa_has_bf16(jcp.isa) ? 30 : 25; }; + + /* Offset between input and accummulators is 3, therefore, assume 'kw' + * is no larger than 3*/ + Xbyak::Zmm zmm_bias_reg = Xbyak::Zmm(0); + Xbyak::Zmm zmm_out_reg = Xbyak::Zmm(1); + + inline Xbyak::Zmm get_acc_reg(int idx) { + assert(idx + idx_start <= get_max_regs()); + return Xbyak::Zmm(idx + idx_start); + } + inline Xbyak::Zmm get_input_reg(int idx) { + const int i_idx = idx_start + jcp.kw + idx % jcp.kw; + assert(i_idx <= get_max_regs()); + return Xbyak::Zmm(i_idx); + } + + reg64_t reg_tmp_input = r9; + reg64_t reg_tmp_output = r10; + reg64_t reg_tmp_filter = r13; + reg64_t reg_kh_offset = rax; + + /* parameter passed by driver into kernel */ + Xbyak::Reg8 reg_exec_flags = bl; + reg64_t reg_oh_worksize = r14; + reg64_t reg_oh = rax; + reg64_t reg_iter_ow_blk = r11; + reg64_t reg_kh_aux = rsi; + reg64_t reg_kh = rdx; + + /* Base addresses for convolution parameters. */ + reg64_t reg_input_baddr = r15; + reg64_t reg_output_baddr = r12; + reg64_t reg_filter_baddr = abi_not_param1; + reg64_t reg_bias_baddr = r13; + + reg64_t reg_tmp = r8; + + Xbyak::Opmask k_ch_tail_mask = Xbyak::Opmask(1); + + /* Registers used for bfloat16 emulation */ + Xbyak::Zmm bf16_emu_reserv_1 = Xbyak::Zmm(26); + Xbyak::Zmm bf16_emu_reserv_2 = Xbyak::Zmm(27); + Xbyak::Zmm bf16_emu_reserv_3 = Xbyak::Zmm(28); + reg64_t bf16_emu_reserv_4 = r8; + Xbyak::Zmm bf16_emu_reserv_5 = Xbyak::Zmm(29); + Xbyak::Zmm bf16_emu_reserv_6 = Xbyak::Zmm(30); + + bf16_emulation_t *bf16_emu_; + + /* Micro-kernel JIT'ing, fusing 'kw' and 'ow_block' loops into unrolled FMAs + */ + void compute_ow_step_unroll(int unroll_w, int l_pad, int pad_offset, + int ow_block, bool is_last_ch); + + /* JIT'ing the outer loops for the micro-kernel -> {kh, oh_block} */ + void compute_kh_step(int unroll_w, int l_pad, int pad_offset, int ow_block, + bool is_last_ch); + /* Channel loop for 'nxc' format */ + void compute_ch_loop(int unroll_w, int l_pad, int pad_offset, int ow_block); + void compute_h_loop(int unroll_w, int l_pad, int pad_offset, int ow_block); + + /* Write 'width' micro-kernel JITs; depending on the padding and convolution + * size, write a micro-kernel for the left ow-block, middle ow-block(s), and + * right ow-block.*/ + void compute_ow_block_unroll(); + void deploy_zero_filter(); + void zero_filter_kh_loop(); + void load_filter(bool is_last_ch = false); + void zero_filter(); + void load_bias(bool is_last_ch); + void zero_bias(); + void compute_bias_step_unroll(const int unroll_w, bool is_last_ch); + void compute_ch_loop_bias(bool do_load_bias); + void deploy_ch_loop_bias(); + void compute_single_ch_block_bias(); + void compute_spatial_loop_bias(bool is_last_ch); + void store_filter(bool is_last_ch = false); + void store_bias(bool is_last_ch); + void compute_bias(); + void calculate_w_unrolling( + int &unroll_trips, int &unroll_w, int &unroll_w_tail); + + void generate() override; + + inline bool is_layout_nxc() { + return utils::everyone_is( + true, is_src_layout_nxc(), is_ddst_layout_nxc()); + } + inline bool is_src_layout_nxc() { + return utils::one_of(jcp.src_tag, format_tag::ndhwc, format_tag::nhwc, + format_tag::nwc); + } + inline bool is_ddst_layout_nxc() { + return utils::one_of(jcp.dst_tag, format_tag::ndhwc, format_tag::nhwc, + format_tag::nwc); + } +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif /* JIT_UNI_DW_CONV_KERNEL_BF16_HPP */ diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_bf16cvt.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_bf16cvt.hpp new file mode 100644 index 0000000000000000000000000000000000000000..65f9b04963240c0f59ad1dc4bced4105c5141e1f --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_bf16cvt.hpp @@ -0,0 +1,406 @@ +/******************************************************************************* +* Copyright 2019-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_AVX512_CORE_BF16CVT_HPP +#define CPU_X64_JIT_AVX512_CORE_BF16CVT_HPP + +#include + +#include "common/c_types_map.hpp" +#include "common/nstl.hpp" +#include "common/type_helpers.hpp" +#include "cpu/x64/cpu_isa_traits.hpp" +#include "oneapi/dnnl/dnnl_debug.h" + +#include "common/bfloat16.hpp" +#include "cpu/x64/jit_generator.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +namespace bf16_support { +struct jit_call_t { + void *inp; + void *out; + void *add; + size_t nelems; + int mask; +}; +} // namespace bf16_support + +#define GET_OFF(field) offsetof(bf16_support::jit_call_t, field) + +struct bf16_emulation_t { + using opmask_t = const Xbyak::Opmask; + using Zmm_t = const Xbyak::Zmm; + using Ymm_t = const Xbyak::Ymm; + using Xmm_t = const Xbyak::Xmm; + using reg64_t = const Xbyak::Reg64; + + bf16_emulation_t(jit_generator *host, Zmm_t one, Zmm_t even, Zmm_t selector, + reg64_t scratch, Zmm_t tr0, Zmm_t tr1) + : host_(host) + , one_(one) + , even_(even) + , selector_(selector) + , scratch_(scratch) + , tr0_(tr0) + , tr1_(tr1) {} + + bf16_emulation_t(jit_generator *host, Zmm_t one, Zmm_t even, Zmm_t selector, + reg64_t scratch, Zmm_t tr0) + : bf16_emulation_t(host, one, even, selector, scratch, tr0, tr0) {} + + void vdpbf16ps(Zmm_t &acc, Zmm_t wei, Zmm_t inp) { + host_->vpsrad(tr0_, wei, 16); + host_->vpslld(tr0_, tr0_, 16); + + host_->vpsrad(tr1_, inp, 16); + host_->vpslld(tr1_, tr1_, 16); + + host_->vfmadd231ps(acc, tr1_, tr0_); + + host_->vpslld(tr0_, wei, 16); + host_->vpslld(tr1_, inp, 16); + + host_->vfmadd231ps(acc, tr1_, tr0_); + } + + void vcvtneps2bf16(Xmm_t &out, Xmm_t &in) { + const bool input_is_zmm = in.isZMM() && out.isYMM(); + const bool input_is_ymm = in.isYMM() && out.isXMM(); + assert((input_is_zmm || input_is_ymm) + && "Incorrect usage of vcvtneps2bf16 instruction."); + + if (input_is_zmm) + vcvtneps2bf16(out, in, tr0_, one_, even_, selector_); + else if (input_is_ymm) { + const Ymm_t tr0_y {tr0_.getIdx()}; + const Ymm_t even_y {even_.getIdx()}; + const Ymm_t selector_y {selector_.getIdx()}; + const Ymm_t one_y {one_.getIdx()}; + + vcvtneps2bf16(out, in, tr0_y, one_y, even_y, selector_y); + } + } + +private: + void vcvtneps2bf16(const Xbyak::Operand &out, const Xmm_t &in, + const Xmm_t &tr0, const Xbyak::Operand &one, const Xmm_t &even, + const Xbyak::Operand &selector) { + host_->vpsrld(tr0, in, 16); + host_->vpandd(tr0, tr0, one); + + host_->vpaddd(tr0, even, tr0); + + host_->vpaddd(tr0, in, tr0); + host_->vfixupimmps(tr0, in, selector, 0); + + host_->vpsrad(tr0, tr0, 16); + host_->vpmovdw(out, tr0); + } + +public: + void init_vcvtneps2bf16() { + const int selector_int32 = + /* qnan input to qnan output (presenrving input bits 0..21) */ + encode_fixup_selector( + fixup_input_code_snan, fixup_output_code_qnan_input) + | + /* snan input to qnan output (presenrving input bits 0..21) */ + encode_fixup_selector( + fixup_input_code_qnan, fixup_output_code_qnan_input) + | + /* neg inf input copied to output */ + encode_fixup_selector( + fixup_input_code_ninf, fixup_output_code_copy_input) + | + /* pos inf input copied to output */ + encode_fixup_selector( + fixup_input_code_pinf, fixup_output_code_copy_input); + + host_->xor_(scratch_, scratch_); + host_->mov(scratch_.cvt32(), 0x1); + host_->vpbroadcastd(one_, scratch_.cvt32()); + + host_->xor_(scratch_, scratch_); + host_->mov(scratch_.cvt32(), 0x7fff); + host_->vpbroadcastd(even_, scratch_.cvt32()); + + host_->xor_(scratch_, scratch_); + host_->mov(scratch_.cvt32(), selector_int32); + host_->vpbroadcastd(selector_, scratch_.cvt32()); + } + + static cpu_isa_t get_isa() { return avx512_core; } + +private: + jit_generator *const host_; + Zmm_t one_; + Zmm_t even_; + Zmm_t selector_; + reg64_t scratch_; + Zmm_t tr0_; + Zmm_t tr1_; + + int encode_fixup_selector(int input, int output) { + return ((output) << (4 * (input))); + } + + enum { + fixup_input_code_qnan = 0, + fixup_input_code_snan = 1, + fixup_input_code_ninf = 4, + fixup_input_code_pinf = 5, + fixup_output_code_copy_input = 1, + fixup_output_code_qnan_input = 2, + }; +}; + +// performs element-by-element sum of inp and add float arrays and stores +// result to bfloat16 out array with downconversion +struct jit_avx512_core_add_cvt_ps_to_bf16_t : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_add_cvt_ps_to_bf16) + + jit_avx512_core_add_cvt_ps_to_bf16_t() + : jit_generator(jit_name()), simd_w_(16) { + bf16_emu_ = new bf16_emulation_t( + this, one, even, selector, scratch, fp32_tmp, fp32_tmp); + + UNUSED_STATUS(create_kernel()); + } + + ~jit_avx512_core_add_cvt_ps_to_bf16_t() { delete bf16_emu_; } + + void generate() override { + preamble(); + + bool use_bf16_emu = !mayiuse(avx512_core_bf16); + + auto add_cvt = [&](size_t idx, Xbyak::Opmask ktail_mask) { + vmovups(fp32_inp | ktail_mask | T_z, + ptr[reg_inp + sizeof(float) * (idx)]); + vaddps(fp32_inp | ktail_mask | T_z, fp32_inp, + ptr[reg_add + sizeof(float) * (idx)]); + if (use_bf16_emu) + bf16_emu_->vcvtneps2bf16(bf16_out, fp32_inp); + else + vcvtneps2bf16(bf16_out, fp32_inp); + + vmovdqu16(yword[reg_out + sizeof(bfloat16_t) * (idx)] | ktail_mask, + bf16_out); + }; + + mov(reg_inp, ptr[abi_param1 + GET_OFF(inp)]); + mov(reg_add, ptr[abi_param1 + GET_OFF(add)]); + mov(reg_out, ptr[abi_param1 + GET_OFF(out)]); + mov(reg_nelems, ptr[abi_param1 + GET_OFF(nelems)]); + + if (use_bf16_emu) bf16_emu_->init_vcvtneps2bf16(); + + mov(reg32_tail, 0xffff); + kmovw(ktail_mask, reg32_tail); + + constexpr int n_unroll = 2; // unroll by powers of 2 from 2^n to 2^0 + Xbyak::Label l_simd_loop[n_unroll + 2], l_simd_notail; + for (int i = n_unroll; i >= 0; i--) { + const int unroll = 1 << i; // 4, 2, 1 + L(l_simd_loop[i + 1]); + { + cmp(reg_nelems, simd_w_ * unroll); + jl(l_simd_loop[i], T_NEAR); + for (int j = 0; j < simd_w_ * unroll; j += simd_w_) { + add_cvt(j, ktail_mask); + } + add(reg_inp, simd_w_ * unroll * sizeof(float)); + add(reg_add, simd_w_ * unroll * sizeof(float)); + add(reg_out, simd_w_ * unroll * sizeof(bfloat16_t)); + + sub(reg_nelems, simd_w_ * unroll); + jmp(l_simd_loop[i + 1], T_NEAR); + } + } + L(l_simd_loop[0]); + test(reg_nelems, reg_nelems); + jz(l_simd_notail); + // JIT of `tail_mask_ = (1 << (nelems_ % simd_w_)) - 1;` + mov(reg32_mask, 1); + mov(reg64_tail, reg_nelems); + shl(reg32_mask, reg8_mask_shift); + sub(reg32_mask, 1); + kmovd(ktail_mask, reg32_mask); + add_cvt(0, ktail_mask); + L(l_simd_notail); + + postamble(); + } + + void operator()(bf16_support::jit_call_t *params) const { + jit_generator::operator()(params); + msan_unpoison(params->out, params->nelems * sizeof(bfloat16_t)); + } + +private: + int simd_w_; + + bf16_emulation_t *bf16_emu_; + + Xbyak::Opmask ktail_mask = k2; + Xbyak::Zmm fp32_inp = Xbyak::Zmm(0); + Xbyak::Zmm fp32_tmp = Xbyak::Zmm(1); + + Xbyak::Zmm one = Xbyak::Zmm(2); + Xbyak::Zmm even = Xbyak::Zmm(3); + Xbyak::Zmm selector = Xbyak::Zmm(4); + Xbyak::Reg64 scratch = r15; + + Xbyak::Ymm bf16_out = Xbyak::Ymm(5); + + Xbyak::Reg64 reg_inp = rax; + Xbyak::Reg64 reg_out = rbx; + Xbyak::Reg64 reg_add = r11; + Xbyak::Reg64 reg_nelems = rdx; + + Xbyak::Reg64 reg64_tail = rcx; + Xbyak::Reg32 reg32_tail = ecx; + Xbyak::Reg8 reg8_mask_shift = cl; + Xbyak::Reg32 reg32_mask = r8d; +}; + +// implementation of reorder of part of tensor [s][16c] -> [S][16c][2s] +// it is required for quick implementation of 1x1 bf16 bwd_w jit kernel +// w/o using permw instruction inside +// TODO: consider modification/replacement for outer transformation jit kernel +struct jit_avx512_core_bf16_reorder_s16c_to_S16c2s_t : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_bf16_reorder_s16c_to_S16c2s) + + jit_avx512_core_bf16_reorder_s16c_to_S16c2s_t() + : jit_generator(jit_name()), simd_w_(16), in_stride_(16) {} + + jit_avx512_core_bf16_reorder_s16c_to_S16c2s_t(int in_stride) + : jit_generator(jit_name()), simd_w_(16), in_stride_(in_stride) {} + + ~jit_avx512_core_bf16_reorder_s16c_to_S16c2s_t() {} + + void generate() override { + preamble(); + + mov(reg32_tail, ptr[abi_param1 + GET_OFF(mask)]); + mov(reg_inp, ptr[abi_param1 + GET_OFF(inp)]); + mov(reg_out, ptr[abi_param1 + GET_OFF(out)]); + mov(reg_nelems, ptr[abi_param1 + GET_OFF(nelems)]); + + auto zmm_reg = [=](int idx) { + assert(idx < 31); + return Xbyak::Zmm(idx); + }; + + kmovd(ktail_mask_lo, reg32_tail); + kshiftld(ktail_mask_hi, ktail_mask_lo, 16); + + Xbyak::Label dst_prm_table; + mov(reg_prm, dst_prm_table); + vmovups(zmm_prm, ptr[reg_prm]); + + constexpr int n_unroll = 2; // unroll by powers of 2 from 2^n to 2^0 + int sizeofcacheline = 2 * simd_w_ * sizeof(bfloat16_t); + int in_stride_bytes = in_stride_ * sizeof(bfloat16_t); + Xbyak::Label l_simd_loop[n_unroll + 2], l_simd_notail; + for (int i = n_unroll; i >= 0; i--) { + const int unroll = 1 << i; // 4, 2, 1 + L(l_simd_loop[i + 1]); + { + cmp(reg_nelems, 2 * unroll); + jl(l_simd_loop[i], T_NEAR); + for (int j = 0; j < unroll; j++) { + auto zmm_inp = zmm_reg(j); + if (in_stride_ == 16) + vmovups(zmm_inp, zword[reg_inp + j * sizeofcacheline]); + else { + vmovdqu16(zmm_inp | ktail_mask_lo | T_z, + zword[reg_inp + 2 * j * in_stride_bytes]); + vmovdqu16(zmm_inp | ktail_mask_hi, + zword[reg_inp + (2 * j + 1) * in_stride_bytes + - 32]); + } + vpermw(zmm_inp, zmm_prm, zmm_inp); + vmovups(zword[reg_out + j * sizeofcacheline], zmm_inp); + } + add(reg_inp, + unroll + * (in_stride_ == 16 ? sizeofcacheline + : 2 * in_stride_bytes)); + add(reg_out, unroll * sizeofcacheline); + + sub(reg_nelems, 2 * unroll); + jmp(l_simd_loop[i + 1], T_NEAR); + } + } + L(l_simd_loop[0]); + + test(reg_nelems, reg_nelems); + jz(l_simd_notail); + + auto zmm_inp = zmm_reg(0); + vpxord(zmm_inp, zmm_inp, zmm_inp); + vmovdqu16(zmm_inp | ktail_mask_lo | T_z, ptr[reg_inp]); + vpermw(zmm_inp, zmm_prm, zmm_inp); + vmovups(zword[reg_out], zmm_inp); + + L(l_simd_notail); + + postamble(); + + const uint16_t dst_prm_array[32] = {0, 16, 1, 17, 2, 18, 3, 19, 4, 20, + 5, 21, 6, 22, 7, 23, 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, + 29, 14, 30, 15, 31}; + + align(64); + L(dst_prm_table); + for (size_t i = 0; i < 32; ++i) + dw(dst_prm_array[i]); + } + + void operator()(bf16_support::jit_call_t *params) const { + jit_generator::operator()(params); + msan_unpoison(params->out, params->nelems * sizeof(bfloat16_t)); + } + +private: + int simd_w_; + int in_stride_; + + Xbyak::Opmask ktail_mask_lo = k2; + Xbyak::Opmask ktail_mask_hi = k3; + Xbyak::Zmm zmm_prm = Xbyak::Zmm(31); + + Xbyak::Reg64 reg_inp = rax; + Xbyak::Reg64 reg_out = rbx; + Xbyak::Reg64 reg_prm = r11; + Xbyak::Reg64 reg_nelems = rdx; + + Xbyak::Reg32 reg32_tail = abi_not_param1.cvt32(); +}; + +#undef GET_OFF +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_fp16cvt.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_fp16cvt.hpp new file mode 100644 index 0000000000000000000000000000000000000000..e61433f438392d23207593c87ddf8dc8e73e66ee --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_fp16cvt.hpp @@ -0,0 +1,93 @@ +/******************************************************************************* +* Copyright 2022 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_AVX512_CORE_FP16CVT_HPP +#define CPU_X64_JIT_AVX512_CORE_FP16CVT_HPP + +#include + +#include "common/c_types_map.hpp" +#include "common/float16.hpp" +#include "common/nstl.hpp" +#include "common/type_helpers.hpp" + +#include "cpu/x64/cpu_isa_traits.hpp" +#include "cpu/x64/jit_generator.hpp" + +#include "oneapi/dnnl/dnnl_debug.h" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +namespace f16_support { +struct jit_call_t { + void *inp; + void *out; + void *add; + size_t nelems; +}; +} // namespace f16_support + +// performs element-by-element sum of inp and add float arrays and stores +// result to float16 out array with downconversion +struct jit_avx512_core_fp16_add_cvt_ps_to_f16_t : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_add_cvt_ps_to_f16) + + jit_avx512_core_fp16_add_cvt_ps_to_f16_t() + : jit_generator(jit_name()), simd_w_(16) { + create_kernel(); + } + + void generate() override; + + void operator()(f16_support::jit_call_t *params) const { + jit_generator::operator()(params); + msan_unpoison(params->out, params->nelems * sizeof(float16_t)); + } + +private: + int simd_w_; + + Xbyak::Opmask ktail_mask = k2; + Xbyak::Zmm fp32_inp = Xbyak::Zmm(0); + Xbyak::Zmm fp32_tmp = Xbyak::Zmm(1); + + Xbyak::Zmm one = Xbyak::Zmm(2); + Xbyak::Zmm even = Xbyak::Zmm(3); + Xbyak::Zmm selector = Xbyak::Zmm(4); + Xbyak::Reg64 scratch = r15; + + Xbyak::Ymm f16_out = Xbyak::Ymm(5); + + Xbyak::Reg64 reg_inp = rax; + Xbyak::Reg64 reg_out = rbx; + Xbyak::Reg64 reg_add = r11; + Xbyak::Reg64 reg_nelems = rdx; + + Xbyak::Reg64 reg64_tail = rcx; + Xbyak::Reg32 reg32_tail = ecx; + Xbyak::Reg8 reg8_mask_shift = cl; + Xbyak::Reg32 reg32_mask = r8d; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_resampling.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_resampling.hpp new file mode 100644 index 0000000000000000000000000000000000000000..2c1e30fbe1a456af336d791e6f92bb755be4a7d1 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_resampling.hpp @@ -0,0 +1,74 @@ +/******************************************************************************* +* Copyright 2020-2022 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_AVX512_CORE_RESAMPLING_HPP +#define CPU_X64_JIT_AVX512_CORE_RESAMPLING_HPP + +#include "common/c_types_map.hpp" +#include "common/primitive.hpp" + +#include "cpu/cpu_resampling_pd.hpp" +#include "cpu/x64/cpu_isa_traits.hpp" + +#include "cpu/x64/jit_generator.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +struct jit_resampling_args_t; + +struct jit_avx512_core_resampling_kernel_base_t : public jit_generator { + jit_avx512_core_resampling_kernel_base_t( + const resampling_pd_t *pd, const char *name); + virtual ~jit_avx512_core_resampling_kernel_base_t() = default; + +protected: + const resampling_pd_t *pd_; + + data_type_t src_data_type() const; + data_type_t dst_data_type() const; +}; + +struct jit_avx512_core_resampling_bwd_t : public primitive_t { + struct pd_t : public cpu_resampling_bwd_pd_t { + using cpu_resampling_bwd_pd_t::cpu_resampling_bwd_pd_t; + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit:", avx512_core, ""), + jit_avx512_core_resampling_bwd_t); + + status_t init(engine_t *engine); + }; + + jit_avx512_core_resampling_bwd_t(const pd_t *apd) : primitive_t(apd) {} + ~jit_avx512_core_resampling_bwd_t(); + + status_t init(engine_t *engine) override; + + status_t execute(const exec_ctx_t &ctx) const override; + +private: + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + std::unique_ptr kernel_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_x8s8s32x_1x1_conv_kernel.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_x8s8s32x_1x1_conv_kernel.hpp new file mode 100644 index 0000000000000000000000000000000000000000..044cca678edbab1bda36614bb6a8612c5ebc7c0b --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_x8s8s32x_1x1_conv_kernel.hpp @@ -0,0 +1,201 @@ +/******************************************************************************* +* Copyright 2018-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_AVX512_CORE_X8S8S32X_1X1_CONV_KERNEL_HPP +#define CPU_X64_JIT_AVX512_CORE_X8S8S32X_1X1_CONV_KERNEL_HPP + +#include "common/c_types_map.hpp" +#include "common/memory_tracking.hpp" + +#include "cpu/x64/injectors/jit_uni_postops_injector.hpp" +#include "cpu/x64/jit_avx512_core_bf16cvt.hpp" +#include "cpu/x64/jit_generator.hpp" +#include "cpu/x64/jit_primitive_conf.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +template +struct _jit_avx512_core_x8s8s32x_1x1_conv_kernel : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(_jit_avx512_core_x8s8s32x_1x1_conv_fwd_ker_t) + _jit_avx512_core_x8s8s32x_1x1_conv_kernel(const jit_1x1_conv_conf_t &ajcp, + const primitive_attr_t &attr, const memory_desc_t &dst_md); + + jit_1x1_conv_conf_t jcp; + const primitive_attr_t &attr_; + +private: + constexpr static int isa_simd_width_ + = cpu_isa_traits::vlen / sizeof(float); + using Vmm_down_t = + typename utils::conditional::value, + Xbyak::Ymm, Xbyak::Xmm>::type; + std::unique_ptr> + postops_injector_; + + /* register mapping */ + const Xbyak::Reg64 reg_last_load = r8; + const Xbyak::Reg64 reg_bcast_data = r8; + const Xbyak::Reg64 reg_ptr_scales = r8; + const Xbyak::Reg64 reg_ptr_saturation_ubound = r8; + const Xbyak::Reg64 reg_output_data = r9; + const Xbyak::Reg64 reg_load_data = r10; + const Xbyak::Reg64 reg_ptr_sum_scale = r10; + const Xbyak::Reg64 reg_reduce_loop_work = r11; + const Xbyak::Reg64 reg_bias_data = r12; + const Xbyak::Reg64 reg_comp_data = r12; + const Xbyak::Reg64 reg_ptr_dst_scale = r12; + const Xbyak::Reg64 reg_scratch = r13; + const Xbyak::Reg64 aux_reg_bcast_data = r14; + const Xbyak::Reg64 aux_reg_load_data = r15; + const Xbyak::Reg64 imm_addr64 = r15; + const Xbyak::Reg64 reg_reduce_pos_flag = rax; + const Xbyak::Reg64 aux1_reg_bcast_data = rbx; + const Xbyak::Reg64 reg_bcast_loop_work = rbx; + const Xbyak::Reg64 bcast_loop_iter = rdx; // Note: Fix me + const Xbyak::Reg64 reg_load_loop_work = rsi; + const Xbyak::Reg64 aux_reg_output_data = abi_not_param1; + const Xbyak::Reg64 reduce_loop_iter = abi_param1; + // zero-point computation + const Xbyak::Reg64 reg_zp_compensation = aux_reg_load_data; // r15 + const Xbyak::Reg64 reg_src_zero_point = aux_reg_bcast_data; // r14 + const Xbyak::Reg64 reg_dst_zero_point = reg_src_zero_point; + const Xbyak::Reg64 reg_load_dim_tail_mask = reg_scratch; + + const Xbyak::Opmask k_load_dim_mask = Xbyak::Opmask(2); + const Xbyak::Opmask k_load_dim_mask_extended = Xbyak::Opmask(3); + const Xbyak::Opmask k_load_dim_tail_mask = Xbyak::Opmask(4); + const Xbyak::Opmask k_load_dim_tail_mask_extended = Xbyak::Opmask(5); + const Xbyak::Opmask postops_mask = Xbyak::Opmask(6); + const Xbyak::Opmask vmask = k7; + + const Vmm vmm_tmp = Vmm(28); + const Vmm vmm_saturation = Vmm(28); + const Vmm vmm_one = Vmm(29); + const Vmm vmm_zero = Vmm(30); + const Vmm vmm_prev_dst = Vmm(30); + const Vmm vmm_shift = Vmm(30); + const Vmm vmm_bcast = Vmm(31); + /* zero-point */ + const Vmm vmm_zp = Vmm(30); + const Vmm vmm_zp_tmp = vmm_zp; + + const Vmm vmm_dst_scale = Vmm(30); + + /* bfloat16 */ + const Xbyak::Zmm bf16_emu_reserv_1 = Xbyak::Zmm(25); + const Xbyak::Zmm bf16_emu_reserv_2 = Xbyak::Zmm(26); + const Xbyak::Zmm bf16_emu_reserv_3 = Xbyak::Zmm(27); + const Xbyak::Reg64 bf16_emu_reserv_4 = imm_addr64; + const Xbyak::Zmm bf16_emu_reserv_5 = Xbyak::Zmm(28); + const Xbyak::Ymm ymm_store = Xbyak::Ymm(31); + + std::unique_ptr bf16_emu_; + + constexpr static int reg64_size_ = sizeof(int64_t); + constexpr static int bcast_loop_work_off = 0; + constexpr static int reg_bias_data_off = 1 * reg64_size_; + constexpr static int reg_bcast_data_off = 2 * reg64_size_; + constexpr static int reg_load_data_off = 3 * reg64_size_; + constexpr static int reg_ptr_sum_scale_off = 4 * reg64_size_; + constexpr static int reg_ptr_sum_zp_off = 5 * reg64_size_; + constexpr static int reg_comp_data_off = 6 * reg64_size_; + constexpr static int reg_zp_compensation_off = 7 * reg64_size_; + constexpr static int reg_src_zero_point_off = 8 * reg64_size_; + constexpr static int reg_dst_zero_point_off = 9 * reg64_size_; + constexpr static int reg_dst_scale_off = 10 * reg64_size_; + constexpr static int reg_abi_param1_backup = 11 * reg64_size_; + constexpr static int stack_space_needed = 12 * reg64_size_; + + inline Vmm maybe_mask_vmm(Vmm vmm, bool mask_flag) { + return mask_flag ? vmm | k_load_dim_mask_extended : vmm; + } + inline Vmm_down_t maybe_mask_vmm_down(Vmm_down_t vmm_down, bool mask_flag) { + return mask_flag ? vmm_down | k_load_dim_mask : vmm_down; + } + inline Vmm_down_t vmm_store() { return Vmm_down_t(ymm_store.getIdx()); }; + + void bcast_loop(int load_loop_blk); + void reduce_loop(int load_loop_blk, int ur, bool wraparound); + + Xbyak::Address output_ptr(const int i_load, const int i_ur); + int vreg_accum_idx(const int load_loop_blk, int i_load, int i_ur) const; + Vmm vreg_accum(const int load_loop_blk, int i_load, int i_ur) const; + void apply_sum(const int load_loop_blk, const int ur, + const bool mask_flag_in, const float *p_sum_scale, + const int32_t *p_sum_zp); + void apply_postops(const int load_loop_blk, const int ur, + const bool mask_flag_in, const float *p_sum_scale, + const int32_t *p_sum_zp); + void generate() override; + void cvt2ps(data_type_t type_in, const Vmm vmm_in, const Xbyak::Operand &op, + bool mask_flag); +}; + +struct jit_avx512_core_x8s8s32x_1x1_conv_kernel { + jit_avx512_core_x8s8s32x_1x1_conv_kernel(const jit_1x1_conv_conf_t &ajcp, + const primitive_attr_t &attr, const memory_desc_t &dst_md) + : kernel_(nullptr) { + int ch_block = ajcp.ic_block; + switch (ch_block) { + case 16: + kernel_ = new _jit_avx512_core_x8s8s32x_1x1_conv_kernel< + Xbyak::Zmm>(ajcp, attr, dst_md); + return; + case 8: + kernel_ = new _jit_avx512_core_x8s8s32x_1x1_conv_kernel< + Xbyak::Ymm>(ajcp, attr, dst_md); + return; + case 4: + kernel_ = new _jit_avx512_core_x8s8s32x_1x1_conv_kernel< + Xbyak::Xmm>(ajcp, attr, dst_md); + return; + default: assert(!"invalid channel blocking"); + } + } + + status_t create_kernel() { + if (kernel_) return kernel_->create_kernel(); + return status::out_of_memory; + } + + ~jit_avx512_core_x8s8s32x_1x1_conv_kernel() { delete kernel_; } + + static status_t init_conf(jit_1x1_conv_conf_t &jcp, + const convolution_desc_t &cd, const memory_desc_t *&src_md, + memory_desc_t &weights_md, memory_desc_t &dst_md, + memory_desc_t &bias_md, const primitive_attr_t &attr, int nthreads, + bool reduce_src); + + static void init_scratchpad(memory_tracking::registrar_t &scratchpad, + const jit_1x1_conv_conf_t &jcp, const primitive_attr_t &attr); + + void operator()(const jit_1x1_conv_call_s *p) const { (*kernel_)(p); } + const Xbyak::uint8 *jit_ker() const { return kernel_->jit_ker(); } + +private: + DNNL_DISALLOW_COPY_AND_ASSIGN(jit_avx512_core_x8s8s32x_1x1_conv_kernel); + jit_generator *kernel_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_x8s8s32x_1x1_convolution.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_x8s8s32x_1x1_convolution.hpp new file mode 100644 index 0000000000000000000000000000000000000000..a57d11ccb7c378f0db24d63ee8409e38183bbb76 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_x8s8s32x_1x1_convolution.hpp @@ -0,0 +1,328 @@ +/******************************************************************************* +* Copyright 2018-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_AVX512_CORE_X8S8S32X_1X1_CONVOLUTION_HPP +#define CPU_X64_JIT_AVX512_CORE_X8S8S32X_1X1_CONVOLUTION_HPP + +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/memory_tracking.hpp" +#include "common/primitive.hpp" +#include "common/primitive_hashing.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_convolution_pd.hpp" +#include "cpu/dw_convolution_utils.hpp" +#include "cpu/platform.hpp" + +#include "cpu/x64/jit_avx512_core_x8s8s32x_1x1_conv_kernel.hpp" +#include "cpu/x64/jit_avx512_core_x8s8s32x_convolution.hpp" +#include "cpu/x64/jit_uni_1x1_conv_utils.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +struct jit_avx512_core_x8s8s32x_1x1_convolution_fwd_t : public primitive_t { + struct pd_t : public cpu_convolution_fwd_pd_t { + using dw_conv_pd_type = cpu_convolution_fwd_pd_t; + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const typename pd_t::base_class *hint_fwd_pd) + : cpu_convolution_fwd_pd_t(adesc, attr, hint_fwd_pd) + , jcp_() + , rtus_() + , jcp_dw_(nullptr) {} + + pd_t(const pd_t &other) : cpu_convolution_fwd_pd_t(other) { + if (copy(other) != status::success) is_initialized_ = false; + } + + DECLARE_COMMON_PD_T( + JIT_IMPL_NAME_HELPER("jit_int8_1x1:", + ((jcp_.has_vnni) ? avx512_core_vnni : avx512_core), ""), + jit_avx512_core_x8s8s32x_1x1_convolution_fwd_t); + + status_t init(engine_t *engine) { + using namespace data_type; + using smask_t = primitive_attr_t::skip_mask_t; + bool ok = is_fwd() + && set_default_alg_kind(alg_kind::convolution_direct) + && utils::one_of(src_md(0)->data_type, s8, u8) + && weights_md(0)->data_type == s8 + && IMPLICATION(with_bias(), weights_md(1)->data_type == f32) + && utils::one_of( + dst_md(0)->data_type, f32, s32, s8, u8, bf16) + && desc()->accum_data_type == s32 + && attr()->has_default_values(smask_t::scales_runtime + | smask_t::zero_points_runtime + | smask_t::post_ops | smask_t::sum_dt, + dst_md(0)->data_type) + && attr()->scales_.has_default_values( + {DNNL_ARG_SRC, DNNL_ARG_WEIGHTS, DNNL_ARG_DST, + DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_WEIGHTS, + DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_DST}) + && attr()->post_ops_.check_sum_consistency( + dst_md(0)->data_type, + /* is_int8 */ true) + && !has_zero_dim_memory() && attr_scales_ok() + && zero_points_ok() + && set_default_formats_common( + dat_tag(), format_tag::any, dat_tag()) + && attr_.set_default_formats(dst_md(0)) == status::success; + if (!ok) return status::unimplemented; + + const convolution_desc_t *conv_d = desc(); + const memory_desc_t *src_d = src_md(); + rtus_prepare(this, conv_d, src_d, dst_md(), weights_md()); + + CHECK(jit_avx512_core_x8s8s32x_1x1_conv_kernel::init_conf(jcp_, + *conv_d, src_d, weights_md_, dst_md_, bias_md_, *attr(), + dnnl_get_max_threads(), rtus_.reduce_src_)); + if (jcp_.with_dw_conv) CHECK(depthwise_po_init(engine)); + + auto scratchpad = scratchpad_registry().registrar(); + jit_avx512_core_x8s8s32x_1x1_conv_kernel::init_scratchpad( + scratchpad, jcp_, *attr()); + + rtus_prepare_space_info(this, scratchpad, jcp_.nthr); + + return status::success; + } + + const memory_desc_t *dst_1x1_md(int index = 0) const { + return cpu_convolution_fwd_pd_t::dst_md(index); + } + + const memory_desc_t *dst_md( + int index = 0, bool user_input = false) const override { + return jcp_.with_dw_conv + ? dw_conv_pd_->dst_md(index, user_input) + : cpu_convolution_fwd_pd_t::dst_md(index, user_input); + } + + const memory_desc_t *arg_md( + int arg, bool user_input = false) const override { + if (jcp_.with_dw_conv) { + switch (arg) { + case DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_SRC: + return cpu_convolution_fwd_pd_t::dst_md(0, user_input); + case DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_WEIGHTS: + return dw_conv_pd_->weights_md(0); + case DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_BIAS: + return dw_conv_pd_->weights_md(1); + default: break; + } + } + return convolution_fwd_pd_t::arg_md(arg, user_input); + } + + arg_usage_t arg_usage(int arg) const override { + if (arg == (DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_WEIGHTS)) + return arg_usage_t::input; + + if (arg == (DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_BIAS) + && attr_post_op_dw_inputs() > 1) + return arg_usage_t::input; + + if (arg == (DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_ATTR_OUTPUT_SCALES) + && jcp_.with_dw_conv) + return arg_usage_t::input; + return convolution_fwd_pd_t::arg_usage(arg); + } + + jit_1x1_conv_conf_t jcp_; + reduce_to_unit_stride_t rtus_; + jit_conv_conf_t *jcp_dw_; // doesn't own a resource + std::unique_ptr dw_conv_pd_; + using dw_pd_t = + typename jit_avx512_core_x8s8s32x_convolution_fwd_t::pd_t; + + protected: + format_tag_t dat_tag() const { + return utils::pick(src_md_.ndims - 3, format_tag::nwc, + format_tag::nhwc, format_tag::ndhwc); + } + + bool zero_points_ok() const { + // Only common zero points are supported -> mask should only be 0 + int mask_src = 0, mask_dst = 0; + attr()->zero_points_.get(DNNL_ARG_SRC, &mask_src); + attr()->zero_points_.get(DNNL_ARG_DST, &mask_dst); + return attr()->zero_points_.has_default_values(DNNL_ARG_WEIGHTS) + && mask_src == 0 && mask_dst == 0; + } + + status_t copy(const pd_t &other) { + jcp_ = other.jcp_; + rtus_ = other.rtus_; + jcp_dw_ = nullptr; + + if (other.dw_conv_pd_) { + dw_conv_pd_.reset(static_cast( + other.dw_conv_pd_->clone())); + if (!dw_conv_pd_) return status::out_of_memory; + + jcp_dw_ = &(static_cast(dw_conv_pd_.get())->jcp_); + } + return status::success; + } + + status_t depthwise_po_init(engine_t *engine) { + using namespace memory_tracking; + auto &jcp_1x1 = jcp_; + primitive_attr_t attr_1x1(*attr()); + if (!attr_1x1.is_initialized()) return status::out_of_memory; + + const auto &src_md = dst_md_; + const memory_desc_wrapper src_d(src_md); + const auto nthr = dnnl_get_max_threads(); + auto l2_cache = platform::get_per_core_cache_size(2) * nthr; + + // Note: A robust fusion implementation would be to check if both + // 1x1 conv and dw conv that are considered here for fusion are + // optimal independently. This would require creating a new + // primitive_desc through primitive_iterator & check if they match. + // Due to concern that these creations and/or checks could be heavy, + // for 1x1: Check that no better ISA is available. + // for dw: Always fuse with same ISA. + // Caveat: May be a better dw conv exists. + + bool ok = !mayiuse(avx512_core_amx) + && (attr_1x1.post_ops_.find(primitive_kind::sum) == -1) + // TODO: Below may be further tuned. + && (l2_cache < src_d.size()) + // load_grp_count check can be redundant due to l2 check + // above. Adding it explicitly as the current driver doesn't + // work if this condition fails. + && (jcp_1x1.load_grp_count < 2); + if (!ok) return status::unimplemented; + + int dw_po_index + = attr_1x1.post_ops_.find(primitive_kind::convolution); + + convolution_desc_t cd_dw; + primitive_attr_t attr_dw; + CHECK(get_depthwise_conv_desc( + cd_dw, src_md, attr_1x1, attr_dw, dw_po_index)); + + std::unique_ptr fusable_pd( + new dw_pd_t(&cd_dw, &attr_dw, nullptr)); + CHECK(fusable_pd->init(engine)); + jcp_dw_ = &(fusable_pd->jcp_); + dw_conv_pd_ = std::move(fusable_pd); + + ok = true + && (dnnl_memory_desc_equal(&src_md, dw_conv_pd_->src_md(0))) + && (jcp_1x1.oc_without_padding % jcp_1x1.oc_block == 0) + && IMPLICATION(jcp_dw_->ow_block, + jcp_dw_->ow_block == jcp_dw_->ow); + if (!ok) return status::unimplemented; + + assert(jcp_dw_); + assert(dw_conv_pd_->dst_md(0)->format_kind != format_kind::any); + assert(dw_conv_pd_->weights_md(0)->format_kind != format_kind::any); + assert(IMPLICATION( + dw_conv_pd_->weights_md(1)->data_type != data_type::undef, + dw_conv_pd_->weights_md(1)->format_kind + != format_kind::any)); + + jcp_dw_->is_fused_conv = true; + // TODO: Support/experiment arbitary oc_work in dw conv. + // Until then we keep ch_work perfectly divisible. + while (jcp_1x1.nb_load % jcp_1x1.nb_load_blocking != 0) + --jcp_1x1.nb_load_blocking; + jcp_1x1.nb_load_blocking_max = jcp_1x1.nb_load_blocking; + + while (jcp_1x1.nb_load_blocking % jcp_dw_->nb_ch_blocking != 0) + --jcp_dw_->nb_ch_blocking; + + jcp_dw_->dw_conv_buffer_oc + = jcp_1x1.nb_load_blocking * jcp_1x1.oc_block; + jcp_1x1.bcast_loop_output_step = jcp_1x1.ur + * (jcp_1x1.nb_load_blocking * jcp_1x1.oc_block) + * jcp_1x1.typesize_out; + + registrar_t scratchpad(scratchpad_registry_); + registrar_t dw_scratchpad(scratchpad, names::prefix_fusion); + + size_t dw_conv_buffer_size_ = (size_t)nthr * jcp_dw_->kh + * jcp_dw_->iw * jcp_dw_->dw_conv_buffer_oc; + assert(dw_conv_buffer_size_); + dw_scratchpad.book(memory_tracking::names::key_fusion_inout_buffer, + dw_conv_buffer_size_, + types::data_type_size(dw_conv_pd_->src_md()->data_type)); + + dw_conv_kernel_t::init_scratchpad( + dw_scratchpad, *jcp_dw_, *(dw_conv_pd_->attr())); + return status::success; + } + }; + template + friend status_t init_rtus_driver(conv_t *self); + + jit_avx512_core_x8s8s32x_1x1_convolution_fwd_t(const pd_t *apd) + : primitive_t(apd) {} + + // Note: In case of fused depthwise convolution, the final output data type + // after fusion may not be same as for dst. + typedef typename prec_traits::type acc_data_t; + + status_t init(engine_t *engine) override { + CHECK(safe_ptr_assign(kernel_, + new jit_avx512_core_x8s8s32x_1x1_conv_kernel( + pd()->jcp_, *pd()->attr(), *pd()->dst_1x1_md(0)))); + CHECK(kernel_->create_kernel()); + + if (pd()->jcp_.with_dw_conv) { + CHECK(safe_ptr_assign(kernel_dw_, + new dw_conv_kernel_t(*(pd()->jcp_dw_), + *(pd()->dw_conv_pd_->attr()), *pd()->dst_md(0)))); + CHECK(kernel_dw_->create_kernel()); + } + + CHECK(init_rtus_driver(this)); + return status::success; + } + + status_t execute(const exec_ctx_t &ctx) const override { + return execute_forward(ctx); + } + +private: + status_t execute_forward(const exec_ctx_t &ctx) const; + void execute_forward_thr(const int ithr, const int nthr, const char *src, + const char *weights, const char *bias, const char *weights_dw, + const char *bias_dw, char *dst, const float *oscales, + const float *dst_scales, const float *dw_oscales, + const float *dw_dst_scales, const int32_t *src_zero_point, + const int32_t *dst_zero_point, + const memory_tracking::grantor_t &scratchpad, + const void *post_ops_binary_rhs_arg_vec, + const void *post_ops_binary_rhs_arg_vec_dw) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + std::unique_ptr kernel_; + std::unique_ptr> rtus_driver_; + using dw_conv_kernel_t = jit_avx512_core_x8s8s32x_fwd_kernel; + std::unique_ptr kernel_dw_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_x8s8s32x_1x1_deconvolution.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_x8s8s32x_1x1_deconvolution.hpp new file mode 100644 index 0000000000000000000000000000000000000000..d2778ff3ec89cbcacbaad3f7a2f96ad44d82c1d6 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_x8s8s32x_1x1_deconvolution.hpp @@ -0,0 +1,158 @@ +/******************************************************************************* +* Copyright 2018-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_AVX512_CORE_X8S8S32X_1X1_DECONVOLUTION_HPP +#define CPU_X64_JIT_AVX512_CORE_X8S8S32X_1X1_DECONVOLUTION_HPP + +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/primitive.hpp" +#include "common/primitive_desc_iterator.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_convolution_pd.hpp" +#include "cpu/cpu_deconvolution_pd.hpp" +#include "cpu/zero_point_utils.hpp" + +#include "cpu/x64/jit_avx512_core_x8s8s32x_1x1_convolution.hpp" +#include "cpu/x64/jit_uni_1x1_conv_utils.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +struct jit_avx512_core_x8s8s32x_1x1_deconvolution_fwd_t : public primitive_t { + struct pd_t : public cpu_deconvolution_fwd_pd_t { + pd_t(const deconvolution_desc_t *adesc, const primitive_attr_t *attr, + const deconvolution_fwd_pd_t *hint_fwd_pd) + : cpu_deconvolution_fwd_pd_t(adesc, attr, hint_fwd_pd) {} + + pd_t(const pd_t &other) + : cpu_deconvolution_fwd_pd_t(other) + , conv_pd_(other.conv_pd_->clone()) {} + + ~pd_t() = default; + + DECLARE_COMMON_PD_T(conv_pd_->name(), + jit_avx512_core_x8s8s32x_1x1_deconvolution_fwd_t); + + status_t init_convolution(engine_t *engine) { + convolution_desc_t cd; + + auto dd = desc(); + CHECK(conv_desc_init(&cd, prop_kind::forward_training, + alg_kind::convolution_direct, &(dd->src_desc), + &(dd->weights_desc), &(dd->bias_desc), &(dd->dst_desc), + dd->strides, dd->dilates, dd->padding[0], dd->padding[1])); + + primitive_attr_t conv_attr(*attr()); + if (!conv_attr.is_initialized()) return status::out_of_memory; + primitive_desc_iterator_t it( + engine, (op_desc_t *)&cd, &conv_attr, nullptr); + if (!it.is_initialized()) return status::out_of_memory; + + while (++it != it.end()) { + conv_pd_ = *it; + // XXX: find another way to create required implementation. + if (dynamic_cast(conv_pd_.get())) + return set_default_params(); + } + + return status::unimplemented; + }; + + status_t init(engine_t *engine) { + using namespace data_type; + using skip_mask_t = primitive_attr_t::skip_mask_t; + bool ok = is_fwd() + && desc()->alg_kind == alg_kind::deconvolution_direct + && !has_zero_dim_memory() + && utils::one_of(src_md(0)->data_type, s8, u8) + && weights_md(0)->data_type == s8 + && IMPLICATION(with_bias(), + utils::one_of( + weights_md(1)->data_type, f32, s32, s8, u8)) + && utils::one_of(dst_md(0)->data_type, f32, s32, s8, u8) + && desc()->accum_data_type == s32 + && attr()->has_default_values(skip_mask_t::scales_runtime + | skip_mask_t::post_ops + | skip_mask_t::zero_points_runtime) + && zero_points_valid( + attr(), true /*per_oc_bcast_accepted*/); + + if (!ok) return status::unimplemented; + + CHECK(init_convolution(engine)); + CHECK(attr_.set_default_formats(dst_md(0))); + init_scratchpad(); + + return status::success; + } + + protected: + status_t set_default_params() { + auto conv_1x1_pd_ = static_cast(conv_pd_.get()); + src_md_ = *conv_1x1_pd_->src_md(); + dst_md_ = *conv_1x1_pd_->dst_md(); + weights_md_ = *conv_1x1_pd_->weights_md(); + if (with_bias()) bias_md_ = *conv_1x1_pd_->weights_md(1); + return status::success; + } + + using conv_pd_t = + typename jit_avx512_core_x8s8s32x_1x1_convolution_fwd_t::pd_t; + friend jit_avx512_core_x8s8s32x_1x1_deconvolution_fwd_t; + + std::shared_ptr conv_pd_; + + private: + void init_scratchpad() { + auto scratchpad = scratchpad_registry().registrar(); + scratchpad.book(memory_tracking::names::key_nested, + conv_pd_->scratchpad_registry()); + } + }; + + jit_avx512_core_x8s8s32x_1x1_deconvolution_fwd_t(const pd_t *apd) + : primitive_t(apd) {} + + status_t init(engine_t *engine) override { + pd()->conv_pd_->create_primitive(conv_p_, engine); + return status::success; + } + + status_t execute(const exec_ctx_t &ctx) const override { + nested_scratchpad_t ns( + ctx, memory_tracking::names::key_nested, conv_p_); + // XXX: create a new ctx for convolution? + auto &tmp_ctx = const_cast(ctx); + tmp_ctx.set_scratchpad_grantor(ns.grantor()); + return conv_p_->execute(tmp_ctx); + } + +private: + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + std::shared_ptr conv_p_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif /* CPU_X64_JIT_AVX512_CORE_X8S8S32X_1X1_DECONVOLUTION_HPP */ diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_x8s8s32x_conv_kernel.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_x8s8s32x_conv_kernel.hpp new file mode 100644 index 0000000000000000000000000000000000000000..8c60474787b7b39d85cfcc781cb325960c745dd3 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_x8s8s32x_conv_kernel.hpp @@ -0,0 +1,289 @@ +/******************************************************************************* +* Copyright 2016-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_AVX512_CORE_X8S8S32X_CONV_KERNEL_HPP +#define CPU_X64_JIT_AVX512_CORE_X8S8S32X_CONV_KERNEL_HPP + +#include "common/c_types_map.hpp" +#include "common/memory_tracking.hpp" + +#include "cpu/x64/injectors/jit_uni_postops_injector.hpp" +#include "cpu/x64/jit_avx512_core_bf16cvt.hpp" +#include "cpu/x64/jit_generator.hpp" +#include "cpu/x64/jit_primitive_conf.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +template +struct _jit_avx512_core_x8s8s32x_fwd_kernel : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(_jit_avx512_core_x8s8s32x_conv_fwd_ker_t) + + enum { STATE_FIRST_DST_LOAD = 0x1U }; + + _jit_avx512_core_x8s8s32x_fwd_kernel(const jit_conv_conf_t &ajcp, + const primitive_attr_t &attr, const memory_desc_t &dst_md); + + jit_conv_conf_t jcp; + const primitive_attr_t &attr_; + +private: + constexpr static int isa_simd_width_ + = cpu_isa_traits::vlen / sizeof(float); + using Vmm_down_t = + typename utils::conditional::value, + Xbyak::Ymm, Xbyak::Xmm>::type; + const int ic_sub_step = 4; + std::unique_ptr> + postops_injector_; + + enum { + typesize = sizeof(float), + ker_reg_base_idx = 28, + ker_dw_reg_base_idx = 30, + ker_zp_reg_base_idx = 26, + }; + typedef enum { + no_last_block, + last_ic_block, + last_sp_block, + } ic_block_t; + + /* data regs */ + const Xbyak::Reg64 reg_ptr_scales = rax; + const Xbyak::Reg64 aux_reg_saturation = rax; + const Xbyak::Reg64 reg_inp = r8; + const Xbyak::Reg64 reg_ker = r9; + const Xbyak::Reg64 reg_out = r10; + const Xbyak::Reg64 aux_reg_inp = r11; + const Xbyak::Reg64 reg_ptr_sum_scale = r11; + const Xbyak::Reg64 reg_ptr_sum_zp = abi_not_param1; + const Xbyak::Reg64 aux_reg_ker = r12; + const Xbyak::Reg64 reg_compensation = r14; + const Xbyak::Reg64 aux_reg_inp_d = r13; + const Xbyak::Reg64 aux_reg_ker_d = r15; + const Xbyak::Reg64 reg_ker_long_offt = r13; + // Using 3d regs as depthwise_3d is not yet supported + const Xbyak::Reg64 reg_inp_buffer_ptr = aux_reg_inp_d; + const Xbyak::Reg64 aux_reg_inp_buffer_ptr = aux_reg_ker_d; + // zero-point computation + const Xbyak::Reg64 reg_zp_compensation = aux_reg_inp; + const Xbyak::Reg64 reg_src_zero_point = aux_reg_ker_d; + const Xbyak::Reg64 reg_dst_zero_point = reg_src_zero_point; + + // dst scale + const Xbyak::Reg64 reg_dst_scale = reg_src_zero_point; + + /* counter regs */ + const Xbyak::Reg64 reg_oi = rbx; + const Xbyak::Reg64 reg_bias = rdx; + const Xbyak::Reg64 reg_oc_blocks = rsi; + const Xbyak::Reg64 reg_owb = aux_reg_ker; + const Xbyak::Reg64 reg_scratch = reg_compensation; + const Xbyak::Reg64 reg_kj = reg_ptr_scales; + const Xbyak::Reg64 reg_ki = reg_compensation; + const Xbyak::Reg64 reg_overflow = reg_ptr_scales; + const Xbyak::Reg64 reg_icb = reg_bias; + const Xbyak::Reg64 reg_jmp_tbl_base = reg_kj; + + /* binary post-op operand */ + const Xbyak::Reg64 temp_offset_reg = r12; + + const Xbyak::Opmask ktail_mask = Xbyak::Opmask(2); + const Xbyak::Opmask kblend_mask = Xbyak::Opmask(3); + const Xbyak::Opmask postops_mask = Xbyak::Opmask(4); + const Xbyak::Opmask ktail_mask_extended = Xbyak::Opmask(5); + + const Vmm vmm_wei = Vmm(31); + /* used during bias section of store_output */ + const Vmm vmm_comp = Vmm(30); // only for signed input + const Vmm vmm_bias = Vmm(31); + /* used during post_op sum section of store_output */ + const Vmm vmm_prev_dst = Vmm(31); + /* used during write-out section of store_output */ + const Vmm vmm_saturation = Vmm(30); + const Vmm vmm_sum_zp = Vmm(30); + const Vmm vmm_zero = Vmm(31); + + /* used in compute_ker (but set during prepare_output) */ + const Vmm vmm_shift = vmm_comp; // only for signed input + /* used in compute_ker (but only for pre-VNNI machines) */ + const Vmm vmm_tmp = Vmm(28); // not used for depthwise + const Vmm vmm_one + = Vmm(29); // set at start of kernel, not used for depthwise. + /* zero-point */ + const Vmm vmm_zp = Vmm(25); + const Vmm vmm_zp_one = Vmm(26); + const Vmm vmm_zp_tmp = vmm_zp; + + const Vmm vmm_dst_scale = Vmm(31); + + /* bf16 emulation */ + Xbyak::Zmm bf16_emu_reserv_1 = Xbyak::Zmm(26); + Xbyak::Zmm bf16_emu_reserv_2 = Xbyak::Zmm(27); + Xbyak::Zmm bf16_emu_reserv_3 = Xbyak::Zmm(28); + Xbyak::Zmm bf16_emu_reserv_4 = Xbyak::Zmm(30); + // bf16_emu_reserv_5 not required when only computing vcvtneps2bf16() + const Xbyak::Reg64 bf16_emu_scratch = aux_reg_ker; + std::unique_ptr bf16_emu_; + + /* registers use only for depthwise + groups are always blocked by 16(padded if needed), + hence use only Zmm registers */ + const Xbyak::Zmm zmm_wei = Xbyak::Zmm(31); + Xbyak::Zmm zmm_tmp; + Xbyak::Zmm zmm_src; + Xbyak::Zmm zmm_shifted_zero; + Xbyak::Zmm zmm_permute; + + int vmm_out_idx(int i_ur, int i_oc) { + const int nb_x_blocking + = jcp.is_depthwise ? jcp.nb_ch_blocking : jcp.nb_oc_blocking; + const int idx = i_ur * nb_x_blocking + i_oc; + assert(idx < (jcp.is_depthwise ? ker_dw_reg_base_idx + : jcp.src_zero_point ? ker_zp_reg_base_idx + : ker_reg_base_idx)); + return idx; + } + + Vmm vmm_out(int i_ur, int i_oc) { return Vmm(vmm_out_idx(i_ur, i_oc)); } + Xbyak::Zmm zmm_out(int i_ur, int i_oc) { + int idx = vmm_out(i_ur, i_oc).getIdx(); + assert(idx + < (jcp.is_depthwise ? ker_dw_reg_base_idx : ker_reg_base_idx)); + return Xbyak::Zmm(idx); + } + Vmm vmm_inp(int i_ic, int nb_x_blocking) { + int idx = i_ic + nb_x_blocking * jcp.ur_w; + assert(idx < 31); + return Vmm(idx); + } + Xbyak::Zmm zmm_inp(int i_ic, int nb_x_blocking) { + const int idx = i_ic + nb_x_blocking * jcp.ur_w; + const int max_idx = jcp.src_zero_point ? ker_zp_reg_base_idx + : ker_dw_reg_base_idx; + assert(idx < max_idx); + MAYBE_UNUSED(max_idx); + + return Xbyak::Zmm(idx); + } + int get_ow_start(int ki, int pad_l) { + return nstl::max(0, + utils::div_up(pad_l - ki * (jcp.dilate_w + 1), jcp.stride_w)); + } + int get_ow_end(int ur_w, int ki, int pad_r) { + return ur_w + - nstl::max(0, + utils::div_up( + pad_r - (jcp.kw - 1 - ki) * (jcp.dilate_w + 1), + jcp.stride_w)); + } + + // bf16 utils + int get_src_down_idx(int nb_x_blocking) { + int idx = nb_x_blocking * jcp.ur_w; + assert(idx < 31); + return idx; + } + inline Vmm maybe_mask_vmm(Vmm vmm, bool mask_flag) { + return mask_flag ? vmm | ktail_mask_extended : vmm; + } + inline Vmm_down_t maybe_mask_vmm_down(Vmm_down_t vmm, bool mask_flag) { + return (mask_flag) ? vmm | ktail_mask : vmm; + } + inline void store_bf16(Xbyak::Address addr, int vmm_dst_idx, + int vmm_down_idx, bool mask_flag) { + auto vmm_down = Vmm_down_t(vmm_down_idx); + bf16_emu_->vcvtneps2bf16( + Xbyak::Ymm(vmm_down_idx), Xbyak::Zmm(vmm_dst_idx)); + + // for xmm, upper half is zero after conversion to + // bf16, so mask always & mask for tails + vmovdqu16(addr, + maybe_mask_vmm_down(vmm_down, mask_flag || jcp.simd_w == 4)); + } + + void prepare_output(int ur_w); + void apply_sum(int ur_w, bool last_oc_block_flag, const int nb_oc_block, + const int oc_block, const float *p_sum_scale, + const int32_t *p_sum_zp); + void apply_postops(int ur_w, bool last_oc_block_flag, const int nb_oc_block, + const int oc_block, const float *p_sum_scale, + const int32_t *p_sum_zp); + void store_output(int ur_w, bool last_oc_block_flag); + void compute_ker_dw(int ur_w, int pad_l, int pad_r, + ic_block_t last_ic_block_flag, bool h_padded); + void compute_ker(int ur_w, int pad_l, int pad_r, + ic_block_t last_ic_block_flag, bool h_padded = false); + void kh_loop(int ur_w, int pad_l, int pad_r, ic_block_t last_ic_block_flag); + void icb_loop(int ur_w, int pad_l, int pad_r, bool is_last_spatial_block); + void generate() override; + void cvt2ps(data_type_t type_in, Vmm ymm_in, const Xbyak::Operand &op, + bool mask_flag); + Vmm vmm_mask(const Vmm vmm_in, bool mask_flag, bool store = false); +}; + +struct jit_avx512_core_x8s8s32x_fwd_kernel { + + jit_avx512_core_x8s8s32x_fwd_kernel(const jit_conv_conf_t &ajcp, + const primitive_attr_t &attr, const memory_desc_t &dst_md) + : kernel_(nullptr) { + int ch_block = ajcp.is_depthwise ? ajcp.ch_block : ajcp.ic_block; + switch (ch_block) { + case 16: + kernel_ = new _jit_avx512_core_x8s8s32x_fwd_kernel( + ajcp, attr, dst_md); + return; + case 8: + kernel_ = new _jit_avx512_core_x8s8s32x_fwd_kernel( + ajcp, attr, dst_md); + return; + case 4: + kernel_ = new _jit_avx512_core_x8s8s32x_fwd_kernel( + ajcp, attr, dst_md); + return; + default: assert(!"invalid channel blocking"); + } + } + + status_t create_kernel() { + if (kernel_) return kernel_->create_kernel(); + return status::out_of_memory; + } + + ~jit_avx512_core_x8s8s32x_fwd_kernel() { delete kernel_; } + + static status_t init_conf(jit_conv_conf_t &jcp, + const convolution_desc_t &cd, memory_desc_t &src_pd, + memory_desc_t &weights_pd, memory_desc_t &dst_pd, + memory_desc_t &bias_pd, primitive_attr_t &attr, int nthreads); + static void init_scratchpad(memory_tracking::registrar_t &scratchpad, + const jit_conv_conf_t &jcp, const primitive_attr_t &attr); + void operator()(const jit_conv_call_s *p) const { (*kernel_)(p); } + const Xbyak::uint8 *jit_ker() const { return kernel_->jit_ker(); } + +private: + jit_generator *kernel_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_x8s8s32x_convolution.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_x8s8s32x_convolution.hpp new file mode 100644 index 0000000000000000000000000000000000000000..008da923a71bccc5ae10f7cabe93e5a363749f6f --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_x8s8s32x_convolution.hpp @@ -0,0 +1,136 @@ +/******************************************************************************* +* Copyright 2016-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_AVX512_CORE_X8S8S32X_CONVOLUTION_HPP +#define CPU_X64_JIT_AVX512_CORE_X8S8S32X_CONVOLUTION_HPP + +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/memory_tracking.hpp" +#include "common/primitive.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_convolution_pd.hpp" + +#include "cpu/x64/jit_avx512_core_x8s8s32x_conv_kernel.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +struct jit_avx512_core_x8s8s32x_convolution_fwd_t : public primitive_t { + struct pd_t : public cpu_convolution_fwd_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const typename pd_t::base_class *hint_fwd_pd) + : cpu_convolution_fwd_pd_t(adesc, attr, hint_fwd_pd), jcp_() {} + + DECLARE_COMMON_PD_T( + JIT_IMPL_NAME_HELPER("jit_int8:", + (jcp_.has_vnni ? avx512_core_vnni : avx512_core), ""), + jit_avx512_core_x8s8s32x_convolution_fwd_t); + + status_t init(engine_t *engine) { + using namespace data_type; + using smask_t = primitive_attr_t::skip_mask_t; + bool ok = is_fwd() + && set_default_alg_kind(alg_kind::convolution_direct) + && utils::one_of(src_md(0)->data_type, s8, u8) + && weights_md(0)->data_type == s8 + && IMPLICATION(with_bias(), + utils::one_of( + weights_md(1)->data_type, f32, s32, s8, u8)) + && utils::one_of( + dst_md(0)->data_type, f32, s32, s8, u8, bf16) + && desc()->accum_data_type == s32 + && attr()->has_default_values(smask_t::scales_runtime + | smask_t::zero_points_runtime + | smask_t::post_ops | smask_t::sum_dt, + dst_md(0)->data_type) + && attr()->post_ops_.check_sum_consistency( + dst_md(0)->data_type, /* is_int8 */ true) + && !has_zero_dim_memory() && attr_scales_ok() + && zero_points_ok(); + if (!ok) return status::unimplemented; + + CHECK(jit_avx512_core_x8s8s32x_fwd_kernel::init_conf(jcp_, *desc(), + src_md_, weights_md_, dst_md_, bias_md_, attr_, + dnnl_get_max_threads())); + + auto scratchpad = scratchpad_registry().registrar(); + jit_avx512_core_x8s8s32x_fwd_kernel::init_scratchpad( + scratchpad, jcp_, *attr()); + + return status::success; + } + + jit_conv_conf_t jcp_; + + protected: + bool zero_points_ok() const { + // Only common zero points are supported -> mask should only be 0 + int mask_src = 0, mask_dst = 0; + attr()->zero_points_.get(DNNL_ARG_SRC, &mask_src); + attr()->zero_points_.get(DNNL_ARG_DST, &mask_dst); + return attr()->zero_points_.has_default_values(DNNL_ARG_WEIGHTS) + && mask_src == 0 && mask_dst == 0; + } + }; + + jit_avx512_core_x8s8s32x_convolution_fwd_t(const pd_t *apd) + : primitive_t(apd) {} + + status_t init(engine_t *engine) override { + CHECK(safe_ptr_assign(kernel_, + new jit_avx512_core_x8s8s32x_fwd_kernel( + pd()->jcp_, *pd()->attr(), *pd()->dst_md(0)))); + return kernel_->create_kernel(); + } + + status_t execute(const exec_ctx_t &ctx) const override { + const auto &_pd = pd(); + if (_pd->ndims() == 3) + return execute_forward_1d(ctx); + else if (_pd->ndims() == 4) + if (_pd->jcp_.is_depthwise) + return execute_forward_2d_dw(ctx); + else + return execute_forward_2d(ctx); + else if (_pd->ndims() == 5) + return execute_forward_3d(ctx); + return status::unimplemented; + } + +private: + status_t execute_forward_1d(const exec_ctx_t &ctx) const; + status_t execute_forward_2d(const exec_ctx_t &ctx) const; + status_t execute_forward_2d_dw(const exec_ctx_t &ctx) const; + status_t execute_forward_3d(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + const float *adjust_oscales(const memory_tracking::grantor_t &scratchpad, + const float *src_scales, const float *wei_scales) const; + + std::unique_ptr kernel_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_x8s8s32x_deconvolution.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_x8s8s32x_deconvolution.hpp new file mode 100644 index 0000000000000000000000000000000000000000..f691fd1842e8f065c8f5984f337ae6029e3f7bd1 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_avx512_core_x8s8s32x_deconvolution.hpp @@ -0,0 +1,333 @@ +/******************************************************************************* +* Copyright 2018-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_AVX512_CORE_X8S8S32X_DECONVOLUTION_HPP +#define CPU_X64_JIT_AVX512_CORE_X8S8S32X_DECONVOLUTION_HPP + +#include +#include + +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/memory.hpp" +#include "common/nstl.hpp" +#include "common/primitive.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_deconvolution_pd.hpp" +#include "cpu/x64/injectors/jit_uni_postops_injector.hpp" +#include "cpu/x64/jit_generator.hpp" +#include "cpu/x64/jit_primitive_conf.hpp" +#include "cpu/x64/jit_uni_deconv_zp_pad_str_kernel.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +typedef enum { + no_last_block = 0x1U, + last_ic_block = 0x2U, + last_sp_block = 0x4U, +} ker_block_t; + +struct ur_w_blks_params_t { + struct single_ur_w_blk_params_t { + single_ur_w_blk_params_t( + int l_overflow, int r_overflow, bool process_sp_carefully) + : l_overflow(l_overflow) + , r_overflow(r_overflow) + , process_sp_carefully(process_sp_carefully) {} + + // l_overflow - no. of spatial elements of weights standing out of + // src spatial when computing the 1st output pixel in the current blk + int l_overflow; + // r_overflow - no. of spatial elements of weights standing out of + // src spatial when computing the lst output pixel in the current blk + int r_overflow; + // process_sp_carefully - indicates if loading the last src sp + // for computation of the last dst sp of the block can't be done + // by fetching 4 src sp at once + bool process_sp_carefully; + }; + std::vector blks_params; + int num_pre_blks; // num of blocks with l_overflow>0 + int num_post_blks; // num of blocks with r_overflow>0 or that need to be + // processed carefully +}; + +template +struct jit_avx512_core_x8s8s32x_deconv_fwd_kernel : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_x8s8s32x_deconv_fwd_ker_t); + + jit_avx512_core_x8s8s32x_deconv_fwd_kernel(const jit_conv_conf_t &ajcp, + const primitive_attr_t &attr, const memory_desc_t &dst_md); + ~jit_avx512_core_x8s8s32x_deconv_fwd_kernel(); + + const jit_conv_conf_t &jcp; + const primitive_attr_t &attr_; + +private: + std::unique_ptr> + postops_injector_; + + const int ic_sub_step = 4; + + /* data regs */ + const Xbyak::Reg64 reg_src = r8; + const Xbyak::Reg64 reg_filt = r9; + const Xbyak::Reg64 reg_dst = r10; + const Xbyak::Reg64 param1 = abi_param1; + const Xbyak::Reg64 reg_kh = abi_not_param1; + const Xbyak::Reg64 reg_ki = r14; + + const Xbyak::Reg64 reg_nur_w = rbx; + const Xbyak::Reg64 reg_bias = rdx; + const Xbyak::Reg64 reg_icb = reg_bias; + const Xbyak::Reg64 reg_ptr_scales = rax; + const Xbyak::Reg64 reg_ptr_dst_scales = rax; + const Xbyak::Reg64 reg_ptr_saturation_ubound = rax; + const Xbyak::Reg64 reg_oc_blocks = rsi; + + const Xbyak::Reg64 aux_reg_src = r11; + const Xbyak::Reg64 aux_reg_filt = r12; + + const Xbyak::Reg64 aux_reg_src_d = r13; + const Xbyak::Reg64 aux_reg_filt_d = r15; + + const Xbyak::Reg64 reg_compensation = r14; + const Xbyak::Reg64 reg_scratch = r14; + const Xbyak::Reg64 reg_ptr_sum_scale = r11; + const Xbyak::Reg64 reg_overflow = rax; + const Xbyak::Reg64 reg_comp_strides = reg_overflow; + const Xbyak::Reg64 reg_ker_long_offt = r15; + const Xbyak::Reg64 ®_zp_dst_ = r15; + const Xbyak::Reg64 ®_zp_src_ = r15; + const Xbyak::Reg64 ®_zp_compensation = r11; + static constexpr int reserved_stack_size_ = 16; + const Xbyak::Address zp_src_pad_comp_addr = ptr[rsp]; + const Xbyak::Address reg_scratch_preserved = ptr[rsp + 8]; + + Xbyak::Opmask ktail_mask = Xbyak::Opmask(2); + const Vmm vmm_tmp = Vmm(28); + const Vmm vmm_one = Vmm(29); + /* used during write-out section of store_output */ + const Vmm vmm_zero = Vmm(31); + const Vmm vmm_saturation = Vmm(31); + const Vmm vmm_wei = Vmm(31); + + /* signed input */ + const Vmm vmm_shift = Vmm(30); + const Vmm vmm_comp = Vmm(30); + const Vmm vmm_bias = Vmm(31); + const Vmm vmm_dst_scale = Vmm(31); + const Vmm vmm_prev_dst = Vmm(31); + + Vmm vmm_out(int i_ur, int i_oc) { + int idx = i_ur * jcp.nb_oc_blocking + i_oc; + assert(idx < 31); + return Vmm(idx); + } + Vmm vmm_inp(int i_ic, int nb_x_blocking) const { + int idx = i_ic + nb_x_blocking * jcp.ur_w; + assert(idx < 31); + return Vmm(idx); + } + + int get_ow_start(int ki, int l_overflow) { + int res = (jcp.ow - 1 + jcp.r_pad) % jcp.stride_w + + l_overflow * jcp.stride_w + - (jcp.kw - 1 - ki) * (jcp.dilate_w + 1); + while (res < 0) + res += jcp.stride_w; + return res; + } + + int get_ow_end(int ur_w, int ki, int r_overflow) { + if (utils::one_of(ur_w, jcp.ow, jcp.ur_w_tail)) + ur_w += nstl::min(0, jcp.r_pad); // remove negative padding + int res = (ur_w - 1 + jcp.l_pad) % jcp.stride_w + + r_overflow * jcp.stride_w - ki * (jcp.dilate_w + 1); + while (res < 0) + res += jcp.stride_w; + return ur_w - res; + } + + int get_blocking_size() const noexcept; + int get_tail_size() const noexcept; + void prepare_output(int ur_w); + void store_output(int ur_w, bool last_oc_block); + void compute(const Vmm &vreg_acc, const Vmm &vreg_wei, const Vmm &vreg_src); + std::function prepare_round_robin_vmm_inp_generator( + int ur_w) const noexcept; + void apply_zp_src_pad_str_comp( + int ur_w, int l_overflow, int r_overflow, bool h_padded); + void append_zp_src_pad_str_comp(int ur_w, int l_overflow, int r_overflow, + bool h_padded, bool last_oc_block); + void compute_ker(int ur_w, int l_overflow, int r_overflow, + ker_block_t last_ic_block_flag, bool h_padded = false); + void kh_loop(int ur_w, int pad_l, int pad_r, ker_block_t last_ker_block); + void icb_loop(int ur_w, int pad_l, int pad_r, bool last_block); + + ur_w_blks_params_t get_ur_w_blks_params(); + + void generate() override; + void cvt2ps(data_type_t type_in, Vmm vmm_in, const Xbyak::Operand &op, + bool mask_flag); +}; + +struct _jit_avx512_core_x8s8s32x_deconv_fwd_kernel { + _jit_avx512_core_x8s8s32x_deconv_fwd_kernel(const jit_conv_conf_t &ajcp, + const primitive_attr_t &attr, const memory_desc_t &dst_md) + : kernel_(nullptr) { + + int ch_block = ajcp.is_depthwise ? ajcp.ch_block : ajcp.ic_block; + switch (ch_block) { + case 16: + kernel_ = new jit_avx512_core_x8s8s32x_deconv_fwd_kernel< + Xbyak::Zmm>(ajcp, attr, dst_md); + return; + case 8: + kernel_ = new jit_avx512_core_x8s8s32x_deconv_fwd_kernel< + Xbyak::Ymm>(ajcp, attr, dst_md); + return; + case 4: + kernel_ = new jit_avx512_core_x8s8s32x_deconv_fwd_kernel< + Xbyak::Xmm>(ajcp, attr, dst_md); + return; + default: assert(!"invalid channel blocking"); + } + } + + status_t create_kernel() { + if (kernel_) return kernel_->create_kernel(); + return status::out_of_memory; + } + + ~_jit_avx512_core_x8s8s32x_deconv_fwd_kernel() { delete kernel_; } + + void operator()(const jit_deconv_call_s *p) const { (*kernel_)(p); } + + static bool post_ops_ok(jit_conv_conf_t &jcp, primitive_attr_t &attr, + const memory_desc_wrapper &dst_d); + + static status_t init_conf(jit_conv_conf_t &jcp, + const deconvolution_desc_t &cd, memory_desc_t &src_md, + memory_desc_t &weights_md, memory_desc_t &dst_md, + const bool with_bias, memory_desc_t &bias_md, + primitive_attr_t &attr, int nthreads); + + static void init_scratchpad(memory_tracking::registrar_t &scratchpad, + const jit_conv_conf_t &jcp, const primitive_attr_t &attr); + +private: + DNNL_DISALLOW_COPY_AND_ASSIGN(_jit_avx512_core_x8s8s32x_deconv_fwd_kernel); + jit_generator *kernel_; +}; + +struct jit_avx512_core_x8s8s32x_deconvolution_fwd_t : public primitive_t { + struct pd_t : public cpu_deconvolution_fwd_pd_t { + using cpu_deconvolution_fwd_pd_t::cpu_deconvolution_fwd_pd_t; + + DECLARE_COMMON_PD_T( + JIT_IMPL_NAME_HELPER("jit_deconvolution:", + ((jcp_.has_vnni) ? avx512_core_vnni : avx512_core), ""), + jit_avx512_core_x8s8s32x_deconvolution_fwd_t); + + status_t init(engine_t *engine) { + using namespace data_type; + using skip_mask_t = primitive_attr_t::skip_mask_t; + const bool ok = is_fwd() + && (desc()->alg_kind & alg_kind::deconvolution_direct) + && utils::one_of(src_md(0)->data_type, s8, u8) + && weights_md(0)->data_type == s8 + && IMPLICATION(with_bias(), + utils::one_of( + weights_md(1)->data_type, f32, s32, s8, u8)) + && utils::one_of(dst_md(0)->data_type, f32, s32, s8, u8) + && desc()->accum_data_type == s32 + && attr()->has_default_values(skip_mask_t::scales_runtime + | skip_mask_t::post_ops + | skip_mask_t::zero_points_runtime) + && attr_scales_ok(); + if (!ok) return status::unimplemented; + + CHECK(_jit_avx512_core_x8s8s32x_deconv_fwd_kernel::init_conf(jcp_, + *desc(), src_md_, weights_md_, dst_md_, with_bias(), + bias_md_, attr_, dnnl_get_max_threads())); + + auto scratchpad = scratchpad_registry().registrar(); + _jit_avx512_core_x8s8s32x_deconv_fwd_kernel::init_scratchpad( + scratchpad, jcp_, *attr()); + + return status::success; + } + + jit_conv_conf_t jcp_; + }; + + jit_avx512_core_x8s8s32x_deconvolution_fwd_t(const pd_t *apd) + : primitive_t(apd) {} + + status_t init(engine_t *engine) override { + CHECK(safe_ptr_assign(kernel_, + new _jit_avx512_core_x8s8s32x_deconv_fwd_kernel( + pd()->jcp_, *pd()->attr(), *pd()->dst_md(0)))); + + if (zp::should_calculate_deconv_zp_src_pad_str_comp(pd()->jcp_)) { + CHECK(safe_ptr_assign(zp_src_pad_comp_kernel_, + zp::create_deconv_zp_pad_str_comp_ker( + pd()->jcp_))); + const auto zp_kernel_status + = zp_src_pad_comp_kernel_->create_kernel(); + if (zp_kernel_status != status::success) return zp_kernel_status; + } + + return kernel_->create_kernel(); + } + + status_t execute(const exec_ctx_t &ctx) const override { + auto ndims = pd()->ndims(); + if (ndims == 3) + return execute_forward_1d(ctx); + else if (ndims == 4) + return execute_forward_2d(ctx); + else if (ndims == 5) + return execute_forward_3d(ctx); + return status::runtime_error; + } + +private: + status_t execute_forward_1d(const exec_ctx_t &ctx) const; + status_t execute_forward_2d(const exec_ctx_t &ctx) const; + status_t execute_forward_3d(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + std::unique_ptr<_jit_avx512_core_x8s8s32x_deconv_fwd_kernel> kernel_; + std::unique_ptr + zp_src_pad_comp_kernel_; + const float *adjust_oscales(const memory_tracking::grantor_t &scratchpad, + const float *src_scales, const float *wei_scales) const; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brdgmm_dw_conv.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brdgmm_dw_conv.hpp new file mode 100644 index 0000000000000000000000000000000000000000..44e9ed93fa18e82275ab6b270cf27c24ba3f7b1a --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brdgmm_dw_conv.hpp @@ -0,0 +1,65 @@ +/******************************************************************************* +* Copyright 2021 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_BRDGMM_DW_CONV_HPP +#define CPU_X64_JIT_BRDGMM_DW_CONV_HPP + +#include "common/primitive.hpp" + +#include "cpu/cpu_convolution_pd.hpp" +#include "cpu/platform.hpp" + +#include "cpu/x64/brgemm/brgemm.hpp" +#include "cpu/x64/jit_primitive_conf.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +struct brdgmm_dw_convolution_fwd_t : public primitive_t { + struct pd_t : public cpu_convolution_fwd_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const typename pd_t::base_class *hint_fwd_pd) + : cpu_convolution_fwd_pd_t(adesc, attr, hint_fwd_pd), jcp_() {} + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("brdgmm_dw:", jcp_.isa, ""), + brdgmm_dw_convolution_fwd_t); + + status_t init(engine_t *engine); + jit_brdgmm_conv_conf_t jcp_; + std::vector bcps_; + size_t buffer_size_ = 0; + + private: + status_t init_brdgmm_conf(); + status_t init_scratchpad(); + }; + + brdgmm_dw_convolution_fwd_t(const pd_t *apd) : primitive_t(apd) {} + + status_t init(engine_t *engine) override; + status_t execute(const exec_ctx_t &ctx) const override; + +private: + std::vector> brdgmm_kernels_; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } +}; +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_1x1_conv.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_1x1_conv.hpp new file mode 100644 index 0000000000000000000000000000000000000000..9ee1a54a2b52aee3a235376daed6232d71af20e3 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_1x1_conv.hpp @@ -0,0 +1,167 @@ +/******************************************************************************* +* Copyright 2021-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_BRGEMM_1X1_CONV_HPP +#define CPU_X64_JIT_BRGEMM_1X1_CONV_HPP + +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/memory_tracking.hpp" +#include "common/primitive.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_convolution_pd.hpp" +#include "cpu/platform.hpp" + +#include "cpu/x64/amx_tile_configure.hpp" +#include "cpu/x64/brgemm/brgemm.hpp" +#include "cpu/x64/brgemm/brgemm_containers.hpp" +#include "cpu/x64/cpu_barrier.hpp" +#include "cpu/x64/cpu_reducer.hpp" +#include "cpu/x64/jit_brgemm_conv_trans_kernel.hpp" +#include "cpu/x64/jit_brgemm_conv_utils.hpp" +#include "cpu/x64/jit_brgemm_post_ops.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +template +struct brgemm_1x1_convolution_fwd_t : public primitive_t { + struct pd_t : public cpu_convolution_fwd_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const typename pd_t::base_class *hint_fwd_pd) + : cpu_convolution_fwd_pd_t(adesc, attr, hint_fwd_pd) + , with_sum(false) + , sum_scale(0) {} + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("brgconv_1x1:", isa, ""), + brgemm_1x1_convolution_fwd_t); + + status_t init(engine_t *engine); + + std::shared_ptr brgs_; + bool with_sum; + float sum_scale; + + bool need_postwork; + int ic_chunks; + + jit_brgemm_conv_conf_t jcp_; + + protected: + bool arg_scales_ok() const { + std::vector supported_args + = {DNNL_ARG_SRC, DNNL_ARG_WEIGHTS, DNNL_ARG_DST}; + return attr_scales_ok(supported_args); + } + bool zero_points_ok() const { + // Only common zero points are supported -> mask should only be 0 + int mask_src = 0, mask_dst = 0; + attr()->zero_points_.get(DNNL_ARG_SRC, &mask_src); + attr()->zero_points_.get(DNNL_ARG_DST, &mask_dst); + return attr()->zero_points_.has_default_values(DNNL_ARG_WEIGHTS) + && mask_src == 0 && mask_dst == 0; + } + }; + + brgemm_1x1_convolution_fwd_t(const pd_t *apd) + : primitive_t(apd), bias_d(pd()->weights_md(1)) {} + + ~brgemm_1x1_convolution_fwd_t() {} + + status_t execute(const exec_ctx_t &ctx) const override { + execute_forward_all(ctx); + + if (pd()->wants_zero_pad_dst()) ctx.memory(DNNL_ARG_DST)->zero_pad(ctx); + + return status::success; + } + +protected: + status_t init(engine_t *engine) override; + +private: + // brgemm convolution execution context + struct brgemm_exec_ctx_t { + brgemm_exec_ctx_t(const exec_ctx_t &ctx, const pd_t *pd) + : src(CTX_IN_MEM(const char *, DNNL_ARG_SRC)) + , weights(CTX_IN_MEM(const char *, DNNL_ARG_WEIGHTS)) + , bias(CTX_IN_MEM(const char *, DNNL_ARG_BIAS)) + , dst(CTX_OUT_MEM(char *, DNNL_ARG_DST)) + , post_ops_binary_rhs_arg_vec(binary_injector::prepare_binary_args( + pd->attr()->post_ops_, ctx)) + , wsp_tile(ctx.get_scratchpad_grantor().template get( + memory_tracking::names::key_conv_amx_tile_buffer)) {} + const char *const __restrict src; + const char *const __restrict weights; + const char *const __restrict bias; + char *const __restrict dst; + const std::vector post_ops_binary_rhs_arg_vec; + char *const wsp_tile; + }; + + void maybe_rtus(int ithr, const char *__restrict src, + char *__restrict inp_buffer, uint8_t *__restrict inp_buffer_mask, + int g, int n, int icc, int od, int oh, int ow) const; + void exec_ker(const brgemm_exec_ctx_t &brgemm_ctx, int ithr, + brgemm_batch_element_t *const __restrict brg_batch, + char *const c_buffer, const char *inp_buffer, int g, int n, int ocb, + int od, int oh, int ow, int icc, int *last_brg_idx, + const float *oscales, int32_t src_zp_vals, int32_t *src_zp_comp, + int32_t *dst_zp_vals, int32_t *s8s8_compensation, + const float *dst_scales) const; + status_t execute_forward_all(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + static int get_brg_idx(bool do_initialization, int is_M_tail, + bool is_N_tail, bool is_K_tail) { + return (((int)do_initialization * 2 + (int)is_M_tail) * 2 + + (int)is_N_tail) + * 2 + + (int)is_K_tail; + } + + static int get_ker_po_idx(int is_M_tail, bool is_N_tail) { + return (int)is_M_tail * 2 + (int)is_N_tail; + } + + brgemm_containers::brgemm_kernel_container_t brg_kernels_ {16}; + brgemm_containers::brgemm_palette_container_t brgemm_palettes_ {16}; + + std::unique_ptr + rtus_kernel_; + + const memory_desc_wrapper bias_d; + + int ID, IH, IW, OD, OH, OW, SD, SH, SW; + size_t bia_dsz, acc_dsz, src_dsz, wei_dsz; + // const variables used for address calculations + dim_t src_w_sz, src_h_sz, src_d_sz, dst_w_sz, dst_h_sz, dst_d_sz; + dim_t wei_g_stride, wei_ic_stride, wei_ocb_stride; + dim_t wei_kw_stride, wei_kh_stride, wei_kd_stride; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_conv.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_conv.hpp new file mode 100644 index 0000000000000000000000000000000000000000..f329d47fd8aaa017417e43cc4a15386459e2dd7b --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_conv.hpp @@ -0,0 +1,296 @@ +/******************************************************************************* +* Copyright 2021-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_BRGEMM_CONV_HPP +#define CPU_X64_JIT_BRGEMM_CONV_HPP + +#include +#include + +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/memory_tracking.hpp" +#include "common/primitive.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_convolution_pd.hpp" +#include "cpu/platform.hpp" + +#include "cpu/x64/amx_tile_configure.hpp" +#include "cpu/x64/brgemm/brgemm.hpp" +#include "cpu/x64/brgemm/brgemm_containers.hpp" +#include "cpu/x64/cpu_barrier.hpp" +#include "cpu/x64/cpu_reducer.hpp" +#include "cpu/x64/jit_brgemm_conv_comp_pad_kernel.hpp" +#include "cpu/x64/jit_brgemm_conv_trans_kernel.hpp" +#include "cpu/x64/jit_brgemm_conv_utils.hpp" +#include "cpu/x64/jit_brgemm_post_ops.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +template +struct brgemm_convolution_fwd_t : public primitive_t { + + struct brgemm_thread_ctx_t; + + struct pd_t : public cpu_convolution_fwd_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const typename pd_t::hint_class *hint_fwd_pd) + : cpu_convolution_fwd_pd_t(adesc, attr, hint_fwd_pd) + , with_sum(false) {} + + ~pd_t() = default; + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("brgconv:", isa, ""), + brgemm_convolution_fwd_t); + + status_t init(engine_t *engine); + + int brgs_sz_; + std::shared_ptr + brgemm_descriptors_; + bool with_sum; + jit_brgemm_conv_conf_t jcp_; + + int ic_chunks; + bool need_postwork; + dim_t wei_g_stride, wei_ic_stride, wei_ocb_stride; + dim_t wei_kw_stride, wei_kh_stride, wei_kd_stride; + dim_t pbuf_w_sz, pbuf_h_sz, pbuf_d_sz; + + // batch sizes info for unrolled kernels + int bs_c; + // need custom hasher to use array as key in unordered_map + struct hasher { + size_t operator()(const std::array &a) const { + size_t seed = 0; + for (auto e : a) + seed = hash_combine(seed, e); + return seed; + } + }; + std::unordered_map, int, hasher> batchsizes; + + inline size_t get_brg_idx(int m, bool do_initialization, bool is_N_tail, + bool is_K_tail, int kd_b, int kd_e, int kh_b, int kh_e) const { + int bs_idx = 0; + if (jcp_.use_uker) { + const auto bs = batchsizes.find({kd_b, kd_e, kh_b, kh_e}); + if (bs == batchsizes.end()) { + assert(!"unregistered batch size"); + return 0; + } + bs_idx = bs->second; + } + return (((m * bs_c + bs_idx) * 2 + + static_cast(do_initialization)) + * 2 + + static_cast(is_N_tail)) + * 2 + + static_cast(is_K_tail); + } + + int get_any_brg_idx(bool is_N_tail, bool is_K_tail) const { + // return first defined brgemm_descriptor for specified parameters + const int M_end = nstl::max(jcp_.M, jcp_.M_tail); + const bool N_begin = (jcp_.N == jcp_.N_tail) ? false : is_N_tail; + const bool N_end = (jcp_.N == jcp_.N_tail) ? true : is_N_tail; + const bool K_begin = (jcp_.K == jcp_.K_tail) ? false : is_K_tail; + const bool K_end = (jcp_.K == jcp_.K_tail) ? true : is_K_tail; + for_(int m = 0; m < M_end; m++) + for_(bool i_init : {false, true}) + for_(bool i_N_tail : {N_begin, N_end}) + for_(bool i_K_tail : {K_begin, K_end}) + for (const auto &key_value_pair : batchsizes) { + const int kd_b = key_value_pair.first[0]; + const int kd_e = key_value_pair.first[1]; + const int kh_b = key_value_pair.first[2]; + const int kh_e = key_value_pair.first[3]; + const auto brg_idx = get_brg_idx( + m, i_init, i_N_tail, i_K_tail, kd_b, kd_e, kh_b, kh_e); + if ((*brgemm_descriptors_)[brg_idx]) return brg_idx; + } + return 0; + } + + inline int maybe_invert(int k, int K) const { + return use_inversion ? K - 1 - k : k; + }; + + void init_batch(int icc, const char *src_base, const char *wei_base, + int n_ic_blocks, int ic_block_s, int iid_b, int iih_b, + int iiw_b, const dim_t *const __restrict kw_top_vpads, + const dim_t *const __restrict kw_bottom_vpads, int kd_b, + int kd_e, int kh_b, int kh_e, int kw_b, int kw_e, int k_l, + brgemm_batch_element_t *brg_batch) const; + + void get_A_B(int icc, const char *src_base, const char *wei_base, + int ic_block_s, int iid_b, int iih_b, int iiw_b, int kd_b, + int kh_b, const void *&ptrA, const void *&ptrB) const; + + status_t add_brg_descriptor(int M, int i_N, int i_K, int i_init, + int kd_b, int kd_e, int kh_b, int kh_e); + + int ndims = 0; + + protected: + bool arg_scales_ok() const { + std::vector supported_args + = {DNNL_ARG_SRC, DNNL_ARG_WEIGHTS, DNNL_ARG_DST}; + return attr_scales_ok(supported_args); + } + + bool zero_points_ok() const { + // Only common zero points are supported -> mask should only be 0 + int mask_src = 0, mask_dst = 0; + attr()->zero_points_.get(DNNL_ARG_SRC, &mask_src); + attr()->zero_points_.get(DNNL_ARG_DST, &mask_dst); + return attr()->zero_points_.has_default_values(DNNL_ARG_WEIGHTS) + && mask_src == 0 && mask_dst == 0; + } + + int KD, KH, KW, EXT_KD, EXT_KH, EXT_KW, KS, KD_BLOCK, KH_BLOCK, + KW_BLOCK, KD_BLOCK_PAD, KH_BLOCK_PAD, ID, IH, IW, IDP, IHP, IWP, + OD, OH, OW, SD, SH, SW, FP, TP, LP, DD, DH, DW; + size_t acc_dsz, bia_dsz, src_dsz, wei_dsz, dst_dsz; + dim_t src_w_sz, src_h_sz, src_d_sz, dst_w_sz, dst_h_sz, dst_d_sz, + wei_ocb_sz; + dim_t adj_src_h_sz, adj_src_h_offset, src_iw_offset, src_d_offset, + wei_ic_offset, wei_kd_offset, wei_kh_offset, wei_kw_offset; + }; + + brgemm_convolution_fwd_t(const pd_t *apd); + + ~brgemm_convolution_fwd_t() = default; + + status_t execute(const exec_ctx_t &ctx) const override; + +protected: + status_t init(engine_t *engine) override; + +private: + // brgemm convolution execution context + struct brgemm_exec_ctx_t { + brgemm_exec_ctx_t(const exec_ctx_t &ctx, const pd_t *pd) + : src(CTX_IN_MEM(const char *, DNNL_ARG_SRC)) + , weights(CTX_IN_MEM(const char *, DNNL_ARG_WEIGHTS)) + , bias(CTX_IN_MEM(const char *, DNNL_ARG_BIAS)) + , dst(CTX_OUT_MEM(char *, DNNL_ARG_DST)) + , post_ops_binary_rhs_arg_vec(binary_injector::prepare_binary_args( + pd->attr()->post_ops_, ctx)) {} + const char *const __restrict src; + const char *const __restrict weights; + const char *const __restrict bias; + char *const __restrict dst; + const std::vector post_ops_binary_rhs_arg_vec; + }; + + inline static int get_ker_po_idx(int m, bool do_postwork, bool is_N_tail) { + return (m * 2 + static_cast(do_postwork)) * 2 + + static_cast(is_N_tail); + } + + inline static int get_inp_size( + int max_src_size, int dst_size, int k, int stride, int dilate) { + const auto res = nstl::min(max_src_size, + calculate_end_padding(0, dst_size, 0, stride, + calculate_extended_filter_size(k, dilate))); + return res; + } + + inline int maybe_invert_range(int k, int k_inv, int K) const { + return use_inversion ? K - k_inv : k; + }; + + void get_kw_range( + int ow, int &kw_s, int &kw_full_s, int &kw_full_e, int &kw_e) const; + void get_ow_range(int ow, int kw, int &ow_s, int &ow_e) const; + + void ker_base(brgemm_thread_ctx_t &btc) const; + void ker_trans(brgemm_thread_ctx_t &btc, char *inp_buffer) const; + void ker_vpad(brgemm_thread_ctx_t &btc) const; + + void perform_outwork(const brgemm_thread_ctx_t &btc, char *dst_base, + const char *bias_w, int ow, int g_oc, bool is_oc_tail, int ker_ow_s, + int ker_ow_f, int kd_l, int kh_l, bool maybe_do_init, + bool do_postwork, bool do_post_comp) const; + + void call_brgemm_kernel(const brgemm_thread_ctx_t &btc, + const brgemm_kernel_t *brg_ker, int batch_size, char *ptr_C, + char *ptr_D, const char *bias_w, int g_oc, bool do_postops, + int comp_ker_offs, bool do_only_comp) const; + + void maybe_conv_inp(int ithr, const char *__restrict src, + char *__restrict inp_buffer, uint8_t *__restrict inp_buffer_mask, + int g, int n, int icc, int odb, int ohb, int owb, int last_g, + int last_n, int last_icc, int last_odb, int last_ohb, + int last_owb) const; + + status_t add_po_kernel(brgemm_t *bcfg, int ker_idx, bool is_init); + void add_po_kernels(int i_N, int init_bcast_dim, int po_bcast_dim); + status_t add_brg_kernel(int M, int i_N, int i_K, int i_init, int kd_b, + int kd_e, int kh_b, int kh_e); + + status_t cal_compensation(const char *__restrict weights, + int32_t *src_zp_buffer, int32_t *s8s8_comp_buffer) const; + int get_comp_ker_idx(const int kd_b, const int kd_e, const int kh_b, + const int kh_e, const int kw_b, const int kw_e) const; + int get_comp_offset(const int g, const int ocb, const int ow, + const int kd_b, const int kd_e, const int kh_b, const int kh_e, + const int kw_b, const int kw_e) const; + inline const pd_t *pd() const { + return static_cast(primitive_t::pd().get()); + } + + brgemm_containers::brgemm_kernel_container_t brgemm_kernels_; + brgemm_containers::brgemm_palette_container_t brgemm_palettes_; + + std::vector>> kernels_po_; + std::unique_ptr + copy_to_pbuffer_; + std::unique_ptr comp_vpad_pbuffer_; + + size_t acc_dsz, bia_dsz, src_dsz, wei_dsz, dst_dsz; + + const memory_desc_wrapper bias_d; + + // pre - calculated values + std::vector owb_kw_top_vpads; + std::vector owb_kw_bottom_vpads; + std::vector kd_bs, kd_es, kh_bs, kh_es, kw_bs, kw_es; + + int KD, KH, KW, EXT_KD, EXT_KH, EXT_KW, KS, KD_BLOCK, KH_BLOCK, KW_BLOCK, + KD_BLOCK_PAD, KH_BLOCK_PAD, ID, IH, IW, IDP, IHP, IWP, OD, OH, OW, + SD, SH, SW, FP, TP, LP, DD, DH, DW; + dim_t src_w_sz, src_h_sz, src_d_sz, dst_w_sz, dst_h_sz, dst_d_sz; + dim_t ker_vpad_sz, comp_ocb_sz, comp_ker_sz, comp_kw_sz; + + bool need_compensation; + bool is_amx; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_conv_bwd.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_conv_bwd.hpp new file mode 100644 index 0000000000000000000000000000000000000000..c3a4d7767ab7dbc29f92a92f10d7713330ee845e --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_conv_bwd.hpp @@ -0,0 +1,80 @@ +/******************************************************************************* +* Copyright 2022-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_BRGEMM_CONV_BWD_HPP +#define CPU_X64_JIT_BRGEMM_CONV_BWD_HPP + +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/memory_tracking.hpp" +#include "common/primitive.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_convolution_pd.hpp" + +#include "cpu/x64/jit_brgemm_1x1_conv.hpp" +#include "cpu/x64/jit_brgemm_conv.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +template +struct brgemm_convolution_bwd_t : public primitive_t { + + struct pd_t : public cpu_convolution_bwd_data_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const typename pd_t::hint_class *hint_fwd_pd) + : cpu_convolution_bwd_data_pd_t(adesc, attr, hint_fwd_pd) {} + + ~pd_t() = default; + + DECLARE_COMMON_PD_T(name_.c_str(), brgemm_convolution_bwd_t); + + status_t init(engine_t *engine); + + std::shared_ptr fwd_pd_; + + private: + std::string name_ + = JIT_IMPL_NAME_HELPER("brg_fwd:", isa, "") + std::string("+"); + void init_name() { name_.append(fwd_pd_->name()); } + }; + + brgemm_convolution_bwd_t(const pd_t *apd) : primitive_t(apd) {}; + + ~brgemm_convolution_bwd_t() = default; + + status_t init(engine_t *engine) override; + + status_t execute(const exec_ctx_t &ctx) const override; + +private: + const pd_t *pd() const { + return static_cast(primitive_t::pd().get()); + } + std::shared_ptr fwd_p_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_conv_bwd_strided.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_conv_bwd_strided.hpp new file mode 100644 index 0000000000000000000000000000000000000000..4c323ab99805d2a29033abd9c0b383eb2e0471b7 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_conv_bwd_strided.hpp @@ -0,0 +1,217 @@ +/******************************************************************************* +* Copyright 2022-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_BRGEMM_CONV_BWD_STRIDED_HPP +#define CPU_X64_JIT_BRGEMM_CONV_BWD_STRIDED_HPP + +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/memory_tracking.hpp" +#include "common/primitive.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_convolution_pd.hpp" +#include "cpu/platform.hpp" + +#include "cpu/x64/amx_tile_configure.hpp" +#include "cpu/x64/brgemm/brgemm.hpp" +#include "cpu/x64/brgemm/brgemm_containers.hpp" +#include "cpu/x64/jit_brgemm_conv_bwd_trans_kernel.hpp" +#include "cpu/x64/jit_brgemm_conv_comp_pad_kernel.hpp" +#include "cpu/x64/jit_brgemm_post_ops.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +template +struct brgemm_convolution_bwd_strided_t : public primitive_t { + + struct pd_t : public cpu_convolution_bwd_data_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const typename pd_t::hint_class *hint_fwd_pd) + : cpu_convolution_bwd_data_pd_t(adesc, attr, hint_fwd_pd) {} + + ~pd_t() = default; + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("brgconv_strided:", isa, ""), + brgemm_convolution_bwd_strided_t); + + status_t init(engine_t *engine); + + int brgs_sz_; + std::shared_ptr brgs_; + + jit_brgemm_conv_conf_t jcp_; + // batch sizes info for unrolled kernels + int bs_c, first_bs; + std::vector batchsizes; + int get_brg_idx(int bs, int m, bool do_initialization, bool is_N_tail, + bool is_K_tail) const { + auto bs_idx = 0; + return (((m * bs_c + bs_idx) * 2 + + static_cast(do_initialization)) + * 2 + + static_cast(is_N_tail)) + * 2 + + static_cast(is_K_tail); + } + }; + + brgemm_convolution_bwd_strided_t(const pd_t *apd) + : primitive_t(apd), bias_d(pd()->weights_md(1)) {} + + ~brgemm_convolution_bwd_strided_t() = default; + + status_t execute(const exec_ctx_t &ctx) const override; + +protected: + status_t init(engine_t *engine) override; + +private: + // brgemm convolution execution context + struct brgemm_bwd_exec_ctx_t { + brgemm_bwd_exec_ctx_t(const exec_ctx_t &ctx, const pd_t *pd) + : diff_dst(CTX_IN_MEM(const char *, DNNL_ARG_DIFF_DST)) + , weights(CTX_IN_MEM(const char *, DNNL_ARG_WEIGHTS)) + , bias(CTX_IN_MEM(const char *, DNNL_ARG_BIAS)) + , dst(CTX_OUT_MEM(char *, DNNL_ARG_DIFF_SRC)) + , post_ops_binary_rhs_arg_vec(binary_injector::prepare_binary_args( + pd->attr()->post_ops_, ctx)) {} + const char *const __restrict diff_dst; + const char *const __restrict weights; + const char *const __restrict bias; + char *const __restrict dst; + const std::vector post_ops_binary_rhs_arg_vec; + }; + + struct brgemm_bwd_thread_ctx_t { + brgemm_bwd_thread_ctx_t(brgemm_bwd_exec_ctx_t &brgemm_ctx_, int ithr_, + brgemm_batch_element_t *__restrict brg_batch_, char *c_buffer_, + char *wsp_tile_) + : brgemm_ctx(brgemm_ctx_) + , ithr(ithr_) + , brg_batch(brg_batch_) + , c_buffer(c_buffer_) + , wsp_tile(wsp_tile_) {} + + brgemm_bwd_exec_ctx_t &brgemm_ctx; + int ithr; + brgemm_batch_element_t *__restrict brg_batch; + char *c_buffer; + char *wsp_tile; + int cur_brg_idx = -1; + int g, n, icb; + int id, idb, ih, ihb, iwb; + int occ; + int sw; + const float *oscales {nullptr}; + const float *dst_scales {nullptr}; + int32_t src_zp_vals; + int32_t *src_zp_comp_ptr; + int32_t *dst_zp_vals; + int32_t *s8s8_comp_ptr; + }; + + static int get_ker_po_idx(int m, bool do_postwork, bool is_N_tail) { + return (m * 2 + static_cast(do_postwork)) * 2 + + static_cast(is_N_tail); + } + + void get_kw_range(int iw, int iw_raw, int &kw_s, int &kw_full_s, + int &kw_full_e, int &kw_e) const; + void get_iw_range(int iw, int iw_raw, int kw, int &ow_s, int &ow_e) const; + + void ker_base(brgemm_bwd_thread_ctx_t &btc) const; + void ker_trans(brgemm_bwd_thread_ctx_t &btc, char *inp_buffer) const; + + void perform_outwork(char *dst_base, char *dst, char *c_buffer, + const char *bias_w, int od, int oh, int ow, int iw_raw, int g_oc, + bool is_oc_tail, int ker_ow_s, int ker_ow_f, int kd_l, int kh_l, + const void *post_ops_binary_rhs_arg_vec, const float *oscales, + int32_t src_zp_vals, int32_t *src_zp_ptr, int32_t *dst_zp_ptr, + int32_t *s8s8_compensation, bool maybe_do_init, bool do_postwork, + bool do_post_comp, const float *dst_scales) const; + + void call_brgemm_kernel(brgemm_bwd_thread_ctx_t &btc, int brg_idx, + int batch_size, char *ptr_C, char *ptr_D, const char *bias_w, + int g_ic, bool do_postops, const void *binary_post_ops_rhs, + int32_t src_zp_vals, int32_t *src_zp_ptr, int32_t *dst_zp_ptr, + int32_t *s8s8_comp, bool do_only_comp, + bool is_first_call_postops) const; + + void maybe_trans_inp(int ithr, const char *__restrict input, + char *__restrict inp_buffer, uint8_t *__restrict inp_buffer_mask, + int g, int n, int icc, int odb, int ohb, int owb, int last_g, + int last_n, int last_icc, int last_odb, int last_ohb, + int last_owb) const; + + status_t add_po_kernel(brgemm_t *bcfg, int ker_idx, bool is_init); + void add_po_kernels(int i_N, int init_bcast_dim, int po_bcast_dim); + status_t add_brg_kernel(int bs, int M, int i_N, int i_K, int i_init); + + void cal_compensation(const char *__restrict weights, + int32_t *src_zp_buffer, int32_t *s8s8_comp_buffer) const; + int get_comp_ker_idx(const int kd_b, const int kd_e, const int kh_b, + const int kh_e, const int kw_b, const int kw_e) const; + int get_comp_offset(const int g, const int icb, const int iw, + const int kd_b, const int kd_e, const int kh_b, const int kh_e, + const int kw_b, const int kw_e) const; + void create_kernels(); + + const pd_t *pd() const { + return static_cast(primitive_t::pd().get()); + } + + brgemm_containers::brgemm_kernel_container_t brg_kernels_; + brgemm_containers::brgemm_palette_container_t brgemm_palettes_; + + std::vector>> kernels_po_; + std::unique_ptr + copy_to_pbuffer_; + std::unique_ptr comp_vpad_pbuffer_; + + size_t acc_dsz, bia_dsz, src_dsz, wei_dsz, dst_dsz; + + const memory_desc_wrapper bias_d; + + // precalculated values + std::vector kd_bs, kd_es, kh_bs, kh_es, kw_bs, kw_es; + + int KD, KH, KW, EXT_KD, EXT_KH, EXT_KW, KS, KD_BLOCK, KH_BLOCK, KW_BLOCK, + KD_BLOCK_PAD, KH_BLOCK_PAD, ID, IH, IW, ODP, OHP, OWP, OD, OH, OW, + SD, SH, SW, FP, TP, LP, DD, DH, DW; + dim_t src_w_sz, src_h_sz, src_d_sz, dst_w_sz, dst_h_sz, dst_d_sz, wei_oc_sz, + wei_kw_sz, wei_kh_sz, wei_kd_sz, wei_icb_sz; + dim_t pbuf_w_sz, pbuf_h_sz, pbuf_d_sz; + dim_t comp_icb_sz, comp_ker_sz, comp_kw_sz; + + int oc_chunks; + bool need_postwork; + bool need_compensation; + bool is_amx; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_conv_bwd_trans_kernel.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_conv_bwd_trans_kernel.hpp new file mode 100644 index 0000000000000000000000000000000000000000..9425d3da7c61f2427687eacddbc38b7157fc15c9 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_conv_bwd_trans_kernel.hpp @@ -0,0 +1,102 @@ +/******************************************************************************* +* Copyright 2022 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_BRGEMM_CONV_BWD_TRANS_KERNEL_HPP +#define CPU_X64_JIT_BRGEMM_CONV_BWD_TRANS_KERNEL_HPP + +#include "cpu/x64/jit_generator.hpp" +#include "cpu/x64/jit_primitive_conf.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +namespace jit_avx512_core_brgemm_conv_bwd_trans_kernel { +struct jit_brgemm_conv_bwd_trans_kernel_call_s { + const void *src; + const void *dst; + size_t iwb; + size_t oc; + size_t t_pad; + size_t h_count; + size_t b_pad; +}; + +struct jit_avx512_core_brgemm_conv_bwd_trans_kernel_t : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS( + jit_avx512_core_brgemm_conv_bwd_trans_kernel_t) + + using reg64_t = const Xbyak::Reg64; + + jit_avx512_core_brgemm_conv_bwd_trans_kernel_t( + const jit_brgemm_conv_conf_t &ajcp, const char *name = jit_name()); + +protected: + jit_brgemm_conv_conf_t jcp; + dim_t inp_dsz; + dim_t oc_block_sz; + dim_t ow_size, dst_w_block, dst_stride; + dim_t dst_h_offset, dst_w_offset; + dim_t VL, n_vec, n_tail_vec; + const reg64_t inp_ptr = r15; + const reg64_t dst_ptr = r14; + + const reg64_t aux_inp_ptr = r13; + const reg64_t aux_dst_ptr = r12; + + const reg64_t reg_hc = r10; + + const reg64_t reg_oc = r9; + + const reg64_t reg_iwb = rdx; + + const reg64_t kh_over = r8; + const reg64_t reg_t_pad = rax; + const reg64_t reg_b_pad = rbx; + + const reg64_t reg_tmp = rsi; + + const Xbyak::Opmask ktail_mask = Xbyak::Opmask(2); + const Xbyak::Opmask kblock_tail_mask = Xbyak::Opmask(3); + + const Xbyak::Zmm zmm_tmp = Xbyak::Zmm(0); + const Xbyak::Zmm zmm_zero = Xbyak::Zmm(1); + + void load(const Xbyak::Xmm &x, const Xbyak::Address &addr); + + void store(const Xbyak::Address &addr, const Xbyak::Xmm &x); + + void zero_oc_block(bool is_oc_tail, dim_t dst_off); + void copy_oc_block( + bool is_oc_tail, dim_t inp_off, dim_t dst_off, bool do_load); + void generate() override; + void copy_iw_block(bool is_oc_tail); + void copy_iw_block_body(int lpad, int iw_len, int ow_len, bool is_oc_tail); + + int inp_w(int out_w) const; + int inp_w_start(int iwb) const; +}; + +} // namespace jit_avx512_core_brgemm_conv_bwd_trans_kernel +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_conv_bwd_utils.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_conv_bwd_utils.hpp new file mode 100644 index 0000000000000000000000000000000000000000..dea1cf1a7a5512c4ac25d7586e43dd685d9fd9fc --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_conv_bwd_utils.hpp @@ -0,0 +1,75 @@ +/******************************************************************************* +* Copyright 2022-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_BRGEMM_CONV_BWD_UTILS_HPP +#define CPU_X64_JIT_BRGEMM_CONV_BWD_UTILS_HPP + +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/memory_tracking.hpp" + +#include "cpu/cpu_convolution_pd.hpp" +#include "cpu/cpu_engine.hpp" +#include "cpu/platform.hpp" + +#include "cpu/x64/brgemm/brgemm.hpp" +#include "cpu/x64/jit_primitive_conf.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +namespace brgemm_convolution_bwd_utils { + +constexpr size_t P4K = 4096; + +bool is_amx(cpu_isa_t isa); + +void set_k_range(int P, int D, int S, dim_t i, dim_t O, int K, int &k_s, + int &k_f, bool is_w = false); + +void get_iw_range(const jit_brgemm_conv_conf_t &jcp, int iw, int iw_raw, int kw, + int &iw_s, int &M_without_overflow); + +void get_kw_range(const jit_brgemm_conv_conf_t &jcp, int iw, int iw_raw, + int &kw_s, int &kw_full_s, int &kw_full_f, int &kw_f); + +dim_t precalculate_comp_pad_kernels(const jit_brgemm_conv_conf_t &jcp, + std::vector *kd_bs = nullptr, + std::vector *kd_es = nullptr, + std::vector *kh_bs = nullptr, + std::vector *kh_es = nullptr, + std::vector *kw_bs = nullptr, + std::vector *kw_es = nullptr); + +status_t init_conf(jit_brgemm_conv_conf_t &jcp, cpu_isa_t isa, + const convolution_desc_t &cd, memory_desc_t &src_md, + memory_desc_t &weights_md, memory_desc_t &dst_md, + memory_desc_t &bias_md, primitive_attr_t &attr, int nthreads, + bool enable_postops); + +void init_scratchpad(memory_tracking::registrar_t &scratchpad, + const jit_brgemm_conv_conf_t &jcp); + +} // namespace brgemm_convolution_bwd_utils + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_conv_bwd_w.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_conv_bwd_w.hpp new file mode 100644 index 0000000000000000000000000000000000000000..2c96c77d0e95fcc6a2bc1899a432b428af534d1d --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_conv_bwd_w.hpp @@ -0,0 +1,211 @@ +/******************************************************************************* +* Copyright 2022-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_BRGEMM_CONV_BWD_W_HPP +#define CPU_X64_JIT_BRGEMM_CONV_BWD_W_HPP + +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/memory_tracking.hpp" +#include "common/primitive.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_convolution_pd.hpp" +#include "cpu/platform.hpp" + +#include "cpu/x64/amx_tile_configure.hpp" +#include "cpu/x64/brgemm/brgemm.hpp" +#include "cpu/x64/brgemm/brgemm_containers.hpp" +#include "cpu/x64/cpu_barrier.hpp" +#include "cpu/x64/cpu_reducer.hpp" +#include "cpu/x64/jit_brgemm_conv_comp_pad_kernel.hpp" +#include "cpu/x64/jit_brgemm_conv_trans_kernel.hpp" +#include "cpu/x64/jit_brgemm_conv_utils.hpp" +#include "cpu/x64/jit_brgemm_post_ops.hpp" + +#include "cpu/x64/jit_avx512_core_amx_conv_kernel.hpp" +#include "cpu/x64/jit_transpose_utils.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +struct brgemm_convolution_bwd_weights_t : public primitive_t { + struct pd_t : public cpu_convolution_bwd_weights_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const convolution_fwd_pd_t *hint_fwd_pd) + : cpu_convolution_bwd_weights_pd_t(adesc, attr, hint_fwd_pd) + , jcp_() + , brgs_sz_(0) + , bs_c(0) {} + + ~pd_t() = default; + + DECLARE_COMMON_PD_T( + JIT_IMPL_NAME_HELPER("brgconv_bwd_w:", jcp_.isa, ""), + brgemm_convolution_bwd_weights_t); + + status_t init(engine_t *engine); + + jit_brgemm_conv_conf_t jcp_; + jit_conv_conf_t jit_jcp_; + void copy2jit_jcp(); + + int brgs_sz_; + std::shared_ptr brgs_; + + int bs_c; + std::vector batchsizes; + bool are_empty_bs {false}; + + int get_brg_idx(int bs, int m, bool do_initialization, bool is_N_tail, + bool is_K_tail) const { + auto my_bs = jcp_.var_bs ? 1 : bs; + auto bs_idx = jcp_.use_uker ? batchsizes[my_bs] : 0; + assert(bs_idx >= 0); + return (((m * bs_c + bs_idx) * 2 + + static_cast(do_initialization)) + * 2 + + static_cast(is_N_tail)) + * 2 + + static_cast(is_K_tail); + } + inline int filter_w_to_src(int kw) const { + return kw * (jcp_.dilate_w + 1); + } + inline int filter_h_to_src(int kh) const { + return kh * (jcp_.dilate_h + 1) - jcp_.t_pad; + } + inline int filter_d_to_src(int kd) const { + return kd * (jcp_.dilate_d + 1) - jcp_.f_pad; + } + inline int get_start_ih(int kh, int oh_s) const { + const auto real_ih = filter_h_to_src(kh) + oh_s * jcp_.stride_h; + return utils::saturate(0, jcp_.ih, + real_ih + + utils::rnd_up( + nstl::max(0, -real_ih), jcp_.stride_h)); + } + inline int get_finish_ih(int kh, int oh_e) const { + return utils::saturate(0, jcp_.ih, + filter_h_to_src(kh) + (oh_e - 1) * jcp_.stride_h + 1); + } + inline int get_start_id(int kd, int od_s) const { + const auto real_id = filter_d_to_src(kd) + od_s * jcp_.stride_d; + return utils::saturate(0, jcp_.id, + real_id + + utils::rnd_up( + nstl::max(0, -real_id), jcp_.stride_d)); + } + inline int get_finish_id(int kd, int od_e) const { + return utils::saturate(0, jcp_.id, + filter_d_to_src(kd) + (od_e - 1) * jcp_.stride_d + 1); + } + + inline int get_finish_oh(int oh_s, int start, int end) const { + int work_rem = end - start; + return (oh_s + work_rem > jcp_.oh ? jcp_.oh : oh_s + work_rem); + } + inline int get_finish_od(int od_s, int start, int end) const { + int work_rem = end - start; + return (od_s + work_rem > jcp_.od ? jcp_.od : od_s + work_rem); + } + }; + + brgemm_convolution_bwd_weights_t(const pd_t *apd) : primitive_t(apd) {} + + typedef typename prec_traits::type src_data_t; + typedef typename prec_traits::type diff_dst_data_t; + + status_t init(engine_t *engine) override; + + status_t execute(const exec_ctx_t &ctx) const override { + execute_backward_weights(ctx); + return status::success; + } + +private: + struct thread_info_t; + + void execute_backward_weights(const exec_ctx_t &ctx) const; + void prepare_scratchpad_data(const exec_ctx_t &ctx) const; + void compute_diff_weights_2d(thread_info_t *) const; + void compute_diff_weights_3d(thread_info_t *) const; + void reduce_and_convert_diff_weights_and_bias(thread_info_t *) const; + void store_in_vnni_format(thread_info_t *) const; + + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr> acc_ker_; + + std::unique_ptr diff_wei_trans_kernel_; + std::unique_ptr trans_kernel_; + std::unique_ptr trans_dst_kernel_; + std::unique_ptr diff_bias_kernel_; + + brgemm_containers::brgemm_kernel_container_t brg_kernels_; + brgemm_containers::brgemm_palette_container_t brgemm_palettes_; + + status_t add_brg_kernel(int bs, int M, int i_N, int i_K, int i_init); + void call_brgemm_kernel( + thread_info_t &btc, int brg_idx, int batch_size, void *ptr_C) const; + inline dim_t wei_offset_int( + int g, int oc_b, int ic_b, int kd, int kh, int kw) const { + const auto &jcp = pd()->jcp_; + const dim_t const_extra_offset = jcp.ic_block * jcp.oc_block; + dim_t extra_offset + = ((kd * jcp.kh + kh) * jcp.kw + kw) * const_extra_offset; + return (dim_t)((g * jcp.nb_oc + oc_b) * jcp.nb_ic + ic_b) * jcp.kd + * jcp.kh * jcp.kw * jcp.ic_block * jcp.oc_block + + extra_offset; + } + + inline dim_t wei_offset_int(int g, int oc_b, int ic_b, int kX) const { + const auto &jcp = pd()->jcp_; + const dim_t const_extra_offset = jcp.kw * jcp.ic_block * jcp.oc_block; + dim_t extra_offset = (jcp.ndims == 5) ? kX * jcp.kh * const_extra_offset + : kX * const_extra_offset; + return (dim_t)((g * jcp.nb_oc + oc_b) * jcp.nb_ic + ic_b) * jcp.kd + * jcp.kh * jcp.kw * jcp.ic_block * jcp.oc_block + + extra_offset; + } + + inline dim_t wei_offset_ext(int g, int oc_b, int ic_b, int kX) const { + const auto &jcp = pd()->jcp_; + const int nb_ic = utils::div_up(jcp.ic, 2 * jcp.ic_block); + const dim_t const_extra_offset + = jcp.kw * jcp.ic_block * jcp.oc_block * 2; + dim_t extra_offset = (jcp.ndims == 5) ? kX * jcp.kh * const_extra_offset + : kX * const_extra_offset; + return (dim_t)((g * jcp.nb_oc + oc_b) * nb_ic + ic_b) * jcp.kd * jcp.kh + * jcp.kw * jcp.ic_block * jcp.oc_block * 2 + + extra_offset; + } + + inline int get_end(int start, int step, int limit) const { + return nstl::min(start + step, limit); + } +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_conv_comp_pad_kernel.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_conv_comp_pad_kernel.hpp new file mode 100644 index 0000000000000000000000000000000000000000..0e79ac7d6ccad652ce228dca9445607732480327 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_conv_comp_pad_kernel.hpp @@ -0,0 +1,124 @@ +/******************************************************************************* +* Copyright 2022-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_BRGEMM_CONV_COMP_PAD_KERNEL_HPP +#define CPU_X64_JIT_BRGEMM_CONV_COMP_PAD_KERNEL_HPP + +#include "cpu/x64/jit_generator.hpp" +#include "cpu/x64/jit_primitive_conf.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +namespace jit_uni_brgemm_conv_comp_pad_kernel { +struct jit_brgemm_conv_comp_pad_call_s { + const void *ptr_in; + void *ptr_zp_out; + void *ptr_cp_out; + size_t kw_l; + size_t kh_l; + size_t kd_l; +}; + +// Kernel is unified to work with fwd and bwd_d conv +// Variables with "ic" and "oc" are named from perspective of fwd +// For bwd_d "ic" and "oc" are swapped +template +struct jit_uni_brgemm_conv_comp_pad_kernel_t : public jit_generator { + + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_uni_brgemm_conv_comp_pad_kernel_t) + + using reg64_t = const Xbyak::Reg64; + + jit_uni_brgemm_conv_comp_pad_kernel_t(const jit_brgemm_conv_conf_t &ajcp); + + ~jit_uni_brgemm_conv_comp_pad_kernel_t() = default; + +protected: + static constexpr bool is_ymm_ = std::is_same::value; + + jit_brgemm_conv_conf_t jcp_; + const int inp_dsz_; + const int out_dsz_; + const size_t nb_ic_; + const size_t inp_ic_sz_; + const size_t inp_kw_sz_; + const size_t inp_kh_sz_; + const size_t inp_kd_sz_; + const int isa_max_regs; + + // Register decomposition + const reg64_t param1 = abi_param1; + const reg64_t reg_in = r15; + const reg64_t reg_comp_out = r14; + const reg64_t reg_zp_comp_out = r13; + + const reg64_t reg_kd_l = r12; + const reg64_t reg_kh_l = r11; + const reg64_t reg_kw_l = r10; + const reg64_t reg_icb = r9; + + const reg64_t reg_aux_in = r8; + const reg64_t reg_aux_kh_in = rbx; + const reg64_t reg_aux_kw_in = rsi; + const reg64_t reg_tmp = rax; + + Vmm vmm_tmp = Vmm(isa_max_regs - 1); + Vmm vmm_one_bytes = Vmm(isa_max_regs - 2); + Vmm vmm_zp_shift = Vmm(isa_max_regs - 3); + Vmm vmm_cp_shift = Vmm(isa_max_regs - 4); + + Xbyak::Zmm zmm_one_words = Xbyak::Zmm(27); + Xbyak::Zmm zmm_int8_temp = Xbyak::Zmm(26); + + const int last_ic_block_ = 4; + const int m_block2_ = vreg_traits::vlen / sizeof(int32_t); + static constexpr int max_oc_block_ = 64; + const int n_max_regs_ = max_oc_block_ / m_block2_; + + const Vmm &vmm_tmp_1() const noexcept { return vmm_tmp; } + + Vmm accum(const int n_block, const int m, const int n) const; + size_t out_oc_offset(const int n) const; + size_t inp_ic_offset( + const int m_block, const int icb, const int m, const int n) const; + int compute_ic_step( + const int m_max_regs, const int m_block, const int n_block) const; + + void store_accumulators(const int m_block, const int n_block); + void zero_accumulators(const int m_block, const int n_block); + void compute(const int ic_step, const int m_block, const int n_block, + const int m_tail, const bool is_mb_tail); + void icb_loop(const int icb, const int icb_tail, const int ic_step, + const int m_block, const int mb_tail, const int n_block); + void khw_loop(const int icb, const int icb_tail, const int ic_step, + const int m_block, const int mb_tail, const int n_block); + void load_params(); + void generate() override; +}; + +} // namespace jit_uni_brgemm_conv_comp_pad_kernel + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_conv_trans_kernel.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_conv_trans_kernel.hpp new file mode 100644 index 0000000000000000000000000000000000000000..92040bc3ec7f33badff6b43c628bc4274e23b4d2 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_conv_trans_kernel.hpp @@ -0,0 +1,116 @@ +/******************************************************************************* +* Copyright 2021-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_BRGEMM_CONV_TRANS_KERNEL_HPP +#define CPU_X64_JIT_BRGEMM_CONV_TRANS_KERNEL_HPP + +#include "cpu/x64/jit_generator.hpp" +#include "cpu/x64/jit_primitive_conf.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +namespace jit_avx512_core_brgemm_conv_trans_kernel { +struct jit_brgemm_conv_trans_kernel_call_s { + const void *src; + const void *dst; + size_t owb; + size_t ic; + size_t t_pad; + size_t h_count; + size_t b_pad; +}; + +struct jit_avx512_core_brgemm_conv_trans_kernel_t : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_brgemm_conv_trans_kernel_t) + + using reg64_t = const Xbyak::Reg64; + + jit_avx512_core_brgemm_conv_trans_kernel_t( + const jit_brgemm_conv_conf_t &ajcp, const char *name = jit_name()); + + static int dst_w(const jit_brgemm_conv_conf_t &ajcp, int out_w); + +protected: + jit_brgemm_conv_conf_t jcp; + dim_t inp_dsz; + dim_t ic_block_sz; + dim_t iw_size, dst_w_block, dst_stride; + dim_t dst_h_offset, dst_w_offset; + dim_t VL, n_vec, n_tail_vec; + const reg64_t inp_ptr = r15; + const reg64_t dst_ptr = r14; + + const reg64_t aux_inp_ptr = r13; + const reg64_t aux_dst_ptr = r12; + + const reg64_t reg_hc = r10; + + const reg64_t reg_ic = r9; + + const reg64_t reg_owb = rdx; + + const reg64_t kh_over = r8; + const reg64_t reg_t_pad = rax; + const reg64_t reg_b_pad = rbx; + + const reg64_t reg_tmp = rsi; + + const Xbyak::Opmask ktail_mask = Xbyak::Opmask(2); + const Xbyak::Opmask kblock_tail_mask = Xbyak::Opmask(3); + + const Xbyak::Zmm zmm_tmp = Xbyak::Zmm(0); + const Xbyak::Zmm zmm_zero = Xbyak::Zmm(1); + + void load(const Xbyak::Xmm &x, const Xbyak::Address &addr); + + void store(const Xbyak::Address &addr, const Xbyak::Xmm &x); + + void zero_ic_block(bool is_ic_tail, dim_t dst_off); + void copy_ic_block( + bool is_ic_tail, dim_t inp_off, dim_t dst_off, bool do_load); + void generate() override; + void copy_ow_block(bool is_ic_tail); + void copy_ow_block_body(int lpad, int ow_len, int iw_len, bool is_ic_tail); + + int inp_w(int out_w) const; + int inp_w(int out_w, int kw) const; + int inp_w_start(int owb) const; +}; + +struct jit_avx512_core_brgemm_conv_rtus_kernel_t + : jit_avx512_core_brgemm_conv_trans_kernel_t { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_brgemm_conv_rtus_kernel_t) + + jit_avx512_core_brgemm_conv_rtus_kernel_t( + const jit_brgemm_conv_conf_t &ajcp); + +private: + void generate() override; +}; + +} // namespace jit_avx512_core_brgemm_conv_trans_kernel + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_conv_utils.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_conv_utils.hpp new file mode 100644 index 0000000000000000000000000000000000000000..2614479e2ec06b48d4e59a9ef0ab51cf62f28e34 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_conv_utils.hpp @@ -0,0 +1,75 @@ +/******************************************************************************* +* Copyright 2021-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_BRGEMM_CONV_UTILS_HPP +#define CPU_X64_JIT_BRGEMM_CONV_UTILS_HPP + +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/memory_tracking.hpp" + +#include "cpu/cpu_convolution_pd.hpp" +#include "cpu/cpu_engine.hpp" +#include "cpu/platform.hpp" + +#include "cpu/x64/brgemm/brgemm.hpp" +#include "cpu/x64/jit_primitive_conf.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +namespace brgemm_convolution_utils { + +constexpr size_t P4K = 4096; + +bool is_amx(cpu_isa_t isa); +bool uses_batch_elements( + brgemm_batch_kind_t brg_type, conv_brgemm_exec_type_t exec_type); + +status_t init_conf(jit_brgemm_conv_conf_t &jcp, cpu_isa_t isa, + const convolution_desc_t &cd, memory_desc_t &src_md, + memory_desc_t &weights_md, memory_desc_t &dst_md, + memory_desc_t &bias_md, primitive_attr_t &attr, int nthreads); + +status_t init_1x1_conf(jit_brgemm_conv_conf_t &jcp, cpu_isa_t isa, + const convolution_desc_t &cd, memory_desc_t &src_md, + memory_desc_t &weights_md, memory_desc_t &dst_md, + memory_desc_t &bias_md, primitive_attr_t &attr, int nthreads); + +void set_amx_wsp_per_thread(jit_brgemm_conv_conf_t &jcp); + +void init_scratchpad(memory_tracking::registrar_t &scratchpad, + const jit_brgemm_conv_conf_t &jcp); + +status_t init_conf_bwd_w(jit_brgemm_conv_conf_t &jcp, + const convolution_desc_t &cd, memory_desc_t &src_md, + memory_desc_t &diff_weights_md, memory_desc_t &diff_bias_md, + memory_desc_t &diff_dst_md, primitive_attr_t &attr, int nthreads); + +status_t init_scratchpad_bwd_w(memory_tracking::registrar_t &scratchpad, + const jit_brgemm_conv_conf_t &jcp, memory_desc_t &src_md, + memory_desc_t &diff_weights_md, memory_desc_t &diff_dst_md); + +} // namespace brgemm_convolution_utils + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_deconv.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_deconv.hpp new file mode 100644 index 0000000000000000000000000000000000000000..1f8fc80cc4f16372ebfe51cc3d3840d262bbdf2e --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_deconv.hpp @@ -0,0 +1,107 @@ +/******************************************************************************* +* Copyright 2022-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_BRGEMM_DECONV_HPP +#define CPU_X64_JIT_BRGEMM_DECONV_HPP + +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/memory_tracking.hpp" +#include "common/primitive.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_deconvolution_pd.hpp" + +#include "cpu/x64/jit_brgemm_1x1_conv.hpp" +#include "cpu/x64/jit_brgemm_conv.hpp" +#include "cpu/x64/jit_brgemm_conv_bwd_strided.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +template +struct brgemm_deconvolution_fwd_t : public primitive_t { + + struct pd_t : public cpu_deconvolution_fwd_pd_t { + pd_t(const deconvolution_desc_t *adesc, const primitive_attr_t *attr, + const typename pd_t::hint_class *hint_fwd_pd) + : cpu_deconvolution_fwd_pd_t(adesc, attr, hint_fwd_pd) {} + + pd_t(const pd_t &other) + : cpu_deconvolution_fwd_pd_t(other) + , conv_pd_(other.conv_pd_->clone()) + , has_strides_(other.has_strides_) + , name_(other.name_) {} + + ~pd_t() = default; + + DECLARE_COMMON_PD_T(name_.c_str(), brgemm_deconvolution_fwd_t); + + status_t init(engine_t *engine); + + bool post_ops_ok() const { + return attr()->post_ops_.find(primitive_kind::convolution) == -1; + } + + bool zero_points_ok() const { + using namespace data_type; + int mask_src = 0, mask_dst = 0; + attr()->zero_points_.get(DNNL_ARG_SRC, &mask_src); + attr()->zero_points_.get(DNNL_ARG_DST, &mask_dst); + + return IMPLICATION(!utils::one_of(src_md()->data_type, s8, u8), + attr()->zero_points_.has_default_values()) + && attr()->zero_points_.has_default_values(DNNL_ARG_WEIGHTS) + && (mask_src == 0 || mask_src == 1 << 1) + && (mask_dst == 0 || mask_dst == 1 << 1); + } + + std::shared_ptr conv_pd_; + bool has_strides_ = false; + + private: + std::string name_ + = JIT_IMPL_NAME_HELPER("brg_conv:", isa, "") + std::string("+"); + + void init_name() { name_.append(conv_pd_->name()); } + }; + + brgemm_deconvolution_fwd_t(const pd_t *apd) : primitive_t(apd) {}; + + ~brgemm_deconvolution_fwd_t() = default; + + status_t init(engine_t *engine) override; + + status_t execute(const exec_ctx_t &ctx) const override; + +private: + const pd_t *pd() const { + return static_cast(primitive_t::pd().get()); + } + + std::shared_ptr conv_p_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_inner_product.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_inner_product.hpp new file mode 100644 index 0000000000000000000000000000000000000000..f46df1c5e018a00125a1a2a7efe8484ef8edd3e9 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_inner_product.hpp @@ -0,0 +1,601 @@ +/******************************************************************************* +* Copyright 2020-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_BRGEMM_INNER_PRODUCT_HPP +#define CPU_X64_BRGEMM_INNER_PRODUCT_HPP + +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/memory_tracking.hpp" +#include "common/primitive.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_inner_product_pd.hpp" + +#include "cpu/x64/amx_tile_configure.hpp" +#include "cpu/x64/brgemm/brgemm.hpp" +#include "cpu/x64/brgemm/brgemm_containers.hpp" +#include "cpu/x64/cpu_barrier.hpp" +#include "cpu/x64/cpu_reducer.hpp" +#include "cpu/x64/jit_brgemm_inner_product_utils.hpp" +#include "cpu/x64/jit_brgemm_post_ops.hpp" +#include "cpu/x64/jit_brgemm_transpose_utils.hpp" +#include "cpu/x64/jit_transpose_utils.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +template +struct brgemm_inner_product_fwd_t : public primitive_t { + struct pd_t : public cpu_inner_product_fwd_pd_t { + pd_t(const inner_product_desc_t *adesc, const primitive_attr_t *attr, + const typename pd_t::base_class *hint_fwd_pd) + : cpu_inner_product_fwd_pd_t(adesc, attr, hint_fwd_pd) {} + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("brgemm:", isa, ""), + brgemm_inner_product_fwd_t); + + status_t init(engine_t *engine) { + using namespace utils; + using namespace data_type; + + auto src_dt = invariant_src_md()->data_type; + auto dst_dt = invariant_dst_md()->data_type; + auto wei_dt = invariant_wei_md()->data_type; + const bool is_int8 = one_of(src_dt, u8, s8); + + using skip_mask_t = primitive_attr_t::skip_mask_t; + auto skip_mask = skip_mask_t::post_ops | skip_mask_t::sum_dt; + if (is_int8) skip_mask |= skip_mask_t::scales_runtime; + + bool ok = is_fwd() && mayiuse(isa) + && expect_data_types(src_dt, wei_dt, data_type::undef, + dst_dt, data_type::undef) + && IMPLICATION(with_bias() && is_int8, + one_of(bias_md_.data_type, f32, bf16, s32, s8, u8)) + && IMPLICATION(with_bias() && !is_int8, + one_of(bias_md_.data_type, f32, src_dt)) + && attr()->has_default_values(skip_mask, dst_dt) + && attr()->post_ops_.check_sum_consistency(dst_dt, is_int8) + && !has_zero_dim_memory() && arg_scales_ok(); + if (!ok) return status::unimplemented; + + CHECK(jbgp_.init_conf(isa, *desc(), src_md_, weights_md_, dst_md_, + bias_md_, attr_, dnnl_get_max_threads())); + + bool are_post_ops_applicable = one_of(true, jbgp_.with_sum, + jbgp_.with_bias, jbgp_.with_scales, jbgp_.with_eltwise, + jbgp_.with_binary, jbgp_.acc_dt != jbgp_.dst_dt, + jbgp_.req_s8s8_compensation, jbgp_.with_dst_scales); + + const float alpha = 1.0; + const float beta = 1.0; + const float beta_init = 0.0; + + for_(int i_bs = 0; i_bs < 2; i_bs++) + for_(int i_init = 0; i_init < 2; i_init++) + for_(int i_M = 0; i_M < 2; i_M++) + for_(int i_N = 0; i_N < 2; i_N++) + for (int i_K = 0; i_K < 2; i_K++) { + auto vbeta = (i_init) ? beta_init : beta; + auto vM = (i_M) ? jbgp_.M_tail : jbgp_.M; + auto vN = (i_N) ? jbgp_.N_tail : jbgp_.N; + auto vK = (i_K) ? jbgp_.K_tail : jbgp_.K; + int bs = get_brg_batchsize(i_bs, i_K); + int idx = get_brg_kernel_idx(i_bs, i_init, i_M, i_N, i_K, bs); + if (idx < 0) continue; + brgemm_t &brg = brg_descs_[idx]; + CHECK(brgemm_desc_init(&brg, isa, jbgp_.brg_type, jbgp_.src_dt, + jbgp_.wei_dt, false, false, brgemm_row_major, alpha, + vbeta, jbgp_.LDA, jbgp_.LDB, jbgp_.LDC, vM, vN, vK)); + + auto LDD = jbgp_.oc_without_padding; + CHECK(brgemm_desc_set_postops( + &brg, attr(), &dst_md_, LDD, jbgp_.bia_dt)); + + if (are_post_ops_applicable && jbgp_.nthr_ic_b > 1) { + brgemm_attr_t brgattr; + brgattr.generate_skip_accumulation = true; + CHECK(brgemm_desc_set_attr(&brg, brgattr)); + } + if (jbgp_.is_amx) { + brgemm_attr_t brgattr; + brgattr.max_bs = bs; + brgattr.wary_tail_read = false; + brgattr.hint_expected_A_size = jbgp_.mb * jbgp_.ic; + brgattr.hint_expected_B_size = jbgp_.oc * jbgp_.ic; + brgattr.hint_expected_C_size = jbgp_.mb * jbgp_.oc; + brgattr.hint_innermost_loop = brgemm_innermost_undef; + brgattr.use_uker = jbgp_.use_uker; + brgattr.use_interleave_stores = jbgp_.use_interleave_stores; + brgattr.hint_prefetching = jbgp_.hint_prefetching; + brgattr.fpmath_mode = attr()->fpmath_mode_; + + CHECK(brgemm_desc_set_attr(&brg, brgattr)); + jbgp_.amx_buf_size_per_thread + = nstl::max(brg.get_wsp_buffer_size(), + jbgp_.amx_buf_size_per_thread); + } + } + + auto scratchpad = scratchpad_registry().registrar(); + jbgp_.init_scratchpad(scratchpad); + if (jbgp_.with_scales) + book_precomputed_scales(scratchpad, attr()->scales_, OC()); + + return status::success; + } + + bool arg_scales_ok() const { + std::vector supported_args + = {DNNL_ARG_SRC, DNNL_ARG_WEIGHTS, DNNL_ARG_DST}; + return attr_scales_ok(supported_args); + } + + int get_brg_kernel_idx(bool is_bs_tail, bool do_initialization, + bool is_M_tail, bool is_N_tail, bool is_K_tail, int bs) const { + auto vM = (is_M_tail) ? jbgp_.M_tail : jbgp_.M; + auto vN = (is_N_tail) ? jbgp_.N_tail : jbgp_.N; + auto vK = (is_K_tail) ? jbgp_.K_tail : jbgp_.K; + + if (vM == 0 || vN == 0 || vK == 0 || bs == 0 || jbgp_.LDA < vK + || jbgp_.LDB < vN || jbgp_.LDC < vN) + return -1; + return brgemm_inner_product_utils::get_brg_kernel_index(is_bs_tail, + do_initialization, is_M_tail, is_N_tail, is_K_tail); + } + + int get_brg_batchsize(bool is_bs_tail, bool is_K_tail) const { + auto adj_ic = jbgp_.use_buffer_a + ? utils::rnd_up(jbgp_.ic, jbgp_.ic_block) + : jbgp_.ic; + auto bs = (is_K_tail) + ? 1 + : ((is_bs_tail) ? (adj_ic / jbgp_.K) % jbgp_.gemm_batch_size + : jbgp_.gemm_batch_size); + return bs; + } + + brgemm_t brg_descs_[brgemm_inner_product_utils::max_num_brg_kernels_ip]; + brgemm_inner_product_utils::jit_brgemm_ip_fwd_conf_t jbgp_; + }; + + brgemm_inner_product_fwd_t(const pd_t *apd) : primitive_t(apd) {} + + status_t init(engine_t *engine) override { + for_(int i_bs = 0; i_bs < 2; i_bs++) + for_(int i_M = 0; i_M < 2; i_M++) + for_(int i_N = 0; i_N < 2; i_N++) + for_(int i_K = 0; i_K < 2; i_K++) + for (int i_init = 0; i_init < 2; i_init++) { + int bs = pd()->get_brg_batchsize(i_bs, i_K); + int idx = pd()->get_brg_kernel_idx(i_bs, i_init, i_M, i_N, i_K, bs); + if (idx < 0) continue; + + brgemm_kernel_t *ker = nullptr; + CHECK(brgemm_kernel_create(&ker, pd()->brg_descs_[idx])); + CHECK(safe_ptr_assign(brg_kernels_[idx], ker)); + if (pd()->jbgp_.is_amx) + brgemm_palettes_.insert(idx, pd()->brg_descs_[idx]); + } + if (pd()->jbgp_.use_buffer_a) + CHECK(create_brgemm_copy_to_coarse(copy_src_kernel_, &pd()->jbgp_)); + if (pd()->jbgp_.nthr_ic_b > 1) { + CHECK(safe_ptr_assign( + acc_ker_, new cpu_accumulator_1d_t())); + CHECK(acc_ker_->create_kernel()); + } + return status::success; + } + + status_t execute(const exec_ctx_t &ctx) const override { + return execute_forward(ctx); + } + +private: + status_t execute_forward(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr + brg_kernels_[brgemm_inner_product_utils::max_num_brg_kernels_ip]; + std::unique_ptr copy_src_kernel_; + std::unique_ptr> acc_ker_; + brgemm_containers::brgemm_palette_container_t brgemm_palettes_ { + brgemm_inner_product_utils::max_num_brg_kernels_ip}; +}; + +template +struct brgemm_inner_product_bwd_data_t : public primitive_t { + struct pd_t : public cpu_inner_product_bwd_data_pd_t { + pd_t(const inner_product_desc_t *adesc, const primitive_attr_t *attr, + const inner_product_fwd_pd_t *hint_fwd_pd) + : cpu_inner_product_bwd_data_pd_t(adesc, attr, hint_fwd_pd) {} + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("brgemm_bwd_d:", isa, ""), + brgemm_inner_product_bwd_data_t); + + status_t init(engine_t *engine) { + + auto diff_src_dt = invariant_src_md()->data_type; + auto diff_dst_dt = invariant_dst_md()->data_type; + auto wei_dt = invariant_wei_md()->data_type; + + bool ok = true && desc()->prop_kind == prop_kind::backward_data + && !has_zero_dim_memory() && mayiuse(isa) + && utils::one_of(diff_dst_dt, data_type::f32, + data_type::bf16, data_type::f16) + && wei_dt == diff_dst_dt + && utils::one_of(diff_src_dt, data_type::f32, diff_dst_dt) + && attr()->has_default_values( + primitive_attr_t::skip_mask_t::post_ops); + if (!ok) return status::unimplemented; + + memory_desc_t dummy_bias_md; + CHECK(jbgp_.init_conf(isa, *desc(), diff_src_md_, weights_md_, + diff_dst_md_, dummy_bias_md, attr_, + dnnl_get_max_threads())); + + const float alpha = 1.0; + const float beta = 1.0; + const float beta_init = 0.0; + const auto dt_b = isa == avx512_core_fp16 && jbgp_.use_buffer_b + ? data_type::f32 + : wei_dt; + + for_(int i_bs = 0; i_bs < 2; i_bs++) + for_(int i_init = 0; i_init < 2; i_init++) + for_(int i_M = 0; i_M < 2; i_M++) + for_(int i_N = 0; i_N < 2; i_N++) + for (int i_K = 0; i_K < 2; i_K++) { + auto vbeta = (i_init) ? beta_init : beta; + auto vM = (i_M) ? jbgp_.M_tail : jbgp_.M; + auto vN = (i_N) ? jbgp_.N_tail : jbgp_.N; + auto vK = (i_K) ? jbgp_.K_tail : jbgp_.K; + int bs = get_brg_batchsize(i_bs, i_K); + int idx = get_brg_kernel_idx(i_bs, i_init, i_M, i_N, i_K, bs); + if (idx < 0) continue; + + brgemm_t &brg = brg_descs_[idx]; + CHECK(brgemm_desc_init(&brg, isa, jbgp_.brg_type, diff_dst_dt, + dt_b, false, false, brgemm_row_major, alpha, vbeta, + jbgp_.LDA, jbgp_.LDB, jbgp_.LDC, vM, vN, vK)); + + auto LDD = jbgp_.ic_without_padding; + CHECK(brgemm_desc_set_postops( + &brg, attr(), &diff_src_md_, LDD, jbgp_.bia_dt)); + if (jbgp_.is_amx) { + brgemm_attr_t brgattr; + brgattr.max_bs = bs; + brgattr.wary_tail_read = false; + brgattr.hint_expected_A_size = jbgp_.mb * jbgp_.oc; + brgattr.hint_expected_B_size = jbgp_.oc * jbgp_.ic; + brgattr.hint_expected_C_size = jbgp_.mb * jbgp_.ic; + brgattr.hint_innermost_loop = brgemm_innermost_undef; + brgattr.use_uker = jbgp_.use_uker; + brgattr.use_interleave_stores = jbgp_.use_interleave_stores; + brgattr.hint_prefetching = jbgp_.hint_prefetching; + brgattr.fpmath_mode = attr()->fpmath_mode_; + + CHECK(brgemm_desc_set_attr(&brg, brgattr)); + jbgp_.amx_buf_size_per_thread + = nstl::max(brg.get_wsp_buffer_size(), + jbgp_.amx_buf_size_per_thread); + } + } + + auto scratchpad = scratchpad_registry().registrar(); + jbgp_.init_scratchpad(scratchpad); + + return status::success; + } + + int get_brg_kernel_idx(bool is_bs_tail, bool do_initialization, + bool is_M_tail, bool is_N_tail, bool is_K_tail, int bs) const { + auto vM = (is_M_tail) ? jbgp_.M_tail : jbgp_.M; + auto vN = (is_N_tail) ? jbgp_.N_tail : jbgp_.N; + auto vK = (is_K_tail) ? jbgp_.K_tail : jbgp_.K; + + if (vM == 0 || vN == 0 || vK == 0 || bs == 0 || jbgp_.LDA < vK + || jbgp_.LDB < vN || jbgp_.LDC < vN) + return -1; + return brgemm_inner_product_utils::get_brg_kernel_index(is_bs_tail, + do_initialization, is_M_tail, is_N_tail, is_K_tail); + } + + int get_brg_batchsize(bool is_bs_tail, bool is_K_tail) const { + auto adj_oc = jbgp_.use_buffer_a + ? utils::rnd_up(jbgp_.oc, jbgp_.oc_block) + : jbgp_.oc; + auto bs = (is_K_tail) ? 1 + : ((is_bs_tail) ? (adj_oc / jbgp_.oc_block) + % jbgp_.nb_oc_blocking + : jbgp_.nb_oc_blocking); + + return bs; + } + + brgemm_t brg_descs_[brgemm_inner_product_utils::max_num_brg_kernels_ip]; + brgemm_inner_product_utils::jit_brgemm_ip_bwd_d_conf_t jbgp_; + }; + + brgemm_inner_product_bwd_data_t(const pd_t *apd) : primitive_t(apd) {} + + status_t init(engine_t *engine) override { + const auto &jbgp = pd()->jbgp_; + for_(int i_bs = 0; i_bs < 2; i_bs++) + for_(int i_M = 0; i_M < 2; i_M++) + for_(int i_N = 0; i_N < 2; i_N++) + for_(int i_K = 0; i_K < 2; i_K++) + for (int i_init = 0; i_init < 2; i_init++) { + int bs = pd()->get_brg_batchsize(i_bs, i_K); + int idx = pd()->get_brg_kernel_idx(i_bs, i_init, i_M, i_N, i_K, bs); + if (idx < 0) continue; + + brgemm_kernel_t *ker = nullptr; + CHECK(brgemm_kernel_create(&ker, pd()->brg_descs_[idx])); + CHECK(safe_ptr_assign(brg_kernels_[idx], ker)); + if (jbgp.is_amx) + brgemm_palettes_.insert(idx, pd()->brg_descs_[idx]); + } + + if (pd()->jbgp_.use_buffer_a) + CHECK(create_brgemm_copy_to_coarse( + copy_diff_dst_kernel_, &pd()->jbgp_)); + if (jbgp.use_buffer_b) + CHECK(create_brgemm_trans_wei(trans_B_kernel_, &pd()->jbgp_)); + + if (jbgp.nthr_oc_b > 1) { + CHECK(safe_ptr_assign( + acc_ker_, new cpu_accumulator_1d_t())); + CHECK(acc_ker_->create_kernel()); + } + + return status::success; + } + + status_t execute(const exec_ctx_t &ctx) const override { + execute_backward_data(ctx); + return status::success; + } + +private: + void execute_backward_data(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr + brg_kernels_[brgemm_inner_product_utils::max_num_brg_kernels_ip]; + std::unique_ptr copy_diff_dst_kernel_; + std::unique_ptr trans_B_kernel_; + std::unique_ptr> acc_ker_; + brgemm_containers::brgemm_palette_container_t brgemm_palettes_ { + brgemm_inner_product_utils::max_num_brg_kernels_ip}; +}; + +template +struct brgemm_inner_product_bwd_weights_t : public primitive_t { + struct pd_t : public cpu_inner_product_bwd_weights_pd_t { + pd_t(const inner_product_desc_t *adesc, const primitive_attr_t *attr, + const inner_product_fwd_pd_t *hint_fwd_pd) + : cpu_inner_product_bwd_weights_pd_t(adesc, attr, hint_fwd_pd) {} + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("brgemm_bwd_w:", isa, ""), + brgemm_inner_product_bwd_weights_t); + + status_t init(engine_t *engine) { + + auto src_dt = invariant_src_md()->data_type; + auto diff_wei_type = invariant_wei_md()->data_type; + auto diff_dst_type = invariant_dst_md()->data_type; + + bool ok = true && desc()->prop_kind == prop_kind::backward_weights + && !has_zero_dim_memory() && mayiuse(isa) + && utils::one_of(src_dt, data_type::f32, data_type::bf16, + data_type::f16) + && diff_dst_type == src_dt + && utils::one_of(diff_wei_type, data_type::f32, src_dt) + && attr()->has_default_values( + primitive_attr_t::skip_mask_t::post_ops); + if (!ok) return status::unimplemented; + + CHECK(jbgp_.init_conf(isa, *desc(), src_md_, diff_weights_md_, + diff_dst_md_, diff_bias_md_, attr_, + dnnl_get_max_threads())); + + const float alpha = 1.0; + const float beta = 1.0; + const float beta_init = 0.0; + const auto dt_a = isa == avx512_core_fp16 && jbgp_.use_buffer_a + ? data_type::f32 + : jbgp_.src_dt; + const auto dt_b = isa == avx512_core_fp16 && jbgp_.use_buffer_b + ? data_type::f32 + : jbgp_.dst_dt; + + for_(int i_bs = 0; i_bs < 2; i_bs++) + for_(int i_init = 0; i_init < 2; i_init++) + for_(int i_M = 0; i_M < 2; i_M++) + for_(int i_N = 0; i_N < 2; i_N++) + for (int i_K = 0; i_K < 2; i_K++) { + auto vbeta = (i_init) ? beta_init : beta; + auto vM = (i_M) ? jbgp_.M_tail : jbgp_.M; + auto vN = (i_N) ? jbgp_.N_tail : jbgp_.N; + auto vK = (i_K) ? jbgp_.K_tail : jbgp_.K; + int bs = get_brg_batchsize(i_bs, i_K); + int idx = get_brg_kernel_idx(i_bs, i_init, i_M, i_N, i_K, bs); + if (idx < 0) continue; + brgemm_t &brg = brg_descs_[idx]; + CHECK(brgemm_desc_init(&brg, isa, jbgp_.brg_type, dt_a, dt_b, + false, false, brgemm_row_major, alpha, vbeta, jbgp_.LDA, + jbgp_.LDB, jbgp_.LDC, vM, vN, vK)); + if (jbgp_.is_amx) { + brgemm_attr_t brgattr; + brgattr.max_bs = bs; + brgattr.wary_tail_read = false; + brgattr.hint_expected_A_size = jbgp_.mb * jbgp_.ic; + brgattr.hint_expected_B_size = jbgp_.mb * jbgp_.oc; + brgattr.hint_expected_C_size = jbgp_.ic * jbgp_.oc; + brgattr.hint_innermost_loop = brgemm_innermost_undef; + brgattr.use_uker = jbgp_.use_uker; + brgattr.use_interleave_stores = jbgp_.use_interleave_stores; + brgattr.hint_prefetching = jbgp_.hint_prefetching; + brgattr.fpmath_mode = attr()->fpmath_mode_; + + CHECK(brgemm_desc_set_attr(&brg, brgattr)); + jbgp_.amx_buf_size_per_thread + = nstl::max(brg.get_wsp_buffer_size(), + jbgp_.amx_buf_size_per_thread); + } + } + + auto scratchpad = scratchpad_registry().registrar(); + jbgp_.init_scratchpad(scratchpad); + + return status::success; + } + + int get_brg_kernel_idx(bool is_bs_tail, bool do_initialization, + bool is_M_tail, bool is_N_tail, bool is_K_tail, int bs) const { + auto vM = (is_M_tail) ? jbgp_.M_tail : jbgp_.M; + auto vN = (is_N_tail) ? jbgp_.N_tail : jbgp_.N; + auto vK = (is_K_tail) ? jbgp_.K_tail : jbgp_.K; + + if (vM == 0 || vN == 0 || vK == 0 || bs == 0 || jbgp_.LDA < vK + || jbgp_.LDB < vN || jbgp_.LDC < vN) + return -1; + return brgemm_inner_product_utils::get_brg_kernel_index(is_bs_tail, + do_initialization, is_M_tail, is_N_tail, is_K_tail); + } + + int get_brg_batchsize(bool is_bs_tail, bool is_K_tail) const { + auto bs = (is_K_tail) ? 1 + : ((is_bs_tail) ? (jbgp_.os / jbgp_.os_block) + % jbgp_.nb_os_blocking + : jbgp_.nb_os_blocking); + return bs; + } + + brgemm_t brg_descs_[brgemm_inner_product_utils::max_num_brg_kernels_ip]; + brgemm_inner_product_utils::jit_brgemm_ip_bwd_w_conf_t jbgp_; + }; + + brgemm_inner_product_bwd_weights_t(const pd_t *apd) : primitive_t(apd) {} + + status_t init(engine_t *engine) override { + const auto &jbgp = pd()->jbgp_; + for_(int i_bs = 0; i_bs < 2; i_bs++) + for_(int i_M = 0; i_M < 2; i_M++) + for_(int i_N = 0; i_N < 2; i_N++) + for_(int i_K = 0; i_K < 2; i_K++) + for (int i_init = 0; i_init < 2; i_init++) { + int bs = pd()->get_brg_batchsize(i_bs, i_K); + int idx = pd()->get_brg_kernel_idx(i_bs, i_init, i_M, i_N, i_K, bs); + if (idx < 0) continue; + + brgemm_kernel_t *ker = nullptr; + CHECK(brgemm_kernel_create(&ker, pd()->brg_descs_[idx])); + CHECK(safe_ptr_assign(brg_kernels_[idx], ker)); + if (jbgp.is_amx) + brgemm_palettes_.insert(idx, pd()->brg_descs_[idx]); + + if (jbgp.with_bias && i_M == 0 && i_init == 0) { + kernels_db_[i_K][i_N] = nullptr; + auto db_desc = pd()->brg_descs_[idx]; + db_desc.reduce_dim = (i_K) ? jbgp.K_tail : jbgp.K; + if (db_desc.reduce_dim > 0 && db_desc.load_dim > 0) { + CHECK(safe_ptr_assign(kernels_db_[i_K][i_N], + new jit_brgemm_kernel_diff_bias_t(jbgp, db_desc))); + CHECK(kernels_db_[i_K][i_N]->create_kernel()); + } + } + } + if (jbgp.is_amx) { + ext_ic_block_ = jbgp.ic_block_ext; + ext_oc_block_ = jbgp.oc_block_ext; + } + CHECK(create_brgemm_trans_src(trans_A_kernel_, &pd()->jbgp_)); + + if (jbgp.use_buffer_b) + CHECK(create_brgemm_trans_to_vnni(trans_B_kernel_, &pd()->jbgp_, + jit_brgemm_trans_to_vnni_t::matrix_to_transform::matrix_B)); + + if (!jbgp.is_amx) { + if (jbgp.wei_dt != jbgp.acc_dt) + CHECK(create_brgemm_trans_to_vnni(trans_C_kernel_, &pd()->jbgp_, + jit_brgemm_trans_to_vnni_t::matrix_to_transform:: + matrix_C)); + } else if (utils::one_of( + jbgp.wei_dt, data_type::bf16, data_type::f16)) { + CHECK(create_brgemm_amx_ip_trans_wei(diff_wei_trans_kernel_, + &pd()->jbgp_, ext_ic_block_, ext_oc_block_)); + } + if (jbgp.nthr_mb > 1) { + CHECK(safe_ptr_assign( + acc_ker_, new cpu_accumulator_1d_t())); + CHECK(acc_ker_->create_kernel()); + } + + return status::success; + } + + status_t execute(const exec_ctx_t &ctx) const override { + execute_backward_weights(ctx); + return status::success; + } + +private: + struct thread_info_t; + std::unique_ptr kernels_db_[2][2]; + std::unique_ptr + brg_kernels_[brgemm_inner_product_utils::max_num_brg_kernels_ip]; + std::unique_ptr trans_A_kernel_; + std::unique_ptr trans_B_kernel_; + std::unique_ptr trans_C_kernel_; + std::unique_ptr> acc_ker_; + std::unique_ptr diff_wei_trans_kernel_; + + void execute_backward_weights(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + void compute_diff_weights_and_bias(const thread_info_t *ti) const; + void reduce_and_convert_diff_weights_and_bias( + const thread_info_t *ti) const; + void transform_matrix_a_chunk(char *tr_src, const char *src, + int trans_batch, int current_m, int current_k) const; + void transform_matrix_b_chunk(char *tr_diff_dst, const char *diff_dst, + int trans_batch, int current_col_size, int current_row_size) const; + void transpose_matrix_c_chunk(const thread_info_t *ti, const int ocb, + const int icb, int oc_size, int ic_size, + bool is_reduction = false) const; + + brgemm_containers::brgemm_palette_container_t brgemm_palettes_ { + brgemm_inner_product_utils::max_num_brg_kernels_ip}; + dim_t get_wei_offset(int ocb, int icb) const; + char *get_wei_acc_ptr(const thread_info_t *ti, int ocb, int icb, + int reduction_buf_idx = -1) const; + + int ext_ic_block_ = 0; + int ext_oc_block_ = 0; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_inner_product_utils.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_inner_product_utils.hpp new file mode 100644 index 0000000000000000000000000000000000000000..35df3a7696f4ceb29b087db1e6e14990f11ce5b7 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_inner_product_utils.hpp @@ -0,0 +1,144 @@ +/******************************************************************************* +* Copyright 2020-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_BRGEMM_INNER_PRODUCT_UTILS_HPP +#define CPU_X64_BRGEMM_INNER_PRODUCT_UTILS_HPP + +#include "dnnl_types.h" + +#include "common/bfloat16.hpp" +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/memory_tracking.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_engine.hpp" +#include "cpu/cpu_inner_product_pd.hpp" +#include "cpu/platform.hpp" + +#include "cpu/x64/cpu_barrier.hpp" +#include "cpu/x64/cpu_isa_traits.hpp" +#include "cpu/x64/injectors/jit_uni_postops_injector.hpp" +#include "cpu/x64/jit_brgemm_primitive_conf.hpp" +#include "cpu/x64/jit_generator.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +namespace brgemm_inner_product_utils { + +// Common for fwd/bwd_d/bwd_w. +struct jit_brgemm_ip_conf_t : jit_brgemm_primitive_conf_t { + // Use kernels and blocking for small os that consume less bandwidth. + bool use_small_os_kernels = false; + +protected: + status_t init_conf_base(cpu_isa_t isa, const inner_product_desc_t &ipd, + memory_desc_t &src_md, memory_desc_t &weights_md, + memory_desc_t &dst_md, memory_desc_t &bias_md, + primitive_attr_t &attr, int nthreads); + + void init_scratchpad_base(memory_tracking::registrar_t &scratchpad) const; + + int get_os_block(bool try_to_adjust, bool is_adjustment) const; + int get_oc_block(bool try_to_adjust = false) const; + std::unordered_map get_desired_weights_tag() const; + + int get_adjusted_oc_block() const; + int get_nb_oc_blocking(bool is_adjustment = false) const; + bool adjust_thread_balance() const; + + format_tag_t get_brgemm_ip_weights_tag( + const memory_desc_t &weights_md) const; +}; + +// Specific for forward. +struct jit_brgemm_ip_fwd_conf_t : jit_brgemm_ip_conf_t { + enum loop_order_t { + osc_occ_icc_osb_ocb, + osc_occ_osb_ocb_icc, + icc_osc_occ_osb_ocb, + icc_occ_osc_ocb_osb, + } loop_order + = osc_occ_osb_ocb_icc; + + status_t init_conf(cpu_isa_t isa, const inner_product_desc_t &ipd, + memory_desc_t &src_md, memory_desc_t &weights_md, + memory_desc_t &dst_md, memory_desc_t &bias_md, + primitive_attr_t &attr, int nthreads); + + void init_scratchpad(memory_tracking::registrar_t &scratchpad) const; + +private: + void choose_loop_order(); +}; + +// Specific for backward by data. +struct jit_brgemm_ip_bwd_d_conf_t : jit_brgemm_ip_conf_t { + bool global_b_transpose; + + status_t init_conf(cpu_isa_t isa, const inner_product_desc_t &ipd, + memory_desc_t &src_md, memory_desc_t &weights_md, + memory_desc_t &dst_md, memory_desc_t &bias_md, + primitive_attr_t &attr, int nthreads); + + void init_scratchpad(memory_tracking::registrar_t &scratchpad) const; +}; + +// Specific for backward by weights. +struct jit_brgemm_ip_bwd_w_conf_t : jit_brgemm_ip_conf_t { + enum loop_order_t { + osc_icc_occ, + osc_occ_icc, + occ_icc_osc, + } loop_order + = occ_icc_osc; + + bool local_buffers_for_input_tensors; + + status_t init_conf(cpu_isa_t isa, const inner_product_desc_t &ipd, + memory_desc_t &src_md, memory_desc_t &weights_md, + memory_desc_t &dst_md, memory_desc_t &bias_md, + primitive_attr_t &attr, int nthreads); + + void init_scratchpad(memory_tracking::registrar_t &scratchpad) const; + +private: + void thread_balance(int &nb_os_blocking_, int &nb_oc_blocking_, + int &nb_ic_blocking_, int &nthr_, int &nthr_mb_, int &nthr_oc_b_, + int &nthr_ic_b_) const; + + void choose_loop_order(); +}; + +static const int max_num_brg_kernels_ip = 2 * 2 * 2 * 2 * 2; + +int get_brg_kernel_index(bool is_bs_tail, bool do_initialization, + bool is_M_tail, bool is_N_tail, bool is_K_tail); + +size_t buf_dt_size(data_type_t dt, cpu_isa_t isa); + +} // namespace brgemm_inner_product_utils + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_post_ops.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_post_ops.hpp new file mode 100644 index 0000000000000000000000000000000000000000..29ba73658e90ef3304c13145e120b05dad55bd4e --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_post_ops.hpp @@ -0,0 +1,1054 @@ +/******************************************************************************* +* Copyright 2020-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_BRGEMM_POST_OPS_HPP +#define CPU_X64_JIT_BRGEMM_POST_OPS_HPP + +#include + +#include "common/c_types_map.hpp" +#include "common/memory_tracking.hpp" + +#include "cpu/cpu_engine.hpp" + +#include "cpu/x64/injectors/jit_uni_postops_injector.hpp" +#include "cpu/x64/jit_avx512_core_bf16cvt.hpp" +#include "cpu/x64/jit_brgemm_primitive_conf.hpp" +#include "cpu/x64/jit_generator.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +struct brgemm_kernel_diff_bias_t { + brgemm_kernel_diff_bias_t() + : ptr_diff_dst(nullptr) + , ptr_diff_bias_acc(nullptr) + , ptr_diff_bias(nullptr) + , flags(0) {}; + + void *ptr_diff_dst; + void *ptr_diff_bias_acc; + void *ptr_diff_bias; + int flags; +}; + +#define GET_OFF(field) offsetof(brgemm_kernel_diff_bias_t, field) + +struct jit_brgemm_kernel_diff_bias_t : public jit_generator { + jit_brgemm_kernel_diff_bias_t( + const jit_brgemm_primitive_conf_t &ajbgp, const brgemm_t &abrg) + : jit_generator(jit_name()) + , brg_(abrg) + , ddst_dt_(ajbgp.dst_dt) + , bia_dt_(ajbgp.bia_dt) + , acc_dt_(ajbgp.acc_dt) + , bia_typesize_(types::data_type_size(bia_dt_)) + , acc_typesize_(types::data_type_size(acc_dt_)) { + + ddst_dt_ = (ajbgp.isa == avx512_core_fp16 && ajbgp.use_buffer_b) + ? data_type::f32 + : ajbgp.dst_dt; + ddst_typesize_ = types::data_type_size(ddst_dt_); + mult_ = data_type_vnni_granularity(ddst_dt_); + } + + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_brgemm_kernel_diff_bias_t) + +private: + brgemm_t brg_; + data_type_t ddst_dt_; + data_type_t bia_dt_; + data_type_t acc_dt_; + + int ddst_typesize_; + int bia_typesize_; + int acc_typesize_; + int mult_; + + using reg64_t = const Xbyak::Reg64; + // Register decomposition + const reg64_t param1 = abi_param1; + const reg64_t reg_ddst = r15; + const reg64_t reg_bias = r14; + const reg64_t reg_bias_acc = r13; + const reg64_t aux_reg_ddst = r12; + const reg64_t reg_k_iter = r11; + const reg64_t reg_flag = r10; + const reg64_t reg_mask = rax; + + Xbyak::Opmask k_full_mask = Xbyak::Opmask(2); + Xbyak::Opmask k_tail_mask = Xbyak::Opmask(3); + Xbyak::Opmask k_f16_perm_mask = Xbyak::Opmask(4); + Xbyak::Zmm vreg_unit = Xbyak::Zmm(31); + Xbyak::Zmm vreg_perm = Xbyak::Zmm(30); + + const int n_max_regs_ = 4; + + const Xbyak::Zmm zmm_mask(const Xbyak::Zmm zmm_in, bool mask_flag, + bool store, Xbyak::Opmask ktail_mask) { + return mask_flag + ? (store ? zmm_in | ktail_mask : zmm_in | ktail_mask | T_z) + : zmm_in; + } + + Xbyak::Zmm get_bias_reg(int n) const { return Xbyak::Zmm(n); } + Xbyak::Ymm get_bias_reg_lower(int n) const { return Xbyak::Ymm(n); } + Xbyak::Zmm get_ddst_reg(int n) const { return Xbyak::Zmm(n + n_max_regs_); } + + void accumulate_bias(int idx, bool mask_flag) { + auto vddst = get_ddst_reg(idx); + auto vddst_load = zmm_mask(vddst, mask_flag, false, k_tail_mask); + auto vbias = get_bias_reg(idx); + if (ddst_dt_ == data_type::f16) { + // As we do not have fp16_vnni, we add twice to accumulate + // adjacent elements. + for (int i = 0; i < 2; ++i) { + auto addr = ptr[aux_reg_ddst + + ddst_typesize_ * mult_ * idx * brg_.ld_block + i * 2]; + vmovups(vddst_load, addr); + vpermw(vddst | k_f16_perm_mask | T_z, vreg_perm, vddst); + vcvtph2psx(vddst, Xbyak::Ymm(vddst.getIdx())); + vaddps(vbias, vbias, vddst); + } + } else { + auto addr = ptr[aux_reg_ddst + + ddst_typesize_ * mult_ * idx * brg_.ld_block]; + vmovups(vddst_load, addr); + if (ddst_dt_ == data_type::bf16) + vdpbf16ps(vbias, vreg_unit, vddst); + else + vaddps(vbias, vbias, vddst); + } + } + + void store(int idx, bool mask_flag) { + auto addr = ptr[reg_bias + bia_typesize_ * idx * brg_.ld_block]; + auto vbias = get_bias_reg(idx); + auto vbias_lower = get_bias_reg_lower(idx); + switch (bia_dt_) { + case data_type::bf16: + vcvtneps2bf16(vbias_lower, vbias); + if (mask_flag) { + vmovdqu16(addr, + zmm_mask(vbias, mask_flag, true, k_tail_mask)); + } else { + vmovups(addr, vbias_lower); + } + break; + case data_type::f16: + vcvtps2ph(vbias_lower, vbias, 0x4); + if (mask_flag) { + vmovdqu16(addr, + zmm_mask(vbias, mask_flag, true, k_tail_mask)); + } else { + vmovups(addr, vbias_lower); + } + break; + case data_type::f32: + vmovups(addr, + zmm_mask(get_bias_reg(idx), mask_flag, true, + k_tail_mask)); + break; + default: assert("Unsupported bias data type"); + } + } + + void loop_by_N(int n_loop, int nb_tail) { + + mov(aux_reg_ddst, reg_ddst); + + int n_iters = n_loop; + if (nb_tail > 0) n_iters--; + Xbyak::Label k_loop, init_zero, init_done; + int n_ = 0; + + test(reg_flag, FLAG_REDUCE_FIRST); + jnz(init_zero, T_NEAR); // FLAG_REDUCE_FIRST is set + + for (; n_ < n_iters; n_++) { + auto vbias = get_bias_reg(n_); + auto addr = ptr[reg_bias_acc + acc_typesize_ * n_ * brg_.ld_block]; + vmovups(vbias, addr); + } + if (nb_tail > 0) { + auto vbias = zmm_mask(get_bias_reg(n_), true, false, k_tail_mask); + auto addr = ptr[reg_bias_acc + acc_typesize_ * n_ * brg_.ld_block]; + vmovups(vbias, addr); + } + jmp(init_done, T_NEAR); + L(init_zero); + + for (int n_ = 0; n_ < n_loop; n_++) { + vxorpd(get_bias_reg(n_), get_bias_reg(n_), get_bias_reg(n_)); + } + L(init_done); + + mov(reg_k_iter, utils::div_up(brg_.reduce_dim, mult_)); + L(k_loop); + { + int n_ = 0; + for (; n_ < n_iters; n_++) + accumulate_bias(n_, false); + + if (nb_tail > 0) accumulate_bias(n_, true); + + add(aux_reg_ddst, ddst_typesize_ * mult_ * brg_.LDB); + + sub(reg_k_iter, 1); + jnz(k_loop, T_NEAR); + } + + Xbyak::Label store_final, store_done; + test(reg_flag, FLAG_REDUCE_LAST); + jnz(store_final, T_NEAR); // FLAG_REDUCE_LAST is set + + n_ = 0; + for (; n_ < n_iters; n_++) { + auto vbias = get_bias_reg(n_); + auto addr = ptr[reg_bias_acc + acc_typesize_ * n_ * brg_.ld_block]; + vmovups(addr, vbias); + } + if (nb_tail > 0) { + auto addr = ptr[reg_bias_acc + acc_typesize_ * n_ * brg_.ld_block]; + auto vbias = zmm_mask(get_bias_reg(n_), true, true, k_tail_mask); + vmovups(addr, vbias); + } + jmp(store_done, T_NEAR); + + L(store_final); + n_ = 0; + + for (; n_ < n_iters; n_++) + store(n_, false); + + if (nb_tail > 0) store(n_, true); + + L(store_done); + } + + void generate() override { + preamble(); + + int nb = utils::div_up(brg_.load_dim, brg_.ld_block); + int nb_tail = brg_.load_dim % brg_.ld_block; + + int n_loop = nb / n_max_regs_; + int n_loop_tail = nb % n_max_regs_; + if (n_loop_tail == 0 && nb_tail > 0) { + n_loop--; + n_loop_tail = n_max_regs_; + } + + const auto full_mask = size_t {0xffffffffffffffff}; + const auto tail_mask = size_t((1 << nb_tail) - 1); + + mov(reg_mask, full_mask); + kmovq(k_full_mask, reg_mask); + mov(reg_mask, tail_mask); + kmovq(k_tail_mask, reg_mask); + + if (ddst_dt_ == data_type::bf16) { + auto reg_unit_val = reg_mask.cvt16(); + mov(reg_unit_val, 0x3f80); // bf16 value of 1. + vpbroadcastw(vreg_unit, reg_unit_val); + } + + Xbyak::Label f16_perm_table; + if (ddst_dt_ == data_type::f16) { + const auto half_mask = size_t((1 << 16) - 1); + mov(reg_mask, half_mask); + kmovq(k_f16_perm_mask, reg_mask); + + mov(reg_mask, f16_perm_table); + vmovups(vreg_perm | k_f16_perm_mask | T_z, ptr[reg_mask]); + } + + mov(reg_ddst, ptr[param1 + GET_OFF(ptr_diff_dst)]); + mov(reg_bias_acc, ptr[param1 + GET_OFF(ptr_diff_bias_acc)]); + mov(reg_bias, ptr[param1 + GET_OFF(ptr_diff_bias)]); + mov(reg_flag, ptr[param1 + GET_OFF(flags)]); + + for (int nb_ = 0; nb_ < n_loop; nb_++) { + loop_by_N(n_max_regs_, 0); + + add(reg_ddst, ddst_typesize_ * mult_ * n_max_regs_ * brg_.ld_block); + add(reg_bias, bia_typesize_ * n_max_regs_ * brg_.ld_block); + add(reg_bias_acc, acc_typesize_ * n_max_regs_ * brg_.ld_block); + } + + if (n_loop_tail > 0) loop_by_N(n_loop_tail, nb_tail); + postamble(); + + if (ddst_dt_ == data_type::f16) { + // convert interleaved vnni data with holes to packed. + const uint16_t f16_prm_array[16] = { + 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30}; + align(64); + L(f16_perm_table); + for (int i = 0; i < 16; ++i) + dw(f16_prm_array[i]); + } + } +}; + +#undef GET_OFF + +#define GET_OFF(field) offsetof(brgemm_kernel_post_ops_t, field) + +struct brgemm_kernel_post_ops_t { + void *ptr_in; + void *ptr_out; + void *ptr_bias; + void *ptr_scales; + const void *ptr_binary_post_ops_rhs; + size_t apply_comp = 0; + int32_t a_comp_val = 1; + int32_t *a_zp_compensation; + int32_t *c_zp_values; + int32_t *s8s8_compensation; + const void *dst_orig; + void *ptr_dst_scales; +}; + +template +struct jit_brgemm_kernel_post_ops : public jit_generator { + + jit_brgemm_kernel_post_ops(const jit_brgemm_conv_conf_t &ajcp, + const brgemm_t &abrg, const primitive_attr_t &aattr) + : jit_generator(jit_name()) + , brg(abrg) + , jcp(ajcp) + , attr(aattr) + , postops_injector_(nullptr) + , with_binary_non_scalar_bcast_(brg.with_binary + && binary_injector:: + any_binary_postop_rhs_non_scalar_broadcast( + brg.attr->post_ops_, + memory_desc_wrapper(brg.dst_md))) { + + if (brg.beta != 0) { + static constexpr bool preserve_gpr = true; + static constexpr bool preserve_vmm = true; + static constexpr bool use_exact_tail_scalar_bcast = false; + + const binary_injector::rhs_arg_static_params_t rhs_sp { + static_cast(vmm_tmp(4).getIdx()), this->r14, + this->r15, this->r13, preserve_gpr, preserve_vmm, + GET_OFF(ptr_binary_post_ops_rhs), GET_OFF(dst_orig), + memory_desc_wrapper(brg.dst_md), + static_cast(brg.load_dim % brg.ld_block), + k_tail_mask, use_exact_tail_scalar_bcast}; + const binary_injector::static_params_t bsp {this->param1, rhs_sp}; + + const bool save_state = jcp.with_eltwise; + const auto &reserved_eltwise_gpr = reg_reserved_eltwise; + const auto reserved_eltwise_maskr = Xbyak::Opmask(1); + + const eltwise_injector::static_params_t esp { + save_state, reserved_eltwise_gpr, reserved_eltwise_maskr}; + + postops_injector_ = utils::make_unique< + injector::jit_uni_postops_injector_t>( + this, attr.post_ops_, bsp, esp); + } + if (brg.is_bf16_emu) + bf16_emu_ = utils::make_unique(this, + bf16_emu_reserv_1, bf16_emu_reserv_2, bf16_emu_reserv_3, + bf16_emu_scratch, bf16_emu_reserv_4, bf16_emu_reserv_4); + + const auto &wei_scales = attr.scales_.get(DNNL_ARG_WEIGHTS); + // per_oc: conv: 1 << 0, (1 << 1) + (1 << 0) (with groups) + // per_oc: ip: 1 << 0 + is_oc_scale_ + = utils::one_of(wei_scales.mask_, 1 << 0, (1 << 1) + (1 << 0)); + + LDD_ = brg.LDD; + inp_dt_ = brg.dt_c; + out_dt_ = brg.dt_d; + bia_dt_ = jcp.bia_dt; + inp_typesize_ = types::data_type_size(inp_dt_); + out_typesize_ = types::data_type_size(out_dt_); + bia_typesize_ = (jcp.with_bias) ? types::data_type_size(bia_dt_) : 0; + } + + ~jit_brgemm_kernel_post_ops() = default; + + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_brgemm_kernel_post_ops) + + brgemm_t brg; + jit_brgemm_conv_conf_t jcp; + const primitive_attr_t &attr; + +private: + int LDD_; + + data_type_t inp_dt_; + data_type_t out_dt_; + data_type_t bia_dt_; + static constexpr cpu_isa_t po_isa_t = utils::map(isa, avx512_core, avx2, + avx2, avx2_vnni, avx2, avx2_vnni_2, avx2_vnni_2, avx512_core_fp16, + avx512_core_fp16); + std::unique_ptr> + postops_injector_; + std::unique_ptr bf16_emu_; + + const bool with_binary_non_scalar_bcast_; + + int inp_typesize_; + int out_typesize_; + int bia_typesize_; + + int is_oc_scale_; + constexpr static int max_vregs_ = cpu_isa_traits::n_vregs; + + using reg64_t = const Xbyak::Reg64; + using Vmm = typename utils::conditional::type; + using Vmm_lower_t = typename vreg_traits::Vmm_lower_t; + + // Register decomposition + const reg64_t reg_reserved_eltwise = rax; + const reg64_t param1 = abi_param1; + const reg64_t reg_in = r15; + const reg64_t reg_out = r14; + const reg64_t aux_reg_in = r13; + const reg64_t aux_reg_out = r12; + + const reg64_t reg_bias = r11; + const reg64_t aux_reg_bias = r10; + + const reg64_t reg_scales = r9; + const reg64_t aux_reg_scales = r8; + + const reg64_t reg_ptr_sum_scale = rdx; + const reg64_t reg_ptr_sum_zp = rsi; + + const reg64_t reg_zp_c_values = rbx; + const reg64_t aux_reg_zp_c_values = rbx; + const reg64_t reg_zp_a_comp = rbx; + const reg64_t aux_reg_zp_a_comp = rbx; + const reg64_t reg_s8s8_comp = rbx; + const reg64_t aux_reg_s8s8_comp = rbx; + const reg64_t reg_zp_a_val = rbx; + const reg64_t reg_apply_comp = rbx; + const reg64_t reg_dst_scales = rbx; + const reg64_t aux_reg_dst_scales = rbx; + const reg64_t reg_tmp = abi_not_param1; + + constexpr static int reg_zp_c_values_offs_ = 0; + constexpr static int aux_reg_zp_c_values_offs_ = 8; + constexpr static int reg_zp_a_comp_offs_ = 16; + constexpr static int aux_reg_zp_a_comp_offs_ = 24; + constexpr static int reg_s8s8_comp_offs_ = 32; + constexpr static int aux_reg_s8s8_comp_offs_ = 40; + constexpr static int reg_zp_a_val_offs_ = 48; + constexpr static int reg_apply_comp_offs_ = 56; + constexpr static int reg_dst_scales_offs_ = 64; + constexpr static int stack_space_needed_ = 72; + + /* bf16 emulation */ + Xbyak::Zmm bf16_emu_reserv_1 = Xbyak::Zmm(27); + Xbyak::Zmm bf16_emu_reserv_2 = Xbyak::Zmm(24); + Xbyak::Zmm bf16_emu_reserv_3 = Xbyak::Zmm(25); + Xbyak::Zmm bf16_emu_reserv_4 = Xbyak::Zmm(26); + reg64_t bf16_emu_scratch = reg_tmp; + + Xbyak::Opmask k_full_mask = Xbyak::Opmask(2); + Xbyak::Opmask k_tail_mask = Xbyak::Opmask(3); + + const int n_block2_ = 4; + + Vmm vmm_tmp(int i) const { return Vmm(max_vregs_ - 1 - i); } + + int zp_c_values_offset(int n, bool is_tail = false) const noexcept { + if (brg.zp_type_c == brgemm_broadcast_t::per_n) { + return (is_tail) ? sizeof(int32_t) * brg.ldb_tail + : sizeof(int32_t) * n * brg.ld_block; + } + + return 0; + } + int zp_comp_a_vpad_offset( + int n, int m, bool is_tail = false) const noexcept { + return (is_tail) ? sizeof(int32_t) * (brg.ldb_tail + m * brg.LDB) + : sizeof(int32_t) * (n * brg.ld_block + m * brg.LDB); + } + int mb_zp_comp_a_offset(int m_block) const noexcept { + return sizeof(int32_t) * m_block * brg.LDB; + } + int compensation_vpad_offset( + int n, int m, bool is_tail = false) const noexcept { + return (is_tail) ? sizeof(int32_t) * (brg.ldb_tail + m * brg.LDB) + : sizeof(int32_t) * (n * brg.ld_block + m * brg.LDB); + } + int mb_compensation_offset(int m_block) const noexcept { + return sizeof(int32_t) * m_block * brg.LDB; + } + + template + const T maybe_mask(const T vmm_in, bool mask_flag, bool store, + Xbyak::Opmask ktail_mask) { + assert(IMPLICATION(mask_flag, isa_has_masks(isa))); + return mask_flag + ? (store ? vmm_in | ktail_mask : vmm_in | ktail_mask | T_z) + : vmm_in; + } + + void cvt2ps(data_type_t type_in, const Vmm vmm_in, const Xbyak::Operand &op, + int tail_size, bool store, Xbyak::Opmask ktail_mask, + bool skip_cvt2ps = false) { + const bool is_tail = op.isMEM() + && tail_size != vreg_traits::vlen / sizeof(float) + // The current kernel is written such that tail_size = 0 implies + // no tail and full vmm must be processed. + && tail_size > 0; + + if (IMPLICATION(is_tail, isa_has_masks(isa))) { + const Vmm vmm = maybe_mask(vmm_in, is_tail, store, ktail_mask); + switch (type_in) { + case data_type::f32: + case data_type::s32: vmovups(vmm, op); break; + case data_type::s8: vpmovsxbd(vmm, op); break; + case data_type::u8: vpmovzxbd(vmm, op); break; + case data_type::bf16: + vpmovzxwd(vmm, op); + vpslld(vmm, vmm, 16); + break; + case data_type::f16: vcvtph2ps(vmm, op); break; + default: assert(!"unsupported data type"); + } + } else { + load_data(type_in, vmm_in, op.getAddress(), tail_size); + } + if (!skip_cvt2ps && types::is_integral_dt(type_in)) + uni_vcvtdq2ps(vmm_in, vmm_in); + } + + Vmm vector(int m, int n, int n_block) { return Vmm(m * n_block + n); }; + + void inject_attr_postops(int m_block, int n_block, int tail = 0) { + const auto &p = attr.post_ops_; + const int sum_idx = p.find(primitive_kind::sum); + const auto k_mask = tail == 0 ? k_full_mask : k_tail_mask; + const auto sum_dt = p.get_sum_dt(out_dt_); + + const auto sum_injector = [&] { + const float *p_sum_scale = &p.entry_[sum_idx].sum.scale; + const int32_t *p_sum_zp = &p.entry_[sum_idx].sum.zero_point; + if (*p_sum_scale != 1.f) + mov(reg_ptr_sum_scale, (size_t)p_sum_scale); + auto vmm_sum_zp = vmm_tmp(1); + if (*p_sum_zp != 0) { + mov(reg_ptr_sum_zp, (size_t)p_sum_zp); + if (is_superset(isa, avx512_core)) { + vcvtdq2ps(vmm_sum_zp, ptr_b[reg_ptr_sum_zp]); + } else { + vpbroadcastd(vmm_sum_zp, ptr[reg_ptr_sum_zp]); + uni_vcvtdq2ps(vmm_sum_zp, vmm_sum_zp); + } + } + + for_(int m = 0; m < m_block; m++) + for (int n = 0; n < n_block; n++) { + const auto vmm = vector(m, n, n_block); + const auto addr = ptr[aux_reg_out + + out_typesize_ * (m * LDD_ + n * brg.ld_block)]; + + const auto vmm_prev_dst = vmm_tmp(0); + cvt2ps(sum_dt, vmm_prev_dst, addr, tail, false, k_mask); + if (*p_sum_zp != 0) + uni_vsubps(vmm_prev_dst, vmm_prev_dst, vmm_sum_zp); + if (*p_sum_scale == 1.f) + uni_vaddps(vmm, vmm, vmm_prev_dst); + else { + if (is_superset(isa, avx512_core)) { + vfmadd231ps( + vmm, vmm_prev_dst, ptr_b[reg_ptr_sum_scale]); + } else { + auto vmm_sum_scale = vmm_tmp(2); + vpbroadcastd(vmm_sum_scale, ptr[reg_ptr_sum_scale]); + vfmadd231ps(vmm, vmm_prev_dst, vmm_sum_scale); + } + } + } + }; + + if (jcp.with_sum) { + postops_injector_->set_lambda_injector( + primitive_kind::sum, sum_injector); + } + + binary_injector::rhs_arg_dynamic_params_t rhs_arg_params; + + if (with_binary_non_scalar_bcast_) { + for_(int m = 0; m < m_block; m++) + for (int n = 0; n < n_block; n++) { + const auto vmm_idx = vector(m, n, n_block).getIdx(); + const size_t aux_output_offset + = out_typesize_ * (m * LDD_ + n * brg.ld_block); + + rhs_arg_params.vmm_idx_to_out_reg.emplace(vmm_idx, aux_reg_out); + rhs_arg_params.vmm_idx_to_out_elem_off_val.emplace( + vmm_idx, aux_output_offset); + if (tail) rhs_arg_params.vmm_tail_idx_.emplace(vmm_idx); + } + } + + postops_injector_->compute_vector_range( + 0, m_block * n_block, rhs_arg_params); + } + void apply_comp(int m_block, int n_block, int tail = 0) { + auto k_mask = (tail == 0) ? k_full_mask : k_tail_mask; + const bool has_tail = tail > 0; + + if (brg.zp_type_a != brgemm_broadcast_t::none) { + auto vmm_zp_a_val = vmm_tmp(1); + mov(reg_zp_a_val, ptr[rsp + reg_zp_a_val_offs_]); + uni_vpbroadcastd(vmm_zp_a_val, reg_zp_a_val.cvt32()); + + mov(aux_reg_zp_a_comp, ptr[rsp + aux_reg_zp_a_comp_offs_]); + for (int n = 0; n < n_block; n++) { + auto vmm_zp_comp_a = vmm_tmp(0); + const size_t zp_comp_offset + = sizeof(int32_t) * (n * brg.ld_block); + auto zp_comp_a_addr = is_superset(isa, avx512_core) + ? EVEX_compress_addr(aux_reg_zp_a_comp, zp_comp_offset) + : ptr[aux_reg_zp_a_comp + zp_comp_offset]; + if (IMPLICATION(has_tail, isa_has_masks(isa))) { + vmm_zp_comp_a = maybe_mask( + vmm_zp_comp_a, has_tail, false, k_mask); + vmovups(vmm_zp_comp_a, zp_comp_a_addr); + } else { + load_data(data_type::f32, vmm_zp_comp_a, zp_comp_a_addr, + tail); + } + uni_vpmulld(vmm_zp_comp_a, vmm_zp_a_val, zp_comp_a_addr); + for (int m = 0; m < m_block; m++) { + auto vmm = vector(m, n, n_block); + uni_vpaddd(vmm, vmm, vmm_zp_comp_a); + } + } + } + + if (brg.req_s8s8_compensation) { + mov(aux_reg_s8s8_comp, ptr[rsp + aux_reg_s8s8_comp_offs_]); + for (int n = 0; n < n_block; n++) { + auto vmm_comp = vmm_tmp(0); + const size_t s8s8_comp_offset + = sizeof(int32_t) * (n * brg.ld_block); + auto comp_addr = is_superset(isa, avx512_core) + ? EVEX_compress_addr( + aux_reg_s8s8_comp, s8s8_comp_offset) + : ptr[aux_reg_s8s8_comp + s8s8_comp_offset]; + if (IMPLICATION(tail > 0, isa_has_masks(isa))) { + vmm_comp = maybe_mask(vmm_comp, tail > 0, false, k_mask); + vmovups(vmm_comp, comp_addr); + } else + load_data(data_type::f32, vmm_comp, comp_addr, tail); + for (int m = 0; m < m_block; m++) { + auto vmm = vector(m, n, n_block); + uni_vpaddd(vmm, vmm, vmm_comp); + } + } + } + } + void maybe_apply_comp(int m_block, int n_block, int tail = 0) { + Xbyak::Label label_apply_without_comp; + mov(reg_apply_comp, ptr[rsp + reg_apply_comp_offs_]); + cmp(reg_apply_comp, 0); + je(label_apply_without_comp, T_NEAR); + apply_comp(m_block, n_block, tail); + L_aligned(label_apply_without_comp); + + for_(int m = 0; m < m_block; m++) + for (int n = 0; n < n_block; n++) { + uni_vcvtdq2ps(vector(m, n, n_block), vector(m, n, n_block)); + } + } + + void apply_post_ops(int m_block, int n_block, int tail = 0) { + const auto vector = [=](int m, int n) { return Vmm(m * n_block + n); }; + auto k_mask = (tail == 0) ? k_full_mask : k_tail_mask; + const auto req_comp = brg.is_int8 && brg.beta != 0 + && (brg.req_s8s8_compensation + || brg.zp_type_a != brgemm_broadcast_t::none); + + // brg.alpha == 0 means initialize registers, 1 means read from input + // brg.beta == 0 means skip postwork, 1 means do postwork + // req_comp == true -> convert accumulated values to f32 after applying + // compensation to avoid the loss of accuracy when converting s32 to f32 + for_(int m = 0; m < m_block; m++) + for (int n = 0; n < n_block; n++) { + if (brg.alpha == 0 && brg.beta != 0) { + // if postwork then have to init vmm each time + uni_vpxor(vector(m, n), vector(m, n), vector(m, n)); + } else if (brg.alpha != 0) { + auto inp_addr = ptr[aux_reg_in + + inp_typesize_ * (m * brg.LDC + n * brg.ld_block)]; + cvt2ps(inp_dt_, vector(m, n), inp_addr, tail, false, k_mask, + req_comp); + } + } + + if (req_comp) maybe_apply_comp(m_block, n_block, tail); + + if (brg.beta != 0) { + for_(int m = 0; m < m_block; m++) + for (int n = 0; n < n_block; n++) { + const auto addr = ptr[aux_reg_scales + + is_oc_scale_ * sizeof(float) * (n * brg.ld_block)]; + auto vmm = vector(m, n); + if (IMPLICATION(tail > 0, isa_has_masks(isa))) { + vmm = maybe_mask(vector(m, n), tail > 0, false, k_mask); + vmulps(vmm, vmm, addr); + } else { + auto vmm_scales = vmm_tmp(0); + load_data(data_type::f32, vmm_scales, addr, tail); + vmulps(vmm, vmm, vmm_scales); + } + } + } + + if (brg.beta != 0 && jcp.with_bias) { + for (int n = 0; n < n_block; n++) { + auto vmm_bias = vmm_tmp(0); + auto bias_addr = ptr[aux_reg_bias + + bia_typesize_ * (n * brg.ld_block)]; + cvt2ps(bia_dt_, vmm_bias, bias_addr, tail, false, k_mask); + for (int m = 0; m < m_block; m++) { + vaddps(vector(m, n), vmm_bias); + } + } + } + + if (postops_injector_) inject_attr_postops(m_block, n_block, tail); + + if (brg.beta != 0 && brg.with_dst_scales) { + mov(aux_reg_dst_scales, ptr[rsp + reg_dst_scales_offs_]); + const auto addr = ptr[aux_reg_dst_scales]; + auto vmm_scales = vmm_tmp(0); + if (!isa_has_masks(isa)) vmovups(vmm_scales, addr); + + for_(int m = 0; m < m_block; m++) + for (int n = 0; n < n_block; n++) { + auto vmm = vector(m, n); + if (isa_has_masks(isa)) { + vmm = maybe_mask(vector(m, n), tail > 0, false, k_mask); + vmulps(vmm, vmm, addr); + } else { + vmulps(vmm, vmm, vmm_scales); + } + } + } + + if (brg.beta != 0 && brg.zp_type_c != brgemm_broadcast_t::none) { + mov(aux_reg_zp_c_values, ptr[rsp + aux_reg_zp_c_values_offs_]); + auto vmm_zp_c = vmm_tmp(0); + if (brg.zp_type_c == brgemm_broadcast_t::per_tensor) { + if (is_superset(isa, avx512_core)) + vcvtdq2ps(vmm_zp_c, + EVEX_compress_addr(aux_reg_zp_c_values, 0, true)); + else { + uni_vbroadcastss(vmm_zp_c, ptr[aux_reg_zp_c_values]); + uni_vcvtdq2ps(vmm_zp_c, vmm_zp_c); + } + } + for (int n = 0; n < n_block; n++) { + if (brg.zp_type_c == brgemm_broadcast_t::per_n) { + int zp_c_off = zp_c_values_offset(n); + auto zp_c_addr = is_superset(isa, avx512_core) + ? EVEX_compress_addr(aux_reg_zp_c_values, zp_c_off) + : ptr[aux_reg_zp_c_values + zp_c_off]; + cvt2ps(data_type::s32, vmm_zp_c, zp_c_addr, tail, false, + k_mask); + } + for (int m = 0; m < m_block; m++) { + const auto vmm = vector(m, n); + uni_vaddps(vmm, vmm, vmm_zp_c); + } + } + } + + const bool dt_requires_saturation = types::is_integral_dt(out_dt_); + + const reg64_t reg_tmp_gpr = reg_tmp; + auto vmm_lbound = vmm_tmp(0); + auto vmm_ubound = vmm_tmp(1); + if (dt_requires_saturation) { + init_saturate_f32(vmm_lbound, vmm_ubound, reg_tmp_gpr, + data_type::f32, out_dt_); + } + + if (brg.is_bf16_emu) bf16_emu_->init_vcvtneps2bf16(); + + for_(int m = 0; m < m_block; m++) + for (int n = 0; n < n_block; n++) { + // incase of tail, stores are unconditionally masked, regardless + // of `n`, implying n_block must be equal to `1`. + assert(IMPLICATION(tail > 0, n_block == 1)); + auto vmm = vector(m, n); + const size_t offset = out_typesize_ * (m * LDD_ + n * brg.ld_block); + const auto addr = ptr[aux_reg_out + offset]; + + if (dt_requires_saturation) { + saturate_f32(vmm, vmm_lbound, vmm_ubound, out_dt_); + vcvtps2dq(vmm, vmm); + } + + if (is_superset(isa, avx512_core)) { + auto vmm_masked = maybe_mask(vmm, tail > 0, true, k_mask); + Vmm_lower_t vmm_low = Vmm_lower_t(vmm.getIdx()); + auto vmm_low_masked + = maybe_mask(vmm_low, tail > 0, true, k_mask); + switch (out_dt_) { + case data_type::f32: + case data_type::s32: uni_vmovups(addr, vmm_masked); break; + case data_type::bf16: + if (brg.is_bf16_emu) { + bf16_emu_->vcvtneps2bf16(vmm_low, vmm); + vmovdqu16(addr, vmm_low_masked); + } else { + vcvtneps2bf16(vmm_low, vmm); + vmovdqu16(addr, vmm_low_masked); + } + break; + case data_type::f16: + vcvtps2ph(vmm_low, vmm, _op_mxcsr); + vmovdqu16(addr, vmm_low_masked); + break; + case data_type::s8: vpmovsdb(addr, vmm_masked); break; + case data_type::u8: vpmovusdb(addr, vmm_masked); break; + default: assert(!"unknown dst_dt"); + } + } else { + const int simd_w = vreg_traits::vlen / sizeof(float); + const int nelems = tail > 0 ? tail : simd_w; + store_data(out_dt_, vmm, aux_reg_out, offset, nelems); + } + } + } + + void loop_by_N(int m_block, int nb2, int nb2_tail, int nb_tail) { + + if (brg.alpha) { mov(aux_reg_in, reg_in); } + if (brg.beta != 0) { + if (jcp.with_bias) mov(aux_reg_bias, reg_bias); + if (brg.zp_type_c != brgemm_broadcast_t::none) { + mov(aux_reg_zp_c_values, ptr[rsp + reg_zp_c_values_offs_]); + mov(ptr[rsp + aux_reg_zp_c_values_offs_], aux_reg_zp_c_values); + } + if (brg.zp_type_a != brgemm_broadcast_t::none) { + mov(aux_reg_zp_a_comp, ptr[rsp + reg_zp_a_comp_offs_]); + mov(ptr[rsp + aux_reg_zp_a_comp_offs_], aux_reg_zp_a_comp); + } + if (brg.req_s8s8_compensation) { + mov(aux_reg_s8s8_comp, ptr[rsp + reg_s8s8_comp_offs_]); + mov(ptr[rsp + aux_reg_s8s8_comp_offs_], aux_reg_s8s8_comp); + } + mov(aux_reg_scales, reg_scales); + } + mov(aux_reg_out, reg_out); + + for (int n_loop_ = 0; n_loop_ < nb2; n_loop_++) { + apply_post_ops(m_block, n_block2_); + + const auto oc_l_offset = n_block2_ * brg.ld_block; + + add(aux_reg_out, out_typesize_ * oc_l_offset); + if (brg.alpha != 0) { + add(aux_reg_in, inp_typesize_ * oc_l_offset); + } + if (brg.beta != 0) { + if (jcp.with_bias) + add(aux_reg_bias, bia_typesize_ * oc_l_offset); + if (brg.zp_type_c != brgemm_broadcast_t::none) { + mov(aux_reg_zp_c_values, + ptr[rsp + aux_reg_zp_c_values_offs_]); + add(aux_reg_zp_c_values, zp_c_values_offset(n_block2_)); + mov(ptr[rsp + aux_reg_zp_c_values_offs_], + aux_reg_zp_c_values); + } + if (brg.zp_type_a != brgemm_broadcast_t::none) { + mov(aux_reg_zp_a_comp, ptr[rsp + aux_reg_zp_a_comp_offs_]); + add(aux_reg_zp_a_comp, sizeof(int32_t) * oc_l_offset); + mov(ptr[rsp + aux_reg_zp_a_comp_offs_], aux_reg_zp_a_comp); + } + if (brg.req_s8s8_compensation) { + mov(aux_reg_s8s8_comp, ptr[rsp + aux_reg_s8s8_comp_offs_]); + add(aux_reg_s8s8_comp, sizeof(int32_t) * oc_l_offset); + mov(ptr[rsp + aux_reg_s8s8_comp_offs_], aux_reg_s8s8_comp); + } + + add(aux_reg_scales, is_oc_scale_ * sizeof(float) * oc_l_offset); + } + } + if (nb2_tail > 0) { + apply_post_ops(m_block, nb2_tail); + const auto oc_l_offset = nb2_tail * brg.ld_block; + + add(aux_reg_out, out_typesize_ * oc_l_offset); + if (brg.alpha != 0) { + add(aux_reg_in, inp_typesize_ * oc_l_offset); + } + if (brg.beta != 0) { + if (jcp.with_bias) + add(aux_reg_bias, bia_typesize_ * oc_l_offset); + if (brg.zp_type_c != brgemm_broadcast_t::none) { + mov(aux_reg_zp_c_values, + ptr[rsp + aux_reg_zp_c_values_offs_]); + add(aux_reg_zp_c_values, zp_c_values_offset(nb2_tail)); + mov(ptr[rsp + aux_reg_zp_c_values_offs_], + aux_reg_zp_c_values); + } + if (brg.zp_type_a != brgemm_broadcast_t::none) { + mov(aux_reg_zp_a_comp, ptr[rsp + aux_reg_zp_a_comp_offs_]); + add(aux_reg_zp_a_comp, sizeof(int32_t) * oc_l_offset); + mov(ptr[rsp + aux_reg_zp_a_comp_offs_], aux_reg_zp_a_comp); + } + if (brg.req_s8s8_compensation) { + mov(aux_reg_s8s8_comp, ptr[rsp + aux_reg_s8s8_comp_offs_]); + add(aux_reg_s8s8_comp, sizeof(int32_t) * oc_l_offset); + mov(ptr[rsp + aux_reg_s8s8_comp_offs_], aux_reg_s8s8_comp); + } + + add(aux_reg_scales, is_oc_scale_ * sizeof(float) * oc_l_offset); + } + } + if (nb_tail > 0) { + apply_post_ops(m_block, 1, nb_tail); + + if (brg.alpha != 0) { add(aux_reg_in, inp_typesize_ * (nb_tail)); } + if (brg.beta != 0) { + if (jcp.with_bias) add(aux_reg_bias, bia_typesize_ * (nb_tail)); + if (brg.zp_type_c != brgemm_broadcast_t::none) { + mov(aux_reg_zp_c_values, + ptr[rsp + aux_reg_zp_c_values_offs_]); + add(aux_reg_zp_c_values, zp_c_values_offset(1, nb_tail)); + mov(ptr[rsp + aux_reg_zp_c_values_offs_], + aux_reg_zp_c_values); + } + if (brg.zp_type_a != brgemm_broadcast_t::none) { + mov(aux_reg_zp_a_comp, ptr[rsp + aux_reg_zp_a_comp_offs_]); + add(aux_reg_zp_a_comp, sizeof(int32_t) * nb_tail); + mov(ptr[rsp + aux_reg_zp_a_comp_offs_], aux_reg_zp_a_comp); + } + if (brg.req_s8s8_compensation) { + mov(aux_reg_s8s8_comp, ptr[rsp + aux_reg_s8s8_comp_offs_]); + add(aux_reg_s8s8_comp, sizeof(int32_t) * nb_tail); + mov(ptr[rsp + aux_reg_s8s8_comp_offs_], aux_reg_s8s8_comp); + } + add(aux_reg_scales, is_oc_scale_ * bia_typesize_ * (nb_tail)); + } + add(aux_reg_out, out_typesize_ * (nb_tail)); + } + } + + void generate() override { + preamble(); + + sub(rsp, stack_space_needed_); + + int nb = brg.load_dim / brg.ld_block; + int nb_tail = brg.load_dim % brg.ld_block; + + int nb2 = nb / n_block2_; + int nb2_tail = nb % n_block2_; + int n_block = (nb2 == 0) ? nstl::max(1, nb2_tail) : n_block2_; + + int m_max_regs = (brg.is_bf16_emu ? 24 : max_vregs_ - 4) / n_block; + int m_block = nstl::min(brg.bcast_dim, m_max_regs); + + int mb = brg.bcast_dim / m_block; + int mb_tail = brg.bcast_dim % m_block; + + if (isa_has_masks(isa)) { + const auto full_mask = size_t {0xffffffffffffffff}; + const auto tail_mask = size_t((1 << nb_tail) - 1); + + reg64_t reg_mask = reg_tmp; + mov(reg_mask, full_mask); + kmovq(k_full_mask, reg_mask); + mov(reg_mask, tail_mask); + kmovq(k_tail_mask, reg_mask); + } + + if (brg.alpha != 0) { mov(reg_in, ptr[param1 + GET_OFF(ptr_in)]); } + if (brg.beta != 0) { + mov(reg_scales, ptr[param1 + GET_OFF(ptr_scales)]); + mov(reg_apply_comp, ptr[param1 + GET_OFF(apply_comp)]); + mov(ptr[rsp + reg_apply_comp_offs_], reg_apply_comp); + + if (jcp.with_bias) mov(reg_bias, ptr[param1 + GET_OFF(ptr_bias)]); + if (brg.zp_type_c != brgemm_broadcast_t::none) { + mov(reg_zp_c_values, ptr[param1 + GET_OFF(c_zp_values)]); + mov(ptr[rsp + reg_zp_c_values_offs_], reg_zp_c_values); + } + if (brg.zp_type_a != brgemm_broadcast_t::none) { + mov(reg_zp_a_comp, ptr[param1 + GET_OFF(a_zp_compensation)]); + mov(ptr[rsp + reg_zp_a_comp_offs_], reg_zp_a_comp); + + mov(reg_zp_a_val, ptr[param1 + GET_OFF(a_comp_val)]); + mov(ptr[rsp + reg_zp_a_val_offs_], reg_zp_a_val); + } + if (brg.req_s8s8_compensation) { + mov(reg_s8s8_comp, ptr[param1 + GET_OFF(s8s8_compensation)]); + mov(ptr[rsp + reg_s8s8_comp_offs_], reg_s8s8_comp); + } + if (brg.with_dst_scales) { + mov(reg_dst_scales, ptr[param1 + GET_OFF(ptr_dst_scales)]); + mov(ptr[rsp + reg_dst_scales_offs_], reg_dst_scales); + } + } + mov(reg_out, ptr[param1 + GET_OFF(ptr_out)]); + + // brg.alpha == 0 means initialize registers, 1 means read from input + // brg.beta == 0 means skip postwork, 1 means do postwork + if (brg.alpha == 0 && brg.beta == 0) { + for_(int m = 0; m < m_block; m++) + for (int n = 0; n < n_block; n++) { + auto vmm = Vmm(m * n_block + n); + uni_vpxor(vmm, vmm, vmm); + } + } + + for (int mb_ = 0; mb_ < mb; mb_++) { + loop_by_N(m_block, nb2, nb2_tail, nb_tail); + + if (brg.alpha != 0) + add(reg_in, inp_typesize_ * (m_block * brg.LDC)); + add(reg_out, out_typesize_ * (m_block * LDD_)); + } + if (mb_tail > 0) loop_by_N(mb_tail, nb2, nb2_tail, nb_tail); + + add(rsp, stack_space_needed_); + + postamble(); + + if (postops_injector_) postops_injector_->prepare_table(); + } +}; + +#undef GET_OFF + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_primitive_conf.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_primitive_conf.hpp new file mode 100644 index 0000000000000000000000000000000000000000..28106812317ce9d0d9d85270d542ee7bf20a8eb5 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_primitive_conf.hpp @@ -0,0 +1,93 @@ +/******************************************************************************* +* Copyright 2020-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_BRGEMM_PRIMITIVE_CONF_HPP +#define CPU_X64_JIT_BRGEMM_PRIMITIVE_CONF_HPP + +#include "cpu/x64/brgemm/brgemm_types.hpp" +#include "cpu/x64/jit_primitive_conf.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +struct jit_brgemm_primitive_conf_t { + prop_kind_t prop_kind; + conv_harness_t harness; + int simd_w; + int ndims; + int mb; + int ngroups, ic, oc, oc_without_padding, ic_without_padding; + int id, ih, iw, od, oh, ow, os; + int f_pad, l_pad, t_pad; + int back_pad, r_pad, b_pad; + int kd, kh, kw; + int stride_d, stride_h, stride_w; + int dilate_d, dilate_h, dilate_w; + format_tag_t src_tag, wei_tag, dst_tag; // temporary workaround + bool is_wei_layout_any; + bool with_bias; + bool with_sum; + bool with_eltwise; + bool with_binary; + bool with_scales; + bool req_s8s8_compensation; + int nb_ic, ic_block, ic_block_ext; + int nb_oc, oc_block, oc_block_ext; + int nb_iw, iw_block; + int nb_ow, ow_block; + int nb_os, os_block; + int nb_oc_blocking; + int nb_ic_blocking; + int nb_os_blocking; + + data_type_t src_dt; + data_type_t dst_dt; + data_type_t wei_dt; + data_type_t acc_dt; + data_type_t bia_dt; + + bool is_amx; + bool use_buffer; + bool use_buffer_a; + bool use_buffer_b; + bool is_bf32; + + int is_oc_scale; + + int LDA, LDB, LDC, LDD; + int M, N, K, M_tail, N_tail, K_tail; + int gemm_batch_size, adjusted_batch_size; + brgemm_batch_kind_t brg_type; + int num_gemm_kernels; + int nthr, nthr_mb, nthr_oc_b, nthr_ic_b; + + cpu_isa_t isa; + bool use_uker; + bool use_interleave_stores; + int amx_buf_size_per_thread; + brgemm_kernel_prefetching_t hint_prefetching + = brgemm_kernel_prefetching_t::brgemm_prf_default; + bool with_dst_scales; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_transpose_utils.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_transpose_utils.hpp new file mode 100644 index 0000000000000000000000000000000000000000..94d8a2639c547a71aaef18e4d93779c87a80d59f --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_brgemm_transpose_utils.hpp @@ -0,0 +1,228 @@ +/******************************************************************************* +* Copyright 2020-2022 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_BRGEMM_TRANSPOSE_UTILS_HPP +#define CPU_X64_JIT_BRGEMM_TRANSPOSE_UTILS_HPP + +#include "cpu/x64/jit_brgemm_primitive_conf.hpp" +#include "cpu/x64/jit_generator.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +struct jit_brgemm_trans_src_t { + struct ctx_t { + const void *src; + const void *tr_src; + + dim_t current_gemm_batch; + dim_t current_M, current_K; + }; + + virtual void operator()(ctx_t *ctx) = 0; + virtual status_t create_kernel() = 0; + + jit_brgemm_trans_src_t(const jit_brgemm_primitive_conf_t *conf) + : conf_(conf) {} + virtual ~jit_brgemm_trans_src_t() {} + + const jit_brgemm_primitive_conf_t *conf_; +}; + +struct jit_brgemm_copy_to_coarse_t : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_brgemm_copy_to_coarse_t) + + struct ctx_t { + const void *data; + const void *tr_data; + + dim_t os_work; + dim_t last_row_blk; + }; + + void operator()(ctx_t *ctx) { jit_generator::operator()(ctx); } + status_t create_kernel() override { return jit_generator::create_kernel(); } + + jit_brgemm_copy_to_coarse_t(const jit_brgemm_primitive_conf_t *conf) + : jit_generator(jit_name()) + , conf_(conf) + , typesize_(sizeof(float) / data_type_vnni_granularity(conf_->wei_dt)) + , is_fwd_dir_(utils::one_of(conf_->prop_kind, + prop_kind::forward_training, prop_kind::forward_inference)) + , row_block_size_(is_fwd_dir_ ? conf_->ic_block : conf_->oc_block) + , row_size_(is_fwd_dir_ ? conf_->ic_without_padding + : conf_->oc_without_padding) + , tr_row_size_(conf_->LDA) + , row_granularity_(granularity_in_bytes / typesize_) + , row_step_(zmm_size_in_bytes / typesize_) + , data_stride_(row_size_ * typesize_) + , tr_data_stride_(tr_row_size_ * typesize_) { + + // Kernel is supposed to be called under the following constraints + assert(is_superset(conf_->isa, avx512_core_amx)); + assert(row_size_ % row_granularity_ != 0); + + MAYBE_UNUSED(row_granularity_); + } + ~jit_brgemm_copy_to_coarse_t() {} + +private: + enum { + zmm_size_in_bytes = 64, + row_loop_unroll = 16, + granularity_in_bytes = 4, + }; + + const jit_brgemm_primitive_conf_t *conf_; + const int typesize_; + const bool is_fwd_dir_; + const int row_block_size_, row_size_, tr_row_size_, row_granularity_, + row_step_; + const dim_t data_stride_, tr_data_stride_; + + inline size_t addr_offset(int row_idx) { + return row_idx * row_step_ * typesize_; + } + + inline Xbyak::Zmm get_zmm_copy(int row_idx) const { + assert(row_idx >= 0 && row_idx < row_loop_unroll); + return Xbyak::Zmm(row_idx); + } + + const Xbyak::Zmm zmm_zero = Xbyak::Zmm(row_loop_unroll); + const Xbyak::Zmm zmm_row_tail = Xbyak::Zmm(row_loop_unroll + 1); + + const Xbyak::Opmask reg_m_full_row_tail_load = k7; + const Xbyak::Opmask reg_m_full_row_tail_store = k6; + const Xbyak::Opmask reg_m_last_row_tail_load = k5; + const Xbyak::Opmask reg_m_last_row_tail_store = k4; + + const Xbyak::Reg64 reg_data = rax; + const Xbyak::Reg64 reg_tr_data = rbx; + + const Xbyak::Reg64 reg_os_work = r11; + const Xbyak::Reg64 reg_last_row_blk = r12; + const Xbyak::Reg64 reg_tail_mask = r13; + + void copy_os_loop(); + void copy_row_loop(); + + void copy_row_blks(int num_row_blks); + void copy_row_tail(bool is_last_iteration, int row_offset); + void zero_out_rows(); + + void set_full_row_tail_masks(); + void set_last_row_tail_masks(); + + void generate() override; +}; + +struct jit_brgemm_trans_to_vnni_t { + struct ctx_t { + const void *src; + const void *tr_src; + + dim_t current_gemm_batch; + dim_t current_col_size, current_row_size; + }; + + typedef enum matrix_to_transform { + matrix_B, + matrix_C + } matrix_to_transform_t; + + virtual void operator()(ctx_t *ctx) = 0; + virtual status_t create_kernel() = 0; + + jit_brgemm_trans_to_vnni_t(const jit_brgemm_primitive_conf_t *conf, + matrix_to_transform_t matrix_to_transform) + : conf_(conf), matrix_to_transform_(matrix_to_transform) {} + virtual ~jit_brgemm_trans_to_vnni_t() {} + + const jit_brgemm_primitive_conf_t *conf_; + matrix_to_transform_t matrix_to_transform_; +}; + +struct jit_brgemm_trans_wei_t { + struct ctx_t { + const void *src; + const void *tr_src; + + dim_t current_gemm_batch; + dim_t current_N, current_K; + }; + + virtual void operator()(ctx_t *ctx) = 0; + virtual status_t create_kernel() = 0; + + jit_brgemm_trans_wei_t(const jit_brgemm_primitive_conf_t *conf) + : conf_(conf) {} + virtual ~jit_brgemm_trans_wei_t() {} + + const jit_brgemm_primitive_conf_t *conf_; +}; + +struct jit_amx_ip_trans_diff_wei { + struct ctx_t { + const void *src; + const void *dst; + + size_t last_oc_block; + size_t last_ic_block; + }; + + virtual void operator()(ctx_t *ctx) = 0; + virtual status_t create_kernel() = 0; + + jit_amx_ip_trans_diff_wei(const jit_brgemm_primitive_conf_t *jbgp, + const int ext_ic_block, const int ext_oc_block) + : jbgp_(jbgp) + , ext_ic_block_(ext_ic_block) + , ext_oc_block_(ext_oc_block) {} + + virtual ~jit_amx_ip_trans_diff_wei() {} + + const jit_brgemm_primitive_conf_t *jbgp_; + + int ext_ic_block_ = 0; + int ext_oc_block_ = 0; +}; + +status_t create_brgemm_trans_src( + std::unique_ptr &trans_ker, + const jit_brgemm_primitive_conf_t *conf); +status_t create_brgemm_copy_to_coarse( + std::unique_ptr ©_ker, + const jit_brgemm_primitive_conf_t *conf); +status_t create_brgemm_trans_to_vnni( + std::unique_ptr &trans_ker, + const jit_brgemm_primitive_conf_t *conf, + jit_brgemm_trans_to_vnni_t::matrix_to_transform_t matrix_to_transform); +status_t create_brgemm_trans_wei( + std::unique_ptr &trans_ker, + const jit_brgemm_primitive_conf_t *conf); +status_t create_brgemm_amx_ip_trans_wei( + std::unique_ptr &trans_ker, + const jit_brgemm_primitive_conf_t *conf, const int ext_ic_block, + const int ext_oc_block); +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_gemm_inner_product_utils.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_gemm_inner_product_utils.hpp new file mode 100644 index 0000000000000000000000000000000000000000..f3400dd7d77eab6d9ed4f13d0365a43e44578a73 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_gemm_inner_product_utils.hpp @@ -0,0 +1,51 @@ +/******************************************************************************* +* Copyright 2020-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_GEMM_INNER_PRODUCT_UTILS_HPP +#define CPU_X64_JIT_GEMM_INNER_PRODUCT_UTILS_HPP + +#include "cpu/gemm_inner_product_utils.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { +namespace inner_product_utils { + +cpu::inner_product_utils::pp_kernel_t *jit_pp_kernel_create(size_t OC, + size_t MB, dim_t dst_mb_stride, const primitive_attr_t *attr, + data_type_t bias_dt, data_type_t acc_dt, const memory_desc_t *dst_md, + bool skip_sum); + +inline cpu_isa_t get_max_jit_pp_kernel_supported_isa() { +#define CASE(isa) \ + do { \ + if (mayiuse(isa)) return isa; \ + } while (false) + CASE(avx512_core_bf16); + CASE(avx512_core); + CASE(avx2); +#undef CASE + return sse41; +} + +} // namespace inner_product_utils +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_gemm_x8s8s32x_conv_zp_src_pad_comp.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_gemm_x8s8s32x_conv_zp_src_pad_comp.hpp new file mode 100644 index 0000000000000000000000000000000000000000..91dcb7cbff420433827dd7937ca17c8cac9ddba6 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_gemm_x8s8s32x_conv_zp_src_pad_comp.hpp @@ -0,0 +1,130 @@ +/******************************************************************************* +* Copyright 2021 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_GEMM_X8S8S32X_CONV_ZP_SRC_PAD_COMP_HPP +#define CPU_X64_JIT_GEMM_X8S8S32X_CONV_ZP_SRC_PAD_COMP_HPP + +#include + +#include "common/c_types_map.hpp" +#include "cpu/x64/cpu_isa_traits.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { + +struct conv_gemm_conf_t; + +namespace x64 { + +class jit_generator; + +namespace gemm_x8s8s32x_convolution_utils { + +struct jit_gemm_x8s8s32x_zp_pad_comp_helper { + jit_gemm_x8s8s32x_zp_pad_comp_helper(jit_generator *host, + const conv_gemm_conf_t &jcp, const Xbyak::Reg64 ®_zp_pad_comp, + const Xbyak::Reg64 ®_zp_pad_comp_temp, + const Xbyak::Reg8 &should_apply_zp_src_pad, const dim_t ndims); + +public: + void init(const dim_t off_w, const dim_t off_h, const dim_t off_w_size, + const dim_t off_w_off, const dim_t off_zp_pad_com_base_off, + const dim_t off_g_oc_offset_prologue, const dim_t off_g_oc_offset, + const dim_t off_zp_src_pad_com_d_offset, + const dim_t off_should_apply_zp_src_pad_comp_d); + void fin(); + void load_next_point_zp_src_comp_pad_addr(); + void zp_src_comp_pad_operation( + const std::function &op); + struct zp_src_pad_com_d { + bool should_apply_pad_comp_d; + dim_t offset; + }; + + zp_src_pad_com_d calculate_zp_src_pad_com_d(const dim_t d_off) const; + +private: + enum bound { upper, lower }; + + dim_t calculate_lower_bound_dim(const dim_t begin_comp_pad) const noexcept; + dim_t calculate_upper_bound_dim( + const dim_t output_size, const dim_t end_comp_pad) const noexcept; + + void set_up_initial_args(const dim_t off_w, const dim_t off_h, + const dim_t off_w_size, const dim_t off_w_off, + const dim_t off_zp_pad_com_base_off, + const dim_t off_g_oc_offset_prologue, const dim_t off_g_oc_offset, + const dim_t off_zp_src_pad_com_d_offset, + const dim_t off_should_apply_zp_src_pad_comp_d); + void check_bound(const Xbyak::Reg64 ®_dim, + const Xbyak::Address &result_addr, const dim_t bound_value, + const bound bound_kind); + void load_zp_src_comp_pad_addr_if_needed(const Xbyak::Address &g_oc_offset); + void calculate_zp_src_comp_pad_effective_addr( + const Xbyak::Address &g_oc_offset); + void get_zp_pad_com_dim(const Xbyak::Address &dim_under_lower_bound, + const Xbyak::Address &dim_over_eq_upper_bound, + const dim_t begin_pad, dim_t mid_pad, const dim_t end_pad, + const dim_t out_dim_size, const Xbyak::Address &out_point_dim, + const Xbyak::Address &result); + void should_apply_zp_src_pad(); + void next_point(); + + jit_generator *const host_; + const conv_gemm_conf_t &jcp_; + const Xbyak::Address w_addr_; + const Xbyak::Address h_addr_; + const Xbyak::Address w_size_addr_; + const Xbyak::Address w_off_addr_; + const Xbyak::Address zp_pad_com_h_; + const Xbyak::Address zp_pad_com_w_; + const Xbyak::Address zp_pad_com_base_; + const Xbyak::Address g_oc_offset_prologue_; + const Xbyak::Address g_oc_offset_; + const Xbyak::Address zp_pad_com_d_offset_; + + const Xbyak::Address h_under_lower_bound_; + const Xbyak::Address h_over_eq_upper_bound_; + const Xbyak::Address w_under_lower_bound_; + const Xbyak::Address w_over_eq_upper_bound_; + const Xbyak::Address should_apply_zp_src_pad_comp_d_; + const Xbyak::Reg8 &should_apply_zp_src_pad_; + + const dim_t lower_h_bound_; + const dim_t upper_h_bound_; + const dim_t lower_w_bound_; + const dim_t upper_w_bound_; + const dim_t lower_d_bound_; + const dim_t upper_d_bound_; + + const bool with_zp_pad_com_d_; + const bool with_zp_pad_com_h_; + + const Xbyak::Reg64 ®_zp_pad_comp_; + const Xbyak::Reg64 ®_zp_pad_comp_tmp_; + // 10 * 4 (qword_size) + 5 * 1 (byte size) = 85 + // 85 aligned to 4 = 88 + static constexpr dim_t reserved_stack_size_ = 88; +}; + +} // namespace gemm_x8s8s32x_convolution_utils +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_gemm_x8s8s32x_convolution_utils.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_gemm_x8s8s32x_convolution_utils.hpp new file mode 100644 index 0000000000000000000000000000000000000000..98142197deeb835b6270c2aa13318bf18ed70da9 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_gemm_x8s8s32x_convolution_utils.hpp @@ -0,0 +1,40 @@ +/******************************************************************************* +* Copyright 2020-2022 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_GEMM_X8S8S32X_CONVOLUTION_UTILS_HPP +#define CPU_X64_JIT_GEMM_X8S8S32X_CONVOLUTION_UTILS_HPP + +#include "cpu/gemm_x8s8s32x_convolution_utils.hpp" +#include "cpu/x64/injectors/injector_utils.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { +namespace gemm_x8s8s32x_convolution_utils { + +cpu::gemm_x8s8s32x_convolution_utils::pp_ker_t *jit_pp_ker_create( + const convolution_pd_t *pd, const conv_gemm_conf_t &jcp); +bool mayiuse_jit_pp_kernel(data_type_t dst_dt) noexcept; +bool post_ops_ok(const post_ops_t &post_ops, const memory_desc_wrapper *dst_d); + +} // namespace gemm_x8s8s32x_convolution_utils +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_generator.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_generator.hpp new file mode 100644 index 0000000000000000000000000000000000000000..64a28a0b5f1f6e834294f784335169d9cfb64a47 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_generator.hpp @@ -0,0 +1,2721 @@ +/******************************************************************************* +* Copyright 2016-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_GENERATOR_HPP +#define CPU_X64_JIT_GENERATOR_HPP + +#include +#include + +#include "common/bit_cast.hpp" +#include "common/compiler_workarounds.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/x64/cpu_isa_traits.hpp" + +#include "cpu/jit_utils/jit_utils.hpp" + +#if defined(_WIN32) && !defined(__GNUC__) +#define STRUCT_ALIGN(al, ...) __declspec(align(al)) __VA_ARGS__ +#else +#define STRUCT_ALIGN(al, ...) __VA_ARGS__ __attribute__((__aligned__(al))) +#endif + +#if defined(_WIN32) +#define OFFSET_SHADOWSPACE 0x28 +#endif + +#if GCC_WA_NO_TREE_DOMINATOR_OPTS +#define ATTRIBUTE_OPTIMIZE __attribute__((optimize("no-tree-dominator-opts"))) +#else +#define ATTRIBUTE_OPTIMIZE +#endif + +#define DECLARE_CPU_JIT_AUX_FUNCTIONS(gen_name) \ + const char *name() const override { return STRINGIFY(gen_name); } \ + const char *source_file() const override { return __FILE__; } \ + static const char *jit_name() { \ + static constexpr char ret[] = "/oneDNN:" STRINGIFY(gen_name); \ + return ret; \ + } + +// If assertions are broken during code generation, then set an Xbyak error. +// Warning: this may cause kernel creation failure, so use wisely! +#define JIT_ASSERT(condition) \ + do { \ + assert(condition); \ + if (!(condition)) XBYAK_THROW(Xbyak::ERR_INTERNAL); \ + } while (false) + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +// TODO: move this to jit_generator class? +namespace { + +typedef enum { + MAX_CODE_SIZE = 256 * 1024, +} max_code_size_t; + +// TODO: move this somewhere else? Although this is only used by jit kernels +// (Roma) +static inline int float2int(float x) { + return utils::bit_cast(x); +} + +static inline void tc_configure_tile( + palette_config_t *tc, int t, int rows, int cols) { + const bool rows_ok = (size_t)t < sizeof(tc->rows) / sizeof(tc->rows[0]); + const bool cols_ok = (size_t)t < sizeof(tc->cols) / sizeof(tc->cols[0]); + if (rows_ok && cols_ok) { + tc->rows[t] = rows; + tc->cols[t] = cols; + } else { + assert(!"out of range"); + } +} + +// TODO: A GPR class that hides ABI details from the JIT kernels and allows +// numbering registers from 0 to 14 (x86_64) / 6 (x32) (gpr0, gpr1, ...) and +// stack register (sr). +// +// This will allow using syntax like this: +// +// param = gpr0; +// reg_input = gpr0; +// reg_output = gpr1; +// ... +// +// #ifndef XBYAK64 +// mov(param, ptr[sr]) +// #endif +// +// (Roma) + +} // namespace + +#ifdef XBYAK64 +constexpr Xbyak::Operand::Code abi_save_gpr_regs[] = { + Xbyak::Operand::RBP, + Xbyak::Operand::RBX, + Xbyak::Operand::R12, + Xbyak::Operand::R13, + Xbyak::Operand::R14, + Xbyak::Operand::R15, +#ifdef _WIN32 + Xbyak::Operand::RDI, + Xbyak::Operand::RSI, +#endif +}; + +constexpr Xbyak::Operand::Code abi_param_regs[] = { +#ifdef _WIN32 + Xbyak::Operand::RCX, Xbyak::Operand::RDX, Xbyak::Operand::R8, + Xbyak::Operand::R9 +#else + Xbyak::Operand::RDI, Xbyak::Operand::RSI, Xbyak::Operand::RDX, + Xbyak::Operand::RCX, Xbyak::Operand::R8, Xbyak::Operand::R9 +#endif +}; + +constexpr Xbyak::Operand::Code abi_not_param_reg = +#ifdef _WIN32 + Xbyak::Operand::RDI; +#else + Xbyak::Operand::RCX; +#endif + +#define abi_param1 Xbyak::Reg64(abi_param_regs[0]) +#define abi_param2 Xbyak::Reg64(abi_param_regs[1]) +#define abi_param3 Xbyak::Reg64(abi_param_regs[2]) +#define abi_param4 Xbyak::Reg64(abi_param_regs[3]) +#define abi_param5 Xbyak::Reg64(abi_param_regs[4]) +#define abi_param6 Xbyak::Reg64(abi_param_regs[5]) +#define abi_not_param1 Xbyak::Reg64(abi_not_param_reg) + +#endif + +class jit_generator : public Xbyak::MmapAllocator, + public Xbyak::CodeGenerator, + public c_compatible { +public: + using c_compatible::operator new; + using c_compatible::operator new[]; + using c_compatible::operator delete; + using c_compatible::operator delete[]; + +private: + const size_t xmm_len = 16; +#ifdef _WIN32 + const size_t xmm_to_preserve_start = 6; + const size_t xmm_to_preserve = 10; +#else + const size_t xmm_to_preserve_start = 0; + const size_t xmm_to_preserve = 0; +#endif + + const size_t num_abi_save_gpr_regs + = sizeof(abi_save_gpr_regs) / sizeof(abi_save_gpr_regs[0]); + + const size_t size_of_abi_save_regs + = num_abi_save_gpr_regs * rax.getBit() / 8 + + xmm_to_preserve * xmm_len; + +public: + enum { + _cmp_eq_oq = 0u, + _cmp_lt_os = 1u, + _cmp_le_os = 2u, + _cmp_neq_uq = 4u, + _cmp_nlt_us = 5u, + _cmp_nle_us = 6u, + + _op_floor = 1u, + _op_mxcsr = 4u, + }; + + Xbyak::Reg64 param1 = abi_param1; + const int EVEX_max_8b_offt = 0x200; + const Xbyak::Reg64 reg_EVEX_max_8b_offt = rbp; + + inline size_t get_size_of_abi_save_regs() { return size_of_abi_save_regs; } + + void preamble() { + if (xmm_to_preserve) { + sub(rsp, xmm_to_preserve * xmm_len); + for (size_t i = 0; i < xmm_to_preserve; ++i) + uni_vmovdqu(ptr[rsp + i * xmm_len], + Xbyak::Xmm(xmm_to_preserve_start + i)); + } + for (size_t i = 0; i < num_abi_save_gpr_regs; ++i) { + push(Xbyak::Reg64(abi_save_gpr_regs[i])); + // Stack magic: save rsp into rbp state to be able to unwind stack. + if (i == 0) mov(rbp, rsp); + } +#ifndef DNNL_ENABLE_MEM_DEBUG + // do not use RBP in mem debug mode to enable backtracing from jit code + if (is_valid_isa(avx512_core)) { + mov(reg_EVEX_max_8b_offt, 2 * EVEX_max_8b_offt); + } +#endif + +#ifdef DNNL_ENABLE_MEM_DEBUG + // This section poisons vector registers with NaNs to catch situations + // when leftover trash in the register is used in a valid instruction + // without handling trash first. + { + // Preserve GPR since GeMM code relies on this one. + push(abi_not_param1); + if (is_valid_isa(avx512_core)) { + for (int i = 0; i < 32; i++) { + init_vmm(Xbyak::Zmm(i), abi_not_param1, NAN); + } + } else if (is_valid_isa(avx)) { + for (int i = 0; i < 16; i++) { + init_vmm(Xbyak::Ymm(i), abi_not_param1, NAN); + } + } else { + for (int i = 0; i < 16; i++) { + init_vmm(Xbyak::Xmm(i), abi_not_param1, NAN); + } + } + pop(abi_not_param1); + } +#endif + } + + // This function returns the address on the stack of the fist argument + // that is not passed by register + // By default it assumes to be called after the prologue + // Note: that we cannot use RBP inside as we override it in preamble + // for address computation in EVEX instructions + inline const Xbyak::RegExp get_stack_params_address( + bool after_prolog = true) { + int saved_regs_size = after_prolog ? get_size_of_abi_save_regs() : 0; +#ifdef _WIN32 + // Using stack layout described in MS ABI + // (https://docs.microsoft.com/en-us/cpp/build/stack-usage?view=vs-2019) + // here, the return address and the first 4 parameters are allocated + // on the stack + int first_params_and_return_addr_size = 40; +#else + // In System V ABI, only the return address is stacked + // before the arguments + int first_params_and_return_addr_size = 8; +#endif + return rsp + saved_regs_size + first_params_and_return_addr_size; + } + + void uni_vzeroupper() { + if (mayiuse(avx)) vzeroupper(); + } + + void postamble() { + for (size_t i = 0; i < num_abi_save_gpr_regs; ++i) + pop(Xbyak::Reg64(abi_save_gpr_regs[num_abi_save_gpr_regs - 1 - i])); + if (xmm_to_preserve) { + for (size_t i = 0; i < xmm_to_preserve; ++i) + uni_vmovdqu(Xbyak::Xmm(xmm_to_preserve_start + i), + ptr[rsp + i * xmm_len]); + add(rsp, xmm_to_preserve * xmm_len); + } + uni_vzeroupper(); + ret(); + } + + template + Xbyak::Address EVEX_compress_addr( + Xbyak::Reg64 base, T raw_offt, bool bcast = false) { + using Xbyak::Address; + using Xbyak::Reg64; + using Xbyak::RegExp; + using Xbyak::Zmm; + + assert(raw_offt <= INT_MAX); + auto offt = static_cast(raw_offt); + + int scale = 0; + +#ifndef DNNL_ENABLE_MEM_DEBUG + // do not use RBP in mem debug mode to enable backtracing from jit code + if (EVEX_max_8b_offt <= offt && offt < 3 * EVEX_max_8b_offt) { + offt = offt - 2 * EVEX_max_8b_offt; + scale = 1; + } else if (3 * EVEX_max_8b_offt <= offt + && offt < 5 * EVEX_max_8b_offt) { + offt = offt - 4 * EVEX_max_8b_offt; + scale = 2; + } +#endif + + auto re = RegExp() + base + offt; + if (scale) re = re + reg_EVEX_max_8b_offt * scale; + + if (bcast) + return zword_b[re]; + else + return zword[re]; + } + + template + Xbyak::Address maybe_EVEX_compress_addr( + Xbyak::Reg64 base, T raw_offt, bool bcast = false) { + if (is_valid_isa(avx512_core)) + return EVEX_compress_addr(base, raw_offt, bcast); + else { + assert(!bcast); + assert(raw_offt <= INT_MAX); + return ptr[base + raw_offt]; + } + } + + Xbyak::Address make_safe_addr(const Xbyak::Reg64 ®_out, size_t offt, + const Xbyak::Reg64 &tmp_reg, bool bcast = false) { + if (offt > INT_MAX) { + mov(tmp_reg, offt); + return bcast ? ptr_b[reg_out + tmp_reg] : ptr[reg_out + tmp_reg]; + } else { + return bcast ? ptr_b[reg_out + offt] : ptr[reg_out + offt]; + } + } + + Xbyak::Address EVEX_compress_addr_safe(const Xbyak::Reg64 &base, + size_t raw_offt, const Xbyak::Reg64 ®_offt, bool bcast = false) { + if (raw_offt > INT_MAX) { + return make_safe_addr(base, raw_offt, reg_offt, bcast); + } else { + return EVEX_compress_addr(base, raw_offt, bcast); + } + } + + void safe_add(const Xbyak::Reg64 &base, size_t raw_offt, + const Xbyak::Reg64 ®_offt) { + if (raw_offt > INT_MAX) { + mov(reg_offt, raw_offt); + add(base, reg_offt); + } else { + add(base, raw_offt); + } + } + + void safe_sub(const Xbyak::Reg64 &base, size_t raw_offt, + const Xbyak::Reg64 ®_offt) { + if (raw_offt > INT_MAX) { + mov(reg_offt, raw_offt); + sub(base, reg_offt); + } else { + sub(base, raw_offt); + } + } + + // Disallow char-based labels completely + void L(const char *label) = delete; + void L(Xbyak::Label &label) { Xbyak::CodeGenerator::L(label); } + + void L_aligned(Xbyak::Label &label, int alignment = 16) { + align(alignment); + L(label); + } + + void uni_vpxor(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op) { + if (is_valid_isa(avx512_core)) + vpxord(x1, x2, op); + else if (is_valid_isa(avx)) + vpxor(x1, x2, op); + else { + assert(x1.isEqualIfNotInherited(x2)); + pxor(x2, op); + } + } + void uni_vpxor(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op) { + if (is_valid_isa(avx512_core)) + vpxord(x1, x2, op); + else if (is_valid_isa(avx2)) + vpxor(x1, x2, op); + else + vxorps(x1, x2, op); + } + void uni_vpxor(const Xbyak::Zmm &x1, const Xbyak::Zmm &x2, + const Xbyak::Operand &op) { + vpxord(x1, x2, op); + } + + void uni_vmovss(const Xbyak::Address &addr, const Xbyak::Xmm &x) { + if (is_valid_isa(avx)) + vmovss(addr, x); + else + movss(addr, x); + } + void uni_vmovss(const Xbyak::Xmm &x, const Xbyak::Address &addr) { + if (is_valid_isa(avx)) + vmovss(x, addr); + else + movss(x, addr); + } + void uni_vmovss(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2) { + if (is_valid_isa(avx)) + vmovss(x1, x1, x2); + else + movss(x1, x2); + } + void uni_vmovss(const Xbyak::Address &addr, const Xbyak::Ymm &x) { + vmovss(addr, Xbyak::Xmm(x.getIdx())); + } + void uni_vmovss(const Xbyak::Ymm &x, const Xbyak::Address &addr) { + vmovss(Xbyak::Xmm(x.getIdx()), addr); + } + void uni_vmovss(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2) { + vmovss(Xbyak::Xmm(x1.getIdx()), Xbyak::Xmm(x2.getIdx())); + } + + void uni_vmovsd(const Xbyak::Address &addr, const Xbyak::Xmm &x) { + if (is_valid_isa(avx)) + vmovsd(addr, x); + else + movsd(addr, x); + } + void uni_vmovsd(const Xbyak::Address &addr, const Xbyak::Ymm &x) { + vmovsd(addr, x); + } + void uni_vmovsd(const Xbyak::Xmm &x, const Xbyak::Address &addr) { + if (is_valid_isa(avx)) + vmovsd(x, addr); + else + movsd(x, addr); + } + void uni_vmovsd(const Xbyak::Ymm &x, const Xbyak::Address &addr) { + vmovsd(x, addr); + } + + void uni_vmovlps(const Xbyak::Address &addr, const Xbyak::Xmm &x) { + if (is_valid_isa(avx)) + vmovlps(addr, x); + else + movlps(addr, x); + } + void uni_vmovlps(const Xbyak::Address &addr, const Xbyak::Ymm &x) { + vmovlps(addr, x); + } + void uni_vmovlps(const Xbyak::Xmm &x, const Xbyak::Address &addr) { + if (is_valid_isa(avx)) + vmovlps(x, addr); + else + movlps(x, addr); + } + void uni_vmovlps(const Xbyak::Ymm &x, const Xbyak::Address &addr) { + vmovlps(x, addr); + } + + void uni_vmovdqu(const Xbyak::Address &addr, const Xbyak::Xmm &x) { + if (is_valid_isa(avx)) + vmovdqu(addr, x); + else + movdqu(addr, x); + } + void uni_vmovdqu(const Xbyak::Address &addr, const Xbyak::Ymm &x) { + vmovdqu(addr, x); + } + void uni_vmovdqu(const Xbyak::Address &addr, const Xbyak::Zmm &x) { + vmovdqu32(addr, x); + } + + void uni_vmovdqu(const Xbyak::Xmm &x, const Xbyak::Address &addr) { + if (is_valid_isa(avx)) + vmovdqu(x, addr); + else + movdqu(x, addr); + } + void uni_vmovdqu(const Xbyak::Ymm &x, const Xbyak::Address &addr) { + vmovdqu(x, addr); + } + void uni_vmovdqu(const Xbyak::Zmm &x, const Xbyak::Address &addr) { + vmovdqu32(x, addr); + } + + void uni_vmovdqu16(const Xbyak::Address &addr, const Xbyak::Xmm &x) { + if (is_valid_isa(avx512_core)) + vmovdqu16(addr, x); + else if (is_valid_isa(avx)) + vmovups(addr, x); + else + movups(addr, x); + } + + void uni_vmovdqu16(const Xbyak::Xmm &x, const Xbyak::Address &addr) { + if (is_valid_isa(avx512_core)) + vmovdqu16(x, addr); + else if (is_valid_isa(avx)) + vmovups(x, addr); + else + movups(x, addr); + } + + void uni_vmovups(const Xbyak::Address &addr, const Xbyak::Xmm &x) { + if (is_valid_isa(avx)) + vmovups(addr, x); + else + movups(addr, x); + } + void uni_vmovups(const Xbyak::Address &addr, const Xbyak::Ymm &x) { + vmovups(addr, x); + } + + void uni_vmovups(const Xbyak::Xmm &x, const Xbyak::Operand &op) { + if (is_valid_isa(avx)) + vmovups(x, op); + else + movups(x, op); + } + void uni_vmovups(const Xbyak::Ymm &x, const Xbyak::Operand &op) { + vmovups(x, op); + } + + void uni_vmovups_tail(const Xbyak::Address &addr, const Xbyak::Ymm &mask, + const Xbyak::Ymm &x) { + vmaskmovps(addr, mask, x); + } + void uni_vmovups_tail(const Xbyak::Ymm &x, const Xbyak::Ymm &mask, + const Xbyak::Address &addr) { + vmaskmovps(x, mask, addr); + } + + void uni_vmovups_tail(const Xbyak::Address &addr, const Xbyak::Opmask &mask, + const Xbyak::Zmm &x) { + vmovups(addr | mask, x); + } + void uni_vmovups_tail(const Xbyak::Zmm &x, const Xbyak::Opmask &mask, + const Xbyak::Address &addr) { + vmovups(x | mask | T_z, addr); + } + + void uni_vmovntps(const Xbyak::Address &addr, const Xbyak::Xmm &x) { + if (is_valid_isa(avx)) + vmovntps(addr, x); + else + movntps(addr, x); + } + + void uni_vbroadcastss(const Xbyak::Xmm &x, const Xbyak::Operand &op) { + if (is_valid_isa(avx2) || (is_valid_isa(avx) && op.isMEM())) + vbroadcastss(x, op); + else if (is_valid_isa(avx)) { + vmovss(x, x, op); + vshufps(x, x, x, 0x0); + } else { + movss(x, op); + shufps(x, x, 0x0); + } + } + void uni_vbroadcastss(const Xbyak::Ymm &x, const Xbyak::Operand &op) { + if (op.isMEM() || is_valid_isa(avx2)) { + vbroadcastss(x, op); + } else { + Xbyak::Xmm t(x.getIdx()); + if (!t.isEqualIfNotInherited(op)) movss(t, op); + vinsertf128(x, x, t, 1); + vshufps(x, x, x, 0); + } + } + + void uni_vpbroadcastb(const Xbyak::Ymm &x, const Xbyak::Reg8 &r) { + if (is_valid_isa(avx512_core)) + vpbroadcastb(x, r); // broadcast reg32 directly + else if (is_valid_isa(avx2)) { + const Xbyak::Xmm t(x.getIdx()); + uni_vmovd(t, r.cvt32()); + vpbroadcastb(x, t); + } + assert(is_valid_isa(avx2) && "avx does not support vpbroadcastb"); + } + + void uni_vpbroadcastd(const Xbyak::Xmm &x, const Xbyak::Operand &op) { + if (is_valid_isa(avx2)) + vpbroadcastd(x, op); + else if (is_valid_isa(avx)) { + if (op.isMEM()) + vmovss(x, op.getAddress()); + else + vmovss(x, x, op); + vpshufd(x, x, 0x0); + } else { + movss(x, op); + pshufd(x, x, 0x0); + } + } + void uni_vpbroadcastd(const Xbyak::Ymm &x, const Xbyak::Reg32 &r) { + if (is_valid_isa(avx512_core)) + vpbroadcastd(x, r); // broadcast reg32 directly + else { + const Xbyak::Xmm t(x.getIdx()); + uni_vmovd(t, r); + uni_vpbroadcastd(x, t); + } + } + void uni_vpbroadcastd(const Xbyak::Ymm &x, const Xbyak::Operand &op) { + if (is_valid_isa(avx2)) { + vpbroadcastd(x, op); + } else { + const Xbyak::Xmm t(x.getIdx()); + if (!t.isEqualIfNotInherited(op)) { + if (op.isMEM()) + vmovss(t, op.getAddress()); + else + vmovss(t, t, op); + } + vinsertf128(x, x, t, 1); + vshufps(x, x, x, 0); + } + } + + void uni_vshufps(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op, Xbyak::uint8 imm) { + if (is_valid_isa(avx)) + vshufps(x1, x2, op, imm); + else { + movups(x1, x2); + shufps(x1, op, imm); + } + } + + void uni_vpshufd( + const Xbyak::Xmm &x1, const Xbyak::Operand &op, Xbyak::uint8 imm) { + if (is_valid_isa(avx)) + vpshufd(x1, op, imm); + else { + pshufd(x1, op, imm); + } + } + + void uni_vrcpss(const Xbyak::Xmm &x, const Xbyak::Operand &op) { + if (is_valid_isa(avx)) + vrcpss(x, x, op); + else + rcpss(x, op); + } + void uni_vrcpss(const Xbyak::Ymm &x1, const Xbyak::Xmm &x2) { + Xbyak::Xmm x1_(x1.getIdx()); + Xbyak::Xmm x2_(x2.getIdx()); + vrcpss(x1_, x1_, x2_); + } + void uni_vrcpss(const Xbyak::Ymm &x, const Xbyak::Address &op) { + Xbyak::Xmm x_(x.getIdx()); + vrcpss(x_, x_, op); + } + + void uni_vrcpps(const Xbyak::Xmm &x, const Xbyak::Operand &op) { + if (is_valid_isa(avx)) + vrcpps(x, op); + else + rcpps(x, op); + } + void uni_vrcpps(const Xbyak::Ymm &x, const Xbyak::Operand &op) { + vrcpps(x, op); + } + void uni_vrcpps(const Xbyak::Zmm &x, const Xbyak::Operand &op) { + vrcp14ps(x, op); + } + + void uni_vdivps(const Xbyak::Xmm &x, const Xbyak::Operand &op1, + const Xbyak::Operand &op2) { + if (is_valid_isa(avx)) + vdivps(x, op1, op2); + else { + assert(x.isEqualIfNotInherited(op1)); + divps(x, op2); + } + } + void uni_vdivps(const Xbyak::Ymm &x, const Xbyak::Operand &op1, + const Xbyak::Operand &op2) { + vdivps(x, op1, op2); + } + + void uni_vdivss(const Xbyak::Xmm &x, const Xbyak::Operand &op1, + const Xbyak::Operand &op2) { + if (is_valid_isa(avx)) + vdivss(x, op1, op2); + else { + assert(x.isEqualIfNotInherited(op1)); + divss(x, op2); + } + } + + void uni_vdivps(const Xbyak::Xmm &x, const Xbyak::Operand &op1, + const Xbyak::Operand &op2, const Xbyak::Xmm &buf) { + if (is_valid_isa(avx)) + vdivps(x, op1, op2); + else { + movups(buf, op1); + divps(buf, op2); + if (x.getIdx() != buf.getIdx()) { movups(x, buf); } + } + } + + void uni_vdivps(const Xbyak::Ymm &x, const Xbyak::Operand &op1, + const Xbyak::Operand &op2, const Xbyak::Ymm &buf) { + vdivps(x, op1, op2); + } + + void uni_vaddps(const Xbyak::Xmm &x, const Xbyak::Operand &op1, + const Xbyak::Operand &op2) { + if (is_valid_isa(avx)) + vaddps(x, op1, op2); + else { + assert(x.getIdx() == op1.getIdx()); + addps(x, op2); + } + } + void uni_vaddps(const Xbyak::Ymm &x, const Xbyak::Operand &op1, + const Xbyak::Operand &op2) { + vaddps(x, op1, op2); + } + void uni_vaddss(const Xbyak::Xmm &x, const Xbyak::Operand &op1, + const Xbyak::Operand &op2) { + if (is_valid_isa(avx)) + vaddss(x, op1, op2); + else { + assert(x.isEqualIfNotInherited(op1)); + addss(x, op2); + } + } + void uni_vaddss(const Xbyak::Ymm &x, const Xbyak::Operand &op1, + const Xbyak::Operand &op2) { + vaddss(x, op1, op2); + } + + void uni_vphaddd(const Xbyak::Xmm &x, const Xbyak::Xmm &x2, + const Xbyak::Operand &op) { + if (is_valid_isa(avx)) { + vphaddd(x, x2, op); + } else { + assert(x.isEqualIfNotInherited(op)); + phaddd(x, op); + } + } + + void uni_vhaddps(const Xbyak::Xmm &x, const Xbyak::Xmm &x2, + const Xbyak::Operand &op) { + if (is_valid_isa(avx)) { + vhaddps(x, x2, op); + } else { + assert(x.isEqualIfNotInherited(op)); + haddps(x, op); + } + } + + void uni_vpsignd(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op) { + if (is_valid_isa(avx)) + vpsignd(x1, x2, op); + else { + assert(x1.getIdx() == x2.getIdx()); + psignd(x1, op); + } + } + void uni_vpsignd(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op) { + vpsignd(x1, x2, op); + } + + void uni_vpsubd(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op) { + if (is_valid_isa(avx)) + vpsubd(x1, x2, op); + else { + assert(x1.getIdx() == x2.getIdx()); + psubd(x1, op); + } + } + void uni_vpsubd(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op) { + vpsubd(x1, x2, op); + } + + void uni_vpsubb(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op) { + if (is_valid_isa(avx)) + vpsubb(x1, x2, op); + else { + assert(x1.getIdx() == x2.getIdx()); + psubb(x1, op); + } + } + void uni_vpsubb(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op) { + vpsubb(x1, x2, op); + } + + void uni_vsubss(const Xbyak::Xmm &x, const Xbyak::Operand &op1, + const Xbyak::Operand &op2) { + if (is_valid_isa(avx)) + vsubss(x, op1, op2); + else { + assert(x.isEqualIfNotInherited(op1)); + subss(x, op2); + } + } + void uni_vsubss(const Xbyak::Ymm &x, const Xbyak::Operand &op1, + const Xbyak::Operand &op2) { + vsubss(x, Xbyak::Xmm(op1.getIdx()), Xbyak::Xmm(op2.getIdx())); + } + + void uni_vsubss(const Xbyak::Xmm &x, const Xbyak::Operand &op1, + const Xbyak::Operand &op2, const Xbyak::Xmm &buf) { + if (is_valid_isa(avx)) + vsubss(x, op1, op2); + else { + if (!buf.isEqualIfNotInherited(op1)) { + assert(!buf.isEqualIfNotInherited(op2)); + movss(buf, op1); + } + subss(buf, op2); + if (x.getIdx() != buf.getIdx()) movss(x, buf); + } + } + + void uni_vsubps(const Xbyak::Xmm &x, const Xbyak::Operand &op1, + const Xbyak::Operand &op2) { + if (is_valid_isa(avx)) + vsubps(x, op1, op2); + else { + assert(x.isEqualIfNotInherited(op1)); + subps(x, op2); + } + } + void uni_vsubps(const Xbyak::Ymm &x, const Xbyak::Operand &op1, + const Xbyak::Operand &op2) { + vsubps(x, op1, op2); + } + + void uni_vsubps(const Xbyak::Xmm &x, const Xbyak::Operand &op1, + const Xbyak::Operand &op2, const Xbyak::Xmm &buf) { + if (is_valid_isa(avx)) + vsubps(x, op1, op2); + else { + movups(buf, op1); + subps(buf, op2); + if (x.getIdx() != buf.getIdx()) { movups(x, buf); } + } + } + + void uni_vsubps(const Xbyak::Ymm &x, const Xbyak::Operand &op1, + const Xbyak::Operand &op2, const Xbyak::Ymm &buf) { + vsubps(x, op1, op2); + } + + void uni_vpmulld(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op) { + if (is_valid_isa(avx)) { + vpmulld(x1, x2, op); + } else { + if (x1.getIdx() != x2.getIdx()) movdqa(x1, x2); + pmulld(x1, op); + } + } + void uni_vpmulld(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op) { + vpmulld(x1, x2, op); + } + + void uni_vmulps(const Xbyak::Xmm &x, const Xbyak::Operand &op1, + const Xbyak::Operand &op2) { + if (is_valid_isa(avx)) + vmulps(x, op1, op2); + else { + if (!x.isEqualIfNotInherited(op1)) { + assert(!x.isEqualIfNotInherited(op2)); + movups(x, op1); + } + mulps(x, op2); + } + } + void uni_vmulps(const Xbyak::Xmm &x, const Xbyak::Operand &op1, + const Xbyak::Operand &op2, const Xbyak::Xmm &buf) { + if (is_valid_isa(avx)) + vmulps(x, op1, op2); + else { + if (!buf.isEqualIfNotInherited(op1)) { + assert(!buf.isEqualIfNotInherited(op2)); + movups(buf, op1); + } + mulps(buf, op2); + if (x.getIdx() != buf.getIdx()) movups(x, buf); + } + } + void uni_vmulps(const Xbyak::Ymm &x, const Xbyak::Operand &op1, + const Xbyak::Operand &op2) { + vmulps(x, op1, op2); + } + + void uni_vmulss(const Xbyak::Xmm &x, const Xbyak::Operand &op1, + const Xbyak::Operand &op2) { + if (is_valid_isa(avx)) + vmulss(x, op1, op2); + else { + assert(x.isEqualIfNotInherited(op1)); + mulss(x, op2); + } + } + void uni_vmulss(const Xbyak::Xmm &x, const Xbyak::Operand &op1, + const Xbyak::Operand &op2, const Xbyak::Xmm &buf) { + if (is_valid_isa(avx)) + vmulss(x, op1, op2); + else { + if (!buf.isEqualIfNotInherited(op1)) { + assert(!buf.isEqualIfNotInherited(op2)); + movss(buf, op1); + } + mulss(buf, op2); + if (x.getIdx() != buf.getIdx()) movss(x, buf); + } + } + void uni_vmulss(const Xbyak::Ymm &x, const Xbyak::Operand &op1, + const Xbyak::Address &op2) { + vmulss(x, Xbyak::Xmm(op1.getIdx()), op2); + } + void uni_vmulss(const Xbyak::Ymm &x, const Xbyak::Operand &op1, + const Xbyak::Ymm &op2) { + vmulss(x, Xbyak::Xmm(op1.getIdx()), Xbyak::Xmm(op2.getIdx())); + } + + void uni_vfmadd132ps(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op, const Xbyak::Xmm &buf) { + if (is_valid_isa(avx2)) + vfmadd132ps(x1, x2, op); + else if (is_valid_isa(avx)) { + assert(x1.getIdx() != x2.getIdx()); + vmulps(x1, x1, op); + vaddps(x1, x1, x2); + } else { + assert(buf.getIdx() != x2.getIdx()); + if (x1.getIdx() != buf.getIdx()) movups(buf, x1); + mulps(buf, op); + addps(buf, x2); + if (x1.getIdx() != buf.getIdx()) movups(x1, buf); + } + } + void uni_vfmadd132ps(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op) { + // Note: SSE, AVX: x1 gets overridden by x1*op + // This is incorrect if x1 == x2 + if (!is_valid_isa(avx2)) assert(x1 != x2); + uni_vfmadd132ps(x1, x2, op, x1); + } + + void uni_vfmadd132ps(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op, const Xbyak::Ymm &buf) { + if (is_valid_isa(avx2)) + vfmadd132ps(x1, x2, op); + else { + // AVX is assumed because of YMM + assert(buf.getIdx() != x2.getIdx()); + vmulps(buf, x1, op); + vaddps(x1, buf, x2); + } + } + void uni_vfmadd132ps(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op) { + // Note: AVX: x1 gets overridden by x1*op + // This is incorrect if x1 == x2 + if (!is_valid_isa(avx2)) assert(x1 != x2); + uni_vfmadd132ps(x1, x2, op, x1); + } + + void uni_vfmadd213ps(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op, const Xbyak::Xmm &buf) { + if (is_valid_isa(avx2)) + vfmadd213ps(x1, x2, op); + else if (is_valid_isa(avx)) { + assert(!buf.isEqualIfNotInherited(op)); + vmulps(buf, x1, x2); + vaddps(x1, buf, op); + } else { + assert(!buf.isEqualIfNotInherited(op)); + if (x1.getIdx() != buf.getIdx()) movups(buf, x1); + mulps(buf, x2); + addps(buf, op); + if (x1.getIdx() != buf.getIdx()) movups(x1, buf); + } + } + void uni_vfmadd213ps(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op) { + // Note: SSE, AVX: x1 gets overridden by x1*x2 + // This is incorrect if x1 == op + if (!is_valid_isa(avx2)) assert(!x1.isEqualIfNotInherited(op)); + uni_vfmadd213ps(x1, x2, op, x1); + } + + void uni_vfmadd213ps(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op, const Xbyak::Ymm &buf) { + if (is_valid_isa(avx2)) + vfmadd213ps(x1, x2, op); + else { + // AVX is assumed because of YMM + assert(!buf.isEqualIfNotInherited(op)); + vmulps(buf, x1, x2); + vaddps(x1, buf, op); + } + } + void uni_vfmadd213ps(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op) { + // Note: AVX: x1 gets overridden by x1*x2 + // This is incorrect if x1 == op + if (!is_valid_isa(avx2)) assert(!x1.isEqualIfNotInherited(op)); + uni_vfmadd213ps(x1, x2, op, x1); + } + + void uni_vfmadd213ss(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op, const Xbyak::Xmm &buf) { + if (is_valid_isa(avx2)) + vfmadd213ss(x1, x2, op); + else if (is_valid_isa(avx)) { + assert(!buf.isEqualIfNotInherited(op)); + vmulss(buf, x1, x2); + vaddss(x1, buf, op); + } else { + assert(!buf.isEqualIfNotInherited(op)); + if (x1.getIdx() != buf.getIdx()) movss(buf, x1); + mulss(buf, x2); + addss(x1, op); + if (x1.getIdx() != buf.getIdx()) movss(x1, buf); + } + } + void uni_vfmadd213ss(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op) { + // Note: SSE, AVX: x1 gets overridden by x1*x2 + // This is incorrect if x1 == op + if (!is_valid_isa(avx2)) assert(!x1.isEqualIfNotInherited(op)); + uni_vfmadd213ss(x1, x2, op, x1); + } + + void uni_vfmadd213ss(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op, const Xbyak::Ymm &buf) { + if (is_valid_isa(avx2)) + vfmadd213ss(x1, x2, op); + else { + // AVX is assumed because of YMM + assert(!buf.isEqualIfNotInherited(op)); + vmulss(buf, x1, x2); + vaddss(x1, buf, op); + } + } + void uni_vfmadd213ss(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op) { + // Note: AVX: x1 gets overridden by x1*x2 + // This is incorrect if x1 == op + if (!is_valid_isa(avx2)) assert(!x1.isEqualIfNotInherited(op)); + uni_vfmadd213ss(x1, x2, op, x1); + } + + void uni_vfmadd231ps(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op, const Xbyak::Xmm &buf) { + if (is_valid_isa(avx2)) + vfmadd231ps(x1, x2, op); + else if (is_valid_isa(avx)) { + assert(buf.getIdx() != x1.getIdx()); + vmulps(buf, x2, op); + vaddps(x1, x1, buf); + } else { + assert(buf.getIdx() != x1.getIdx()); + if (x2.getIdx() != buf.getIdx()) movups(buf, x2); + mulps(buf, op); + addps(x1, buf); + } + } + void uni_vfmadd231ps(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op) { + // Note: SSE, AVX: x2 gets overridden by x2*op + // This is incorrect if x1 == x2 + if (!is_valid_isa(avx2)) assert(x1 != x2); + uni_vfmadd231ps(x1, x2, op, x2); + } + + void uni_vfmadd231ps(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op, const Xbyak::Ymm &buf) { + if (is_valid_isa(avx2)) + vfmadd231ps(x1, x2, op); + else { + // AVX is assumed because of YMM + assert(buf.getIdx() != x1.getIdx()); + vmulps(buf, x2, op); + vaddps(x1, x1, buf); + } + } + void uni_vfmadd231ps(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op) { + // Note: AVX: x2 gets overridden by x2*op + // This is incorrect if x1 == x2 + if (!is_valid_isa(avx2)) assert(x1 != x2); + uni_vfmadd231ps(x1, x2, op, x2); + } + + void uni_vfmadd231ss(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op, const Xbyak::Xmm &buf) { + if (is_valid_isa(avx2)) + vfmadd231ss(x1, x2, op); + else if (is_valid_isa(avx)) { + assert(buf.getIdx() != x1.getIdx()); + vmulss(buf, x2, op); + vaddss(x1, x1, buf); + } else { + assert(buf.getIdx() != x1.getIdx()); + if (x2.getIdx() != buf.getIdx()) movss(buf, x2); + mulss(buf, op); + addss(x1, buf); + } + } + void uni_vfmadd231ss(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op) { + // Note: SSE, AVX: x2 gets overridden by x2*op + // This is incorrect if x1 == x2 + if (!is_valid_isa(avx2)) assert(x1 != x2); + uni_vfmadd231ss(x1, x2, op, x2); + } + + void uni_vfmadd231ss(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op, const Xbyak::Ymm &buf) { + if (is_valid_isa(avx2)) + vfmadd231ss(Xbyak::Xmm(x1.getIdx()), Xbyak::Xmm(x2.getIdx()), op); + else { + // AVX is assumed because of YMM + assert(buf.getIdx() != x1.getIdx()); + vmulss(buf, x2, op); + vaddss(x1, x1, buf); + } + } + void uni_vfmadd231ss(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op) { + // Note: AVX: x2 gets overridden by x2*op + // This is incorrect if x1 == x2 + if (!is_valid_isa(avx2)) assert(x1 != x2); + uni_vfmadd231ss(x1, x2, op, x2); + } + + void uni_vfnmadd231ps(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op, const Xbyak::Xmm &buf) { + if (is_valid_isa(avx2)) + vfnmadd231ps(x1, x2, op); + else if (is_valid_isa(avx)) { + assert(buf.getIdx() != x1.getIdx()); + vmulps(buf, x2, op); + vsubps(x1, x1, buf); + } else { + assert(buf.getIdx() != x1.getIdx()); + if (x2.getIdx() != buf.getIdx()) movups(buf, x2); + mulps(buf, op); + subps(x1, buf); + } + } + void uni_vfnmadd231ps(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op) { + // Note: SSE, AVX: x2 gets overridden by x2*op + // This is incorrect if x1 == x2 + if (!is_valid_isa(avx2)) assert(x1 != x2); + uni_vfnmadd231ps(x1, x2, op, x2); + } + + void uni_vfnmadd231ps(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op, const Xbyak::Ymm &buf) { + if (is_valid_isa(avx2)) + vfnmadd231ps(x1, x2, op); + else { + // AVX is assumed because of YMM + assert(buf.getIdx() != x1.getIdx()); + vmulps(buf, x2, op); + vsubps(x1, x1, buf); + } + } + void uni_vfnmadd231ps(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op) { + // Note: AVX: x2 gets overridden by x2*op + // This is incorrect if x1 == x2 + if (!is_valid_isa(avx2)) assert(x1 != x2); + uni_vfnmadd231ps(x1, x2, op, x2); + } + + void uni_vfnmadd231ss(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op, const Xbyak::Xmm &buf) { + if (is_valid_isa(avx2)) + vfnmadd231ss(x1, x2, op); + else if (is_valid_isa(avx)) { + assert(buf.getIdx() != x1.getIdx()); + vmulss(buf, x2, op); + vsubss(x1, x1, buf); + } else { + assert(buf.getIdx() != x1.getIdx()); + if (x2.getIdx() != buf.getIdx()) movss(buf, x2); + mulss(buf, op); + subss(x1, buf); + } + } + void uni_vfnmadd231ss(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op) { + // Note: SSE, AVX: x2 gets overridden by x2*op + // This is incorrect if x1 == x2 + if (!is_valid_isa(avx2)) assert(x1 != x2); + uni_vfnmadd231ss(x1, x2, op, x2); + } + + void uni_vfnmadd231ss(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op, const Xbyak::Ymm &buf) { + if (is_valid_isa(avx2)) + vfnmadd231ss(x1, x2, op); + else { + // AVX is assumed because of YMM + assert(buf.getIdx() != x1.getIdx()); + vmulss(buf, x2, op); + vsubss(x1, x1, buf); + } + } + void uni_vfnmadd231ss(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op) { + // Note: AVX: x2 gets overridden by x2*op + // This is incorrect if x1 == x2 + if (!is_valid_isa(avx2)) assert(x1 != x2); + uni_vfnmadd231ss(x1, x2, op, x2); + } + + void uni_vfmsub213ps(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op, const Xbyak::Xmm &buf) { + if (is_valid_isa(avx2)) + vfmsub213ps(x1, x2, op); + else if (is_valid_isa(avx)) { + assert(!buf.isEqualIfNotInherited(op)); + vmulps(buf, x1, x2); + vsubps(x1, buf, op); + } else { + assert(!buf.isEqualIfNotInherited(op)); + if (buf.getIdx() != x1.getIdx()) movups(buf, x1); + mulps(buf, x2); + subps(buf, op); + if (buf.getIdx() != x1.getIdx()) movups(x1, buf); + } + } + void uni_vfmsub213ps(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op) { + // Note: SSE, AVX: x1 gets overridden by x1*x2 + // This is incorrect if x1 == op + if (!is_valid_isa(avx2)) assert(!x1.isEqualIfNotInherited(op)); + uni_vfmsub213ps(x1, x2, op, x1); + } + + void uni_vfmsub213ps(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op, const Xbyak::Ymm &buf) { + if (is_valid_isa(avx2)) + vfmsub213ps(x1, x2, op); + else { + // AVX is assumed because of YMM + assert(!buf.isEqualIfNotInherited(op)); + vmulps(buf, x1, x2); + vsubps(x1, buf, op); + } + } + void uni_vfmsub213ps(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op) { + // Note: AVX: x1 gets overridden by x1*x2 + // This is incorrect if x1 == op + if (!is_valid_isa(avx2)) assert(!x1.isEqualIfNotInherited(op)); + uni_vfmsub213ps(x1, x2, op, x1); + } + + void uni_vsqrtps(const Xbyak::Xmm &x, const Xbyak::Operand &op) { + if (is_valid_isa(avx)) + vsqrtps(x, op); + else + sqrtps(x, op); + } + void uni_vsqrtps(const Xbyak::Ymm &x, const Xbyak::Operand &op) { + vsqrtps(x, op); + } + + void uni_vpaddd(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op) { + if (is_valid_isa(avx)) + vpaddd(x1, x2, op); + else { + if (x1.getIdx() != x2.getIdx()) movdqa(x1, x2); + paddd(x1, op); + } + } + void uni_vpaddd(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op) { + vpaddd(x1, x2, op); + } + + void uni_vpaddb(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op) { + if (is_valid_isa(avx)) + vpaddb(x1, x2, op); + else { + if (x1.getIdx() != x2.getIdx()) movdqa(x1, x2); + paddb(x1, op); + } + } + void uni_vpaddb(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op) { + vpaddb(x1, x2, op); + } + + void uni_vpmaddwd(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op) { + if (is_valid_isa(avx)) + vpmaddwd(x1, x2, op); + else { + if (x1.getIdx() != x2.getIdx()) movdqa(x1, x2); + pmaddwd(x1, op); + } + } + void uni_vpmaddwd(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op) { + vpmaddwd(x1, x2, op); + } + + void uni_vpmaddubsw(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op) { + if (is_valid_isa(avx)) + vpmaddubsw(x1, x2, op); + else { + if (x1.getIdx() != x2.getIdx()) movdqa(x1, x2); + pmaddubsw(x1, op); + } + } + void uni_vpmaddubsw(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op) { + vpmaddubsw(x1, x2, op); + } + + void uni_vandps(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op) { + if (is_valid_isa(avx)) + vandps(x1, x2, op); + else { + assert(x1.getIdx() == x2.getIdx()); + andps(x1, op); + } + } + void uni_vandps(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op) { + if (!is_valid_isa(avx512_core) || x1.getBit() < 512) + vandps(x1, x2, op); + else + vpandd(x1, x2, op); + } + + void uni_vpandnd(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op) { + if (is_valid_isa(avx512_core) || x1.getBit() == 512) { + assert(IMPLICATION(x1.getBit() == 512, is_valid_isa(avx512_core))); + vpandnd(x1, x2, op); + } else if (is_valid_isa(avx)) { + assert(IMPLICATION(x1.getBit() == 256, is_valid_isa(avx2))); + vpandn(x1, x2, op); + } else { + assert(x1.getIdx() == x2.getIdx()); + pandn(x1, op); + } + } + + void uni_vorps(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op) { + if (is_valid_isa(avx)) + vorps(x1, x2, op); + else { + assert(x1.getIdx() == x2.getIdx()); + orps(x1, op); + } + } + void uni_vorps(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op) { + if (!is_valid_isa(avx512_core) || x1.getBit() < 512) + vorps(x1, x2, op); + else + vpord(x1, x2, op); + } + + void uni_vxorps(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op) { + if (is_valid_isa(avx)) + vxorps(x1, x2, op); + else { + if (x1.getIdx() != x2.getIdx()) { uni_vmovups(x1, x2); } + xorps(x1, op); + } + } + void uni_vxorps(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op) { + if (!is_valid_isa(avx512_core) || x1.getBit() < 512) + vxorps(x1, x2, op); + else + vpxord(x1, x2, op); + } + + void uni_vpslld( + const Xbyak::Xmm &x, const Xbyak::Operand &op, const int imm) { + if (is_valid_isa(avx)) + vpslld(x, op, imm); + else { + assert(x.isEqualIfNotInherited(op)); + pslld(x, imm); + } + } + void uni_vpslld( + const Xbyak::Ymm &x, const Xbyak::Operand &op, const int imm) { + vpslld(x, op, imm); + } + + void uni_vpsrld( + const Xbyak::Xmm &x, const Xbyak::Operand &op, const int imm) { + if (is_valid_isa(avx)) + vpsrld(x, op, imm); + else { + if (!x.isEqualIfNotInherited(op)) uni_vmovups(x, op); + psrld(x, imm); + } + } + void uni_vpsrld( + const Xbyak::Ymm &x, const Xbyak::Operand &op, const int imm) { + vpsrld(x, op, imm); + } + + void uni_vmaxps(const Xbyak::Xmm &x, const Xbyak::Operand &op1, + const Xbyak::Operand &op2) { + if (is_valid_isa(avx)) + vmaxps(x, op1, op2); + else { + if (!x.isEqualIfNotInherited(op1)) movups(x, op1); + maxps(x, op2); + } + } + void uni_vmaxps(const Xbyak::Ymm &x, const Xbyak::Operand &op1, + const Xbyak::Operand &op2) { + vmaxps(x, op1, op2); + } + + void uni_vmaxss(const Xbyak::Xmm &x, const Xbyak::Operand &op1, + const Xbyak::Operand &op2) { + if (is_valid_isa(avx)) + vmaxss(x, op1, op2); + else { + if (!x.isEqualIfNotInherited(op1)) movss(x, op1); + maxss(x, op2); + } + } + + void uni_vminps(const Xbyak::Xmm &x, const Xbyak::Operand &op1, + const Xbyak::Operand &op2) { + if (is_valid_isa(avx)) + vminps(x, op1, op2); + else { + if (!x.isEqualIfNotInherited(op1)) movups(x, op1); + minps(x, op2); + } + } + + void uni_vminps(const Xbyak::Ymm &x, const Xbyak::Operand &op1, + const Xbyak::Operand &op2) { + vminps(x, op1, op2); + } + + void uni_vminss(const Xbyak::Xmm &x, const Xbyak::Operand &op1, + const Xbyak::Operand &op2) { + if (is_valid_isa(avx)) + vminss(x, op1, op2); + else { + if (!x.isEqualIfNotInherited(op1)) movss(x, op1); + minss(x, op2); + } + } + + void uni_vpmovsxbd(const Xbyak::Xmm &x, const Xbyak::Operand &op) { + if (is_valid_isa(avx)) + vpmovsxbd(x, op); + else + pmovsxbd(x, op); + } + + void uni_vpmovsxbd(const Xbyak::Ymm &y, const Xbyak::Operand &op) { + vpmovsxbd(y, op); + } + + void uni_vpmovzxbd(const Xbyak::Xmm &x, const Xbyak::Operand &op) { + if (is_valid_isa(avx)) + vpmovzxbd(x, op); + else + pmovzxbd(x, op); + } + void uni_vpmovzxbd(const Xbyak::Ymm &y, const Xbyak::Operand &op) { + vpmovzxbd(y, op); + } + + void uni_vcmpps(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op, int cmp_predicate) { + if (is_valid_isa(avx)) + vcmpps(x1, x2, op, cmp_predicate); + else { + if (x1.getIdx() != x2.getIdx()) uni_vmovups(x1, x2); + cmpps(x1, op, cmp_predicate); + } + } + void uni_vcmpps(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op, int cmp_predicate) { + vcmpps(x1, x2, op, cmp_predicate); + } + + void uni_vtestps(const Xbyak::Xmm &x1, const Xbyak::Operand &op) { + if (is_valid_isa(avx)) + vtestps(x1, op); + else + ptest(x1, op); + } + + void uni_vtestps(const Xbyak::Ymm &x1, const Xbyak::Operand &op) { + assert(!(x1.isZMM() || op.isZMM())); + vtestps(x1, op); + } + + void uni_vblendvps(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op, const Xbyak::Xmm &msk) { + if (is_valid_isa(avx)) + vblendvps(x1, x2, op, msk); + else { + assert(x1.getIdx() == x2.getIdx()); + assert(msk.getIdx() == 0); + blendvps(x1, op); + } + } + void uni_vblendvps(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op, const Xbyak::Ymm &msk) { + vblendvps(x1, x2, op, msk); + } + + void uni_vblendps(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op, const int imm) { + assert(!x1.isZMM() && !x2.isZMM()); + + if (is_valid_isa(avx)) + vblendps(x1, x2, op, imm); + else { + assert(x1.getIdx() == x2.getIdx()); + blendps(x1, op, imm); + } + } + + void uni_vroundps( + const Xbyak::Xmm &x, const Xbyak::Operand &op, const int imm) { + if (is_valid_isa(avx512_core)) + vrndscaleps(x, op, imm & 0x3); + else if (is_valid_isa(avx)) + vroundps(x, op, imm); + else + roundps(x, op, imm); + } + + void uni_vroundps( + const Xbyak::Ymm &x, const Xbyak::Operand &op, const int imm) { + if (is_valid_isa(avx512_core)) + vrndscaleps(x, op, imm & 0x3); + else + vroundps(x, op, imm); + } + + void uni_vroundps( + const Xbyak::Zmm &x, const Xbyak::Operand &op, const int imm) { + vrndscaleps(x, op, imm & 0x3); + } + + void uni_vcvtps2dq(const Xbyak::Xmm &x, const Xbyak::Operand &op) { + if (is_valid_isa(avx)) + vcvtps2dq(x, op); + else + cvtps2dq(x, op); + } + void uni_vcvtps2dq(const Xbyak::Ymm &x, const Xbyak::Operand &op) { + vcvtps2dq(x, op); + } + + void uni_vcvtdq2ps(const Xbyak::Xmm &x, const Xbyak::Operand &op) { + if (is_valid_isa(avx)) + vcvtdq2ps(x, op); + else + cvtdq2ps(x, op); + } + + void uni_vcvtdq2ps(const Xbyak::Ymm &x, const Xbyak::Operand &op) { + vcvtdq2ps(x, op); + } + + void uni_vcvtph2psx(const Xbyak::Xmm &x, const Xbyak::Operand &op) { + assert(is_valid_isa(avx2)); + if (is_valid_isa(avx512_core_fp16)) + vcvtph2psx(x, op); + else if (is_valid_isa(avx2)) { + assert(IMPLICATION(op.isMEM(), !op.getAddress().isBroadcast())); + vcvtph2ps(x, op); + } + } + + void uni_vcvtps2phx(const Xbyak::Xmm &x, const Xbyak::Address &addr) { + assert(is_valid_isa(avx512_core_fp16)); + vcvtps2phx(x, addr); + } + + void uni_vcvtps2phx(const Xbyak::Address &addr, const Xbyak::Xmm &x) { + assert(is_valid_isa(avx2)); + vcvtps2ph(addr, x, _op_mxcsr); + } + + void uni_vcvtps2phx(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2) { + assert(is_valid_isa(avx2)); + if (is_valid_isa(avx512_core_fp16)) + vcvtps2phx(x1, x2); + else if (is_valid_isa(avx2)) + vcvtps2ph(x1, x2, _op_mxcsr); + } + + void uni_vmovmskps(const Xbyak::Reg &x1, const Xbyak::Xmm &x2) { + movmskps(x1.cvt64(), x2); + } + void uni_vmovmskps(const Xbyak::Reg &x1, const Xbyak::Ymm &x2) { + vmovmskps(x1, x2); + } + + void uni_vmovd(const Xbyak::Reg32 &r, const Xbyak::Xmm &x) { + if (is_valid_isa(avx)) + vmovd(r, x); + else + movd(r, x); + } + void uni_vmovd(const Xbyak::Xmm &x, const Xbyak::Reg32 &r) { + if (is_valid_isa(avx)) + vmovd(x, r); + else + movd(x, r); + } + void uni_vmovd(const Xbyak::Address &addr, const Xbyak::Xmm &x) { + if (is_valid_isa(avx)) + vmovd(addr, x); + else + movd(addr, x); + } + + void uni_vmovd(const Xbyak::Xmm &x, const Xbyak::Address &addr) { + if (is_valid_isa(avx)) + vmovd(x, addr); + else + movd(x, addr); + } + + void uni_vmovq(const Xbyak::Xmm &x, const Xbyak::Reg64 &r) { + if (is_valid_isa(avx)) + vmovq(x, r); + else + movq(x, r); + } + void uni_vmovq(const Xbyak::Reg64 &r, const Xbyak::Xmm &x) { + if (is_valid_isa(avx)) + vmovq(r, x); + else + movq(r, x); + } + void uni_vmovq(const Xbyak::Address &addr, const Xbyak::Xmm &x) { + if (is_valid_isa(avx)) + vmovq(addr, x); + else + movq(addr, x); + } + void uni_vmovq(const Xbyak::Xmm &x, const Xbyak::Address &addr) { + if (is_valid_isa(avx)) + vmovq(x, addr); + else + movq(x, addr); + } + + void uni_vpackssdw(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op) { + if (is_valid_isa(avx)) + vpackssdw(x1, x2, op); + else { + assert(x1.getIdx() == x2.getIdx()); + packssdw(x1, op); + } + } + void uni_vpackssdw(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op) { + vpackssdw(x1, x2, op); + } + + void uni_vpackuswb(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op) { + if (is_valid_isa(avx)) + vpackuswb(x1, x2, op); + else { + assert(x1.getIdx() == x2.getIdx()); + packuswb(x1, op); + } + } + void uni_vpackuswb(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op) { + vpackuswb(x1, x2, op); + } + + void uni_vpacksswb(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op) { + if (is_valid_isa(avx)) + vpacksswb(x1, x2, op); + else { + assert(x1.getIdx() == x2.getIdx()); + packsswb(x1, op); + } + } + void uni_vpacksswb(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op) { + vpacksswb(x1, x2, op); + } + + void uni_vpinsrb(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op, const int imm) { + if (is_valid_isa(avx)) + vpinsrb(x1, x2, op, imm); + else { + assert(x1.getIdx() == x2.getIdx()); + pinsrb(x1, op, imm); + } + } + + void uni_vpinsrb(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op, const int imm) { + vpinsrb(x1, x2, op, imm); + } + + void uni_vpinsrd(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op, const int imm) { + if (is_valid_isa(avx)) + vpinsrd(x1, x2, op, imm); + else { + assert(x1.getIdx() == x2.getIdx()); + pinsrd(x1, op, imm); + } + } + void uni_vpinsrd(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op, const int imm) { + vpinsrd(x1, x2, op, imm); + } + + void uni_vpinsrq(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op, const int imm) { + if (is_valid_isa(avx)) + vpinsrq(x1, x2, op, imm); + else { + assert(x1.getIdx() == x2.getIdx()); + pinsrq(x1, op, imm); + } + } + void uni_vpinsrq(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op, const int imm) { + vpinsrq(x1, x2, op, imm); + } + + void uni_vpinsrw(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op, const int imm) { + if (is_valid_isa(avx)) + vpinsrw(x1, x2, op, imm); + else { + assert(x1.getIdx() == x2.getIdx()); + pinsrw(x1, op, imm); + } + } + void uni_vpinsrw(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op, const int imm) { + vpinsrw(x1, x2, op, imm); + } + + void uni_vpextrb( + const Xbyak::Operand &op, const Xbyak::Xmm &x, const int imm) { + if (is_valid_isa(avx)) + vpextrb(op, x, imm); + else + pextrb(op, x, imm); + } + + void uni_vpextrb( + const Xbyak::Operand &op, const Xbyak::Ymm &x, const int imm) { + vpextrb(op, x, imm); + } + + void uni_vpextrw( + const Xbyak::Operand &op, const Xbyak::Xmm &x, const int imm) { + if (is_valid_isa(avx)) + vpextrw(op, x, imm); + else + pextrw(op, x, imm); + } + void uni_vpextrw( + const Xbyak::Operand &op, const Xbyak::Ymm &x, const int imm) { + vpextrw(op, x, imm); + } + + void uni_vpextrd( + const Xbyak::Operand &op, const Xbyak::Xmm &x, const int imm) { + if (is_valid_isa(avx)) + vpextrd(op, x, imm); + else + pextrd(op, x, imm); + } + void uni_vpextrd( + const Xbyak::Operand &op, const Xbyak::Ymm &x, const int imm) { + vpextrd(op, x, imm); + } + + void uni_vpextrq( + const Xbyak::Operand &op, const Xbyak::Xmm &x, const int imm) { + if (is_valid_isa(avx)) + vpextrq(op, x, imm); + else + pextrq(op, x, imm); + } + void uni_vpextrq( + const Xbyak::Operand &op, const Xbyak::Ymm &x, const int imm) { + vpextrq(op, x, imm); + } + + void uni_vpmaxsd(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op) { + if (is_valid_isa(avx)) + vpmaxsd(x1, x2, op); + else { + if (x1.getIdx() != x2.getIdx()) movdqa(x1, x2); + pmaxsd(x1, op); + } + } + + void uni_vpmaxsd(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op) { + vpmaxsd(x1, x2, op); + } + + void uni_vpmaxsb(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op) { + if (is_valid_isa(avx)) + vpmaxsb(x1, x2, op); + else { + if (x1.getIdx() != x2.getIdx()) movdqa(x1, x2); + pmaxsb(x1, op); + } + } + + void uni_vpmaxsb(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op) { + vpmaxsb(x1, x2, op); + } + + void uni_vpminub(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op) { + if (is_valid_isa(avx)) + vpminub(x1, x2, op); + else { + if (x1.getIdx() != x2.getIdx()) movdqa(x1, x2); + pminub(x1, op); + } + } + + // Note: instructions below are used in custom forks and are put here to + // decrease maintenance burden on user side. + // Once the instruction becomes used in one of oneDNN implementations, + // please, move out of this section. + void uni_vpshufb(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op) { + if (is_valid_isa(avx)) + vpshufb(x1, x2, op); + else { + assert(x1.getIdx() == x2.getIdx()); + pshufb(x1, op); + } + } + void uni_vpshufb(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op) { + vpshufb(x1, x2, op); + } + + void uni_vpand(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op) { + if (is_valid_isa(avx512_core) && x1.getBit() == 512) + vpandd(x1, x2, op); + else if (is_valid_isa(avx)) + vpand(x1, x2, op); + else { + assert(x1.getIdx() == x2.getIdx()); + pand(x1, op); + } + } + + void uni_vpslldq( + const Xbyak::Xmm &x, const Xbyak::Operand &op, const int imm) { + if (is_valid_isa(avx)) + vpslldq(x, op, imm); + else { + assert(x.isEqualIfNotInherited(op)); + pslldq(x, imm); + } + } + void uni_vpslldq( + const Xbyak::Ymm &x, const Xbyak::Operand &op, const int imm) { + vpslldq(x, op, imm); + } + + void uni_vpmovsxwd(const Xbyak::Xmm &x, const Xbyak::Operand &op) { + if (is_valid_isa(avx)) + vpmovsxwd(x, op); + else + pmovsxwd(x, op); + } + void uni_vpmovsxwd(const Xbyak::Ymm &y, const Xbyak::Operand &op) { + vpmovsxwd(y, op); + } + + void uni_vpmovsxdq(const Xbyak::Xmm &x, const Xbyak::Operand &op) { + if (is_valid_isa(avx)) + vpmovsxdq(x, op); + else + pmovsxdq(x, op); + } + void uni_vpmovsxdq(const Xbyak::Ymm &y, const Xbyak::Operand &op) { + vpmovsxdq(y, op); + } + + void uni_vpmovzxwd(const Xbyak::Xmm &x, const Xbyak::Operand &op) { + if (is_valid_isa(avx)) + vpmovzxwd(x, op); + else + pmovzxwd(x, op); + } + void uni_vpmovzxwd(const Xbyak::Ymm &y, const Xbyak::Operand &op) { + vpmovzxwd(y, op); + } + + void uni_vpcmpeqd(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op) { + if (is_valid_isa(avx)) + vpcmpeqd(x1, x2, op); + else { + if (x1.getIdx() != x2.getIdx()) uni_vmovups(x1, x2); + pcmpeqd(x1, op); + } + } + void uni_vpcmpeqd(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op) { + vpcmpeqd(x1, x2, op); + } + + void uni_vpackusdw(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op) { + if (is_valid_isa(avx)) + vpackusdw(x1, x2, op); + else { + assert(x1.getIdx() == x2.getIdx()); + packusdw(x1, op); + } + } + void uni_vpackusdw(const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, + const Xbyak::Operand &op) { + vpackusdw(x1, x2, op); + } + + void uni_vpminsd(const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, + const Xbyak::Operand &op) { + if (is_valid_isa(avx)) + vpminsd(x1, x2, op); + else { + if (x1.getIdx() != x2.getIdx()) movdqa(x1, x2); + pminsd(x1, op); + } + } + + void uni_movshdup(const Xbyak::Xmm &x, const Xbyak::Operand &op) { + if (is_valid_isa(avx)) + vmovshdup(x, op); + else + movshdup(x, op); + } + void uni_movshdup(const Xbyak::Ymm &x, const Xbyak::Operand &op) { + vmovshdup(x, op); + } + + void uni_vmovhlps( + const Xbyak::Xmm &x1, const Xbyak::Xmm &x2, const Xbyak::Xmm &x3) { + if (is_valid_isa(avx)) + vmovhlps(x1, x2, x3); + else { + assert(x1.getIdx() == x2.getIdx()); + movhlps(x1, x3); + } + } + void uni_vmovhlps( + const Xbyak::Ymm &x1, const Xbyak::Ymm &x2, const Xbyak::Ymm &x3) { + vmovhlps(x1, x2, x3); + } + + // End of custom instructions section. + + void mul_by_const( + const Xbyak::Reg &out, const Xbyak::Reg64 &tmp, int value) { + // Generates a shift + add sequence for multiplicating contents of the + // out register by a known JIT-time value. Clobbers the tmp register. + // + // Pros compared to mul/imul: + // - does not require using known registers + // Still, there are probably a lot of cases when mul/imul is faster on + // Intel(R) Core(TM) processors. Not intended for critical path. + + // TODO: detect when overflow is emminent (Roma) + // TODO: detect when using mul/imul is a better option (Roma) + + int p = 0; // the current power of 2 + int old_p = 0; // the last seen power of 2 such that value[old_p] != 0 + + xor_(tmp, tmp); + while (value) { + if (value & 1) { + int shift = p - old_p; + if (shift) { + shl(out, shift); + old_p = p; + } + add(tmp, out); + } + value >>= 1; + p++; + } + mov(out, tmp); + } + + /* + Saturation facility functions. enable to prepare the register + holding the saturation upperbound and apply the saturation on + the floating point register + */ + template + void init_vmm(Vmm vmm, Xbyak::Reg64 reg_tmp, float value) { + Xbyak::Xmm xmm_tmp(vmm.getIdx()); + mov(reg_tmp, float2int(value)); + uni_vmovq(xmm_tmp, reg_tmp); + if (vmm.isYMM() || vmm.isZMM()) + uni_vbroadcastss(vmm, xmm_tmp); + else + uni_vshufps(vmm, xmm_tmp, xmm_tmp, 0); + } + + template + void init_saturate_f32(Vmm vmm_lbound, Vmm vmm_ubound, Xbyak::Reg64 reg_tmp, + data_type_t idt, data_type_t odt, bool force_lbound = false) { + using namespace data_type; + if (!((idt == f32) && utils::one_of(odt, u8, s8, s32))) return; + + assert(IMPLICATION(idt == u8 || force_lbound, + vmm_lbound.getIdx() != vmm_ubound.getIdx())); + + // No need to saturate on lower bound for signed integer types, as + // the conversion to int would return INT_MIN, and then proper + // saturation will happen in store_data. The param force_lbound, will + // force saturate values unconditionally to lbound. + if (odt == u8) + uni_vpxor(vmm_lbound, vmm_lbound, vmm_lbound); + else if (force_lbound) { + const float saturation_lbound = odt == s8 ? INT8_MIN : INT32_MIN; + init_vmm(vmm_lbound, reg_tmp, saturation_lbound); + } + + const float saturation_ubound = types::max_value(odt); + init_vmm(vmm_ubound, reg_tmp, saturation_ubound); + } + + template + void saturate_f32(const Vmm &vmm, const Vmm &vmm_lbound, + const Vmm &vmm_ubound, data_type_t odt, bool force_lbound = false) { + // This function is used to saturate to odt in f32 before converting + // to s32 in order to avoid bad saturation due to cvtps2dq + // behavior (it returns INT_MIN if the f32 is out of the + // s32 range) + using namespace data_type; + if (!utils::one_of(odt, u8, s8, s32)) return; + + // no need to apply lower saturation bound when odt is + // signed, as cvtps2dq will return MIN_INT if the value + // does not fit. The param force_lbound, will force saturate values + // unconditionally to lbound. + if (odt == u8 || force_lbound) { + if (is_valid_isa(avx)) + vmaxps(vmm, vmm, vmm_lbound); + else + maxps(vmm, vmm_lbound); + } + if (is_valid_isa(avx)) + vminps(vmm, vmm, vmm_ubound); + else + minps(vmm, vmm_ubound); + } + + /** + * load_bytes is the utility function to facilitate loading of + * load_size (0 <= load_size <= 32) many contiguous bytes into the Xmm/Ymm + * register from the memory referenced by ptr[reg + offset] address. + * + * Functionally, invocation of load_bytes is equivalent to + * the following loop: + * + * for (int idx = 0; idx < load_size; ++idx) + * vpinsrb(xmm, xmm, ptr[reg + offset + idx], idx); + * + * TODO: Add an option to zero-out unloaded bytes in the Xmm register. + * TODO: Add an option for unsafe_load wherein one could read outside the + * provided memory buffer so as to minimize the total number of read + * memory instructions. + */ + template + void load_bytes( + const Vmm &vmm, const Xbyak::Address &src_addr, int load_size) { + + constexpr bool is_vmm_supported = std::is_same::value + || std::is_same::value; + if (!is_vmm_supported) { + assert("load_bytes() is only supported for xmm and ymm"); + return; + } + + const auto addr = [&](int bytes_offset) { + return ptr[src_addr.getRegExp() + + Xbyak::RegExp(bytes_offset * sizeof(int8_t))]; + }; + + helper_load_bytes(vmm, load_size, addr); + } + + template + void load_bytes(const Vmm &vmm, const Xbyak::Reg64 ®, int64_t offset, + int load_size) { + + constexpr bool is_vmm_supported = std::is_same::value + || std::is_same::value; + if (!is_vmm_supported) { + assert("load_bytes() is only supported for xmm and ymm"); + return; + } + + // Ensure offset is at most 4 bytes to be encoded in the instruction + assert(offset >= INT_MIN && offset <= INT_MAX); + + const auto addr = [&](int bytes_offset) { + return ptr[reg + offset + bytes_offset * sizeof(int8_t)]; + }; + + helper_load_bytes(vmm, load_size, addr); + } + +private: + template + void helper_load_bytes( + const Vmm &vmm, int load_size, const AddrFunc &addr) { + + constexpr bool is_xmm = std::is_same::value; + constexpr bool is_ymm = std::is_same::value; + assert((is_xmm || is_ymm) && "only Xmm or Ymm registers are allowed"); + + MAYBE_UNUSED(is_xmm); + MAYBE_UNUSED(is_ymm); + + // Ensure data fits completely inside the Xmm/Ymm register + assert(load_size >= 0 && load_size <= 32); + + // At most 16 bytes can fit inside the Xmm register + assert(IMPLICATION(load_size > 16, is_ymm)); + + // Ensure that vector register is compatible with the ISA in hand + assert(IMPLICATION(is_ymm, is_valid_isa(avx))); + + assert(is_valid_isa(sse41) + && "routine is not supported for the current isa"); + + auto xmm = Xbyak::Xmm(vmm.getIdx()); + auto ymm = Xbyak::Ymm(vmm.getIdx()); + + if (load_size == 32) { + vmovups(ymm, addr(0)); + return; + } + + int start_bytes = 0; + int bytes_to_load = load_size; + + if (load_size > 16) { + // Prepare to insert to upper bits of ymm + start_bytes = 16; + bytes_to_load -= 16; + } + + if (bytes_to_load >= 8 && bytes_to_load < 16) + uni_vpinsrq(xmm, xmm, addr(start_bytes), 0); + else if (bytes_to_load == 16) + uni_vmovdqu(xmm, addr(start_bytes)); + + switch (bytes_to_load) { + case 0: break; + case 1: uni_vpinsrb(xmm, xmm, addr(start_bytes), 0); break; + case 2: uni_vpinsrw(xmm, xmm, addr(start_bytes), 0); break; + case 3: + uni_vpinsrw(xmm, xmm, addr(start_bytes), 0); + uni_vpinsrb(xmm, xmm, addr(start_bytes + 2), 2); + break; + case 4: uni_vpinsrd(xmm, xmm, addr(start_bytes), 0); break; + case 5: + uni_vpinsrd(xmm, xmm, addr(start_bytes), 0); + uni_vpinsrb(xmm, xmm, addr(start_bytes + 4), 4); + break; + case 6: + uni_vpinsrd(xmm, xmm, addr(start_bytes), 0); + uni_vpinsrw(xmm, xmm, addr(start_bytes + 4), 2); + break; + case 7: + uni_vpinsrd(xmm, xmm, addr(start_bytes), 0); + uni_vpinsrw(xmm, xmm, addr(start_bytes + 4), 2); + uni_vpinsrb(xmm, xmm, addr(start_bytes + 6), 6); + break; + case 8: break; + case 9: uni_vpinsrb(xmm, xmm, addr(start_bytes + 8), 8); break; + case 10: uni_vpinsrw(xmm, xmm, addr(start_bytes + 8), 4); break; + case 11: + uni_vpinsrw(xmm, xmm, addr(start_bytes + 8), 4); + uni_vpinsrb(xmm, xmm, addr(start_bytes + 10), 10); + break; + case 12: uni_vpinsrd(xmm, xmm, addr(start_bytes + 8), 2); break; + case 13: + uni_vpinsrd(xmm, xmm, addr(start_bytes + 8), 2); + uni_vpinsrb(xmm, xmm, addr(start_bytes + 12), 12); + break; + case 14: + uni_vpinsrd(xmm, xmm, addr(start_bytes + 8), 2); + uni_vpinsrw(xmm, xmm, addr(start_bytes + 12), 6); + break; + case 15: + uni_vpinsrd(xmm, xmm, addr(start_bytes + 8), 2); + uni_vpinsrw(xmm, xmm, addr(start_bytes + 12), 6); + uni_vpinsrb(xmm, xmm, addr(start_bytes + 14), 14); + break; + case 16: break; + default: assert(!"improper load size"); + } + + if (load_size > 16) { + vinsertf128(ymm, ymm, xmm, 1); // insert to upper bits of ymm + vinsertf128(ymm, ymm, addr(0), 0); // insert to lower bits of ymm + } + } + + /** + * store_bytes is the utility function to facilitate storing of + * store_size (0 <= store_size <= 32) many contiguous bytes from the Xmm/Ymm + * register into the memory referenced by ptr[reg + offset] address. + * + * Additionally, when store_size > 16, the input Ymm register will not be + * preserved due to the usage of vextracti128 instruction. + * + * Functionally, invocation of store_bytes is equivalent + * to the following loop: + * + * for (int idx = 0; idx < store_size; ++idx) + * vpextrb(ptr[reg + offset + idx], xmm, idx); + * + * TODO: Add an option for unsafe_store wherein one could store extra dwords + * past the provided memory buffer so as to minimize the total number of + * write memory instructions. + */ +public: + template + void store_bytes( + const Vmm &vmm, const Xbyak::Address &dst_addr, int store_size) { + const auto addr = [&](int bytes_offset) { + return ptr[dst_addr.getRegExp() + + Xbyak::RegExp(bytes_offset * sizeof(int8_t))]; + }; + store_bytes(vmm, store_size, addr); + } + + template + void store_bytes(const Vmm &vmm, const Xbyak::Reg64 ®, int64_t offset, + int store_size) { + + // Ensure offset is at most 4 bytes to be encoded in the instruction + assert(offset >= INT_MIN && offset <= INT_MAX); + + const auto addr = [&](int bytes_offset) { + return ptr[reg + offset + bytes_offset * sizeof(int8_t)]; + }; + + store_bytes(vmm, store_size, addr); + } + +private: + template + void store_bytes(const Vmm &vmm, int store_size, const AddrFunc &addr) { + + constexpr bool is_xmm = std::is_same::value; + constexpr bool is_ymm = std::is_same::value; + static_assert( + is_xmm || is_ymm, "only Xmm or Ymm registers are allowed"); + + MAYBE_UNUSED(is_xmm); + MAYBE_UNUSED(is_ymm); + + // Ensure data fits completely inside the Xmm/Ymm register + assert(store_size >= 0 && store_size <= 32); + + // At most 16 bytes can fit inside the Xmm register + assert(IMPLICATION(store_size > 16, is_ymm)); + + // Ensure that vector register is compatible with the ISA in hand + assert(IMPLICATION(is_ymm, is_valid_isa(avx))); + + assert(is_valid_isa(sse41) + && "routine is not supported for the current isa"); + + auto xmm = Xbyak::Xmm(vmm.getIdx()); + auto ymm = Xbyak::Ymm(vmm.getIdx()); + + if (store_size == 32) { + vmovups(addr(0), ymm); + return; + } + + int start_bytes = 0; + int bytes_to_store = store_size; + + if (store_size > 16) { + vmovdqu(addr(0), xmm); // load lower bits from ymm + start_bytes = 16; + bytes_to_store -= 16; + vextractf128(xmm, ymm, 1); // load upper bits from ymm into xmm + } + + if (bytes_to_store >= 8 && bytes_to_store < 16) + uni_vpextrq(addr(start_bytes), xmm, 0); + else if (bytes_to_store == 16) + uni_vmovdqu(addr(start_bytes), xmm); + + switch (bytes_to_store) { + case 0: break; + case 1: uni_vpextrb(addr(start_bytes), xmm, 0); break; + case 2: uni_vpextrw(addr(start_bytes), xmm, 0); break; + case 3: + uni_vpextrw(addr(start_bytes), xmm, 0); + uni_vpextrb(addr(start_bytes + 2), xmm, 2); + break; + case 4: uni_vpextrd(addr(start_bytes), xmm, 0); break; + case 5: + uni_vpextrd(addr(start_bytes), xmm, 0); + uni_vpextrb(addr(start_bytes + 4), xmm, 4); + break; + case 6: + uni_vpextrd(addr(start_bytes), xmm, 0); + uni_vpextrw(addr(start_bytes + 4), xmm, 2); + break; + case 7: + uni_vpextrd(addr(start_bytes), xmm, 0); + uni_vpextrw(addr(start_bytes + 4), xmm, 2); + uni_vpextrb(addr(start_bytes + 6), xmm, 6); + break; + case 8: break; + case 9: uni_vpextrb(addr(start_bytes + 8), xmm, 8); break; + case 10: uni_vpextrw(addr(start_bytes + 8), xmm, 4); break; + case 11: + uni_vpextrw(addr(start_bytes + 8), xmm, 4); + uni_vpextrb(addr(start_bytes + 10), xmm, 10); + break; + case 12: uni_vpextrd(addr(start_bytes + 8), xmm, 2); break; + case 13: + uni_vpextrd(addr(start_bytes + 8), xmm, 2); + uni_vpextrb(addr(start_bytes + 12), xmm, 12); + break; + case 14: + uni_vpextrd(addr(start_bytes + 8), xmm, 2); + uni_vpextrw(addr(start_bytes + 12), xmm, 6); + break; + case 15: + uni_vpextrd(addr(start_bytes + 8), xmm, 2); + uni_vpextrw(addr(start_bytes + 12), xmm, 6); + uni_vpextrb(addr(start_bytes + 14), xmm, 14); + break; + case 16: break; + default: assert(!"improper store size"); + } + } + +public: + /** + * load_bytes_to_dword_extension is the utility function to facilitate + * loading of load_size (0 <= load_size <= 16) many contiguous bytes in + * the Xmm register from the memory referenced by ptr[reg + offset] + * address and then do signed/zero extension of those to double words. + * + * Functionally, invocation of load_bytes_to_dword_extension is equivalent + * to the following: + * + * for (int idx = 0; idx < load_size; ++idx) + * vpinsrb(xmm, xmm, ptr[reg + offset + idx], idx); + * if (is_signed) vpmovsxbd(vmm, vmm); else vpmovzxbd(vmm, vmm); + * + * Valid values for the load_size variable are: + * [0..4] for XMM version of the function + * [0..8] for YMM version of the function. + * TODO: Implement this routine for every ISA. + */ + template + void load_bytes_to_dword_extension(const Vmm &vmm, const Xbyak::Reg64 ®, + int64_t offset, bool is_signed, int load_size) { + // Ensure offset is at most 4 bytes to be encoded in the instruction + assert(offset >= INT_MIN && offset <= INT_MAX); + load_bytes_to_dword_extension( + vmm, ptr[reg + offset], is_signed, load_size); + } + + template + void load_bytes_to_dword_extension(const Vmm &vmm, + const Xbyak::Address &src_addr, bool is_signed, int load_size) { + + constexpr bool is_vmm_supported = std::is_same::value + || std::is_same::value; + if (!is_vmm_supported) { + assert("load_bytes_to_dword_extension() is only supported for xmm " + "and ymm"); + return; + } + + constexpr bool is_xmm = std::is_same::value; + constexpr bool is_ymm = std::is_same::value; + MAYBE_UNUSED(is_xmm); + MAYBE_UNUSED(is_ymm); + + // Ensure extended double words fit inside Ymm (32 * load_size <= 256) + assert(load_size >= 0 && load_size <= 8); + // For Xmm register, load capacity is halved (32 * load_size <= 128) + assert(IMPLICATION(is_xmm, load_size <= 4)); + + // Ensure that vector register is compatible with the ISA in hand + assert(IMPLICATION(is_ymm, is_valid_isa(avx))); + + assert(is_valid_isa(sse41) + && "routine is not supported for the current isa"); + + // For load_size == 8/4, do load/extension in one go + if (load_size == 8) { + const auto ymm = Xbyak::Ymm(vmm.getIdx()); + if (is_signed) + vpmovsxbd(ymm, src_addr); + else + vpmovzxbd(ymm, src_addr); + } else if (load_size == 4) { + const auto xmm = Xbyak::Xmm(vmm.getIdx()); + if (is_signed) + uni_vpmovsxbd(xmm, src_addr); + else + uni_vpmovzxbd(xmm, src_addr); + } else { + load_bytes(vmm, src_addr, load_size); + if (is_signed) + uni_vpmovsxbd(vmm, vmm); + else + uni_vpmovzxbd(vmm, vmm); + } + } + + /* A utility function to store data of type type_out from vmm register + * into the memory. Moreover store_size many chunks are written to the + * memory beginning with ptr[reg + offset] address. + * + * Note: Content of Vmm register is not guaranteed to be preserved after the + * invocation of this routine. + * + * TODO: Support for every possible data type. + */ + template + void store_data(data_type_t type_out, const Vmm &vmm, + const Xbyak::Reg64 ®, int64_t offset, int store_size) { + constexpr bool is_vmm_supported = std::is_same::value + || std::is_same::value; + using supported_vmm_t = typename utils::conditional::type; + + if (!is_vmm_supported) { + assert("store_data() not supported"); + return; + } + helper_store_data(type_out, supported_vmm_t(vmm.getIdx()), reg, offset, + store_size); + } + +private: + template + void helper_store_data(data_type_t type_out, const Vmm &vmm, + const Xbyak::Reg64 ®, int64_t offset, int store_size) { + + assert(is_valid_isa(sse41) + && "routine is not supported for the current isa"); + constexpr bool is_ymm = std::is_same::value; + + // Owing to lack of cross lane operations in non avx2 compatible isa + // this functionality remains unimplemented for int8 data type + const bool is_int8_dt + = utils::one_of(type_out, data_type::s8, data_type::u8); + assert(IMPLICATION(is_ymm && is_int8_dt, is_valid_isa(avx2))); + + // Ensure that vector register is compatible with the ISA in hand + assert(IMPLICATION(is_ymm, is_valid_isa(avx))); + + MAYBE_UNUSED(is_ymm); + MAYBE_UNUSED(is_int8_dt); + + auto ymm = Xbyak::Ymm(vmm.getIdx()); + auto xmm = Xbyak::Xmm(vmm.getIdx()); + + switch (type_out) { + case data_type::f32: + case data_type::s32: + store_bytes(vmm, reg, offset, sizeof(int32_t) * store_size); + break; + case data_type::u8: + case data_type::s8: + uni_vpackssdw(vmm, vmm, vmm); + // For each y_i of size 64 bits, following cross lane + // operation on ymm yields + // [y_3 y_2 y_1 y_0] |--> [0 0 y_2 y_0] + if (is_ymm) vpermq(ymm, ymm, 0x08); + if (type_out == data_type::s8) + uni_vpacksswb(vmm, vmm, vmm); + else + uni_vpackuswb(vmm, vmm, vmm); + store_bytes(vmm, reg, offset, store_size); + break; + case data_type::bf16: + vcvtneps2bf16(xmm, vmm, + is_valid_isa(avx512_core_bf16) ? Xbyak::EvexEncoding + : Xbyak::VexEncoding); + store_bytes(vmm, reg, offset, sizeof(bfloat16_t) * store_size); + break; + case data_type::f16: + vcvtps2ph(xmm, vmm, _op_mxcsr); + store_bytes(vmm, reg, offset, sizeof(float16_t) * store_size); + break; + default: assert(!"unsupported destination data type"); + } + } + +public: + /* A utility function to load data of type type_in to vmm register + * from the memory. Moreover load_size many chunks are read from the memory + * beginning with ptr[reg + offset] address. + * + * TODO: Support for every possible data type. + */ + template + void load_data(data_type_t type_in, const Vmm &vmm, const Xbyak::Reg64 ®, + int64_t offset, int load_size) { + // Ensure offset is at most 4 bytes to be encoded in the instruction + assert(offset >= INT_MIN && offset <= INT_MAX); + load_data(type_in, vmm, ptr[reg + offset], load_size); + } + + template + void load_data(data_type_t type_in, const Vmm &vmm, + const Xbyak::Address &src_addr, int load_size) { + + assert(is_valid_isa(sse41) + && "routine is not supported for the current isa"); + + switch (type_in) { + case data_type::f32: + case data_type::s32: + load_bytes(vmm, src_addr, sizeof(int32_t) * load_size); + break; + case data_type::s8: + case data_type::u8: + load_bytes_to_dword_extension( + vmm, src_addr, type_in == data_type::s8, load_size); + break; + case data_type::bf16: + load_bytes(vmm, src_addr, sizeof(bfloat16_t) * load_size); + uni_vpmovzxwd(vmm, vmm); + uni_vpslld(vmm, vmm, 16); + break; + case data_type::f16: + load_bytes(vmm, src_addr, sizeof(float16_t) * load_size); + vcvtph2ps(vmm, + typename vreg_traits::Vmm_lower_t(vmm.getIdx())); + break; + default: assert(!"unsupported source data type"); + } + } + + /* A utility function to process f32 tail (load, store or other) depending + * on tail size, stored in Reg64. Tail size must be value from 0 to 3/7 + * (Xmm/Ymm). Tail process functions require integer as argument to specify + * behavior for each tail size. + * + * Only supported for Xmm and Ymm. + */ + template + void runtime_tail_process(const Xbyak::Reg64 ®_tail, + const Xbyak::Reg64 ®_tmp, + const std::function &tail_process, + const data_type_t data_type = data_type::f32) { + const auto simd_w + = vreg_traits::vlen / types::data_type_size(data_type); + + Xbyak::Label label_tbl, label_tbl_end; + std::vector l_case(simd_w); + + mov(reg_tmp, label_tbl); + const Xbyak::Address label_address + = ptr[reg_tmp + reg_tail * sizeof(void *)]; + jmp(label_address, T_NEAR); + + // create jump table + L(label_tbl); + for (size_t i = 0; i < simd_w; i++) + putL(l_case[i]); + + // cases for each tail size - from 0 to 3/7 + L(l_case[0]); + jmp(label_tbl_end, T_NEAR); + for (size_t i = 1; i < simd_w; i++) { + L(l_case[i]); + tail_process(i); + jmp(label_tbl_end, T_NEAR); + } + L(label_tbl_end); + } + + DNNL_DISALLOW_COPY_AND_ASSIGN(jit_generator); + +public: + /* All uni_ instructions -- apart from uni_vzeroupper() -- will comply with + * the max_cpu_isa argument */ + jit_generator(const char *name, void *code_ptr = nullptr, + size_t code_size = MAX_CODE_SIZE, bool use_autogrow = true, + cpu_isa_t max_cpu_isa = get_max_cpu_isa()) + : Xbyak::MmapAllocator(name) + , Xbyak::CodeGenerator(code_size, + (code_ptr == nullptr && use_autogrow) ? Xbyak::AutoGrow + : code_ptr, + /*allocator=*/this) + , max_cpu_isa_(max_cpu_isa) {} + + virtual ~jit_generator() {} + + virtual const char *name() const = 0; + virtual const char *source_file() const = 0; + + void register_jit_code(const Xbyak::uint8 *code, size_t code_size) const { + jit_utils::register_jit_code(code, code_size, name(), source_file()); + } + + const Xbyak::uint8 *jit_ker() const { return jit_ker_; } + + template + void operator()(kernel_args_t... args) const { + using jit_kernel_func_t = void (*)(const kernel_args_t... args); + auto *fptr = (jit_kernel_func_t)jit_ker_; + (*fptr)(std::forward(args)...); + } + + virtual status_t create_kernel() { + int err_code = Xbyak::GetError(); + if (err_code == Xbyak::ERR_CANT_ALLOC) return status::out_of_memory; + if (err_code != Xbyak::ERR_NONE) return status::runtime_error; + generate(); + jit_ker_ = getCode(); + return (jit_ker_) ? status::success : status::runtime_error; + } + +private: + const cpu_isa_t max_cpu_isa_; + const Xbyak::uint8 *getCode() { + this->ready(); + if (!is_initialized()) return nullptr; + const Xbyak::uint8 *code = CodeGenerator::getCode(); + register_jit_code(code, getSize()); + return code; + } + + inline bool is_valid_isa(cpu_isa_t isa) { + return is_subset(isa, max_cpu_isa_) && mayiuse(isa); + } + + static inline bool is_initialized() { + return Xbyak::GetError() == Xbyak::ERR_NONE; + } + +protected: + virtual void generate() = 0; + const Xbyak::uint8 *jit_ker_ = nullptr; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_primitive_conf.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_primitive_conf.hpp new file mode 100644 index 0000000000000000000000000000000000000000..bbc1f6db1a07ce5d005ec0bb1c64dedda2d47c9c --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_primitive_conf.hpp @@ -0,0 +1,907 @@ +/******************************************************************************* +* Copyright 2016-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_PRIMITIVE_CONF_HPP +#define CPU_X64_JIT_PRIMITIVE_CONF_HPP + +#include +#include + +#include "common/primitive_attr.hpp" +#include "cpu/x64/brgemm/brgemm_types.hpp" +#include "cpu/x64/cpu_isa_traits.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +/* convolution */ +enum conv_loop_order_t { + loop_cgn, + loop_gnc, + loop_ngc, + loop_gncw, + loop_cwgn, + loop_ngcw, + loop_nhwcg, + loop_nwcg +}; +enum conv_1x1_loop_order_t { + loop_rbl, + loop_rlb, + loop_lbr, + loop_lrb, + loop_blr, + loop_brl +}; + +enum conv_kernel_kind_t { embd_bcast, expl_bcast }; +enum conv_harness_t { + harness_2d_reduction, + harness_3d_reduction, + harness_mb_reduction, + harness_compute_full_spatial, + harness_nxc +}; + +enum { + FLAG_MB_FIRST = 1 << 0, + FLAG_MB_LAST = 1 << 1, + FLAG_OC_FIRST = 1 << 2, + FLAG_OC_LAST = 1 << 3, + FLAG_IC_FIRST = 1 << 4, + FLAG_IC_LAST = 1 << 5, + FLAG_SP_FIRST = 1 << 6, + FLAG_SP_LAST = 1 << 7, + FLAG_REDUCE_FIRST = 1 << 8, + FLAG_REDUCE_LAST = 1 << 9, + FLAG_ZERO_FILTER = 1 << 0, /* Controls whether the inner kernel skips + loading weights-data from memory; this + needs to happen on the first Group/16 + iteration. */ + FLAG_ZERO_BIAS = 1 << 1, /* Controls whether the inner kernel skip + loading bias data from memory */ + FLAG_COMPUTE_BIAS = 1 << 2, /* Controls bias computation during execution + pass */ +}; + +enum class jit_memory_tag_kind_t { ncsp, nspc, blocked, undef }; + +struct jit_conv_conf_t { + prop_kind_t prop_kind; + bool has_vnni; + conv_loop_order_t loop_order; + conv_harness_t harness; + + int simd_w; + int ndims; + int mb; + int ngroups, ic, oc, oc_without_padding, ic_without_padding; + int id, ih, iw, od, oh, ow; + int f_pad, l_pad, t_pad; + int back_pad, r_pad, b_pad; + int kd, kh, kw; + int stride_d, stride_h, stride_w; + int dilate_d, dilate_h, dilate_w; + format_tag_t src_tag, wei_tag, dst_tag; // temporary workaround + bool with_bias; + bool with_sum; + bool with_eltwise; + bool with_binary; + + data_type_t sum_dt; + + bool with_binary_per_oc_bcast; + bool with_binary_no_bcast; + + bool is_fused_conv; + int dw_conv_buffer_oc; + + post_ops_t::entry_t::eltwise_t eltwise; + post_ops_t post_ops; + bool is_fast_postops; // maybe skip injector for sum and/or relu + + int nthr, nthr_mb, nthr_g, nthr_oc_b, nthr_ic_b, nthr_oh; + + int idp, ihp, iwp, ohp, owp, icp; + int nb_ic, ic_block; + int nb_oc, oc_block; + int nb_iw, iw_block; + int nb_ow, ow_block; + int nb_oc_blocking; /* used in jit kernels for nb_oc work blocking taking + into account vector registers distribution */ + int nb_oc_blocking_thr_chunk; /* used for distribution of nb_oc work + within threads */ + int nb_ic_blocking, nb_ic_blocking_max; // blocking of nb_ic work + int nb_ic_L2; + int h_blocking; + int nb_oc_L2; + int ic_tail, oc_tail, ch_tail; + int ur_h, ur_w; + int ur_w_tail, ur_w_blocks; + int ur_ic, ur_kw; + bool is_1stconv; + int nonblk_group_off; + /* fma avx512_core */ + conv_kernel_kind_t kernel_kind; + + int tr_iw, tr_ih; + int tr_kw, tr_kh; + int tr_src_num_guard_elems; + + // Transpose buffer management + size_t tr_src_buf_size, tr_src_buf_count; + size_t tr_diff_dst_buf_size, tr_diff_dst_buf_count; + int nthr_mb_work; + + int typesize_in; + int typesize_out; + int typesize_bia; + int typesize_acc; + /* avx512_u8s8u8 */ + int ic_nb1, ic_nb2; + int oc_nb1; + int ur_ow_max, ur_ow, ur_ow_tail; + int ur_ow_nsteps; + data_type_t bia_dt; + /* bf16 data-type for output */ + data_type_t dst_dt; + data_type_t src_dt; + /* bf16 weights update */ + data_type_t wei_dt; + data_type_t ddst_dt; + data_type_t dsrc_dt; + data_type_t dwei_dt; + bool expl_bcast; + bool large_spatial, large_w_filter; + int is_ic_scale, is_oc_scale; + int max_regs_ur; // maximum accumulation registers + // dw conv + int nb_ch, ch_block, nb_ch_blocking; + bool is_depthwise, is_fast_depthwise, is_resrc_depthwise; + int aligned_threads; + // large spatial + int ih_blk_size, oh_blk_size; + // s8s8 convolution + bool signed_input; + bool need_saturation; + float wei_adj_scale; + // zero-point compensation + bool src_zero_point; + int zp_pbuff_size; + bool dst_zero_point; + bool zp_src_is_common; // common, otherwise (TODO) per-channel + bool req_zero_point_buffer; // used for calculating padding compensation + bool zp_pbuff_outer_compute; // indicates if zp_bbuff is computed in + + bool dst_scale; + + // a separate parallel region + int ow_pad, oh_pad, od_pad; // output elements with padding & filter overlap + + //output elements requiring zero-point padding compensation + int f_pad_output, back_pad_output; + int t_pad_output, b_pad_output; + int l_pad_output, r_pad_output; + // The number of output blocks corresponding to {l_pad, no_pad, r_pad} + int l_pad_blk, no_pad_w_blk, r_pad_blk; + + bool od_mid, oh_mid, ow_mid; // indicate if there is overlap between the + //width and height padded regions + + size_t h_blk_limits[5]; // pre-computed limits for output height block + + bool uses_permw_transposition; + bool transpose_src; + bool transpose_dst; + int ic_block_step; + + cpu_isa_t isa; + // bf16 bwdw conv + int tr_ow; + bool is_hw_transp; // spatial dim height-width transposed + int spatial_blk_size; // Height/depth block size inside the driver + bool global_transpose; // diff_dst & src tensors are transposed in one go + bool use_nt_stores_ddst; // Use non temporal stores in diff_dst transform + + // Needed for Intel(R) Advanced Matrix Extensions (Intel(R) AMX) kernels + bool is_nspc; // activations in nwc, nhwc, or ndhwc layout + bool is_relo; // reduced lowering optimization + int nreduce; // used with is_relo + bool is_pbuffer_strided; // does pbuffer have strided sectors? + int n_stride_sets; // number of stride sectors (or sets) in pbuffer + int kw_step; // usually stride_w, unless !is_pbuffer_strided + int kw_per_tile; // mostly for 1st convs + // The suffix _int refers to the block sizes of the src and diff_dst tiles, + // as opposed to the vector registers. This distinction is needed due to + // support for blocked layout (ie nChw16c) with bf16 data type. + int ic_block_int, ic_block_int_np, oc_block_int; + int nb_ic_int, nb_oc_int; + int nb_ih_blocking, nb_oh_blocking; + + int full_tile_width; + int max_tiles; + int tile_width; + int tile_tail; + int oh_per_tile; + int iw_blocks, ow_blocks; + + int per_one_pstore; + + size_t inp_buffer_size; + size_t wei_buffer_size; + size_t wsp_buffer_size; + + int nb_os; + int nb_os_blocking; + int nb_os2_blocking; + int os_tail; + int os_blocked; + int max_width; + + bool transform_to_vnni; +}; + +// calculates filter size taking into account dilation +inline int calculate_extended_filter_size(int filter_size, int dilation) { + return (filter_size - 1) * (dilation + 1) + 1; +} + +inline int calculate_end_padding(int start_padding, int dst_size, int src_size, + int spatial_stride, int dilated_filter_size) { + return (dst_size - 1) * spatial_stride + dilated_filter_size + - (src_size + start_padding); +} + +inline status_t init_tag(format_tag_t &tag, const memory_desc_wrapper &mdw, + const format_tag_t &tag_value) { + if (mdw.format_kind() == format_kind::any) return status::unimplemented; + + tag = mdw.matches_one_of_tag(tag_value); + return tag == tag_value ? status::success : status::unimplemented; +} + +struct jit_conv_call_s { + const void *src; /* hack, non-const for backward_data */ + const void *dst; /* hack, non-const for forward */ + const void *filt; /* hack, non-const for backward_weights */ + const void *bias; /* hack, non-const for backward_bias */ + const void *src_prf; + const void *dst_prf; + const void *filt_prf; + const void *bias_prf; + const void *scales; + const void *acc_s32; + const void *compensation; + const int32_t *zp_compensation; + const int32_t *src_zero_point; + const int32_t *zero_point_pbuff; + const int32_t *dst_zero_point; + const void *tile_cfg; + const void *tile_cfg_tail; + const void *dst_scale; + + // ptr to table of void * elements that are pointers to + // post_op binary src1 tensors + const void *post_ops_binary_rhs_arg_vec; + const void *dst_orig; // pointer to dst memory (no offset) + + size_t kd_offset; + size_t kd_offset_prf; + size_t kh_offset; + size_t kh_offset_prf; + size_t os_index_begin; + size_t os_index_begin_prf; + size_t os_index_end; + size_t os_index_end_prf; + size_t kd_padding; + size_t kd_padding_prf; + size_t kh_padding; + size_t kh_padding_prf; + size_t iwb; + size_t iwb_prf; + size_t owb; + size_t owb_prf; + size_t ohb; + size_t kw_padding; + size_t channel; + size_t channel_prf; + size_t ic_blocks; + size_t oc_blocks; + size_t ur_w; + size_t ur_str_w; + size_t ch_blocks; + size_t ch_blocks_prf; + size_t reduce_work; + size_t reduce_work_prf; + size_t load_work; + size_t load_work_prf; + size_t l_overflow; + size_t r_overflow; + size_t t_overflow; + size_t b_overflow; + size_t f_overflow; + size_t back_overflow; + size_t last_h; + size_t tail; + size_t current_iw; + size_t is_osb; + int flags; + int flags_prf; + int oc_flag; + size_t last_ic_block; + size_t last_oc_block; +}; + +struct jit_deconv_call_s { + const void *src; /* hack, non-const for backward_data */ + const void *dst; /* hack, non-const for forward */ + const void *filt; /* hack, non-const for backward_weights */ + const void *bias; /* hack, non-const for backward_bias */ + const void *scales; + const void *dst_scale; + const void *compensation; + const int32_t *zp_src_pad_str_compensation; + const int32_t *zp_compensation; + const int32_t *src_zero_point; + const int32_t *dst_zero_point; + + /* + * ptr to table of void * elements that are pointers to post_op binary + * src1 tensors + */ + const void *post_ops_binary_rhs_arg_vec; + const void *dst_orig; /* pointer to dst memory (no offset) */ + size_t t_overflow; + size_t b_overflow; + size_t f_overflow; + size_t back_overflow; + size_t kh_padding; + size_t kd_padding; + size_t oc_blocks; +}; + +struct jit_dw_conv_call_s { + const void *input; + const void *output; + const void *filter; + const void *bias; + size_t kh_count; + size_t oh_count; + size_t oh_index; + size_t filter_pad_off; + unsigned char + exec_flags; /* Flags passed by driver execution to inner kernel */ +}; + +struct jit_1x1_conv_conf_t { + prop_kind_t prop_kind; + bool has_vnni; + + int ndims; + int mb; + int ngroups, ic, oc, oc_without_padding, ic_without_padding; + int id, ih, iw, od, oh, ow; + int f_pad, t_pad, l_pad; + int kd, kh, kw; + int stride_d, stride_h, stride_w; + format_tag_t src_tag, wei_tag, dst_tag; // temporary workaround + bool with_bias; + bool with_sum; + bool with_eltwise; + bool with_binary; + bool with_dw_conv; + + post_ops_t post_ops; + + dim_t is, os; + int ic_block, oc_block; + + int ur, ur_tail; + + dim_t reduce_dim; + int reduce_block, nb_reduce, nb_reduce_blocking, nb_reduce_blocking_max; + int load_dim, load_block, nb_load, nb_load_blocking, nb_load_blocking_max, + nb_load_chunk; + dim_t bcast_dim; + int bcast_block, nb_bcast, nb_bcast_blocking, nb_bcast_blocking_max; + + int reduce_loop_unroll; + dim_t reduce_loop_bcast_step; + int reduce_loop_load_step; + int load_loop_load_step, load_loop_iter_step; + int bcast_loop_output_step, bcast_loop_output_substep; + int bcast_loop_bcast_step, bcast_loop_bcast_substep; + int load_grp_count; + conv_1x1_loop_order_t loop_order; + bool use_vmovntps; + /* avx512 core */ + bool expl_bcast; + + int typesize_in; + int typesize_out; + int typesize_bia; + int typesize_acc; + + bool transpose_src; + int nthr, nthr_mb, nthr_g, nthr_oc_b, nthr_ic_b; + int is_oc_scale; + data_type_t bia_dt; + data_type_t dst_dt; + data_type_t sum_dt; + bool signed_input; + float wei_adj_scale; + // zero-point compensation + bool src_zero_point; + bool dst_zero_point; + bool zp_src_is_common; // common, otherwise (TODO) per-channel + + bool dst_scale; + + cpu_isa_t isa; + bool uses_permw_transposition; +}; + +struct jit_1x1_conv_call_s { + const void *bcast_data; + const void *load_data; + const void *output_data; + const void *bias_data; // used in forward and backward_weights only + const void *acc_s32; + const void *scales; + const void *compensation; + const void *store_buffer; + const int32_t *zp_compensation; + const int32_t *src_zero_point; + const int32_t *dst_zero_point; + const void *dst_scale; + + // ptr to table of void * elements that are pointers to + // post_op binary src1 tensors + const void *post_ops_binary_rhs_arg_vec; + const void *dst_orig; // pointer to dst memory (no offset) + + size_t load_dim; + size_t bcast_dim; + size_t reduce_dim; + + size_t output_stride; // used in backward_weights only + + size_t first_last_flag; +}; + +struct jit_pool_conf_t { + int ndims; + int mb, c, c_without_padding; + int id, ih, iw, od, oh, ow; + int stride_d, stride_h, stride_w; + int kd, kh, kw; + int f_pad, t_pad, l_pad; + alg_kind_t alg; + bool is_training; + bool pad_w_is_null; + bool is_backward; + bool simple_alg; + bool is_c_padded; + data_type_t ind_dt; + + int c_block, c_tail, nb_c; + int ur_bc, ur_bc_tail; + int ur_c, ur_c_tail; + int ur; + size_t tail[4]; + bool safe_c_tail; + data_type_t src_dt; + data_type_t dst_dt; + + int dt_size; + bool is_bf16; + bool is_f16; + jit_memory_tag_kind_t tag_kind; + bool is_plain() const { + return (tag_kind == jit_memory_tag_kind_t::ncsp + || tag_kind == jit_memory_tag_kind_t::nspc); + } + + cpu_isa_t isa; + post_ops_t post_ops; + bool with_postops; + bool with_eltwise; + bool with_binary; + int nthr; + memory_desc_t tmp_md; +}; + +struct jit_pool_call_s { + const void *src; + const void *dst; + const void *indices; + const void *src_prf; + const void *dst_prf; + const void *indices_prf; + const void *post_ops_binary_rhs_arg_vec; + const void *dst_orig; + const void *dst_po_helper; + size_t zero_ih; + size_t zero_id; + const void *zero_ptr; + size_t kd_padding; + size_t kh_padding; + size_t kh_padding_shift; + size_t kd_padding_shift; + size_t kw_padding; + const void *init_value; + float ker_area_h; + size_t ur_bc; // contains number of channel blocks to processing + size_t b_c; // contains number of channel blocks already processed +}; + +struct jit_resampling_conf_t { + unsigned ndims = 0; + + unsigned c = 0; + unsigned id = 0, ih = 0, iw = 0; + unsigned od = 0, oh = 0, ow = 0; + + unsigned stride_d = 0; + unsigned stride_h = 0; + unsigned stride_w = 0; + unsigned inner_stride = 0; + + // The linear algorithm is an approximation of the point + // value based on the limit values. For one dimension, + // the approximation is based on the line, for two + // dimensions it will be a rectangle, and for three + // dimensions it will be a cuboid. Therefore, + // the possible variants for the number of corners are 2, 4, 8. + unsigned number_of_corners = 0; + + bool is_data_size_bigger_than_L3 = false; + bool is_saturation_needed = false; + data_type_t src_data_type = data_type::undef; + data_type_t dst_data_type = data_type::undef; + size_t src_dt_size = 0; + size_t dst_dt_size = 0; + size_t output_data_size = 0; + size_t el_size_of_indices = 0; + + bool is_blocked_8_format = false; + format_tag_t src_tag = format_tag::undef; + jit_memory_tag_kind_t tag_kind = jit_memory_tag_kind_t::undef; + alg_kind_t alg = alg_kind::undef; + + cpu_isa_t isa = isa_undef; + + post_ops_t post_ops = post_ops_t(); + bool with_postops = false; + bool with_eltwise = false; + bool with_binary = false; + bool with_sum = false; + std::queue sum_scales; +}; + +struct jit_resampling_call_s { + size_t batch_of_sp_points_to_process = 0; + + const void *src = nullptr; + const void *dst = nullptr; + const void *indices = nullptr; + const void *weights = nullptr; + const void *post_ops_binary_rhs_arg_vec = nullptr; + const void *dst_orig = nullptr; + + size_t c_offset = 0; + + size_t src_offset_top = 0; + size_t src_offset_bottom = 0; + size_t src_offset_front = 0; + size_t src_offset_back = 0; + + float weight_top = 0.0f; + float weight_bottom = 0.0f; + float weight_front = 0.0f; + float weight_back = 0.0f; +}; + +struct jit_brdgmm_conv_conf_t { + + int nthr; + int mb, ngroups, ic, oc; + int ih, iw, oh, ow; + int l_pad, r_pad, t_pad, b_pad; + int kh, kw; + int stride_h, stride_w; + int nb_ch, ch_block, chb_tail; + int nb_ch_blocking; + int ow_block, ow_tail, nb_ow; + // idx of jit kernel when mutiple jit kernels are used in a primitive. + int chb_tail_idx, ow_tail_idx, nb_ch_blocking_idx; + int adjusted_batch_size; + + bool with_bias; + bool with_post_ops; + bool with_scale; + bool is_oc_scale; + + data_type_t src_dt; + data_type_t wei_dt; + data_type_t bia_dt; + data_type_t dst_dt; + + brgemm_batch_kind_t batch_kind; + + size_t src_dsz; + size_t wei_dsz; + size_t bia_dsz; + size_t dst_dsz; + + cpu_isa_t isa; +}; + +enum conv_brgemm_loop_order_t { + loop_ndhwgc, + loop_ngcdhw, +}; + +enum conv_brgemm_exec_type_t { + exec_undefined = 0, + exec_base, + exec_trans, + exec_vpad, +}; + +struct jit_brgemm_conv_conf_t { + cpu_isa_t isa; + prop_kind_t prop_kind; + conv_brgemm_loop_order_t loop_order; + conv_harness_t harness; + int simd_w, acc_simd_w, amx_w, amx_h; + int ndims; + int mb; + int ngroups, ic, oc, oc_without_padding, ic_without_padding; + + int od_block, oh_block, nb_od, + nb_oh; // blocking - included in parallelization + int id_block, ih_block, nb_id, nb_ih; + dim_t inp_buffer_size, inp_buffer_mask_size; + conv_brgemm_exec_type_t exec_type; + + int id, ih, iw, od, oh, ow, os, is, idp, ihp, iwp, icp, odp, ohp, owp, ocp; + int f_pad, l_pad, t_pad; + int back_pad, r_pad, b_pad; + int l_ovf, r_ovf, t_ovf, b_ovf, f_ovf, back_ovf; + int kd, kh, kw; + int ext_kd, ext_kh, ext_kw; + int kd_block, kh_block, kw_block, kd_block_pad, kh_block_pad, kw_block_pad; + int stride_d, stride_h, stride_w; + int dilate_d, dilate_h, dilate_w; + format_tag_t src_tag, wei_tag, dst_tag; // temporary workaround + bool with_bias; + bool with_sum; + bool with_eltwise; + bool with_binary; + + bool is_fused_conv; + bool is_is_blocking; + bool is_os_blocking; + bool is_rtus; + bool ununroll_bd_loop {false}; + int nb_ic, ic_block; + int nb_tr_ic, tr_ic_block, tr_ic_tail; + int nb_oc, oc_block; + int nb_iw, iw_block, iw_tail; + int nb_ow, ow_block, ow_tail; + int nb_is, is_block; + int nb_os, os_block; + int nb_oc_blocking; + int nb_ic_blocking; + int nb_is_blocking; + int nb_os_blocking; + + data_type_t src_dt; + data_type_t dst_dt; + data_type_t wei_dt; + data_type_t acc_dt; + data_type_t bia_dt; + size_t src_dsz; + size_t wei_dsz; + size_t dst_dsz; + size_t acc_dsz; + size_t bia_dsz; + + bool use_buffer; + dim_t buffer_size; + dim_t ker_ranges_size; + dim_t comp_a_buffer_size; + dim_t s8s8_comp_buffer_size; + + bool with_scales; + int is_ic_scale, is_oc_scale; + + int LDA, LDB, LDC, LDD; + int M, N, K, M_tail, N_tail, K_tail; + // M for brgemm kernel. For use_store_mask it is usually greater than M (M_tail). Otherwise it is equal to M (M_tail) + int brgM, brgM_tail; + int gemm_batch_size, adjusted_batch_size; + brgemm_batch_kind_t brg_type; + // strides for brg_type == brgemm_strd + dim_t brg_stride_a, brg_stride_b; + int nthr; + + int max_batch; + int max_vpad; + int amx_buf_size_per_thread; + + bool wei_plain; + bool is_ic_padded, is_oc_padded; + int kw_sets, kh_sets; + bool copy_block_only; + bool amx_tile_load_xx; + int use_M_mask; + int oskip, iskip; + bool brgemm_bd_loop_innermost; + + bool use_uker; + bool var_bs {false}; + bool use_interleave_stores; + brgemm_kernel_prefetching_t hint_prefetching; + bool is_1x1; + bool s8s8_compensation_required; + bool src_zero_point; + bool dst_zero_point; + bool req_brg_comp_pad; + bool req_cal_comp_pad; + bool is_bf32; + bool comp_with_vpads; + + int nthr_mb, nthr_g, nthr_oc_b, nthr_ic_b, nthr_oh; + bool transform_to_vnni; + bool has_int8_vnni; + float scale_adjust_factor; + int ic_tail, oc_tail; + size_t tr_src_block_size, tr_src_buf_size, tr_src_buf_count; + size_t tr_diff_dst_block_size, tr_diff_dst_buf_size, tr_diff_dst_buf_count; + int tr_src_num_guard_elems; + bool global_transpose; // diff_dst & src tensors are transposed in one go + int nthr_mb_work; + int tr_iw, tr_ow; + int spatial_blk_size; // Height/depth block size inside the driver + int typesize_in; + int typesize_out; + bool tr_ocb_chunk = false; + bool tr_icb_chunk = false; +}; + +struct jit_shuffle_conf_t { + unsigned ndims = 0; + + unsigned mb = 0, c = 0, d = 0, h = 0, w = 0, sp = 0; + + unsigned stride_mb = 0; + unsigned blk_size = 0; + unsigned group_size = 0; + unsigned axis = 0; + unsigned axis_size = 0; + unsigned simd_tail = 0; + unsigned simd_w = 0; + + jit_memory_tag_kind_t tag_kind = jit_memory_tag_kind_t::undef; + data_type_t data_type = data_type::undef; + size_t dt_size = 0; + unsigned el_size_of_indices = 0; + dim_t c_split_size = 0; + dim_t sp_split_size = 0; + + cpu_isa_t isa = isa_undef; +}; + +struct jit_shuffle_call_s { + const void *src = nullptr; + void *dst = nullptr; + const void *input_off_ptr = nullptr; + + dim_t cb_loop_size + = 0; // number of loop iterations over corresponding C batches + bool is_padded_block = false; +}; + +enum class binary_op_t : unsigned { none, c_blocked, n_spatial_c, n_c_spatial }; + +enum class binary_bcast_t : unsigned { + none, // tensor operation + scalar, + per_batch, + per_c, + per_w +}; + +struct jit_binary_conf_t { + binary_op_t op_type = binary_op_t::none; + binary_bcast_t bcast_type = binary_bcast_t::none; + bool do_scale_src0 = false; + bool do_scale_src1 = false; + bool do_sum = false; + bool with_eltwise = false; + bool with_binary = false; + bool with_postops = false; + float sum_scale = 0.f; + bool use_stride_src1 = false; + bool broadcast_src1_value = false; + bool use_stride_rhs_postops = false; + bool postops_per_oc_broadcast_exists = false; + bool is_i8 = false; + bool is_bf16 = false; + bool is_f16 = false; + bool is_src_different_layouts = false; + dim_t outer_dims = 1; + int src1_stride = 1; + int not_bcasted_sp_dims = 0; + cpu_isa_t isa = isa_undef; + + data_type_t src0_type = data_type::undef; + data_type_t src1_type = data_type::undef; + data_type_t dst_type = data_type::undef; +}; + +struct jit_binary_call_s { + // keep all sizes at 8 bytes -- jit code expects this + const void *src0, *src1, *dst, *indices; + const float *scales_src0, *scales_src1; + size_t spat_offt_count; + const void *post_ops_binary_rhs_arg_vec; + size_t src1_stride_range; + const void *dst_orig; +}; + +struct jit_reduction_conf_t { + data_type_t src_type = data_type::undef; + data_type_t dst_type = data_type::undef; + data_type_t acc_type = data_type::undef; + + std::size_t src_dt_size = 0; + std::size_t dst_dt_size = 0; + std::size_t acc_dt_size = 0; + + alg_kind_t alg = alg_kind::undef; + cpu_isa_t isa = isa_undef; + + dim_t idle_size = 0; + dim_t reduce_size = 0; + + bool is_saturation_needed = false; + + post_ops_t post_ops = post_ops_t(); + bool with_postops = false; + bool with_eltwise = false; + bool with_binary = false; + bool with_sum = false; + std::queue sum_scales; +}; + +struct jit_reduction_call_s { + const void *src = nullptr; + void *dst = nullptr; + const void *post_ops_binary_rhs_arg_vec = nullptr; + const void *dst_orig = nullptr; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_sse41_1x1_conv_kernel_f32.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_sse41_1x1_conv_kernel_f32.hpp new file mode 100644 index 0000000000000000000000000000000000000000..6bb4fc45c34cb14588506cd04cd04300d0202130 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_sse41_1x1_conv_kernel_f32.hpp @@ -0,0 +1,98 @@ +/******************************************************************************* +* Copyright 2017-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_SSE41_1X1_CONV_KERNEL_F32_HPP +#define CPU_X64_JIT_SSE41_1X1_CONV_KERNEL_F32_HPP + +#include "common/c_types_map.hpp" +#include "common/memory.hpp" + +#include "cpu/x64/injectors/jit_uni_postops_injector.hpp" +#include "cpu/x64/jit_generator.hpp" +#include "cpu/x64/jit_primitive_conf.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +struct jit_sse41_1x1_conv_kernel_f32 : public jit_generator { + jit_sse41_1x1_conv_kernel_f32(const jit_1x1_conv_conf_t &ajcp, + const primitive_attr_t &attr, const memory_desc_t &dst_md); + + static status_t init_conf(jit_1x1_conv_conf_t &jcp, + const convolution_desc_t &cd, const memory_desc_wrapper &src_d, + const memory_desc_wrapper &weights_d, + const memory_desc_wrapper &dst_d, const primitive_attr_t &attr, + int nthreads); + + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_sse41_1x1_conv_kernel_f32) + + jit_1x1_conv_conf_t jcp; + const primitive_attr_t &attr_; + +private: + static constexpr auto simd_w_ = cpu_isa_traits::vlen / sizeof(float); + using reg64_t = const Xbyak::Reg64; + using xmm_t = const Xbyak::Xmm; + + reg64_t reg_bcast_data = rax; + reg64_t reg_load_data = rsi; + reg64_t reg_output_data = rbx; + reg64_t aux_reg_bcast_data = rdx; + reg64_t aux1_reg_bcast_data = abi_not_param1; + reg64_t aux_reg_load_data = abi_param1; + reg64_t aux_reg_output_data = rbp; + reg64_t reg_load_loop_work = r9; + reg64_t reg_bcast_loop_work = r10; + reg64_t reg_reduce_loop_work = r11; + reg64_t load_loop_iter = r13; + reg64_t imm_addr64 = load_loop_iter; + reg64_t bcast_loop_iter = r14; + reg64_t reduce_loop_iter = r15; + reg64_t reg_reduce_pos_flag = r8; + reg64_t reg_output_stride = r12; + reg64_t reg_bias_data = r12; + reg64_t reg_diff_bias_data = bcast_loop_iter; + + constexpr static int reg64_size_ = sizeof(int64_t); + constexpr static int reg_diff_bias_data_stack_offt = 0; + constexpr static int reg_abi_param1_backup = 1 * reg64_size_; + constexpr static int reg_dw_binary_output_off = 2 * reg64_size_; + constexpr static int stack_space_needed = 3 * reg64_size_; + + xmm_t reg_bcast = xmm_t(15); + + std::unique_ptr> + postops_injector_; + + void generate_bcast_loop(int load_loop_blk); + void generate_reduce_loop(int load_loop_blk, int ur); + void generate_diff_bias_loop(int load_loop_blk); + + void generate() override; + + void apply_postops(const int load_loop_blk, const int ur); + size_t get_fwd_output_ptr_l_off( + int i, int j, int n, bool ignore_dw_conv) const; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_sse41_1x1_convolution.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_sse41_1x1_convolution.hpp new file mode 100644 index 0000000000000000000000000000000000000000..1c16320947e966a5be3d0ac67bdfd412ddaac948 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_sse41_1x1_convolution.hpp @@ -0,0 +1,291 @@ +/******************************************************************************* +* Copyright 2017-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_SSE41_1X1_CONVOLUTION_HPP +#define CPU_X64_JIT_SSE41_1X1_CONVOLUTION_HPP + +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/memory_tracking.hpp" +#include "common/primitive.hpp" +#include "common/primitive_hashing.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_convolution_pd.hpp" +#include "cpu/dw_convolution_utils.hpp" +#include "cpu/platform.hpp" + +#include "cpu/x64/jit_sse41_1x1_conv_kernel_f32.hpp" +#include "cpu/x64/jit_uni_1x1_conv_utils.hpp" +#include "cpu/x64/jit_uni_dw_convolution.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +struct jit_sse41_1x1_convolution_fwd_t : public primitive_t { + struct pd_t : public cpu_convolution_fwd_pd_t { + using dw_conv_pd_type = jit_sse41_dw_convolution_fwd_t::pd_t; + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const typename pd_t::base_class *hint_fwd_pd) + : cpu_convolution_fwd_pd_t(adesc, attr, hint_fwd_pd), jcp_() {} + + pd_t(const pd_t &other) : cpu_convolution_fwd_pd_t(other) { + if (copy(other) != status::success) is_initialized_ = false; + } + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit_1x1:", sse41, ""), + jit_sse41_1x1_convolution_fwd_t); + + status_t init(engine_t *engine) { + using namespace data_type; + bool ok = is_fwd() + && set_default_alg_kind(alg_kind::convolution_direct) + && expect_data_types(f32, f32, f32, f32, f32) + && attr()->has_default_values( + primitive_attr_t::skip_mask_t::post_ops, f32) + && !has_zero_dim_memory() && set_default_formats() + && attr_.set_default_formats(dst_md(0)) == status::success; + if (!ok) return status::unimplemented; + + CHECK(jit_sse41_1x1_conv_kernel_f32::init_conf(jcp_, *desc(), + *src_md(), *weights_md(), *dst_md(), *attr(), + dnnl_get_max_threads())); + if (jcp_.with_dw_conv) CHECK(depthwise_po_init(engine)); + + return status::success; + } + + const memory_desc_t *dst_1x1_md(int index = 0) const { + return cpu_convolution_fwd_pd_t::dst_md(index); + } + + const memory_desc_t *dst_md( + int index = 0, bool user_input = false) const override { + return jcp_.with_dw_conv + ? dw_conv_pd_->dst_md(index, user_input) + : cpu_convolution_fwd_pd_t::dst_md(index, user_input); + } + + const memory_desc_t *arg_md( + int arg, bool user_input = false) const override { + if (jcp_.with_dw_conv) { + switch (arg) { + case DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_SRC: + return cpu_convolution_fwd_pd_t::dst_md(0, user_input); + case DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_WEIGHTS: + return dw_conv_pd_->weights_md(0); + case DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_BIAS: + return dw_conv_pd_->weights_md(1); + default: break; + } + } + return convolution_fwd_pd_t::arg_md(arg, user_input); + } + + arg_usage_t arg_usage(int arg) const override { + if (arg == (DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_WEIGHTS)) + return arg_usage_t::input; + + if (arg == (DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_BIAS) + && attr_post_op_dw_inputs() > 1) + return arg_usage_t::input; + + return convolution_fwd_pd_t::arg_usage(arg); + } + + jit_1x1_conv_conf_t jcp_; + using dw_pd_t = jit_sse41_dw_convolution_fwd_t::pd_t; + std::unique_ptr dw_conv_pd_; + + protected: + bool set_default_formats() { + using namespace format_tag; + + const memory_desc_wrapper src_d(&src_md_); + const memory_desc_wrapper dst_d(&dst_md_); + + const auto dat_tag_nxc = utils::pick(ndims() - 3, nwc, nhwc, ndhwc); + const auto dat_tag_nCx8c + = utils::pick(ndims() - 3, nCw8c, nChw8c, nCdhw8c); + const auto curr_src_tag + = src_d.matches_one_of_tag(dat_tag_nxc, dat_tag_nCx8c); + const auto curr_dst_tag + = dst_d.matches_one_of_tag(dat_tag_nxc, dat_tag_nCx8c); + const auto is_data_layout_nxc + = IMPLICATION(curr_src_tag != dat_tag_nxc, + src_d.format_kind() == format_kind::any) + && IMPLICATION(curr_dst_tag != dat_tag_nxc, + dst_d.format_kind() == format_kind::any) + && utils::one_of(dat_tag_nxc, curr_src_tag, curr_dst_tag); + auto dat_tag = is_data_layout_nxc ? dat_tag_nxc : dat_tag_nCx8c; + auto wei_tag = with_groups() + ? utils::pick(ndims() - 3, gOIw8i8o, gOIhw8i8o) + : utils::pick(ndims() - 3, OIw8i8o, OIhw8i8o); + + return set_default_formats_common(dat_tag, wei_tag, dat_tag); + } + + status_t copy(const pd_t &other) { + jcp_ = other.jcp_; + if (other.dw_conv_pd_) { + dw_conv_pd_.reset(other.dw_conv_pd_->clone()); + if (!dw_conv_pd_) return status::out_of_memory; + } + return status::success; + } + + status_t depthwise_po_init(engine_t *engine) { + + using namespace memory_tracking; + auto &jcp_1x1 = jcp_; + primitive_attr_t attr_1x1(*attr()); + if (!attr_1x1.is_initialized()) return status::out_of_memory; + const auto &src_md = dst_md_; + const memory_desc_wrapper src_d(src_md); + const auto nthr = dnnl_get_max_threads(); + auto l2_cache = platform::get_per_core_cache_size(2) * nthr; + + // Note: A robust fusion implementation would be to check if both + // 1x1 conv and dw conv that are considered here for fusion are + // optimal independently. This would require creating a new + // primitive_desc through primitive_iterator & check if they match. + // Due to concern that these creations and/or checks could be heavy, + // for 1x1: Check that no better ISA is available. + // for dw: Always fuse with same ISA. + // Caveat: May be a better dw conv exists. + + bool ok = true && (!mayiuse(avx)) + && (attr_1x1.post_ops_.find(primitive_kind::sum) == -1) + // TODO: Below may be further tuned. + && (l2_cache * 2 < src_d.size()) + // load_grp_count check can be redundant due to l2 check + // above. Adding it explicitly as the current driver doesn't + // work if this condition fails. + && (jcp_1x1.load_grp_count < 2); + if (!ok) return status::unimplemented; + + int dw_po_index + = attr_1x1.post_ops_.find(primitive_kind::convolution); + + convolution_desc_t cd_dw; + primitive_attr_t attr_dw; + + CHECK(get_depthwise_conv_desc( + cd_dw, src_md, attr_1x1, attr_dw, dw_po_index)); + + CHECK(safe_ptr_assign( + dw_conv_pd_, new dw_pd_t(&cd_dw, &attr_dw, nullptr))); + CHECK(dw_conv_pd_->init(engine)); + auto &jcp_dw = dw_conv_pd_->jcp_; + + ok = true + && (dnnl_memory_desc_equal(&src_md, dw_conv_pd_->src_md(0))) + && (jcp_1x1.oc_without_padding % jcp_1x1.oc_block == 0) + && IMPLICATION( + jcp_dw.ow_block, jcp_dw.ow_block == jcp_dw.ow); + if (!ok) return status::unimplemented; + + assert(dw_conv_pd_->dst_md(0)->format_kind != format_kind::any); + assert(dw_conv_pd_->weights_md(0)->format_kind != format_kind::any); + assert(IMPLICATION( + dw_conv_pd_->weights_md(1)->data_type != data_type::undef, + dw_conv_pd_->weights_md(1)->format_kind + != format_kind::any)); + + jcp_dw.is_fused_conv = true; + // TODO: Support/experiment arbitary oc_work in dw conv. + // Until then we keep oc_work perfectly divisible. + while (jcp_1x1.nb_load % jcp_1x1.nb_load_blocking != 0) + --jcp_1x1.nb_load_blocking; + jcp_1x1.nb_load_blocking_max = jcp_1x1.nb_load_blocking; + + while (jcp_1x1.nb_load_blocking % jcp_dw.nb_ch_blocking != 0) + --jcp_dw.nb_ch_blocking; + + jcp_dw.dw_conv_buffer_oc + = jcp_1x1.nb_load_blocking * jcp_1x1.oc_block; + + const auto dat_tag_nxc = utils::pick(ndims() - 3, format_tag::nwc, + format_tag::nhwc, format_tag::ndhwc); + const bool is_data_nxc = utils::everyone_is( + dat_tag_nxc, jcp_1x1.src_tag, jcp_1x1.dst_tag); + if (!is_data_nxc) + jcp_1x1.bcast_loop_output_step = jcp_1x1.ur * jcp_1x1.load_block + * jcp_1x1.typesize_out; + + registrar_t scratchpad(scratchpad_registry_); + registrar_t dw_scratchpad(scratchpad, names::prefix_fusion); + + size_t dw_conv_buffer_size_ = (size_t)nthr * jcp_dw.kh * jcp_dw.iw + * jcp_dw.dw_conv_buffer_oc; + assert(dw_conv_buffer_size_); + dw_scratchpad.book(memory_tracking::names::key_fusion_inout_buffer, + dw_conv_buffer_size_, + types::data_type_size(dw_conv_pd_->src_md()->data_type)); + + jit_uni_dw_conv_fwd_kernel::init_scratchpad( + dw_scratchpad, jcp_dw); + + return status::success; + } + }; + + jit_sse41_1x1_convolution_fwd_t(const pd_t *apd) : primitive_t(apd) {} + + typedef typename prec_traits::type data_t; + + status_t init(engine_t *engine) override { + CHECK(safe_ptr_assign(kernel_, + new jit_sse41_1x1_conv_kernel_f32( + pd()->jcp_, *pd()->attr(), *pd()->dst_1x1_md(0)))); + CHECK(kernel_->create_kernel()); + if (pd()->jcp_.with_dw_conv) { + CHECK(safe_ptr_assign(kernel_dw_, + new dw_conv_kernel_t( + pd()->dw_conv_pd_->jcp_, *pd()->dst_md(0)))); + return kernel_dw_->create_kernel(); + } + + return status::success; + } + + status_t execute(const exec_ctx_t &ctx) const override { + execute_forward(ctx); + return status::success; + } + +private: + void execute_forward(const exec_ctx_t &ctx) const; + void execute_forward_thr(const int ithr, const int nthr, const data_t *src, + const data_t *weights, const data_t *bias, const data_t *weights_dw, + const data_t *bias_dw, data_t *dst, + const memory_tracking::grantor_t &scratchpad, + const void *post_ops_binary_rhs_arg_vec, + const void *post_ops_binary_rhs_arg_vec_dw) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + std::unique_ptr kernel_; + using dw_conv_kernel_t = jit_uni_dw_conv_fwd_kernel_f32; + std::unique_ptr kernel_dw_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_sse41_conv_kernel_f32.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_sse41_conv_kernel_f32.hpp new file mode 100644 index 0000000000000000000000000000000000000000..d5db484b65b166c4bcd85cafffd31dce8eeb80f3 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_sse41_conv_kernel_f32.hpp @@ -0,0 +1,127 @@ +/******************************************************************************* +* Copyright 2017-2021 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_SSE41_CONV_KERNEL_F32_HPP +#define CPU_X64_JIT_SSE41_CONV_KERNEL_F32_HPP + +#include "common/c_types_map.hpp" +#include "common/memory.hpp" + +#include "cpu/x64/injectors/jit_uni_postops_injector.hpp" +#include "cpu/x64/jit_generator.hpp" +#include "cpu/x64/jit_primitive_conf.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +struct jit_sse41_conv_fwd_kernel_f32 : public jit_generator { + jit_sse41_conv_fwd_kernel_f32(const jit_conv_conf_t &ajcp, + const primitive_attr_t &attr, const memory_desc_t &dst_md); + + static status_t init_conf(jit_conv_conf_t &jcp, + const convolution_desc_t &cd, const memory_desc_wrapper &src_d, + const memory_desc_wrapper &weights_d, + const memory_desc_wrapper &dst_d, const primitive_attr_t &attr, + int nthreads); + + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_sse41_conv_fwd_kernel_f32) + jit_conv_conf_t jcp; + const primitive_attr_t &attr_; + +private: + static constexpr auto simd_w_ = cpu_isa_traits::vlen / sizeof(float); + using reg64_t = const Xbyak::Reg64; + reg64_t reg_input = rax; + reg64_t aux_reg_input = r8; + reg64_t reg_kernel = rdx; + reg64_t aux_reg_kernel = r9; + reg64_t reg_output = rsi; + reg64_t reg_bias = rbx; + + reg64_t kj = r10; + reg64_t oi_iter = r11; + reg64_t ki_iter = r12; + reg64_t reg_kh = abi_not_param1; + reg64_t simd_iter = r15; + reg64_t reg_oc_blocks = r14; + reg64_t imm_addr64 = reg_oc_blocks; + + Xbyak::Reg32 reg_ci_flag = r13d; + + std::unique_ptr> + postops_injector_; + + inline void oh_step_unroll_kw( + int ur_w, int pad_l, int pad_r, int oc_blocks); + inline void oh_step_nopad(int ur_w, int pad_l, int pad_r, int oc_blocks); + inline void width_blk_step(int ur_w, int pad_l, int pad_r, int oc_blocks); + inline void solve_common(int oc_blocks); + + inline dim_t filter_w_to_input(int ki, int oi = 0, int pad_l = 0) { + return ki * (jcp.dilate_w + 1) + oi * jcp.stride_w - pad_l; + } + + inline dim_t filter_h_to_input(int ki) { + return ki * (jcp.dilate_h + 1) * jcp.iw; + } + + inline dim_t get_input_offset(int i_ic, int i_iw) { + dim_t offset; + if (utils::one_of(jcp.src_tag, format_tag::ncw, format_tag::nchw, + format_tag::ncdhw)) { + offset = i_ic * jcp.ih * jcp.iw + i_iw; + } else if (utils::one_of(jcp.src_tag, format_tag::nwc, format_tag::nhwc, + format_tag::ndhwc)) { + offset = i_iw * jcp.ic * jcp.ngroups + i_ic; + } else { + offset = i_iw * jcp.ic_block + i_ic; + } + return sizeof(float) * offset; + } + + inline dim_t get_output_offset(int i_oc_block, int i_ow) { + dim_t offset; + if (utils::one_of(jcp.dst_tag, format_tag::nwc, format_tag::nhwc, + format_tag::ndhwc)) { + offset = i_ow * jcp.oc * jcp.ngroups + i_oc_block * jcp.oc_block; + } else { + offset = (i_oc_block * jcp.oh * jcp.ow + i_ow) * jcp.oc_block; + } + return sizeof(float) * offset; + } + + inline dim_t get_kernel_offset(int i_oc_block, int ki, int i_ic) { + dim_t block_step_size = jcp.ic_block * jcp.oc_block; + dim_t ic_block_step_size = jcp.kh * jcp.kw * block_step_size; + dim_t oc_block_step_size = jcp.nb_ic * ic_block_step_size; + dim_t offset = i_oc_block * oc_block_step_size + ki * block_step_size + + i_ic * jcp.oc_block; + return sizeof(float) * offset; + } + + void apply_postops(const int oc_blocks, const int ur_w); + + void generate() override; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_sse41_convolution.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_sse41_convolution.hpp new file mode 100644 index 0000000000000000000000000000000000000000..4b8fad41f0b985d8dcd966a791abee8d29546a00 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_sse41_convolution.hpp @@ -0,0 +1,127 @@ +/******************************************************************************* +* Copyright 2017-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_SSE41_CONVOLUTION_HPP +#define CPU_X64_JIT_SSE41_CONVOLUTION_HPP + +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/primitive.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_convolution_pd.hpp" + +#include "cpu/x64/jit_primitive_conf.hpp" +#include "cpu/x64/jit_sse41_conv_kernel_f32.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +struct jit_sse41_convolution_fwd_t : public primitive_t { + struct pd_t : public cpu_convolution_fwd_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const typename pd_t::base_class *hint_fwd_pd) + : cpu_convolution_fwd_pd_t(adesc, attr, hint_fwd_pd), jcp_() {} + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit:", sse41, ""), + jit_sse41_convolution_fwd_t); + + status_t init(engine_t *engine) { + using namespace data_type; + bool ok = is_fwd() + && set_default_alg_kind(alg_kind::convolution_direct) + && expect_data_types(f32, f32, f32, f32, f32) + && attr()->has_default_values( + primitive_attr_t::skip_mask_t::post_ops, f32) + && !has_zero_dim_memory() && set_default_formats() + && attr_.set_default_formats(dst_md(0)) == status::success; + if (!ok) return status::unimplemented; + + CHECK(jit_sse41_conv_fwd_kernel_f32::init_conf(jcp_, *desc(), + *src_md(), *weights_md(), *dst_md(), *attr(), + dnnl_get_max_threads())); + + return status::success; + } + + jit_conv_conf_t jcp_; + + protected: + bool set_default_formats() { + using namespace format_tag; + + const memory_desc_wrapper src_d(&src_md_); + const memory_desc_wrapper dst_d(&dst_md_); + + const auto dat_tag_nxc = utils::pick(ndims() - 3, nwc, nhwc, ndhwc); + const auto dat_tag_ncx = utils::pick(ndims() - 3, ncw, nchw, ncdhw); + const auto dat_tag_nCx8c + = utils::pick(ndims() - 3, nCw8c, nChw8c, nCdhw8c); + const auto curr_src_tag = src_d.matches_one_of_tag( + dat_tag_nxc, dat_tag_ncx, dat_tag_nCx8c); + const auto curr_dst_tag = dst_d.matches_one_of_tag( + dat_tag_nxc, dat_tag_ncx, dat_tag_nCx8c); + const auto is_data_layout_nxc + = IMPLICATION(curr_src_tag != dat_tag_nxc, + src_d.format_kind() == format_kind::any) + && IMPLICATION(curr_dst_tag != dat_tag_nxc, + dst_d.format_kind() == format_kind::any) + && utils::one_of(dat_tag_nxc, curr_src_tag, curr_dst_tag); + const bool flat = IC() == 3; + auto src_tag = is_data_layout_nxc ? dat_tag_nxc + : flat ? dat_tag_ncx + : dat_tag_nCx8c; + auto dst_tag = is_data_layout_nxc ? dat_tag_nxc : dat_tag_nCx8c; + auto wei_tag = with_groups() + ? utils::pick(2 * ndims() - 6 + flat, gOIw8i8o, gOwi8o, + gOIhw8i8o, gOhwi8o, gOIdhw8i8o, gOdhwi8o) + : utils::pick(2 * ndims() - 6 + flat, OIw8i8o, Owi8o, + OIhw8i8o, Ohwi8o, OIdhw8i8o, Odhwi8o); + + return set_default_formats_common(src_tag, wei_tag, dst_tag); + } + }; + + jit_sse41_convolution_fwd_t(const pd_t *apd) : primitive_t(apd) {} + + typedef typename prec_traits::type data_t; + + status_t init(engine_t *engine) override { + CHECK(safe_ptr_assign(kernel_, + new jit_sse41_conv_fwd_kernel_f32( + pd()->jcp_, *pd()->attr(), *pd()->dst_md(0)))); + return kernel_->create_kernel(); + } + + status_t execute(const exec_ctx_t &ctx) const override { + execute_forward(ctx); + return status::success; + } + +private: + void execute_forward(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + std::unique_ptr kernel_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_transpose_utils.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_transpose_utils.hpp new file mode 100644 index 0000000000000000000000000000000000000000..899e4051d99731b9fa49cc8b4dfc92dece83abb3 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_transpose_utils.hpp @@ -0,0 +1,154 @@ +/******************************************************************************* +* Copyright 2017-2022 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_TRANSPOSE_UTILS_HPP +#define CPU_X64_JIT_TRANSPOSE_UTILS_HPP + +#include "cpu/x64/cpu_barrier.hpp" +#include "cpu/x64/jit_primitive_conf.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +struct jit_trans_src_t { + struct ctx_t { + const void *src; + const void *tr_src; + const void *src_prf; + const void *tr_src_prf; + int ch_work; + }; + + virtual void operator()(ctx_t *ctx) = 0; + virtual status_t create_kernel() = 0; + + jit_trans_src_t(const jit_conv_conf_t *conf) : conf_(conf) {} + virtual ~jit_trans_src_t() {} + + const jit_conv_conf_t *conf_; +}; + +struct jit_src_transpose_s { + size_t size; + const void *src; + const void *tr_src; + const void *src_prf; + const void *tr_src_prf; +}; + +struct jit_trans_dst_t { + struct ctx_t { + const void *src; + const void *tr_src; + const void *src_prf; + const void *tr_src_prf; + int ch_work; + }; + + jit_trans_dst_t(const jit_conv_conf_t *conf) : conf_(conf) {} + virtual ~jit_trans_dst_t() {} + + virtual void operator()(ctx_t *ctx) = 0; + virtual status_t create_kernel() = 0; + const jit_conv_conf_t *conf_; +}; + +struct jit_transpose4x16_src_t { + int src_pf0_distance; + int tr_src_pf0_distance; + bool src_pf1; + bool tr_src_pf1; +}; + +struct jit_transpose4x16_src : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_transpose4x16_src) + + jit_transpose4x16_src(const jit_1x1_conv_conf_t *aparams, + jit_transpose4x16_src_t *tparams_) + : jit_generator(jit_name()), params(aparams), tparams(tparams_) {} + + const jit_1x1_conv_conf_t *params; + const jit_transpose4x16_src_t *tparams; + + static const int transpose_size = 4; + +private: + static const int typesize = sizeof(float); + + int src_stride = 0, tr_src_stride = 0; + + Xbyak::Reg64 imm_addr64 = rbx; + + Xbyak::Opmask kF0 = k1; + Xbyak::Opmask kCC = k2; + Xbyak::Opmask k33 = k3; + Xbyak::Opmask kFFFF = k4; + + Xbyak::Zmm vidx01 = zmm31; + Xbyak::Zmm vidx10 = zmm30; + Xbyak::Zmm vidx1 = zmm29; + Xbyak::Zmm vidxP = zmm28; + + Xbyak::Reg64 reg_src = r8; + Xbyak::Reg64 reg_tr_src = r9; + Xbyak::Reg64 reg_src_prf = r10; + Xbyak::Reg64 reg_tr_src_prf = r11; + Xbyak::Reg64 reg_loop = r12; + Xbyak::Reg64 reg_tr_src_tmp = r13; + Xbyak::Reg32 regw_tmp = r14d; + + void transpose_block(int ur, int nrows); + void transpose(int nrows); + void generate() override; +}; + +struct jit_diff_wei_trans_to_vnni_t : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_diff_wei_trans_to_vnni_t) + + jit_diff_wei_trans_to_vnni_t(const data_type_t dt, const int &kd, + const int &kh, const int &kw, const int &ic_block, + const int &oc_block) + : jit_generator(jit_name()) + , out_dt_(dt) + , kd_(kd) + , kh_(kh) + , kw_(kw) + , ic_block_(ic_block) + , oc_block_(oc_block) {} + + ~jit_diff_wei_trans_to_vnni_t() {} + + status_t create_kernel() override { return jit_generator::create_kernel(); } + + const data_type_t out_dt_; + const int kd_, kh_, kw_; + const int ic_block_, oc_block_; + +private: + void generate() override; +}; + +jit_trans_src_t *create_trans_src(const jit_conv_conf_t *conf); +jit_trans_dst_t *create_trans_dst(const jit_conv_conf_t *conf); + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_1x1_conv_utils.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_1x1_conv_utils.hpp new file mode 100644 index 0000000000000000000000000000000000000000..4432ac44f4238a7ad3b1c3aeb2e32f569f708d8f --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_1x1_conv_utils.hpp @@ -0,0 +1,714 @@ +/******************************************************************************* +* Copyright 2017-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_UNI_1X1_CONV_UTILS_HPP +#define CPU_X64_JIT_UNI_1X1_CONV_UTILS_HPP + +#include "common/convolution_pd.hpp" +#include "common/dnnl_thread.hpp" +#include "common/memory_tracking.hpp" +#include "common/nstl.hpp" +#include "common/primitive_desc_iterator.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/x64/jit_generator.hpp" +#include "cpu/x64/jit_primitive_conf.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +struct reduce_to_unit_stride_t { + convolution_desc_t conv_d_; + bool reduce_src_; + size_t space_per_thread_; +}; + +/* 1x1-kernel does not support non-unit strides so far, so the idea is: + * - for fwd or bwd_weights: to copy src to a scratch memory (with strides + * equal to 1) and then call the kernel + * - for bwd_data: reduce the problem to the one with unit stride by + * performing computations in a scratch memory (with strides equal to 1) + * and then copy the result to diff_src */ +template +inline void rtus_prepare(conv_pd_t *self, const convolution_desc_t *&conv_d, + const memory_desc_t *&src_d, const memory_desc_t *dst_d, + const memory_desc_t *weights_d) { + const int ndims = src_d->ndims; + + const bool with_groups + = memory_desc_wrapper(weights_d).ndims() == ndims + 1; + + bool rtus_applicable = utils::one_of(ndims, 3, 4) + && IMPLICATION(with_groups, weights_d->dims[0] == 1); + if (ndims == 3) + rtus_applicable = rtus_applicable && conv_d->strides[0] != 1 + && conv_d->src_desc.data_type != data_type::s32; + else + rtus_applicable = rtus_applicable + && (conv_d->strides[0] != 1 || conv_d->strides[1] != 1); + for (int d = 2; d < ndims; ++d) { + /* TODO: relax these conditions (by improving reducer) */ + rtus_applicable = rtus_applicable && conv_d->padding[0][d - 2] == 0 + && dst_d->dims[d] * conv_d->strides[d - 2] == src_d->dims[d]; + } + if (!rtus_applicable) return; + + const auto dat_tag = ndims == 3 + ? memory_desc_wrapper(src_d).matches_one_of_tag( + format_tag::nCw8c, format_tag::nCw16c, format_tag::nwc) + : memory_desc_wrapper(src_d).matches_one_of_tag( + format_tag::nChw8c, format_tag::nChw16c, format_tag::nhwc); + if (dat_tag == format_tag::undef) return; + + const bool is_nspc + = utils::one_of(dat_tag, format_tag::nwc, format_tag::nhwc); + if (is_nspc && !mayiuse(sse41)) return; + + // rtus is applicable, configure it. + self->rtus_.reduce_src_ = true; + conv_d = &(self->rtus_.conv_d_ = *conv_d); + self->rtus_.conv_d_.strides[0] = 1; + if (ndims == 4) self->rtus_.conv_d_.strides[1] = 1; + utils::array_set(self->rtus_.conv_d_.padding[0], 0, 2); + if (ndims == 4) utils::array_set(self->rtus_.conv_d_.padding[1], 0, 2); + const int ic = src_d->dims[1]; + if (self->desc()->prop_kind == prop_kind::backward_data) { + data_type_t data_type = self->rtus_.conv_d_.diff_src_desc.data_type; + src_d = &(self->rtus_.conv_d_.diff_src_desc = *dst_d); + self->rtus_.conv_d_.diff_src_desc.dims[1] = ic; + self->rtus_.conv_d_.diff_src_desc.data_type = data_type; + memory_desc_wrapper::compute_blocking( + self->rtus_.conv_d_.diff_src_desc, dat_tag); + } else { + data_type_t data_type = self->rtus_.conv_d_.src_desc.data_type; + src_d = &(self->rtus_.conv_d_.src_desc = *dst_d); + self->rtus_.conv_d_.src_desc.dims[1] = ic; + self->rtus_.conv_d_.src_desc.data_type = data_type; + memory_desc_wrapper::compute_blocking( + self->rtus_.conv_d_.src_desc, dat_tag); + } +} + +template +inline void rtus_prepare_space_info(conv_pd_t *self, + memory_tracking::registrar_t &scratchpad, int max_threads) { + if (!self->rtus_.reduce_src_) return; + const auto &jcp = self->jcp_; + const bool is_nspc + = utils::one_of(jcp.src_tag, format_tag::nhwc, format_tag::nwc); + + const size_t factor = utils::pick_by_prop_kind(self->desc()->prop_kind, + jcp.nb_reduce, jcp.nb_load_blocking_max, jcp.nb_bcast_blocking); + size_t typesize + = types::data_type_size(self->invariant_src_md()->data_type); + + self->rtus_.space_per_thread_ + = is_nspc ? jcp.is * jcp.ic : factor * jcp.is * jcp.ic_block; + scratchpad.book(memory_tracking::names::key_conv_rtus_space, + max_threads * self->rtus_.space_per_thread_, typesize); +} + +template +struct rtus_driver_t : public jit_generator { + + struct call_params_t { + const void *ws; /* reduced image (w/ strides = 1) */ + const void *src; /* source image (w/ non-unit strides) */ + size_t icb; + size_t os; + size_t iw_start; + }; + + DECLARE_CPU_JIT_AUX_FUNCTIONS(rtus_driver_t) + + Xbyak::Reg64 reg_ws = r12; + Xbyak::Reg64 reg_src = r13; + Xbyak::Reg64 reg_icb = rdx; + Xbyak::Reg64 reg_os = r11; + Xbyak::Reg64 reg_iw_start = r8; + + Xbyak::Reg64 reg_cur_os = rax; + Xbyak::Reg64 reg_cur_iw = r9; + Xbyak::Reg64 reg_cur_src = r10; + Xbyak::Reg64 reg_cur_src_fin = reg_cur_iw; /* just reuse */ + + Xbyak::Opmask tail_mask = k2; + + // nspc section + Xbyak::Reg64 reg_cur_icb = rax; + Xbyak::Reg64 reg_tail_mask = r14; + Xbyak::Reg64 reg_icb_remainder = rcx; + Xbyak::Reg64 reg_ws_copy = r15; + + int iw_, stride_w_; + int src_step_h_, src_step_icb_, ws_step_icb_, vlen_, vlen_shift_; + bool src_to_ws_; + size_t typesize_; + int ic_, ic_tail_; + bool is_nspc_; + + Xbyak::Xmm reg_zero; + Xbyak::Xmm reg_v; + + rtus_driver_t(int iw, int stride_w, int src_step_h, int src_step_icb, + int ws_step_icb, bool src_to_ws, size_t typesize, int ic, + bool is_nspc = false) + : jit_generator(jit_name(), nullptr, MAX_CODE_SIZE, true, isa) + , iw_(iw) + , stride_w_(stride_w) + , src_step_h_(src_step_h) + , src_step_icb_(src_step_icb) + , ws_step_icb_(ws_step_icb) + , src_to_ws_(src_to_ws) + , typesize_(typesize) + , ic_(ic) + , is_nspc_(is_nspc) { + using namespace Xbyak; + + assert(ic_ > 0); + + /*FIXME: derive Vmm type on compile time. + * changing register type on runtime + * seems dangerous,and some xbyak functions might + * fail to work on reg_v, reg_zero because of this + * data_type change, e.g. uni_vpxor doen't + * work on reg_zero now*/ + auto Vmm = [this](int idx, size_t typesize) { + Xmm res; + if (is_nspc_) { + switch (isa) { + case sse41: res = Xmm(idx); break; + case avx2: res = Ymm(idx); break; + case avx512_core: res = Zmm(idx); break; + default: assert(!"Not supported isa"); res = Xmm(idx); + } + return res; + } + switch (isa) { + case sse41: + switch (typesize) { + case 2: res = Xmm(idx); break; + default: assert(!"Not supported typesize"); + } + break; + case avx2: + switch (typesize) { + case 4: res = Ymm(idx); break; + case 2: res = Xmm(idx); break; + default: + assert(!"Not supported typesize"); + res = Ymm(idx); + } + break; + case avx512_core: + switch (typesize) { + case 4: res = Zmm(idx); break; + case 2: res = Ymm(idx); break; + case 1: res = Xmm(idx); break; + default: + assert(!"Not supported typesize"); + res = Zmm(idx); + } + } + return res; + }; + + reg_zero = Vmm(0, typesize); + reg_v = Vmm(1, typesize); + + vlen_ = reg_v.getBit() / 8; + vlen_shift_ = 0; + + int tvlen = is_nspc_ ? typesize_ : vlen_; + while (tvlen > 1) { + tvlen /= 2; + vlen_shift_++; + } + + const int simd_w = vlen_ / sizeof(float); + ic_tail_ = ic_ % simd_w; + } + + void loop_is() { + using namespace Xbyak; + + mov(reg_cur_src, reg_src); + mov(reg_cur_iw, reg_iw_start); + mov(reg_cur_os, reg_os); + + Label is_loop; + L(is_loop); + + if (src_to_ws_) { + vmovups(reg_v, ptr[reg_cur_src]); + vmovups(ptr[reg_ws], reg_v); + } else { + vmovups(reg_v, ptr[reg_ws]); + vmovups(ptr[reg_cur_src], reg_v); + for (int w = 1; w < stride_w_; ++w) + vmovups(ptr[reg_cur_src + w * vlen_], reg_zero); + } + + add(reg_ws, vlen_); + add(reg_cur_src, stride_w_ * vlen_); + + // for 1d or stride_h=1 convolutions the loop over h should be skipped + if (!(src_step_icb_ == iw_ || src_step_h_ == iw_)) { + Label skip_h_step; + add(reg_cur_iw, stride_w_); + cmp(reg_cur_iw, iw_); + jl(skip_h_step, T_NEAR); + + if (src_to_ws_) { + add(reg_cur_src, (src_step_h_ - iw_) * vlen_); + } else { + mov(reg_cur_src_fin, reg_cur_src); + add(reg_cur_src_fin, (src_step_h_ - iw_) * vlen_); + Label ih_loop; + L(ih_loop); + + for (int w = 0; w < stride_w_; ++w) + vmovups(ptr[reg_cur_src + w * vlen_], reg_zero); + + add(reg_cur_src, stride_w_ * vlen_); + cmp(reg_cur_src, reg_cur_src_fin); + jl(ih_loop, T_NEAR); + } + xor_(reg_cur_iw, reg_cur_iw); + L(skip_h_step); + } + + sub(reg_cur_os, vlen_); + jnz(is_loop, T_NEAR); + + /* restore dst */ + sub(reg_ws, reg_os); + } + + void loop_is_nspc() { + using namespace Xbyak; + + assert(is_nspc_); + + mov(reg_cur_src, reg_src); + mov(reg_cur_iw, reg_iw_start); + + if (isa == avx512_core) { + push(rcx); // preserve rcx, used for shift + mov(reg_icb_remainder, reg_icb); + and_(reg_icb_remainder, + (vlen_ / typesize_) - 1); // # of elements in tail + mov(reg_tail_mask, 1); + shl(reg_tail_mask, reg_icb_remainder.cvt8()); + dec(reg_tail_mask); + pop(rcx); + + switch (typesize_) { + case 4: kmovw(tail_mask, reg_tail_mask.cvt32()); break; + case 2: kmovd(tail_mask, reg_tail_mask.cvt32()); break; + case 1: kmovq(tail_mask, reg_tail_mask); break; + default: assert(!"Unsupported typesize"); + } + } + + auto load_reg = [this](const Xmm &vreg, const Reg64 ®, + const int64_t offset, const int load_size) { + if (isa == avx512_core) { + const Address &addr = ptr[reg + offset]; + switch (typesize_) { + case 4: vmovups(vreg, addr); break; + case 2: vmovdqu16(vreg, addr); break; + case 1: vmovdqu8(vreg, addr); break; + default: assert(!"Unsupported typesize"); + } + } else { + // FIXME: figure out a better way for compile-time definition + // of xmm/ymm registers + const bool is_ymm = load_size > 16; + if (is_ymm) + load_bytes(Ymm(vreg.getIdx()), reg, offset, load_size); + else + load_bytes(vreg, reg, offset, load_size); + } + }; + + auto store_reg = [this](const Reg64 ®, const Xmm &vreg, + const int64_t offset, const int store_size) { + if (isa == avx512_core) { + const Address &addr = ptr[reg + offset]; + switch (typesize_) { + case 4: vmovups(addr, vreg); break; + case 2: vmovdqu16(addr, vreg); break; + case 1: vmovdqu8(addr, vreg); break; + default: assert(!"Unsupported typesize"); + } + } else { + // FIXME: figure out a better way for compile-time definition + // of xmm/ymm registers + const bool is_ymm = store_size > 16; + if (is_ymm) + store_bytes(Ymm(vreg.getIdx()), reg, offset, store_size); + else + store_bytes(vreg, reg, offset, store_size); + } + }; + + mov(reg_ws_copy, reg_ws); + shl(reg_icb, vlen_shift_); + + const size_t w_step_factor = ic_ * typesize_; + const size_t max_load_store_bytes = isa == sse41 + ? typesize_ == 4 ? 16 : 8 + : typesize_ == 4 ? 32 + : 16; + const size_t load_store_size + = isa == avx512_core ? vlen_ : max_load_store_bytes; + size_t load_store_tail_size = (typesize_ == 1 ? max_load_store_bytes + : ic_tail_ * typesize_); + + Label is_loop, ic_loop, ic_loop_tail, ic_loop_finish; + L(is_loop); + { + mov(reg_cur_src, reg_src); + mov(reg_ws, reg_ws_copy); + mov(reg_cur_icb, reg_icb); + + L(ic_loop); + { + cmp(reg_cur_icb, load_store_size); + jl(ic_loop_tail, T_NEAR); + + if (src_to_ws_) { + load_reg(reg_v, reg_cur_src, 0, load_store_size); + store_reg(reg_ws, reg_v, 0, load_store_size); + } else { + load_reg(reg_v, reg_ws, 0, load_store_size); + store_reg(reg_cur_src, reg_v, 0, load_store_size); + for (int w = 1; w < stride_w_; ++w) + store_reg(reg_cur_src, reg_zero, w * w_step_factor, + load_store_size); + } + add(reg_ws, load_store_size); + add(reg_cur_src, load_store_size); + + sub(reg_cur_icb, load_store_size); + jmp(ic_loop, T_NEAR); + } + + L(ic_loop_tail); + { + cmp(reg_cur_icb, 0); + je(ic_loop_finish, T_NEAR); + + if (src_to_ws_) { + load_reg(reg_v | tail_mask, reg_cur_src, 0, + load_store_tail_size); + store_reg( + reg_ws, reg_v | tail_mask, 0, load_store_tail_size); + } else { + load_reg( + reg_v | tail_mask, reg_ws, 0, load_store_tail_size); + store_reg(reg_cur_src, reg_v | tail_mask, 0, + load_store_tail_size); + for (int w = 1; w < stride_w_; ++w) + store_reg(reg_cur_src, reg_zero | tail_mask, + w * w_step_factor, load_store_tail_size); + } + } + L(ic_loop_finish); + + add(reg_ws_copy, w_step_factor); + add(reg_src, stride_w_ * w_step_factor); + + // for 1d or stride_h=1 convolutions the loop over h should be skipped + const bool skip_oh_step = src_step_h_ == iw_; + if (!skip_oh_step) { + mov(reg_cur_src, reg_src); + Label skip_h_step; + add(reg_cur_iw, stride_w_); + cmp(reg_cur_iw, iw_); + jl(skip_h_step, T_NEAR); + + if (src_to_ws_) { + add(reg_src, (src_step_h_ - iw_) * w_step_factor); + } else { + mov(reg_cur_src_fin, reg_cur_src); + add(reg_cur_src_fin, (src_step_h_ - iw_) * w_step_factor); + Label ih_loop_nhwc, ic_ih_loop_nhwc, ic_tail_ih_loop_nhwc, + ic_finish_ih_loop_nhwc; + L(ih_loop_nhwc); + mov(reg_cur_src, reg_src); + mov(reg_cur_icb, reg_icb); + L(ic_ih_loop_nhwc); + cmp(reg_cur_icb, load_store_size); + jl(ic_tail_ih_loop_nhwc, T_NEAR); + + for (int w = 0; w < stride_w_; ++w) + store_reg(reg_cur_src, reg_zero, w * w_step_factor, + load_store_size); + + add(reg_cur_src, load_store_size); + sub(reg_cur_icb, load_store_size); + jnz(ic_ih_loop_nhwc, T_NEAR); + + L(ic_tail_ih_loop_nhwc); + cmp(reg_cur_icb, 0); + jle(ic_finish_ih_loop_nhwc, T_NEAR); + + for (int w = 0; w < stride_w_; ++w) + store_reg(reg_cur_src, reg_zero | tail_mask, + w * w_step_factor, load_store_tail_size); + + L(ic_finish_ih_loop_nhwc); + + add(reg_src, stride_w_ * w_step_factor); + cmp(reg_src, reg_cur_src_fin); + jl(ih_loop_nhwc, T_NEAR); + } + xor_(reg_cur_iw, reg_cur_iw); + L(skip_h_step); + } + + sub(reg_os, 1); + jnz(is_loop, T_NEAR); + } + } + + void generate() override { + using namespace Xbyak; + assert(utils::one_of(isa, sse41, avx2, avx512_core)); + + preamble(); +#define READ_PARAM(what) \ + mov(reg_##what, ptr[abi_param1 + offsetof(call_params_t, what)]) + READ_PARAM(src); + READ_PARAM(icb); + READ_PARAM(os); + READ_PARAM(iw_start); + READ_PARAM(ws); +#undef READ_PARAM + + if (!src_to_ws_) { + switch (reg_zero.getBit() / 8) { + case 16 /*xmm*/: uni_vpxor(reg_zero, reg_zero, reg_zero); break; + case 32 /*ymm*/: { + Xbyak::Ymm ymm_z(reg_zero.getIdx()); + uni_vpxor(ymm_z, ymm_z, ymm_z); + break; + } + case 64 /*zmm*/: { + Xbyak::Zmm zmm_z(reg_zero.getIdx()); + uni_vpxor(zmm_z, zmm_z, zmm_z); + break; + } + default: assert(!"rtus kernel failure"); + } + } + if (is_nspc_) { + loop_is_nspc(); + } else { + shl(reg_os, vlen_shift_); + + Label icb_loop; + L(icb_loop); + + loop_is(); + + add(reg_ws, ws_step_icb_ * vlen_); + add(reg_src, src_step_icb_ * vlen_); + + sub(reg_icb, vlen_ / typesize_); + jnz(icb_loop, T_NEAR); + } + + postamble(); + + uni_vzeroupper(); + ret(); + } +}; + +template +inline status_t init_rtus_driver(conv_t *self) { + const auto &conf = *self->pd(); + if (!conf.rtus_.reduce_src_) return status::success; + + const auto &cd = *conf.desc(); + const int ndims = conf.ndims(); + const int stride_h = (conf.ndims() == 3) ? 1 : cd.strides[0]; + const int stride_w = cd.strides[ndims - 3]; + + const bool is_bwd_data = cd.prop_kind == prop_kind::backward_data; + const auto &src_d = is_bwd_data ? *conf.diff_src_md() : *conf.src_md(); + + const int ih = ndims == 3 ? 1 : src_d.dims[2]; + const int iw = src_d.dims[ndims - 1]; + const int ic = src_d.dims[1]; + + const auto src_tag = memory_desc_wrapper(src_d).matches_one_of_tag( + format_tag::nhwc, format_tag::nwc); + const bool is_nspc = src_tag != format_tag::undef; + const int src_step_h = stride_h * iw; + const int src_step_icb = !is_nspc ? ih * iw : 1; + const int ws_step_icb = !is_nspc ? conf.jcp_.is : 1; + const bool src_to_ws = !is_bwd_data; + const size_t typesize + = types::data_type_size(self->pd()->invariant_src_md()->data_type); + + CHECK(safe_ptr_assign(self->rtus_driver_, + new rtus_driver_t(iw, stride_w, src_step_h, src_step_icb, + ws_step_icb, src_to_ws, typesize, ic, is_nspc))); + + return self->rtus_driver_->create_kernel(); +} + +inline int best_divider(int value, int min_divider, int max_divider, + bool find_max, int step = 1) { + using namespace dnnl::impl::utils; + max_divider = nstl::max(1, nstl::min(max_divider, value)); + min_divider = nstl::max(1, nstl::min(min_divider, max_divider)); + + auto loss_ratio = [](int total, int chunk) { + return float(rnd_up(total, chunk) - total) / rnd_up(total, chunk); + }; + + float min_loss = FLT_MAX; + int x_divider = max_divider; + for (int divider = max_divider; divider >= min_divider; divider -= step) { + const float loss = loss_ratio(value, divider); + if ((find_max && loss < min_loss) || (!find_max && loss <= min_loss)) { + min_loss = loss; + x_divider = divider; + } + } + return x_divider; +} + +typedef jit_1x1_conv_conf_t jcp_t; + +inline bool is_bcast_layout_nxc(const jcp_t &jcp) { + switch (jcp.prop_kind) { + case prop_kind::forward_training: + case prop_kind::forward_inference: + case prop_kind::backward_weights: + return utils::one_of(jcp.src_tag, format_tag::ndhwc, + format_tag::nhwc, format_tag::nwc); + case prop_kind::backward_data: + return utils::one_of(jcp.dst_tag, format_tag::ndhwc, + format_tag::nhwc, format_tag::nwc); + default: assert(!"invalid prop_kind"); return false; + } +} + +inline bool is_load_layout_nxc(const jcp_t &jcp) { + return jcp.prop_kind == prop_kind::backward_weights + && utils::one_of(jcp.dst_tag, format_tag::ndhwc, format_tag::nhwc, + format_tag::nwc); +} + +inline bool is_out_layout_nxc(const jcp_t &jcp) { + switch (jcp.prop_kind) { + case prop_kind::forward_training: + case prop_kind::forward_inference: + return utils::one_of(jcp.dst_tag, format_tag::ndhwc, + format_tag::nhwc, format_tag::nwc); + case prop_kind::backward_data: + return utils::one_of(jcp.src_tag, format_tag::ndhwc, + format_tag::nhwc, format_tag::nwc); + case prop_kind::backward_weights: return false; + default: assert(!"invalid prop_kind"); return false; + } +} + +inline size_t get_bcast_u_offset(const jcp_t &jcp) { + return is_bcast_layout_nxc(jcp) ? jcp.ic : jcp.ic_block; +} + +inline size_t get_bcast_j_offset(const jcp_t &jcp) { + return is_bcast_layout_nxc(jcp) ? jcp.reduce_dim : jcp.reduce_loop_unroll; +} + +inline size_t get_bcast_offset(const jcp_t &jcp, int u, int j) { + size_t offset; + if (utils::one_of(jcp.prop_kind, prop_kind::forward_training, + prop_kind::forward_inference, prop_kind::backward_data)) { + assert(jcp.reduce_loop_unroll == jcp.reduce_block); + if (is_bcast_layout_nxc(jcp) || u != jcp.reduce_loop_unroll) { + offset = j * get_bcast_j_offset(jcp) + u; + } else { + offset = (jcp.bcast_dim + j) * get_bcast_j_offset(jcp); + } + } else { + offset = u * get_bcast_u_offset(jcp) + j; + } + return sizeof(float) * offset; +} + +inline size_t get_load_u_offset(const jcp_t &jcp) { + return is_load_layout_nxc(jcp) ? jcp.oc : jcp.oc_block; +} + +inline size_t get_load_i_offset(const jcp_t &jcp) { + return is_load_layout_nxc(jcp) ? jcp.oc_block : jcp.os; +} + +inline size_t get_load_bwd_w_offset(const jcp_t &jcp, int i, int u0) { + if (is_load_layout_nxc(jcp)) { + return i * get_load_i_offset(jcp) + u0 * get_load_u_offset(jcp); + } else { + return (i * get_load_i_offset(jcp) + u0) * get_load_u_offset(jcp); + } +} + +inline size_t get_output_i_offset( + const jcp_t &jcp, bool ignore_dw_conv = false) { + if (is_out_layout_nxc(jcp)) { + return jcp.load_block; + } else { + return (!ignore_dw_conv && jcp.with_dw_conv ? jcp.ow : jcp.bcast_dim) + * jcp.load_block; + } +} + +inline size_t get_output_j_offset(const jcp_t &jcp) { + return is_out_layout_nxc(jcp) ? jcp.load_dim : jcp.load_block; +} + +inline size_t get_load_loop_output_fwd_offset( + const jcp_t &jcp, int load_loop_blk, bool ignore_dw_conv = false) { + size_t offset = load_loop_blk * jcp.oc_block * sizeof(float); + if (!is_out_layout_nxc(jcp)) { + offset *= !ignore_dw_conv && jcp.with_dw_conv ? jcp.ow : jcp.os; + } + return offset; +} + +inline size_t get_load_loop_output_bwd_d_offset( + const jcp_t &jcp, int load_loop_blk) { + size_t offset = load_loop_blk * jcp.ic_block * sizeof(float); + if (!is_out_layout_nxc(jcp)) { offset *= jcp.os; } + return offset; +} + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_batch_normalization.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_batch_normalization.hpp new file mode 100644 index 0000000000000000000000000000000000000000..d223baa8fa40ec73575f04303402dcf8ea9ced9f --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_batch_normalization.hpp @@ -0,0 +1,124 @@ +/******************************************************************************* +* Copyright 2017-2022 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_UNI_BATCH_NORMALIZATION_HPP +#define CPU_X64_JIT_UNI_BATCH_NORMALIZATION_HPP + +#include + +#include "common/c_types_map.hpp" +#include "common/primitive.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_batch_normalization_pd.hpp" +#include "cpu/x64/cpu_isa_traits.hpp" +#include "cpu/x64/jit_avx512_core_bf16cvt.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +namespace bnorm_impl { +template +struct driver_t; +} + +template +struct jit_uni_batch_normalization_fwd_t : public primitive_t { + struct pd_t : public cpu_batch_normalization_fwd_pd_t { + pd_t(const batch_normalization_desc_t *adesc, + const primitive_attr_t *attr, + const batch_normalization_fwd_pd_t *hint_fwd_pd) + : cpu_batch_normalization_fwd_pd_t(adesc, attr, hint_fwd_pd) {} + + DECLARE_COMMON_PD_T( + JIT_IMPL_NAME_HELPER("bnorm_jit:", + (src_md()->data_type == data_type::bf16) + ? (mayiuse(avx512_core_bf16) ? avx512_core_bf16 + : mayiuse(avx512_core) + ? bf16_emulation_t::get_isa() + : avx2_vnni_2) + : (src_md()->data_type == data_type::f16) + ? (mayiuse(avx512_core_fp16) ? avx512_core_fp16 + : avx2_vnni_2) + : isa, + ""), + jit_uni_batch_normalization_fwd_t); + + status_t init(engine_t *engine); + int nthr_; // To not exceed the limit in execute used for set up. + }; + + jit_uni_batch_normalization_fwd_t(const pd_t *apd); + ~jit_uni_batch_normalization_fwd_t(); + + status_t init(engine_t *engine) override; + + status_t execute(const exec_ctx_t &ctx) const override; + +private: + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + bnorm_impl::driver_t *bnorm_driver_; +}; + +template +struct jit_uni_batch_normalization_bwd_t : public primitive_t { + struct pd_t : public cpu_batch_normalization_bwd_pd_t { + pd_t(const batch_normalization_desc_t *adesc, + const primitive_attr_t *attr, + const batch_normalization_fwd_pd_t *hint_fwd_pd) + : cpu_batch_normalization_bwd_pd_t(adesc, attr, hint_fwd_pd) {} + + DECLARE_COMMON_PD_T( + JIT_IMPL_NAME_HELPER("bnorm_jit:", + (src_md()->data_type == data_type::bf16) + ? (mayiuse(avx512_core_bf16) + ? avx512_core_bf16 + : bf16_emulation_t::get_isa()) + : (src_md()->data_type == data_type::f16) + ? avx512_core_fp16 + : isa, + ""), + jit_uni_batch_normalization_bwd_t); + + status_t init(engine_t *engine); + int nthr_; // To not exceed the limit in execute used for set up. + }; + + jit_uni_batch_normalization_bwd_t(const pd_t *apd); + ~jit_uni_batch_normalization_bwd_t(); + + status_t init(engine_t *engine) override; + + status_t execute(const exec_ctx_t &ctx) const override; + +private: + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + bnorm_impl::driver_t *bnorm_driver_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_batch_normalization_s8.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_batch_normalization_s8.hpp new file mode 100644 index 0000000000000000000000000000000000000000..b9e32654a9cc287d6133c00c9759f43d4f20889d --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_batch_normalization_s8.hpp @@ -0,0 +1,76 @@ +/******************************************************************************* +* Copyright 2019-2020 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_UNI_BATCH_NORMALIZATION_S8_HPP +#define CPU_X64_JIT_UNI_BATCH_NORMALIZATION_S8_HPP + +#include + +#include "common/c_types_map.hpp" +#include "common/primitive.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_batch_normalization_pd.hpp" +#include "cpu/x64/cpu_isa_traits.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +namespace bnorm_s8_impl { +template +struct driver_t; +} + +template +struct jit_uni_batch_normalization_s8_fwd_t : public primitive_t { + struct pd_t : public cpu_batch_normalization_fwd_pd_t { + pd_t(const batch_normalization_desc_t *adesc, + const primitive_attr_t *attr, + const batch_normalization_fwd_pd_t *hint_fwd_pd) + : cpu_batch_normalization_fwd_pd_t(adesc, attr, hint_fwd_pd) {} + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("bnorm_s8_jit:", isa, ""), + jit_uni_batch_normalization_s8_fwd_t); + + status_t init(engine_t *engine); + }; + + typedef int8_t data_t; + + jit_uni_batch_normalization_s8_fwd_t(const pd_t *apd); + ~jit_uni_batch_normalization_s8_fwd_t(); + + status_t init(engine_t *engine) override; + + status_t execute(const exec_ctx_t &ctx) const override; + +private: + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + bnorm_s8_impl::driver_t *bnorm_driver_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_binary.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_binary.hpp new file mode 100644 index 0000000000000000000000000000000000000000..6b608302beb6489e5174d1ea59d2e7f37544a2d1 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_binary.hpp @@ -0,0 +1,114 @@ +/******************************************************************************* +* Copyright 2019-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_UNI_BINARY_HPP +#define CPU_X64_JIT_UNI_BINARY_HPP + +#include "common/primitive.hpp" + +#include "cpu/cpu_eltwise_pd.hpp" +#include "cpu/x64/jit_uni_binary_kernel.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +struct binary_kernel_t; + +using op_t = binary_op_t; +using bcast_t = binary_bcast_t; + +struct jit_uni_binary_t : public primitive_t { + struct pd_t : public cpu_binary_pd_t { + using cpu_binary_pd_t::cpu_binary_pd_t; + + DECLARE_COMMON_PD_T("jit:uni", jit_uni_binary_t); + + status_t init(engine_t *engine); + + jit_binary_conf_t get_conf() const { return conf_; }; + + private: + op_t get_op_type(const memory_desc_wrapper &src0_d); + bool is_only_dim0_bcasted(const dims_t &bcast_dims, const int ndims); + bcast_t get_bcast_type( + const memory_desc_wrapper &src1_d, const dims_t &bcast_dims); + + // alg_preserves_zero returns true if operation preserves zero in case + // of both inputs contain zero. + bool alg_preserves_zero() const; + bool check_scales_mask() const; + bool is_bcast_pattern(const dims_t &bcast_dims, const dim_t ndims, + const dim_t N_bcast, const dim_t C_bcast, + const dim_t W_bcast) const; + bool is_bcast_pattern(const dims_t &bcast_dims, const dim_t N_bcast, + const dim_t C_bcast) const; + bool is_bcast_allowed(const int ndims) const; + bool is_format_non_blocked(const memory_desc_wrapper &mdw) const; + bool is_different_layouts_allowed(const memory_desc_wrapper &src0_d, + const memory_desc_wrapper &src1_d) const; + bool is_applicable(); + + jit_binary_conf_t conf_; + }; + + jit_uni_binary_t(const pd_t *apd); + ~jit_uni_binary_t() = default; + + status_t init(engine_t *engine) override; + + using data_t = int8_t; + + void execute_no_bcast_strategy(const data_t *src0, const data_t *src1, + data_t *dst, const float *scale0, const float *scale1, + const std::vector &post_ops_binary_rhs_arg_vec, + const bcast_t bcast_type) const; + void execute_bcast_per_batch_strategy(const data_t *src0, + const data_t *src1, data_t *dst, const float *scale0, + const float *scale1, + const std::vector &post_ops_binary_rhs_arg_vec) const; + void execute_bcast_per_c_strategy(const data_t *src0, const data_t *src1, + data_t *dst, const float *scale0, const float *scale1, + const std::vector &post_ops_binary_rhs_arg_vec, + const op_t op_type, const bcast_t bcast_type, + const bool blocked_oc_tail) const; + void execute_bcast_per_w_strategy(const data_t *src0, const data_t *src1, + data_t *dst, const float *scale0, const float *scale1, + const std::vector &post_ops_binary_rhs_arg_vec, + const op_t op_type, const bool blocked_oc_tail) const; + + status_t execute(const exec_ctx_t &ctx) const override; + +private: + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + static bool post_ops_ok(const primitive_attr_t *attr, + const memory_desc_wrapper &src0_d, const memory_desc_wrapper &dst_d, + const bool is_src1_different_layouts, const cpu_isa_t isa); + + std::unique_ptr kernel_; + // used only in bcast_c_blocked strategy if tail exists + std::unique_ptr kernel_tail_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_binary_kernel.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_binary_kernel.hpp new file mode 100644 index 0000000000000000000000000000000000000000..021c4749adee6254797cf58564246e8ca72a6019 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_binary_kernel.hpp @@ -0,0 +1,165 @@ +/******************************************************************************* +* Copyright 2021-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_UNI_BINARY_KERNEL_HPP +#define CPU_X64_UNI_BINARY_KERNEL_HPP + +#include + +#include "common/c_types_map.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/x64/cpu_isa_traits.hpp" +#include "cpu/x64/injectors/jit_uni_postops_injector.hpp" +#include "cpu/x64/jit_generator.hpp" +#include "cpu/x64/jit_primitive_conf.hpp" +#include "cpu/x64/utils/jit_io_helper.hpp" + +#include "cpu/cpu_binary_pd.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +using namespace Xbyak; + +struct binary_kernel_t : public jit_generator { + using op_t = binary_op_t; + using bcast_t = binary_bcast_t; + + binary_kernel_t(const size_t vlen, const binary_pd_t *pd, + const jit_binary_conf_t conf, const char *name, + bool tail_kernel = false); + ~binary_kernel_t() override = default; + + void operator()(jit_binary_call_s *p) { jit_generator::operator()(p); } + + size_t simd_w() const noexcept { return simd_w_; } + size_t vlen() const noexcept { return vlen_; } + +protected: + size_t get_tail_size() const; + + const size_t vlen_; + const size_t simd_w_; + constexpr static int vmm_start_idx_ = 1; + const binary_pd_t *pd_; + const jit_binary_conf_t conf_; + const bool is_tail_kernel_; + const bool is_src1_outer_dims_tail_; + const size_t tail_size_; + const size_t padding_tail_size_; +}; + +template +struct jit_uni_binary_kernel_t : public binary_kernel_t { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_uni_binary_kernel_t) + + const AddressFrame &vmmword = (std::is_same::value) + ? xword + : ((std::is_same::value) ? yword : zword); + + const bool is_avx512 = is_superset(isa, avx512_core); + + const Reg64 reg_param_ = abi_param1; + const Reg64 reg_src0_ = r8; + const Reg64 reg_src1_ = r9; + const Reg64 reg_dst_ = r10; + const Reg64 reg_offt_src0_ = r11; + const Reg64 reg_outer_dims_range_ = r12; + const Reg64 reg_offt_src1_ = rax; + const Reg64 reg_src1_stride_range_ = r15; + const Reg64 reg_reverse_src1_stride_range_ = rax; + const Reg64 reg_reverse_spat_offt_ = r13; + const Reg64 reg_tmp_ = r14; + const Reg64 reg_tmp1_ = abi_not_param1; + const Reg64 reg_elt_inj_table_ = r15; + const Reg64 reg_off_rhs_postops_ = rdx; + const Reg64 reg_scales_src0_ = rbx; + const Reg64 reg_scales_src1_ = rbp; + const Reg64 reg_offt_dst_ = rdx; + const Opmask tail_opmask_ = k2; + const Opmask cmp_mask = k3; + const Opmask full_mask_ = k4; + const Vmm vmm_tail_vmask_ = Vmm(0); + const Vmm vreg_sum_scale_ = Vmm(is_avx512 ? 17 : 9); + const Xmm xreg_sum_scale_ = Xmm(9); + const Vmm vreg_zero_ = Vmm(is_avx512 ? 18 : 10); + const Vmm vreg_one_ = Vmm(is_avx512 ? 19 : 11); + const Vmm vreg_saturation_ubound_ = Vmm(is_avx512 ? 20 : 12); + const Vmm vreg_bcast_src1_ = Vmm(is_avx512 ? 21 : 13); + const Xmm xreg_bcast_src1_ = Xmm(13); + const Vmm vreg_scales_src0_ = Vmm(is_avx512 ? 22 : 14); + const Vmm vreg_scales_src1_ = Vmm(is_avx512 ? 23 : 15); + + const Zmm vreg_bf16_emu_1_ = Zmm(26); + const Zmm vreg_bf16_emu_2_ = Zmm(27); + const Zmm vreg_bf16_emu_3_ = Zmm(28); + const Zmm vreg_bf16_emu_4_ = Zmm(29); + + const Vmm vmm_full_mask_ = Vmm(is_avx512 ? 24 : 5); + const Vmm vmm_tmp_gather_ = Vmm(is_avx512 ? 25 : 6); + const Vmm vmm_indices_ = Vmm(is_avx512 ? 30 : 7); + const Vmm vmm_gathered_src_ = Vmm(is_avx512 ? 31 : 8); + + const size_t unroll_regs_ = is_avx512 ? 8 : 4; + const size_t offt_src0_; + const size_t offt_src1_; + + static constexpr cpu_isa_t inject_isa + = isa == avx512_core_bf16 ? avx512_core : isa; + io::jit_io_multi_dt_helper_t io_; + std::unique_ptr> + postops_injector_; + const Opmask elt_inj_opmask_ = k1; + + void init(); + void init_post_ops_injector(); + void apply_postops(int unroll, bool tail); + void load_kernel_params(); + Address src0_ptr(size_t offt = 0); + Address src1_ptr(size_t offt = 0); + Address dst_ptr(size_t offt = 0); + unsigned int cmp_predicate(alg_kind_t alg); + void perform_op( + const Vmm &v0, const Vmm &v1, const Vmm &s_src0, const Vmm &s_src1); + void prepare_isa_kernel(); + void compute_bcast(bool tail); + void load_src1(const Vmm &vreg_src1, const int offt, bool tail); + void store(int unroll, bool tail); + void compute_ne_xf16_dst_body(int unroll, bool tail); + void compute_dst_body(int unroll, bool tail); + void compute_dst(int unroll, bool tail); + void forward(); + void forward_over_outer_dims(); + void generate() override; + + jit_uni_binary_kernel_t(const binary_pd_t *pd, const jit_binary_conf_t conf, + bool tail_kernel = false); + ~jit_uni_binary_kernel_t() override = default; + + std::map + create_saturation_vmm_map() const; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_convert_xf16.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_convert_xf16.hpp new file mode 100644 index 0000000000000000000000000000000000000000..775beaace64515cab9d5868f18b3ae7f7ae72cb2 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_convert_xf16.hpp @@ -0,0 +1,278 @@ +/******************************************************************************* +* Copyright 2022 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_UNI_CONVERT_XF16_HPP +#define CPU_X64_JIT_UNI_CONVERT_XF16_HPP + +#include + +#include "common/c_types_map.hpp" +#include "common/float16.hpp" +#include "common/nstl.hpp" +#include "common/type_helpers.hpp" + +#include "cpu/x64/cpu_isa_traits.hpp" +#include "cpu/x64/jit_avx512_core_bf16cvt.hpp" +#include "cpu/x64/jit_generator.hpp" + +#include "oneapi/dnnl/dnnl_debug.h" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +namespace cvt_xf16_support { +struct jit_call_t { + void *inp; + void *out; + void *add; + size_t nelems; +}; +struct jit_cvt_xf16_to_ps_params_t { + const void *inp; + void *out; + size_t nelems; + size_t rows; +}; +} // namespace cvt_xf16_support + +template +struct jit_uni_cvt_ps_to_xf16_t : public jit_generator { + + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_uni_cvt_ps_to_xf16_t) + + jit_uni_cvt_ps_to_xf16_t(impl::data_type_t dt, size_t nelems = 0) + : jit_generator(jit_name()) + , output_dt_(dt) + , nelems_(nelems) + , is_dynamic_size_(nelems_ == 0) + , tail_size_(nelems_ % simd_w_) {} + + void generate() override; + +protected: + const impl::data_type_t output_dt_; // bf16 or f16 + const size_t nelems_; + const bool is_dynamic_size_; + const int tail_size_; + + constexpr static int simd_w_ = cpu_isa_traits::vlen / sizeof(float); + using Vmm = typename cpu_isa_traits::Vmm; + using Vmm_down_t = typename vreg_traits::Vmm_lower_t; + + const Vmm vmm_input = Vmm(0); + const Vmm_down_t vmm_output = Vmm_down_t(1); + + // used in avx2_vnni_2 + const Vmm vmm_in_mask = Vmm(2); + const Vmm_down_t vmm_out_mask = Vmm(3); + // used in bf16 emulation + const Vmm vmm_one = Vmm(2); + const Vmm vmm_even = Vmm(3); + const Vmm vmm_selector = Vmm(4); + const Vmm vmm_fp32_tmp = Vmm(5); + // used in avx512_core[_fp16] + const Xbyak::Opmask ktail_f32_mask = Xbyak::Opmask(2); + const Xbyak::Opmask ktail_xf16_mask = Xbyak::Opmask(3); + + Xbyak::Reg64 reg_input = rax; + Xbyak::Reg64 reg_output = rbx; + Xbyak::Reg64 reg_nelems = rdx; + Xbyak::Reg64 reg_tail = rcx; + Xbyak::Reg64 reg_tmp = r8; + Xbyak::Reg64 reg_scratch = r9; + + void setup_mask(); + virtual void cvt_ps_to_xf16(const int idx, const bool is_tail); + virtual void init_bf16() {} // unused for f16 +}; + +struct jit_avx512_core_cvt_ps_to_bf16_t + : public jit_uni_cvt_ps_to_xf16_t { + + jit_avx512_core_cvt_ps_to_bf16_t(impl::data_type_t dt, size_t nelems = 0) + : jit_uni_cvt_ps_to_xf16_t(dt, nelems) + , use_bf16_emu_(!mayiuse(avx512_core_bf16)) + , bf16_emu_(use_bf16_emu_ ? utils::make_unique(this, + vmm_one, vmm_even, vmm_selector, reg_scratch, + vmm_fp32_tmp) + : nullptr) { + assert(dt == data_type::bf16); + } + +private: + const bool use_bf16_emu_; + std::unique_ptr bf16_emu_; + + void cvt_ps_to_xf16(const int idx, const bool is_tail) override; + void init_bf16() override { + if (use_bf16_emu_) bf16_emu_->init_vcvtneps2bf16(); + } +}; + +struct jit_cvt_ps_to_xf16_t { + + jit_cvt_ps_to_xf16_t(impl::data_type_t data_type, size_t nelems = 0) + : nelems_(nelems) { + if (data_type == data_type::f16 && mayiuse(avx512_core_fp16)) + kernel_ = utils::make_unique< + jit_uni_cvt_ps_to_xf16_t>( + data_type, nelems); + else if (data_type == data_type::bf16 && mayiuse(avx512_core)) + kernel_ = utils::make_unique( + data_type, nelems); + else if (mayiuse(avx2_vnni_2)) + kernel_ = utils::make_unique>( + data_type, nelems); + else { + assert(!"unsupported ISA for converter"); + return; + } + kernel_->create_kernel(); + } + + void operator()(cvt_xf16_support::jit_call_t *params) const { + (*kernel_)(params); + msan_unpoison(params->out, + (nelems_ ? nelems_ : params->nelems) * sizeof(float16_t)); + } + +private: + std::unique_ptr kernel_; + const size_t nelems_; +}; + +template +struct jit_uni_cvt_xf16_to_ps_t : public jit_generator { + + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_uni_cvt_xf16_to_ps_t) + + jit_uni_cvt_xf16_to_ps_t( + impl::data_type_t dt, bool with_add, size_t row_stride) + : jit_generator(jit_name()) + , input_dt_(dt) + , with_add_(with_add) + , row_stride_(row_stride) { + create_kernel(); + } + + void generate() override; + +protected: + constexpr static int elem_granularity = isa == avx2_vnni_2 ? 2 : 1; + constexpr static int simd_w_ = cpu_isa_traits::vlen / sizeof(float); + using Vmm = typename cpu_isa_traits::Vmm; + using Vmm_down_t = typename vreg_traits::Vmm_lower_t; + + const impl::data_type_t input_dt_; + const bool with_add_; + + const size_t row_stride_; + + const Xbyak::Reg64 reg_input = rax; + const Xbyak::Reg64 reg_output = rbx; + const Xbyak::Reg64 reg_nelems = r8; + const Xbyak::Reg64 reg_nrows = r9; + + const Xbyak::Reg64 reg_tail = rcx; //used for cl + + const Xbyak::Reg64 reg_long_row_stride = r10; + const Xbyak::Reg64 reg_rollback = r11; + const Xbyak::Reg64 reg_nelems_save = r12; + + const Xbyak::Reg64 reg_tmp = r13; + + const Xbyak::Opmask ktail_mask = Xbyak::Opmask(1); + + const Vmm vmm_tmp = Vmm(13); + const Vmm vmm_dst = Vmm(14); + const Vmm vmm_dst_2 = Vmm(15); + const Vmm_down_t vmm_in_mask = Vmm_down_t(15); + + Vmm get_vmm_src(int idx) { return Vmm(get_even_src_idx(idx)); } + int get_even_src_idx(int idx) { + assert(idx < 4); + return idx; + } + int get_odd_src_idx(int idx) { + assert(idx < 4); + return idx + 4; + } + + void convert_xf16(const int idx, const bool handle_x2); + void cvt_tail(); +}; + +struct jit_cvt_xf16_to_ps_t { + + jit_cvt_xf16_to_ps_t(impl::data_type_t data_type, bool with_add = false, + size_t row_stride = 0) { + if (data_type == data_type::f16 && mayiuse(avx512_core_fp16)) + kernel_ = utils::make_unique< + jit_uni_cvt_xf16_to_ps_t>( + data_type, with_add, row_stride); + else if (data_type == data_type::bf16 && mayiuse(avx512_core)) + kernel_ = utils::make_unique>( + data_type, with_add, row_stride); + else if (mayiuse(avx2_vnni_2)) { + if (row_stride != 0) { + assert(!"unsupported row_stride for avx2_vnni_2"); + return; + } else if (with_add) { + assert(!"untested implementation 'with_add' for avx2_vnni_2"); + return; + } + kernel_ = utils::make_unique>( + data_type, with_add, row_stride); + } else { + assert(!"unsupported configuration for converter"); + return; + } + kernel_->create_kernel(); + } + + void operator()( + float *out, const void *inp, size_t nelems, size_t rows = 1) const { + cvt_xf16_support::jit_cvt_xf16_to_ps_params_t p; + p.inp = inp; + p.out = (void *)out; + p.nelems = nelems; + p.rows = rows; + (*kernel_)(&p); + msan_unpoison(out, nelems * sizeof(float)); + } + + void operator()(float *out, const float16_t *inp, size_t nelems, + size_t rows = 1) const { + (*this)(out, (const void *)inp, nelems, rows); + } + + void operator()(float *out, const bfloat16_t *inp, size_t nelems, + size_t rows = 1) const { + (*this)(out, (const void *)inp, nelems, rows); + } + +private: + std::unique_ptr kernel_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_deconv_zp_pad_str_kernel.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_deconv_zp_pad_str_kernel.hpp new file mode 100644 index 0000000000000000000000000000000000000000..9b5707804d8baa87b2cfd40fe684cf2c1f777037 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_deconv_zp_pad_str_kernel.hpp @@ -0,0 +1,121 @@ +/******************************************************************************* +* Copyright 2021 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_UNI_DECONV_ZP_PAD_STR_KERNEL_HPP +#define CPU_X64_JIT_UNI_DECONV_ZP_PAD_STR_KERNEL_HPP + +#include "cpu/x64/jit_generator.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +struct jit_conv_conf_t; + +namespace zp { + +struct jit_uni_deconv_zp_pad_str_call_params_t { + const int8_t *wei; + const int32_t *src_zero_point; + int32_t *dst_scratchpad; + bool last_oc_block; +}; + +/* + * Compute zero point source compensation applied during filter application on + * the padding as well as stride holes. + * + * zp_pad_str_compensation = conv(1, weights_s8) * zero_point_source + * + * output_format - dhwc + */ +class jit_uni_deconv_zp_pad_str_kernel_base_t : public jit_generator { +public: + jit_uni_deconv_zp_pad_str_kernel_base_t(const jit_conv_conf_t &jcp); + + void operator()(const jit_uni_deconv_zp_pad_str_call_params_t *params) { + jit_generator::operator()(params); + } + + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_uni_deconv_zp_pad_str_kernel_base_t); + +private: + DNNL_DISALLOW_COPY_AND_ASSIGN(jit_uni_deconv_zp_pad_str_kernel_base_t); + + void generate() override; + void load_addresses(); + void compute(); + virtual void compute_step(const dim_t icb_offset) = 0; + virtual void apply_zero_point() = 0; + virtual void store_result() = 0; + virtual void init() = 0; + +protected: + size_t number_reserved_vmms_ = 0; + size_t reserve_vmm(); + + const jit_conv_conf_t &jcp_; + const Xbyak::Reg64 ®_src_zp_ = r8; + const Xbyak::Reg64 ®_wei_ = r9; + const Xbyak::Reg64 ®_dst_ = r10; + const Xbyak::Reg64 ®_tmp_ = r11; + const Xbyak::Reg8 ®_last_oc_block_ = r12b; + const size_t tail_size_; +}; + +template +class jit_uni_deconv_zp_pad_str_kernel_t + : public jit_uni_deconv_zp_pad_str_kernel_base_t { +public: + jit_uni_deconv_zp_pad_str_kernel_t(const jit_conv_conf_t &jcp); + +private: + void init() override; + void compute_step(const dim_t icb_offset) override; + void apply_zero_point() override; + void store_result() override; + + Vmm get_next_vmm(); + + const Vmm result_acc_; + const Vmm vmm_tmp_; + const Vmm vmm_one_bytes_; + const Vmm vmm_one_words_; + + const Xbyak::Opmask &ktail_mask_ = k2; + dim_t current_vmm_; +}; + +bool should_calculate_deconv_zp_src_pad_str_comp( + const jit_conv_conf_t &jcp) noexcept; + +template +jit_uni_deconv_zp_pad_str_kernel_base_t *create_deconv_zp_pad_str_comp_ker( + const jit_conv_conf_t &jcp); + +void compute_deconv_zp_pad_str_comp_ker(const jit_conv_conf_t &jcp_, + const bool with_groups, const memory_desc_wrapper &wei_d, + const int8_t *wei, const int32_t *src_zp, int32_t *dst, + jit_uni_deconv_zp_pad_str_kernel_base_t *ker); + +} // namespace zp +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_dw_conv_kernel_f32.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_dw_conv_kernel_f32.hpp new file mode 100644 index 0000000000000000000000000000000000000000..1a152cec9e7fa52e4a35ee95f8ff297199eebbe7 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_dw_conv_kernel_f32.hpp @@ -0,0 +1,339 @@ +/******************************************************************************* +* Copyright 2019-2022 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_UNI_DW_CONV_KERNEL_F32_HPP +#define CPU_X64_JIT_UNI_DW_CONV_KERNEL_F32_HPP + +#include "common/c_types_map.hpp" +#include "common/memory_tracking.hpp" + +#include "cpu/x64/injectors/jit_uni_binary_injector.hpp" +#include "cpu/x64/injectors/jit_uni_eltwise_injector.hpp" +#include "cpu/x64/injectors/jit_uni_postops_injector.hpp" +#include "cpu/x64/jit_generator.hpp" +#include "cpu/x64/jit_primitive_conf.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +template +struct jit_uni_dw_conv_fwd_kernel_f32 : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_uni_dw_conv_fwd_kernel_f32) + + jit_uni_dw_conv_fwd_kernel_f32( + const jit_conv_conf_t &ajcp, const memory_desc_t &dst_md); + + jit_conv_conf_t jcp; + +private: + using Vmm = typename utils::conditional3::type; + using reg64_t = const Xbyak::Reg64; + using mask_t = const Xbyak::Opmask; + const Xbyak::AddressFrame &vmmword = (isa == sse41) ? xword + : (isa == avx2) ? yword + : zword; + const int vlen = cpu_isa_traits::vlen; + + // dw convolution + reg64_t reg_input = r8; + reg64_t aux_reg_input = r9; + reg64_t reg_kernel = r10; + reg64_t aux_reg_kernel = r11; + reg64_t reg_ch_blocks = r12; + reg64_t reg_output = r13; + reg64_t reg_bias = r14; + reg64_t reg_kh = r15; + reg64_t iter_kh = rax; + reg64_t reg_oi = rbx; + reg64_t aux_reg_ch_blocks = rsi; + // fused convolution + reg64_t reg_input_buffer_ptr = rdx; + reg64_t aux_reg_input_buffer_ptr = rbp; + reg64_t reg_iw_offset = reg_input; //Hack: clear reg_input early in kernel + + reg64_t reg_tmp = reg_ch_blocks; + reg64_t reg_tail = rax; + mask_t k_oc_tail_mask = Xbyak::Opmask(2); + + inline void load_src(int ur_ch_blocks, int ur_w, bool is_ch_tail); + inline void compute_loop(int ur_w, int ur_ch_blocks, int pad_l, int pad_r); + inline void ow_loop(int ur_ch_blocks); + inline void apply_filter_unrolled( + int ur_ch_blocks, int ur_w, int pad_l, int pad_r, bool is_ch_tail); + inline void apply_postops( + const int ur_ch_blocks, const int ur_w, const bool is_ch_tail); + inline void store_dst(int ur_ch_blocks, int ur_w, bool is_ch_tail); + + int max_repeats() { return jcp.isa == sse41 ? 2 : 1; } + + inline Vmm get_ker_reg(int idx) { return Vmm(idx + 0); } + inline Vmm get_src_reg(int idx) { return Vmm(idx + 1); } + inline int get_acc_reg_idx(int idx) { + const int max_regs = jcp.isa == avx512_core ? 32 : 16; + return idx + (max_regs - jcp.ur_w * jcp.nb_ch_blocking * max_repeats()); + } + inline Vmm get_acc_reg(int idx) { return Vmm(get_acc_reg_idx(idx)); } + + void load_tail( + Vmm &vmm, const Xbyak::Reg64 ®, int64_t offset, int load_size); + void add_tail_from_mem(Vmm &vmm_acc, Vmm &vmm_tmp, const Xbyak::Reg64 ®, + int64_t offset, int load_size); + void store_tail( + Vmm &vmm, const Xbyak::Reg64 ®, int64_t offset, int store_size); + + int get_ow_start(int ki, int pad_l) { + return nstl::max(0, + utils::div_up(pad_l - ki * (jcp.dilate_w + 1), jcp.stride_w)); + } + + int get_ow_end(int ur_w, int ki, int pad_r) { + return ur_w + - nstl::max(0, + utils::div_up( + pad_r - (jcp.kw - 1 - ki) * (jcp.dilate_w + 1), + jcp.stride_w)); + } + + inline bool is_src_layout_nxc() { + return utils::one_of(jcp.src_tag, format_tag::ndhwc, format_tag::nhwc, + format_tag::nwc); + } + inline bool is_dst_layout_nxc() { + return utils::one_of(jcp.dst_tag, format_tag::ndhwc, format_tag::nhwc, + format_tag::nwc); + } + + std::unique_ptr> + postops_injector_; + + void generate() override; +}; + +template +struct jit_uni_dw_conv_bwd_data_kernel_f32 : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_uni_dw_conv_bwd_data_kernel_f32) + + jit_uni_dw_conv_bwd_data_kernel_f32(const jit_conv_conf_t &ajcp) + : jit_generator(jit_name()), jcp(ajcp) {} + jit_conv_conf_t jcp; + +private: + using Vmm = typename utils::conditional3::type; + const int reg_repeats_ = (isa == sse41) ? 2 : 1; + const int simd_w_ = cpu_isa_traits::vlen / sizeof(float); + using reg64_t = const Xbyak::Reg64; + + inline Vmm get_ker_reg(int idx) { return Vmm(idx + 0); } + inline Vmm get_ddst_reg(int idx) { return Vmm(idx + 1); } + inline Vmm get_acc_reg(int idx) { return Vmm(idx + 4); } + + reg64_t reg_ddst = rax; + reg64_t aux_reg_ddst = r8; + reg64_t aux1_reg_ddst = abi_not_param1; + reg64_t reg_kernel = rdx; + reg64_t aux_reg_kernel = r10; + reg64_t aux1_reg_kernel = rbp; + reg64_t reg_dsrc = rsi; + + reg64_t reg_ur_str_w = r9; + reg64_t reg_ch_blocks = rbx; + + reg64_t iter_kh = r11; + reg64_t iter_kw = r12; + reg64_t reg_kh = r13; + reg64_t reg_kw = r14; + + reg64_t aux_reg_ch_blocks = r15; + reg64_t reg_tmp = r15; + Xbyak::Opmask k_ch_tail_mask = Xbyak::Opmask(1); + + void load_vmm(Vmm &vmm, const Xbyak::Address &addr, bool tail); + void store_vmm(Vmm &vmm, const Xbyak::Address &addr, bool tail); + + inline void ch_loop_body(int ur_ch_blocks, int unroll_w); + inline void unroll_width_body(int ur_ch_blocks); + inline void load_ddst(int ur_ch_blocks, int ur_str_w); + inline void apply_filter(int ur_ch_blocks, int ur_str_w, bool is_last_ch); + inline void store_dsrc(int ur_ch_blocks, int ur_str_w, bool is_last_ch); + + void generate() override; + + inline bool tail_simd_overlap(int reg_repeat) { + return reg_repeat * simd_w_ >= jcp.ch_tail; + } + + inline bool is_dsrc_layout_nxc() { + return utils::one_of(jcp.src_tag, format_tag::ndhwc, format_tag::nhwc, + format_tag::nwc); + } + inline bool is_ddst_layout_nxc() { + return utils::one_of(jcp.dst_tag, format_tag::ndhwc, format_tag::nhwc, + format_tag::nwc); + } +}; + +template +struct jit_uni_dw_conv_bwd_weights_kernel_f32 : public jit_generator { + + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_uni_dw_conv_bwd_weights_kernel_f32) + + jit_uni_dw_conv_bwd_weights_kernel_f32(const jit_conv_conf_t &ajcp) + : jit_generator(jit_name()), jcp(ajcp) {} + + jit_conv_conf_t jcp; + +private: + using Vmm = typename utils::conditional3::type; + + const int simd_w_ = cpu_isa_traits::vlen / sizeof(float); + const int reg_repeats_ = (isa == sse41) ? 2 : 1; + const int req_aux_vmm = isa == sse41 ? 1 : 0; // used for FMA operand + + const int max_unroll_w_ = 30; + const int block_size_ = 15; + + const Xbyak::AddressFrame &vmmword = (isa == sse41) ? xword + : (isa == avx2) ? yword + : zword; + + /* Offset between input and accummulators is 3, therefore, assume 'kw' + * is no larger than 3*/ + inline Vmm get_bias_reg(int idx = 0) { return Vmm(idx); } + inline Vmm get_output_reg(int idx) { + int vmm_idx = jcp.is_fast_depthwise + ? idx + 2 * jcp.kw * jcp.nb_ch_blocking + : idx + req_aux_vmm; + return Vmm(vmm_idx); + } + inline Vmm get_input_reg(int idx) { + int vmm_idx = jcp.is_fast_depthwise + ? idx + jcp.kw * jcp.nb_ch_blocking + : idx + 4 * reg_repeats_ + req_aux_vmm; + return Vmm(vmm_idx); + } + inline Vmm get_acc_reg(int idx) { + int vmm_idx = jcp.is_fast_depthwise + ? idx + : idx + 1 * reg_repeats_ + req_aux_vmm; + return Vmm(vmm_idx); + } + inline Vmm get_aux_reg() { return Vmm(0); } + + using reg64_t = const Xbyak::Reg64; + reg64_t reg_tmp_input = r9; + reg64_t reg_tmp_output = r10; + reg64_t reg_tmp_filter = r13; + reg64_t reg_kh_offset = rax; + + /* parameter passed by driver into kernel */ + Xbyak::Reg8 reg_exec_flags = bl; + + reg64_t reg_oh_worksize = r14; + reg64_t reg_oh = rax; + + reg64_t reg_iter_ow_blk = r11; + + reg64_t reg_kh_aux = rsi; + reg64_t reg_kh = rdx; + + /* Base addresses for convolution parameters. */ + reg64_t reg_input_baddr = r15; + reg64_t reg_output_baddr = r12; + reg64_t reg_filter_baddr = abi_not_param1; + reg64_t reg_bias_baddr = r13; + + reg64_t reg_tmp = r8; + + Xbyak::Opmask k_ch_tail_mask = Xbyak::Opmask(1); + + void addps_xmm(Vmm &vmm_dst, Vmm &vmm_src, const Xbyak::Address &addr, + bool compute_tail); + void load_xmm( + Vmm &vmm, const Xbyak::Address &addr, bool compute_tail = false); + void store_xmm( + Vmm &vmm, const Xbyak::Address &addr, bool compute_tail = false); + + void dispatch_ow_step_unroll(int unroll_w, int l_pad, int pad_offset, + int ow_block, int nb_ch_blocking, bool is_last_ch); + + /* Micro-kernel JIT'ing, fusing 'kw' and 'ow_block' loops into unrolled FMAs + */ + void compute_unroll_ow_step(int unroll_w, int l_pad, int pad_offset, + int ow_block, bool is_last_ch); + + /* Micro-kernel JIT'ing, fusing 'kw', 'ow_block' and 'nb_ch_blocking' loops + * into unrolled FMAs. */ + void compute_unroll_ow_step_nxc(int unroll_w, int l_pad, int pad_offset, + int ow_block, int nb_ch_blocking, bool is_last_ch); + + /* JIT'ing the outer loops for the micro-kernel -> {kh, oh_block} */ + void compute_kh_step(int unroll_w, int l_pad, int pad_offset, int ow_block, + int nb_ch_blocking, bool is_last_ch); + /* Channel loop for 'nxc' format */ + void compute_ch_loop(int unroll_w, int l_pad, int pad_offset, int ow_block); + void compute_h_loop(int unroll_w, int l_pad, int pad_offset, int ow_block); + + /* Write 'width' micro-kernel JITs; depending on the padding and convolution + * size, write a micro-kernel for the left ow-block, middle ow-block(s), and + * right ow-block.*/ + void compute_ow_block_unroll(); + + void deploy_zero_filter(); + void zero_filter_ch_loop(); + void zero_filter_kh_loop(int nb_ch_blocking = 1); + void load_filter(int nb_ch_blocking, bool is_last_ch = false); + void zero_filter(); + void load_bias(int nb_ch_blocking, bool is_last_ch); + void zero_bias(); + void compute_bias_step_unroll( + const int unroll_w, int nb_ch_blocking, bool is_last_ch); + void compute_ch_loop_bias(bool do_load_bias); + void deploy_ch_loop_bias(); + void compute_single_ch_block_bias(); + void compute_spatial_loop_bias(int nb_ch_blocking, bool is_last_ch); + void store_filter(int nb_ch_blocking, bool is_last_ch = false); + void store_bias(int nb_ch_blocking, bool is_last_ch); + void compute_bias(); + void calculate_w_unrolling( + int &unroll_trips, int &unroll_w, int &unroll_w_tail); + + void generate() override; + + inline bool is_layout_nxc() { + return utils::everyone_is( + true, is_src_layout_nxc(), is_ddst_layout_nxc()); + } + inline bool is_src_layout_nxc() { + return utils::one_of(jcp.src_tag, format_tag::ndhwc, format_tag::nhwc, + format_tag::nwc); + } + inline bool is_ddst_layout_nxc() { + return utils::one_of(jcp.dst_tag, format_tag::ndhwc, format_tag::nhwc, + format_tag::nwc); + } +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_dw_conv_kernel_utils.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_dw_conv_kernel_utils.hpp new file mode 100644 index 0000000000000000000000000000000000000000..c6b51d22f8b38a7f82a5b73b2a171d89d2afefed --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_dw_conv_kernel_utils.hpp @@ -0,0 +1,145 @@ +/******************************************************************************* +* Copyright 2019-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_UNI_DW_CONV_KERNEL_UTILS_HPP +#define CPU_X64_JIT_UNI_DW_CONV_KERNEL_UTILS_HPP + +#include "common/c_types_map.hpp" +#include "common/memory_tracking.hpp" +#include "common/nstl.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/x64/jit_generator.hpp" +#include "cpu/x64/jit_primitive_conf.hpp" + +#include "cpu/x64/jit_avx512_core_bf16_dw_conv_kernel.hpp" +#include "cpu/x64/jit_uni_dw_conv_kernel_f32.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +template +struct jit_uni_dw_conv_fwd_kernel { + + jit_uni_dw_conv_fwd_kernel( + const jit_conv_conf_t &ajcp, const memory_desc_t &dst_md) { + ker_ = new jit_kernel_t(ajcp, dst_md); + } + + status_t create_kernel() { + if (ker_) return ker_->create_kernel(); + return status::out_of_memory; + } + ~jit_uni_dw_conv_fwd_kernel() { delete ker_; } + + static status_t init_conf(jit_conv_conf_t &jcp, + const convolution_desc_t &cd, memory_desc_t &src_md, + memory_desc_t &weights_md, memory_desc_t &bias_md, + memory_desc_t &dst_md, primitive_attr_t &attr); + + static void init_scratchpad(memory_tracking::registrar_t &scratchpad, + const jit_conv_conf_t &jcp); + + jit_generator *ker() const { return ker_; } + void operator()(const jit_conv_call_s *p) const { (*ker_)(p); } + +private: + constexpr static bool ker_condition_ + = isa == avx512_core && kernel_dt == data_type::bf16; + using jit_kernel_t = typename utils::conditional>::type; + jit_kernel_t *ker_; +}; + +template +struct jit_uni_dw_conv_bwd_data_kernel { + + jit_uni_dw_conv_bwd_data_kernel(const jit_conv_conf_t &ajcp) + : ker_(nullptr) { + ker_ = new jit_kernel_t(ajcp); + } + + status_t create_kernel() { + if (ker_) return ker_->create_kernel(); + return status::out_of_memory; + } + ~jit_uni_dw_conv_bwd_data_kernel() { delete ker_; } + + static status_t init_conf(jit_conv_conf_t &jcp, + const convolution_desc_t &cd, memory_desc_t &diff_src_md, + memory_desc_t &weights_md, memory_desc_t &diff_dst_md); + + static void init_scratchpad(memory_tracking::registrar_t &scratchpad, + const jit_conv_conf_t &jcp); + + void operator()(const jit_conv_call_s *p) const { (*ker_)(p); } + +private: + using jit_kernel_t = typename utils::conditional>::type; + jit_kernel_t *ker_; + + DNNL_DISALLOW_COPY_AND_ASSIGN(jit_uni_dw_conv_bwd_data_kernel); +}; + +template +struct jit_uni_dw_conv_bwd_weights_kernel { + + jit_uni_dw_conv_bwd_weights_kernel(const jit_conv_conf_t &ajcp) + : ker_(nullptr) { + ker_ = new jit_kernel_t(ajcp); + } + + status_t create_kernel() { + if (ker_) return ker_->create_kernel(); + return status::out_of_memory; + } + + ~jit_uni_dw_conv_bwd_weights_kernel() { delete ker_; } + + static status_t init_conf(jit_conv_conf_t &jcp, + const convolution_desc_t &cd, memory_desc_t &src_md, + memory_desc_t &diff_weights_md, memory_desc_t &diff_bias_md, + memory_desc_t &diff_dst_md, int nthreads); + + static void init_scratchpad(memory_tracking::registrar_t &scratchpad, + const jit_conv_conf_t &jcp); + + static void partition_nthr_nxc( + jit_conv_conf_t &jcp, int nthreads, bool prioritize_threading); + static void balance(jit_conv_conf_t &jcp, int nthreads); + + void operator()(const jit_dw_conv_call_s *p) const { (*ker_)(p); } + +private: + using jit_kernel_t = typename utils::conditional>::type; + jit_kernel_t *ker_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl +#endif /* CPU_X64_JIT_UNI_DW_CONV_KERNEL_UTILS_HPP */ diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_dw_convolution.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_dw_convolution.hpp new file mode 100644 index 0000000000000000000000000000000000000000..a7ca1d965d6ad68a4170d070db4805ea17566165 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_dw_convolution.hpp @@ -0,0 +1,279 @@ +/******************************************************************************* +* Copyright 2019-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_UNI_DW_CONVOLUTION_HPP +#define CPU_X64_JIT_UNI_DW_CONVOLUTION_HPP + +#include "common/c_types_map.hpp" +#include "common/memory_tracking.hpp" +#include "common/primitive.hpp" + +#include "cpu/cpu_convolution_pd.hpp" +#include "cpu/x64/cpu_barrier.hpp" +#include "cpu/x64/cpu_reducer.hpp" + +#include "cpu/x64/jit_uni_dw_conv_kernel_utils.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +template +struct jit_uni_dw_convolution_fwd_t : public primitive_t { + struct pd_t : public cpu_convolution_fwd_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const typename pd_t::base_class *hint_fwd_pd) + : cpu_convolution_fwd_pd_t(adesc, attr, hint_fwd_pd), jcp_() {} + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit_dw:", jcp_.isa, ""), + jit_uni_dw_convolution_fwd_t); + + status_t init(engine_t *engine) { + bool ok = true && is_fwd() + && set_default_alg_kind(alg_kind::convolution_direct) + && expect_data_types(src_type, src_type, data_type::undef, + dst_type, data_type::f32) + && IMPLICATION(this->with_bias(), + utils::one_of(this->desc()->bias_desc.data_type, + data_type::f32, data_type::bf16)) + && attr()->has_default_values( + primitive_attr_t::skip_mask_t::post_ops, dst_type) + && !has_zero_dim_memory(); + if (!ok) return status::unimplemented; + + auto status = jit_uni_dw_conv_fwd_kernel::init_conf( + jcp_, *desc(), src_md_, weights_md_, bias_md_, dst_md_, + attr_); + if (status != status::success) return status::unimplemented; + + auto scratchpad = scratchpad_registry().registrar(); + jit_uni_dw_conv_fwd_kernel::init_scratchpad( + scratchpad, jcp_); + + return status::success; + } + + jit_conv_conf_t jcp_; + }; + + jit_uni_dw_convolution_fwd_t(const pd_t *apd) : primitive_t(apd) {} + + typedef typename prec_traits::type f32_data_t; + typedef typename prec_traits::type bf16_data_t; + typedef typename prec_traits::type data_t; + typedef typename prec_traits::type dst_data_t; + + status_t init(engine_t *engine) override { + CHECK(safe_ptr_assign(kernel_, + new jit_uni_dw_conv_fwd_kernel( + pd()->jcp_, *pd()->dst_md(0)))); + return kernel_->create_kernel(); + } + + status_t execute(const exec_ctx_t &ctx) const override { + execute_forward(ctx); + return status::success; + } + +private: + void execute_forward(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr> kernel_; +}; + +using jit_avx512_common_dw_convolution_fwd_t + = jit_uni_dw_convolution_fwd_t; +using jit_avx2_dw_convolution_fwd_t + = jit_uni_dw_convolution_fwd_t; +using jit_sse41_dw_convolution_fwd_t + = jit_uni_dw_convolution_fwd_t; + +template +struct jit_uni_dw_convolution_bwd_data_t : public primitive_t { + struct pd_t : public cpu_convolution_bwd_data_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const convolution_fwd_pd_t *hint_fwd_pd) + : cpu_convolution_bwd_data_pd_t(adesc, attr, hint_fwd_pd), jcp_() {} + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit_dw:", jcp_.isa, ""), + jit_uni_dw_convolution_bwd_data_t); + + status_t init(engine_t *engine) { + bool ok = true && desc()->prop_kind == prop_kind::backward_data + && set_default_alg_kind(alg_kind::convolution_direct) + && expect_data_types(diff_src_type, diff_dst_type, + data_type::undef, diff_dst_type, data_type::f32) + && attr()->has_default_values() && !has_zero_dim_memory(); + + if (!ok) return status::unimplemented; + + status_t status = jit_uni_dw_conv_bwd_data_kernel::init_conf(jcp_, *desc(), diff_src_md_, + weights_md_, diff_dst_md_); + if (status != status::success) return status; + + auto scratchpad = scratchpad_registry().registrar(); + jit_uni_dw_conv_bwd_data_kernel::init_scratchpad(scratchpad, jcp_); + + return status::success; + } + + jit_conv_conf_t jcp_; + }; + + jit_uni_dw_convolution_bwd_data_t(const pd_t *apd) : primitive_t(apd) {} + + typedef typename prec_traits::type diff_src_data_t; + typedef typename prec_traits::type diff_dst_data_t; + typedef typename prec_traits::type wei_data_t; + + status_t init(engine_t *engine) override { + CHECK(safe_ptr_assign(kernel_, + new jit_uni_dw_conv_bwd_data_kernel( + pd()->jcp_))); + return kernel_->create_kernel(); + } + + status_t execute(const exec_ctx_t &ctx) const override { + execute_backward_data(ctx); + return status::success; + } + +private: + void execute_backward_data(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr> + kernel_; +}; + +using jit_avx512_common_dw_convolution_bwd_data_t + = jit_uni_dw_convolution_bwd_data_t; +using jit_avx2_dw_convolution_bwd_data_t + = jit_uni_dw_convolution_bwd_data_t; +using jit_sse41_dw_convolution_bwd_data_t + = jit_uni_dw_convolution_bwd_data_t; + +template +struct jit_uni_dw_convolution_bwd_weights_t : public primitive_t { + struct pd_t : public cpu_convolution_bwd_weights_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const convolution_fwd_pd_t *hint_fwd_pd) + : cpu_convolution_bwd_weights_pd_t(adesc, attr, hint_fwd_pd) + , jcp_() {} + using jit_uni_dw_convolution_bwd_weights + = jit_uni_dw_convolution_bwd_weights_t; + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit_dw:", jcp_.isa, ""), + jit_uni_dw_convolution_bwd_weights); + + status_t init(engine_t *engine) { + bool ok = true && desc()->prop_kind == prop_kind::backward_weights + && set_default_alg_kind(alg_kind::convolution_direct) + && expect_data_types(src_type, diff_weights_type, + data_type::undef, src_type, data_type::f32) + && IMPLICATION(this->with_bias(), + utils::one_of( + this->desc()->diff_bias_desc.data_type, + data_type::f32, data_type::bf16)) + && attr()->has_default_values() && !has_zero_dim_memory(); + if (!ok) return status::unimplemented; + + const int max_threads + = dnnl_in_parallel() ? 1 : dnnl_get_max_threads(); + + status_t status = jit_uni_dw_conv_bwd_weights_kernel::init_conf(jcp_, *desc(), src_md_, + diff_weights_md_, diff_bias_md_, diff_dst_md_, max_threads); + if (status != status::success) return status; + + auto scratchpad = scratchpad_registry().registrar(); + jit_uni_dw_conv_bwd_weights_kernel::init_scratchpad( + scratchpad, jcp_); + + return status::success; + } + + jit_conv_conf_t jcp_; + }; + jit_uni_dw_convolution_bwd_weights_t(const pd_t *apd); + + typedef typename prec_traits::type f32_data_t; + typedef typename prec_traits::type bf16_data_t; + typedef typename prec_traits::type src_data_t; + typedef typename prec_traits::type diff_dst_data_t; + typedef typename prec_traits::type diff_weights_data_t; + + status_t init(engine_t *engine) override { + CHECK(safe_ptr_assign(kernel_, + new jit_uni_dw_conv_bwd_weights_kernel( + pd()->jcp_))); + CHECK(kernel_->create_kernel()); + + const auto jcp = &pd()->jcp_; + const int reduction = jcp->nthr_mb * jcp->nthr_oh; + if (reduction > 1 && isa != sse41) { + CHECK(safe_ptr_assign( + acc_ker_, new cpu_accumulator_1d_t())); + CHECK(acc_ker_->create_kernel()); + } + return status::success; + } + + status_t execute(const exec_ctx_t &ctx) const override { + switch (pd()->jcp_.harness) { + case harness_nxc: + execute_backward_weights_nxc(ctx); + execute_reduction_nxc(ctx); + break; + case harness_mb_reduction: + execute_backward_weights(ctx); + execute_reduction(ctx); + break; + default: assert(!"Invalid harness type"); + } + return status::success; + } + +private: + void execute_backward_weights(const exec_ctx_t &ctx) const; + void execute_reduction(const exec_ctx_t &ctx) const; + void execute_backward_weights_nxc(const exec_ctx_t &ctx) const; + void execute_reduction_nxc(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr> acc_ker_; + std::unique_ptr> kernel_; +}; + +using jit_avx512_common_dw_convolution_bwd_weights_t + = jit_uni_dw_convolution_bwd_weights_t; +using jit_avx2_dw_convolution_bwd_weights_t + = jit_uni_dw_convolution_bwd_weights_t; +using jit_sse41_dw_convolution_bwd_weights_t + = jit_uni_dw_convolution_bwd_weights_t; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_eltwise.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_eltwise.hpp new file mode 100644 index 0000000000000000000000000000000000000000..b06de783f47d9b8dd7eb09f05e599c9d26ded1eb --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_eltwise.hpp @@ -0,0 +1,103 @@ +/******************************************************************************* +* Copyright 2017-2020 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_UNI_ELTWISE_HPP +#define CPU_X64_JIT_UNI_ELTWISE_HPP + +#include + +#include "common/c_types_map.hpp" +#include "common/primitive.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_eltwise_pd.hpp" + +#include "cpu/x64/cpu_isa_traits.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +struct jit_uni_eltwise_kernel; + +template +struct jit_uni_eltwise_fwd_t : public primitive_t { + struct pd_t : public cpu_eltwise_fwd_pd_t { + using cpu_eltwise_fwd_pd_t::cpu_eltwise_fwd_pd_t; + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit:", + ((d_type == data_type::bf16) + && mayiuse(avx512_core_bf16)) + ? avx512_core_bf16 + : isa, + ""), + jit_uni_eltwise_fwd_t); + + status_t init(engine_t *engine); + }; + + jit_uni_eltwise_fwd_t(const pd_t *apd); + virtual ~jit_uni_eltwise_fwd_t(); + + typedef typename prec_traits::type data_t; + + status_t init(engine_t *engine) override; + + status_t execute(const exec_ctx_t &ctx) const override; + +private: + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + std::unique_ptr kernel_; +}; + +template +struct jit_uni_eltwise_bwd_t : public primitive_t { + struct pd_t : public cpu_eltwise_bwd_pd_t { + using cpu_eltwise_bwd_pd_t::cpu_eltwise_bwd_pd_t; + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit:", + ((d_type == data_type::bf16) + && mayiuse(avx512_core_bf16)) + ? avx512_core_bf16 + : isa, + ""), + jit_uni_eltwise_bwd_t); + + status_t init(engine_t *engine); + }; + + jit_uni_eltwise_bwd_t(const pd_t *apd); + virtual ~jit_uni_eltwise_bwd_t(); + + typedef typename prec_traits::type data_t; + + status_t init(engine_t *engine) override; + + status_t execute(const exec_ctx_t &ctx) const override; + +private: + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + std::unique_ptr kernel_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_eltwise_int.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_eltwise_int.hpp new file mode 100644 index 0000000000000000000000000000000000000000..58e442d836ad841717cfe150e75f47639302a4eb --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_eltwise_int.hpp @@ -0,0 +1,71 @@ +/******************************************************************************* +* Copyright 2020-2021 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_UNI_ELTWISE_INT_HPP +#define CPU_X64_JIT_UNI_ELTWISE_INT_HPP + +#include + +#include "common/c_types_map.hpp" +#include "common/primitive.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_eltwise_pd.hpp" + +#include "cpu/x64/cpu_isa_traits.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +struct jit_uni_eltwise_int_kernel; + +template +struct jit_uni_eltwise_int_fwd_t : public primitive_t { + struct pd_t : public cpu_eltwise_fwd_pd_t { + using cpu_eltwise_fwd_pd_t::cpu_eltwise_fwd_pd_t; + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit_int8:", isa, ""), + jit_uni_eltwise_int_fwd_t); + + status_t init(engine_t *engine); + }; + + jit_uni_eltwise_int_fwd_t(const pd_t *apd); + ~jit_uni_eltwise_int_fwd_t(); + + typedef typename prec_traits::type data_t; + + status_t init(engine_t *engine) override; + + status_t execute(const exec_ctx_t &ctx) const override { + return execute_forward(ctx); + } + +private: + status_t execute_forward(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + jit_uni_eltwise_int_kernel *kernel_ = nullptr; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_i8i8_pooling.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_i8i8_pooling.hpp new file mode 100644 index 0000000000000000000000000000000000000000..8c11ca4974d4b70616d3b3680f77e9fd0269c6e0 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_i8i8_pooling.hpp @@ -0,0 +1,100 @@ +/******************************************************************************* +* Copyright 2017-2021 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_UNI_I8I8_POOLING_HPP +#define CPU_X64_JIT_UNI_I8I8_POOLING_HPP + +#include "common/c_types_map.hpp" +#include "common/primitive.hpp" +#include "common/type_helpers.hpp" + +#include "cpu/cpu_pooling_pd.hpp" + +#include "cpu/x64/cpu_isa_traits.hpp" +#include "cpu/x64/jit_primitive_conf.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +template +struct jit_uni_i8i8_pooling_fwd_ker_t; + +template +struct jit_uni_i8i8_pooling_fwd_t : public primitive_t { + struct pd_t : public cpu_pooling_fwd_pd_t { + using cpu_pooling_fwd_pd_t::cpu_pooling_fwd_pd_t; + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit_int:", isa, ""), + jit_uni_i8i8_pooling_fwd_t); + + status_t init(engine_t *engine) { + using namespace format_tag; + bool ok = mayiuse(isa) && utils::one_of(ndims(), 3, 4, 5) + && desc()->prop_kind == prop_kind::forward_inference + && utils::one_of(desc()->alg_kind, alg_kind::pooling_max, + alg_kind::pooling_avg_include_padding, + alg_kind::pooling_avg_exclude_padding) + && utils::one_of(src_md()->data_type, data_type::s32, + data_type::s8, data_type::u8) + && src_md()->data_type == dst_md()->data_type + && !is_dilated() + && attr()->has_default_values( + primitive_attr_t::skip_mask_t::post_ops) + && set_default_params() == status::success + && memory_desc_matches_one_of_tag( + *src_md(), nwc, nhwc, ndhwc) + != format_tag::undef + && memory_desc_matches_one_of_tag( + *dst_md(), nwc, nhwc, ndhwc) + != format_tag::undef + && attr_.set_default_formats(dst_md(0)) == status::success; + if (!ok) return status::unimplemented; + + CHECK(jit_conf()); + + return status::success; + } + + jit_pool_conf_t jpp_; + + protected: + status_t jit_conf(); + }; + + jit_uni_i8i8_pooling_fwd_t(const pd_t *apd); + ~jit_uni_i8i8_pooling_fwd_t(); + + status_t init(engine_t *engine) override; + + status_t execute(const exec_ctx_t &ctx) const override { + return execute_forward(ctx); + } + +private: + status_t execute_forward(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr> ker_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_layer_normalization.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_layer_normalization.hpp new file mode 100644 index 0000000000000000000000000000000000000000..540b5b93bead8dff15fcafb96420b33910909e50 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_layer_normalization.hpp @@ -0,0 +1,364 @@ +/******************************************************************************* +* Copyright 2019-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_UNI_LAYER_NORMALIZATION_HPP +#define CPU_X64_JIT_UNI_LAYER_NORMALIZATION_HPP + +#include + +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/memory_tracking.hpp" +#include "common/primitive.hpp" +#include "common/reorder.hpp" +#include "common/stream.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_layer_normalization_pd.hpp" + +#include "cpu/x64/cpu_isa_traits.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +struct stat_and_data_kernel_t { + static stat_and_data_kernel_t *create(const layer_normalization_pd_t *pd); + virtual ~stat_and_data_kernel_t() = default; + + virtual void operator()(const void *src, void *dst, const float *scale, + const float *shift, float *mean, float *var, + const float *src_scales, const float *dst_scales, + const size_t block_size) const {}; + + virtual status_t create_kernel() { return status::success; } + +protected: + stat_and_data_kernel_t(const layer_normalization_pd_t *pd) : pd_(pd) {} + + const layer_normalization_pd_t *pd_; +}; + +struct diff_ss_kernel_t { + static diff_ss_kernel_t *create(const layer_normalization_pd_t *pd); + virtual ~diff_ss_kernel_t() = default; + + virtual void operator()(const void *src, const void *diff_dst, + float *diff_gamma, float *diff_beta, const float *mean, + const float *var, float *const inv_sqrtvar, + const size_t block_size) const {}; + + virtual status_t create_kernel() { return status::success; } + +protected: + diff_ss_kernel_t(const layer_normalization_pd_t *pd) : pd_(pd) {} + + const layer_normalization_pd_t *pd_; +}; + +struct diff_data_kernel_t { + static diff_data_kernel_t *create(const layer_normalization_pd_t *pd); + virtual ~diff_data_kernel_t() = default; + + virtual void operator()(const void *src, const void *diff_dst, + void *diff_src, const float *ss, const float *mean, + float *const inv_sqrtvar, const size_t block_size) const {}; + + virtual status_t create_kernel() { return status::success; } + +protected: + diff_data_kernel_t(const layer_normalization_pd_t *pd) : pd_(pd) {} + + const layer_normalization_pd_t *pd_; +}; + +struct jit_uni_layer_normalization_fwd_t : public primitive_t { + struct pd_t : public cpu_layer_normalization_fwd_pd_t { + using cpu_layer_normalization_fwd_pd_t:: + cpu_layer_normalization_fwd_pd_t; + + DECLARE_COMMON_PD_T("jit:uni", jit_uni_layer_normalization_fwd_t); + + status_t init(engine_t *engine) { + using namespace data_type; + using skip_mask_t = primitive_attr_t::skip_mask_t; + const memory_desc_wrapper src_d(src_md()); + + const bool ok = is_fwd() && !has_zero_dim_memory() + && utils::one_of( + src_md()->data_type, f32, bf16, f16, s8, u8) + && utils::one_of( + dst_md()->data_type, f32, bf16, f16, s8, u8) + && IMPLICATION(utils::one_of(bf16, src_md()->data_type, + dst_md()->data_type), + mayiuse(avx512_core) || mayiuse(avx2_vnni_2)) + && IMPLICATION(utils::one_of(f16, src_md()->data_type, + dst_md()->data_type), + mayiuse(avx512_core_fp16) || mayiuse(avx2_vnni_2)) + && stat_md()->data_type == f32 + && check_scale_shift_data_type() + && attr()->has_default_values(skip_mask_t::scales_runtime) + && attr_scales_ok() && set_default_formats_common() + && src_d.is_blocking_desc() + // plain format, last logical dim is last physical + && src_d.blocking_desc().strides[ndims() - 1] == 1; + if (!ok) return status::unimplemented; + + CHECK(fill_compatible_stats_md(*src_md(), reordered_stat_md_)); + + if (reordered_stat_md_ != *stat_md() && !stats_are_tmp()) { + CHECK(reorder_primitive_desc_create(reorder_pd_, engine, + stats_are_src() ? stat_md() : &reordered_stat_md_, + stats_are_src() ? &reordered_stat_md_ : stat_md())); + } + + init_scratchpad(); + return status::success; + } + + bool use_tmp_stats() const { return reorder_pd_ || stats_are_tmp(); } + + std::shared_ptr reorder_pd_; + memory_desc_t reordered_stat_md_; + + private: + void init_scratchpad() { + using namespace memory_tracking::names; + auto scratchpad = scratchpad_registry().registrar(); + if (use_tmp_stats()) { + scratchpad.template book( + key_lnorm_tmp_mean, across_axis()); + scratchpad.template book( + key_lnorm_tmp_var, across_axis()); + } + if (reordered_stat_md_ != *stat_md() && !stats_are_tmp()) { + scratchpad.book(key_nested, reorder_pd_->scratchpad_registry()); + } + } + }; + + status_t init(engine_t *engine) override { + if (pd()->reorder_pd_) + pd()->reorder_pd_->create_primitive(reorder_, engine); + CHECK(safe_ptr_assign( + stat_and_data_kernel_, stat_and_data_kernel_t::create(pd()))); + if (stat_and_data_kernel_) + CHECK(stat_and_data_kernel_->create_kernel()); + return status::success; + } + + jit_uni_layer_normalization_fwd_t(const pd_t *apd) : primitive_t(apd) {} + virtual ~jit_uni_layer_normalization_fwd_t() = default; + + void reorder_stat(const exec_ctx_t &ctx, engine_t *engine, + const memory_arg_t &in, const memory_arg_t &out) const { + using namespace memory_tracking::names; + exec_args_t r_args; + r_args[DNNL_ARG_SRC] = in; + r_args[DNNL_ARG_DST] = out; + exec_ctx_t r_ctx(ctx, std::move(r_args)); + + nested_scratchpad_t ns(ctx, key_nested, reorder_); + r_ctx.set_scratchpad_grantor(ns.grantor()); + reorder_->execute(r_ctx); + } + + status_t execute(const exec_ctx_t &ctx) const override { + /* LN supports arbitrary layout for input/output statistics. + * For best performance we compute LN with statistics in the same format + * as data tensor (i.e. data in abcd, stats in abc) and user's + * input/output statistics are reordered if necessary */ + using namespace memory_tracking::names; + engine_t *engine = ctx.stream()->engine(); + auto scratchpad = ctx.get_scratchpad_grantor(); + auto mean_mem = scratchpad.get_memory_storage(key_lnorm_tmp_mean); + auto variance_mem = scratchpad.get_memory_storage(key_lnorm_tmp_var); + memory_t mean(engine, &(pd()->reordered_stat_md_), std::move(mean_mem)); + memory_t variance( + engine, &(pd()->reordered_stat_md_), std::move(variance_mem)); + + // reorder input stats + if (pd()->stats_are_src() && reorder_) { + reorder_stat( + ctx, engine, ctx.args().at(DNNL_ARG_MEAN), {&mean, false}); + reorder_stat(ctx, engine, ctx.args().at(DNNL_ARG_VARIANCE), + {&variance, false}); + } + status_t status = execute_forward(ctx); + if (status != status::success) return status; + // reorder output stats + if (!pd()->stats_are_src() && reorder_) { + reorder_stat( + ctx, engine, {&mean, true}, ctx.args().at(DNNL_ARG_MEAN)); + reorder_stat(ctx, engine, {&variance, true}, + ctx.args().at(DNNL_ARG_VARIANCE)); + } + + return status::success; + } + +private: + status_t execute_forward(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr stat_and_data_kernel_; + std::shared_ptr reorder_; +}; + +struct jit_uni_layer_normalization_bwd_t : public primitive_t { + struct pd_t : public cpu_layer_normalization_bwd_pd_t { + using cpu_layer_normalization_bwd_pd_t:: + cpu_layer_normalization_bwd_pd_t; + + DECLARE_COMMON_PD_T("jit:uni", jit_uni_layer_normalization_bwd_t); + + status_t init(engine_t *engine) { + using namespace data_type; + const memory_desc_wrapper src_d(src_md()); + + const bool ok = !is_fwd() && !has_zero_dim_memory() + && mayiuse(avx2) // sse41 is not supported yet + && utils::one_of(src_md()->data_type, f32, bf16, f16) + && utils::one_of(diff_dst_md()->data_type, f32, bf16, f16) + && utils::one_of(diff_src_md()->data_type, f32, bf16, f16) + && IMPLICATION(utils::one_of(bf16, src_md()->data_type, + diff_dst_md()->data_type, + diff_src_md()->data_type), + mayiuse(avx512_core)) + && IMPLICATION(utils::one_of(f16, src_md()->data_type, + diff_dst_md()->data_type, + diff_src_md()->data_type), + mayiuse(avx512_core_fp16)) + && stat_md()->data_type == f32 + && check_scale_shift_data_type() + && attr()->has_default_values() + && set_default_formats_common() + && src_d.is_blocking_desc() + // plain format, last logical dim is last physical + && src_d.blocking_desc().strides[ndims() - 1] == 1; + if (!ok) return status::unimplemented; + + CHECK(fill_compatible_stats_md(*src_md(), reordered_stat_md_)); + + if (reordered_stat_md_ != *stat_md()) { + CHECK(reorder_primitive_desc_create( + reorder_pd_, engine, stat_md(), &reordered_stat_md_)); + } + + nthr_ = dnnl_get_max_threads(); + init_scratchpad(); + return status::success; + } + + bool use_tmp_stats() const { return reorder_pd_.get(); } + + std::shared_ptr reorder_pd_; + memory_desc_t reordered_stat_md_; + int nthr_; // To not exceed the limit in execute used for set up. + + private: + void init_scratchpad() { + using namespace memory_tracking::names; + auto scratchpad = scratchpad_registry().registrar(); + if (use_tmp_stats()) { + scratchpad.template book( + key_lnorm_tmp_mean, across_axis()); + scratchpad.template book( + key_lnorm_tmp_var, across_axis()); + } + scratchpad.template book( + key_lnorm_reduction, 2 * norm_axis() * nthr_); + scratchpad.template book( + key_lnorm_tmp_diff_ss, 2 * norm_axis()); + if (reordered_stat_md_ != *stat_md() && !stats_are_tmp()) { + scratchpad.book(key_nested, reorder_pd_->scratchpad_registry()); + } + scratchpad.template book( + key_lnorm_inv_sqrtvar, across_axis()); + } + }; + + status_t init(engine_t *engine) override { + if (pd()->reorder_pd_) + pd()->reorder_pd_->create_primitive(reorder_, engine); + CHECK(safe_ptr_assign(diff_ss_kernel_, diff_ss_kernel_t::create(pd()))); + CHECK(safe_ptr_assign( + diff_data_kernel_, diff_data_kernel_t::create(pd()))); + if (diff_ss_kernel_) CHECK(diff_ss_kernel_->create_kernel()); + if (diff_data_kernel_) CHECK(diff_data_kernel_->create_kernel()); + return status::success; + } + + jit_uni_layer_normalization_bwd_t(const pd_t *apd) : primitive_t(apd) {} + virtual ~jit_uni_layer_normalization_bwd_t() = default; + + void reorder_stat(const exec_ctx_t &ctx, engine_t *engine, + const memory_arg_t &in, const memory_arg_t &out) const { + using namespace memory_tracking::names; + exec_args_t r_args; + r_args[DNNL_ARG_SRC] = in; + r_args[DNNL_ARG_DST] = out; + exec_ctx_t r_ctx(ctx, std::move(r_args)); + + nested_scratchpad_t ns(ctx, key_nested, reorder_); + r_ctx.set_scratchpad_grantor(ns.grantor()); + reorder_->execute(r_ctx); + } + + status_t execute(const exec_ctx_t &ctx) const override { + using namespace memory_tracking::names; + /* LN supports arbitrary layout for input/output statistics. + * For best performance we compute LN with statistics in the same format + * as data tensor (i.e. data in abcd, stats in abc) and user's + * input/output statistics are reordered if necessary */ + + if (reorder_) { + engine_t *engine = ctx.stream()->engine(); + auto scratchpad = ctx.get_scratchpad_grantor(); + auto mean_mem = scratchpad.get_memory_storage(key_lnorm_tmp_mean); + auto variance_mem + = scratchpad.get_memory_storage(key_lnorm_tmp_var); + memory_t mean( + engine, &(pd()->reordered_stat_md_), std::move(mean_mem)); + memory_t variance(engine, &(pd()->reordered_stat_md_), + std::move(variance_mem)); + reorder_stat( + ctx, engine, ctx.args().at(DNNL_ARG_MEAN), {&mean, false}); + reorder_stat(ctx, engine, ctx.args().at(DNNL_ARG_VARIANCE), + {&variance, false}); + } + + return execute_backward(ctx); + } + +private: + status_t execute_backward(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr diff_ss_kernel_; + std::unique_ptr diff_data_kernel_; + std::shared_ptr reorder_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino^=l0,\:0,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_pool_kernel.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_pool_kernel.hpp new file mode 100644 index 0000000000000000000000000000000000000000..a5c349124da9e93e89a536b82b6cdc767b718d2f --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_pool_kernel.hpp @@ -0,0 +1,269 @@ +/******************************************************************************* +* Copyright 2017-2022 Intel Corporation +* Copyright 2018 YANDEX LLC +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_UNI_POOL_KERNEL_HPP +#define CPU_X64_JIT_UNI_POOL_KERNEL_HPP + +#include +#include +#include + +#include "common/memory_tracking.hpp" + +#include "cpu/x64/injectors/jit_uni_postops_injector.hpp" +#include "cpu/x64/jit_generator.hpp" +#include "cpu/x64/jit_primitive_conf.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +struct bf16_emulation_t; + +template +struct jit_uni_pool_kernel : public jit_generator { + + jit_uni_pool_kernel( + const jit_pool_conf_t &ajpp, const memory_desc_t *dst_md); + jit_pool_conf_t jpp; + ~jit_uni_pool_kernel(); + + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_uni_pool_kernel) + + static status_t init_conf(jit_pool_conf_t &jbp, + memory_tracking::registrar_t &scratchpad, primitive_attr_t &attr, + const pooling_pd_t *ppd); + +private: + using Xmm = Xbyak::Xmm; + using Ymm = Xbyak::Ymm; + using Zmm = Xbyak::Zmm; + using Opmask = Xbyak::Opmask; + using Reg32 = Xbyak::Reg32; + using Reg64 = Xbyak::Reg64; + + using Vmm = typename cpu_isa_traits::Vmm; + + int vmm_idx_upper_bound() const noexcept { + return is_superset(isa, avx512_core) ? 31 : 15; + } + + int reg_idx(int idx) const noexcept { return vmm_idx_upper_bound() - idx; } + + Xmm xreg(int idx) const noexcept { return Xmm(reg_idx(idx)); } + Ymm yreg(int idx) const noexcept { return Ymm(reg_idx(idx)); } + Zmm zreg(int idx) const noexcept { return Zmm(reg_idx(idx)); } + Vmm vreg(int idx) const noexcept { return Vmm(reg_idx(idx)); } + + const Xbyak::AddressFrame &vmmword = (isa == sse41) ? xword + : utils::one_of(isa, avx, avx2, avx2_vnni_2) ? yword + : zword; + + Xmm vmm_mask = Xmm(0); + Xmm xmm_tmp_1 = Xmm(0); + Ymm ymm_tmp_1 = Ymm(0); + Vmm vmm_tmp_1 = Vmm(0); + + // Used only for avx and if c tail is present + Vmm vmm_c_tail_mask = Vmm(2); + Xmm xmm_c_tail_mask = Xmm(2); + + Xmm xmm_tmp = Xmm(3); + + Vmm vmm_ker_area_h = Vmm(2); + Vmm vmm_one = Vmm(2); + Vmm vmm_tmp = Vmm(3); + Ymm ymm_tmp = Ymm(3); + + Vmm vmm_k_offset = Vmm(1); + + // Used only for avx512 when bf16 is present + inline Vmm vmm_idx() { + if (!jpp.is_backward) { + return (jpp.is_training) ? Vmm(4) : Vmm(1); + } else + return Vmm(4); + } + + Zmm bf16_emu_reserv_1 = Zmm(5); + Zmm bf16_emu_reserv_2 = Zmm(6); + Zmm bf16_emu_reserv_3 = Zmm(7); + Reg64 bf16_emu_reserv_4 = r11; + Zmm bf16_emu_reserv_5 = Zmm(8); + + Opmask k_c_tail_mask = Opmask(4); + Opmask k_mask_cvt = Opmask(5); + Opmask k_store_mask = Opmask(6); + + // Here be some (tame) dragons. This kernel does not follow the regular + // OS-agnostic ABI pattern because when isa is sse41 it uses maskmovdqu + // instruction which has its destination hardcoded in rdi. Therefore: + // - all registers are hardcoded + // - on Windows rdi and rcx are swapped to mimic the Unix x86_64 ABI + // + // While this is only required by the backward pass, the quirk above + // is applied to the forward pass as well to keep things simpler. + + using reg64_t = const Reg64; + reg64_t reg_param = rdi; // Always mimic the Unix ABI + reg64_t reg_input = r8; + reg64_t aux_reg_input = r9; + reg64_t reg_index = r10; + reg64_t reg_output = r12; + reg64_t reg_kd_pad_shift = r13; + reg64_t dst_ptr = rdi; // Must be rdi due to maskmovdqu + + reg64_t kj = r14; + reg64_t oi_iter = r15; + reg64_t reg_kh = rax; + reg64_t reg_k_shift = rbx; + reg64_t tmp_gpr = rcx; // Must be rcx because rdi is used above + reg64_t reg_ker_area_h = rdx; + reg64_t reg_nbc = rsi; + + reg64_t reg_zero_ptr = r9; + reg64_t reg_zero_id = r13; + reg64_t reg_zero_ih = r14; + reg64_t aux_reg_zero_ih = r15; + reg64_t ki = r12; + reg64_t aux_reg_input_d = r8; + + Reg32 reg_shuf_mask = esi; + + bool sse_high_half = false; + bool disable_postops_when_sse_high_half_processed_ = false; + + int prev_kw; + + void prepare_tail_mask(); + void put_one_in_vmm(); + void uni_broadcast_reg_val(const int reg_idx, const int vmm_idx); + void push_vmm_val(const int idx); + void pop_vmm_val(const int idx); + void load(const int idx, const reg64_t ®_ptr, const int offset, + const bool is_c_tail_proccessing); + void store(const int idx, const reg64_t ®_ptr, const int offset, + const bool is_c_tail_proccessing); + + void maybe_recalculate_divisor(int jj, int ur_w, int pad_l, int pad_r, + bool with_c_tail_proccessing); + void avg_step(int ur_w, int ur_bc, int pad_l, int pad_r, + bool with_c_tail_proccessing); + void max_step_fwd(int ur_w, int ur_bc, int pad_l, int pad_r, + bool with_c_tail_proccessing); + void max_step_bwd(int ur_w, int ur_bc, int pad_l, int pad_r, + bool with_c_tail_proccessing); + + void zero_diff_src(int ur_bc, bool with_c_tail_proccessing); + + void step(int ur_w, int ur_bc, int pad_l, int pad_r, + bool with_c_tail_proccessing) { + if (jpp.alg == alg_kind::pooling_max) { + if (jpp.is_backward) + max_step_bwd( + ur_w, ur_bc, pad_l, pad_r, with_c_tail_proccessing); + else + max_step_fwd( + ur_w, ur_bc, pad_l, pad_r, with_c_tail_proccessing); + } else + avg_step(ur_w, ur_bc, pad_l, pad_r, with_c_tail_proccessing); + } + + void step_high_half(int ur_w, int ur_bc, int pad_l, int pad_r, + bool with_c_tail_processing) { + add(reg_input, sizeof(float) * 4); + add(reg_output, sizeof(float) * 4); + if (jpp.alg == alg_kind::pooling_max + && (jpp.is_training || jpp.is_backward)) + add(reg_index, types::data_type_size(jpp.ind_dt) * 4); + + step(ur_w, ur_bc, pad_l, pad_r, with_c_tail_processing); + } + + void generate() override; + + void avx_vpadd1(const Ymm &y0, const Xmm &x1, const Xmm &xtmp) { + assert(y0.getIdx() != x1.getIdx()); + vextractf128(xtmp, y0, 0); + vpaddd(xtmp, xtmp, x1); + vinsertf128(y0, y0, xtmp, 0); + vextractf128(xtmp, y0, 1); + vpaddd(xtmp, xtmp, x1); + vinsertf128(y0, y0, xtmp, 1); + } + + void avx_vpadd1(const Xmm &x0, const Xmm &x1, const Xmm &) { + assert(false /*function should not be used*/); + paddd(x0, x1); + } + + void avx_pmovzxbd(const Ymm &y0, const Xmm &x1, const Xmm &xtmp) { + Xmm x0(y0.getIdx()); + pshufd(xmm_tmp, x1, 1); + pmovzxbd(x0, x1); + pmovzxbd(xmm_tmp, xmm_tmp); + vinsertf128(y0, y0, xmm_tmp, 1); + } + + void avx_pmovzxbd(const Xmm &x0, const Xmm &x1, const Xmm &) { + assert(false /*function should not be used*/); + pmovzxbd(x0, x1); + } + + void avx_pcmpeqd( + const Ymm &y0, const Ymm &y1, const Ymm &y2, const Xmm &xtmp) { + assert(y0.getIdx() != y1.getIdx()); + assert(y0.getIdx() != y2.getIdx()); + Xmm x0(y0.getIdx()); + Xmm x2(y2.getIdx()); + vextractf128(x0, y1, 1); + vextractf128(xtmp, y2, 1); + pcmpeqd(xtmp, x0); + vextractf128(x0, y1, 0); + pcmpeqd(x0, x2); + vinsertf128(y0, y0, xtmp, 1); + } + + void avx_pcmpeqd(const Xmm &x0, const Xmm &x1, const Xmm &, const Xmm &) { + assert(false /*function should not be used*/); + pcmpeqd(x0, x1); + } + + void apply_postops(int ur_bc, int ur_w, int c_block, + const std::function &is_tail_predicate); + + static bool post_ops_ok(jit_pool_conf_t &jpp, const primitive_attr_t &attr, + const memory_desc_wrapper &dst_d); + + inline bool use_bf16_emulation() const { + return jpp.is_bf16 && !isa_has_bf16(jpp.isa) && isa != avx2_vnni_2; + } + + std::unique_ptr bf16_emu_; + std::unique_ptr> + postops_injector_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_pooling.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_pooling.hpp new file mode 100644 index 0000000000000000000000000000000000000000..fad3eff849c2389e966b860f18a2bf60ef6cc487 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_pooling.hpp @@ -0,0 +1,190 @@ +/******************************************************************************* +* Copyright 2017-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_UNI_POOLING_HPP +#define CPU_X64_JIT_UNI_POOLING_HPP + +#include +#include + +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/primitive.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_pooling_pd.hpp" +#include "cpu/x64/jit_uni_pool_kernel.hpp" +#include "cpu/x64/jit_uni_reorder.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +namespace jit_uni_pooling_utils { +struct trans_wrapper_t; +struct trans_context_t; +} // namespace jit_uni_pooling_utils + +template +struct jit_uni_pooling_fwd_t : public primitive_t { + struct pd_t : public cpu_pooling_fwd_pd_t { + using cpu_pooling_fwd_pd_t::cpu_pooling_fwd_pd_t; + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit:", jpp_.isa, ""), + jit_uni_pooling_fwd_t); + + status_t init(engine_t *engine) { + using namespace utils; + + const bool ok = is_fwd() && !has_zero_dim_memory() + && everyone_is( + d_type, src_md()->data_type, dst_md()->data_type) + && attr()->has_default_values( + primitive_attr_t::skip_mask_t::post_ops, d_type) + && !is_dilated() && set_default_params() == status::success; + if (!ok) return status::unimplemented; + + const bool is_training + = desc_.prop_kind == prop_kind::forward_training; + if (desc()->alg_kind == alg_kind::pooling_max && is_training) + init_default_ws(); + + auto scratchpad = scratchpad_registry().registrar(); + + CHECK(jit_uni_pool_kernel::init_conf( + jpp_, scratchpad, attr_, this)); + + return status::success; + } + + jit_pool_conf_t jpp_; + }; + + explicit jit_uni_pooling_fwd_t(const pd_t *apd); + jit_uni_pooling_fwd_t(jit_uni_pooling_fwd_t &&) = default; + jit_uni_pooling_fwd_t &operator=(jit_uni_pooling_fwd_t &&) = default; + ~jit_uni_pooling_fwd_t(); + + using data_t = typename prec_traits::type; + + status_t init(engine_t *engine) override; + + status_t execute(const exec_ctx_t &ctx) const override { + auto src = CTX_IN_MEM(const data_t *, DNNL_ARG_SRC); + auto dst = CTX_OUT_MEM(data_t *, DNNL_ARG_DST); + auto ws = CTX_OUT_MEM(char *, DNNL_ARG_WORKSPACE); + + if (pd()->ndims() == 5) + execute_forward_3d(src, dst, ws, ctx); + else + execute_forward(src, dst, ws, ctx); + + return status::success; + } + +private: + void execute_forward(const data_t *src, data_t *dst, char *indices, + const exec_ctx_t &ctx) const; + void execute_forward_3d(const data_t *src, data_t *dst, char *indices, + const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + status_t init_ncsp_trans_ctx(); + + std::unique_ptr> kernel_; + std::unique_ptr trans_ctx_; + static constexpr data_type_t wsp_dt_ = data_type::f32; +}; + +template +struct jit_uni_pooling_bwd_t : public primitive_t { + struct pd_t : public cpu_pooling_bwd_pd_t { + using cpu_pooling_bwd_pd_t::cpu_pooling_bwd_pd_t; + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit:", jpp_.isa, ""), + jit_uni_pooling_bwd_t); + + status_t init(engine_t *engine) { + using namespace utils; + + const bool ok = true && set_default_params() == status::success + && !is_fwd() && !has_zero_dim_memory() + && everyone_is(d_type, diff_src_md()->data_type, + diff_dst_md()->data_type) + && attr()->has_default_values() && !is_dilated(); + if (!ok) return status::unimplemented; + + if (desc()->alg_kind == alg_kind::pooling_max) { + const auto ws_dt = hint_fwd_pd_->workspace_md()->data_type; + init_default_ws(ws_dt); + if (!compare_ws(hint_fwd_pd_)) return status::unimplemented; + } + + auto scratchpad = scratchpad_registry().registrar(); + + CHECK(jit_uni_pool_kernel::init_conf( + jpp_, scratchpad, attr_, this)); + + return status::success; + } + + jit_pool_conf_t jpp_; + }; + + explicit jit_uni_pooling_bwd_t(const pd_t *apd); + jit_uni_pooling_bwd_t(jit_uni_pooling_bwd_t &&) = default; + jit_uni_pooling_bwd_t &operator=(jit_uni_pooling_bwd_t &&) = default; + ~jit_uni_pooling_bwd_t(); + + using data_t = typename prec_traits::type; + + status_t init(engine_t *engine) override; + + status_t execute(const exec_ctx_t &ctx) const override { + auto diff_dst = CTX_IN_MEM(const data_t *, DNNL_ARG_DIFF_DST); + auto ws = CTX_IN_MEM(const char *, DNNL_ARG_WORKSPACE); + auto diff_src = CTX_OUT_MEM(data_t *, DNNL_ARG_DIFF_SRC); + + if (pd()->ndims() == 5) + execute_backward_3d(diff_dst, ws, diff_src, ctx); + else + execute_backward(diff_dst, ws, diff_src, ctx); + + return status::success; + } + +private: + void execute_backward(const data_t *diff_dst, const char *indices, + data_t *diff_src, const exec_ctx_t &ctx) const; + void execute_backward_3d(const data_t *diff_dst, const char *indices, + data_t *diff_src, const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + status_t init_ncsp_trans_ctx(); + + std::unique_ptr> kernel_; + std::unique_ptr trans_ctx_; + static constexpr data_type_t wsp_dt_ = data_type::f32; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_reduction.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_reduction.hpp new file mode 100644 index 0000000000000000000000000000000000000000..844fa730413b038e483073c7c2d052be8231b98f --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_reduction.hpp @@ -0,0 +1,71 @@ +/******************************************************************************* +* Copyright 2021-2022 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_UNI_REDUCTION_HPP +#define CPU_X64_UNI_REDUCTION_HPP + +#include "common/c_types_map.hpp" +#include "common/primitive.hpp" + +#include "cpu/cpu_reduction_pd.hpp" + +#include "cpu/x64/injectors/jit_uni_postops_injector.hpp" +#include "cpu/x64/jit_primitive_conf.hpp" +#include "cpu/x64/jit_uni_reduction_kernel.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +struct jit_uni_reduction_t : public primitive_t { + struct pd_t : public cpu_reduction_pd_t { + using cpu_reduction_pd_t::cpu_reduction_pd_t; + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit:", conf_.isa, ""), + jit_uni_reduction_t); + + status_t init(engine_t *engine); + + const jit_reduction_conf_t &get_conf() const { return conf_; }; + + private: + bool fill_post_ops_conf(); + + jit_reduction_conf_t conf_; + }; + + jit_uni_reduction_t(const pd_t *apd) : primitive_t(apd) {} + virtual ~jit_uni_reduction_t() = default; + + status_t init(engine_t *engine) override; + status_t execute(const exec_ctx_t &ctx) const override; + +private: + status_t get_proper_kernel( + const memory_desc_t *dst_md, const jit_reduction_conf_t &conf); + + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr kernel_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_reduction_kernel.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_reduction_kernel.hpp new file mode 100644 index 0000000000000000000000000000000000000000..34b0b66acaabb4d18e023762e8e5c574d1d3dcd4 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_reduction_kernel.hpp @@ -0,0 +1,153 @@ +/******************************************************************************* +* Copyright 2021-2022 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_UNI_REDUCTION_KERNEL_HPP +#define CPU_X64_UNI_REDUCTION_KERNEL_HPP + +#include "common/c_types_map.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_resampling_pd.hpp" + +#include "cpu/x64/injectors/jit_uni_postops_injector.hpp" +#include "cpu/x64/jit_generator.hpp" +#include "cpu/x64/jit_primitive_conf.hpp" +#include "cpu/x64/utils/jit_io_helper.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +struct jit_uni_reduction_kernel_base_t : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_uni_reduction) + + jit_uni_reduction_kernel_base_t(const jit_reduction_conf_t &conf) + : jit_generator(jit_name(), nullptr, MAX_CODE_SIZE, true, conf.isa) + , conf_(conf) + , sum_scales_(conf_.sum_scales) {} + virtual ~jit_uni_reduction_kernel_base_t() = default; + + virtual std::size_t get_simd_w() = 0; + +protected: + const jit_reduction_conf_t &conf_; + std::queue sum_scales_; +}; + +template ::Vmm> +struct jit_uni_reduction_kernel_t : public jit_uni_reduction_kernel_base_t { + jit_uni_reduction_kernel_t( + const jit_reduction_conf_t &conf, const memory_desc_t *dst_md); + + virtual ~jit_uni_reduction_kernel_t() = default; + + std::size_t get_simd_w() override { return simd_w_; } + +private: + using compute_fn_t = std::function; + + void init_acc(); + void init_compute_op(); + void init_compute_scalar_op(); + void init_post_ops_injector(const memory_desc_t *dst_md); + + void reduce_ymm_to_xmm(const Xbyak::Xmm &acc, const Xbyak::Xmm &tmp); + void reduce_xmm_to_scalar(const Xbyak::Xmm &acc, const Xbyak::Xmm &tmp, + const std::size_t number_of_values_to_reduce + = number_of_f32_in_xmm_); + void reduce_zmm_to_ymm(const Xbyak::Xmm &acc, const Xbyak::Xmm &tmp); + void reduce_ymm_to_scalar(const Xbyak::Xmm &acc, const Xbyak::Xmm &tmp1, + const Xbyak::Xmm &tmp2, + const std::size_t number_of_values_to_reduce + = number_of_f32_in_ymm_); + void reduce_vmm_to_scalar(const Xbyak::Xmm &acc, const Xbyak::Xmm &tmp1, + const Xbyak::Xmm &tmp2, const Xbyak::Xmm &tmp3, + const std::size_t number_of_values_to_reduce + = number_of_f32_in_zmm_); + + void reduce(); + void reduce_base(); + void reduce_ne_convert_xf16(); + + void load_params(); + void apply_sum(const int data_idx); + void apply_postops(const int data_idx); + void finalize(); + void generate() override; + + const Vmm vmm_tail_load_mask_ = Vmm(0); + const Vmm vmm_tail_store_mask_ = Vmm(1); + const Vmm vmm_zero_saturation_ = Vmm(2); + const Vmm vmm_saturation_ubound_ = Vmm(3); + const Vmm vmm_acc_ = Vmm(4); + const Vmm vmm_tmp1_ = Vmm(5); + const Vmm vmm_tmp2_ = Vmm(6); + const Vmm vmm_tmp3_ = Vmm(7); + const Vmm vmm_tmp4_ = Vmm(8); + const Vmm vmm_sum_scale_ = Vmm(9); + const Vmm rhs_dt_helper_vmm_ = Vmm(10); + const Xbyak::Zmm vmm_bf16_emu_1_ = Xbyak::Zmm(28); + const Xbyak::Zmm vmm_bf16_emu_2_ = Xbyak::Zmm(29); + const Xbyak::Zmm vmm_bf16_emu_3_ = Xbyak::Zmm(30); + const Xbyak::Zmm vmm_bf16_emu_4_ = Xbyak::Zmm(31); + + const Xbyak::Opmask k_tail_load_mask_ = k3; + const Xbyak::Opmask k_tail_store_mask_ = k4; + + const Xbyak::Reg64 reg_work_ = rax; + const Xbyak::Reg64 reg_src_ = rbx; + const Xbyak::Reg64 reg_dst_ = rdx; + const Xbyak::Reg64 reg_param_ = abi_param1; + const Xbyak::Reg64 reg_tmp_ = abi_not_param1; + const Xbyak::Reg64 reg_tmp1_ = r13; + + static constexpr bool is_zmm_ = std::is_same::value; + static constexpr bool is_ymm_ = std::is_same::value; + static constexpr std::size_t vlen_ = is_zmm_ ? 64 : is_ymm_ ? 32 : 16; + static constexpr std::size_t simd_w_ = vlen_ / sizeof(float); + static constexpr std::size_t number_of_f32_in_xmm_ = 4; + static constexpr std::size_t number_of_f32_in_ymm_ = 8; + static constexpr std::size_t number_of_f32_in_zmm_ = 16; + const std::size_t load_tail_size_; + static constexpr std::size_t store_tail_size_ = 1; + + io::jit_io_helper_t io_load_; + io::jit_io_helper_t io_store_; + + compute_fn_t compute_op_; + compute_fn_t compute_scalar_op_; + + const Xbyak::Opmask elt_inj_opmask_ = k1; + const Xbyak::Reg64 reg_po_injector_helper_1_ = r14; + const Xbyak::Reg64 reg_po_injector_helper_2_ = r15; + const Xbyak::Reg64 reg_po_injector_helper_3_ = r12; + + // post-ops injector does not use avx512_core_bf16 instructions + static constexpr cpu_isa_t inject_isa_ + = isa == avx512_core_bf16 ? avx512_core : isa; + std::unique_ptr> + postops_injector_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_reorder.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_reorder.hpp new file mode 100644 index 0000000000000000000000000000000000000000..eb3b035839b57291624480cd2d2051a815f388e0 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_reorder.hpp @@ -0,0 +1,312 @@ +/******************************************************************************* +* Copyright 2018-2022 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_UNI_REORDER_HPP +#define CPU_X64_JIT_UNI_REORDER_HPP + +#include + +#include "common/c_types_map.hpp" +#include "common/type_helpers.hpp" + +#include "cpu/reorder/cpu_reorder_pd.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +namespace tr { + +constexpr int max_ndims = DNNL_MAX_NDIMS; + +struct node_t { + static constexpr int64_t empty_field = -1; + + size_t n = 0; + size_t tail_size = 0; + int dim_id = empty_field; + int parent_node_id = empty_field; + bool is_zero_pad_needed = false; + ptrdiff_t is = 0; // input stride + ptrdiff_t os = 0; // output stride + ptrdiff_t ss = 0; // scale stride + ptrdiff_t cs = 0; // compensation stride + + bool is_dim_id_empty() const { return dim_id == empty_field; } + bool is_parent_empty() const { return parent_node_id == empty_field; } +}; + +enum class scale_type_t { NONE, COMMON, MANY }; + +struct prb_t { + /* The compensation mask value indicates how big an additional buffer should be. + * Possible values for reorder: + * 1) standard compensation = 1 = 0b01 + * 2) asymmetric compensation = 2 = 0b10 + * 3) compensation if tensor contains group = 3 = 0b11 */ + static constexpr int invalid_comp_mask = 0; + static constexpr int standard_comp_mask = 0b1; + static constexpr int asymmetric_comp_mask = 0b10; + static constexpr int comp_mask_with_groups + = standard_comp_mask + asymmetric_comp_mask; + + bool is_tail_in_one_of_child_nodes(int parent_node_id) const { + for (int i = parent_node_id; i >= 0; i--) { + if (nodes[i].parent_node_id == parent_node_id) { + if (nodes[i].tail_size != 0) + return true; + else + parent_node_id = i; + } + } + + return false; + } + + int tail(int d) const { + assert(d < ndims); + return static_cast(nodes[d].tail_size); + } + + int n(int d) const { + assert(d < ndims); + return static_cast(nodes[d].n); + } + int is(int d) const { + assert(d < ndims); + return static_cast(nodes[d].is); + } + int os(int d) const { + assert(d < ndims); + return static_cast(nodes[d].os); + } + int ss(int d) const { + assert(d < ndims); + return static_cast(nodes[d].ss); + } + + int cs(int d) const { + assert(d < ndims); + return static_cast(nodes[d].cs); + } + + data_type_t itype; + data_type_t otype; + int ndims; + node_t nodes[max_ndims]; + ptrdiff_t ioff; + ptrdiff_t ooff; + scale_type_t src_scale_type; + scale_type_t dst_scale_type; + float beta; + int full_ndims; + bool is_tail_present = false; + float scale_adjust = 1.f; + int compensation_mask = invalid_comp_mask; + bool req_s8s8_comp = false; + bool req_asymmetric_comp = false; + bool req_src_zp = false; + bool req_dst_zp = false; +}; + +status_t prb_init(prb_t &prb, const memory_desc_t &imd, + const memory_desc_t &omd, const primitive_attr_t *attr); + +/** sorts the problem nodes so that output strides come in ascending order */ +void prb_normalize(prb_t &p); + +/** fill parent node info for blocked nodes */ +void prb_node_dependency(prb_t &p); + +/** folds nodes together if possible */ +void prb_simplify(prb_t &p); + +/** splits the node dim into two of sizes n1 and n / n1 + * @warning n must be multiple of n1 */ +void prb_node_split(prb_t &p, int dim, size_t n1); + +/** swaps d0 and d1 nodes */ +void prb_node_swap(prb_t &p, int d0, int d1); + +/** moves node d0 to the d1 position. + * nodes (d0, d1] are shifted to the left if d0 < d1 or + * to the right if d0 > d1 */ +void prb_node_move(prb_t &p, int d0, int d1); + +/** dumps the problem to stdout */ +void prb_dump(const prb_t &p); + +struct call_param_t { + const void *in = nullptr; + void *out = nullptr; + const float *src_scales = nullptr; + const float *dst_scales = nullptr; + int32_t src_zp = 0; + int32_t dst_zp = 0; + int32_t *compensation_scratch = nullptr; +}; + +// The additional structure is needed because +// using a data structure with tail processing +// data for non-tail cases reduces kernel +// performance. This is because there is too +// much data that has to be transferred to the kernel. +struct tail_call_param_t { + call_param_t base_params; + int64_t curr_data_chunks[DNNL_MAX_NDIMS] = {-1}; + int64_t zeroing_data = static_cast(false); + int64_t skip_kernel_execution = static_cast(false); +}; + +struct kernel_t { + struct desc_t { + int id; + prb_t prb; + }; + + kernel_t(const desc_t &desc) + : desc_(desc) + , compensation_needed_( + desc.prb.req_s8s8_comp || desc.prb.req_asymmetric_comp) {} + virtual void operator()(const call_param_t *c) const = 0; + virtual void operator()(const tail_call_param_t *c) const = 0; + virtual status_t create_kernel() = 0; + virtual ~kernel_t() {} + + /** inits kernel descriptor: + * desc -- kernel descriptor (output) + * prb -- transposition problem (input) + * ndims_ker_max -- limit the maximum number of dimensions kernel + * will process (optional, 0 -- no limitation) */ + static status_t desc_init( + desc_t &desc, const prb_t &prb, int ndims_ker_max = 0); + + /** creates kernel for the problem described in desc */ + static kernel_t *create(const desc_t &desc); + +protected: + const desc_t desc_; + const prb_t &prb_ = desc_.prb; + bool compensation_needed_ = false; +}; + +/* TODO: add trans_t class */ + +struct jit_single_blk_kernel_t; + +} // namespace tr + +struct jit_uni_reorder_t : public primitive_t { + using primitive_t::primitive_t; + struct pd_t : public cpu_reorder_pd_t { + using cpu_reorder_pd_t::cpu_reorder_pd_t; + + DECLARE_COMMON_PD_T("jit:uni", jit_uni_reorder_t); + + tr::prb_t prb_; + tr::kernel_t::desc_t ker_desc_; + int nthr_; + bool with_groups_ = false; + dim_t D_mask_ = 0; + + status_t init( + engine_t *engine, engine_t *src_engine, engine_t *dst_engine); + + private: + status_t init_scratchpad(); + static status_t create(reorder_pd_t **reorder_pd, engine_t *engine, + const primitive_attr_t *attr, engine_t *src_engine, + const memory_desc_t *src_md, engine_t *dst_engine, + const memory_desc_t *dst_md); + + friend dnnl::impl::impl_list_item_t; + }; + + status_t init(engine_t *engine) override; + status_t execute(const exec_ctx_t &ctx) const override; + + enum { ndims_driver_max = 4 }; + +private: + void omp_driver_0d(int off, const char *in, char *out, + const float *src_scales, const float *dst_scales, int src_zp, + int dst_zp, int32_t *compensation_scratch) const; + void omp_driver_1d(int ithr, int nthr, int off, const char *in, char *out, + const float *src_scales, const float *dst_scales, int src_zp, + int dst_zp, int32_t *compensation_scratch) const; + void omp_driver_2d(int ithr, int nthr, int off, const char *in, char *out, + const float *src_scales, const float *dst_scales, int src_zp, + int dst_zp, int32_t *compensation_scratch) const; + void omp_driver_3d(int ithr, int nthr, int off, const char *in, char *out, + const float *src_scales, const float *dst_scales, int src_zp, + int dst_zp, int32_t *compensation_scratch) const; + void omp_driver_4d(int ithr, int nthr, int off, const char *in, char *out, + const float *src_scales, const float *dst_scales, int src_zp, + int dst_zp, int32_t *compensation_scratch) const; + + void omp_driver(const char *in, char *out, const float *src_scales, + const float *dst_scales, int src_zp, int dst_zp, + const memory_tracking::grantor_t &scratchpad) const; + + void fill_curr_data_chunks(const tr::prb_t &prb, const int off, + const ptrdiff_t *omp_data_chunks, const int omp_ndims, + tr::tail_call_param_t &c) const; + + void reduce_compensation(char *out, + const int32_t *compensation_reduce_scratch, const int nthr, + const dim_t wspace_per_thr_size) const; + + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + std::unique_ptr kernel_; +}; + +struct jit_blk_reorder_t : public primitive_t { + using primitive_t::primitive_t; + struct pd_t : public cpu_reorder_pd_t { + using cpu_reorder_pd_t::cpu_reorder_pd_t; + DECLARE_COMMON_PD_T("jit:blk", jit_blk_reorder_t); + + tr::prb_t prb_; + + private: + static status_t create(reorder_pd_t **reorder_pd, engine_t *engine, + const primitive_attr_t *attr, engine_t *src_engine, + const memory_desc_t *src_md, engine_t *dst_engine, + const memory_desc_t *dst_md); + + // Swap last two nodes, put block 4, 8, 16 nodes to first + static void prb_tile_normalize(tr::prb_t &p); + friend dnnl::impl::impl_list_item_t; + }; + + status_t init(engine_t *engine) override; + status_t execute(const exec_ctx_t &ctx) const override; + + jit_blk_reorder_t(const pd_t *apd); + ~jit_blk_reorder_t(); + +private: + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + std::unique_ptr kernel_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_resampling.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_resampling.hpp new file mode 100644 index 0000000000000000000000000000000000000000..0676475e221c039630f809082a413accc5efd60f --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_resampling.hpp @@ -0,0 +1,192 @@ +/******************************************************************************* +* Copyright 2020-2021 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_UNI_RESAMPLING_HPP +#define CPU_X64_UNI_RESAMPLING_HPP + +#include "common/c_types_map.hpp" +#include "common/primitive.hpp" + +#include "cpu/cpu_resampling_pd.hpp" + +#include "cpu/x64/cpu_isa_traits.hpp" +#include "cpu/x64/injectors/jit_uni_postops_injector.hpp" +#include "cpu/x64/jit_primitive_conf.hpp" +#include "cpu/x64/jit_uni_resampling_kernel.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +struct jit_uni_resampling_fwd_t : public primitive_t { + struct pd_t : public cpu_resampling_fwd_pd_t { + using cpu_resampling_fwd_pd_t::cpu_resampling_fwd_pd_t; + + DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit:", conf_.isa, ""), + jit_uni_resampling_fwd_t); + + status_t init(engine_t *engine); + + const jit_resampling_conf_t &get_conf() const { return conf_; } + + private: + void fill_format_tag_info(); + + jit_resampling_conf_t conf_; + }; + + jit_uni_resampling_fwd_t(const pd_t *apd) : primitive_t(apd) {} + virtual ~jit_uni_resampling_fwd_t() = default; + + status_t init(engine_t *engine) override; + status_t execute(const exec_ctx_t &ctx) const override; + +private: + status_t fill_data_for_interpolation(); + /* + * Fills indices_ with the data that contains the corresponding + * input point for each output point. + * The data is arranged as follows: + * od_0 = id_0 * stride_w + * od_1 = id_1 * stride_w + * od_2 = id_2 * stride_w + * ... + * ih_0 = ih_0 * stride_h + * ih_1 = ih_1 * stride_h + * ... + * iw_0 = iw_1 * stride_w + * ... + */ + status_t fill_data_for_nearest(); + /* + * Fills indices_ with the data that contains the corresponding + * input point for each output point. + * The data is arranged as follows: + * od_0 = id_0 + * od_1 = id_1 + * od_2 = id_2 + * ... + * oh_0 = ih_0 + * oh_1 = ih_1 + * ... + * ow_0 = iw_0 + * ... + */ + status_t fill_data_for_linear(); + /* + * Fills indices_ with the data that contains the corresponding + * corners from input tensor for each output point and fills + * weights_ with with the data that contains weights for + * corners from input tensor for each output point. + * The data is arranged as follows: + * NSPC and BLOCKED: + * + * indices_: + * ow_0 = iw_0_left + * ow_0 = iw_0_right + * ow_1 = iw_1_left + * ow_1 = iw_1_right + * ... + * oh_0 = ih_0_top + * oh_1 = ih_1_top + * ... + * oh_0 = ih_0_bottom + * oh_1 = ih_1_bottom + * ... + * od_0 = id_0_front + * od_1 = id_1_front + * ... + * od_0 = id_0_back + * od_1 = id_1_back + * ... + * + * weights_: + * ow_0 = weight_0_left + * ow_0 = weight_0_right + * ow_1 = weight_1_left + * ow_1 = weight_1_right + * ... + * oh_0 = weight_0_top + * oh_1 = weight_1_top + * ... + * oh_0 = weight_0_bottom + * oh_1 = weight_1_bottom + * ... + * od_0 = weight_0_front + * od_1 = weight_1_front + * ... + * od_0 = weight_0_back + * od_1 = weight_1_back + * ... + * + * NCSP: + * + * indices_: + * sp_0 = id_0_front + ih_0_top + iw_0_left + * sp_0 = id_0_front + ih_0_top + iw_0_right + * sp_0 = id_0_front + ih_0_bottom + iw_0_left + * sp_0 = id_0_front + ih_0_bottom + iw_0_right + * sp_0 = id_0_back + ih_0_top + iw_0_left + * sp_0 = id_0_back + ih_0_top + iw_0_right + * sp_0 = id_0_back + ih_0_bottom + iw_0_left + * sp_0 = id_0_back + ih_0_bottom + iw_0_right + * sp_1 = id_1_front + ih_1_top + iw_1_left + * sp_1 = id_1_front + ih_1_top + iw_1_right + * sp_1 = id_1_front + ih_1_bottom + iw_1_left + * ... + * + * weights_: + * sp_0 = weight_0_front * weight_0_top * weight_0_left + * sp_0 = weight_0_front * weight_0_top * weight_0_right + * sp_0 = weight_0_front * weight_0_bottom * weight_0_left + * sp_0 = weight_0_front * weight_0_bottom * weight_0_right + * sp_0 = weight_0_back * weight_0_top * weight_0_left + * sp_0 = weight_0_back * weight_0_top * weight_0_right + * sp_0 = weight_0_back * weight_0_bottom * weight_0_left + * sp_0 = weight_0_back * weight_0_bottom * weight_0_right + * sp_1 = weight_1_front * weight_1_top * weight_1_left + * sp_1 = weight_1_front * weight_1_top * weight_1_right + * sp_1 = weight_1_front * weight_1_bottom * weight_1_left + * ... + */ + + status_t interpolate_nearest(const uint8_t *src, uint8_t *dst, + const std::vector &post_ops_args) const; + status_t interpolate_linear(const uint8_t *src, uint8_t *dst, + const std::vector &post_ops_args) const; + + status_t get_proper_kernel_for_avx512( + const memory_desc_t *dst_md, const jit_resampling_conf_t &conf); + status_t get_proper_kernel_for_avx( + const memory_desc_t *dst_md, const jit_resampling_conf_t &conf); + status_t get_proper_kernel_for_sse( + const memory_desc_t *dst_md, const jit_resampling_conf_t &conf); + + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr kernel_; + + std::vector indices_; + std::vector weights_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_resampling_kernel.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_resampling_kernel.hpp new file mode 100644 index 0000000000000000000000000000000000000000..be414b6d562e5cb3c18503a3856833fa8838571a --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_resampling_kernel.hpp @@ -0,0 +1,218 @@ +/******************************************************************************* +* Copyright 2020-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_UNI_RESAMPLING_KERNEL_HPP +#define CPU_X64_UNI_RESAMPLING_KERNEL_HPP + +#include "common/c_types_map.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_resampling_pd.hpp" + +#include "cpu/x64/cpu_isa_traits.hpp" +#include "cpu/x64/injectors/jit_uni_postops_injector.hpp" +#include "cpu/x64/jit_generator.hpp" +#include "cpu/x64/jit_primitive_conf.hpp" +#include "cpu/x64/utils/jit_io_helper.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +struct jit_uni_resampling_kernel_base_t : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_uni_resampling) + + jit_uni_resampling_kernel_base_t(const jit_resampling_conf_t &conf) + : jit_generator(jit_name(), nullptr, MAX_CODE_SIZE, true, conf.isa) + , conf_(conf) + , sum_scales_(conf_.sum_scales) {} + + virtual ~jit_uni_resampling_kernel_base_t() = default; + + virtual std::size_t get_simd_w() = 0; + +protected: + const jit_resampling_conf_t &conf_; + std::queue sum_scales_; +}; + +template +struct jit_uni_resampling_kernel_t : public jit_uni_resampling_kernel_base_t { + + jit_uni_resampling_kernel_t( + const jit_resampling_conf_t &conf, const memory_desc_t *dst_md); + + virtual ~jit_uni_resampling_kernel_t() = default; + + std::size_t get_simd_w() override { return simd_w_; } + +private: + using Xmm = Xbyak::Xmm; + using Ymm = Xbyak::Ymm; + using Zmm = Xbyak::Zmm; + using Opmask = Xbyak::Opmask; + using Reg64 = Xbyak::Reg64; + using c_oriented_generation_fn_t = std::function; + + constexpr int vmm_idx(int idx) const { + return (cpu_isa_traits::n_vregs - 1) - idx; + } + + bool can_movntps_be_used() const; + std::size_t calculate_tail_size() const; + int get_channels_to_compute_without_tail( + bool is_tail_in_blocked_format) const; + + std::map + create_saturation_vmm_map() const; + + void get_params_for_linear_in_c_oriented_format(); + + void preserve_zero_padding_in_post_ops(int data_idx); + void apply_sum( + const int data_idx, const bool is_tail, const size_t offset = 0); + void apply_postops( + const int data_idx, const bool is_tail, const size_t offset = 0); + + void preserve_zero_padding( + int c_to_compute_without_tail, const bool is_tail); + + void interpolate_c_oriented_format( + const c_oriented_generation_fn_t &generation_fn); + void nearest_ncsp_format(); + void nearest_c_oriented_format(const bool is_tail_in_blocked_format); + void linear_ncsp_format(); + void linear_c_oriented_format(const bool is_tail_in_blocked_format); + void compute_nearest_c_interpolate( + const int c_to_compute_without_tail, const bool is_tail); + void compute_ne_xf16_nearest_c_interpolate( + const int c_to_compute_without_tail); + void compute_linear_c_interpolate( + const int c_to_compute_without_tail, const bool is_tail); + void compute_ne_xf16_linear_c_interpolate( + const int c_to_compute_without_tail); + + void generate() override; + + // Used only for avx and if c tail is present. + const Vmm vmm_tail_mask_ = Vmm(0); + // Used only for avx2 and if ncsp format is present. + // Vgatherdps always gets data using a conditional mask. + // This register contains all bits set to 1, allowing + // to get the maximum number of values available to the register + const Vmm vmm_full_mask_ = Vmm(1); + const Vmm vmm_src_ = Vmm(2); + const Vmm vmm_weights_ = Vmm(3); + const Vmm vmm_indices_ = Vmm(4); + const Vmm vmm_tmp_gather_ = Vmm(5); + const Vmm vmm_sum_scale_ = Vmm(7); + const Vmm vmm_tmp_ = Vmm(8); + const Vmm vmm_post_op_helper_ = Vmm(9); + const Vmm vmm_zero_saturation_ = isa == avx512_core ? Vmm(18) : Vmm(10); + const Vmm vmm_saturation_ubound_ = isa == avx512_core ? Vmm(19) : Vmm(11); + const Vmm vmm_src_even_ = vmm_src_; + const Vmm vmm_src_odd_ = Vmm(12); + + const Zmm vmm_bf16_emu_1_ = Zmm(20); + const Zmm vmm_bf16_emu_2_ = Zmm(21); + const Zmm vmm_bf16_emu_3_ = Zmm(22); + const Zmm vmm_bf16_emu_4_ = Zmm(23); + + const Opmask k_tail_mask_ = k3; + const Opmask k_full_mask_ = k4; + + const Reg64 reg_tmp_ = rax; + const Reg64 reg_dst_ = rbx; + const Reg64 reg_work_ = rdx; + const Reg64 reg_indices_ = rsi; + const Reg64 reg_c_offset = rbp; + const Reg64 reg_param = abi_param1; + const Reg64 reg_weights = abi_not_param1; + const Reg64 reg_src_ = r8; + const Reg64 reg_aux_src_0_ = r9; + const Reg64 reg_aux_src_1_ = r10; + const Reg64 reg_aux_src_2_ = r11; + const Reg64 reg_tmp1_ = r15; + + // Registers which are used only for linear algorithm + // and for channel oriented formats. + // Meaning of shortcuts: + // f - front, b - back + // t - top, b - bottom + // l - left, r - right + // Example: + // src_ftl_ - source tensor data for the front top left corner + // reg_src_ftl_ - register which contains address of source + // tensor data for the front top left corner + const Vmm weight_left_ = Vmm(1); + const Vmm weight_right_ = Vmm(2); + const Vmm weight_top_ = Vmm(3); + const Vmm weight_bottom_ = Vmm(4); + const Vmm weight_front_ = Vmm(5); + const Vmm weight_back_ = Vmm(6); + const Vmm src_ftl_ = Vmm(vmm_idx(0)); + const Vmm src_ftr_ = Vmm(vmm_idx(1)); + const Vmm src_fbl_ = Vmm(vmm_idx(2)); + const Vmm src_fbr_ = Vmm(vmm_idx(3)); + const Vmm src_btl_ = Vmm(vmm_idx(4)); + const Vmm src_btr_ = Vmm(vmm_idx(5)); + const Vmm src_bbl_ = Vmm(vmm_idx(6)); + const Vmm src_bbr_ = Vmm(vmm_idx(7)); + + const Reg64 reg_src_ftl_ = reg_src_; + const Reg64 reg_src_ftr_ = reg_aux_src_0_; + const Reg64 reg_src_fbl_ = reg_aux_src_1_; + const Reg64 reg_src_fbr_ = reg_aux_src_2_; + const Reg64 reg_src_btl_ = r12; + const Reg64 reg_src_btr_ = r13; + const Reg64 reg_src_bbl_ = r14; + const Reg64 reg_src_bbr_ = r15; + + const Vmm src_ftl_even_ = Vmm(vmm_idx(0)); + const Vmm src_ftl_odd_ = Vmm(vmm_idx(1)); + const Vmm src_ftr_even_ = Vmm(vmm_idx(2)); + const Vmm src_ftr_odd_ = Vmm(vmm_idx(3)); + const Vmm src_fbl_even_ = Vmm(vmm_idx(4)); + const Vmm src_fbl_odd_ = Vmm(vmm_idx(5)); + const Vmm src_fbr_even_ = Vmm(vmm_idx(2)); + const Vmm src_fbr_odd_ = Vmm(vmm_idx(3)); + + const std::vector> src_regs_ + = {reg_src_ftl_, reg_src_ftr_, reg_src_fbl_, reg_src_fbr_, + reg_src_btl_, reg_src_btr_, reg_src_bbl_, reg_src_bbr_}; + + static constexpr bool is_zmm_ = std::is_same::value; + static constexpr bool is_ymm_ = std::is_same::value; + static constexpr bool is_xmm_ = std::is_same::value; + static constexpr std::size_t vlen_ = is_zmm_ ? 64 : is_ymm_ ? 32 : 16; + static constexpr std::size_t simd_w_ = vlen_ / sizeof(float); + const std::size_t tail_size_; + + bool any_binary_postop_is_per_oc_bcast_type_ = false; + bool any_binary_postop_is_per_oc_sp_bcast_type_ = false; + + io::jit_io_multi_dt_helper_t io_; + std::unique_ptr> + postops_injector_; +}; +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_softmax.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_softmax.hpp new file mode 100644 index 0000000000000000000000000000000000000000..c49ed5cb98e1ea938c1a502f8948bf39e0a6a6a4 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_softmax.hpp @@ -0,0 +1,299 @@ +/******************************************************************************* +* Copyright 2019-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_UNI_SOFTMAX_HPP +#define CPU_X64_JIT_UNI_SOFTMAX_HPP + +#include + +#include "common/c_types_map.hpp" +#include "common/memory_tracking.hpp" +#include "common/primitive.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_softmax_pd.hpp" + +#include "cpu/x64/cpu_isa_traits.hpp" +#include "cpu/x64/injectors/jit_uni_postops_injector.hpp" +#include "cpu/x64/jit_avx512_core_bf16cvt.hpp" + +#define VCHECK_SOFTMAX(cond, msg, ...) \ + VCONDCHECK(create, dispatch, softmax, (cond), status::unimplemented, \ + "%s," msg, this->info(engine), ##__VA_ARGS__) + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +namespace softmax_impl { +// This class isolates primitive implementation from templates introduced by +// the kernel. +struct jit_softmax_kernel_base_t { + static jit_softmax_kernel_base_t *create( + const softmax_pd_t *pd, const cpu_isa_t isa); + + virtual ~jit_softmax_kernel_base_t() = default; + + struct call_params_t { + // keep all sizes at 8 bytes -- jit code expects this + const void *src, *dst, *diff_dst; // src dubs as diff_src + const void *interim; // scratch memory for intermediate storage + const void *src_scales; // src_scales defined for all data type cases + const void *dst_scales; // dst_scales defined for all data type cases + size_t process_n_elems; + + // post ops + const void *dst_orig; + const void *post_ops_binary_rhs_arg_vec; + }; + + virtual void operator()(const call_params_t *p) const = 0; + virtual status_t create_kernel() = 0; + +protected: + jit_softmax_kernel_base_t(const softmax_pd_t *pd) : pd_(pd) {} + + const softmax_pd_t *pd_; +}; + +bcast_set_t get_supported_bcast_strategies(); +std::vector get_supported_isa(bool is_fwd); +} // namespace softmax_impl + +struct jit_uni_softmax_fwd_t : public primitive_t { + struct pd_t : public cpu_softmax_fwd_pd_t { + using cpu_softmax_fwd_pd_t::cpu_softmax_fwd_pd_t; + + const char *impl_name() const { + return JIT_IMPL_NAME_HELPER("jit:", isa_, ""); + } + + DECLARE_COMMON_PD_T(impl_name(), jit_uni_softmax_fwd_t); + + status_t init(engine_t *engine) { + auto is_dense = [&](const cpu_isa_t isa) { + const memory_desc_wrapper src_d(src_md()); + const auto &bd = src_d.blocking_desc(); + + if (!src_d.is_dense(true) || !src_d.only_padded_dim(axis())) + return false; + + if (src_d.is_plain()) return bd.strides[axis()] == 1; + + // It is fine to use float here as the kernel uses halfs of + // vector registers. + const dim_t blk_size = isa_max_vlen(isa) / sizeof(float); + // 31 is a general limit, 2 is for unroll_regs_ = 4; + const size_t max_stride = (1LL << (31 - 2)) - 1; + const int last_blk = bd.inner_nblks - 1; + return bd.inner_blks[last_blk] == blk_size + && bd.inner_idxs[last_blk] == axis() + && sizeof(float) * bd.strides[axis()] < max_stride; + }; + + using namespace data_type; + using skip_mask_t = primitive_attr_t::skip_mask_t; + + // try multiple vlen + for (const auto &i : softmax_impl::get_supported_isa(true)) { + if (mayiuse(i) && is_dense(i)) { + isa_ = i; + break; + } + } + // not dense impl can be easily done + if (isa_ == isa_undef) return status::unimplemented; + + const auto src_dt = src_md()->data_type; + const auto dst_dt = dst_md()->data_type; + bool ok = is_fwd() && !has_zero_dim_memory() + && utils::one_of(src_dt, f32, bf16, f16, s8, u8) + && utils::one_of(dst_dt, f32, bf16, f16, s8, u8) + // s8/u8 are temporary limitations due to priorities + && IMPLICATION( + (utils::one_of(s8, src_dt, dst_dt) + || utils::one_of(u8, src_dt, dst_dt)), + is_superset(isa_, avx512_core)) + && IMPLICATION(utils::one_of(bf16, src_dt, dst_dt), + is_superset(isa_, avx512_core) + || is_superset(isa_, avx2_vnni_2)) + && IMPLICATION(utils::one_of(f16, src_dt, dst_dt), + is_superset(isa_, avx512_core_fp16) + || is_superset(isa_, avx2_vnni_2)); + if (!ok) return status::unimplemented; + + VCHECK_SOFTMAX( + attr()->has_default_values(skip_mask_t::scales_runtime + | skip_mask_t::post_ops), + VERBOSE_UNSUPPORTED_ATTR); + VCHECK_SOFTMAX(attr_scales_ok(), VERBOSE_UNSUPPORTED_SCALES_CFG); + VCHECK_SOFTMAX(post_ops_ok(), VERBOSE_UNSUPPORTED_POSTOP); +#undef VCHECK_SOFTMAX + + ok = set_default_formats() == status::success + && attr_.set_default_formats(dst_md(0)) == status::success; + if (!ok) return status::unimplemented; + + ok = memory_desc_wrapper(src_md()).similar_to( + memory_desc_wrapper(dst_md()), true, false, 0); + if (!ok) return status::unimplemented; + + // AVX2 only supports xf16 on plain layout now + ok = IMPLICATION(is_superset(isa_, avx2_vnni_2) + && !is_superset(isa_, avx512_core) + && (utils::one_of(bf16, src_dt, dst_dt) + || utils::one_of(f16, src_dt, dst_dt)), + memory_desc_wrapper(src_md()).is_plain()); + if (!ok) return status::unimplemented; + + nthr_ = dnnl_get_max_threads(); + init_scratchpad(); + + return status::success; + }; + + int nthr_; // To not exceed the limit in execute used for set up. + cpu_isa_t isa_ = isa_undef; + + private: + void init_scratchpad() { + if (utils::one_of( + dst_md()->data_type, data_type::u8, data_type::s8)) { + auto scratchpad = scratchpad_registry().registrar(); + scratchpad.template book( + memory_tracking::names::key_softmax_interim_store, + axis_size(true) * sizeof(float) * nthr_); + } + } + + bool post_ops_ok() const { + const auto &post_ops = attr()->post_ops_; + const bool with_sum = post_ops.find(primitive_kind::sum) != -1; + const std::vector accepted_post_ops + = {injector::eltwise, injector::binary}; + const memory_desc_wrapper dst_d(dst_md()); + injector::post_ops_ok_args_t post_ops_args(isa_, accepted_post_ops, + attr()->post_ops_, &dst_d, true, true, true, true, + softmax_impl::get_supported_bcast_strategies()); + return !with_sum && injector::post_ops_ok(post_ops_args); + } + }; + + jit_uni_softmax_fwd_t(const pd_t *apd); + + status_t init(engine_t *engine) override; + + status_t execute(const exec_ctx_t &ctx) const override; + +private: + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + std::unique_ptr ker_; +}; + +struct jit_uni_softmax_bwd_t : public primitive_t { + struct pd_t : public cpu_softmax_bwd_pd_t { + using cpu_softmax_bwd_pd_t::cpu_softmax_bwd_pd_t; + + const char *impl_name() const { + return JIT_IMPL_NAME_HELPER("jit:", isa_, ""); + } + + DECLARE_COMMON_PD_T(impl_name(), jit_uni_softmax_bwd_t); + + status_t init(engine_t *engine) { + auto is_dense = [&](const cpu_isa_t isa) { + const memory_desc_wrapper dst_d(dst_md()); + const auto &bd = dst_d.blocking_desc(); + + if (!dst_d.is_dense(true) || !dst_d.only_padded_dim(axis())) + return false; + + // It is fine to use float here as the kernel uses halfs of + // vector registers. + const dim_t blk_size = isa_max_vlen(isa) / sizeof(float); + if (dst_d.is_plain()) + return bd.strides[axis()] == 1; + else { + // 31 is a general limit, 2 is for unroll_regs_ = 4; + const size_t max_stride = (1LL << (31 - 2)) - 1; + const int last_blk = bd.inner_nblks - 1; + return bd.inner_blks[last_blk] == blk_size + && bd.inner_idxs[last_blk] == axis() + && sizeof(float) * bd.strides[axis()] < max_stride; + } + }; + + // try multiple vlen + for (const auto &i : softmax_impl::get_supported_isa(false)) { + if (mayiuse(i) && is_dense(i)) { + isa_ = i; + break; + } + } + // not dense impl can be easily done + if (isa_ == isa_undef) return status::unimplemented; + + using namespace data_type; + bool ok = !is_fwd() && !has_zero_dim_memory() + && utils::one_of(dst_md()->data_type, f32, bf16, f16) + && utils::one_of(diff_dst_md()->data_type, f32, bf16, f16) + && utils::one_of(diff_src_md()->data_type, f32, bf16, f16) + && IMPLICATION(utils::one_of(bf16, dst_md()->data_type, + diff_dst_md()->data_type, + diff_src_md()->data_type), + is_superset(isa_, avx512_core)) + && IMPLICATION(utils::one_of(f16, dst_md()->data_type, + diff_dst_md()->data_type, + diff_src_md()->data_type), + is_superset(isa_, avx512_core_fp16)) + && attr()->has_default_values() + && set_default_formats() == status::success; + if (!ok) return status::unimplemented; + + ok = memory_desc_wrapper(diff_src_md()) + .similar_to(memory_desc_wrapper(diff_dst_md()), + true, false, 0) + && memory_desc_wrapper(diff_dst_md()) + == memory_desc_wrapper(dst_md()); + if (!ok) return status::unimplemented; + + return status::success; + } + cpu_isa_t isa_ = isa_undef; + }; + + jit_uni_softmax_bwd_t(const pd_t *apd); + + status_t init(engine_t *engine) override; + + status_t execute(const exec_ctx_t &ctx) const override; + +private: + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr ker_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_tbb_batch_normalization.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_tbb_batch_normalization.hpp new file mode 100644 index 0000000000000000000000000000000000000000..618a4d2e9b2fdb152deaa41080c11fce22f8a9f8 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_tbb_batch_normalization.hpp @@ -0,0 +1,124 @@ +/******************************************************************************* +* Copyright 2019-2022 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_UNI_TBB_BATCH_NORMALIZATION_HPP +#define CPU_X64_JIT_UNI_TBB_BATCH_NORMALIZATION_HPP + +#include "common/c_types_map.hpp" +#include "common/primitive.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_batch_normalization_pd.hpp" +#include "cpu/x64/cpu_isa_traits.hpp" +#include "jit_primitive_conf.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +namespace bnorm_tbb_impl { +template +struct driver_t; +} + +template +struct jit_uni_tbb_batch_normalization_fwd_t : public primitive_t { + struct pd_t : public cpu_batch_normalization_fwd_pd_t { + pd_t(const batch_normalization_desc_t *adesc, + const primitive_attr_t *attr, + const batch_normalization_fwd_pd_t *hint_fwd_pd) + : cpu_batch_normalization_fwd_pd_t(adesc, attr, hint_fwd_pd) {} + + DECLARE_COMMON_PD_T( + JIT_IMPL_NAME_HELPER("bnorm_tbb_jit:", + (src_md()->data_type == data_type::bf16) + ? (mayiuse(avx512_core_bf16) ? avx512_core_bf16 + : mayiuse(avx512_core) + ? bf16_emulation_t::get_isa() + : avx2_vnni_2) + : (src_md()->data_type == data_type::f16) + ? (mayiuse(avx512_core_fp16) ? avx512_core_fp16 + : avx2_vnni_2) + : isa, + ""), + jit_uni_tbb_batch_normalization_fwd_t); + + status_t init(engine_t *engine); + + jit_memory_tag_kind_t tag_kind_; + }; + + jit_uni_tbb_batch_normalization_fwd_t(const pd_t *apd); + ~jit_uni_tbb_batch_normalization_fwd_t(); + + status_t init(engine_t *engine) override; + + status_t execute(const exec_ctx_t &ctx) const override; + +private: + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr> bnorm_driver_; +}; + +template +struct jit_uni_tbb_batch_normalization_bwd_t : public primitive_t { + struct pd_t : public cpu_batch_normalization_bwd_pd_t { + pd_t(const batch_normalization_desc_t *adesc, + const primitive_attr_t *attr, + const batch_normalization_fwd_pd_t *hint_fwd_pd) + : cpu_batch_normalization_bwd_pd_t(adesc, attr, hint_fwd_pd) {} + + DECLARE_COMMON_PD_T( + JIT_IMPL_NAME_HELPER("bnorm_tbb_jit:", + (src_md()->data_type == data_type::bf16) + ? (mayiuse(avx512_core_bf16) + ? avx512_core_bf16 + : bf16_emulation_t::get_isa()) + : (src_md()->data_type == data_type::f16) + ? avx512_core_fp16 + : isa, + ""), + jit_uni_tbb_batch_normalization_bwd_t); + + status_t init(engine_t *engine); + + jit_memory_tag_kind_t tag_kind_; + }; + + jit_uni_tbb_batch_normalization_bwd_t(const pd_t *apd); + ~jit_uni_tbb_batch_normalization_bwd_t(); + + status_t init(engine_t *engine) override; + + status_t execute(const exec_ctx_t &ctx) const override; + +private: + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr> bnorm_driver_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino^=l0,\:0,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_x8s8s32x_1x1_conv_kernel.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_x8s8s32x_1x1_conv_kernel.hpp new file mode 100644 index 0000000000000000000000000000000000000000..bc9f85e18c4a7e8dab82b947b8da1ceb6d99493c --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_x8s8s32x_1x1_conv_kernel.hpp @@ -0,0 +1,184 @@ +/******************************************************************************* +* Copyright 2019-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_UNI_X8S8S32X_1X1_CONV_KERNEL_HPP +#define CPU_X64_JIT_UNI_X8S8S32X_1X1_CONV_KERNEL_HPP + +#include "common/c_types_map.hpp" +#include "common/memory_tracking.hpp" + +#include "cpu/x64/injectors/jit_uni_postops_injector.hpp" +#include "cpu/x64/jit_generator.hpp" +#include "cpu/x64/jit_primitive_conf.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +template +struct _jit_uni_x8s8s32x_1x1_conv_kernel : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(_jit_uni_x8s8s32x_1x1_conv_kernel) + _jit_uni_x8s8s32x_1x1_conv_kernel(const jit_1x1_conv_conf_t &ajcp, + const primitive_attr_t &attr, const memory_desc_t &dst_md); + + int get_tail_size() { return jcp.oc_without_padding % jcp.oc_block; } + + jit_1x1_conv_conf_t jcp; + const primitive_attr_t &attr_; + +private: + std::unique_ptr> + postops_injector_; + + enum { + ker_max_reg_idx = 13, + }; + const Xbyak::Reg64 reg_bcast_data = r8; + const Xbyak::Reg64 reg_ptr_scales = r8; + const Xbyak::Reg64 reg_output_data = r9; + const Xbyak::Reg64 reg_load_data = r10; + const Xbyak::Reg64 reg_ptr_sum_scale = r10; + const Xbyak::Reg64 reg_ptr_sum_zp = rdx; + const Xbyak::Reg64 reg_reduce_loop_work = r11; + const Xbyak::Reg64 reg_bias_data = r12; + const Xbyak::Reg64 reg_comp_data = r12; + const Xbyak::Reg64 reg_ptr_dst_scale = r12; + const Xbyak::Reg64 reg_init_bcast = r13; + const Xbyak::Reg64 reg_store_bcast = r13; + const Xbyak::Reg64 reg_reduce_loop_iter = r13; + const Xbyak::Reg64 aux_reg_bcast_data = r14; + const Xbyak::Reg64 aux_reg_load_data = r15; + const Xbyak::Reg64 aux_reg_saturation = r15; + const Xbyak::Reg64 reg_reduce_pos_flag = rax; + const Xbyak::Reg64 aux1_reg_bcast_data = rbx; + const Xbyak::Reg64 reg_bcast_loop_work = rbx; + const Xbyak::Reg64 reg_bcast_loop_iter = rdx; + const Xbyak::Reg64 reg_load_loop_work = rsi; + const Xbyak::Reg64 aux_reg_output_data = abi_not_param1; + // zero-point computation + const Xbyak::Reg64 reg_zp_compensation = aux_reg_load_data; // r15 + const Xbyak::Reg64 reg_src_zero_point = aux_reg_bcast_data; // r14 + const Xbyak::Reg64 reg_dst_zero_point = reg_src_zero_point; + + const Vmm vmm_tmp = Vmm(3); + const Vmm vmm_one = Vmm(2); + const Vmm vmm_zero = Vmm(1); + const Vmm vmm_shift = Vmm(1); + const Vmm vmm_bcast = Vmm(0); + const Vmm vmm_saturation = Vmm(0); + /* used during scale section of store_output */ + const Vmm vmm_scale = Vmm(1); + /* used during post_op sum section of store_output */ + const Vmm vmm_prev_dst = Vmm(1); + /* used during bias section of store_output */ + const Vmm vmm_comp = Vmm(0); // only for signed input + const Vmm vmm_bias = Vmm(3); + /* zero-point */ + const Vmm vmm_zp = Vmm(1); + const Vmm vmm_zp_comp = Vmm(2); + /* dst scale */ + const Vmm vmm_dst_scale = Vmm(1); + + constexpr static int simd_w = isa == avx2 ? 8 : 4; + constexpr static int reg64_size = sizeof(int64_t); + constexpr static int bcast_loop_work_off = 0; + constexpr static int reg_bias_data_off = 1 * reg64_size; + constexpr static int reg_bcast_data_off = 2 * reg64_size; + constexpr static int reg_load_data_off = 3 * reg64_size; + constexpr static int reg_ptr_sum_scale_off = 4 * reg64_size; + constexpr static int reg_bcast_loop_iter_off = 5 * reg64_size; + constexpr static int reg_comp_data_off = 6 * reg64_size; + constexpr static int reg_zp_compensation_off = 7 * reg64_size; + constexpr static int reg_src_zero_point_off = 8 * reg64_size; + constexpr static int reg_dst_zero_point_off = 9 * reg64_size; + constexpr static int reg_dst_scale_off = 10 * reg64_size; + constexpr static int stack_space_needed = 11 * reg64_size; + + int vreg_accum_idx( + const int load_loop_blk, const int i_load, const int i_ur); + Vmm vreg_accum(const int load_loop_blk, const int i_load, const int i_ur); + int output_ptr(const int i_load, const int i_ur); + void bcast_loop(int load_loop_blk); + void apply_sum(const int ur, const int load_loop_blk, + const bool mask_flag_in, const float *p_sum_scale, + const int32_t *p_sum_zp); + void apply_postops(const int ur, const int load_loop_blk, + const bool mask_flag_in, const float *p_sum_scale, + const int32_t *p_sum_zp); + void reduce_loop(int load_loop_blk, int ur, bool wraparound); + + void generate() override; + void cvt2ps(data_type_t type_in, const Vmm &vmm_in, const Xbyak::Reg64 ®, + int offset, int load_size); +}; + +template +struct jit_uni_x8s8s32x_1x1_conv_kernel { + + jit_uni_x8s8s32x_1x1_conv_kernel(const jit_1x1_conv_conf_t &ajcp, + const primitive_attr_t &attr, const memory_desc_t &dst_md) + : kernel_(nullptr) { + + switch (isa) { + case avx2: + kernel_ = new jit_avx2_x8s8s32x_1x1_conv_kernel( + ajcp, attr, dst_md); + return; + case sse41: + kernel_ = new jit_sse41_x8s8s32x_1x1_conv_kernel( + ajcp, attr, dst_md); + return; + default: assert(!"Current ISA is not supported!"); + } + } + + status_t create_kernel() { + if (kernel_) return kernel_->create_kernel(); + return status::out_of_memory; + } + + ~jit_uni_x8s8s32x_1x1_conv_kernel() { delete kernel_; } + + void operator()(const jit_1x1_conv_call_s *p) const { (*kernel_)(p); } + + static status_t init_conf(jit_1x1_conv_conf_t &jcp, + const convolution_desc_t &cd, const memory_desc_wrapper &src_d, + const memory_desc_wrapper &weights_d, + const memory_desc_wrapper &dst_d, const memory_desc_wrapper &bias_d, + primitive_attr_t &attr, int nthreads, bool reduce_src); + + static void init_scratchpad(memory_tracking::registrar_t &scratchpad, + const jit_1x1_conv_conf_t &jcp, const primitive_attr_t &attr); + + using jit_sse41_x8s8s32x_1x1_conv_kernel + = _jit_uni_x8s8s32x_1x1_conv_kernel; + using jit_avx2_x8s8s32x_1x1_conv_kernel + = _jit_uni_x8s8s32x_1x1_conv_kernel; + + constexpr static int simd_w = isa == avx2 ? 8 : 4; + +private: + DNNL_DISALLOW_COPY_AND_ASSIGN(jit_uni_x8s8s32x_1x1_conv_kernel); + jit_generator *kernel_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_x8s8s32x_1x1_convolution.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_x8s8s32x_1x1_convolution.hpp new file mode 100644 index 0000000000000000000000000000000000000000..95a11d27a9ef56fa4e9ed97a80a5133390e071de --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_x8s8s32x_1x1_convolution.hpp @@ -0,0 +1,388 @@ +/******************************************************************************* +* Copyright 2019-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_UNI_X8S8S32X_1X1_CONVOLUTION_HPP +#define CPU_X64_JIT_UNI_X8S8S32X_1X1_CONVOLUTION_HPP + +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/memory_tracking.hpp" +#include "common/primitive.hpp" +#include "common/primitive_hashing.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_convolution_pd.hpp" +#include "cpu/dw_convolution_utils.hpp" +#include "cpu/platform.hpp" + +#include "cpu/x64/jit_uni_1x1_conv_utils.hpp" +#include "cpu/x64/jit_uni_x8s8s32x_1x1_conv_kernel.hpp" +#include "cpu/x64/jit_uni_x8s8s32x_convolution.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +template +struct jit_uni_x8s8s32x_1x1_convolution_fwd_t : public primitive_t { + struct pd_t : public cpu_convolution_fwd_pd_t { + using dw_conv_pd_type = cpu_convolution_fwd_pd_t; + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const typename pd_t::base_class *hint_fwd_pd) + : cpu_convolution_fwd_pd_t(adesc, attr, hint_fwd_pd) + , jcp_() + , rtus_() + , jcp_dw_(nullptr) {} + + pd_t(const pd_t &other) : cpu_convolution_fwd_pd_t(other) { + if (copy(other) != status::success) is_initialized_ = false; + } + + DECLARE_COMMON_PD_T( + JIT_IMPL_NAME_HELPER("jit_uni_int8_1x1:", + isa == avx2 && jcp_.has_vnni ? avx2_vnni : isa, ""), + jit_uni_x8s8s32x_1x1_convolution_fwd_t); + + status_t init(engine_t *engine) { + using namespace data_type; + using smask_t = primitive_attr_t::skip_mask_t; + bool ok = is_fwd() + && set_default_alg_kind(alg_kind::convolution_direct) + && utils::one_of(src_md(0)->data_type, s8, u8) + && weights_md(0)->data_type == s8 + && IMPLICATION(with_bias(), + utils::one_of( + weights_md(1)->data_type, f32, s32, s8, u8)) + && utils::one_of(dst_md(0)->data_type, f32, s32, s8, u8) + && desc()->accum_data_type == s32 + && attr()->has_default_values(smask_t::scales_runtime + | smask_t::zero_points_runtime + | smask_t::post_ops | smask_t::sum_dt, + dst_md(0)->data_type) + && attr()->scales_.has_default_values( + {DNNL_ARG_SRC, DNNL_ARG_WEIGHTS, DNNL_ARG_DST, + DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_WEIGHTS, + DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_DST}) + && attr()->post_ops_.check_sum_consistency( + dst_md(0)->data_type, /* is_int8 */ true) + && !has_zero_dim_memory() && attr_scales_ok() + && zero_points_ok() + && set_default_formats_common( + dat_tag(), format_tag::any, dat_tag()) + && set_or_check_wei_format() + && attr_.set_default_formats(dst_md(0)) == status::success; + if (!ok) return status::unimplemented; + + const convolution_desc_t *conv_d = desc(); + const memory_desc_t *src_d = src_md(); + rtus_prepare(this, conv_d, src_d, dst_md(), weights_md()); + + CHECK(jit_uni_x8s8s32x_1x1_conv_kernel::init_conf(jcp_, + *conv_d, *src_d, *weights_md(), *dst_md(), + with_bias() ? *weights_md(1) : types::zero_md(), attr_, + dnnl_get_max_threads(), rtus_.reduce_src_)); + if (jcp_.with_dw_conv) CHECK(depthwise_po_init(engine)); + + auto scratchpad = scratchpad_registry().registrar(); + jit_uni_x8s8s32x_1x1_conv_kernel::init_scratchpad( + scratchpad, jcp_, *attr()); + + rtus_prepare_space_info(this, scratchpad, jcp_.nthr); + + return status::success; + } + + const memory_desc_t *dst_1x1_md(int index = 0) const { + return cpu_convolution_fwd_pd_t::dst_md(index); + } + + const memory_desc_t *dst_md( + int index = 0, bool user_input = false) const override { + return jcp_.with_dw_conv + ? dw_conv_pd_->dst_md(index, user_input) + : cpu_convolution_fwd_pd_t::dst_md(index, user_input); + } + + const memory_desc_t *arg_md( + int arg, bool user_input = false) const override { + if (jcp_.with_dw_conv) { + switch (arg) { + case DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_SRC: + return cpu_convolution_fwd_pd_t::dst_md(0, user_input); + case DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_WEIGHTS: + return dw_conv_pd_->weights_md(0); + case DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_BIAS: + return dw_conv_pd_->weights_md(1); + default: break; + } + } + return convolution_fwd_pd_t::arg_md(arg, user_input); + } + + arg_usage_t arg_usage(int arg) const override { + if (arg == (DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_WEIGHTS)) + return arg_usage_t::input; + + if (arg == (DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_BIAS) + && attr_post_op_dw_inputs() > 1) + return arg_usage_t::input; + + if (arg == (DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_ATTR_OUTPUT_SCALES) + && jcp_.with_dw_conv) + return arg_usage_t::input; + + return convolution_fwd_pd_t::arg_usage(arg); + } + + jit_1x1_conv_conf_t jcp_; + reduce_to_unit_stride_t rtus_; + jit_conv_conf_t *jcp_dw_; // doesn't own a resource + std::unique_ptr dw_conv_pd_; + using dw_pd_t = typename jit_uni_x8s8s32x_convolution_fwd_t::pd_t; + + protected: + bool zero_points_ok() const { + // Only common zero points are supported -> mask should only be 0 + int mask_src = 0, mask_dst = 0; + attr()->zero_points_.get(DNNL_ARG_SRC, &mask_src); + attr()->zero_points_.get(DNNL_ARG_DST, &mask_dst); + return attr()->zero_points_.has_default_values(DNNL_ARG_WEIGHTS) + && mask_src == 0 && mask_dst == 0; + } + + status_t copy(const pd_t &other) { + jcp_ = other.jcp_; + rtus_ = other.rtus_; + jcp_dw_ = nullptr; + if (other.dw_conv_pd_) { + dw_conv_pd_.reset(static_cast( + other.dw_conv_pd_->clone())); + if (!dw_conv_pd_) return status::out_of_memory; + + jcp_dw_ = &(static_cast(dw_conv_pd_.get())->jcp_); + } + return status::success; + } + + format_tag_t dat_tag() const { + return utils::pick(ndims() - 3, format_tag::nwc, format_tag::nhwc, + format_tag::ndhwc); + } + + bool set_or_check_wei_format() { + using namespace format_tag; + using namespace memory_extra_flags; + const auto zp = attr()->zero_points_; + const int c_mask = 0x1, + g_mask = 0x3; // mask for i/o-channel and ngroups + + const bool is_src_s8 = src_md_.data_type == data_type::s8; + const bool is_src_zero_point = !zp.has_default_values(DNNL_ARG_SRC); + format_tag_t wei_tag; + switch (isa) { + case avx2: + wei_tag = with_groups() + ? utils::pick(ndims() - 3, gOIw2i8o4i, gOIhw2i8o4i, + gOIdhw2i8o4i) + : utils::pick(ndims() - 3, OIw2i8o4i, OIhw2i8o4i, + OIdhw2i8o4i); + break; + case sse41: + wei_tag = with_groups() ? utils::pick(ndims() - 3, gOIw4o4i, + gOIhw4o4i, gOIdhw4o4i) + : utils::pick(ndims() - 3, OIw4o4i, + OIhw4o4i, OIdhw4o4i); + break; + default: assert(!"Current ISA is not supported!"); break; + } + + memory_desc_t want_wei_md = weights_md_; + memory_desc_init_by_tag(want_wei_md, wei_tag); + if (is_src_s8) { + want_wei_md.extra.flags + = 0 | compensation_conv_s8s8 | scale_adjust; + want_wei_md.extra.compensation_mask + = with_groups() ? g_mask : c_mask; + want_wei_md.extra.scale_adjust + = mayiuse(avx2_vnni) ? 1.0f : 0.5f; + } + if (is_src_zero_point) { + want_wei_md.extra.flags |= compensation_conv_asymmetric_src; + want_wei_md.extra.asymm_compensation_mask + = with_groups() ? g_mask : c_mask; + } + + if (weights_md_.format_kind == format_kind::any) { + weights_md_ = want_wei_md; + return true; + } + + return weights_md_ == want_wei_md; + } + + status_t depthwise_po_init(engine_t *engine) { + using namespace memory_tracking; + auto &jcp_1x1 = jcp_; + primitive_attr_t attr_1x1(*attr()); + if (!attr_1x1.is_initialized()) return status::out_of_memory; + + const auto &src_md = dst_md_; + const memory_desc_wrapper src_d(src_md); + const auto nthr = dnnl_get_max_threads(); + auto l2_cache = platform::get_per_core_cache_size(2) * nthr; + + // Note: A robust fusion implementation would be to check if both + // 1x1 conv and dw conv that are considered here for fusion are + // optimal independently. This would require creating a new + // primitive_desc through primitive_iterator & check if they match. + // Due to concern that these creations and/or checks could be heavy, + // for 1x1: Check that no better ISA is available. + // for dw: Always fuse with same ISA. + // Caveat: May be a better dw conv exists. + + bool ok = true && (!mayiuse(isa == avx2 ? avx512_core : avx2)) + && (attr_1x1.post_ops_.find(primitive_kind::sum) == -1) + // TODO: Below may be further tuned. + && (l2_cache < src_d.size()) + // load_grp_count check can be redundant due to l2 check + // above. Adding it explicitly as the current driver doesn't + // work if this condition fails. + && (jcp_1x1.load_grp_count < 2); + if (!ok) return status::unimplemented; + + int dw_po_index + = attr_1x1.post_ops_.find(primitive_kind::convolution); + + convolution_desc_t cd_dw; + primitive_attr_t attr_dw; + CHECK(get_depthwise_conv_desc( + cd_dw, src_md, attr_1x1, attr_dw, dw_po_index)); + + std::unique_ptr fusable_pd( + new dw_pd_t(&cd_dw, &attr_dw, nullptr)); + CHECK(fusable_pd->init(engine)); + jcp_dw_ = &(fusable_pd->jcp_); + dw_conv_pd_ = std::move(fusable_pd); + + ok = true + && (dnnl_memory_desc_equal(&src_md, dw_conv_pd_->src_md(0))) + && (jcp_1x1.oc_without_padding % jcp_1x1.oc_block == 0) + && IMPLICATION(jcp_dw_->ow_block, + jcp_dw_->ow_block == jcp_dw_->ow); + if (!ok) return status::unimplemented; + + assert(jcp_dw_); + assert(dw_conv_pd_->dst_md(0)->format_kind != format_kind::any); + assert(dw_conv_pd_->weights_md(0)->format_kind != format_kind::any); + assert(IMPLICATION( + dw_conv_pd_->weights_md(1)->data_type != data_type::undef, + dw_conv_pd_->weights_md(1)->format_kind + != format_kind::any)); + + jcp_dw_->is_fused_conv = true; + // TODO: Support/experiment arbitary oc_work in dw conv. + // Until then we keep ch_work perfectly divisible. + while (jcp_1x1.nb_load % jcp_1x1.nb_load_blocking != 0) + --jcp_1x1.nb_load_blocking; + jcp_1x1.nb_load_blocking_max = jcp_1x1.nb_load_blocking; + + while (jcp_1x1.nb_load_blocking % jcp_dw_->nb_ch_blocking != 0) + --jcp_dw_->nb_ch_blocking; + + jcp_dw_->dw_conv_buffer_oc + = jcp_1x1.nb_load_blocking * jcp_1x1.oc_block; + jcp_1x1.bcast_loop_output_step = jcp_1x1.ur + * (jcp_1x1.nb_load_blocking * jcp_1x1.oc_block) + * jcp_1x1.typesize_out; + + registrar_t scratchpad(scratchpad_registry_); + registrar_t dw_scratchpad(scratchpad, names::prefix_fusion); + + size_t dw_conv_buffer_size_ = (size_t)nthr * jcp_dw_->kh + * jcp_dw_->iw * jcp_dw_->dw_conv_buffer_oc; + assert(dw_conv_buffer_size_); + dw_scratchpad.book(memory_tracking::names::key_fusion_inout_buffer, + dw_conv_buffer_size_, + types::data_type_size(dw_conv_pd_->src_md()->data_type)); + + dw_conv_kernel_t::init_scratchpad( + dw_scratchpad, *jcp_dw_, *(dw_conv_pd_->attr())); + + return status::success; + } + }; + + template + friend status_t init_rtus_driver(conv_t *self); + + using fusable_pd_type = + typename jit_uni_x8s8s32x_convolution_fwd_t::pd_t; + + jit_uni_x8s8s32x_1x1_convolution_fwd_t(const pd_t *apd) + : primitive_t(apd) {} + + // Note: In case of fused depthwise convolution, the final output data type + // after fusion may not be same as for dst. + typedef typename prec_traits::type acc_data_t; + + status_t init(engine_t *engine) override { + CHECK(safe_ptr_assign(kernel_, + new jit_uni_x8s8s32x_1x1_conv_kernel( + pd()->jcp_, *pd()->attr(), *pd()->dst_1x1_md()))); + CHECK(kernel_->create_kernel()); + + if (pd()->jcp_.with_dw_conv) { + CHECK(safe_ptr_assign(kernel_dw_, + new dw_conv_kernel_t(*(pd()->jcp_dw_), + *(pd()->dw_conv_pd_->attr()), + *(pd()->dw_conv_pd_->dst_md())))); + CHECK(kernel_dw_->create_kernel()); + } + + CHECK(init_rtus_driver(this)); + return status::success; + } + + status_t execute(const exec_ctx_t &ctx) const override { + return execute_forward(ctx); + } + +private: + status_t execute_forward(const exec_ctx_t &ctx) const; + void execute_forward_thr(const int ithr, const int nthr, const char *src, + const char *weights, const char *bias, const char *weights_dw, + const char *bias_dw, char *dst, const float *oscales, + const float *dst_scales, const float *dw_oscales, + const float *dw_dst_scales, const int32_t *src_zero_point, + const int32_t *dst_zero_point, + const memory_tracking::grantor_t &scratchpad, + const void *post_ops_binary_rhs_arg_vec, + const void *post_ops_binary_rhs_arg_vec_dw) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr> kernel_; + std::unique_ptr> rtus_driver_; + using dw_conv_kernel_t = jit_uni_x8s8s32x_fwd_kernel; + std::unique_ptr kernel_dw_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_x8s8s32x_1x1_deconvolution.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_x8s8s32x_1x1_deconvolution.hpp new file mode 100644 index 0000000000000000000000000000000000000000..4beb3cc91c4ec8d3700e8b2cc57e22dcc56b7dd4 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_x8s8s32x_1x1_deconvolution.hpp @@ -0,0 +1,158 @@ +/******************************************************************************* +* Copyright 2020-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* *******************************************************************************/ + +#ifndef CPU_X64_JIT_UNI_X8S8S32X_1X1_DECONVOLUTION_HPP +#define CPU_X64_JIT_UNI_X8S8S32X_1X1_DECONVOLUTION_HPP + +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/primitive.hpp" +#include "common/primitive_desc_iterator.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_convolution_pd.hpp" +#include "cpu/cpu_deconvolution_pd.hpp" + +#include "cpu/x64/jit_uni_1x1_conv_utils.hpp" +#include "cpu/x64/jit_uni_x8s8s32x_1x1_convolution.hpp" +#include "cpu/zero_point_utils.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +template +struct jit_uni_x8s8s32x_1x1_deconvolution_fwd_t : public primitive_t { + struct pd_t : public cpu_deconvolution_fwd_pd_t { + pd_t(const deconvolution_desc_t *adesc, const primitive_attr_t *attr, + const deconvolution_fwd_pd_t *hint_fwd_pd) + : cpu_deconvolution_fwd_pd_t(adesc, attr, hint_fwd_pd) {} + + pd_t(const pd_t &other) + : cpu_deconvolution_fwd_pd_t(other) + , conv_pd_(other.conv_pd_->clone()) {} + + ~pd_t() = default; + + DECLARE_COMMON_PD_T( + conv_pd_->name(), jit_uni_x8s8s32x_1x1_deconvolution_fwd_t); + + status_t init_convolution(engine_t *engine) { + convolution_desc_t cd; + + auto dd = desc(); + CHECK(conv_desc_init(&cd, prop_kind::forward_training, + alg_kind::convolution_direct, &(dd->src_desc), + &(dd->weights_desc), &(dd->bias_desc), &(dd->dst_desc), + dd->strides, dd->dilates, dd->padding[0], dd->padding[1])); + + primitive_attr_t conv_attr(*attr()); + if (!conv_attr.is_initialized()) return status::out_of_memory; + primitive_desc_iterator_t it( + engine, (op_desc_t *)&cd, &conv_attr, nullptr); + if (!it.is_initialized()) return status::out_of_memory; + + while (++it != it.end()) { + conv_pd_ = *it; + // XXX: find another way to create required implementation. + if (dynamic_cast(conv_pd_.get())) + return set_default_params(); + } + + return status::unimplemented; + }; + + status_t init(engine_t *engine) { + using namespace data_type; + using skip_mask_t = primitive_attr_t::skip_mask_t; + bool ok = is_fwd() + && desc()->alg_kind == alg_kind::deconvolution_direct + && !has_zero_dim_memory() + && utils::one_of(src_md(0)->data_type, s8, u8) + && weights_md(0)->data_type == s8 + && IMPLICATION(with_bias(), + utils::one_of( + weights_md(1)->data_type, f32, s32, s8, u8)) + && utils::one_of(dst_md(0)->data_type, f32, s32, s8, u8) + && desc()->accum_data_type == s32 + && attr()->has_default_values(skip_mask_t::scales_runtime + | skip_mask_t::post_ops + | skip_mask_t::zero_points_runtime) + && zero_points_valid( + attr(), true /*per_oc_bcast_accepted*/); + if (!ok) return status::unimplemented; + + CHECK(init_convolution(engine)); + CHECK(attr_.set_default_formats(dst_md(0))); + init_scratchpad(); + + return status::success; + } + + protected: + status_t set_default_params() { + auto conv_1x1_pd_ = static_cast(conv_pd_.get()); + src_md_ = *conv_1x1_pd_->src_md(); + dst_md_ = *conv_1x1_pd_->dst_md(); + weights_md_ = *conv_1x1_pd_->weights_md(); + if (with_bias()) bias_md_ = *conv_1x1_pd_->weights_md(1); + return status::success; + } + + using conv_pd_t = + typename jit_uni_x8s8s32x_1x1_convolution_fwd_t::pd_t; + friend jit_uni_x8s8s32x_1x1_deconvolution_fwd_t; + + std::shared_ptr conv_pd_; + + private: + void init_scratchpad() { + auto scratchpad = scratchpad_registry().registrar(); + scratchpad.book(memory_tracking::names::key_nested, + conv_pd_->scratchpad_registry()); + } + }; + + jit_uni_x8s8s32x_1x1_deconvolution_fwd_t(const pd_t *apd) + : primitive_t(apd) {} + + status_t init(engine_t *engine) override { + pd()->conv_pd_->create_primitive(conv_p_, engine); + return status::success; + } + + status_t execute(const exec_ctx_t &ctx) const override { + nested_scratchpad_t ns( + ctx, memory_tracking::names::key_nested, conv_p_); + // XXX: create a new ctx for convolution? + auto &tmp_ctx = const_cast(ctx); + tmp_ctx.set_scratchpad_grantor(ns.grantor()); + return conv_p_->execute(tmp_ctx); + } + +private: + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + std::shared_ptr conv_p_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif /* CPU_X64_JIT_UNI_X8S8S32X_1X1_DECONVOLUTION_HPP */ diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_x8s8s32x_conv_kernel.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_x8s8s32x_conv_kernel.hpp new file mode 100644 index 0000000000000000000000000000000000000000..4c83b5ac3ba9b8d2f105d8db219b741c4ece0f2e --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_x8s8s32x_conv_kernel.hpp @@ -0,0 +1,240 @@ +/******************************************************************************* +* Copyright 2019-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_UNI_X8S8S32X_CONV_KERNEL_HPP +#define CPU_X64_JIT_UNI_X8S8S32X_CONV_KERNEL_HPP + +#include "common/c_types_map.hpp" +#include "common/memory_tracking.hpp" + +#include "cpu/x64/injectors/jit_uni_postops_injector.hpp" +#include "cpu/x64/jit_generator.hpp" +#include "cpu/x64/jit_primitive_conf.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +template +struct _jit_uni_x8s8s32x_fwd_kernel : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(_jit_uni_x8s8s32x_conv_fwd_ker_t_) + + _jit_uni_x8s8s32x_fwd_kernel(const jit_conv_conf_t &ajcp, + const primitive_attr_t &attr, const memory_desc_t &dst_md); + + jit_conv_conf_t jcp; + const primitive_attr_t &attr_; + +private: + constexpr static int isa_simd_width_ + = cpu_isa_traits::vlen / sizeof(float); + std::unique_ptr> + postops_injector_; + enum { + typesize = sizeof(float), + ic_sub_step = 4, + ker_zp_reg_base_idx = 9, + ker_reg_base_idx = 12, + ker_dw_reg_base_idx = 14, + ker_max_reg = 15, + }; + enum ic_block_t { + no_last_block, + last_ic_block, + last_sp_block, + }; + + /* data registers */ + const Xbyak::Reg64 reg_ptr_scales = rax; + const Xbyak::Reg64 reg_ptr_saturation_ubound = rax; + const Xbyak::Reg64 reg_inp = r8; + const Xbyak::Reg64 reg_ker = r9; + const Xbyak::Reg64 reg_out = r10; + const Xbyak::Reg64 aux_reg_inp = r11; + const Xbyak::Reg64 reg_ptr_sum_scale = r11; + const Xbyak::Reg64 reg_ptr_sum_zp = rdx; + const Xbyak::Reg64 aux_reg_ker = r12; + const Xbyak::Reg64 aux_reg_inp_d = r13; + const Xbyak::Reg64 reg_compensation = r14; + const Xbyak::Reg64 aux_reg_ker_d = r15; + const Xbyak::Reg64 reg_ker_long_offt = r13; + + /* counter regs */ + const Xbyak::Reg64 reg_oi = rbx; + const Xbyak::Reg64 reg_bias = rdx; + const Xbyak::Reg64 reg_oc_blocks = rsi; + const Xbyak::Reg64 reg_owb = aux_reg_ker; + const Xbyak::Reg64 reg_scratch = reg_compensation; + const Xbyak::Reg64 reg_ki = reg_compensation; + const Xbyak::Reg64 reg_kj = reg_ptr_scales; + const Xbyak::Reg64 reg_overflow = reg_ptr_scales; + const Xbyak::Reg64 reg_icb = reg_bias; + // Using 3d regs as depthwise3d is not yet supported + const Xbyak::Reg64 reg_inp_buffer_ptr = aux_reg_inp_d; + const Xbyak::Reg64 aux_reg_inp_buffer_ptr = aux_reg_ker_d; + const Xbyak::Reg64 reg_jmp_tbl_base = reg_kj; + // zero-point computation + const Xbyak::Reg64 reg_zp_compensation = aux_reg_inp; + const Xbyak::Reg64 reg_src_zero_point = aux_reg_ker_d; + const Xbyak::Reg64 reg_dst_zero_point = reg_src_zero_point; + // dst scale + const Xbyak::Reg64 reg_dst_scale = reg_dst_zero_point; + + /* binary post-ops operand */ + const Xbyak::Reg64 temp_offset_reg = r12; + + const Vmm vmm_wei = Vmm(0); + /* used during bias/comp/scale section of store_output */ + const Vmm vmm_bias = Vmm(0); + const Vmm vmm_comp = Vmm(2); // only for signed input + const Vmm vmm_scale = Vmm(1); + /* used during post_op sum section of store_output */ + const Vmm vmm_prev_dst = Vmm(0); + /* used during write-out section of store_output */ + const Vmm vmm_zero = Vmm(0); + const Vmm vmm_saturation = Vmm(0); + /* used for zero-point */ + const Vmm vmm_zp = Vmm(6); + const Vmm vmm_zp_one = Vmm(5); + const Vmm vmm_zp_comp = vmm_zp_one; + const Vmm vmm_zp_dw_tmp = vmm_zp_one; + /* dst scale */ + const Vmm vmm_dst_scale = Vmm(0); + + /* used in compute_ker (but set during prepare_output) */ + const Vmm vmm_shift = Vmm(1); // only for signed input + /* used in compute_ker */ + const Vmm vmm_tmp = Vmm(2); // not used for depthwise + const Vmm vmm_one + = Vmm(3); // set at start of kernel, not used for depthwise. + /* used only for depthwise */ + Vmm vmm_dw_tmp; + Vmm vmm_dw_src; + + int vmm_out_idx(int i_ur, int i_oc) { + const int idx_limit = jcp.src_zero_point ? ker_zp_reg_base_idx + : jcp.is_depthwise ? ker_dw_reg_base_idx - jcp.signed_input + : ker_reg_base_idx; + const int nb_x_blocking + = jcp.is_depthwise ? jcp.nb_ch_blocking : jcp.nb_oc_blocking; + const int idx = i_ur * nb_x_blocking + i_oc; + assert(idx < idx_limit); + MAYBE_UNUSED(idx_limit); + /* remap register indices from 4 to 15 + * to avoid passing xmm0 to comp*/ + return ker_max_reg - idx; + } + Vmm vmm_out(int i_ur, int i_oc) { + const int idx = vmm_out_idx(i_ur, i_oc); + return Vmm(idx); + } + Vmm vmm_inp(int i_ic, int nb_x_blocking) { + int idx = i_ic + nb_x_blocking * jcp.ur_w; + assert(idx < ker_max_reg); + return Vmm(ker_max_reg - idx); + } + int get_ow_start(int ki, int pad_l) { + return nstl::max(0, + utils::div_up(pad_l - ki * (jcp.dilate_w + 1), jcp.stride_w)); + } + int get_ow_end(int ur_w, int ki, int pad_r) { + return ur_w + - nstl::max(0, + utils::div_up( + pad_r - (jcp.kw - 1 - ki) * (jcp.dilate_w + 1), + jcp.stride_w)); + } + int get_blocking_size() { + return jcp.is_depthwise ? jcp.ch_block : jcp.oc_block; + } + int get_tail_size() { + return jcp.is_depthwise ? jcp.ngroups % jcp.ch_block + : jcp.oc_without_padding % jcp.oc_block; + } + + void prepare_output(int ur_w); + void store_output(int ur_w, bool last_oc_block_flag); + void compute_ker_dw(int ur_w, int pad_l, int pad_r, + ic_block_t last_ic_block_flag, bool h_padded); + void compute_ker(int ur_w, int pad_l, int pad_r, + ic_block_t last_ic_block_flag, bool h_padded = false); + void kh_loop(int ur_w, int pad_l, int pad_r, ic_block_t last_ic_block_flag); + void icb_loop(int ur_w, int pad_l, int pad_r, bool is_last_spatial_block); + void generate() override; + + void cvt2ps(data_type_t type_in, const Vmm &vmm_in, const Xbyak::Reg64 ®, + int offset, int load_size); + void apply_sum(const int nb_oc_block, const int ur_w, + const bool last_oc_block_flag, const int oc_block, + const float *p_sum_scale, const int32_t *p_sum_zp); + void apply_postops(const int nb_oc_block, const int ur_w, + const bool last_oc_block_flag, const int oc_block, + const float *p_sum_scale, const int32_t *p_sum_zp); +}; + +template +struct jit_uni_x8s8s32x_fwd_kernel { + + jit_uni_x8s8s32x_fwd_kernel(const jit_conv_conf_t &ajcp, + const primitive_attr_t &attr, const memory_desc_t &dst_md) + : kernel_(nullptr) { + int ch_block = ajcp.is_depthwise ? ajcp.ch_block : ajcp.ic_block; + switch (ch_block) { + case 8: + if (utils::one_of(isa, avx2)) { + kernel_ = new _jit_uni_x8s8s32x_fwd_kernel( + ajcp, attr, dst_md); + } else + assert(!"invalid channel blocking for current ISA"); + return; + case 4: + kernel_ = new _jit_uni_x8s8s32x_fwd_kernel( + ajcp, attr, dst_md); + return; + default: assert(!"invalid channel blocking"); + } + } + + status_t create_kernel() { + if (kernel_) return kernel_->create_kernel(); + return status::out_of_memory; + } + + ~jit_uni_x8s8s32x_fwd_kernel() { delete kernel_; } + + void operator()(const jit_conv_call_s *p) const { (*kernel_)(p); } + + static status_t init_conf(jit_conv_conf_t &jcp, + const convolution_desc_t &cd, memory_desc_t &src_pd, + memory_desc_t &weights_pd, memory_desc_t &dst_pd, + memory_desc_t &bias_pd, primitive_attr_t &attr, int nthreads); + static void init_scratchpad(memory_tracking::registrar_t &scratchpad, + const jit_conv_conf_t &jcp, const primitive_attr_t &attr); + + void (*jit_ker)(jit_conv_call_s *); + +private: + DNNL_DISALLOW_COPY_AND_ASSIGN(jit_uni_x8s8s32x_fwd_kernel); + jit_generator *kernel_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_x8s8s32x_convolution.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_x8s8s32x_convolution.hpp new file mode 100644 index 0000000000000000000000000000000000000000..b03718f4c7455bcd7a70363cd2a74778373266d5 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_x8s8s32x_convolution.hpp @@ -0,0 +1,136 @@ +/******************************************************************************* +* Copyright 2019-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_UNI_X8S8S32X_CONVOLUTION_HPP +#define CPU_X64_JIT_UNI_X8S8S32X_CONVOLUTION_HPP + +#include "common/c_types_map.hpp" +#include "common/dnnl_thread.hpp" +#include "common/memory_tracking.hpp" +#include "common/primitive.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_convolution_pd.hpp" + +#include "cpu/x64/jit_uni_x8s8s32x_conv_kernel.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +template +struct jit_uni_x8s8s32x_convolution_fwd_t : public primitive_t { + struct pd_t : public cpu_convolution_fwd_pd_t { + pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr, + const typename pd_t::base_class *hint_fwd_pd) + : cpu_convolution_fwd_pd_t(adesc, attr, hint_fwd_pd), jcp_() {} + + DECLARE_COMMON_PD_T( + JIT_IMPL_NAME_HELPER("jit_uni_int8:", + isa == avx2 && jcp_.has_vnni ? avx2_vnni : isa, ""), + jit_uni_x8s8s32x_convolution_fwd_t); + + status_t init(engine_t *engine) { + using namespace data_type; + using smask_t = primitive_attr_t::skip_mask_t; + const bool args_ok = is_fwd() + && set_default_alg_kind(alg_kind::convolution_direct) + && utils::one_of(src_md(0)->data_type, s8, u8) + && weights_md(0)->data_type == s8 + && IMPLICATION(with_bias(), + utils::one_of( + weights_md(1)->data_type, f32, s32, s8, u8)) + && utils::one_of(dst_md(0)->data_type, f32, s32, s8, u8) + && desc()->accum_data_type == s32 + && attr()->has_default_values(smask_t::scales_runtime + | smask_t::zero_points_runtime + | smask_t::post_ops | smask_t::sum_dt, + dst_md(0)->data_type) + && attr()->post_ops_.check_sum_consistency( + dst_md(0)->data_type, /* is_int8 */ true) + && !has_zero_dim_memory() && attr_scales_ok() + && zero_points_ok(); + if (!args_ok) return status::unimplemented; + + CHECK(jit_uni_x8s8s32x_fwd_kernel::init_conf(jcp_, *desc(), + src_md_, weights_md_, dst_md_, bias_md_, attr_, + dnnl_get_max_threads())); + + auto scratchpad = scratchpad_registry().registrar(); + jit_uni_x8s8s32x_fwd_kernel::init_scratchpad( + scratchpad, jcp_, *attr()); + + return attr_.set_default_formats(dst_md(0)); + } + + jit_conv_conf_t jcp_; + + protected: + bool zero_points_ok() const { + // Only common zero points are supported -> mask should only be 0 + int mask_src = 0, mask_dst = 0; + attr()->zero_points_.get(DNNL_ARG_SRC, &mask_src); + attr()->zero_points_.get(DNNL_ARG_DST, &mask_dst); + return attr()->zero_points_.has_default_values(DNNL_ARG_WEIGHTS) + && mask_src == 0 && mask_dst == 0; + } + }; + + jit_uni_x8s8s32x_convolution_fwd_t(const pd_t *apd) : primitive_t(apd) {} + + status_t init(engine_t *engine) override { + CHECK(safe_ptr_assign(kernel_, + new jit_uni_x8s8s32x_fwd_kernel( + pd()->jcp_, *pd()->attr(), *pd()->dst_md()))); + return kernel_->create_kernel(); + } + + status_t execute(const exec_ctx_t &ctx) const override { + const auto &_pd = pd(); + const int ndims = _pd->ndims(); + const bool is_dw = _pd->jcp_.is_depthwise; + + switch (ndims) { + case 3: return execute_forward_1d(ctx); + case 4: + if (is_dw) return execute_forward_2d_dw(ctx); + return execute_forward_2d(ctx); + case 5: return execute_forward_3d(ctx); + } + return status::unimplemented; + } + +private: + status_t execute_forward_1d(const exec_ctx_t &ctx) const; + status_t execute_forward_2d(const exec_ctx_t &ctx) const; + status_t execute_forward_3d(const exec_ctx_t &ctx) const; + status_t execute_forward_2d_dw(const exec_ctx_t &ctx) const; + const pd_t *pd() const { + return static_cast(primitive_t::pd().get()); + } + const float *adjust_oscales(const memory_tracking::grantor_t &scratchpad, + const float *src_scales, const float *wei_scales) const; + + std::unique_ptr> kernel_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_x8s8s32x_deconvolution.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_x8s8s32x_deconvolution.hpp new file mode 100644 index 0000000000000000000000000000000000000000..4385fb0265a0db54c515d78eb7dbab4520157985 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_x8s8s32x_deconvolution.hpp @@ -0,0 +1,224 @@ +/******************************************************************************* +* Copyright 2020-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_UNI_X8S8S32X_DECONVOLUTION_HPP +#define CPU_X64_JIT_UNI_X8S8S32X_DECONVOLUTION_HPP + +#include +#include + +#include "common/c_types_map.hpp" +#include "common/primitive.hpp" + +#include "cpu/cpu_deconvolution_pd.hpp" + +#include "cpu/x64/jit_generator.hpp" +#include "cpu/x64/jit_primitive_conf.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +namespace zp { +class jit_uni_deconv_zp_pad_str_kernel_base_t; +} // namespace zp + +namespace injector { +template +class jit_uni_postops_injector_t; +} // namespace injector + +using namespace Xbyak; + +template +struct _jit_uni_x8s8s32x_deconv_fwd_kernel : public jit_generator { + DECLARE_CPU_JIT_AUX_FUNCTIONS(_jit_uni_x8s8s32x_deconv_fwd_kernel); + + _jit_uni_x8s8s32x_deconv_fwd_kernel(const jit_conv_conf_t &ajcp, + const primitive_attr_t &attr, const memory_desc_wrapper &dst_d); + ~_jit_uni_x8s8s32x_deconv_fwd_kernel(); + + const jit_conv_conf_t jcp_; + +private: + std::unique_ptr> + postops_injector_; + using reg64_t = const Xbyak::Reg64; + + static constexpr dim_t IC_SUB_STEP = 4; + const int ker_max_regs_ = -1; + + enum ker_block_t { + no_last_block = 0x1U, + last_ic_block = 0x2U, + last_sp_block = 0x4U, + }; + + /* data regs */ + const reg64_t reg_src_ = r8; + const reg64_t reg_filt_ = r9; + const reg64_t reg_dst_ = r10; + const reg64_t param1_ = abi_param1; + const reg64_t reg_kh_ = abi_not_param1; + const reg64_t reg_ki_ = r14; + + const reg64_t reg_nur_w_ = rbx; + const reg64_t reg_bias_ = rdx; + const reg64_t reg_icb_ = reg_bias_; + const reg64_t reg_ptr_scales_ = rax; + const reg64_t reg_ptr_dst_scales_ = abi_not_param1; + const reg64_t reg_ptr_saturation_ubound_ = rax; + const reg64_t reg_oc_blocks_ = rsi; + + const reg64_t aux_reg_src_ = r11; + const reg64_t aux_reg_filt_ = r12; + + const reg64_t aux_reg_src_d_ = r13; + const reg64_t aux_reg_filt_d_ = r15; + + const reg64_t reg_compensation_ = r14; + const reg64_t reg_scratch_ = r14; + const reg64_t reg_ptr_sum_scale_ = r11; + const reg64_t reg_ptr_sum_zp_ = r15; + const reg64_t reg_overflow_ = rax; + const reg64_t reg_comp_strides_ = reg_overflow_; + const reg64_t reg_ker_long_offt_ = r15; + const reg64_t reg_zp_dst_ = r15; + const reg64_t reg_zp_src_ = r15; + const reg64_t reg_zp_compensation_ = r11; + const Xbyak::Address zp_src_pad_comp_addr_ = ptr[rsp]; + const Xbyak::Address reg_scratch_preserved_ = ptr[rsp + 8]; + static constexpr int reserved_stack_size_ = 16; + + const Vmm vmm_tmp_ = Vmm(3); + const Vmm vmm_one_ = Vmm(2); + /* used during write-out section of store_output */ + const Vmm vmm_zero_ = Vmm(0); + const Vmm vmm_saturation_ = vmm_zero_; + const Vmm vmm_wei_ = vmm_zero_; + const Vmm vmm_scale_ = vmm_zero_; + const Vmm vmm_dst_scale_ = vmm_zero_; + /* signed input */ + const Vmm vmm_shift_ = Vmm(1); + const Vmm vmm_comp_ = Vmm(1); + const Vmm vmm_bias_ = vmm_zero_; + const Vmm vmm_prev_dst_ = vmm_zero_; + const Vmm vmm_sum_zp_ = vmm_tmp_; + + Vmm vmm_out(int i_ur, int i_oc) const; + Vmm vmm_inp(int i_ic, int nb_x_blocking) const; + + int get_ow_start(int ki, int l_overflow) const noexcept; + int get_ow_end(int ur_w, int ki, int r_overflow) const noexcept; + int get_blocking_size() const noexcept; + int get_tail_size() const noexcept; + + void prepare_output(int ur_w); + void apply_postops(int ur_w, bool last_oc_block, const float *p_sum_scale, + const int32_t *p_sum_zp); + void store_output(int ur_w, bool last_oc_block); + void compute_ker(int ur_w, int l_overflow, int r_overflow, + ker_block_t last_ic_block_flag, bool h_padded = false); + void compute(const Vmm vreg_acc, const Vmm vreg_wei, const Vmm vreg_src); + std::function prepare_round_robin_vmm_inp_generator( + int ur_w) const noexcept; + void apply_zp_src_pad_str_comp( + int ur_w, int l_overflow, int r_overflow, bool h_padded); + void append_zp_src_pad_str_comp(int ur_w, int l_overflow, int r_overflow, + bool h_padded, bool last_oc_block); + void kh_loop(int ur_w, int pad_l, int pad_r, ker_block_t last_ker_block); + void icb_loop(int ur_w, int pad_l, int pad_r, bool last_block); + void generate() override; + void cvt2ps(data_type_t type_in, const Vmm vmm_in, const Reg64 reg, + int offset, int load_size); +}; + +template +struct jit_uni_x8s8s32x_deconv_fwd_kernel { + + jit_uni_x8s8s32x_deconv_fwd_kernel(const jit_conv_conf_t &ajcp, + const primitive_attr_t &attr, const memory_desc_wrapper &dst_d); + + status_t create_kernel() { + if (kernel_) return kernel_->create_kernel(); + return status::out_of_memory; + } + + ~jit_uni_x8s8s32x_deconv_fwd_kernel(); + + void operator()(const jit_deconv_call_s *p) const { (*kernel_)(p); } + + static bool post_ops_ok(jit_conv_conf_t &jcp, + const memory_desc_wrapper &dst_d, const primitive_attr_t &attr); + + static status_t init_conf(jit_conv_conf_t &jcp, + const deconvolution_desc_t &cd, memory_desc_t &src_md, + memory_desc_t &weights_md, memory_desc_t &dst_md, + const bool with_bias, memory_desc_t &bias_md, + primitive_attr_t &attr, int nthreads); + + static void init_scratchpad(memory_tracking::registrar_t &scratchpad, + const jit_conv_conf_t &jcp, const primitive_attr_t &attr); + + using _jit_avx2_x8s8s32x_deconv_fwd_kernel + = _jit_uni_x8s8s32x_deconv_fwd_kernel; + +private: + DNNL_DISALLOW_COPY_AND_ASSIGN(jit_uni_x8s8s32x_deconv_fwd_kernel); + std::unique_ptr kernel_; +}; + +template +struct jit_uni_x8s8s32x_deconvolution_fwd_t : public primitive_t { + struct pd_t : public cpu_deconvolution_fwd_pd_t { + using cpu_deconvolution_fwd_pd_t::cpu_deconvolution_fwd_pd_t; + + DECLARE_COMMON_PD_T( + JIT_IMPL_NAME_HELPER("jit_uni_int8:", + isa == avx2 && jcp_.has_vnni ? avx2_vnni : isa, ""), + jit_uni_x8s8s32x_deconvolution_fwd_t); + + status_t init(engine_t *engine); + jit_conv_conf_t jcp_; + }; + + jit_uni_x8s8s32x_deconvolution_fwd_t(const pd_t *apd); + ~jit_uni_x8s8s32x_deconvolution_fwd_t(); + + status_t init(engine_t *engine) override; + status_t execute(const exec_ctx_t &ctx) const override; + +private: + status_t execute_forward_1d(const exec_ctx_t &ctx) const; + status_t execute_forward_2d(const exec_ctx_t &ctx) const; + status_t execute_forward_3d(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + const float *adjust_oscales(const memory_tracking::grantor_t &scratchpad, + const float *src_scales, const float *wei_scales) const; + std::unique_ptr> kernel_; + std::unique_ptr + zp_src_pad_comp_kernel_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_xf16_sum.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_xf16_sum.hpp new file mode 100644 index 0000000000000000000000000000000000000000..99b15d85f0802af52599a45218168f99fe12aa7f --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/jit_uni_xf16_sum.hpp @@ -0,0 +1,330 @@ +/******************************************************************************* +* Copyright 2019-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_UNI_XF16_SUM_HPP +#define CPU_X64_JIT_UNI_XF16_SUM_HPP + +#include "common/c_types_map.hpp" +#include "common/primitive.hpp" + +#include "cpu/cpu_sum_pd.hpp" +#include "cpu/x64/jit_avx512_core_bf16cvt.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +struct jit_sum_conf_t { + int num_srcs; + cpu_isa_t isa; + data_type_t src_dt; + data_type_t dst_dt; + int unroll_reg_count; + int is_bf16_dst; + int typesize_in; + int typesize_out; + int loop_unroll; + int size_blocking; /* minimum recommended data blocking size as this + number of elements computes main unrolled loop + in jit kernel per iteration */ +}; + +struct jit_sum_call_t { + const void **srcs; + const void *dst; + const void *scales; + dim_t size; +}; + +template +struct jit_uni_xf16_sum_kernel_t : public jit_generator { + jit_uni_xf16_sum_kernel_t(jit_sum_conf_t ajsp, unsigned int num_acc_iters) + : jit_generator(jit_name()) + , jsp(ajsp) + , reg_src {r8, r9, r10, r11, r12, r13, r14, r15} + , num_acc_iters(num_acc_iters) {} + + ~jit_uni_xf16_sum_kernel_t() {} + + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_uni_xf16_sum_kernel_t) + + jit_sum_conf_t jsp; + +protected: + using reg64_t = const Xbyak::Reg64; + using reg32_t = const Xbyak::Reg32; + + reg64_t reg_src[8]; + + reg64_t param = abi_param1; /* may be rcx, note that cl is required + for mask computation */ + reg64_t reg_srcs = abi_not_param1; /* may be rcx, note that cl is required + for mask computation */ + reg64_t reg_dst = rax; + reg64_t reg_scales = rbx; + reg64_t reg_sz = rdx; + + const int num_acc_iters; + + Xbyak::Label exit_label; + + virtual int acc_vreg_idx(int i_unroll, int i_acc) = 0; + virtual int scale_vreg_idx(int i_acc_iter) = 0; + virtual int src_vreg_idx(int i_unroll, int i_inp) = 0; + virtual int tmp_vreg_idx(int i_unroll, int i_acc_iter) = 0; + virtual void pre_compute_init() = 0; + virtual void broadcast_scale(int scale_iter) = 0; + virtual void read_iter(int acc_iter, int u_idx, int src_shift) = 0; + virtual void add_iter(int acc_iter, int u_idx) = 0; + virtual void write_iter(int u_idx, int dst_shift) = 0; + void loop_iteration(int current_unroll); + virtual void tail_iteration() = 0; + virtual void index_tables() = 0; + void generate() override; +}; + +struct jit_avx512_core_bf16_sum_kernel_t + : jit_uni_xf16_sum_kernel_t { + jit_avx512_core_bf16_sum_kernel_t(jit_sum_conf_t ajsp) + : jit_uni_xf16_sum_kernel_t( + ajsp, utils::div_up(ajsp.num_srcs, 2)) + , max_vregs_available(cpu_isa_traits::n_vregs + - (isa_has_bf16(jsp.isa) ? 1 : 6)) + , bf16_emu_(nullptr) { + if (!mayiuse(avx512_core_bf16)) + bf16_emu_ = new bf16_emulation_t(this, bf16_emu_reserved_1, + bf16_emu_reserved_2, bf16_emu_reserved_3, bf16_emu_scratch, + bf16_emu_reserved_4, bf16_emu_reserved_5); + } + + ~jit_avx512_core_bf16_sum_kernel_t() { delete bf16_emu_; } + + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_core_bf16_sum_kernel_t) + + static status_t init_conf(jit_sum_conf_t &jsp, const int num_srcs, + const memory_desc_t &dst_d); + + static constexpr unsigned int max_num_arrs = 8; + +protected: + reg64_t reg_idx_table = abi_not_param1; /* may be rcx, note that cl is + required for mask computation */ + reg64_t reg_mask = rsi; + reg32_t reg32_mask = esi; + + const int max_vregs_available; + + int acc_vreg_idx(int i_unroll, int i_acc) override { + // 2 accumulation registers per unroll iteration + const int idx = 2 * i_unroll + i_acc; + assert(idx < max_vregs_available); + return idx; + } + + int scale_vreg_idx(int i_acc_iter) override { + const int scale_idx_start + = 2 * jsp.loop_unroll; // reserved for acc registers + const int idx = scale_idx_start + i_acc_iter; + assert(idx < max_vregs_available); + return idx; + } + + int src_vreg_idx(int i_unroll, int i_inp) override { + // reserved for acc and scale registers + const int inp_idx_start + = 2 * jsp.loop_unroll + utils::div_up(jsp.num_srcs, 2); + const int idx = inp_idx_start + + utils::rnd_up(jsp.num_srcs, 2) * i_unroll + i_inp; + assert(idx < max_vregs_available); + return idx; + } + + int tmp_vreg_idx(int i_unroll, int i_acc_iter) override { + const int num_acc_iters = utils::div_up(jsp.num_srcs, 2); + // reserved for acc, scale and src registers + const int tmp_idx_start = utils::div_up(jsp.num_srcs, 2) + + (2 + utils::rnd_up(jsp.num_srcs, 2)) * jsp.loop_unroll; + const int idx = tmp_idx_start + num_acc_iters * i_unroll + i_acc_iter; + assert(idx < max_vregs_available); + return idx; + } + + static int num_vregs_required(int unroll, int num_srcs) { + const int num_acc_iters = utils::div_up(num_srcs, 2); + // reserved for acc, scale and src registers + int num_regs = utils::div_up(num_srcs, 2) + + (2 + utils::rnd_up(num_srcs, 2)) * unroll; + // tmp registers + num_regs += num_acc_iters * unroll; + return num_regs; + } + + bf16_emulation_t *bf16_emu_; + + Xbyak::Zmm bf16_emu_reserved_1 = Xbyak::Zmm(26); + Xbyak::Zmm bf16_emu_reserved_2 = Xbyak::Zmm(27); + Xbyak::Zmm bf16_emu_reserved_3 = Xbyak::Zmm(28); + Xbyak::Zmm bf16_emu_reserved_4 = Xbyak::Zmm(29); + Xbyak::Zmm bf16_emu_reserved_5 = Xbyak::Zmm(30); + Xbyak::Reg64 bf16_emu_scratch = abi_not_param1; + + Xbyak::Zmm zmm_idx = Xbyak::Zmm(31); + + Xbyak::Label idx_table; + + const Xbyak::Opmask k_mask = k1; + + void pre_compute_init() override; + void broadcast_scale(int scale_iter) override; + void read_iter(int acc_iter, int u_idx, int shift) override; + void add_iter(int acc_iter, int u_idx) override; + void write_iter(int u_idx, int shift) override; + void tail_iteration() override; + void index_tables() override; +}; + +struct jit_avx2_vnni_2_xf16_sum_kernel_t + : jit_uni_xf16_sum_kernel_t { + jit_avx2_vnni_2_xf16_sum_kernel_t(jit_sum_conf_t ajsp) + : jit_uni_xf16_sum_kernel_t(ajsp, ajsp.num_srcs) {} + + ~jit_avx2_vnni_2_xf16_sum_kernel_t() {} + + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx2_vnni_2_xf16_sum_kernel_t) + + static status_t init_conf(jit_sum_conf_t &jsp, const int num_srcs, + const std::vector &src_d, + const memory_desc_t &dst_d); + + static constexpr unsigned int max_num_arrs = 4; + +protected: + int scale_vreg_idx(int i_acc_iter) override { return i_acc_iter; } + + int acc_vreg_idx(int i_unroll, int i_acc) override { + return jsp.num_srcs + + ((i_unroll * jsp.unroll_reg_count + i_acc) + % (16 - jsp.num_srcs)); + } + + int src_vreg_idx(int i_unroll, int i_inp) override { + return jsp.num_srcs + + ((i_unroll * jsp.unroll_reg_count + 2 + i_inp) + % (16 - jsp.num_srcs)); + } + + // max 2 tmp registers in a given unroll. + int tmp_vreg_idx(int i_unroll, int i_acc_iter) override { + // scale + unroll_window(max 12 registers i.e. 16 - num_srcs) + return jsp.num_srcs + + ((i_unroll * jsp.unroll_reg_count + 2 + 2 * jsp.num_srcs + + i_acc_iter) + % (16 - jsp.num_srcs)); + } + + void pre_compute_init() override {} + void broadcast_scale(int scale_iter) override; + void read_iter(int acc_iter, int u_idx, int shift) override; + void add_iter(int acc_iter, int u_idx) override; + void write_iter(int u_idx, int shift) override; + void tail_iteration() override; + void index_tables() override {} +}; + +template +struct jit_xf16_sum_t : public primitive_t { + struct pd_t : public cpu_sum_pd_t { + using cpu_sum_pd_t::cpu_sum_pd_t; + + DECLARE_SUM_PD_T(JIT_IMPL_NAME_HELPER("jit_xf16_", jsp_.isa, ""), + jit_xf16_sum_t); + + status_t init(engine_t *engine) { + + unsigned int max_num_arrs; + if (!mayiuse(isa)) return status::unimplemented; + if (is_superset(isa, avx512_core)) { + max_num_arrs = jit_avx512_core_bf16_sum_kernel_t::max_num_arrs; + } else { + assert(isa == avx2_vnni_2); + max_num_arrs = jit_avx2_vnni_2_xf16_sum_kernel_t::max_num_arrs; + } + + bool ok = true && cpu_sum_pd_t::init(engine) == status::success + && src_mds_.size() <= (long unsigned int)max_num_arrs; + if (!ok) return status::unimplemented; + + const memory_desc_wrapper o_d(&dst_md_); + ok = true && o_d.data_type() == dst_data_type && o_d.is_dense(true); + if (!ok) return status::unimplemented; + + for (size_t i = 0; i < src_mds_.size(); ++i) { + const memory_desc_wrapper i_d(&src_mds_[i]); + ok = true && src_data_type == i_d.data_type() + && o_d.similar_to(i_d, true, false, 0) + && i_d.is_dense(true); + // are scales representable in their respective xfloat16 datatype? scales will be down + // converted to xf16. + if (src_data_type == data_type::bf16) + ok = ok && scales_[i] == float(bfloat16_t(scales_[i])); + else + ok = ok && scales_[i] == float(float16_t(scales_[i])); + + if (!ok) return status::unimplemented; + } + + return is_superset(isa, avx512_core) + ? jit_avx512_core_bf16_sum_kernel_t::init_conf( + jsp_, src_mds_.size(), dst_md_) + : jit_avx2_vnni_2_xf16_sum_kernel_t::init_conf( + jsp_, src_mds_.size(), src_mds_, dst_md_); + } + jit_sum_conf_t jsp_; + }; + + jit_xf16_sum_t(const pd_t *apd) : primitive_t(apd) {} + + status_t init(engine_t *engine) override { + if (is_superset(isa, avx512_core)) { + CHECK(safe_ptr_assign(kernel_, + new jit_avx512_core_bf16_sum_kernel_t(pd()->jsp_))); + } else { + assert(isa == avx2_vnni_2); + CHECK(safe_ptr_assign(kernel_, + new jit_avx2_vnni_2_xf16_sum_kernel_t(pd()->jsp_))); + } + + return kernel_->create_kernel(); + } + + status_t execute(const exec_ctx_t &ctx) const override; + + typedef typename prec_traits::type src_data_t; + typedef typename prec_traits::type dst_data_t; + typedef typename prec_traits::type acc_data_t; + +private: + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + std::unique_ptr kernel_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/lrn/jit_avx512_common_lrn.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/lrn/jit_avx512_common_lrn.hpp new file mode 100644 index 0000000000000000000000000000000000000000..65ca74c12fa05c0f11a9a353ebbe77b2dc62202a --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/lrn/jit_avx512_common_lrn.hpp @@ -0,0 +1,118 @@ +/******************************************************************************* +* Copyright 2017-2022 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_LRN_JIT_AVX512_COMMON_LRN_HPP +#define CPU_X64_LRN_JIT_AVX512_COMMON_LRN_HPP + +#include +#include "common/c_types_map.hpp" +#include "common/primitive.hpp" + +#include "cpu/cpu_lrn_pd.hpp" +#include "cpu/x64/cpu_isa_traits.hpp" +#include "cpu/x64/jit_avx512_core_bf16cvt.hpp" +#include "cpu/x64/lrn/lrn_executor.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { +template +struct jit_avx512_common_lrn_fwd_t : public primitive_t { + struct pd_t : public cpu_lrn_fwd_pd_t { + using cpu_lrn_fwd_pd_t::cpu_lrn_fwd_pd_t; + + DECLARE_COMMON_PD_T( + JIT_IMPL_NAME_HELPER("lrn_jit:", + utils::map(true, avx512_core, + d_type == data_type::bf16 + && mayiuse(avx512_core_bf16), + avx512_core_bf16, + d_type == data_type::bf16 + && !mayiuse(avx512_core_bf16), + bf16_emulation_t::get_isa(), + d_type == data_type::f16, avx512_core_fp16), + ""), + jit_avx512_common_lrn_fwd_t); + + status_t init(engine_t *engine); + }; + + jit_avx512_common_lrn_fwd_t(const pd_t *apd); + ~jit_avx512_common_lrn_fwd_t(); + + using data_t = typename prec_traits::type; + + status_t init(engine_t *engine) override { + return lrn_executor_->create_kernel(); + } + + status_t execute(const exec_ctx_t &ctx) const override { + return lrn_executor_->execute(ctx); + } + +private: + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + std::unique_ptr lrn_executor_; +}; + +template +struct jit_avx512_common_lrn_bwd_t : public primitive_t { + struct pd_t : public cpu_lrn_bwd_pd_t { + using cpu_lrn_bwd_pd_t::cpu_lrn_bwd_pd_t; + + DECLARE_COMMON_PD_T( + JIT_IMPL_NAME_HELPER("lrn_jit:", + utils::map(true, avx512_core, + d_type == data_type::bf16 + && mayiuse(avx512_core_bf16), + avx512_core_bf16, + d_type == data_type::bf16 + && !mayiuse(avx512_core_bf16), + bf16_emulation_t::get_isa(), + d_type == data_type::f16, avx512_core_fp16), + ""), + jit_avx512_common_lrn_bwd_t); + + status_t init(engine_t *engine); + }; + + jit_avx512_common_lrn_bwd_t(const pd_t *apd); + ~jit_avx512_common_lrn_bwd_t(); + + using data_t = typename prec_traits::type; + + status_t init(engine_t *engine) override { + return lrn_executor_->create_kernel(); + } + + status_t execute(const exec_ctx_t &ctx) const override { + return lrn_executor_->execute(ctx); + } + +private: + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + std::unique_ptr lrn_executor_; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/lrn/jit_avx512_common_lrn_bwd_base.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/lrn/jit_avx512_common_lrn_bwd_base.hpp new file mode 100644 index 0000000000000000000000000000000000000000..f4cced2f9d4280b32400f5f2a362bf7f30ab0ee4 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/lrn/jit_avx512_common_lrn_bwd_base.hpp @@ -0,0 +1,114 @@ +/******************************************************************************* +* Copyright 2020-2022 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_LRN_JIT_AVX512_COMMON_LRN_BWD_BASE_HPP +#define CPU_X64_LRN_JIT_AVX512_COMMON_LRN_BWD_BASE_HPP + +#include +#include +#include "common/c_types_map.hpp" +#include "cpu/x64/jit_avx512_core_bf16cvt.hpp" +#include "cpu/x64/jit_generator.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { +namespace lrn { + +using acc_data_t = float; +using acc_data_bf16_t = uint16_t; + +using namespace dnnl::impl::status; +using namespace dnnl::impl::utils; +using namespace data_type; +using namespace Xbyak; +using namespace Xbyak::util; + +template +class jit_avx512_common_lrn_kernel_bwd_t : public jit_generator { +public: + jit_avx512_common_lrn_kernel_bwd_t(float alpha, float beta, int local_size, + void *code_ptr, size_t code_size, const char *name = jit_name()); + + using data_t = typename prec_traits::type; + + struct jit_args_bwd_t { + jit_args_bwd_t(); + const data_t *src, *diff_dst, *ws0, *ws1; + data_t *diff_src; + static const int32_t mask[48]; + const int32_t *mask_ptr; + }; + + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_common_lrn_kernel_bwd_t); + +protected: + Zmm zreg(int irb, int i) const; + Ymm yreg(int irb, int i) const; + Xmm xreg(int irb, int i) const; + + void store_data(bool non_temp_hint, const Address addr, Zmm zr); + void load_data(Xmm reg, const Address p, bool from_stack = false); + void load_tail(int tail_value, Reg64 src, int src_mem_offset, + int dst_stack_offset, int tmp_load_to_stack_idx_tail); + void store_tail(int tail_value, Zmm src, Reg64 dst, int dst_mem_offset, + int tmp_stack_offset, int tmp_idx); + + const Reg64 src_ = rax; + const Reg64 diffsrc_ = r8; + const Reg64 diffdst_ = r9; + const Reg64 workspace0_ = rdx; + const Reg64 workspace1_ = rsi; + const Reg64 imm_addr64_ = rbx; + const Reg64 param_ = abi_param1; + const Reg16 imm_addr16_ = bx; + const Zmm znalphabeta_ = zmm0; + const Xmm xnalphabeta_ = xmm0; + + const Zmm bf16_emu_reserv_1_ = Zmm(28); + const Zmm bf16_emu_reserv_2_ = Zmm(29); + const Reg64 bf16_emu_scratch_ = rax; + const Zmm bf16_emu_reserv_3_ = Zmm(30); + const Zmm bf16_emu_reserv_4_ = Zmm(31); + const int local_size_; + + static constexpr int z_tmp_ = 7; + + static constexpr int zdiffdst_ = 1; + static constexpr int zdiffsrc_ = 2; + static constexpr int zsrc_ = 3; + + const std::vector z_prev_; + const std::vector z_next_; + + static constexpr int zws0_ = 4; + + float nalphabeta_; + const bool emulateBfloat_; + const int regs_used_per_block_; + const int reg_block_; + static constexpr int vlen_ = utils::one_of(d_type, bf16, f16) ? 32 : 64; + std::unique_ptr bf16_emu_; +}; + +} // namespace lrn +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/lrn/jit_avx512_common_lrn_bwd_blocked.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/lrn/jit_avx512_common_lrn_bwd_blocked.hpp new file mode 100644 index 0000000000000000000000000000000000000000..29ec4954a0b06944e8cfd33e1040123380eb8798 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/lrn/jit_avx512_common_lrn_bwd_blocked.hpp @@ -0,0 +1,80 @@ +/******************************************************************************* +* Copyright 2020-2022 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_LRN_JIT_AVX512_COMMON_LRN_BWD_BLOCKED_HPP +#define CPU_X64_LRN_JIT_AVX512_COMMON_LRN_BWD_BLOCKED_HPP + +#include "cpu/x64/lrn/jit_avx512_common_lrn_bwd_base.hpp" +#include "cpu/x64/lrn/jit_avx512_common_lrn_utils.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { +namespace lrn { + +using namespace dnnl::impl::status; +using namespace dnnl::impl::utils; +using namespace data_type; +using namespace Xbyak; +using namespace Xbyak::util; + +template +class jit_avx512_common_lrn_kernel_bwd_blocked_t + : public jit_avx512_common_lrn_kernel_bwd_t { +public: + using data_t = typename prec_traits::type; + + struct jit_args_bwd_t { + const data_t *src, *diff_dst, *ws0, *ws1; + data_t *diff_src; + }; + + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_common_lrn_kernel_bwd_blocked_t) + + jit_avx512_common_lrn_kernel_bwd_blocked_t(const struct nChw16c_across_t &J, + float alpha, float beta, int local_size, int use_h_parallel, + void *code_ptr = nullptr, + size_t code_size = 1 * Xbyak::DEFAULT_MAX_CODE_SIZE); + +private: + void generate() override; + void compute_loop(int loop_size_param); + + int xmm_size_, zmm_size_, buffer_block_, buffer_nest_offset_, + src_prev_offset_; + int HW_, W_; + across_version version_; + + const Reg64 hw_ = r10; + + const int xws1_prev_ = 3; + const int xdiffdst_prev_ = 4; + const int zws1_ = 3; + + const int xws1_next_ = 3; + const int xdiffdst_next_ = 5; + + int use_h_parallelism_; +}; + +} // namespace lrn +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/lrn/jit_avx512_common_lrn_bwd_nhwc.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/lrn/jit_avx512_common_lrn_bwd_nhwc.hpp new file mode 100644 index 0000000000000000000000000000000000000000..2fcee8e69a6097a2c6a1cff2fef17b10b4236cd7 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/lrn/jit_avx512_common_lrn_bwd_nhwc.hpp @@ -0,0 +1,84 @@ +/******************************************************************************* +* Copyright 2020 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_LRN_JIT_AVX512_COMMON_LRN_BWD_NHWC_HPP +#define CPU_X64_LRN_JIT_AVX512_COMMON_LRN_BWD_NHWC_HPP + +#include "cpu/x64/lrn/jit_avx512_common_lrn_bwd_base.hpp" +#include "cpu/x64/lrn/jit_avx512_common_lrn_utils.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { +namespace lrn { + +using namespace dnnl::impl::status; +using namespace dnnl::impl::utils; +using namespace data_type; +using namespace Xbyak; +using namespace Xbyak::util; + +template +class jit_avx512_common_lrn_kernel_bwd_nhwc_t + : public jit_avx512_common_lrn_kernel_bwd_t { +public: + jit_avx512_common_lrn_kernel_bwd_nhwc_t(unsigned C, float alpha, float beta, + int local_size, void *code_ptr = nullptr, + size_t code_size = 1 * Xbyak::DEFAULT_MAX_CODE_SIZE); + + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_common_lrn_kernel_bwd_nhwc_t) + +private: + void generate() override; + void set_up_ker_params(); + void execute_compute_loop(unsigned num_full_16c_blocks, unsigned C_tail); + void compute_loop(across_version version, tail_mode tail_proc, + unsigned C_tail = 0, int loop_size_param = 1); + void compute(int loop_size_param, tail_mode tail_proc); + void increment_loop_params(std::size_t offset); + void load_compute_data( + across_version version, tail_mode tail_proc, int loop_size_param); + void store_compute_data( + int loop_size_param, tail_mode tail_m, unsigned C_tail); + void reserve_stack_space(std::size_t space); + void unreserve_stack_space(std::size_t space); + void load_data_to_stack( + unsigned C_tail, across_version version, tail_mode tail_proc); + int get_stack_offset(const Reg64 reg, tail_mode tail_proc); + + const std::vector tmp_mask_prev_; + const std::vector tmp_mask_next_; + + static constexpr int zmm_size_ = 64; + static constexpr int tmp_load_to_stack_idx_prev_ = 12; + static constexpr int tmp_load_to_stack_idx_tail_ = 13; + static constexpr int tmp_store_from_stack_idx_tail_ = 14; + + const Reg64 mask_ = r11; + const Reg64 blockC_ = r12; + + const int half_ls_; + unsigned C_; +}; + +} // namespace lrn +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/lrn/jit_avx512_common_lrn_fwd_base.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/lrn/jit_avx512_common_lrn_fwd_base.hpp new file mode 100644 index 0000000000000000000000000000000000000000..d21dc8d22a0927be048c730b34f0fd2ce320c871 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/lrn/jit_avx512_common_lrn_fwd_base.hpp @@ -0,0 +1,120 @@ +/******************************************************************************* +* Copyright 2020-2022 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_LRN_JIT_AVX512_COMMON_LRN_FWD_BASE_HPP +#define CPU_X64_LRN_JIT_AVX512_COMMON_LRN_FWD_BASE_HPP + +#include +#include +#include "common/c_types_map.hpp" +#include "cpu/x64/jit_avx512_core_bf16cvt.hpp" +#include "cpu/x64/jit_generator.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { +namespace lrn { + +using acc_data_t = float; +using acc_data_bf16_t = uint16_t; + +using namespace dnnl::impl::status; +using namespace dnnl::impl::utils; +using namespace data_type; +using namespace Xbyak; +using namespace Xbyak::util; + +template +class jit_avx512_common_lrn_kernel_fwd_t : public jit_generator { +public: + jit_avx512_common_lrn_kernel_fwd_t(prop_kind_t prop_kind, float alpha, + float beta, float k, int local_size, void *code_ptr, + size_t code_size, const char *name = jit_name()); + + using data_t = typename prec_traits::type; + + struct jit_args_fwd_t { + jit_args_fwd_t(); + const data_t *src; + data_t *dst, *ws0, *ws1; + static const int32_t mask[48]; + const int32_t *mask_ptr; + }; + + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_common_lrn_kernel_fwd_t); + +protected: + Zmm zreg(int irb, int i) const; + Ymm yreg(int irb, int i) const; + Xmm xreg(int irb, int i) const; + + void store_data(const Address addr, Zmm zr, Ymm yr); + void load_tail(int tail_value, Reg64 src, int src_mem_offset, + int dst_stack_offset, int tmp_load_to_stack_idx_tail); + void load_data(Xmm reg, const Address p, bool from_stack = false); + void store_tail(int tail_value, Zmm src, Reg64 dst, int dst_mem_offset, + int tmp_stack_offset, int tmp_idx); + + prop_kind_t pk_; + float alpha_, beta_, k_; + static constexpr int xmm_size_ = 4 * sizeof(acc_data_t); + static constexpr int zmm_size_ = 64; + const Reg64 imm_addr64_ = rbx; + const Reg16 imm_addr16_ = bx; + + const Xmm xalpha_ = xmm0; + const Zmm zalpha_ = zmm0; + const Zmm zk_ = zmm1; + const Xmm xk_ = xmm1; + const Reg64 src_ = rax; + const Reg64 dst_ = r8; + const Reg64 ws0_ = rdx; + const Reg64 ws1_ = rsi; + const Reg64 param_ = abi_param1; + + const int local_size_; + + static constexpr int zc_ = 2; + const std::vector z_prev_; + const std::vector z_next_; + + const int zsum_; + static constexpr int zsrc_ = 2; + static constexpr int zdst_ = 3; + static constexpr int zsum2_ = 5; + static constexpr int zbase_ = 4; + + const Zmm bf16_emu_reserv_1_ = zmm28; + const Zmm bf16_emu_reserv_2_ = zmm29; + const Reg64 bf16_emu_scratch_ = rax; + const Zmm bf16_emu_reserv_3_ = zmm30; + const Zmm bf16_emu_reserv_4_ = zmm31; + + const bool emulateBfloat_; + const int regs_used_per_block_; + const int reg_block_; + static constexpr int vlen_ = utils::one_of(d_type, bf16, f16) ? 32 : 64; + std::unique_ptr bf16_emu_ = nullptr; +}; + +} // namespace lrn +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/lrn/jit_avx512_common_lrn_fwd_blocked.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/lrn/jit_avx512_common_lrn_fwd_blocked.hpp new file mode 100644 index 0000000000000000000000000000000000000000..793807ab085cf323ebb16b38e3658c4aad4c7ae5 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/lrn/jit_avx512_common_lrn_fwd_blocked.hpp @@ -0,0 +1,64 @@ +/******************************************************************************* +* Copyright 2020 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_LRN_JIT_AVX512_COMMON_LRN_FWD_BLOCKED_HPP +#define CPU_X64_LRN_JIT_AVX512_COMMON_LRN_FWD_BLOCKED_HPP + +#include "cpu/x64/lrn/jit_avx512_common_lrn_fwd_base.hpp" +#include "cpu/x64/lrn/jit_avx512_common_lrn_utils.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { +namespace lrn { + +template +class jit_avx512_common_lrn_kernel_fwd_blocked_t + : public jit_avx512_common_lrn_kernel_fwd_t { + +public: + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_common_lrn_kernel_fwd_blocked_t) + + jit_avx512_common_lrn_kernel_fwd_blocked_t(const struct nChw16c_across_t &J, + prop_kind_t prop_kind, int use_h_parallel, float alpha, float beta, + float k, int local_size, void *code_ptr = nullptr, + size_t code_size = 2 * Xbyak::DEFAULT_MAX_CODE_SIZE); + + void compute_loop(int loop_size_param); + +private: + void generate() override; + using data_t = typename jit_avx512_common_lrn_kernel_fwd_t::data_t; + + int xmm_size_, zmm_size_, buffer_block_, buffer_nest_offset_, + src_prev_offset_, HW_, W_; + across_version version_; + const Reg64 t_ = rsp; + const Reg64 hw_ = r9; + + static constexpr int xsrc_prev_ = 3; + static constexpr int xsrc_next_ = 4; + int use_h_parallelism_; +}; + +} // namespace lrn +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/lrn/jit_avx512_common_lrn_fwd_nhwc.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/lrn/jit_avx512_common_lrn_fwd_nhwc.hpp new file mode 100644 index 0000000000000000000000000000000000000000..d98e2a60224ba3f94044c36e70c0918d57440d99 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/lrn/jit_avx512_common_lrn_fwd_nhwc.hpp @@ -0,0 +1,77 @@ +/******************************************************************************* +* Copyright 2020 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_LRN_JIT_AVX512_COMMON_LRN_FWD_NHWC_HPP +#define CPU_X64_LRN_JIT_AVX512_COMMON_LRN_FWD_NHWC_HPP + +#include "cpu/x64/lrn/jit_avx512_common_lrn_fwd_base.hpp" +#include "cpu/x64/lrn/jit_avx512_common_lrn_utils.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { +namespace lrn { + +template +class jit_avx512_common_lrn_kernel_fwd_nhwc_t + : public jit_avx512_common_lrn_kernel_fwd_t { +public: + jit_avx512_common_lrn_kernel_fwd_nhwc_t(unsigned C, prop_kind_t prop_kind, + float alpha, float beta, float k, int local_size, + void *code_ptr = nullptr, + size_t code_size = 2 * Xbyak::DEFAULT_MAX_CODE_SIZE); + + DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_common_lrn_kernel_fwd_nhwc_t); + +private: + void generate() override; + void set_up_ker_params(); + void execute_compute_loop(unsigned num_full_16c_blocks, unsigned C_tail); + void compute_loop(across_version version, tail_mode tail_mode, + unsigned C_tail = 0, int loop_size_param = 1); + void compute(int loop_size_param); + void increment_loop_params(std::size_t offset); + void load_compute_data( + across_version version, tail_mode tail_proc, int loop_size_param); + void store_compute_data( + int loop_size_param, tail_mode tail_mode, unsigned C_tail); + void reserve_stack_space(std::size_t space); + void unreserve_stack_space(std::size_t space); + void load_data_to_stack( + unsigned C_tail, across_version version, tail_mode tail_mode); + + const std::vector tmp_mask_prev_; + const std::vector tmp_mask_next_; + static constexpr int tmp_load_to_stack_idx_prev_ = 12; + static constexpr int tmp_load_to_stack_idx_tail_ = 13; + static constexpr int tmp_store_from_stack_idx_tail_ = 14; + + static constexpr int zmm_size = 64; + const Reg64 mask_ = r10; + const Reg64 blockC_ = r9; + + const int half_ls_; + unsigned C; +}; + +} // namespace lrn +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/lrn/jit_avx512_common_lrn_utils.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/lrn/jit_avx512_common_lrn_utils.hpp new file mode 100644 index 0000000000000000000000000000000000000000..829639661e6a81e3eb277e993a7a0baf4e06802b --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/lrn/jit_avx512_common_lrn_utils.hpp @@ -0,0 +1,50 @@ +/******************************************************************************* +* Copyright 2020 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_LRN_JIT_AVX512_COMMON_UTILS_HPP +#define CPU_X64_LRN_JIT_AVX512_COMMON_UTILS_HPP + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { +namespace lrn { + +#define IRB_LOOP(statement) \ + for (int irb = 0; irb < loop_size; irb++) { \ + statement; \ + } + +enum class direction { forward, backward }; + +enum class across_version : char { First, Middle, Last, Single }; + +struct nChw16c_across_t { + int H, W; + across_version version; + constexpr nChw16c_across_t(int h, int w, across_version version) + : H(h), W(w), version(version) {} +}; + +enum class tail_mode { NoTail, NextTail, CurrentTail }; + +} // namespace lrn +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/lrn/jit_uni_lrn.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/lrn/jit_uni_lrn.hpp new file mode 100644 index 0000000000000000000000000000000000000000..6bfc293af9b03d1ced6b6bb665ce43c785744452 --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/lrn/jit_uni_lrn.hpp @@ -0,0 +1,110 @@ +/******************************************************************************* +* Copyright 2016-2021 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_LRN_JIT_UNI_LRN_HPP +#define CPU_X64_LRN_JIT_UNI_LRN_HPP + +#include +#include "common/c_types_map.hpp" +#include "common/primitive.hpp" +#include "common/type_helpers.hpp" +#include "common/utils.hpp" + +#include "cpu/cpu_lrn_pd.hpp" +#include "cpu/x64/cpu_isa_traits.hpp" +#include "cpu/x64/lrn/jit_uni_lrn_kernel.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +template +struct jit_uni_lrn_fwd_t : public primitive_t { + struct pd_t : public cpu_lrn_fwd_pd_t { + using cpu_lrn_fwd_pd_t::cpu_lrn_fwd_pd_t; + + DECLARE_COMMON_PD_T( + JIT_IMPL_NAME_HELPER("jit:", isa, ""), jit_uni_lrn_fwd_t); + + status_t init(engine_t *engine); + + format_tag_t dat_tag_; + }; + + jit_uni_lrn_fwd_t(const pd_t *apd); + ~jit_uni_lrn_fwd_t(); + + using data_t = typename prec_traits::type; + + status_t init(engine_t *engine) override; + + status_t execute(const exec_ctx_t &ctx) const override { + return execute_forward(ctx); + } + +private: + status_t execute_forward(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr> ker_, ker_first_, + ker_last_; + static constexpr int VECTOR_LENGTH + = jit_uni_lrn_fwd_kernel_t::VECTOR_LENGTH; +}; + +template +struct jit_uni_lrn_bwd_t : public primitive_t { + struct pd_t : public cpu_lrn_bwd_pd_t { + using cpu_lrn_bwd_pd_t::cpu_lrn_bwd_pd_t; + + DECLARE_COMMON_PD_T( + JIT_IMPL_NAME_HELPER("jit:", isa, ""), jit_uni_lrn_bwd_t); + + status_t init(engine_t *engine); + + format_tag_t dat_tag_; + }; + + jit_uni_lrn_bwd_t(const pd_t *apd); + ~jit_uni_lrn_bwd_t(); + + using data_t = typename prec_traits::type; + + status_t init(engine_t *engine) override; + + status_t execute(const exec_ctx_t &ctx) const override { + return execute_backward(ctx); + } + +private: + status_t execute_backward(const exec_ctx_t &ctx) const; + const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); } + + std::unique_ptr> ker_, ker_first_, + ker_last_; + static constexpr int VECTOR_LENGTH + = jit_uni_lrn_bwd_kernel_t::VECTOR_LENGTH; +}; + +} // namespace x64 +} // namespace cpu +} // namespace impl +} // namespace dnnl + +#endif + +// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s diff --git a/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/lrn/jit_uni_lrn_kernel.hpp b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/lrn/jit_uni_lrn_kernel.hpp new file mode 100644 index 0000000000000000000000000000000000000000..08cfd2c5c216f8ed33af1738e32447cc49c8fb3e --- /dev/null +++ b/miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/x64/lrn/jit_uni_lrn_kernel.hpp @@ -0,0 +1,280 @@ +/******************************************************************************* +* Copyright 2016-2023 Intel Corporation +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef CPU_X64_JIT_UNI_LRN_KERNEL_HPP +#define CPU_X64_JIT_UNI_LRN_KERNEL_HPP + +#include "common/c_types_map.hpp" +#include "common/type_helpers.hpp" + +#include "cpu/x64/jit_generator.hpp" +#include "cpu/x64/utils/jit_io_helper.hpp" + +namespace dnnl { +namespace impl { +namespace cpu { +namespace x64 { + +struct bf16_emulation_t; +struct jit_args_fwd_t { + const void *src; + void *dst, *scratch, *bwd_intermediate_res; +}; + +struct jit_args_bwd_t { + const void *src, *diff_dst, *scratch, *bwd_intermediate_res; + void *diff_src; +}; + +struct nchw8c_across_t { + /* version: + * -1: channels 0..7, + * 1: channels C-8 .. C-1, + * 0: other channels + * 3: channels only for this kernel(without prev and next) + */ + int H, W, version; + nchw8c_across_t(int h, int w, int v) : H(h), W(w), version(v) {} + nchw8c_across_t() : nchw8c_across_t(0, 0, 0) {} +}; + +struct within_config_t { + const int H, W, C, size; + const format_tag_t dat_tag; + within_config_t(int h, int w, int c, int s, format_tag_t dat_tag) + : H(h), W(w), C(c), size(s), dat_tag(dat_tag) {} + within_config_t() : within_config_t(0, 0, 0, 0, dnnl_format_tag_undef) {} +}; + +struct nchw_across_t { + int C, HW, tail; + nchw_across_t(int c, int hw, int t) : C(c), HW(hw), tail(t) {} + nchw_across_t() : nchw_across_t(0, 0, 0) {} +}; + +struct nhwc_across_t { + int C; + nhwc_across_t(int c) : C(c) {} + nhwc_across_t() : nhwc_across_t(0) {} +}; + +enum class lrn_config_t { + none = 0, + nchw8c_across, + within_config, + nchw_across, + nhwc_across, +}; + +template +class jit_uni_lrn_kernel_t; // primary template + +template