diff --git "a/data/catalog.json" "b/data/catalog.json"
--- "a/data/catalog.json"
+++ "b/data/catalog.json"
@@ -17330,3068 +17330,2347 @@
     "linearized": true
   },
   {
-    "id": "cmos_vlsi_design_4th_edition",
-    "title": "CMOS VLSI Design 4th Edition",
-    "author": "Neil H. E. Weste and David Money Harris",
-    "totalPages": 867,
+    "id": "digital_design_and_computer_architecture_arm_edition",
+    "title": "Digital Design and Computer Architecture: ARM® Edition",
+    "author": "Sarah L. Harris",
+    "totalPages": 732,
     "category": "Electronics",
     "tags": [
+      "Software Architecture",
       "Electrical Circuits",
-      "System Design",
+      "Algorithms & Data Structures",
       "ML Engineering",
-      "Software Architecture",
-      "Operating Systems",
-      "Electronics"
+      "System Design"
     ],
-    "coverUrl": "data/covers/cmos_vlsi_design_4th_edition.png",
-    "pdfUrl": "data/pdfs/cmos_vlsi_design_4th_edition.pdf",
-    "layoutUrl": "data/layouts/cmos_vlsi_design_4th_edition.json",
+    "coverUrl": "data/covers/digital_design_and_computer_architecture_arm_edition.png",
+    "pdfUrl": "data/pdfs/digital_design_and_computer_architecture_arm_edition.pdf",
+    "layoutUrl": "data/layouts/digital_design_and_computer_architecture_arm_edition.json",
     "linearized": true,
     "toc": [
       {
         "level": 1,
-        "title": "Cover\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000",
+        "title": "Front Cover",
         "page": 1
       },
       {
         "level": 1,
-        "title": "Title Page",
-        "page": 4
+        "title": "Digital Design and Computer Architecture",
+        "page": 6
       },
       {
         "level": 1,
-        "title": "Copyright",
-        "page": 5
+        "title": "Copyright Page",
+        "page": 7
       },
       {
         "level": 1,
         "title": "Contents",
-        "page": 8
+        "page": 10
       },
       {
         "level": 1,
         "title": "Preface",
-        "page": 24
+        "page": 20
       },
       {
-        "level": 1,
-        "title": "Chapter 1 Introduction",
-        "page": 28
+        "level": 2,
+        "title": "Features",
+        "page": 21
       },
       {
-        "level": 2,
-        "title": "1.1 A Brief History",
-        "page": 28
+        "level": 3,
+        "title": "Side-by-Side Coverage of SystemVerilog and VHDL",
+        "page": 21
       },
       {
-        "level": 2,
-        "title": "1.2 Preview",
-        "page": 33
+        "level": 3,
+        "title": "ARM Architecture and Microarchitecture",
+        "page": 21
+      },
+      {
+        "level": 3,
+        "title": "Real-World Perspectives",
+        "page": 21
+      },
+      {
+        "level": 3,
+        "title": "Accessible Overview of Advanced Microarchitecture",
+        "page": 21
+      },
+      {
+        "level": 3,
+        "title": "End-of-Chapter Exercises and Interview Questions",
+        "page": 22
       },
       {
         "level": 2,
-        "title": "1.3 MOS Transistors",
-        "page": 33
+        "title": "Online Supplements",
+        "page": 22
       },
       {
         "level": 2,
-        "title": "1.4 CMOS Logic",
-        "page": 36
+        "title": "How To Use The Software Tools In A Course",
+        "page": 23
       },
       {
         "level": 3,
-        "title": "1.4.1 The Inverter",
-        "page": 36
+        "title": "Altera Quartus II",
+        "page": 23
       },
       {
         "level": 3,
-        "title": "1.4.2 The NAND Gate",
-        "page": 36
+        "title": "Keil's ARM Microcontroller Development Kit (MDK-ARM)",
+        "page": 23
       },
       {
-        "level": 3,
-        "title": "1.4.3 CMOS Logic Gates",
-        "page": 36
+        "level": 2,
+        "title": "Labs",
+        "page": 23
       },
       {
-        "level": 3,
-        "title": "1.4.4 The NOR Gate",
-        "page": 38
+        "level": 2,
+        "title": "Bugs",
+        "page": 24
       },
       {
-        "level": 3,
-        "title": "1.4.5 Compound Gates",
-        "page": 38
+        "level": 2,
+        "title": "Acknowledgments",
+        "page": 25
       },
       {
-        "level": 3,
-        "title": "1.4.6 Pass Transistors and Transmission Gates",
-        "page": 39
+        "level": 1,
+        "title": "1 From Zero to One",
+        "page": 28
+      },
+      {
+        "level": 2,
+        "title": "1.1 The Game Plan",
+        "page": 28
+      },
+      {
+        "level": 2,
+        "title": "1.2 The Art of Managing Complexity",
+        "page": 29
       },
       {
         "level": 3,
-        "title": "1.4.7 Tristates",
-        "page": 41
+        "title": "1.2.1 Abstraction",
+        "page": 29
       },
       {
         "level": 3,
-        "title": "1.4.8 Multiplexers",
-        "page": 42
+        "title": "1.2.2 Discipline",
+        "page": 30
       },
       {
         "level": 3,
-        "title": "1.4.9 Sequential Circuits",
-        "page": 43
+        "title": "1.2.3 The Three-Y's",
+        "page": 31
       },
       {
         "level": 2,
-        "title": "1.5 CMOS Fabrication and Layout",
-        "page": 46
+        "title": "1.3 The Digital Abstraction",
+        "page": 32
+      },
+      {
+        "level": 2,
+        "title": "1.4 Number Systems",
+        "page": 34
       },
       {
         "level": 3,
-        "title": "1.5.1 Inverter Cross-Section",
-        "page": 46
+        "title": "1.4.1 Decimal Numbers",
+        "page": 34
       },
       {
         "level": 3,
-        "title": "1.5.2 Fabrication Process",
-        "page": 47
+        "title": "1.4.2 Binary Numbers",
+        "page": 34
       },
       {
         "level": 3,
-        "title": "1.5.3 Layout Design Rules",
-        "page": 51
+        "title": "1.4.3 Hexadecimal Numbers",
+        "page": 36
       },
       {
         "level": 3,
-        "title": "1.5.4 Gate Layouts",
-        "page": 54
+        "title": "1.4.4 Bytes, Nibbles, and All That Jazz",
+        "page": 38
       },
       {
         "level": 3,
-        "title": "1.5.5 Stick Diagrams",
-        "page": 55
+        "title": "1.4.5 Binary Addition",
+        "page": 39
+      },
+      {
+        "level": 3,
+        "title": "1.4.6 Signed Binary Numbers",
+        "page": 40
+      },
+      {
+        "level": 4,
+        "title": "Sign/Magnitude Numbers",
+        "page": 40
+      },
+      {
+        "level": 4,
+        "title": "Two's Complement Numbers",
+        "page": 41
+      },
+      {
+        "level": 4,
+        "title": "Comparison of Number Systems",
+        "page": 43
       },
       {
         "level": 2,
-        "title": "1.6 Design Partitioning",
-        "page": 56
+        "title": "1.5 Logic Gates",
+        "page": 44
       },
       {
         "level": 3,
-        "title": "1.6.1 Design Abstractions",
-        "page": 57
+        "title": "1.5.1 NOT Gate",
+        "page": 45
       },
       {
         "level": 3,
-        "title": "1.6.2 Structured Design",
-        "page": 58
+        "title": "1.5.2 Buffer",
+        "page": 45
       },
       {
         "level": 3,
-        "title": "1.6.3 Behavioral, Structural, and Physical Domains",
-        "page": 58
+        "title": "1.5.3 AND Gate",
+        "page": 45
       },
       {
-        "level": 2,
-        "title": "1.7 Example: A Simple MIPS Microprocessor",
-        "page": 60
+        "level": 3,
+        "title": "1.5.4 OR Gate",
+        "page": 46
       },
       {
         "level": 3,
-        "title": "1.7.1 MIPS Architecture",
-        "page": 60
+        "title": "1.5.5 Other Two-Input Gates",
+        "page": 46
       },
       {
         "level": 3,
-        "title": "1.7.2 Multicycle MIPS Microarchitecture",
-        "page": 61
+        "title": "1.5.6 Multiple-Input Gates",
+        "page": 46
       },
       {
         "level": 2,
-        "title": "1.8 Logic Design",
-        "page": 65
+        "title": "1.6 Beneath the Digital Abstraction",
+        "page": 47
       },
       {
         "level": 3,
-        "title": "1.8.1 Top-Level Interfaces",
-        "page": 65
+        "title": "1.6.1 Supply Voltage",
+        "page": 47
       },
       {
         "level": 3,
-        "title": "1.8.2 Block Diagrams",
-        "page": 65
+        "title": "1.6.2 Logic Levels",
+        "page": 47
       },
       {
         "level": 3,
-        "title": "1.8.3 Hierarchy",
-        "page": 67
+        "title": "1.6.3 Noise Margins",
+        "page": 48
       },
       {
         "level": 3,
-        "title": "1.8.4 Hardware Description Languages",
-        "page": 67
+        "title": "1.6.4 DC Transfer Characteristics",
+        "page": 49
       },
       {
-        "level": 2,
-        "title": "1.9 Circuit Design",
-        "page": 69
+        "level": 3,
+        "title": "1.6.5 The Static Discipline",
+        "page": 49
       },
       {
         "level": 2,
-        "title": "1.10 Physical Design",
-        "page": 72
+        "title": "1.7 CMOS Transistors",
+        "page": 51
       },
       {
         "level": 3,
-        "title": "1.10.1 Floorplanning",
-        "page": 72
+        "title": "1.7.1 Semiconductors",
+        "page": 52
       },
       {
         "level": 3,
-        "title": "1.10.2 Standard Cells",
-        "page": 75
+        "title": "1.7.2 Diodes",
+        "page": 52
       },
       {
         "level": 3,
-        "title": "1.10.3 Pitch Matching",
-        "page": 77
+        "title": "1.7.3 Capacitors",
+        "page": 53
       },
       {
         "level": 3,
-        "title": "1.10.4 Slice Plans",
-        "page": 77
+        "title": "1.7.4 nMOS and pMOS Transistors",
+        "page": 53
       },
       {
         "level": 3,
-        "title": "1.10.5 Arrays",
-        "page": 78
+        "title": "1.7.5 CMOS NOT Gate",
+        "page": 56
       },
       {
         "level": 3,
-        "title": "1.10.6 Area Estimation",
-        "page": 78
+        "title": "1.7.6 Other CMOS Logic Gates",
+        "page": 56
       },
       {
-        "level": 2,
-        "title": "1.11 Design Verification",
-        "page": 80
+        "level": 3,
+        "title": "1.7.7 Transmission Gates",
+        "page": 58
+      },
+      {
+        "level": 3,
+        "title": "1.7.8 Pseudo-nMOS Logic",
+        "page": 58
       },
       {
         "level": 2,
-        "title": "1.12 Fabrication, Packaging, and Testing",
-        "page": 81
+        "title": "1.8 Power Consumption",
+        "page": 59
       },
       {
         "level": 2,
-        "title": "Summary and a Look Ahead",
-        "page": 82
+        "title": "1.9 Summary and a Look Ahead",
+        "page": 60
       },
       {
         "level": 2,
         "title": "Exercises",
-        "page": 84
+        "page": 62
       },
       {
-        "level": 1,
-        "title": "Chapter 2 MOS Transistor Theory",
-        "page": 88
+        "level": 2,
+        "title": "Interview Questions",
+        "page": 77
       },
       {
-        "level": 2,
-        "title": "2.1 Introduction",
-        "page": 88
+        "level": 1,
+        "title": "2 Combinational Logic Design",
+        "page": 80
       },
       {
         "level": 2,
-        "title": "2.2 Long-Channel I-V Characteristics",
-        "page": 91
+        "title": "2.1 Introduction",
+        "page": 80
       },
       {
         "level": 2,
-        "title": "2.3 C-V Characteristics",
-        "page": 95
+        "title": "2.2 Boolean Equations",
+        "page": 83
       },
       {
         "level": 3,
-        "title": "2.3.1 Simple MOS Capacitance Models",
-        "page": 95
+        "title": "2.2.1 Terminology",
+        "page": 83
       },
       {
         "level": 3,
-        "title": "2.3.2 Detailed MOS Gate Capacitance Model",
-        "page": 97
+        "title": "2.2.2 Sum-of-Products Form",
+        "page": 83
       },
       {
         "level": 3,
-        "title": "2.3.3 Detailed MOS Diffusion Capacitance Model",
-        "page": 99
+        "title": "2.2.3 Product-of-Sums Form",
+        "page": 85
       },
       {
         "level": 2,
-        "title": "2.4 Nonideal I-V Effects",
-        "page": 101
-      },
-      {
-        "level": 3,
-        "title": "2.4.1 Mobility Degradation and Velocity Saturation",
-        "page": 102
+        "title": "2.3 Boolean Algebra",
+        "page": 85
       },
       {
         "level": 3,
-        "title": "2.4.2 Channel Length Modulation",
-        "page": 105
+        "title": "2.3.1 Axioms",
+        "page": 86
       },
       {
         "level": 3,
-        "title": "2.4.3 Threshold Voltage Effects",
-        "page": 106
+        "title": "2.3.2 Theorems of One Variable",
+        "page": 86
       },
       {
         "level": 3,
-        "title": "2.4.4 Leakage",
-        "page": 107
+        "title": "2.3.3 Theorems of Several Variables",
+        "page": 87
       },
       {
         "level": 3,
-        "title": "2.4.5 Temperature Dependence",
-        "page": 112
+        "title": "2.3.4 The Truth Behind It All",
+        "page": 89
       },
       {
         "level": 3,
-        "title": "2.4.6 Geometry Dependence",
-        "page": 113
+        "title": "2.3.5 Simplifying Equations",
+        "page": 90
       },
       {
-        "level": 3,
-        "title": "2.4.7 Summary",
-        "page": 113
+        "level": 2,
+        "title": "2.4 From Logic to Gates",
+        "page": 91
       },
       {
         "level": 2,
-        "title": "2.5 DC Transfer Characteristics",
-        "page": 114
+        "title": "2.5 Multilevel Combinational Logic",
+        "page": 94
       },
       {
         "level": 3,
-        "title": "2.5.1 Static CMOS Inverter DC Characteristics",
-        "page": 115
+        "title": "2.5.1 Hardware Reduction",
+        "page": 95
       },
       {
         "level": 3,
-        "title": "2.5.2 Beta Ratio Effects",
-        "page": 117
+        "title": "2.5.2 Bubble Pushing",
+        "page": 96
+      },
+      {
+        "level": 2,
+        "title": "2.6 X’s and Z’s, Oh My",
+        "page": 98
       },
       {
         "level": 3,
-        "title": "2.5.3 Noise Margin",
-        "page": 118
+        "title": "2.6.1 Illegal Value: X",
+        "page": 98
       },
       {
         "level": 3,
-        "title": "2.5.4 Pass Transistor DC Characteristics",
-        "page": 119
+        "title": "2.6.2 Floating Value: Z",
+        "page": 99
       },
       {
         "level": 2,
-        "title": "2.6 Pitfalls and Fallacies",
-        "page": 120
+        "title": "2.7 Karnaugh Maps",
+        "page": 100
       },
       {
-        "level": 2,
-        "title": "Summary",
-        "page": 121
+        "level": 3,
+        "title": "2.7.1 Circular Thinking",
+        "page": 101
       },
       {
-        "level": 2,
-        "title": "Exercises",
-        "page": 122
+        "level": 3,
+        "title": "2.7.2 Logic Minimization with K-Maps",
+        "page": 102
       },
       {
-        "level": 1,
-        "title": "Chapter 3 CMOS Processing Technology",
-        "page": 126
+        "level": 3,
+        "title": "2.7.3 Don't Cares",
+        "page": 106
       },
       {
-        "level": 2,
-        "title": "3.1 Introduction",
-        "page": 126
+        "level": 3,
+        "title": "2.7.4 The Big Picture",
+        "page": 107
       },
       {
         "level": 2,
-        "title": "3.2 CMOS Technologies",
-        "page": 127
+        "title": "2.8 Combinational Building Blocks",
+        "page": 108
       },
       {
         "level": 3,
-        "title": "3.2.1 Wafer Formation",
-        "page": 127
+        "title": "2.8.1 Multiplexers",
+        "page": 108
       },
       {
         "level": 3,
-        "title": "3.2.2 Photolithography",
-        "page": 128
+        "title": "2.8.2 Decoders",
+        "page": 111
       },
       {
-        "level": 3,
-        "title": "3.2.3 Well and Channel Formation",
-        "page": 130
+        "level": 2,
+        "title": "2.9 Timing",
+        "page": 113
       },
       {
         "level": 3,
-        "title": "3.2.4 Silicon Dioxide (SiO[sup(2)])",
-        "page": 132
+        "title": "2.9.1 Propagation and Contamination Delay",
+        "page": 113
       },
       {
         "level": 3,
-        "title": "3.2.5 Isolation",
-        "page": 133
+        "title": "2.9.2 Glitches",
+        "page": 117
       },
       {
-        "level": 3,
-        "title": "3.2.6 Gate Oxide",
+        "level": 2,
+        "title": "2.10 Summary",
+        "page": 120
+      },
+      {
+        "level": 2,
+        "title": "Exercises",
+        "page": 122
+      },
+      {
+        "level": 2,
+        "title": "Interview Questions",
+        "page": 131
+      },
+      {
+        "level": 1,
+        "title": "3 Sequential Logic Design",
+        "page": 134
+      },
+      {
+        "level": 2,
+        "title": "3.1 Introduction",
+        "page": 134
+      },
+      {
+        "level": 2,
+        "title": "3.2 Latches and Flip-Flops",
         "page": 134
       },
       {
         "level": 3,
-        "title": "3.2.7 Gate and Source/Drain Formations",
-        "page": 135
+        "title": "3.2.1 SR Latch",
+        "page": 136
       },
       {
         "level": 3,
-        "title": "3.2.8 Contacts and Metallization",
-        "page": 137
+        "title": "3.2.2 D Latch",
+        "page": 138
       },
       {
         "level": 3,
-        "title": "3.2.9 Passivation",
+        "title": "3.2.3 D FIip-Flop",
         "page": 139
       },
       {
         "level": 3,
-        "title": "3.2.10 Metrology",
+        "title": "3.2.4 Register",
         "page": 139
       },
       {
-        "level": 2,
-        "title": "3.3 Layout Design Rules",
+        "level": 3,
+        "title": "3.2.5 Enabled Flip-Flop",
         "page": 140
       },
       {
         "level": 3,
-        "title": "3.3.1 Design Rule Background",
-        "page": 140
+        "title": "3.2.6 Resettable Flip-Flop",
+        "page": 141
       },
       {
         "level": 3,
-        "title": "3.3.2 Scribe Line and Other Structures",
+        "title": "3.2.7 Transistor-Level Latch and Flip-Flop Designs",
+        "page": 141
+      },
+      {
+        "level": 3,
+        "title": "3.2.8 Putting It All Together",
         "page": 143
       },
+      {
+        "level": 2,
+        "title": "3.3 Synchronous Logic Design",
+        "page": 144
+      },
       {
         "level": 3,
-        "title": "3.3.3 MOSIS Scalable CMOS Design Rules",
+        "title": "3.3.1 Some Problematic Circuits",
         "page": 144
       },
       {
         "level": 3,
-        "title": "3.3.4 Micron Design Rules",
+        "title": "3.3.2 Synchronous Sequential Circuits",
         "page": 145
       },
       {
-        "level": 2,
-        "title": "3.4 CMOS Process Enhancements",
-        "page": 146
+        "level": 3,
+        "title": "3.3.3 Synchronous and Asynchronous Circuits",
+        "page": 147
       },
       {
-        "level": 3,
-        "title": "3.4.1 Transistors",
-        "page": 146
+        "level": 2,
+        "title": "3.4 Finite State Machines",
+        "page": 148
       },
       {
         "level": 3,
-        "title": "3.4.2 Interconnect",
-        "page": 149
+        "title": "3.4.1 FSM Design Example",
+        "page": 148
       },
       {
         "level": 3,
-        "title": "3.4.3 Circuit Elements",
-        "page": 151
+        "title": "3.4.2 State Encodings",
+        "page": 154
       },
       {
         "level": 3,
-        "title": "3.4.4 Beyond Conventional CMOS",
-        "page": 156
+        "title": "3.4.3 Moore and Mealy Machines",
+        "page": 157
       },
       {
-        "level": 2,
-        "title": "3.5 Technology-Related CAD Issues",
-        "page": 157
+        "level": 3,
+        "title": "3.4.4 Factoring State Machines",
+        "page": 159
       },
       {
         "level": 3,
-        "title": "3.5.1 Design Rule Checking (DRC)",
-        "page": 158
+        "title": "3.4.5 Deriving an FSM from a Schematic",
+        "page": 162
       },
       {
         "level": 3,
-        "title": "3.5.2 Circuit Extraction",
-        "page": 159
+        "title": "3.4.6 FSM Review",
+        "page": 165
       },
       {
         "level": 2,
-        "title": "3.6 Manufacturing Issues",
-        "page": 160
+        "title": "3.5 Timing of Sequential Logic",
+        "page": 166
       },
       {
         "level": 3,
-        "title": "3.6.1 Antenna Rules",
-        "page": 160
+        "title": "3.5.1 The Dynamic Discipline",
+        "page": 167
       },
       {
         "level": 3,
-        "title": "3.6.2 Layer Density Rules",
-        "page": 161
+        "title": "3.5.2 System Timing",
+        "page": 167
       },
       {
         "level": 3,
-        "title": "3.6.3 Resolution Enhancement Rules",
-        "page": 161
+        "title": "3.5.3 Clock Skew",
+        "page": 173
       },
       {
         "level": 3,
-        "title": "3.6.4 Metal Slotting Rules",
-        "page": 162
+        "title": "3.5.4 Metastability",
+        "page": 176
       },
       {
         "level": 3,
-        "title": "3.6.5 Yield Enhancement Guidelines",
-        "page": 162
+        "title": "3.5.5 Synchronizers",
+        "page": 177
       },
       {
-        "level": 2,
-        "title": "3.7 Pitfalls and Fallacies",
-        "page": 163
+        "level": 3,
+        "title": "3.5.6 Derivation of Resolution Time",
+        "page": 179
       },
       {
         "level": 2,
-        "title": "3.8 Historical Perspective",
-        "page": 164
+        "title": "3.6 Parallelism",
+        "page": 182
       },
       {
         "level": 2,
-        "title": "Summary",
-        "page": 166
+        "title": "3.7 Summary",
+        "page": 186
       },
       {
         "level": 2,
         "title": "Exercises",
-        "page": 166
+        "page": 187
+      },
+      {
+        "level": 2,
+        "title": "Interview Questions",
+        "page": 196
       },
       {
         "level": 1,
-        "title": "Chapter 4 Delay",
-        "page": 168
+        "title": "4 Hardware Description Languages",
+        "page": 198
       },
       {
         "level": 2,
         "title": "4.1 Introduction",
-        "page": 168
+        "page": 198
       },
       {
         "level": 3,
-        "title": "4.1.1 Definitions",
-        "page": 168
+        "title": "4.1.1 Modules",
+        "page": 198
       },
       {
         "level": 3,
-        "title": "4.1.2 Timing Optimization",
-        "page": 169
+        "title": "4.1.2 Language Origins",
+        "page": 199
       },
       {
-        "level": 2,
-        "title": "4.2 Transient Response",
-        "page": 170
+        "level": 3,
+        "title": "4.1.3 Simulation and Synthesis",
+        "page": 200
       },
       {
         "level": 2,
-        "title": "4.3 RC Delay Model",
-        "page": 173
+        "title": "4.2 Combinational Logic",
+        "page": 202
       },
       {
         "level": 3,
-        "title": "4.3.1 Effective Resistance",
-        "page": 173
+        "title": "4.2.1 Bitwise Operators",
+        "page": 202
       },
       {
         "level": 3,
-        "title": "4.3.2 Gate and Diffusion Capacitance",
-        "page": 174
+        "title": "4.2.2 Comments and White Space",
+        "page": 205
       },
       {
         "level": 3,
-        "title": "4.3.3 Equivalent RC Circuits",
-        "page": 174
+        "title": "4.2.3 Reduction Operators",
+        "page": 205
       },
       {
         "level": 3,
-        "title": "4.3.4 Transient Response",
-        "page": 175
+        "title": "4.2.4 Conditional Assignment",
+        "page": 206
       },
       {
         "level": 3,
-        "title": "4.3.5 Elmore Delay",
-        "page": 177
+        "title": "4.2.5 Internal Variables",
+        "page": 207
       },
       {
         "level": 3,
-        "title": "4.3.6 Layout Dependence of Capacitance",
-        "page": 180
+        "title": "4.2.6 Precedence",
+        "page": 209
       },
       {
         "level": 3,
-        "title": "4.3.7 Determining Effective Resistance",
-        "page": 181
+        "title": "4.2.7 Numbers",
+        "page": 210
       },
       {
-        "level": 2,
-        "title": "4.4 Linear Delay Model",
-        "page": 182
+        "level": 3,
+        "title": "4.2.8 Z’s and X’s",
+        "page": 211
       },
       {
         "level": 3,
-        "title": "4.4.1 Logical Effort",
-        "page": 183
+        "title": "4.2.9 Bit Swizzling",
+        "page": 213
       },
       {
         "level": 3,
-        "title": "4.4.2 Parasitic Delay",
-        "page": 183
+        "title": "4.2.10 Delays",
+        "page": 213
       },
       {
-        "level": 3,
-        "title": "4.4.3 Delay in a Logic Gate",
-        "page": 185
+        "level": 2,
+        "title": "4.3 Structural Modeling",
+        "page": 215
       },
       {
-        "level": 3,
-        "title": "4.4.4 Drive",
-        "page": 186
+        "level": 2,
+        "title": "4.4 Sequential Logic",
+        "page": 218
       },
       {
         "level": 3,
-        "title": "4.4.5 Extracting Logical Effort from Datasheets",
-        "page": 186
+        "title": "4.4.1 Registers",
+        "page": 218
       },
       {
         "level": 3,
-        "title": "4.4.6 Limitations to the Linear Delay Model",
-        "page": 187
+        "title": "4.4.2 Resettable Registers",
+        "page": 219
       },
       {
-        "level": 2,
-        "title": "4.5 Logical Effort of Paths",
-        "page": 190
+        "level": 3,
+        "title": "4.4.3 Enabled Registers",
+        "page": 221
       },
       {
         "level": 3,
-        "title": "4.5.1 Delay in Multistage Logic Networks",
-        "page": 190
+        "title": "4.4.4 Multiple Registers",
+        "page": 222
       },
       {
         "level": 3,
-        "title": "4.5.2 Choosing the Best Number of Stages",
-        "page": 193
+        "title": "4.4.5 Latches",
+        "page": 223
+      },
+      {
+        "level": 2,
+        "title": "4.5 More Combinational Logic",
+        "page": 223
       },
       {
         "level": 3,
-        "title": "4.5.3 Example",
-        "page": 195
+        "title": "4.5.1 Case Statements",
+        "page": 226
       },
       {
         "level": 3,
-        "title": "4.5.4 Summary and Observations",
-        "page": 196
+        "title": "4.5.2 If Statements",
+        "page": 227
       },
       {
         "level": 3,
-        "title": "4.5.5 Limitations of Logical Effort",
-        "page": 198
+        "title": "4.5.3 Truth Tables with Don’t Cares",
+        "page": 230
       },
       {
         "level": 3,
-        "title": "4.5.6 Iterative Solutions for Sizing",
-        "page": 198
+        "title": "4.5.4 Blocking and Nonblocking Assignments",
+        "page": 230
       },
       {
         "level": 2,
-        "title": "4.6 Timing Analysis Delay Models",
-        "page": 200
+        "title": "4.6 Finite State Machines",
+        "page": 234
       },
       {
-        "level": 3,
-        "title": "4.6.1 Slope-Based Linear Model",
-        "page": 200
+        "level": 2,
+        "title": "4.7 Data Types",
+        "page": 238
       },
       {
         "level": 3,
-        "title": "4.6.2 Nonlinear Delay Model",
-        "page": 201
+        "title": "4.7.1 SystemVerilog",
+        "page": 239
       },
       {
         "level": 3,
-        "title": "4.6.3 Current Source Model",
-        "page": 201
+        "title": "4.7.2 VHDL",
+        "page": 240
       },
       {
         "level": 2,
-        "title": "4.7 Pitfalls and Fallacies",
-        "page": 201
+        "title": "4.8 Parameterized Modules",
+        "page": 242
       },
       {
         "level": 2,
-        "title": "4.8 Historical Perspective",
-        "page": 202
+        "title": "4.9 Testbenches",
+        "page": 245
       },
       {
         "level": 2,
-        "title": "Summary",
-        "page": 203
+        "title": "4.10 Summary",
+        "page": 249
       },
       {
         "level": 2,
         "title": "Exercises",
-        "page": 203
+        "page": 251
+      },
+      {
+        "level": 2,
+        "title": "Interview Questions",
+        "page": 262
       },
       {
         "level": 1,
-        "title": "Chapter 5 Power",
-        "page": 208
+        "title": "5 Digital Building Blocks",
+        "page": 264
       },
       {
         "level": 2,
         "title": "5.1 Introduction",
-        "page": 208
+        "page": 264
       },
       {
-        "level": 3,
-        "title": "5.1.1 Definitions",
-        "page": 209
+        "level": 2,
+        "title": "5.2 Arithmetic Circuits",
+        "page": 264
       },
       {
         "level": 3,
-        "title": "5.1.2 Examples",
-        "page": 209
+        "title": "5.2.1 Addition",
+        "page": 264
       },
       {
-        "level": 3,
-        "title": "5.1.3 Sources of Power Dissipation",
-        "page": 211
+        "level": 4,
+        "title": "Half Adder",
+        "page": 265
       },
       {
-        "level": 2,
-        "title": "5.2 Dynamic Power",
-        "page": 212
+        "level": 4,
+        "title": "Full Adder",
+        "page": 265
       },
       {
-        "level": 3,
-        "title": "5.2.1 Activity Factor",
-        "page": 213
+        "level": 4,
+        "title": "Carry Propagate Adder",
+        "page": 265
       },
       {
-        "level": 3,
-        "title": "5.2.2 Capacitance",
-        "page": 215
+        "level": 4,
+        "title": "Ripple-Carry Adder",
+        "page": 265
       },
       {
-        "level": 3,
-        "title": "5.2.3 Voltage",
-        "page": 217
+        "level": 4,
+        "title": "Carry-Lookahead Adder",
+        "page": 266
       },
       {
-        "level": 3,
-        "title": "5.2.4 Frequency",
-        "page": 219
+        "level": 4,
+        "title": "Prefix Adder",
+        "page": 268
       },
       {
-        "level": 3,
-        "title": "5.2.5 Short-Circuit Current",
-        "page": 220
+        "level": 4,
+        "title": "Putting It All Together",
+        "page": 270
       },
       {
         "level": 3,
-        "title": "5.2.6 Resonant Circuits",
-        "page": 220
+        "title": "5.2.2 Subtraction",
+        "page": 271
       },
       {
-        "level": 2,
-        "title": "5.3 Static Power",
-        "page": 221
+        "level": 3,
+        "title": "5.2.3 Comparators",
+        "page": 271
       },
       {
         "level": 3,
-        "title": "5.3.1 Static Power Sources",
-        "page": 221
+        "title": "5.2.4 ALU",
+        "page": 273
       },
       {
         "level": 3,
-        "title": "5.3.2 Power Gating",
-        "page": 224
+        "title": "5.2.5 Shifters and Rotators",
+        "page": 276
       },
       {
         "level": 3,
-        "title": "5.3.3 Multiple Threshold Voltages and Oxide Thicknesses",
-        "page": 226
+        "title": "5.2.6 Multiplication",
+        "page": 277
       },
       {
         "level": 3,
-        "title": "5.3.4 Variable Threshold Voltages",
-        "page": 226
+        "title": "5.2.7 Division",
+        "page": 279
       },
       {
         "level": 3,
-        "title": "5.3.5 Input Vector Control",
-        "page": 227
+        "title": "5.2.8 Further Reading",
+        "page": 280
       },
       {
         "level": 2,
-        "title": "5.4 Energy-Delay Optimization",
-        "page": 227
+        "title": "5.3 Number Systems",
+        "page": 280
       },
       {
         "level": 3,
-        "title": "5.4.1 Minimum Energy",
-        "page": 227
+        "title": "5.3.1 Fixed-Point Number Systems",
+        "page": 280
       },
       {
         "level": 3,
-        "title": "5.4.2 Minimum Energy-Delay Product",
-        "page": 230
+        "title": "5.3.2 Floating-Point Number Systems",
+        "page": 281
       },
       {
-        "level": 3,
-        "title": "5.4.3 Minimum Energy Under a Delay Constraint",
-        "page": 230
+        "level": 4,
+        "title": "Special Cases: 0, ±∞, and NaN",
+        "page": 283
       },
       {
-        "level": 2,
-        "title": "5.5 Low Power Architectures",
-        "page": 231
+        "level": 4,
+        "title": "Single- and Double-Precision Formats",
+        "page": 283
       },
       {
-        "level": 3,
-        "title": "5.5.1 Microarchitecture",
-        "page": 231
+        "level": 4,
+        "title": "Rounding",
+        "page": 284
       },
       {
-        "level": 3,
-        "title": "5.5.2 Parallelism and Pipelining",
-        "page": 231
-      },
-      {
-        "level": 3,
-        "title": "5.5.3 Power Management Modes",
-        "page": 232
-      },
-      {
-        "level": 2,
-        "title": "5.6 Pitfalls and Fallacies",
-        "page": 233
-      },
-      {
-        "level": 2,
-        "title": "5.7 Historical Perspective",
-        "page": 234
-      },
-      {
-        "level": 2,
-        "title": "Summary",
-        "page": 236
-      },
-      {
-        "level": 2,
-        "title": "Exercises",
-        "page": 236
-      },
-      {
-        "level": 1,
-        "title": "Chapter 6 Interconnect",
-        "page": 238
-      },
-      {
-        "level": 2,
-        "title": "6.1 Introduction",
-        "page": 238
-      },
-      {
-        "level": 3,
-        "title": "6.1.1 Wire Geometry",
-        "page": 238
-      },
-      {
-        "level": 3,
-        "title": "6.1.2 Example: Intel Metal Stacks",
-        "page": 239
-      },
-      {
-        "level": 2,
-        "title": "6.2 Interconnect Modeling",
-        "page": 240
-      },
-      {
-        "level": 3,
-        "title": "6.2.1 Resistance",
-        "page": 241
-      },
-      {
-        "level": 3,
-        "title": "6.2.2 Capacitance",
-        "page": 242
-      },
-      {
-        "level": 3,
-        "title": "6.2.3 Inductance",
-        "page": 245
-      },
-      {
-        "level": 3,
-        "title": "6.2.4 Skin Effect",
-        "page": 246
-      },
-      {
-        "level": 3,
-        "title": "6.2.5 Temperature Dependence",
-        "page": 247
-      },
-      {
-        "level": 2,
-        "title": "6.3 Interconnect Impact",
-        "page": 247
-      },
-      {
-        "level": 3,
-        "title": "6.3.1 Delay",
-        "page": 247
-      },
-      {
-        "level": 3,
-        "title": "6.3.2 Energy",
-        "page": 249
-      },
-      {
-        "level": 3,
-        "title": "6.3.3 Crosstalk",
-        "page": 249
-      },
-      {
-        "level": 3,
-        "title": "6.3.4 Inductive Effects",
-        "page": 251
-      },
-      {
-        "level": 3,
-        "title": "6.3.5 An Aside on Effective Resistance and Elmore Delay",
-        "page": 254
-      },
-      {
-        "level": 2,
-        "title": "6.4 Interconnect Engineering",
-        "page": 256
-      },
-      {
-        "level": 3,
-        "title": "6.4.1 Width, Spacing, and Layer",
-        "page": 256
-      },
-      {
-        "level": 3,
-        "title": "6.4.2 Repeaters",
-        "page": 257
-      },
-      {
-        "level": 3,
-        "title": "6.4.3 Crosstalk Control",
-        "page": 259
-      },
-      {
-        "level": 3,
-        "title": "6.4.4 Low-Swing Signaling",
-        "page": 261
-      },
-      {
-        "level": 3,
-        "title": "6.4.5 Regenerators",
-        "page": 263
-      },
-      {
-        "level": 2,
-        "title": "6.5 Logical Effort with Wires",
-        "page": 263
-      },
-      {
-        "level": 2,
-        "title": "6.6 Pitfalls and Fallacies",
-        "page": 264
-      },
-      {
-        "level": 2,
-        "title": "Summary",
-        "page": 265
-      },
-      {
-        "level": 2,
-        "title": "Exercises",
-        "page": 265
-      },
-      {
-        "level": 1,
-        "title": "Chapter 7 Robustness",
-        "page": 268
-      },
-      {
-        "level": 2,
-        "title": "7.1 Introduction",
-        "page": 268
-      },
-      {
-        "level": 2,
-        "title": "7.2 Variability",
-        "page": 268
-      },
-      {
-        "level": 3,
-        "title": "7.2.1 Supply Voltage",
-        "page": 269
-      },
-      {
-        "level": 3,
-        "title": "7.2.2 Temperature",
-        "page": 269
-      },
-      {
-        "level": 3,
-        "title": "7.2.3 Process Variation",
-        "page": 270
-      },
-      {
-        "level": 3,
-        "title": "7.2.4 Design Corners",
-        "page": 271
-      },
-      {
-        "level": 2,
-        "title": "7.3 Reliability",
-        "page": 273
-      },
-      {
-        "level": 3,
-        "title": "7.3.1 Reliability Terminology",
-        "page": 273
-      },
-      {
-        "level": 3,
-        "title": "7.3.2 Oxide Wearout",
-        "page": 274
-      },
-      {
-        "level": 3,
-        "title": "7.3.3 Interconnect Wearout",
-        "page": 276
-      },
-      {
-        "level": 3,
-        "title": "7.3.4 Soft Errors",
-        "page": 278
-      },
-      {
-        "level": 3,
-        "title": "7.3.5 Overvoltage Failure",
-        "page": 279
-      },
-      {
-        "level": 3,
-        "title": "7.3.6 Latchup",
-        "page": 280
+        "level": 4,
+        "title": "Floating-Point Addition",
+        "page": 284
       },
       {
         "level": 2,
-        "title": "7.4 Scaling",
-        "page": 281
-      },
-      {
-        "level": 3,
-        "title": "7.4.1 Transistor Scaling",
-        "page": 282
-      },
-      {
-        "level": 3,
-        "title": "7.4.2 Interconnect Scaling",
+        "title": "5.4 Sequential Building Blocks",
         "page": 284
       },
       {
         "level": 3,
-        "title": "7.4.3 International Technology Roadmap for Semiconductors",
+        "title": "5.4.1 Counters",
         "page": 285
       },
       {
         "level": 3,
-        "title": "7.4.4 Impacts on Design",
+        "title": "5.4.2 Shift Registers",
         "page": 286
       },
       {
         "level": 2,
-        "title": "7.5 Statistical Analysis of Variability",
-        "page": 290
-      },
-      {
-        "level": 3,
-        "title": "7.5.1 Properties of Random Variables",
-        "page": 290
-      },
-      {
-        "level": 3,
-        "title": "7.5.2 Variation Sources",
-        "page": 293
-      },
-      {
-        "level": 3,
-        "title": "7.5.3 Variation Impacts",
-        "page": 296
-      },
-      {
-        "level": 2,
-        "title": "7.6 Variation-Tolerant Design",
-        "page": 301
-      },
-      {
-        "level": 3,
-        "title": "7.6.1 Adaptive Control",
-        "page": 302
+        "title": "5.5 Memory Arrays",
+        "page": 289
       },
       {
         "level": 3,
-        "title": "7.6.2 Fault Tolerance",
-        "page": 302
-      },
-      {
-        "level": 2,
-        "title": "7.7 Pitfalls and Fallacies",
-        "page": 304
-      },
-      {
-        "level": 2,
-        "title": "7.8 Historical Perspective",
-        "page": 305
-      },
-      {
-        "level": 2,
-        "title": "Summary",
-        "page": 311
+        "title": "5.5.1 Overview",
+        "page": 289
       },
       {
-        "level": 2,
-        "title": "Exercises",
-        "page": 311
+        "level": 4,
+        "title": "Bit Cells",
+        "page": 289
       },
       {
-        "level": 1,
-        "title": "Chapter 8 Circuit Simulation",
-        "page": 314
+        "level": 4,
+        "title": "Organization",
+        "page": 290
       },
       {
-        "level": 2,
-        "title": "8.1 Introduction",
-        "page": 314
+        "level": 4,
+        "title": "Memory Ports",
+        "page": 290
       },
       {
-        "level": 2,
-        "title": "8.2 A SPICE Tutorial",
-        "page": 315
+        "level": 4,
+        "title": "Memory Types",
+        "page": 291
       },
       {
         "level": 3,
-        "title": "8.2.1 Sources and Passive Components",
-        "page": 315
+        "title": "5.5.2 Dynamic Random Access Memory (DRAM)",
+        "page": 291
       },
       {
         "level": 3,
-        "title": "8.2.2 Transistor DC Analysis",
-        "page": 319
+        "title": "5.5.3 Static Random Access Memory (SRAM)",
+        "page": 292
       },
       {
         "level": 3,
-        "title": "8.2.3 Inverter Transient Analysis",
-        "page": 319
+        "title": "5.5.4 Area and Delay",
+        "page": 292
       },
       {
-        "level": 3,
-        "title": "8.2.4 Subcircuits and Measurement",
-        "page": 321
-      },
-      {
-        "level": 3,
-        "title": "8.2.5 Optimization",
-        "page": 323
-      },
-      {
-        "level": 3,
-        "title": "8.2.6 Other HSPICE Commands",
-        "page": 325
-      },
-      {
-        "level": 2,
-        "title": "8.3 Device Models",
-        "page": 325
-      },
-      {
-        "level": 3,
-        "title": "8.3.1 Level 1 Models",
-        "page": 326
-      },
-      {
-        "level": 3,
-        "title": "8.3.2 Level 2 and 3 Models",
-        "page": 327
-      },
-      {
-        "level": 3,
-        "title": "8.3.3 BSIM Models",
-        "page": 327
-      },
-      {
-        "level": 3,
-        "title": "8.3.4 Diffusion Capacitance Models",
-        "page": 327
-      },
-      {
-        "level": 3,
-        "title": "8.3.5 Design Corners",
-        "page": 329
-      },
-      {
-        "level": 2,
-        "title": "8.4 Device Characterization",
-        "page": 330
-      },
-      {
-        "level": 3,
-        "title": "8.4.1 I-V Characteristics",
-        "page": 330
-      },
-      {
-        "level": 3,
-        "title": "8.4.2 Threshold Voltage",
-        "page": 333
-      },
-      {
-        "level": 3,
-        "title": "8.4.3 Gate Capacitance",
-        "page": 335
-      },
-      {
-        "level": 3,
-        "title": "8.4.4 Parasitic Capacitance",
-        "page": 335
-      },
-      {
-        "level": 3,
-        "title": "8.4.5 Effective Resistance",
-        "page": 337
-      },
-      {
-        "level": 3,
-        "title": "8.4.6 Comparison of Processes",
-        "page": 338
-      },
-      {
-        "level": 3,
-        "title": "8.4.7 Process and Environmental Sensitivity",
-        "page": 340
-      },
-      {
-        "level": 2,
-        "title": "8.5 Circuit Characterization",
-        "page": 340
-      },
-      {
-        "level": 3,
-        "title": "8.5.1 Path Simulations",
-        "page": 340
-      },
-      {
-        "level": 3,
-        "title": "8.5.2 DC Transfer Characteristics",
-        "page": 342
-      },
-      {
-        "level": 3,
-        "title": "8.5.3 Logical Effort",
-        "page": 342
-      },
-      {
-        "level": 3,
-        "title": "8.5.4 Power and Energy",
-        "page": 345
-      },
-      {
-        "level": 3,
-        "title": "8.5.5 Simulating Mismatches",
-        "page": 346
-      },
-      {
-        "level": 3,
-        "title": "8.5.6 Monte Carlo Simulation",
-        "page": 346
-      },
-      {
-        "level": 2,
-        "title": "8.6 Interconnect Simulation",
-        "page": 346
-      },
-      {
-        "level": 2,
-        "title": "8.7 Pitfalls and Fallacies",
-        "page": 349
-      },
-      {
-        "level": 2,
-        "title": "Summary",
-        "page": 351
-      },
-      {
-        "level": 2,
-        "title": "Exercises",
-        "page": 351
-      },
-      {
-        "level": 1,
-        "title": "Chapter 9 Combinational Circuit Design",
-        "page": 354
-      },
-      {
-        "level": 2,
-        "title": "9.1 Introduction",
-        "page": 354
-      },
-      {
-        "level": 2,
-        "title": "9.2 Circuit Families",
-        "page": 355
-      },
-      {
-        "level": 3,
-        "title": "9.2.1 Static CMOS",
-        "page": 356
-      },
-      {
-        "level": 3,
-        "title": "9.2.2 Ratioed Circuits",
-        "page": 361
-      },
-      {
-        "level": 3,
-        "title": "9.2.3 Cascode Voltage Switch Logic",
-        "page": 366
-      },
-      {
-        "level": 3,
-        "title": "9.2.4 Dynamic Circuits",
-        "page": 366
-      },
-      {
-        "level": 3,
-        "title": "9.2.5 Pass-Transistor Circuits",
-        "page": 376
-      },
-      {
-        "level": 2,
-        "title": "9.3 Circuit Pitfalls",
-        "page": 381
-      },
-      {
-        "level": 3,
-        "title": "9.3.1 Threshold Drops",
-        "page": 382
-      },
-      {
-        "level": 3,
-        "title": "9.3.2 Ratio Failures",
-        "page": 382
-      },
-      {
-        "level": 3,
-        "title": "9.3.3 Leakage",
-        "page": 383
-      },
-      {
-        "level": 3,
-        "title": "9.3.4 Charge Sharing",
-        "page": 383
-      },
-      {
-        "level": 3,
-        "title": "9.3.5 Power Supply Noise",
-        "page": 383
-      },
-      {
-        "level": 3,
-        "title": "9.3.6 Hot Spots",
-        "page": 384
-      },
-      {
-        "level": 3,
-        "title": "9.3.7 Minority Carrier Injection",
-        "page": 384
-      },
-      {
-        "level": 3,
-        "title": "9.3.8 Back-Gate Coupling",
-        "page": 385
-      },
-      {
-        "level": 3,
-        "title": "9.3.9 Diffusion Input Noise Sensitivity",
-        "page": 385
-      },
-      {
-        "level": 3,
-        "title": "9.3.10 Process Sensitivity",
-        "page": 385
-      },
-      {
-        "level": 3,
-        "title": "9.3.11 Example: Domino Noise Budgets",
-        "page": 386
-      },
-      {
-        "level": 2,
-        "title": "9.4 More Circuit Families",
-        "page": 387
-      },
-      {
-        "level": 2,
-        "title": "9.5 Silicon-On-Insulator Circuit Design",
-        "page": 387
-      },
-      {
-        "level": 3,
-        "title": "9.5.1 Floating Body Voltage",
-        "page": 388
-      },
-      {
-        "level": 3,
-        "title": "9.5.2 SOI Advantages",
-        "page": 389
-      },
-      {
-        "level": 3,
-        "title": "9.5.3 SOI Disadvantages",
-        "page": 389
-      },
-      {
-        "level": 3,
-        "title": "9.5.4 Implications for Circuit Styles",
-        "page": 390
-      },
-      {
-        "level": 3,
-        "title": "9.5.5 Summary",
-        "page": 391
-      },
-      {
-        "level": 2,
-        "title": "9.6 Subthreshold Circuit Design",
-        "page": 391
-      },
-      {
-        "level": 3,
-        "title": "9.6.1 Sizing",
-        "page": 392
-      },
-      {
-        "level": 3,
-        "title": "9.6.2 Gate Selection",
-        "page": 392
-      },
-      {
-        "level": 2,
-        "title": "9.7 Pitfalls and Fallacies",
-        "page": 393
-      },
-      {
-        "level": 2,
-        "title": "9.8 Historical Perspective",
-        "page": 394
-      },
-      {
-        "level": 2,
-        "title": "Summary",
-        "page": 396
-      },
-      {
-        "level": 2,
-        "title": "Exercises",
-        "page": 397
-      },
-      {
-        "level": 1,
-        "title": "Chapter 10 Sequential Circuit Design",
-        "page": 402
-      },
-      {
-        "level": 2,
-        "title": "10.1 Introduction",
-        "page": 402
-      },
-      {
-        "level": 2,
-        "title": "10.2 Sequencing Static Circuits",
-        "page": 403
-      },
-      {
-        "level": 3,
-        "title": "10.2.1 Sequencing Methods",
-        "page": 403
-      },
-      {
-        "level": 3,
-        "title": "10.2.2 Max-Delay Constraints",
-        "page": 406
-      },
-      {
-        "level": 3,
-        "title": "10.2.3 Min-Delay Constraints",
-        "page": 410
-      },
-      {
-        "level": 3,
-        "title": "10.2.4 Time Borrowing",
-        "page": 413
-      },
-      {
-        "level": 3,
-        "title": "10.2.5 Clock Skew",
-        "page": 416
-      },
-      {
-        "level": 2,
-        "title": "10.3 Circuit Design of Latches and Flip-Flops",
-        "page": 418
-      },
-      {
-        "level": 3,
-        "title": "10.3.1 Conventional CMOS Latches",
-        "page": 419
-      },
-      {
-        "level": 3,
-        "title": "10.3.2 Conventional CMOS Flip-Flops",
-        "page": 420
-      },
-      {
-        "level": 3,
-        "title": "10.3.3 Pulsed Latches",
-        "page": 422
-      },
-      {
-        "level": 3,
-        "title": "10.3.4 Resettable Latches and Flip-Flops",
-        "page": 423
-      },
-      {
-        "level": 3,
-        "title": "10.3.5 Enabled Latches and Flip-Flops",
-        "page": 424
-      },
-      {
-        "level": 3,
-        "title": "10.3.6 Incorporating Logic into Latches",
-        "page": 425
-      },
-      {
-        "level": 3,
-        "title": "10.3.7 Klass Semidynamic Flip-Flop (SDFF)",
-        "page": 426
-      },
-      {
-        "level": 3,
-        "title": "10.3.8 Differential Flip-Flops",
-        "page": 426
-      },
-      {
-        "level": 3,
-        "title": "10.3.9 Dual Edge-Triggered Flip-Flops",
-        "page": 427
-      },
-      {
-        "level": 3,
-        "title": "10.3.10 Radiation-Hardened Flip-Flops",
-        "page": 428
-      },
-      {
-        "level": 3,
-        "title": "10.3.11 True Single-Phase-Clock (TSPC) Latches and Flip-Flops",
-        "page": 429
-      },
-      {
-        "level": 2,
-        "title": "10.4 Static Sequencing Element Methodology",
-        "page": 429
-      },
-      {
-        "level": 3,
-        "title": "10.4.1 Choice of Elements",
-        "page": 430
-      },
-      {
-        "level": 3,
-        "title": "10.4.2 Characterizing Sequencing Element Delays",
-        "page": 432
-      },
-      {
-        "level": 3,
-        "title": "10.4.3 State Retention Registers",
-        "page": 435
-      },
-      {
-        "level": 3,
-        "title": "10.4.4 Level-Converter Flip-Flops",
-        "page": 435
-      },
-      {
-        "level": 3,
-        "title": "10.4.5 Design Margin and Adaptive Sequential Elements",
-        "page": 436
-      },
-      {
-        "level": 3,
-        "title": "10.4.6 Two-Phase Timing Types",
-        "page": 438
-      },
-      {
-        "level": 2,
-        "title": "10.5 Sequencing Dynamic Circuits",
-        "page": 438
-      },
-      {
-        "level": 2,
-        "title": "10.6 Synchronizers",
-        "page": 438
-      },
-      {
-        "level": 3,
-        "title": "10.6.1 Metastability",
-        "page": 439
-      },
-      {
-        "level": 3,
-        "title": "10.6.2 A Simple Synchronizer",
-        "page": 442
-      },
-      {
-        "level": 3,
-        "title": "10.6.3 Communicating Between Asynchronous Clock Domains",
-        "page": 443
-      },
-      {
-        "level": 3,
-        "title": "10.6.4 Common Synchronizer Mistakes",
-        "page": 444
-      },
-      {
-        "level": 3,
-        "title": "10.6.5 Arbiters",
-        "page": 446
-      },
-      {
-        "level": 3,
-        "title": "10.6.6 Degrees of Synchrony",
-        "page": 446
-      },
-      {
-        "level": 2,
-        "title": "10.7 Wave Pipelining",
-        "page": 447
-      },
-      {
-        "level": 2,
-        "title": "10.8 Pitfalls and Fallacies",
-        "page": 449
-      },
-      {
-        "level": 2,
-        "title": "10.9 Case Study: Pentium 4 and Itanium 2 Sequencing Methodologies",
-        "page": 450
-      },
-      {
-        "level": 2,
-        "title": "Summary",
-        "page": 450
-      },
-      {
-        "level": 2,
-        "title": "Exercises",
-        "page": 452
-      },
-      {
-        "level": 1,
-        "title": "Chapter 11 Datapath Subsystems",
-        "page": 456
-      },
-      {
-        "level": 2,
-        "title": "11.1 Introduction",
-        "page": 456
-      },
-      {
-        "level": 2,
-        "title": "11.2 Addition/Subtraction",
-        "page": 456
-      },
-      {
-        "level": 3,
-        "title": "11.2.1 Single-Bit Addition",
-        "page": 457
-      },
-      {
-        "level": 3,
-        "title": "11.2.2 Carry-Propagate Addition",
-        "page": 461
-      },
-      {
-        "level": 3,
-        "title": "11.2.3 Subtraction",
-        "page": 485
-      },
-      {
-        "level": 3,
-        "title": "11.2.4 Multiple-Input Addition",
-        "page": 485
-      },
-      {
-        "level": 3,
-        "title": "11.2.5 Flagged Prefix Adders",
-        "page": 486
-      },
-      {
-        "level": 2,
-        "title": "11.3 One/Zero Detectors",
-        "page": 488
-      },
-      {
-        "level": 2,
-        "title": "11.4 Comparators",
-        "page": 489
+        "level": 3,
+        "title": "5.5.5 Register Files",
+        "page": 293
       },
       {
         "level": 3,
-        "title": "11.4.1 Magnitude Comparator",
-        "page": 489
+        "title": "5.5.6 Read Only Memory",
+        "page": 293
       },
       {
         "level": 3,
-        "title": "11.4.2 Equality Comparator",
-        "page": 489
+        "title": "5.5.7 Logic Using Memory Arrays",
+        "page": 295
       },
       {
         "level": 3,
-        "title": "11.4.3 K = A + B Comparator",
-        "page": 490
+        "title": "5.5.8 Memory HDL",
+        "page": 296
       },
       {
         "level": 2,
-        "title": "11.5 Counters",
-        "page": 490
+        "title": "5.6 Logic Arrays",
+        "page": 296
       },
       {
         "level": 3,
-        "title": "11.5.1 Binary Counters",
-        "page": 491
+        "title": "5.6.1 Programmable Logic Array",
+        "page": 297
       },
       {
         "level": 3,
-        "title": "11.5.2 Fast Binary Counters",
-        "page": 492
+        "title": "5.6.2 Field Programmable Gate Array",
+        "page": 299
       },
       {
         "level": 3,
-        "title": "11.5.3 Ring and Johnson Counters",
-        "page": 493
+        "title": "5.6.3 Array Implementations",
+        "page": 304
       },
       {
-        "level": 3,
-        "title": "11.5.4 Linear-Feedback Shift Registers",
-        "page": 493
+        "level": 2,
+        "title": "5.7 Summary",
+        "page": 306
       },
       {
         "level": 2,
-        "title": "11.6 Boolean Logical Operations",
-        "page": 495
+        "title": "Exercises",
+        "page": 307
       },
       {
         "level": 2,
-        "title": "11.7 Coding",
-        "page": 495
+        "title": "Interview Questions",
+        "page": 318
       },
       {
-        "level": 3,
-        "title": "11.7.1 Parity",
-        "page": 495
+        "level": 1,
+        "title": "6 Architecture",
+        "page": 320
       },
       {
-        "level": 3,
-        "title": "11.7.2 Error-Correcting Codes",
-        "page": 495
+        "level": 2,
+        "title": "6.1 Introduction",
+        "page": 320
       },
       {
-        "level": 3,
-        "title": "11.7.3 Gray Codes",
-        "page": 497
+        "level": 2,
+        "title": "6.2 Assembly Language",
+        "page": 321
       },
       {
         "level": 3,
-        "title": "11.7.4 XOR/XNOR Circuit Forms",
-        "page": 498
-      },
-      {
-        "level": 2,
-        "title": "11.8 Shifters",
-        "page": 499
+        "title": "6.2.1 Instructions",
+        "page": 322
       },
       {
         "level": 3,
-        "title": "11.8.1 Funnel Shifter",
-        "page": 500
+        "title": "6.2.2 Operands: Registers, Memory, and Constants",
+        "page": 323
       },
       {
-        "level": 3,
-        "title": "11.8.2 Barrel Shifter",
-        "page": 502
+        "level": 4,
+        "title": "Registers",
+        "page": 324
       },
       {
-        "level": 3,
-        "title": "11.8.3 Alternative Shift Functions",
-        "page": 503
+        "level": 4,
+        "title": "The Register Set",
+        "page": 325
       },
       {
-        "level": 2,
-        "title": "11.9 Multiplication",
-        "page": 503
+        "level": 4,
+        "title": "Constants/Immediates",
+        "page": 325
       },
       {
-        "level": 3,
-        "title": "11.9.1 Unsigned Array Multiplication",
-        "page": 505
+        "level": 4,
+        "title": "Memory",
+        "page": 326
       },
       {
-        "level": 3,
-        "title": "11.9.2 Two’s Complement Array Multiplication",
-        "page": 506
+        "level": 2,
+        "title": "6.3 Programming",
+        "page": 328
       },
       {
         "level": 3,
-        "title": "11.9.3 Booth Encoding",
-        "page": 507
+        "title": "6.3.1 Data-processing Instructions",
+        "page": 328
       },
       {
-        "level": 3,
-        "title": "11.9.4 Column Addition",
-        "page": 512
+        "level": 4,
+        "title": "Logical Instructions",
+        "page": 328
       },
       {
-        "level": 3,
-        "title": "11.9.5 Final Addition",
-        "page": 516
+        "level": 4,
+        "title": "Shift Instructions",
+        "page": 329
       },
       {
-        "level": 3,
-        "title": "11.9.6 Fused Multiply-Add",
-        "page": 517
+        "level": 4,
+        "title": "Multiply Instructions*",
+        "page": 330
       },
       {
         "level": 3,
-        "title": "11.9.7 Serial Multiplication",
-        "page": 517
+        "title": "6.3.2 Condition Flags",
+        "page": 331
       },
       {
         "level": 3,
-        "title": "11.9.8 Summary",
-        "page": 517
+        "title": "6.3.3 Branching",
+        "page": 333
       },
       {
-        "level": 2,
-        "title": "11.10 Parallel-Prefix Computations",
-        "page": 518
+        "level": 3,
+        "title": "6.3.4 Conditional Statements",
+        "page": 334
       },
       {
-        "level": 2,
-        "title": "11.11 Pitfalls and Fallacies",
-        "page": 520
+        "level": 4,
+        "title": "if Statements",
+        "page": 334
       },
       {
-        "level": 2,
-        "title": "Summary",
-        "page": 521
+        "level": 4,
+        "title": "if/else Statements",
+        "page": 335
       },
       {
-        "level": 2,
-        "title": "Exercises",
-        "page": 521
+        "level": 4,
+        "title": "switch/case Statements*",
+        "page": 336
       },
       {
-        "level": 1,
-        "title": "Chapter 12 Array Subsystems",
-        "page": 524
+        "level": 3,
+        "title": "6.3.5 Getting Loopy",
+        "page": 337
       },
       {
-        "level": 2,
-        "title": "12.1 Introduction",
-        "page": 524
+        "level": 4,
+        "title": "while Loops",
+        "page": 337
       },
       {
-        "level": 2,
-        "title": "12.2 SRAM",
-        "page": 525
+        "level": 4,
+        "title": "for Loops",
+        "page": 337
       },
       {
         "level": 3,
-        "title": "12.2.1 SRAM Cells",
-        "page": 526
+        "title": "6.3.6 Memory",
+        "page": 338
       },
       {
-        "level": 3,
-        "title": "12.2.2 Row Circuitry",
-        "page": 533
+        "level": 4,
+        "title": "Bytes and Characters",
+        "page": 340
       },
       {
         "level": 3,
-        "title": "12.2.3 Column Circuitry",
-        "page": 537
+        "title": "6.3.7 Function Calls",
+        "page": 342
       },
       {
-        "level": 3,
-        "title": "12.2.4 Multi-Ported SRAM and Register Files",
-        "page": 541
+        "level": 4,
+        "title": "Function Calls and Returns",
+        "page": 343
       },
       {
-        "level": 3,
-        "title": "12.2.5 Large SRAMs",
-        "page": 542
+        "level": 4,
+        "title": "Input Arguments and Return Values",
+        "page": 344
       },
       {
-        "level": 3,
-        "title": "12.2.6 Low-Power SRAMs",
-        "page": 544
+        "level": 4,
+        "title": "The Stack",
+        "page": 345
       },
       {
-        "level": 3,
-        "title": "12.2.7 Area, Delay, and Power of RAMs and Register Files",
-        "page": 547
+        "level": 4,
+        "title": "Loading and Storing Multiple Registers",
+        "page": 347
       },
       {
-        "level": 2,
-        "title": "12.3 DRAM",
-        "page": 549
+        "level": 4,
+        "title": "Preserved Registers",
+        "page": 347
       },
       {
-        "level": 3,
-        "title": "12.3.1 Subarray Architectures",
-        "page": 550
+        "level": 4,
+        "title": "Nonleaf Function Calls",
+        "page": 349
       },
       {
-        "level": 3,
-        "title": "12.3.2 Column Circuitry",
-        "page": 552
+        "level": 4,
+        "title": "Recursive Function Calls",
+        "page": 351
       },
       {
-        "level": 3,
-        "title": "12.3.3 Embedded DRAM",
-        "page": 553
+        "level": 4,
+        "title": "Additional Arguments and Local Variables*",
+        "page": 353
       },
       {
         "level": 2,
-        "title": "12.4 Read-Only Memory",
-        "page": 554
+        "title": "6.4 Machine Language",
+        "page": 354
       },
       {
         "level": 3,
-        "title": "12.4.1 Programmable ROMs",
-        "page": 556
+        "title": "6.4.1 Data-processing Instructions",
+        "page": 354
       },
       {
         "level": 3,
-        "title": "12.4.2 NAND ROMs",
-        "page": 557
+        "title": "6.4.2 Memory Instructions",
+        "page": 358
       },
       {
         "level": 3,
-        "title": "12.4.3 Flash",
-        "page": 558
+        "title": "6.4.3 Branch Instructions",
+        "page": 359
       },
       {
-        "level": 2,
-        "title": "12.5 Serial Access Memories",
-        "page": 560
+        "level": 3,
+        "title": "6.4.4 Addressing Modes",
+        "page": 361
       },
       {
         "level": 3,
-        "title": "12.5.1 Shift Registers",
-        "page": 560
+        "title": "6.4.5 Interpreting Machine Language Code",
+        "page": 361
       },
       {
         "level": 3,
-        "title": "12.5.2 Queues (FIFO, LIFO)",
-        "page": 560
+        "title": "6.4.6 The Power of the Stored Program",
+        "page": 362
       },
       {
         "level": 2,
-        "title": "12.6 Content-Addressable Memory",
-        "page": 562
+        "title": "6.5 Lights, Camera, Action: Compiling, Assembling, and Loading",
+        "page": 364
       },
       {
-        "level": 2,
-        "title": "12.7 Programmable Logic Arrays",
-        "page": 564
+        "level": 3,
+        "title": "6.5.1 The Memory Map",
+        "page": 364
       },
       {
-        "level": 2,
-        "title": "12.8 Robust Memory Design",
-        "page": 568
+        "level": 4,
+        "title": "The Text Segment",
+        "page": 365
       },
       {
-        "level": 3,
-        "title": "12.8.1 Redundancy",
-        "page": 568
+        "level": 4,
+        "title": "The Global Data Segment",
+        "page": 365
       },
       {
-        "level": 3,
-        "title": "12.8.2 Error Correcting Codes (ECC)",
-        "page": 570
+        "level": 4,
+        "title": "The Dynamic Data Segment",
+        "page": 365
       },
       {
-        "level": 3,
-        "title": "12.8.3 Radiation Hardening",
-        "page": 570
+        "level": 4,
+        "title": "The Exception Handler, OS, and I/O Segments",
+        "page": 365
       },
       {
-        "level": 2,
-        "title": "12.9 Historical Perspective",
-        "page": 571
+        "level": 3,
+        "title": "6.5.2 Compilation",
+        "page": 365
       },
       {
-        "level": 2,
-        "title": "Summary",
-        "page": 572
+        "level": 3,
+        "title": "6.5.3 Assembling",
+        "page": 367
       },
       {
-        "level": 2,
-        "title": "Exercises",
-        "page": 573
+        "level": 3,
+        "title": "6.5.4 Linking",
+        "page": 368
       },
       {
-        "level": 1,
-        "title": "Chapter 13 Special-Purpose Subsystems",
-        "page": 576
+        "level": 3,
+        "title": "6.5.5 Loading",
+        "page": 369
       },
       {
         "level": 2,
-        "title": "13.1 Introduction",
-        "page": 576
+        "title": "6.6 Odds and Ends",
+        "page": 370
       },
       {
-        "level": 2,
-        "title": "13.2 Packaging and Cooling",
-        "page": 576
+        "level": 3,
+        "title": "6.6.1 Loading Literals",
+        "page": 370
       },
       {
         "level": 3,
-        "title": "13.2.1 Package Options",
-        "page": 576
+        "title": "6.6.2 NOP",
+        "page": 371
       },
       {
         "level": 3,
-        "title": "13.2.2 Chip-to-Package Connections",
-        "page": 577
+        "title": "6.6.3 Exceptions",
+        "page": 372
       },
       {
-        "level": 3,
-        "title": "13.2.3 Package Parasitics",
-        "page": 578
+        "level": 4,
+        "title": "Execution Modes and Privilege Levels",
+        "page": 372
       },
       {
-        "level": 3,
-        "title": "13.2.4 Heat Dissipation",
-        "page": 578
+        "level": 4,
+        "title": "Exception Vector Table",
+        "page": 372
       },
       {
-        "level": 3,
-        "title": "13.2.5 Temperature Sensors",
-        "page": 580
+        "level": 4,
+        "title": "Banked Registers",
+        "page": 373
       },
       {
-        "level": 2,
-        "title": "13.3 Power Distribution",
-        "page": 582
+        "level": 4,
+        "title": "Exception Handling",
+        "page": 374
       },
       {
-        "level": 3,
-        "title": "13.3.1 On-Chip Power Distribution Network",
-        "page": 583
+        "level": 4,
+        "title": "Exception-Related Instructions",
+        "page": 374
       },
       {
-        "level": 3,
-        "title": "13.3.2 IR Drops",
-        "page": 584
+        "level": 4,
+        "title": "Start-up",
+        "page": 375
       },
       {
-        "level": 3,
-        "title": "13.3.3 L di/dt Noise",
-        "page": 585
+        "level": 2,
+        "title": "6.7 Evolution of ARM Architecture",
+        "page": 375
       },
       {
         "level": 3,
-        "title": "13.3.4 On-Chip Bypass Capacitance",
-        "page": 586
+        "title": "6.7.1 Thumb Instruction Set",
+        "page": 376
       },
       {
         "level": 3,
-        "title": "13.3.5 Power Network Modeling",
-        "page": 587
+        "title": "6.7.2 DSP Instructions",
+        "page": 377
       },
       {
         "level": 3,
-        "title": "13.3.6 Power Supply Filtering",
-        "page": 591
+        "title": "6.7.3 Floating-Point Instructions",
+        "page": 382
       },
       {
         "level": 3,
-        "title": "13.3.7 Charge Pumps",
-        "page": 591
+        "title": "6.7.4 Power-Saving and Security Instructions",
+        "page": 383
       },
       {
         "level": 3,
-        "title": "13.3.8 Substrate Noise",
-        "page": 592
+        "title": "6.7.5 SIMD Instructions",
+        "page": 383
       },
       {
         "level": 3,
-        "title": "13.3.9 Energy Scavenging",
-        "page": 592
+        "title": "6.7.6 64-bit Architecture",
+        "page": 385
       },
       {
         "level": 2,
-        "title": "13.4 Clocks",
-        "page": 593
+        "title": "6.8 Another Perspective: x86 Architecture",
+        "page": 385
       },
       {
         "level": 3,
-        "title": "13.4.1 Definitions",
-        "page": 593
+        "title": "6.8.1 x86 Registers",
+        "page": 387
       },
       {
         "level": 3,
-        "title": "13.4.2 Clock System Architecture",
-        "page": 595
+        "title": "6.8.2 x86 Operands",
+        "page": 387
       },
       {
         "level": 3,
-        "title": "13.4.3 Global Clock Generation",
-        "page": 596
+        "title": "6.8.3 Status Flags",
+        "page": 388
       },
       {
         "level": 3,
-        "title": "13.4.4 Global Clock Distribution",
-        "page": 598
+        "title": "6.8.4 x86 Instructions",
+        "page": 389
       },
       {
         "level": 3,
-        "title": "13.4.5 Local Clock Gaters",
-        "page": 602
+        "title": "6.8.5 x86 Instruction Encoding",
+        "page": 389
       },
       {
         "level": 3,
-        "title": "13.4.6 Clock Skew Budgets",
-        "page": 604
+        "title": "6.8.6 Other x86 Peculiarities",
+        "page": 392
       },
       {
         "level": 3,
-        "title": "13.4.7 Adaptive Deskewing",
-        "page": 606
+        "title": "6.8.7 The Big Picture",
+        "page": 393
       },
       {
         "level": 2,
-        "title": "13.5 PLLs and DLLs",
-        "page": 607
+        "title": "6.9 Summary",
+        "page": 393
       },
       {
-        "level": 3,
-        "title": "13.5.1 PLLs",
-        "page": 607
+        "level": 2,
+        "title": "Exercises",
+        "page": 395
       },
       {
-        "level": 3,
-        "title": "13.5.2 DLLs",
-        "page": 614
+        "level": 2,
+        "title": "Interview Questions",
+        "page": 408
       },
       {
-        "level": 3,
-        "title": "13.5.3 Pitfalls",
-        "page": 616
+        "level": 1,
+        "title": "7 Microarchitecture",
+        "page": 410
       },
       {
         "level": 2,
-        "title": "13.6 I/0",
-        "page": 617
+        "title": "7.1 Introduction",
+        "page": 410
       },
       {
         "level": 3,
-        "title": "13.6.1 Basic I/O Pad Circuits",
-        "page": 618
+        "title": "7.1.1 Architectural State and Instruction Set",
+        "page": 410
       },
       {
         "level": 3,
-        "title": "13.6.2 Electrostatic Discharge Protection",
-        "page": 620
+        "title": "7.1.2 Design Process",
+        "page": 411
       },
       {
         "level": 3,
-        "title": "13.6.3 Example: MOSIS I/O Pads",
-        "page": 621
+        "title": "7.1.3 Microarchitectures",
+        "page": 413
       },
       {
-        "level": 3,
-        "title": "13.6.4 Mixed-Voltage I/O",
-        "page": 623
+        "level": 2,
+        "title": "7.2 Performance Analysis",
+        "page": 414
       },
       {
         "level": 2,
-        "title": "13.7 High-Speed Links",
-        "page": 624
+        "title": "7.3 Single-Cycle Processor",
+        "page": 415
       },
       {
         "level": 3,
-        "title": "13.7.1 High-Speed I/O Channels",
-        "page": 624
+        "title": "7.3.1 Single-Cycle Datapath",
+        "page": 415
       },
       {
         "level": 3,
-        "title": "13.7.2 Channel Noise and Interference",
-        "page": 627
+        "title": "7.3.2 Single-Cycle Control",
+        "page": 422
       },
       {
         "level": 3,
-        "title": "13.7.3 High-Speed Transmitters and Receivers",
-        "page": 628
+        "title": "7.3.3 More Instructions",
+        "page": 427
       },
       {
         "level": 3,
-        "title": "13.7.4 Synchronous Data Transmission",
-        "page": 633
+        "title": "7.3.4 Performance Analysis",
+        "page": 427
       },
       {
-        "level": 3,
-        "title": "13.7.5 Clock Recovery in Source-Synchronous Systems",
-        "page": 633
+        "level": 2,
+        "title": "7.4 Multicycle Processor",
+        "page": 431
       },
       {
         "level": 3,
-        "title": "13.7.6 Clock Recovery in Mesochronous Systems",
-        "page": 635
+        "title": "7.4.1 Multicycle Datapath",
+        "page": 432
       },
       {
-        "level": 3,
-        "title": "13.7.7 Clock Recovery in Pleisochronous Systems",
-        "page": 637
+        "level": 4,
+        "title": "LDR",
+        "page": 432
       },
       {
-        "level": 2,
-        "title": "13.8 Random Circuits",
-        "page": 637
+        "level": 4,
+        "title": "STR",
+        "page": 436
+      },
+      {
+        "level": 4,
+        "title": "Data-Processing Instructions with Immediate Addressing",
+        "page": 437
       },
       {
         "level": 3,
-        "title": "13.8.1 True Random Number Generators",
-        "page": 637
+        "title": "7.4.2 Multicycle Control",
+        "page": 438
       },
       {
         "level": 3,
-        "title": "13.8.2 Chip Identification",
-        "page": 638
+        "title": "7.4.3 Performance Analysis",
+        "page": 446
       },
       {
         "level": 2,
-        "title": "13.9 Pitfalls and Fallacies",
-        "page": 639
+        "title": "7.5 Pipelined Processor",
+        "page": 450
       },
       {
-        "level": 2,
-        "title": "Summary",
-        "page": 640
+        "level": 3,
+        "title": "7.5.1 Pipelined Datapath",
+        "page": 453
       },
       {
-        "level": 2,
-        "title": "Exercises",
-        "page": 641
+        "level": 3,
+        "title": "7.5.2 Pipelined Control",
+        "page": 455
       },
       {
-        "level": 1,
-        "title": "Chapter 14 Design Methodology and Tools",
-        "page": 642
+        "level": 3,
+        "title": "7.5.3 Hazards",
+        "page": 456
       },
       {
-        "level": 2,
-        "title": "14.1 Introduction",
-        "page": 642
+        "level": 3,
+        "title": "7.5.4 Performance Analysis",
+        "page": 466
       },
       {
         "level": 2,
-        "title": "14.2 Structured Design Strategies",
-        "page": 644
+        "title": "7.6 HDL Representation",
+        "page": 468
       },
       {
         "level": 3,
-        "title": "14.2.1 A Software Radio—A System Example",
-        "page": 645
+        "title": "7.6.1 Single-Cycle Processor",
+        "page": 469
       },
       {
         "level": 3,
-        "title": "14.2.2 Hierarchy",
-        "page": 647
+        "title": "7.6.2 Generic Building Blocks",
+        "page": 474
       },
       {
         "level": 3,
-        "title": "14.2.3 Regularity",
-        "page": 650
+        "title": "7.6.3 Testbench",
+        "page": 477
       },
       {
-        "level": 3,
-        "title": "14.2.4 Modularity",
-        "page": 652
+        "level": 2,
+        "title": "7.7 Advanced Microarchitecture",
+        "page": 481
       },
       {
         "level": 3,
-        "title": "14.2.5 Locality",
-        "page": 653
+        "title": "7.7.1 Deep Pipelines",
+        "page": 482
       },
       {
         "level": 3,
-        "title": "14.2.6 Summary",
-        "page": 654
+        "title": "7.7.2 Micro-Operations",
+        "page": 483
       },
       {
-        "level": 2,
-        "title": "14.3 Design Methods",
-        "page": 654
+        "level": 3,
+        "title": "7.7.3 Branch Prediction",
+        "page": 484
       },
       {
         "level": 3,
-        "title": "14.3.1 Microprocessor/DSP",
-        "page": 654
+        "title": "7.7.4 Superscalar Processor",
+        "page": 486
       },
       {
         "level": 3,
-        "title": "14.3.2 Programmable Logic",
-        "page": 655
+        "title": "7.7.5 Out-of-Order Processor",
+        "page": 488
       },
       {
         "level": 3,
-        "title": "14.3.3 Gate Array and Sea of Gates Design",
-        "page": 658
+        "title": "7.7.6 Register Renaming",
+        "page": 490
       },
       {
         "level": 3,
-        "title": "14.3.4 Cell-Based Design",
-        "page": 659
+        "title": "7.7.7 Multithreading",
+        "page": 492
       },
       {
         "level": 3,
-        "title": "14.3.5 Full Custom Design",
-        "page": 661
+        "title": "7.7.8 Multiprocessors",
+        "page": 493
       },
       {
-        "level": 3,
-        "title": "14.3.6 Platform-Based Design—System on a Chip",
-        "page": 662
+        "level": 2,
+        "title": "7.8 Real-World Perspective: Evolution of ARM Microarchitecture",
+        "page": 495
       },
       {
-        "level": 3,
-        "title": "14.3.7 Summary",
-        "page": 663
+        "level": 2,
+        "title": "7.9 Summary",
+        "page": 501
       },
       {
         "level": 2,
-        "title": "14.4 Design Flows",
-        "page": 663
+        "title": "Exercises",
+        "page": 503
       },
       {
-        "level": 3,
-        "title": "14.4.1 Behavioral Synthesis Design Flow (ASIC Design Flow)",
-        "page": 664
+        "level": 2,
+        "title": "Interview Questions",
+        "page": 509
       },
       {
-        "level": 3,
-        "title": "14.4.2 Automated Layout Generation",
-        "page": 668
+        "level": 1,
+        "title": "8 Memory Systems",
+        "page": 512
       },
       {
-        "level": 3,
-        "title": "14.4.3 Mixed-Signal or Custom-Design Flow",
-        "page": 672
+        "level": 2,
+        "title": "8.1 Introduction",
+        "page": 512
       },
       {
         "level": 2,
-        "title": "14.5 Design Economics",
-        "page": 673
+        "title": "8.2 Memory System Performance Analysis",
+        "page": 516
       },
       {
-        "level": 3,
-        "title": "14.5.1 Non-Recurring Engineering Costs (NREs)",
-        "page": 674
+        "level": 2,
+        "title": "8.3 Caches",
+        "page": 517
       },
       {
         "level": 3,
-        "title": "14.5.2 Recurring Costs",
-        "page": 676
+        "title": "8.3.1 What Data is Held in the Cache?",
+        "page": 518
       },
       {
         "level": 3,
-        "title": "14.5.3 Fixed Costs",
-        "page": 677
+        "title": "8.3.2 How is Data Found?",
+        "page": 519
       },
       {
-        "level": 3,
-        "title": "14.5.4 Schedule",
-        "page": 678
+        "level": 4,
+        "title": "Direct Mapped Cache",
+        "page": 519
       },
       {
-        "level": 3,
-        "title": "14.5.5 Personpower",
-        "page": 680
+        "level": 4,
+        "title": "Multi-way Set Associative Cache",
+        "page": 523
+      },
+      {
+        "level": 4,
+        "title": "Fully Associative Cache",
+        "page": 524
+      },
+      {
+        "level": 4,
+        "title": "Block Size",
+        "page": 525
+      },
+      {
+        "level": 4,
+        "title": "Putting it All Together",
+        "page": 526
       },
       {
         "level": 3,
-        "title": "14.5.6 Project Management",
-        "page": 680
+        "title": "8.3.3 What Data is Replaced?",
+        "page": 527
       },
       {
         "level": 3,
-        "title": "14.5.7 Design Reuse",
-        "page": 681
+        "title": "8.3.4 Advanced Cache Design",
+        "page": 528
       },
       {
-        "level": 2,
-        "title": "14.6 Data Sheets and Documentation",
-        "page": 682
+        "level": 4,
+        "title": "Multiple-Level Caches",
+        "page": 529
       },
       {
-        "level": 3,
-        "title": "14.6.1 The Summary",
-        "page": 682
+        "level": 4,
+        "title": "Reducing Miss Rate",
+        "page": 530
+      },
+      {
+        "level": 4,
+        "title": "Write Policy",
+        "page": 531
       },
       {
         "level": 3,
-        "title": "14.6.2 Pinout",
-        "page": 682
+        "title": "8.3.5 The Evolution of ARM Caches",
+        "page": 532
+      },
+      {
+        "level": 2,
+        "title": "8.4 Virtual Memory",
+        "page": 533
       },
       {
         "level": 3,
-        "title": "14.6.3 Description of Operation",
-        "page": 682
+        "title": "8.4.1 Address Translation",
+        "page": 535
       },
       {
         "level": 3,
-        "title": "14.6.4 DC Specifications",
-        "page": 682
+        "title": "8.4.2 The Page Table",
+        "page": 537
       },
       {
         "level": 3,
-        "title": "14.6.5 AC Specifications",
-        "page": 683
+        "title": "8.4.3 The Translation Lookaside Buffer",
+        "page": 539
       },
       {
         "level": 3,
-        "title": "14.6.6 Package Diagram",
-        "page": 683
+        "title": "8.4.4 Memory Protection",
+        "page": 540
       },
       {
         "level": 3,
-        "title": "14.6.7 Principles of Operation Manual",
-        "page": 683
+        "title": "8.4.5 Replacement Policies",
+        "page": 541
       },
       {
         "level": 3,
-        "title": "14.6.8 User Manual",
-        "page": 683
+        "title": "8.4.6 Multilevel Page Tables",
+        "page": 541
       },
       {
         "level": 2,
-        "title": "14.7 CMOS Physical Design Styles",
-        "page": 683
+        "title": "8.5 Summary",
+        "page": 543
       },
       {
         "level": 2,
-        "title": "14.8 Pitfalls and Fallacies",
-        "page": 684
+        "title": "Epilogue",
+        "page": 544
       },
       {
         "level": 2,
         "title": "Exercises",
-        "page": 684
+        "page": 545
+      },
+      {
+        "level": 2,
+        "title": "Interview Questions",
+        "page": 554
       },
       {
         "level": 1,
-        "title": "Chapter 15 Testing, Debugging, and Verification",
-        "page": 686
+        "title": "9 I/O Systems",
+        "page": 557
       },
       {
         "level": 2,
-        "title": "15.1 Introduction",
-        "page": 686
+        "title": "9.1 Introduction",
+        "page": 557
       },
       {
-        "level": 3,
-        "title": "15.1.1 Logic Verification",
-        "page": 687
+        "level": 2,
+        "title": "9.2 Memory-Mapped I/O",
+        "page": 557
       },
       {
-        "level": 3,
-        "title": "15.1.2 Debugging",
-        "page": 689
+        "level": 2,
+        "title": "9.3 Embedded I/O Systems",
+        "page": 559
       },
       {
         "level": 3,
-        "title": "15.1.3 Manufacturing Tests",
-        "page": 691
+        "title": "9.3.1 BCM2835 System-on-Chip",
+        "page": 560
       },
       {
-        "level": 2,
-        "title": "15.2 Testers, Test Fixtures, and Test Programs",
-        "page": 693
+        "level": 3,
+        "title": "9.3.2 Device Drivers",
+        "page": 562
       },
       {
         "level": 3,
-        "title": "15.2.1 Testers and Test Fixtures",
-        "page": 693
+        "title": "9.3.3 General-Purpose Digital I/O",
+        "page": 564
       },
       {
         "level": 3,
-        "title": "15.2.2 Test Programs",
-        "page": 695
+        "title": "9.3.4 Serial I/O",
+        "page": 567
       },
       {
-        "level": 3,
-        "title": "15.2.3 Handlers",
-        "page": 696
+        "level": 4,
+        "title": "9.3.4.1 Serial Peripheral Interface (SPI)",
+        "page": 568
       },
       {
-        "level": 2,
-        "title": "15.3 Logic Verification Principles",
-        "page": 697
+        "level": 4,
+        "title": "9.3.4.2 Universal Asynchronous Receiver/Transmitter (UART)",
+        "page": 573
       },
       {
         "level": 3,
-        "title": "15.3.1 Test Vectors",
-        "page": 697
+        "title": "9.3.5 Timers",
+        "page": 579
       },
       {
         "level": 3,
-        "title": "15.3.2 Testbenches and Harnesses",
-        "page": 698
+        "title": "9.3.6 Analog I/O",
+        "page": 581
       },
       {
-        "level": 3,
-        "title": "15.3.3 Regression Testing",
-        "page": 698
+        "level": 4,
+        "title": "9.3.6.1 D/A Conversion",
+        "page": 581
       },
       {
-        "level": 3,
-        "title": "15.3.4 Version Control",
-        "page": 699
+        "level": 4,
+        "title": "9.3.6.2 Pulse-Width Modulation",
+        "page": 584
+      },
+      {
+        "level": 4,
+        "title": "9.3.6.3 A/D Conversion",
+        "page": 587
       },
       {
         "level": 3,
-        "title": "15.3.5 Bug Tracking",
-        "page": 700
+        "title": "9.3.7 Interrupts",
+        "page": 588
       },
       {
         "level": 2,
-        "title": "15.4 Silicon Debug Principles",
-        "page": 700
+        "title": "9.4 Other Microcontroller Peripherals",
+        "page": 588
       },
       {
-        "level": 2,
-        "title": "15.5 Manufacturing Test Principles",
-        "page": 703
+        "level": 3,
+        "title": "9.4.1 Character LCDs",
+        "page": 589
       },
       {
         "level": 3,
-        "title": "15.5.1 Fault Models",
-        "page": 704
+        "title": "9.4.2 VGA Monitor",
+        "page": 592
       },
       {
         "level": 3,
-        "title": "15.5.2 Observability",
-        "page": 706
+        "title": "9.4.3 Bluetooth Wireless Communication",
+        "page": 598
       },
       {
         "level": 3,
-        "title": "15.5.3 Controllability",
-        "page": 706
+        "title": "9.4.4 Motor Control",
+        "page": 599
       },
       {
-        "level": 3,
-        "title": "15.5.4 Repeatability",
-        "page": 706
+        "level": 4,
+        "title": "9.4.4.1 DC Motors",
+        "page": 600
       },
       {
-        "level": 3,
-        "title": "15.5.5 Survivability",
-        "page": 706
+        "level": 4,
+        "title": "9.4.4.2 Servo Motor",
+        "page": 604
       },
       {
-        "level": 3,
-        "title": "15.5.6 Fault Coverage",
-        "page": 707
+        "level": 4,
+        "title": "9.4.4.3 Stepper Motor",
+        "page": 605
+      },
+      {
+        "level": 2,
+        "title": "9.5 Bus Interfaces",
+        "page": 610
       },
       {
         "level": 3,
-        "title": "15.5.7 Automatic Test Pattern Generation (ATPG)",
-        "page": 707
+        "title": "9.5.1 AHB-Lite",
+        "page": 610
       },
       {
         "level": 3,
-        "title": "15.5.8 Delay Fault Testing",
-        "page": 707
+        "title": "9.5.2 Memory and Peripheral Interface Example",
+        "page": 611
       },
       {
         "level": 2,
-        "title": "15.6 Design for Testability",
-        "page": 708
+        "title": "9.6 PC I/O Systems",
+        "page": 613
       },
       {
         "level": 3,
-        "title": "15.6.1 Ad Hoc Testing",
-        "page": 708
+        "title": "9.6.1 USB",
+        "page": 615
       },
       {
         "level": 3,
-        "title": "15.6.2 Scan Design",
-        "page": 709
+        "title": "9.6.2 PCI and PCI Express",
+        "page": 615
       },
       {
         "level": 3,
-        "title": "15.6.3 Built-In Self-Test (BIST)",
-        "page": 711
+        "title": "9.6.3 DDR3 Memory",
+        "page": 616
       },
       {
         "level": 3,
-        "title": "15.6.4 IDDQ Testing",
-        "page": 714
+        "title": "9.6.4 Networking",
+        "page": 617
       },
       {
         "level": 3,
-        "title": "15.6.5 Design for Manufacturability",
-        "page": 714
-      },
-      {
-        "level": 2,
-        "title": "15.7 Boundary Scan",
-        "page": 715
+        "title": "9.6.5 SATA",
+        "page": 617
       },
       {
-        "level": 2,
-        "title": "15.8 Testing in a University Environment",
-        "page": 716
+        "level": 3,
+        "title": "9.6.6 Interfacing to a PC",
+        "page": 618
       },
       {
-        "level": 2,
-        "title": "15.9 Pitfalls and Fallacies",
-        "page": 717
+        "level": 4,
+        "title": "9.6.6.1 Data Acquisition Systems",
+        "page": 618
       },
       {
-        "level": 2,
-        "title": "Summary",
-        "page": 724
+        "level": 4,
+        "title": "9.6.6.2 USB Links",
+        "page": 619
       },
       {
         "level": 2,
-        "title": "Exercises",
-        "page": 724
+        "title": "9.7 Summary",
+        "page": 620
       },
       {
         "level": 1,
-        "title": "Appendix A: Hardware Description Languages",
-        "page": 726
+        "title": "Appendix A Digital System Implementation",
+        "page": 623
       },
       {
         "level": 2,
         "title": "A.1 Introduction",
-        "page": 726
-      },
-      {
-        "level": 3,
-        "title": "A.1.1 Modules",
-        "page": 727
-      },
-      {
-        "level": 3,
-        "title": "A.1.2 Simulation and Synthesis",
-        "page": 728
+        "page": 623
       },
       {
         "level": 2,
-        "title": "A.2 Combinational Logic",
-        "page": 729
-      },
-      {
-        "level": 3,
-        "title": "A.2.1 Bitwise Operators",
-        "page": 729
+        "title": "A.2 74xx Logic",
+        "page": 623
       },
       {
         "level": 3,
-        "title": "A.2.2 Comments and White Space",
-        "page": 730
+        "title": "A.2.1 Logic Gates",
+        "page": 624
       },
       {
         "level": 3,
-        "title": "A.2.3 Reduction Operators",
-        "page": 730
+        "title": "A.2.2 Other Functions",
+        "page": 624
       },
       {
-        "level": 3,
-        "title": "A.2.4 Conditional Assignment",
-        "page": 731
+        "level": 2,
+        "title": "A.3 Programmable Logic",
+        "page": 624
       },
       {
         "level": 3,
-        "title": "A.2.5 Internal Variables",
-        "page": 733
+        "title": "A.3.1 PROMs",
+        "page": 624
       },
       {
         "level": 3,
-        "title": "A.2.6 Precedence and Other Operators",
-        "page": 735
+        "title": "A.3.2 PLAs",
+        "page": 628
       },
       {
         "level": 3,
-        "title": "A.2.7 Numbers",
-        "page": 735
+        "title": "A.3.3 FPGAs",
+        "page": 629
       },
       {
-        "level": 3,
-        "title": "A.2.8 Zs and Xs",
-        "page": 736
+        "level": 2,
+        "title": "A.4 Application-Specific Integrated Circuits",
+        "page": 631
       },
       {
-        "level": 3,
-        "title": "A.2.9 Bit Swizzling",
-        "page": 738
+        "level": 2,
+        "title": "A.5 Data Sheets",
+        "page": 631
       },
       {
-        "level": 3,
-        "title": "A.2.10 Delays",
-        "page": 739
+        "level": 2,
+        "title": "A.6 Logic Families",
+        "page": 637
       },
       {
         "level": 2,
-        "title": "A.3 Structural Modeling",
-        "page": 740
+        "title": "A.7 Packaging and Assembly",
+        "page": 639
       },
       {
         "level": 2,
-        "title": "A.4 Sequential Logic",
-        "page": 744
+        "title": "A.8 Transmission Lines",
+        "page": 642
       },
       {
         "level": 3,
-        "title": "A.4.1 Registers",
-        "page": 744
+        "title": "A.8.1 Matched Termination",
+        "page": 644
       },
       {
         "level": 3,
-        "title": "A.4.2 Resettable Registers",
-        "page": 745
+        "title": "A.8.2 Open Termination",
+        "page": 646
       },
       {
         "level": 3,
-        "title": "A.4.3 Enabled Registers",
-        "page": 746
+        "title": "A.8.3 Short Termination",
+        "page": 647
       },
       {
         "level": 3,
-        "title": "A.4.4 Multiple Registers",
-        "page": 747
+        "title": "A.8.4 Mismatched Termination",
+        "page": 647
       },
       {
         "level": 3,
-        "title": "A.4.5 Latches",
-        "page": 748
+        "title": "A.8.5 When to Use Transmission Line Models",
+        "page": 650
       },
       {
         "level": 3,
-        "title": "A.4.6 Counters",
-        "page": 749
+        "title": "A.8.6 Proper Transmission Line Terminations",
+        "page": 650
       },
       {
         "level": 3,
-        "title": "A.4.7 Shift Registers",
-        "page": 751
-      },
-      {
-        "level": 2,
-        "title": "A.5 Combinational Logic with Always / Process Statements",
-        "page": 751
+        "title": "A.8.7 Derivation of Z0",
+        "page": 652
       },
       {
         "level": 3,
-        "title": "A.5.1 Case Statements",
-        "page": 753
+        "title": "A.8.8 Derivation of the Reflection Coefficient",
+        "page": 653
       },
       {
         "level": 3,
-        "title": "A.5.2 If Statements",
-        "page": 756
+        "title": "A.8.9 Putting It All Together",
+        "page": 654
       },
       {
-        "level": 3,
-        "title": "A.5.3 SystemVerilog Casez",
-        "page": 758
+        "level": 2,
+        "title": "A.9 Economics",
+        "page": 655
       },
       {
-        "level": 3,
-        "title": "A.5.4 Blocking and Nonblocking Assignments",
-        "page": 758
+        "level": 1,
+        "title": "Appendix B ARM Instructions",
+        "page": 659
       },
       {
         "level": 2,
-        "title": "A.6 Finite State Machines",
-        "page": 762
-      },
-      {
-        "level": 3,
-        "title": "A.6.1 FSM Example",
-        "page": 762
+        "title": "B.1 Data-Processing Instructions",
+        "page": 659
       },
       {
         "level": 3,
-        "title": "A.6.2 State Enumeration",
-        "page": 763
+        "title": "B.1.1 Multiply Instructions",
+        "page": 661
       },
       {
-        "level": 3,
-        "title": "A.6.3 FSM with Inputs",
-        "page": 765
+        "level": 2,
+        "title": "B.2 Memory Instructions",
+        "page": 662
       },
       {
         "level": 2,
-        "title": "A.7 Type Idiosyncracies",
-        "page": 767
+        "title": "B.3 Branch Instructions",
+        "page": 663
       },
       {
         "level": 2,
-        "title": "A.8 Parameterized Modules",
-        "page": 769
+        "title": "B.4 Miscellaneous Instructions",
+        "page": 663
       },
       {
         "level": 2,
-        "title": "A.9 Memory",
-        "page": 772
+        "title": "B.5 Condition Flags",
+        "page": 664
       },
       {
-        "level": 3,
-        "title": "A.9.1 RAM",
-        "page": 772
+        "level": 1,
+        "title": "Appendix C C Programming",
+        "page": 666
       },
       {
-        "level": 3,
-        "title": "A.9.2 Multiported Register Files",
-        "page": 774
+        "level": 2,
+        "title": "C.1 Introduction",
+        "page": 666
       },
       {
-        "level": 3,
-        "title": "A.9.3 ROM",
-        "page": 775
+        "level": 2,
+        "title": "C.2 Welcome to C",
+        "page": 668
       },
       {
-        "level": 2,
-        "title": "A.10 Testbenches",
-        "page": 776
+        "level": 3,
+        "title": "C.2.1 C Program Dissection",
+        "page": 668
       },
       {
-        "level": 2,
-        "title": "A.11 SystemVerilog Netlists",
-        "page": 781
+        "level": 3,
+        "title": "C.2.2 Running a C Program",
+        "page": 669
       },
       {
         "level": 2,
-        "title": "A.12 Example: MIPS Processor",
-        "page": 782
+        "title": "C.3 Compilation",
+        "page": 670
       },
       {
         "level": 3,
-        "title": "A.12.1 Testbench",
-        "page": 783
+        "title": "C.3.1 Comments",
+        "page": 670
       },
       {
         "level": 3,
-        "title": "A.12.2 SystemVerilog",
-        "page": 784
+        "title": "C.3.2 #define",
+        "page": 670
       },
       {
         "level": 3,
-        "title": "A.12.3 VHDL",
-        "page": 793
+        "title": "C.3.3 #include",
+        "page": 671
       },
       {
         "level": 2,
-        "title": "Exercises",
-        "page": 803
-      },
-      {
-        "level": 1,
-        "title": "References",
-        "page": 812
+        "title": "C.4 Variables",
+        "page": 672
       },
       {
-        "level": 1,
-        "title": "Index",
-        "page": 844
+        "level": 3,
+        "title": "C.4.1 Primitive Data Types",
+        "page": 673
       },
       {
-        "level": 2,
-        "title": "A",
-        "page": 844
+        "level": 3,
+        "title": "C.4.2 Global and Local Variables",
+        "page": 674
       },
       {
-        "level": 2,
-        "title": "B",
-        "page": 845
+        "level": 3,
+        "title": "C.4.3 Initializing Variables",
+        "page": 676
       },
       {
         "level": 2,
-        "title": "C",
-        "page": 845
+        "title": "C.5 Operators",
+        "page": 676
       },
       {
         "level": 2,
-        "title": "D",
-        "page": 848
+        "title": "C.6 Function Calls",
+        "page": 680
       },
       {
         "level": 2,
-        "title": "E",
-        "page": 850
+        "title": "C.7 Control-Flow Statements",
+        "page": 681
       },
       {
-        "level": 2,
-        "title": "F",
-        "page": 850
+        "level": 3,
+        "title": "C.7.1 Conditional Statements",
+        "page": 682
       },
       {
-        "level": 2,
-        "title": "G",
-        "page": 851
+        "level": 3,
+        "title": "C.7.2 Loops",
+        "page": 684
       },
       {
         "level": 2,
-        "title": "H",
-        "page": 852
+        "title": "C.8 More Data Types",
+        "page": 686
       },
       {
-        "level": 2,
-        "title": "I",
-        "page": 852
+        "level": 3,
+        "title": "C.8.1 Pointers",
+        "page": 686
       },
       {
-        "level": 2,
-        "title": "J",
-        "page": 853
+        "level": 3,
+        "title": "C.8.2 Arrays",
+        "page": 688
       },
       {
-        "level": 2,
-        "title": "K",
-        "page": 853
+        "level": 3,
+        "title": "C.8.3 Characters",
+        "page": 692
       },
       {
-        "level": 2,
-        "title": "L",
-        "page": 853
+        "level": 3,
+        "title": "C.8.4 Strings",
+        "page": 693
       },
       {
-        "level": 2,
-        "title": "M",
-        "page": 854
+        "level": 3,
+        "title": "C.8.5 Structures",
+        "page": 694
       },
       {
-        "level": 2,
-        "title": "N",
-        "page": 855
+        "level": 3,
+        "title": "C.8.6 typedef",
+        "page": 696
       },
       {
-        "level": 2,
-        "title": "O",
-        "page": 856
+        "level": 3,
+        "title": "C.8.7 Dynamic Memory Allocation",
+        "page": 697
       },
       {
-        "level": 2,
-        "title": "P",
-        "page": 857
+        "level": 3,
+        "title": "C.8.8 Linked Lists",
+        "page": 698
       },
       {
         "level": 2,
-        "title": "Q",
-        "page": 859
+        "title": "C.9 Standard Libraries",
+        "page": 700
       },
       {
-        "level": 2,
-        "title": "R",
-        "page": 859
+        "level": 3,
+        "title": "C.9.1 stdio",
+        "page": 700
       },
       {
-        "level": 2,
-        "title": "S",
-        "page": 860
+        "level": 3,
+        "title": "C.9.2 stdlib",
+        "page": 705
       },
       {
-        "level": 2,
-        "title": "T",
-        "page": 862
+        "level": 3,
+        "title": "C.9.3 math",
+        "page": 707
       },
       {
-        "level": 2,
-        "title": "U",
-        "page": 863
+        "level": 3,
+        "title": "C.9.4 string",
+        "page": 708
       },
       {
         "level": 2,
-        "title": "V",
-        "page": 863
+        "title": "C.10 Compiler and Command Line Options",
+        "page": 708
       },
       {
-        "level": 2,
-        "title": "W",
-        "page": 864
+        "level": 3,
+        "title": "C.10.1 Compiling Multiple C Source Files",
+        "page": 708
       },
       {
-        "level": 2,
-        "title": "X",
-        "page": 864
+        "level": 3,
+        "title": "C.10.2 Compiler Options",
+        "page": 708
       },
       {
-        "level": 2,
-        "title": "Y",
-        "page": 864
+        "level": 3,
+        "title": "C.10.3 Command Line Arguments",
+        "page": 709
       },
       {
         "level": 2,
-        "title": "Z",
-        "page": 864
+        "title": "C.11 Common Mistakes",
+        "page": 710
       },
       {
         "level": 1,
-        "title": "Credits",
-        "page": 865
+        "title": "Index",
+        "page": 716
       }
     ]
   }