# e-GPU and citing works — downloaded reference material

The e-GPU paper (EPFL, 2025) and the six works citing it (per Google Scholar),
with the open-source repos behind them. Downloaded 2026-08-10.

## papers/

| File | What it is |
|---|---|
| `e-GPU_2505.08421.pdf` | **Root paper**: e-GPU — configurable RISC-V GPU for TinyAI, integrates with X-HEEP as an APU; Tiny-OpenCL framework (arXiv 2505.08421) |
| `X-HEEP_2508.16959.pdf` | X-HEEP RISC-V TinyAI host platform, TSMC 65nm, 0.15mm², 29µW leakage (arXiv 2508.16959) |
| `FEMU_tinyai_emulation_2508.16981.pdf` | FEMU — FPGA emulation framework for prototyping X-HEEP-based heterogeneous systems (arXiv 2508.16981) |
| `VOLT_gpu_compiler_2511.13751.pdf` | VOLT — open-source GPU compiler (Vortex ecosystem) (arXiv 2511.13751) |
| `CGRA_polyhedral_kernels_2604.22297.pdf` | Polyhedral transformations for CGRA compilation (arXiv 2604.22297) |
| `Bandwidth_wall_data_streaming_2603.19057.pdf` | Data-streaming system–accelerator co-design for transformers, ACM TACO (arXiv 2603.19057) |
| `Sargantana_bitmanip_thesis_UPC.pdf` | UPC thesis: RISC-V bit-manipulation (B/Zvbb) extensions on the Sargantana core |

## repos/ (shallow clones)

| Repo | Size | Relation |
|---|---|---|
| `x-heep/` | 218M | The host platform e-GPU plugs into (github.com/x-heep/x-heep) — RTL, TinyAI accelerator interface (XAIF) |
| `x-heep-femu/` | 8.7M | FEMU paper's emulation framework (esl-epfl/x-heep-femu) |
| `sargantana/` | 45M | BSC's 1GHz+ RV64 in-order core from the thesis (bsc-loca/sargantana) |
| `OpenEdgeCGRA/` | 1.3M | EPFL's edge CGRA relevant to the CGRA compilation paper (esl-epfl/OpenEdgeCGRA) |

Notes:
- **The paper's official repo link is dead, but the RTL was found elsewhere.**
  Footnote 1's URL (github.com/esl-epfl/e-gpu) is a 404 (checked 2026-08-10).
  Archive forensics say it was likely NEVER public: Wayback Machine's earliest
  capture (2025-05-14, the day after the arXiv release) is already a 404, as
  are all later ones, and Software Heritage — which permanently archives
  public GitHub repos — has no record of the origin. No forks survive either.
  However, the first author's personal fork github.com/simone-machetti/vortex
  contains the e-GPU compute unit: it implements the paper's custom SLEEP_REQ
  instruction (hw/rtl/VX_decode.sv line ~391, wired through VX_pipeline.sv)
  and its last commit ("Fixed instr cache line size to 16B", 2025-04-26)
  matches the paper's exact I-cache config, two weeks before submission.
  Cloned at `repos/vortex-egpu-fork/` (trimmed Vortex, ~2MB source).
  Still not public: the X-HEEP integration glue and the full Tiny-OpenCL
  framework (the fork's runtime/ dir is Vortex's, not verified as Tiny-OpenCL).
- `repos/ai-core/` — the author's ACTIVE successor project (pushed 2026-08-07):
  "next-generation AI-Core architecture (clean redesign, in progress)" with a
  fully open EDA flow (Verilator sim, Yosys synthesis, OpenROAD P&R, OpenSTA
  timing/power). Worth watching.
- VOLT's code is already cloned at `../vortex/Volt/`.
- The bandwidth-wall TACO paper has no standalone public repo.