In many (older) serial communications protocols, each data byte is sent along with a start bit and a stop bit, to help the receiver delimit bytes from the stream of bits. One common scheme is to use one start bit (0), 8 data bits, and 1 stop bit (1). The line is also at logic 1 when nothing is being transmitted (idle). Design a finite state machine that will identify when bytes have been correctly received when given a stream of bits. It needs to identify the start bit, wait for all 8 data bits, then verify that the stop bit was correct. If the stop bit does not appear when expected, the FSM must wait until it finds a stop bit before attempting to receive the next byte. Include a active-high synchronous reset. Note that the serial protocol sends the least significant bit first.

module top_module (
	input clk,
	input in,
	input reset,
	output done
);
 // Define the states of the FSM
         parameter IDLE = 2'b00;
         parameter START = 2'b01;
         parameter DATA = 2'b10;
         parameter STOP = 2'b11;

         // Define the state register and next state logic
         reg [1:0] state, next_state;
         always @ (posedge clk) begin
             if (reset) begin
                 state <= IDLE;
             end else begin
                 state <= next_state;
             end
         end

         // Define the output register and output logic
         reg done;
         always @ (state) begin
             case (state)
                 IDLE: done = 0;
                 START: done = 0;
                 DATA: done = 0;
                 STOP: done = 1;
             endcase
         end

         // Define the next state logic
         always @ (state, in) begin
             case (state)
                 IDLE: begin
                     if (in == 0) begin
                         next_state = START;
                     end else begin
                         next_state = IDLE;
                     end
                 end
                 START: begin
                     if (in == 0) begin
                         next_state = DATA;
                     end else begin
                         next_state = IDLE;
                     end
                 end
                 DATA: begin
                     if (in == 1) begin
                         next_state = STOP;
                     end else begin
                         next_state = DATA;
                     end
                 end
                 STOP: begin
                     if (in == 1) begin
                         next_state = IDLE;
                     end else begin
                         next_state = STOP;
                     end
                 end
             endcase
         end

endmodule

24: error: 'done' has already been declared in this scope.
5:      : It was declared here as a net.


module top_module (
	input clk,
	input in,
	input reset,
	output done
);
 // Define the states of the FSM
         parameter IDLE = 2'b00;
         parameter START = 2'b01;
         parameter DATA = 2'b10;
         parameter STOP = 2'b11;

         // Define the state register and next state logic
         reg [1:0] state, next_state;
         always @(posedge clk) begin
             if (reset) begin
                 state <= IDLE;
             end else begin
                 state <= next_state;
             end
         end

         // Define the output register and output logic
         reg done;
         always @(posedge clk) begin
             if (reset) begin
                 done <= 0;
             end else begin
                 done <= (state == STOP);
             end
         end

         // Define the state transition logic
         always @(*) begin
             case (state)
                 IDLE: begin
                     if (in == 0) begin
                         next_state = START;
                     end else begin
                         next_state = IDLE;
                     end
                 end
                 START: begin
                     if (in == 0) begin
                         next_state = START;
                     end else begin
                         next_state = DATA;
                     end
                 end
                 DATA: begin
                     if (in == 0) begin
                         next_state = DATA;
                     end else begin
                         next_state = STOP;
                     end
                 end
                 STOP: begin
                     if (in == 1) begin
                         next_state = IDLE;
                     end else begin
                         next_state = STOP;
                     end
                 end
             endcase
         end

endmodule


In many (older) serial communications protocols, each data byte is sent along with a start bit and a stop bit, to help the receiver delimit bytes from the stream of bits. One common scheme is to use one start bit (0), 8 data bits, and 1 stop bit (1). The line is also at logic 1 when nothing is being transmitted (idle). Design a finite state machine that will identify when bytes have been correctly received when given a stream of bits. It needs to identify the start bit, wait for all 8 data bits, then verify that the stop bit was correct. The module will also output the correctly-received data byte. out_byte needs to be valid when done is 1, and is don't-care otherwise.If the stop bit does not appear when expected, the FSM must wait until it finds a stop bit before attempting to receive the next byte. Include a active-high synchronous reset. Note that the serial protocol sends the least significant bit first. It should assert done each time it finds a stop bit.

module top_module (
	input clk,
	input in,
	input reset,
	output [7:0] out_byte,
	output done
);
 // State Machine Code

         // States
         parameter IDLE = 2'b00;
         parameter START = 2'b01;
         parameter DATA = 2'b10;
         parameter STOP = 2'b11;

         // State Registers
         reg [1:0] state, next_state;

         // Output Registers
         reg [7:0] out_byte;
         reg done;

         // Bit Counter
         reg [3:0] bit_count;

         // Logic
         always @(posedge clk) begin

            if (reset) begin
               state <= IDLE;
               bit_count <= 4'b0;
               out_byte <= 8'b0;
               done <= 1'b0;
            end else begin
               state <= next_state;
               bit_count <= bit_count + 1;

               case (state)
                  IDLE: begin
                     if (in == 1'b0) begin
                        next_state <= START;
                     end else begin
                        next_state <= IDLE;
                     end
                  end

                  START: begin
                     if (in == 1'b1) begin
                        next_state <= STOP;
                        bit_count <= 4'b0;
                        out_byte <= 8'b0;
                     end else begin
                        next_state <= START;
                     end
                  end

                  DATA: begin
                     out_byte[7 - bit_count] <= in;
                     if (bit_count == 4'b0000) begin
                        next_state <= STOP;
                     end else begin
                        next_state <= DATA;
                     end
                  end

                  STOP: begin
                     if (in == 1'b1) begin
                        next_state <= IDLE;
                        done <= 1'b1;
                     end else begin
                        next_state <= STOP;
                     end
                  end
               endcase
            end
         end

endmodule

6:      : It was declared here as a net.
20: error: 'out_byte' has already been declared in this scope.
21: error: 'done' has already been declared in this scope.
5:      : It was declared here as a net.


module top_module (
	input clk,
	input in,
	input reset,
	output [7:0] out_byte,
	output done
);
 // Your code here
         // Define the states
         parameter IDLE = 2'b00;
         parameter START = 2'b01;
         parameter DATA = 2'b10;
         parameter STOP = 2'b11;

         // Define the state register and next state logic
         reg [1:0] state, next_state;
         always @ (posedge clk) begin
             if (reset) begin
                 state <= IDLE;
             end else begin
                 state <= next_state;
             end
         end

         // Define the FSM output and next state logic
         reg [7:0] byte_reg;
         reg [3:0] bit_count;
         reg stop_detected;
         always @ (*) begin
             case (state)
                 IDLE: begin
                     if (in == 0) begin
                         next_state = START;
                     end else begin
                         next_state = IDLE;
                     end
                 end
                 START: begin
                     if (in == 1) begin
                         next_state = START;
                     end else begin
                         next_state = DATA;
                     end
                 end
                 DATA: begin
                     if (bit_count == 7) begin
                         next_state = STOP;
                     end else begin
                         next_state = DATA;
                     end
                 end
                 STOP: begin
                     if (in == 1) begin
                         next_state = IDLE;
                         stop_detected = 1;
                     end else begin
                         next_state = STOP;
                     end
                 end
             endcase
         end

         // Define the output logic
         always @ (posedge clk) begin
             if (reset) begin
                 byte_reg <= 0;
                 bit_count <= 0;
                 stop_detected <= 0;
             end else begin
                 case (state)
                     IDLE: begin
                         byte_reg <= 0;
                         bit_count <= 0;
                         stop_detected <= 0;
                     end
                     START: begin
                         byte_reg <= {in, byte_reg[7:1]};
                         bit_count <= bit_count + 1;
                     end
                     DATA: begin
                         byte_reg <= {in, byte_reg[7:1]};
                         bit_count <= bit_count + 1;
                     end
                     STOP: begin
                         if (stop_detected) begin
                             out_byte <= byte_reg;
                             done <= 1;
                         end else begin
                             out_byte <= 0;
                             done <= 0;
                         end
                         byte_reg <= 0;
                         bit_count <= 0;
                         stop_detected <= 0;
                     end
                 endcase
             end
         end

         // Define the done signal
         always @ (posedge clk) begin
             if (reset) begin
                 done <= 0;
             end else begin
                 if (state == STOP) begin
                     done <= 1;
                 end else begin
                     done <= 0;
                 end
             end
         end

endmodule

86: error: 'out_byte' is not a valid l-value for a procedural assignment.
6:      : 'done' is declared here as a wire.
108: error: 'done' is not a valid l-value for a procedural assignment.
106: error: 'done' is not a valid l-value for a procedural assignment.
89: error: 'out_byte' is not a valid l-value for a procedural assignment.
90: error: 'done' is not a valid l-value for a procedural assignment.
87: error: 'done' is not a valid l-value for a procedural assignment.
5:      : 'out_byte' is declared here as a wire.
103: error: 'done' is not a valid l-value for a procedural assignment.


Build a combinational circuit with two inputs, a and b. There are 7 outputs, each with a logic gate driving it:
// (1) out_and: a and b
// (2) out_or: a or b
// (3) out_xor: a xor b
// (4) out_nand: a nand b
// (5) out_nor: a nor b
// (6) out_xnor: a xnor b
// (7) out_anotb: a and-not b

module top_module (
	input a,
	input b,
	output out_and,
	output out_or,
	output out_xor,
	output out_nand,
	output out_nor,
	output out_xnor,
	output out_anotb
);
always @(a or b) begin
	 out_and = a & b;
	 out_or = a | b;
	 out_xor = a ^ b;
	 out_nand = ~(a & b);
	 out_nor = ~(a | b);
	 out_xnor = ~(a ^ b);
	 out_anotb = a & ~b;
 end

endmodule

7:      : 'out_nand' is declared here as a wire.
9:      : 'out_xnor' is declared here as a wire.
15: error: 'out_xor' is not a valid l-value for a procedural assignment.
14: error: 'out_or' is not a valid l-value for a procedural assignment.
4:      : 'out_and' is declared here as a wire.
13: error: 'out_and' is not a valid l-value for a procedural assignment.
19: error: 'out_anotb' is not a valid l-value for a procedural assignment.
5:      : 'out_or' is declared here as a wire.
16: error: 'out_nand' is not a valid l-value for a procedural assignment.
18: error: 'out_xnor' is not a valid l-value for a procedural assignment.
17: error: 'out_nor' is not a valid l-value for a procedural assignment.
10:      : 'out_anotb' is declared here as a wire.
6:      : 'out_xor' is declared here as a wire.
8:      : 'out_nor' is declared here as a wire.


Build a combinational circuit with 100 inputs, in[99:0]. There are 3 outputs:
// (1) out_and: output of a 100-input AND gate.
// (2) out_or: output of a 100-input OR gate.
// (3) out_xor: output of a 100-input XOR gate.

module top_module (
	input [99:0] in,
	output out_and,
	output out_or,
	output out_xor
);
 wire [99:0] and_gate_input;
         wire [99:0] or_gate_input;
         wire [99:0] xor_gate_input;
         assign and_gate_input = in;
         assign or_gate_input = in;
         assign xor_gate_input = in;
         and_gate and_gate_inst (.in(and_gate_input), .out(out_and));
         or_gate or_gate_inst (.in(or_gate_input), .out(out_or));
         xor_gate xor_gate_inst (.in(xor_gate_input), .out(out_xor));
         assign out_and = ∈
         assign out_or = |in;
         assign out_xor = ^in;
         assign out_and = (in == 100'b1) ? 1'b1 : 1'b0;
         assign out_or = (in != 100'b0) ? 1'b1 : 1'b0;
         assign out_xor = (in % 2 == 1) ? 1'b1 : 1'b0;
endmodule

13: error: Unknown module type: and_gate
15: error: Unknown module type: xor_gate
14: error: Unknown module type: or_gate


Build a combinational circuit with four inputs, in[3:0]. There are 3 outputs:
// (1) out_and: output of a 4-input AND gate.
// (2) out_or: output of a 4-input OR gate.
// (3) out_xor: output of a 4-input XOR gate.

module top_module (
	input [3:0] in,
	output out_and,
	output out_or,
	output out_xor
);
always @(*) begin
	out_and = ∈
	out_or = |in;
	out_xor = ^in;
end

endmodule

10: error: 'out_xor' is not a valid l-value for a procedural assignment.
5:      : 'out_xor' is declared here as a wire.
7: warning: @* found no sensitivities so it will never trigger.
8: error: 'out_and' is not a valid l-value for a procedural assignment.
9: error: 'out_or' is not a valid l-value for a procedural assignment.
4:      : 'out_or' is declared here as a wire.
3:      : 'out_and' is declared here as a wire.


You are given a four-bit input vector in[3:0]. We want to know some relationships between each bit and its neighbour:
// (1) out_both: Each bit of this output vector should indicate whether both the corresponding input bit and its neighbour to the left (higher index) are '1'. For example, out_both[2] should indicate if in[2] and in[3] are both 1. Since in[3] has no neighbour to the left, the answer is obvious so we don't need to know out_both[3].
// (2) out_any: Each bit of this output vector should indicate whether any of the corresponding input bit and its neighbour to the right are '1'. For example, out_any[2] should indicate if either in[2] or in[1] are 1. Since in[0] has no neighbour to the right, the answer is obvious so we don't need to know out_any[0].
// (3) out_different: Each bit of this output vector should indicate whether the corresponding input bit is different from its neighbour to the left. For example, out_different[2] should indicate if in[2] is different from in[3]. For this part, treat the vector as wrapping around, so in[3]'s neighbour to the left is in[0].

module top_module (
	input [3:0] in,
	output [2:0] out_both,
	output [3:1] out_any,
	output [3:0] out_different
);
 // (1) out_both: Each bit of this output vector should indicate whether both the corresponding input bit and its neighbour to the left (higher index) are '1'.
         // Since in[3] has no neighbour to the left, the answer is obvious so we don't need to know out_both[3].
        // For other bits, we can calculate it using a bitwise AND operation.
        assign out_both[2] = in[2] & in[3];
        assign out_both[1] = in[1] & in[2];
        assign out_both[0] = in[0] & in[1];

         // (2) out_any: Each bit of this output vector should indicate whether any of the corresponding input bit and its neighbour to the right are '1'.
         // Since in[0] has no neighbour to the right, the answer is obvious so we don't need to know out_any[0].
        // For other bits, we can calculate it using a bitwise OR operation.
        assign out_any[3] = in[3] | in[2];
        assign out_any[2] = in[2] | in[1];
        assign out_any[1] = in[1] | in[0];
        assign out_any[0] = in[0] | in[3];

         // (3) out_different: Each bit of this output vector should indicate whether the corresponding input bit is different from its neighbour to the left.
         // For this part, treat the vector as wrapping around, so in[3]'s neighbour to the left is in[0].
        // We can calculate it using a bitwise XOR operation.
        assign out_different[3] = in[3] ^ in[0];
        assign out_different[2] = in[2] ^ in[3];
        assign out_different[1] = in[1] ^ in[2];
        assign out_different[0] = in[0] ^ in[1];

endmodule

20: sorry: part selects straddling the start of signal (out_any['sd0]) are not currently supported.


module top_module (
	input [3:0] in,
	output [2:0] out_both,
	output [3:1] out_any,
	output [3:0] out_different
);
 // (1) out_both
         assign out_both0 = in0 & in1;
         assign out_both1 = in1 & in2;
         assign out_both2 = in2 & in3;

         // (2) out_any
         assign out_any0 = in0 | in1;
         assign out_any1 = in1 | in2;
         assign out_any2 = in2 | in3;
         assign out_any3 = in3 | in0;

         // (3) out_different
         assign out_different0 = in0 ^ in1;
         assign out_different1 = in1 ^ in2;
         assign out_different2 = in2 ^ in3;
         assign out_different3 = in3 ^ in0;

endmodule

21: error: Unable to bind wire/reg/memory `in2' in `top_module'
9: error: Unable to bind wire/reg/memory `in2' in `top_module'
22: error: Unable to bind wire/reg/memory `in0' in `top_module'
14: warning: implicit definition of wire 'out_any1'.
8: error: Unable to elaborate r-value: (in0)&(in1)
19: warning: implicit definition of wire 'out_different0'.
14: error: Unable to bind wire/reg/memory `in1' in `top_module'
20: error: Unable to elaborate r-value: (in1)^(in2)
10: warning: implicit definition of wire 'out_both2'.
16: error: Unable to elaborate r-value: (in3)|(in0)
9: error: Unable to bind wire/reg/memory `in1' in `top_module'
9: error: Unable to elaborate r-value: (in1)&(in2)
13: error: Unable to bind wire/reg/memory `in0' in `top_module'
10: error: Unable to bind wire/reg/memory `in2' in `top_module'
14: error: Unable to elaborate r-value: (in1)|(in2)
20: error: Unable to bind wire/reg/memory `in1' in `top_module'
20: error: Unable to bind wire/reg/memory `in2' in `top_module'
22: warning: implicit definition of wire 'out_different3'.
21: error: Unable to bind wire/reg/memory `in3' in `top_module'
15: error: Unable to bind wire/reg/memory `in3' in `top_module'
8: error: Unable to bind wire/reg/memory `in1' in `top_module'
22: error: Unable to elaborate r-value: (in3)^(in0)
13: error: Unable to bind wire/reg/memory `in1' in `top_module'
15: error: Unable to elaborate r-value: (in2)|(in3)
21: error: Unable to elaborate r-value: (in2)^(in3)
14: error: Unable to bind wire/reg/memory `in2' in `top_module'
16: error: Unable to bind wire/reg/memory `in0' in `top_module'
15: warning: implicit definition of wire 'out_any2'.
19: error: Unable to elaborate r-value: (in0)^(in1)
19: error: Unable to bind wire/reg/memory `in1' in `top_module'
9: warning: implicit definition of wire 'out_both1'.
22: error: Unable to bind wire/reg/memory `in3' in `top_module'
19: error: Unable to bind wire/reg/memory `in0' in `top_module'
16: warning: implicit definition of wire 'out_any3'.
13: warning: implicit definition of wire 'out_any0'.
21: warning: implicit definition of wire 'out_different2'.
13: error: Unable to elaborate r-value: (in0)|(in1)
20: warning: implicit definition of wire 'out_different1'.
8: error: Unable to bind wire/reg/memory `in0' in `top_module'
15: error: Unable to bind wire/reg/memory `in2' in `top_module'
8: warning: implicit definition of wire 'out_both0'.
16: error: Unable to bind wire/reg/memory `in3' in `top_module'
10: error: Unable to elaborate r-value: (in2)&(in3)
10: error: Unable to bind wire/reg/memory `in3' in `top_module'


You are given a 100-bit input vector in[99:0]. We want to know some relationships between each bit and its neighbour:
// (1) out_both: Each bit of this output vector should indicate whether both the corresponding input bit and its neighbour to the left are '1'. For example, out_both[98] should indicate if in[98] and in[99] are both 1. Since in[99] has no neighbour to the left, the answer is obvious so we don't need to know out_both[99].
// (2) out_any: Each bit of this output vector should indicate whether any of the corresponding input bit and its neighbour to the right are '1'. For example, out_any[2] should indicate if either in[2] or in[1] are 1. Since in[0] has no neighbour to the right, the answer is obvious so we don't need to know out_any[0].
// (3) out_different: Each bit of this output vector should indicate whether the corresponding input bit is different from its neighbour to the left. For example, out_different[98] should indicate if in[98] is different from in[99]. For this part, treat the vector as wrapping around, so in[99]'s neighbour to the left is in[0].

module top_module (
	input [99:0] in,
	output [98:0] out_both,
	output [99:1] out_any,
	output [99:0] out_different
);
 assign out_both = {in[99:1] & in[0:98]};
         assign out_any = {in[99:1] | in[0:98]};
         assign out_different = {in[99:1] ^ in[0:98]};

endmodule

9: error: part select in[0:98] is out of order.
8: error: part select in[0:98] is out of order.
7: error: part select in[0:98] is out of order.


module top_module (
	input [99:0] in,
	output [98:0] out_both,
	output [99:1] out_any,
	output [99:0] out_different
);
 assign out_both = {in[99] & in[0:98], in[0:98] & in[1:99]};
         assign out_any = {in[0] | in[1:99], in[1:99] | in[0:98]};
         assign out_different = {in[99] ^ in[0], in[0] ^ in[1:99]};

endmodule

8: error: part select in[0:98] is out of order.
7: internal error: NetEConcat input width = 200, expecting 198
7: error: part select in[0:98] is out of order.
9: internal error: NetEConcat input width = 101, expecting 100
8: internal error: NetEConcat input width = 200, expecting 198
8: error: part select in[1:99] is out of order.
7: error: part select in[1:99] is out of order.
9: error: part select in[1:99] is out of order.


Build a gshare branch predictor with 7-bit pc and 7-bit global history, hashed (using xor) into a 7-bit index. This index accesses a 128-entry table of two-bit saturating counters. The branch predictor should contain a 7-bit global branch history register. The branch predictor has two sets of interfaces: One for doing predictions and one for doing training. The prediction interface is used in the processor's Fetch stage to ask the branch predictor for branch direction predictions for the instructions being fetched. Once these branches proceed down the pipeline and are executed, the true outcomes of the branches become known. The branch predictor is then trained using the actual branch direction outcomes.
// When a branch prediction is requested (predict_valid = 1) for a given pc, the branch predictor produces the predicted branch direction and state of the branch history register used to make the prediction. The branch history register is then updated (at the next positive clock edge) for the predicted branch.
// When training for a branch is requested (train_valid = 1), the branch predictor is told the pc and branch history register value for the branch that is being trained, as well as the actual branch outcome and whether the branch was a misprediction (needing a pipeline flush). Update the pattern history table (PHT) to train the branch predictor to predict this branch more accurately next time. In addition, if the branch being trained is mispredicted, also recover the branch history register to the state immediately after the mispredicting branch completes execution.
// If training for a misprediction and a prediction (for a different, younger instruction) occurs in the same cycle, both operations will want to modify the branch history register. When this happens, training takes precedence, because the branch being predicted will be discarded anyway. If training and prediction of the same PHT entry happen at the same time, the prediction sees the PHT state before training because training only modifies the PHT at the next positive clock edge. The following timing diagram shows the timing when training and predicting PHT entry 0 at the same time. The training request at cycle 4 changes the PHT entry state in cycle 5, but the prediction request in cycle 4 outputs the PHT state at cycle 4, without considering the effect of the training request in cycle 4. Reset is asynchronous active-high.

module top_module(
	input clk,
	input areset,

	input predict_valid,
	input [6:0] predict_pc,
	output predict_taken,
	output [6:0] predict_history,

	input train_valid,
	input train_taken,
	input train_mispredicted,
	input [6:0] train_history,
	input [6:0] train_pc
);
 // Global Branch History Register
         reg [6:0] branch_history_reg;
         reg [6:0] branch_history_reg_next;

         always @(posedge clk) begin
             if (areset) begin
                 branch_history_reg <= 7'b0;
                 branch_history_reg_next <= 7'b0;
             end else begin
                 branch_history_reg <= branch_history_reg_next;
                 branch_history_reg_next <= (branch_history_reg << 1) | train_taken;
             end
         end

         // Pattern History Table
         reg [1:0] PHT [0:127];
         reg [1:0] PHT_next [0:127];

         always @(posedge clk) begin
             if (areset) begin
                 PHT <= {128{2'b01}};
                 PHT_next <= {128{2'b01}};
             end else begin
                 PHT <= PHT_next;
                 PHT_next <= PHT;
             end
         end

         always @(*) begin
             if (train_valid) begin
                 PHT_next[train_pc][1] = train_taken;
             end else begin
                 PHT_next[predict_pc][1] = PHT[predict_pc][1];
             end
         end

         // Prediction Output
         assign predict_taken = PHT[predict_pc][1] ^ branch_history_reg[6];
         assign predict_history = branch_history_reg;

         // Training Input
         always @(posedge clk) begin
             if (train_valid && train_mispredicted) begin
                 branch_history_reg_next <= branch_history_reg;
             end else begin
                 branch_history_reg_next <= branch_history_reg;
             end
         end

endmodule

37: internal error: I don't know how to elaborate(ivl_type_t) this expression: {'sd128{2'd1}}
39: error: the type of the variable 'PHT_next' doesn't match the context type.
40:      : context type=11netuarray_t
36: internal error: I don't know how to elaborate(ivl_type_t) this expression: {'sd128{2'd1}}
40: error: the type of the variable 'PHT' doesn't match the context type.
39:      : context type=11netuarray_t
39:      : variable type=netvector_t:logic unsigned[1:0]
48: warning: @* is sensitive to all 128 words in array 'PHT'.
40:      : variable type=netvector_t:logic unsigned[1:0]


module top_module(
	input clk,
	input areset,

	input predict_valid,
	input [6:0] predict_pc,
	output predict_taken,
	output [6:0] predict_history,

	input train_valid,
	input train_taken,
	input train_mispredicted,
	input [6:0] train_history,
	input [6:0] train_pc
);
 parameter PHT_SIZE = 128;
         parameter PHT_ENTRY_SIZE = 2;
         parameter PHT_INDEX_SIZE = 7;
         parameter GHR_SIZE = 7;

         reg [PHT_ENTRY_SIZE-1:0] pht [PHT_SIZE-1:0];
         reg [GHR_SIZE-1:0] ghr;
         reg [PHT_INDEX_SIZE-1:0] pht_index;

         assign predict_taken = pht[pht_index][0];
         assign predict_history = ghr;

         always @(posedge clk) begin
            if (areset) begin
               ghr <= 0;
               pht <= 0;
            end else begin
               if (train_valid) begin
                  if (train_mispredicted) begin
                     ghr <= train_history;
                  end else begin
                     pht[pht_index] <= pht[pht_index] + train_taken;
                  end
               end
               if (predict_valid) begin
                  pht_index <= predict_pc ^ ghr;
                  ghr <= {ghr[GHR_SIZE-2:0], predict_taken};
               end
            end
         end

endmodule

31: error: The expression ''sd0' cannot be implicitly cast to the target type.


Create a half adder. A half adder adds two bits (with no carry-in) and produces a sum and carry-out.

module top_module (
	input a,
	input b,
	output sum,
	output cout
);
 always @ (a, b) begin
            sum = a ^ b;
            cout = a & b;
         end

endmodule

4:      : 'sum' is declared here as a wire.
5:      : 'cout' is declared here as a wire.
9: error: 'cout' is not a valid l-value for a procedural assignment.
8: error: 'sum' is not a valid l-value for a procedural assignment.


module top_module (
	input a,
	input b,
	output sum,
	output cout
);
 half_adder ha(a, b, sum, cout);

endmodule

7: error: Unknown module type: half_adder


Build a 32-bit global history shift register, including support for rolling back state in response to a pipeline flush caused by a branch misprediction. When a branch prediction is made (predict_valid = 1), shift in predict_taken from the LSB side to update the branch history for the predicted branch. (predict_history[0] is the direction of the youngest branch.) When a branch misprediction occurs (train_mispredicted = 1), load the branch history register with the history after the completion of the mispredicted branch. This is the history before the mispredicted branch (train_history) concatenated with the actual result of the branch (train_taken). If both a prediction and misprediction occur at the same time, the misprediction takes precedence, because the pipeline flush will also flush out the branch that is currently making a prediction. predict_history is the value of the branch history register. areset is a positive edge triggered asynchronous reset that resets the history counter to zero.

module top_module
(
    input clk,
    input areset,
    input predict_valid,
    input predict_taken,
    output logic [31:0] predict_history,

    input train_mispredicted,
    input train_taken,
    input [31:0] train_history
);
 logic [31:0] ghr_next;

        always_comb begin
            ghr_next = ghr;
            if (predict_valid) begin
                ghr_next[0] = predict_taken;
                ghr_next[1:31] = ghr[0:30];
            end else if (train_mispredicted) begin
                ghr_next = train_history | train_taken;
            end
        end

        always_ff @(posedge clk, posedge areset) begin
            if (areset) begin
                ghr <= 0;
            end else begin
                ghr <= ghr_next;
            end
        end

        assign predict_history = ghr;

endmodule

33: error: Unable to elaborate r-value: ghr
29: error: Could not find variable ``ghr'' in ``top_module''
33: error: Unable to bind wire/reg/memory `ghr' in `top_module'
27: error: Could not find variable ``ghr'' in ``top_module''
19: error: part select ghr_next[1:31] is reversed.
16: error: Unable to bind wire/reg/memory `ghr' in `top_module'
19: error: Unable to bind wire/reg/memory `ghr['sd0:'sd30]' in `top_module'


module top_module
(
    input clk,
    input areset,
    input predict_valid,
    input predict_taken,
    output logic [31:0] predict_history,

    input train_mispredicted,
    input train_taken,
    input [31:0] train_history
);

    always_comb begin
        if (train_mispredicted) begin
            predict_history = {train_history, train_taken};
        end
        else if (predict_valid) begin
            predict_history = {predict_history[30:0], predict_taken};
        end
        else begin
            predict_history = predict_history;
        end
    end

    always_ff @(posedge clk) begin
        if (areset) begin
            predict_history <= 0;
        end
        else begin
            predict_history <= predict_history;
        end
    end

endmodule

14: sorry: constant selects in always_* processes are not currently supported (all bits will be included).


Implement the circuit described by the Karnaugh map below.

//        ab
// cd   00 01 11 10
//  00 | 1 | 1 | 0 | 1 |
//  01 | 1 | 0 | 0 | 1 |
//  11 | 0 | 1 | 1 | 1 |
//  10 | 1 | 1 | 0 | 0 |

module top_module (
	input a,
	input b,
	input c,
	input d,
	output out
);
 // Declare variables
         wire w1, w2, w3, w4, w5, w6, w7, w8;

         // Implement Boolean functions
         assign w1 = ~(a & b & ~c & ~d);
         assign w2 = ~(a & ~b & ~c & ~d);
         assign w3 = ~(a & b & c & ~d);
         assign w4 = ~(a & ~b & c & ~d);
         assign w5 = ~(a & b & ~c & d);
         assign w6 = ~(a & ~b & c & d);
         assign w7 = ~(a & b & c & d);
         assign w8 = ~(a & ~b & ~c & d);

         // Implement Karnaugh map using case statement
         always @(*) begin
             case ({a, b, c, d})
                 4'b0000: out = 1;
                 4'b0001: out = 1;
                 4'b0010: out = 0;
                 4'b0100: out = 1;
                 4'b1000: out = 0;
                 4'b0011: out = 1;
                 4'b0110: out = 0;
                 4'b1001: out = 1;
                 4'b1011: out = 0;
                 4'b1100: out = 1;
                 4'b1101: out = 0;
                 default: out = 0;
             endcase
         end

endmodule

30: error: 'out' is not a valid l-value for a procedural assignment.
33: error: 'out' is not a valid l-value for a procedural assignment.
28: error: 'out' is not a valid l-value for a procedural assignment.
34: error: 'out' is not a valid l-value for a procedural assignment.
26: error: 'out' is not a valid l-value for a procedural assignment.
35: error: 'out' is not a valid l-value for a procedural assignment.
25: error: 'out' is not a valid l-value for a procedural assignment.
27: error: 'out' is not a valid l-value for a procedural assignment.
24: error: 'out' is not a valid l-value for a procedural assignment.
29: error: 'out' is not a valid l-value for a procedural assignment.
31: error: 'out' is not a valid l-value for a procedural assignment.
32: error: 'out' is not a valid l-value for a procedural assignment.
6:      : 'out' is declared here as a wire.


Implement the circuit described by the Karnaugh map below. d is don't-care, which means you may choose to output whatever value is convenient.

//        ab
// cd   01 00 10 11
//  00 | d | 0 | 1 | 1 |
//  01 | 0 | 0 | d | d |
//  11 | 0 | 1 | 1 | 1 |
//  10 | 0 | 1 | 1 | 1 |

module top_module (
	input a,
	input b,
	input c,
	input d,
	output reg out
);

	always @(posedge clk) begin
		out <= (a ^ b) ^ (c ^ d);
	end

endmodule

9: error: Failed to evaluate event expression 'posedge clk'.
9: error: Unable to bind wire/reg/memory `clk' in `top_module'


Implement the circuit described by the Karnaugh map below.

//        ab
// cd   00 01 11 10
//  00 | 0 | 1 | 0 | 1 |
//  01 | 1 | 0 | 1 | 0 |
//  11 | 0 | 1 | 0 | 1 |
//  10 | 1 | 0 | 1 | 0 |

11: error: 'd' has already been declared in this scope.
4:      : It was declared here as a net.
2:      : It was declared here as a net.
8: error: 'a' has already been declared in this scope.
5:      : It was declared here as a net.
9: error: 'b' has already been declared in this scope.
10: error: 'c' has already been declared in this scope.
3:      : It was declared here as a net.


The game Lemmings involves critters with fairly simple brains. So simple that we are going to model it using a finite state machine. In the Lemmings' 2D world, Lemmings can be in one of two states: walking left (walk_left is 1) or walking right (walk_right is 1). It will switch directions if it hits an obstacle. In particular, if a Lemming is bumped on the left (by receiving a 1 on bump_left), it will walk right. If it's bumped on the right (by receiving a 1 on bump_right), it will walk left. If it's bumped on both sides at the same time, it will still switch directions. Implement a Moore state machine with two states, two inputs, and one output (internal to the module) that models this behaviour. areset is positive edge triggered asynchronous reseting the Lemming machine to walk left.

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	output walk_left,
	output walk_right
);
 parameter IDLE = 2'b00;
         parameter LEFT = 2'b01;
         parameter RIGHT = 2'b10;
         parameter BOTH = 2'b11;

         reg [1:0] state, next_state;
         reg walk_left, walk_right;

         always @(posedge clk or posedge areset) begin
            if (areset) begin
               state <= IDLE;
               walk_left <= 0;
               walk_right <= 0;
            end else begin
               state <= next_state;
               walk_left <= (state == LEFT) ? 1 : 0;
               walk_right <= (state == RIGHT) ? 1 : 0;
            end
         end

         always @* begin
            case (state)
               IDLE: begin
                  if (bump_left) begin
                     next_state = LEFT;
                  end else if (bump_right) begin
                     next_state = RIGHT;
                  end else begin
                     next_state = IDLE;
                  end
               end
               LEFT: begin
                  if (bump_right) begin
                     next_state = RIGHT;
                  end else if (bump_left && bump_right) begin
                     next_state = BOTH;
                  end else begin
                     next_state = LEFT;
                  end
               end
               RIGHT: begin
                  if (bump_left) begin
                     next_state = LEFT;
                  end else if (bump_left && bump_right) begin
                     next_state = BOTH;
                  end else begin
                     next_state = RIGHT;
                  end
               end
               BOTH: begin
                  if (bump_left && bump_right) begin
                     next_state = BOTH;
                  end else if (bump_left) begin
                     next_state = LEFT;
                  end else if (bump_right) begin
                     next_state = RIGHT;
                  end
               end
            endcase
         end

endmodule

7:      : It was declared here as a net.
15: error: 'walk_right' has already been declared in this scope.
15: error: 'walk_left' has already been declared in this scope.
6:      : It was declared here as a net.


module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	output walk_left,
	output walk_right
);
 parameter IDLE = 2'b00;
         parameter WALK_LEFT = 2'b01;
         parameter WALK_RIGHT = 2'b10;
         parameter IDLE_RIGHT = 2'b11;

         reg [1:0] state, next_state;
         reg walk_left, walk_right;

         always @(posedge clk or posedge areset) begin
             if (areset) begin
                 state <= IDLE;
                 walk_left <= 1'b0;
                 walk_right <= 1'b0;
             end else begin
                 state <= next_state;
                 walk_left <= (state == WALK_LEFT);
                 walk_right <= (state == WALK_RIGHT);
             end
         end

         always @(*) begin
             case (state)
                 IDLE: begin
                     if (bump_left) begin
                         next_state = WALK_RIGHT;
                     end else if (bump_right) begin
                         next_state = WALK_LEFT;
                     end else begin
                         next_state = IDLE;
                     end
                 end
                 WALK_LEFT: begin
                     if (bump_left) begin
                         next_state = WALK_RIGHT;
                     end else if (bump_right) begin
                         next_state = IDLE_RIGHT;
                     end else begin
                         next_state = WALK_LEFT;
                     end
                 end
                 WALK_RIGHT: begin
                     if (bump_left) begin
                         next_state = IDLE_RIGHT;
                     end else if (bump_right) begin
                         next_state = WALK_LEFT;
                     end else begin
                         next_state = WALK_RIGHT;
                     end
                 end
                 IDLE_RIGHT: begin
                     if (bump_left) begin
                         next_state = WALK_LEFT;
                     end else if (bump_right) begin
                         next_state = WALK_RIGHT;
                     end else begin
                         next_state = IDLE_RIGHT;
                     end
                 end
             endcase
         end

endmodule


The game Lemmings involves critters with fairly simple brains. So simple that we are going to model it using a finite state machine. In the Lemmings' 2D world, Lemmings can be in one of two states: walking left (walk_left is 1) or walking right (walk_right is 1). It will switch directions if it hits an obstacle. In particular, if a Lemming is bumped on the left (by receiving a 1 on bump_left), it will walk right. If it's bumped on the right (by receiving a 1 on bump_right), it will walk left. If it's bumped on both sides at the same time, it will still switch directions.
// In addition to walking left and right and changing direction when bumped, when ground=0, the Lemming will fall and say "aaah!". When the ground reappears (ground=1), the Lemming will resume walking in the same direction as before the fall. Being bumped while falling does not affect the walking direction, and being bumped in the same cycle as ground disappears (but not yet falling), or when the ground reappears while still falling, also does not affect the walking direction.
// Implement a Moore state machine that models this behaviour. areset is positive edge triggered asynchronous reseting the Lemming machine to walk left.

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	output walk_left,
	output walk_right,
	output aaah
);
 // Implementing the Lemming Moore state machine using Verilog
         wire [1:0] state, next_state;

         // State definitions
         parameter WALK_LEFT = 2'b00, WALK_RIGHT = 2'b01, FALL_LEFT = 2'b10, FALL_RIGHT = 2'b11;

         // Default values
         assign walk_left = 1'b0;
         assign walk_right = 1'b0;
         assign aaah = 1'b0;

         // State transition logic
         always @ (posedge clk or posedge areset) begin
             if (areset) begin
                 state <= WALK_LEFT;  // Reset to walk left
             end else begin
                 state <= next_state;
             end
         end

         // Next state logic
         always @ (state, bump_left, bump_right, ground) begin
             case (state)
                 WALK_LEFT: begin
                     if (bump_right) begin
                         next_state = WALK_RIGHT;  // Walk right if bumped
                     end else if (ground == 0) begin
                         next_state = FALL_RIGHT;  // Fall if ground is not available
                     end else begin
                         next_state = WALK_LEFT;  // Continue walking to the left
                     end
                 end
                WALK_RIGHT: begin
                     if (bump_left) begin
                         next_state = WALK_LEFT;  // Walk left if bumped
                     end else if (ground == 0) begin
                         next_state = FALL_LEFT;  // Fall if ground is not available
                     end else begin
                         next_state = WALK_RIGHT;  // Continue walking to the right
                     end
                 end
                 FALL_LEFT: begin
                     if (bump_right) begin
                         next_state = WALK_RIGHT;  // Continue walking right when falling
                     end else if (ground) begin  // Resume walking left when ground reappears
                         next_state = WALK_LEFT;
                     end else begin
                         next_state = FALL_LEFT;  // Continue falling
                     end
                 end
                 FALL_RIGHT: begin
                     if (bump_left) begin
                         next_state = WALK_LEFT;  // Continue walking left when falling
                     end else if (ground) begin  // Resume walking right when ground reappears
                         next_state = WALK_RIGHT;
                     end else begin
                         next_state = FALL_RIGHT;  // Continue falling
                     end
                 end
                 default: begin
                     next_state = WALK_LEFT;  // Default to walking left
                 end
             endcase
         end

         // Output logic
         always @ (state) begin
             case (state)
                 WALK_LEFT, FALL_LEFT: begin
                     walk_left = 1'b1;
                     walk_right = 1'b0;
                     aaah = ground;
                 end
                 WALK_RIGHT, FALL_RIGHT: begin
                     walk_left = 1'b0;
                     walk_right = 1'b1;
                     aaah = ground;
                 end
                 default: begin
                     walk_left = 1'b0;
                     walk_right = 1'b0;
                     aaah = 1'b0;
                 end
             endcase
         end

endmodule

71: error: 'next_state' is not a valid l-value for a procedural assignment.
65: error: 'next_state' is not a valid l-value for a procedural assignment.
36: error: 'next_state' is not a valid l-value for a procedural assignment.
86: error: 'walk_right' is not a valid l-value for a procedural assignment.
9:      : 'aaah' is declared here as a wire.
12:      : 'next_state' is declared here as a wire.
27: error: 'state' is not a valid l-value for a procedural assignment.
82: error: 'aaah' is not a valid l-value for a procedural assignment.
87: error: 'aaah' is not a valid l-value for a procedural assignment.
38: error: 'next_state' is not a valid l-value for a procedural assignment.
80: error: 'walk_left' is not a valid l-value for a procedural assignment.
8:      : 'walk_right' is declared here as a wire.
56: error: 'next_state' is not a valid l-value for a procedural assignment.
90: error: 'walk_left' is not a valid l-value for a procedural assignment.
85: error: 'walk_left' is not a valid l-value for a procedural assignment.
81: error: 'walk_right' is not a valid l-value for a procedural assignment.
47: error: 'next_state' is not a valid l-value for a procedural assignment.
12:      : 'state' is declared here as a wire.
91: error: 'walk_right' is not a valid l-value for a procedural assignment.
49: error: 'next_state' is not a valid l-value for a procedural assignment.
67: error: 'next_state' is not a valid l-value for a procedural assignment.
63: error: 'next_state' is not a valid l-value for a procedural assignment.
92: error: 'aaah' is not a valid l-value for a procedural assignment.
25: error: 'state' is not a valid l-value for a procedural assignment.
58: error: 'next_state' is not a valid l-value for a procedural assignment.
7:      : 'walk_left' is declared here as a wire.
40: error: 'next_state' is not a valid l-value for a procedural assignment.
45: error: 'next_state' is not a valid l-value for a procedural assignment.
54: error: 'next_state' is not a valid l-value for a procedural assignment.


module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	output walk_left,
	output walk_right,
	output aaah
);
 parameter IDLE = 2'b00, WALK_LEFT = 2'b01, WALK_RIGHT = 2'b10;
         reg [1:0] state, next_state;
         reg walk_left_reg, walk_right_reg;
         reg aaah_reg;

         always @(posedge clk or posedge areset) begin
            if (areset) begin
               state <= IDLE;
               walk_left_reg <= 1'b0;
               walk_right_reg <= 1'b0;
               aaah_reg <= 1'b0;
            end else begin
               state <= next_state;
               walk_left_reg <= walk_left;
               walk_right_reg <= walk_right;
               aaah_reg <= aaah;
            end
         end

         always @(*) begin
            next_state = state;
            walk_left = walk_left_reg;
            walk_right = walk_right_reg;
            aaah = aaah_reg;
            case (state)
               IDLE: begin
                  if (bump_left) begin
                     next_state = WALK_RIGHT;
                     walk_left = 1'b0;
                     walk_right = 1'b1;
                     aaah = 1'b0;
                  end else if (bump_right) begin
                     next_state = WALK_LEFT;
                     walk_left = 1'b1;
                     walk_right = 1'b0;
                     aaah = 1'b0;
                  end else if (ground == 1'b0) begin
                     next_state = IDLE;
                     walk_left = 1'b0;
                     walk_right = 1'b0;
                     aaah = 1'b1;
                  end else begin
                     next_state = IDLE;
                     walk_left = 1'b0;
                     walk_right = 1'b0;
                     aaah = 1'b0;
                  end
               end
               WALK_LEFT: begin
                  if (bump_left) begin
                     next_state = WALK_RIGHT;
                     walk_left = 1'b0;
                     walk_right = 1'b1;
                     aaah = 1'b0;
                  end else if (bump_right) begin
                     next_state = WALK_LEFT;
                     walk_left = 1'b1;
                     walk_right = 1'b0;
                     aaah = 1'b0;
                  end else if (ground == 1'b0) begin
                     next_state = IDLE;
                     walk_left = 1'b0;
                     walk_right = 1'b0;
                     aaah = 1'b1;
                  end else begin
                     next_state = WALK_LEFT;
                     walk_left = 1'b1;
                     walk_right = 1'b0;
                     aaah = 1'b0;
                  end
               end
               WALK_RIGHT: begin
                  if (bump_left) begin
                     next_state = WALK_RIGHT;
                     walk_left = 1'b0;
                     walk_right = 1'b1;
                     aaah = 1'b0;
                  end else if (bump_right) begin
                     next_state = WALK_LEFT;
                     walk_left = 1'b1;
                     walk_right = 1'b0;
                     aaah = 1'b0;
                  end else if (ground == 1'b0) begin
                     next_state = IDLE;
                     walk_left = 1'b0;
                     walk_right = 1'b0;
                     aaah = 1'b1;
                  end else begin
                     next_state = WALK_RIGHT;
                     walk_left = 1'b0;
                     walk_right = 1'b1;
                     aaah = 1'b0;
                  end
               end
            endcase
         end

endmodule

44: error: 'walk_left' is not a valid l-value for a procedural assignment.
51: error: 'aaah' is not a valid l-value for a procedural assignment.
86: error: 'walk_right' is not a valid l-value for a procedural assignment.
9:      : 'aaah' is declared here as a wire.
55: error: 'walk_right' is not a valid l-value for a procedural assignment.
77: error: 'walk_left' is not a valid l-value for a procedural assignment.
102: error: 'aaah' is not a valid l-value for a procedural assignment.
49: error: 'walk_left' is not a valid l-value for a procedural assignment.
87: error: 'aaah' is not a valid l-value for a procedural assignment.
64: error: 'aaah' is not a valid l-value for a procedural assignment.
40: error: 'walk_right' is not a valid l-value for a procedural assignment.
8:      : 'walk_right' is declared here as a wire.
41: error: 'aaah' is not a valid l-value for a procedural assignment.
74: error: 'aaah' is not a valid l-value for a procedural assignment.
62: error: 'walk_left' is not a valid l-value for a procedural assignment.
100: error: 'walk_left' is not a valid l-value for a procedural assignment.
95: error: 'walk_left' is not a valid l-value for a procedural assignment.
45: error: 'walk_right' is not a valid l-value for a procedural assignment.
46: error: 'aaah' is not a valid l-value for a procedural assignment.
63: error: 'walk_right' is not a valid l-value for a procedural assignment.
85: error: 'walk_left' is not a valid l-value for a procedural assignment.
90: error: 'walk_left' is not a valid l-value for a procedural assignment.
79: error: 'aaah' is not a valid l-value for a procedural assignment.
56: error: 'aaah' is not a valid l-value for a procedural assignment.
50: error: 'walk_right' is not a valid l-value for a procedural assignment.
91: error: 'walk_right' is not a valid l-value for a procedural assignment.
78: error: 'walk_right' is not a valid l-value for a procedural assignment.
68: error: 'walk_right' is not a valid l-value for a procedural assignment.
92: error: 'aaah' is not a valid l-value for a procedural assignment.
54: error: 'walk_left' is not a valid l-value for a procedural assignment.
67: error: 'walk_left' is not a valid l-value for a procedural assignment.
73: error: 'walk_right' is not a valid l-value for a procedural assignment.
72: error: 'walk_left' is not a valid l-value for a procedural assignment.
96: error: 'walk_right' is not a valid l-value for a procedural assignment.
7:      : 'walk_left' is declared here as a wire.
97: error: 'aaah' is not a valid l-value for a procedural assignment.
101: error: 'walk_right' is not a valid l-value for a procedural assignment.
34: error: 'aaah' is not a valid l-value for a procedural assignment.
32: error: 'walk_left' is not a valid l-value for a procedural assignment.
69: error: 'aaah' is not a valid l-value for a procedural assignment.
39: error: 'walk_left' is not a valid l-value for a procedural assignment.
33: error: 'walk_right' is not a valid l-value for a procedural assignment.


The game Lemmings involves critters with fairly simple brains. So simple that we are going to model it using a finite state machine. In the Lemmings' 2D world, Lemmings can be in one of two states: walking left (walk_left is 1) or walking right (walk_right is 1). It will switch directions if it hits an obstacle. In particular, if a Lemming is bumped on the left (by receiving a 1 on bump_left), it will walk right. If it's bumped on the right (by receiving a 1 on bump_right), it will walk left. If it's bumped on both sides at the same time, it will still switch directions.
// In addition to walking left and right and changing direction when bumped, when ground=0, the Lemming will fall and say "aaah!". When the ground reappears (ground=1), the Lemming will resume walking in the same direction as before the fall. Being bumped while falling does not affect the walking direction, and being bumped in the same cycle as ground disappears (but not yet falling), or when the ground reappears while still falling, also does not affect the walking direction.
// In addition to walking and falling, Lemmings can sometimes be told to do useful things, like dig (it starts digging when dig=1). A Lemming can dig if it is currently walking on ground (ground=1 and not falling), and will continue digging until it reaches the other side (ground=0). At that point, since there is no ground, it will fall (aaah!), then continue walking in its original direction once it hits ground again. As with falling, being bumped while digging has no effect, and being told to dig when falling or when there is no ground is ignored. (In other words, a walking Lemming can fall, dig, or switch directions. If more than one of these conditions are satisfied, fall has higher precedence than dig, which has higher precedence than switching directions.)
// Implement a Moore state machine that models this behaviour. areset is positive edge triggered asynchronous reseting the Lemming machine to walk left.

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	input dig,
	output walk_left,
	output walk_right,
	output aaah,
	output digging
);
 parameter IDLE = 2'b00;
         parameter WALK_LEFT = 2'b01;
         parameter WALK_RIGHT = 2'b10;
         parameter FALL = 2'b11;

         reg [1:0] state, next_state;
         reg walk_left, walk_right, aaah, digging;

         always @(posedge clk or posedge areset) begin
            if (areset) begin
               state <= IDLE;
               walk_left <= 0;
               walk_right <= 0;
               aaah <= 0;
               digging <= 0;
            end else begin
               state <= next_state;
               walk_left <= (state == WALK_LEFT);
               walk_right <= (state == WALK_RIGHT);
               aaah <= (state == FALL);
               digging <= (state == WALK_LEFT || state == WALK_RIGHT);
            end
         end

         always @(*) begin
            case (state)
               IDLE: begin
                  if (dig) begin
                     next_state = WALK_LEFT;
                  end else begin
                     next_state = IDLE;
                  end
               end
               WALK_LEFT: begin
                  if (bump_left) begin
                     next_state = WALK_RIGHT;
                  end else if (bump_right) begin
                     next_state = WALK_LEFT;
                  end else if (dig) begin
                     next_state = WALK_LEFT;
                  end else if (ground == 0) begin
                     next_state = FALL;
                  end else begin
                     next_state = WALK_LEFT;
                  end
               end
               WALK_RIGHT: begin
                  if (bump_right) begin
                     next_state = WALK_LEFT;
                  end else if (bump_left) begin
                     next_state = WALK_RIGHT;
                  end else if (dig) begin
                     next_state = WALK_RIGHT;
                  end else if (ground == 0) begin
                     next_state = FALL;
                  end else begin
                     next_state = WALK_RIGHT;
                  end
               end
               FALL: begin
                  if (ground == 1) begin
                     next_state = WALK_LEFT;
                  end else if (dig) begin
                     next_state = WALK_RIGHT;
                  end else begin
                     next_state = FALL;
                  end
               end
               default: begin
                  next_state = IDLE;
               end
            endcase
         end

endmodule

19: error: 'walk_left' has already been declared in this scope.
11:      : It was declared here as a net.
8:      : It was declared here as a net.
9:      : It was declared here as a net.
19: error: 'aaah' has already been declared in this scope.
19: error: 'walk_right' has already been declared in this scope.
19: error: 'digging' has already been declared in this scope.
10:      : It was declared here as a net.


module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	input dig,
	output walk_left,
	output walk_right,
	output aaah,
	output digging
);
 parameter IDLE = 2'b00;
         parameter WALK_LEFT = 2'b01;
         parameter WALK_RIGHT = 2'b10;
         parameter FALL = 2'b11;

         reg [1:0] state, next_state;
         reg walk_left, walk_right, aaah, digging;

         always @(posedge clk or posedge areset) begin
            if (areset) begin
               state <= IDLE;
               walk_left <= 0;
               walk_right <= 0;
               aaah <= 0;
               digging <= 0;
            end else begin
               state <= next_state;
               walk_left <= (state == WALK_LEFT);
               walk_right <= (state == WALK_RIGHT);
               aaah <= (state == FALL);
               digging <= (state == WALK_LEFT || state == WALK_RIGHT);
            end
         end

         always @(*) begin
            case (state)
               IDLE: begin
                  if (dig) begin
                     next_state = WALK_LEFT;
                  end else begin
                     next_state = WALK_RIGHT;
                  end
               end
               WALK_LEFT: begin
                  if (bump_left) begin
                     next_state = WALK_RIGHT;
                  end else if (bump_right) begin
                     next_state = WALK_LEFT;
                  end else if (ground == 0) begin
                     next_state = FALL;
                  end else if (dig) begin
                     next_state = WALK_LEFT;
                  end else begin
                     next_state = WALK_LEFT;
                  end
               end
               WALK_RIGHT: begin
                  if (bump_right) begin
                     next_state = WALK_LEFT;
                  end else if (bump_left) begin
                     next_state = WALK_RIGHT;
                  end else if (ground == 0) begin
                     next_state = FALL;
                  end else if (dig) begin
                     next_state = WALK_RIGHT;
                  end else begin
                     next_state = WALK_RIGHT;
                  end
               end
               FALL: begin
                  if (ground) begin
                     next_state = WALK_LEFT;
                  end else begin
                     next_state = FALL;
                  end
               end
            endcase
         end

endmodule


The game Lemmings involves critters with fairly simple brains. So simple that we are going to model it using a finite state machine. In the Lemmings' 2D world, Lemmings can be in one of two states: walking left (walk_left is 1) or walking right (walk_right is 1). It will switch directions if it hits an obstacle. In particular, if a Lemming is bumped on the left (by receiving a 1 on bump_left), it will walk right. If it's bumped on the right (by receiving a 1 on bump_right), it will walk left. If it's bumped on both sides at the same time, it will still switch directions.
// In addition to walking left and right and changing direction when bumped, when ground=0, the Lemming will fall and say ""aaah!"". When the ground reappears (ground=1), the Lemming will resume walking in the same direction as before the fall. Being bumped while falling does not affect the walking direction, and being bumped in the same cycle as ground disappears (but not yet falling), or when the ground reappears while still falling, also does not affect the walking direction.
// In addition to walking and falling, Lemmings can sometimes be told to do useful things, like dig (it starts digging when dig=1). A Lemming can dig if it is currently walking on ground (ground=1 and not falling), and will continue digging until it reaches the other side (ground=0). At that point, since there is no ground, it will fall (aaah!), then continue walking in its original direction once it hits ground again. As with falling, being bumped while digging has no effect, and being told to dig when falling or when there is no ground is ignored. (In other words, a walking Lemming can fall, dig, or switch directions. If more than one of these conditions are satisfied, fall has higher precedence than dig, which has higher precedence than switching directions.)
// Although Lemmings can walk, fall, and dig, Lemmings aren't invulnerable. If a Lemming falls for too long then hits the ground, it can splatter. In particular, if a Lemming falls for more than 20 clock cycles then hits the ground, it will splatter and cease walking, falling, or digging (all 4 outputs become 0), forever (Or until the FSM gets reset). There is no upper limit on how far a Lemming can fall before hitting the ground. Lemmings only splatter when hitting the ground; they do not splatter in mid-air.
// Implement a Moore state machine that models this behaviour. areset is positive edge triggered asynchronous reseting the Lemming machine to walk left.

module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	input dig,
	output walk_left,
	output walk_right,
	output aaah,
	output digging
);
 // State definitions
         parameter WALK_LEFT = 2'b00;
         parameter WALK_RIGHT = 2'b01;
         parameter FALL = 2'b10;
         parameter SPLAT = 2'b11;

         // State variables
         reg [1:0] state;
         reg [2:0] fall_counter;
         reg [1:0] dig_counter;
         reg splat;

         // Output variables
         reg walk_left_out;
         reg walk_right_out;
         reg aaah_out;
         reg digging_out;

         // Reset logic
         always @(posedge clk or posedge areset) begin
             if (areset) begin
                 state <= WALK_LEFT;
                 fall_counter <= 0;
                 dig_counter <= 0;
                 splat <= 0;
             end else begin
                 // State transitions
                 case (state)
                     WALK_LEFT: begin
                         if (bump_left || bump_right) begin
                             state <= WALK_RIGHT;
                         end else if (!ground) begin
                             state <= FALL;
                         end else if (dig) begin
                             state <= DIGGING;
                         end
                     end
                     WALK_RIGHT: begin
                         if (bump_left || bump_right) begin
                             state <= WALK_LEFT;
                         end else if (!ground) begin
                             state <= FALL;
                         end else if (dig) begin
                             state <= DIGGING;
                         end
                     end
                     FALL: begin
                         if (ground) begin
                             state <= WALK_LEFT;
                         end else if (bump_left || bump_right) begin
                             state <= SPLAT;
                         end else if (fall_counter == 20) begin
                             state <= SPLAT;
                         end else begin
                             fall_counter <= fall_counter + 1;
                         end
                     end
                     DIGGING: begin
                         if (!ground) begin
                             state <= FALL;
                         end else if (dig_counter == 2) begin
                             state <= WALK_LEFT;
                         end else if (dig_counter == 1) begin
                             state <= WALK_RIGHT;
                         end else begin
                             dig_counter <= dig_counter + 1;
                         end
                     end
                     SPLAT: begin
                         if (!bump_left && !bump_right && !ground) begin
                             state <= SPLAT;
                         end else begin
                             splat <= 1;
                             state <= SPLAT;
                         end
                     end
                 endcase
             end
         end

         // Output logic
         always @(state) begin
             case (state)
                 WALK_LEFT: begin
                     walk_left_out = 1;
                     walk_right_out = 0;
                     aaah_out = 0;
                     digging_out = 0;
                 end
                 WALK_RIGHT: begin
                     walk_left_out = 0;
                     walk_right_out = 1;
                     aaah_out = 0;
                     digging_out = 0;
                 end
                 FALL: begin
                     walk_left_out = 0;
                     walk_right_out = 0;
                     aaah_out = 1;
                     digging_out = 0;
                 end
                 DIGGING: begin
                     walk_left_out = 0;
                     walk_right_out = 0;
                     aaah_out = 0;
                     digging_out = 1;
                 end
                 SPLAT: begin
                     walk_left_out = 0;
                     walk_right_out = 0;
                     aaah_out = 0;
                     digging_out = 0;
                 end
             endcase
         end

         // Output assignments
         assign walk_left = walk_left_out;
         assign walk_right = walk_right_out;
         assign aaah = aaah_out;
         assign digging = digging_out;

endmodule

114: error: Unable to bind wire/reg/memory `DIGGING' in `top_module'
47: error: Unable to bind wire/reg/memory `DIGGING' in `top_module'
70: error: Unable to bind wire/reg/memory `DIGGING' in `top_module'
56: error: Unable to bind wire/reg/memory `DIGGING' in `top_module'


module top_module (
	input clk,
	input areset,
	input bump_left,
	input bump_right,
	input ground,
	input dig,
	output walk_left,
	output walk_right,
	output aaah,
	output digging
);
 parameter IDLE = 2'b00;
         parameter WALKING_LEFT = 2'b01;
         parameter FALLING = 2'b10;
         parameter DIGGING = 2'b11;

         reg [1:0] state, next_state;
         reg walk_left, walk_right, aaah, digging;

         always @(posedge clk) begin
            if (areset) begin
               state <= IDLE;
               walk_left <= 0;
               walk_right <= 0;
               aaah <= 0;
               digging <= 0;
            end else begin
               state <= next_state;
            end
         end

         always @* begin
            next_state = state;
            walk_left = 0;
            walk_right = 0;
            aaah = 0;
            digging = 0;

            case (state)
               IDLE: begin
                  if (bump_left && !bump_right) begin
                     next_state = WALKING_LEFT;
                     walk_left = 1;
                  end else if (bump_right && !bump_left) begin
                     next_state = WALKING_LEFT;
                     walk_right = 1;
                  end else if (bump_left && bump_right) begin
                     next_state = WALKING_LEFT;
                     walk_left = 1;
                     walk_right = 1;
                  end else if (dig) begin
                     next_state = DIGGING;
                     digging = 1;
                  end else if (bump_left || bump_right) begin
                     next_state = FALLING;
                     aaah = 1;
                  end
               end

               WALKING_LEFT: begin
                  if (bump_left && !bump_right) begin
                     walk_left = 1;
                  end else if (bump_right && !bump_left) begin
                     walk_right = 1;
                     next_state = WALKING_LEFT;
                  end else if (bump_left && bump_right) begin
                     walk_left = 1;
                     walk_right = 1;
                     next_state = WALKING_LEFT;
                  end else if (dig) begin
                     next_state = DIGGING;
                     digging = 1;
                  end else if (bump_left || bump_right) begin
                     next_state = FALLING;
                     aaah = 1;
                  end
               end

               FALLING: begin
                  if (ground) begin
                     next_state = IDLE;
                     aaah = 0;
                  end
               end

               DIGGING: begin
                  if (!dig) begin
                     next_state = IDLE;
                     digging = 0;
                  end else if (ground) begin
                     next_state = DIGGING;
                     digging = 1;
                  end else if (bump_left || bump_right) begin
                     next_state = FALLING;
                     aaah = 1;
                  end
               end
            endcase
         end
endmodule


A linear feedback shift register is a shift register usually with a few XOR gates to produce the next state of the shift register. A Galois LFSR is one particular arrangement where bit positions with a "tap" are XORed with the output bit to produce each bit's next value, while bit positions without a tap shift. Build a 32-bit Galois LFSR with taps at bit positions 32, 22, 2, and 1. Reset should be active high synchronous, and should reset the output q to 32'h1.

module top_module(
	input clk,
	input reset,
	output reg [31:0] q);
 parameter [31:0] TAP_POS = 32'h1 << 32 | 32'h1 << 22 | 32'h1 << 2 | 32'h1;

         always @(posedge clk) begin
            if (reset) begin
               q <= 32'h1;
            end
            else begin
               q <= (q[TAP_POS] ^ q[TAP_POS - 1] ^ q[TAP_POS - 2] ^ q[TAP_POS - 3]) << 1;
            end
         end
      endmodule

12: warning: Constant bit select [4194308] is after vector q[31:0].
12: warning: Constant bit select [4194306] is after vector q[31:0].
12: warning: Constant bit select [4194307] is after vector q[31:0].
12:        : Replacing select with a constant 1'bx.
12: warning: Constant bit select [4194309] is after vector q[31:0].


module top_module(
	input clk,
	input reset,
	output reg [31:0] q);

        reg [31:0] lfsr;
        reg [4:0] tap;
        integer i;

        always @(posedge clk) begin
            if (reset) begin
                lfsr <= 32'h1;
            end else begin
                tap <= {lfsr[32], lfsr[22], lfsr[2], lfsr[1]};
                lfsr <= {lfsr[31:1], tap[0] ^ tap[1] ^ tap[2] ^ tap[3]};
            end
        end

        assign q = lfsr;

endmodule

14:        : Replacing select with a constant 1'bx.
14: warning: Constant bit select [32] is after vector lfsr[31:0].


A linear feedback shift register is a shift register usually with a few XOR gates to produce the next state of the shift register. A Galois LFSR is one particular arrangement where bit positions with a "tap" are XORed with the output bit to produce its next value, while bit positions without a tap shift. If the taps positions are carefully chosen, the LFSR can be made to be "maximum-length". A maximum-length LFSR of n bits cycles through 2**n-1 states before repeating (the all-zero state is never reached). Build a 5-bit maximal-length Galois LFSR with taps at bit positions 5 and 3. The active-high synchronous reset should reset the LFSR output to 1.

module top_module(
	input clk,
	input reset,
	output reg [4:0] q);
 reg r1;
             reg r2;

             initial begin
                 r1 = 1;
                 r2 = r1 ^ (q[5] ^ q[3]);
             end

             always @(posedge clk) begin
                 if (reset) begin
                     q <= 5'b00001;
                 end else begin
                     q <= r2;
                     r1 <= r2;
                     r2 <= r1 ^ (q[5] ^ q[3]);
                 end
             end
         endmodule

19:        : Replacing select with a constant 1'bx.
10:        : Replacing select with a constant 1'bx.
19: warning: Constant bit select [5] is after vector q[4:0].
10: warning: Constant bit select [5] is after vector q[4:0].


module top_module(
	input clk,
	input reset,
	output reg [4:0] q);
 wire t1, t2, t3, t4, t5;
         wire fb1, fb2, fb3, fb4, fb5;
        reg [4:0] lfsr;
        initial begin
            lfsr = 5'b10000;
        end
        assign fb1 = (lfsr[0] ^ lfsr[1]);
        assign fb2 = (lfsr[0] ^ lfsr[2]);
        assign fb3 = (lfsr[0] ^ lfsr[4]);
        assign fb4 = (lfsr[1] ^ lfsr[2]);
        assign fb5 = (lfsr[2] ^ lfsr[4]);
        assign t1 = lfsr[5];
        assign t2 = fb1;
        assign t3 = fb2;
        assign t4 = fb3;
        assign t5 = fb4;
        always @(posedge clk) begin
           if (reset) begin
              lfsr <= 5'b10000;
           end else begin
              lfsr[4:0] <= {fb5,t1,t2,t3,t4};
           end
        end
        assign q = lfsr;
endmodule

16:        : Replacing select with a constant 1'bx.
16: warning: Constant bit select [5] is after vector lfsr[4:0].


Consider the function f shown in the Karnaugh map below. d is don't-care, which means you may choose to output whatever value is convenient. Implement this function.
//        x[1]x[2]
// x[3]x[4]   00 01 11 10
//  00 | d | 0 | d | d |
//  01 | 0 | d | 1 | 0 |
//  11 | 1 | 1 | d | d |
//  10 | 1 | 1 | 0 | d |

module top_module (
	input [4:1] x,
	output logic f
);

6: error: Unable to bind wire/reg/memory `x1' in `top_module'
6: error: Unable to bind wire/reg/memory `x2' in `top_module'
6: error: Unable to bind wire/reg/memory `x3' in `top_module'
6: error: Unable to bind wire/reg/memory `x4' in `top_module'
6: error: Unable to elaborate this case expression.
6: error: Concatenation/replication may not have zero width in this context.


5: sorry: constant selects in always_* processes are not currently supported (all bits will be included).


Implement a D flip flop, positive edge triggered, with an asynchronous reset "ar".

module top_module (
	input clk,
	input d,
	input ar,
	output logic q
);
 parameter WIDTH = 1;

	dffl_ar #(.WIDTH(WIDTH)) dut (.d(d), .clk(clk), .ar(ar), .q(q));

	endmodule


Implement a simple D flip flop with active high synchronous reset (reset output to 0).

module top_module (
	input clk,
	input d,
	input r,
	output logic q
);
 assign q = (r) ? 1'b0 : q;

	always @(posedge clk)
		q <= d;

endmodule

10: error: Cannot perform procedural assignment to variable 'q' because it is also continuously assigned.


Implement in Verilog the following circuit: A D flip-flop takes as input the output of a two-input XOR. The flip-flop is positive edge triggered by clk, but there is no reset. The XOR takes as input 'in' along with the output 'out' of the flip-flop.

module top_module (
	input clk,
	input in,
	output logic out
);
	logic xor_out;
	logic flipflop_out;

	xor_gate xor_gate_instance (
		.a(in),
		.b(flipflop_out),
		.out(xor_out)
	);

	d_flip_flop d_flip_flop_instance (
		.clk(clk),
		.d(xor_out),
		.q(flipflop_out)
	);

	assign out = flipflop_out;

endmodule

9: error: Unknown module type: xor_gate
15: error: Unknown module type: d_flip_flop


Implement the following circuit in Verilog. Two inputs (in1 and in2) go to an AND gate, but the in2 input to the AND gate has a bubble. The output of the AND gate is connected to 'out'.

module top_module (
	input in1,
	input in2,
	output logic out
);
 // Module definition with input and output ports.

	wire and_out;

	and and_gate (
		.a(in1),
		.b(in2),
		.z(and_out)
	);

	assign out = and_out;

endmodule

10: error: Gates do not have port names.


module top_module (
	input in1,
	input in2,
	output logic out
);
 logic and_out;

             and_gate and_inst (
                 .in1(in1),
                 .in2(in2),
                 .out(and_out)
             );

             assign out = and_out;

endmodule


Implement in Verilog the following circuit: A two-input XNOR (connected to 'in1' and 'in2) has an output connected to the input of a two-input XOR. The second input of the XOR is 'in3.' The output of the XOR is 'out'.

module top_module (
	input in1,
	input in2,
	input in3,
	output logic out
);
 //  Name  Output  Other arguments
         xnor0 (xnor_out, in1, in2);  // Instantiate xnor gate with output xnor_out and inputs in1, in2.
         xor0 (out, xnor_out, in3);   // Instantiate xor gate with output out and inputs xnor_out, in3.

endmodule

9: error: Unknown module type: xor0
8: error: Unknown module type: xnor0
8: warning: implicit definition of wire 'xnor_out'.


module top_module (
	input in1,
	input in2,
	input in3,
	output logic out
);
 //  Name  Output  Other arguments
  xnor2 xnor_inst (out, in1, in2);
  xor2  xor_inst (out, out, in3);

endmodule

8: error: Unknown module type: xnor2
9: error: Unknown module type: xor2


Build a circuit with no inputs and one output. That output should always drive 0 (or logic low).

module top_module(
	output out);
 // Module supplies
         supply1 VPWR;
         supply0 VGND;
         supply1 VPB ;
         supply0 VNB ;

         // Instantiate the module
         always @(*) begin
             out <= 1'b0;
         end

endmodule

11: error: 'out' is not a valid l-value for a procedural assignment.
2:      : 'out' is declared here as a wire.


module top_module(
	output out);
reg out_reg;
 assign out = out_reg;
 always @(*) begin
	out_reg = 1'b0;
 end

endmodule

5: warning: @* found no sensitivities so it will never trigger.


Implement a 4-bit adder with full adders. The output sum should include the overflow bit.

module top_module (
	input [3:0] x,
	input [3:0] y,
	output [4:0] sum
);
 // Define carry signals for each bit
         wire c1, c2, c3;

         // Define full adder modules
         full_adder fa0(.a(x[0]), .b(y[0]), .c(1'b0), .sum(sum[0]), .carry(c1));
         full_adder fa1(.a(x[1]), .b(y[1]), .c(c1), .sum(sum[1]), .carry(c2));
         full_adder fa2(.a(x[2]), .b(y[2]), .c(c2), .sum(sum[2]), .carry(c3));
         full_adder fa3(.a(x[3]), .b(y[3]), .c(c3), .sum(sum[3]), .carry(sum[4]));

endmodule

13: error: Unknown module type: full_adder
12: error: Unknown module type: full_adder
11: error: Unknown module type: full_adder
10: error: Unknown module type: full_adder


module top_module (
	input [3:0] x,
	input [3:0] y,
	output [4:0] sum
);
 full_adder fa0(x[0], y[0], 1'b0, sum[0], c1);
         full_adder fa1(x[1], y[1], c1, sum[1], c2);
         full_adder fa2(x[2], y[2], c2, sum[2], c3);
         full_adder fa3(x[3], y[3], c3, sum[3], sum[4]);

endmodule

6: error: Unknown module type: full_adder
7: warning: implicit definition of wire 'c2'.
8: warning: implicit definition of wire 'c3'.
8: error: Unknown module type: full_adder
9: error: Unknown module type: full_adder
6: warning: implicit definition of wire 'c1'.
7: error: Unknown module type: full_adder


Implement a shift register with four D flops. Reset is active-low synchronous resettable.

module top_module (
	input clk,
	input resetn,
	input in,
	output out
);
 parameter N = 4; // number of D flip-flops
         reg [N-1:0] dff_out; // output of D flip-flops
         wire [N-2:0] shift_in; // input for shift register
         assign shift_in[0] = in; // input is shifted into output
         assign shift_in[1:N-1] = dff_out[0:N-2]; // shift register is shifted right
         assign out = dff_out[N-1]; // output is last D flip-flop output
         always @(posedge clk or negedge resetn) begin
             if (!resetn) begin
                 dff_out <= {N{1'b0}}; // clear to zero
             end else begin
                 dff_out <= {shift_in, in}; // shift input into output
             end
         end

endmodule

11: error: part select dff_out[0:2] is out of order.
11:      : Did you mean shift_in[3:1]?
11: warning: Part select shift_in[1:3] is out of range.
11: error: Part select shift_in[1:3] indices reversed.


module top_module (
	input clk,
	input resetn,
	input in,
	output out
);
 parameter WIDTH = 4;
         wire [WIDTH-1:0] data_in;
         wire [WIDTH-1:0] sr;
         assign data_in = {in,sr[WIDTH-2:0]};
         assign out = sr[WIDTH-1];

         reg_mult_dffe #(WIDTH) dff_4 (
                 .clk(clk),
                 .clrn(resetn),
                 .d(data_in),
                 .q(sr)
         );

endmodule

13: error: Unknown module type: reg_mult_dffe


Consider the state machine shown below:

// A (0) --0--> B
// A (0) --1--> A
// B (0) --0--> C
// B (0) --1--> D
// C (0) --0--> E
// C (0) --1--> D
// D (0) --0--> F
// D (0) --1--> A
// E (1) --0--> E
// E (1) --1--> D
// F (1) --0--> C
// F (1) --1--> D

// Implement this state machine in Verilog.

module top_module (
	input clk,
	input reset,
	input w,
	output z
);
 parameter A = 2'b00;
             parameter B = 2'b01;
             parameter C = 2'b10;
             parameter D = 2'b11;
             parameter E = 2'b100;
             parameter F = 2'b101;

             reg [2:0] state;
             reg [2:0] next_state;

             always @(posedge clk) begin
                 if (reset) begin
                     state <= A;
                     next_state <= B;
                 end else begin
                     state <= next_state;
                 end
             end

             always @(*) begin
                 case (state)
                     A: begin
                         if (w) begin
                             next_state = B;
                         end else begin
                             next_state = C;
                         end
                     end
                     B: begin
                         if (w) begin
                             next_state = D;
                         end else begin
                             next_state = E;
                         end
                     end
                     C: begin
                         if (w) begin
                             next_state = D;
                         end else begin
                             next_state = E;
                         end
                     end
                     D: begin
                         if (w) begin
                             next_state = F;
                         end else begin
                             next_state = E;
                         end
                     end
                     E: begin
                         if (w) begin
                             next_state = D;
                         end else begin
                             next_state = E;
                         end
                     end
                     F: begin
                         if (w) begin
                             next_state = F;
                         end else begin
                             next_state = E;
                         end
                     end
                 endcase
             end

             assign z = (state == F && w);

endmodule

12: warning: Numeric constant truncated to 2 bits.
11: warning: Numeric constant truncated to 2 bits.
11: warning: Extra digits given for sized binary constant.
12: warning: Extra digits given for sized binary constant.


module top_module (
	input clk,
	input reset,
	input w,
	output z
);
 parameter A = 2'b00;
         parameter B = 2'b01;
         parameter C = 2'b10;
         parameter D = 2'b11;
         parameter E = 2'b100;
         parameter F = 2'b101;

         reg [2:0] state, next_state;

         always @(posedge clk, posedge reset) begin
            if (reset) begin
               state <= A;
            end else begin
               state <= next_state;
            end
         end

         always @(*) begin
            case (state)
               A: begin
                  if (w) begin
                     next_state = A;
                  end else begin
                     next_state = B;
                  end
               end
               B: begin
                  if (w) begin
                     next_state = D;
                  end else begin
                     next_state = C;
                  end
               end
               C: begin
                  if (w) begin
                     next_state = D;
                  end else begin
                     next_state = E;
                  end
               end
               D: begin
                  if (w) begin
                     next_state = A;
                  end else begin
                     next_state = F;
                  end
               end
               E: begin
                  if (w) begin
                     next_state = D;
                  end else begin
                     next_state = E;
                  end
               end
               F: begin
                  if (w) begin
                     next_state = D;
                  end else begin
                     next_state = F;
                  end
               end
            endcase
         end

         assign z = (state == E);

endmodule


Consider the state machine shown below:

// A (0) --0--> B
// A (0) --1--> A
// B (0) --0--> C
// B (0) --1--> D
// C (0) --0--> E
// C (0) --1--> D
// D (0) --0--> F
// D (0) --1--> A
// E (1) --0--> E
// E (1) --1--> D
// F (1) --0--> C
// F (1) --1--> D

// Assume that you want to Implement the FSM using three flip-flops and state codes y[3:1] = 000, 001, ..., 101 for states A, B, ..., F, respectively. Implement just the next-state logic for y[2] in Verilog. The output Y2 is y[2].

module top_module(
	input [3:1] y,
	input w,
	output reg Y2);
 reg [1:0] next_state;
         always @ (y, w) begin
             case ({y[3:1], w})
                 {0,0} : next_state = 2'b00;
                 {0,1} : next_state = 2'b01;
                 {1,0} : next_state = 2'b10;
                 {1,1} : next_state = 2'b11;
                 {2,0} : next_state = 2'b00;
                 {2,1} : next_state = 2'b01;
                 {3,0} : next_state = 2'b01;
                 {3,1} : next_state = 2'b00;
                 {4,0} : next_state = 2'b10;
                 {4,1} : next_state = 2'b11;
                 {5,0} : next_state = 2'b11;
                 {5,1} : next_state = 2'b00;
                 {6,0} : next_state = 2'b11;
                 {6,1} : next_state = 2'b10;
                 {7,0} : next_state = 2'b10;
                 {7,1} : next_state = 2'b11;
             endcase
         end
         assign Y2 = next_state;
       endmodule

9: error: Concatenation operand "'sd1" has indefinite width.
8: error: Concatenation operand "'sd0" has indefinite width.
15: error: Concatenation operand "'sd1" has indefinite width.
23: error: Concatenation operand "'sd7" has indefinite width.
22: error: Concatenation operand "'sd0" has indefinite width.
20: error: Concatenation operand "'sd6" has indefinite width.
19: error: Concatenation operand "'sd1" has indefinite width.
12: error: Concatenation operand "'sd2" has indefinite width.
22: error: Concatenation operand "'sd7" has indefinite width.
16: error: Concatenation operand "'sd0" has indefinite width.
13: error: Concatenation operand "'sd1" has indefinite width.
19: error: Concatenation operand "'sd5" has indefinite width.
20: error: Concatenation operand "'sd0" has indefinite width.
17: error: Concatenation operand "'sd1" has indefinite width.
14: error: Concatenation operand "'sd0" has indefinite width.
10: error: Concatenation operand "'sd1" has indefinite width.
14: error: Concatenation operand "'sd3" has indefinite width.
23: error: Concatenation operand "'sd1" has indefinite width.
18: error: Concatenation operand "'sd5" has indefinite width.
9: error: Concatenation operand "'sd0" has indefinite width.
11: error: Concatenation operand "'sd1" has indefinite width.
13: error: Concatenation operand "'sd2" has indefinite width.
17: error: Concatenation operand "'sd4" has indefinite width.
16: error: Concatenation operand "'sd4" has indefinite width.
21: error: Concatenation operand "'sd1" has indefinite width.
12: error: Concatenation operand "'sd0" has indefinite width.
15: error: Concatenation operand "'sd3" has indefinite width.
21: error: Concatenation operand "'sd6" has indefinite width.
18: error: Concatenation operand "'sd0" has indefinite width.
10: error: Concatenation operand "'sd0" has indefinite width.


module top_module(
	input [3:1] y,
	input w,
	output reg Y2);

        always @ (y[2:0]) begin
        case (y[2:0])
            3'b000: if (w) Y2=0; else Y2=1;      //A --> A
            3'b001: if (w) Y2=0; else Y2=1;      //B --> D
            3'b010: if (w) Y2=0; else Y2=1;      //C --> E
            3'b011: if (w) Y2=1; else Y2=0;      //D --> A
            3'b100: if (w) Y2=1; else Y2=0;      //E --> D
	endcase
	end
        endmodule

7: warning: Part select [2:0] is selecting before the vector y[3:1].
6:        : Replacing the out of bound bits with 'bx.
6: warning: Part select [2:0] is selecting before the vector y[3:1].
7:        : Replacing the out of bound bits with 'bx.


Consider the state machine shown below:

// A (0) --0--> B
// A (0) --1--> A
// B (0) --0--> C
// B (0) --1--> D
// C (0) --0--> E
// C (0) --1--> D
// D (0) --0--> F
// D (0) --1--> A
// E (1) --0--> E
// E (1) --1--> D
// F (1) --0--> C
// F (1) --1--> D

// Resets into state A. For this part, assume that a one-hot code is used with the state assignment y[6:1] = 000001, 000010, 000100, 001000, 010000, 100000 for states A, B,..., F, respectively.

// Write Verilog for the next-state signals Y2 and Y4 corresponding to signal y[2] and y[4]. Derive the logic equations by inspection assuming a one-hot encoding.

module top_module (
	input [6:1] y,
	input w,
	output Y2,
	output Y4
);
 assign Y2 = (y == 2'b000010) ? 1'b1 : 1'b0; // Next state of Y2 is B if current state is A and w=0
         assign Y4 = (y == 2'b000100) ? 1'b1 : // Next state of Y4 is C if current state is B and w=0
                   (y == 2'b000001) ? 1'b1 : // Next state of Y4 is D if current state is A and w=1
                   (y == 2'b001000) ? 1'b1 : // Next state of Y4 is E if current state is C and w=1
                   (y == 2'b010000) ? 1'b1 : // Next state of Y4 is D if current state is F and w=1
                   1'b0; // Default value is 0

endmodule

8: warning: Extra digits given for sized binary constant.
10: warning: Extra digits given for sized binary constant.
10: warning: Numeric constant truncated to 2 bits.
11: warning: Extra digits given for sized binary constant.
9: warning: Extra digits given for sized binary constant.
11: warning: Numeric constant truncated to 2 bits.
8: warning: Numeric constant truncated to 2 bits.
7: warning: Extra digits given for sized binary constant.


21: warning: Constant bit select [0] is before vector y[6:1].
21:        : Replacing select with a constant 1'bx.


Create a circuit that has two 2-bit inputs A[1:0] and B[1:0], and produces an output z. The value of z should be 1 if A = B, otherwise z should be 0.

module top_module(
	input [1:0] A,
	input [1:0] B,
	output z);

	wire [1:0] and_result;
	wire or_result;

	// Compare each bit of A and B using AND gates
	and_gate and0(and_result[0], A[0], B[0]);
	and_gate and1(and_result[1], A[1], B[1]);

	// Combine the results of the AND gates using an OR gate
	or_gate or0(or_result, and_result[0], and_result[1]);

	// Output the result of the OR gate
	assign z = or_result;

endmodule

14: error: Unknown module type: or_gate
11: error: Unknown module type: and_gate
10: error: Unknown module type: and_gate


module top_module(
	input [1:0] A,
	input [1:0] B,
	output z);
always @(*) begin
                if(A == B)
                    z = 1'b1;
                else
                    z = 1'b0;
            end

            endmodule

9: error: 'z' is not a valid l-value for a procedural assignment.
4:      : 'z' is declared here as a wire.
7: error: 'z' is not a valid l-value for a procedural assignment.


Consider this Verilog module "full_module":

// module full_module (
//     input [2:0] r,
//     input L,
//     input clk,
//     output reg [2:0] q
);

// always @(posedge clk) begin
//     if (L) begin
//         q <= r;
//     end else begin
//         q <= {q[1] ^ q[2], q[0], q[2]};
//     end
// end

// endmodule

// You want to create a hierarchical Verilog design where a flipflop and 2-1 multiplexer are in a submodule, and that submodule is instantiated three times in this code. Create the submodule called "top_module".

module top_module(
	input clk,
	input L,
	input q_in,
	input r_in,
	output reg Q);
 always @(posedge clk) begin
            if (L) begin
                Q <= r_in;
            end else begin
                Q <= {q_in[1], q_in[0], q_in[2], q_in[3]};
            end
        end

endmodule

11: error: can not select part of scalar: q_in
11: error: Concatenation/replication may not have zero width in this context.


module top_module(
	input clk,
	input L,
	input q_in,
	input r_in,
	output reg Q);
 parameter n=3;
         parameter m=4;

	// Define flipflop
	reg [0:0] ff_out;
	always @(posedge clk) begin
	   if (L) begin
	       ff_out <= q_in;
	   end else begin
	       ff_out <= {ff_out[0] ^ ff_out[1], ff_out[0], ff_out[1]};
	   end
	end

	// Define 2-1 multiplexer
	wire [0:0] mux_out;
	assign mux_out = (L) ? r_in : ff_out;

	// Instantiate full_module 3 times
	reg [2:0] q1, q2, q3;
	full_module module1(.r(r_in), .L(L), .clk(clk), .q(q1));
	full_module module2(.r(q1), .L(L), .clk(clk), .q(q2));
	full_module module3(.r(q2), .L(L), .clk(clk), .q(q3));

	// Output final value
	always @(posedge clk) begin
	   Q <= q3[2];
	end

endmodule

28: error: Unknown module type: full_module
26: error: Unknown module type: full_module
27: error: Unknown module type: full_module