Create 16 D flip-flops. It's sometimes useful to only modify parts of a group of flip-flops. The byte-enable inputs control whether each byte of the 16 registers should be written to on that cycle. byteena[1] controls the upper byte d[15:8], while byteena[0] controls the lower byte d[7:0]. resetn is a synchronous, active-low reset. All DFFs should be triggered by the positive edge of clk.

module top_module(
	input clk,
	input resetn,
	input [1:0] byteena,
	input [15:0] d,
	output reg [15:0] q);
 reg [15:0] ff [0:15];

         always @(posedge clk) begin
            if (!resetn) begin
               for (i=0; i<16; i=i+1) begin
                  ff[i] <= 16'b0;
               end
            end else begin
               for (i=0; i<16; i=i+1) begin
                  if (byteena[1]) begin
                     if (i<8) begin
                        ff[i] <= d[15:8];
                     end else begin
                        ff[i] <= ff[i];
                     end
                  end else begin
                     if (i<8) begin
                        ff[i] <= d[7:0];
                     end else begin
                        ff[i] <= ff[i];
                     end
                  end
               end
            end
         end

         always @(posedge clk) begin
            if (!resetn) begin
               q <= 16'b0;
            end else begin
               q <= {ff[15], ff[14], ff[13], ff[12], ff[11], ff[10], ff[9], ff[8], ff[7], ff[6], ff[5], ff[4], ff[3], ff[2], ff[1], ff[0]};
            end
         end

      endmodule

11: register ``i'' unknown in top_module.
15: register ``i'' unknown in top_module.


Create 8 D flip-flops with active high asynchronous reset. The output should be reset to 0. All DFFs should be triggered by the positive edge of clk.

module top_module(
	input clk,
	input [7:0] d,
	input areset,
	output reg [7:0] q);
 reg [7:0] ff [0:7];

         always @(posedge clk or negedge areset) begin
           if(areset) begin
             q <= 8'b0;
             ff <= 8'b0;
           end else begin
             q <= ff[0];
             ff[0] <= d;
             ff[1] <= ff[0];
             ff[2] <= ff[1];
             ff[3] <= ff[2];
             ff[4] <= ff[3];
             ff[5] <= ff[4];
             ff[6] <= ff[5];
             ff[7] <= ff[6];
           end
         end
       endmodule

11: error: The expression '8'd0' cannot be implicitly cast to the target type.


In this question, you will design a circuit for an 8x1 memory, where writing to the memory is accomplished by shifting-in bits, and reading is "random access", as in a typical RAM. You will then use the circuit to realize a 3-input logic function. First, create an 8-bit shift register with 8 D-type flip-flops. Label the flip-flop outputs from Q[0]...Q[7]. The shift register input should be called S, which feeds the input of Q[0] (MSB is shifted in first). The enable input is synchronous active high and controls whether to shift. Extend the circuit to have 3 additional inputs A,B,C and an output Z. The circuit's behaviour should be as follows: when ABC is 000, Z=Q[0], when ABC is 001, Z=Q[1], and so on. Your circuit should contain ONLY the 8-bit shift register, and multiplexers.

module top_module (
	input clk,
	input enable,
	input S,
	input A,
	input B,
	input C,
	output reg Z
);
reg [7:0] Q;
	reg [2:0] addr;

	always @(posedge clk) begin
		if (enable) begin
			Q <= {Q[6:0], S};
		end
	end

	always @(*) begin
		case ({A,B,C})
			3'b000: addr = 3'b000;
			3'b001: addr = 3'b001;
			3'b010: addr = 3'b010;
			3'b011: addr = 3'b011;
			3'b100: addr = 3'b100;
			3'b101: addr = 3'b101;
			3'b110: addr = 3'b110;
			3'b111: addr = 3'b111;
		endcase
	end

	assign Z = addr[0] ? Q[7] : addr[1] ? Q[6] : addr[2] ? Q[5] : addr[3] ? Q[4] : addr[4] ? Q[3] : addr[5] ? Q[2] : addr[6] ? Q[1] : Q[0];

endmodule

32: warning: Constant bit select [3] is after vector addr[2:0].
32:        : Replacing select with a constant 1'bx.
32: warning: Constant bit select [5] is after vector addr[2:0].
32: warning: Constant bit select [6] is after vector addr[2:0].
32: warning: Constant bit select [4] is after vector addr[2:0].


A single-output digital system with four inputs (a,b,c,d) generates a logic-1 when 2, 7, or 15 appears on the inputs, and a logic-0 when 0, 1, 4, 5, 6, 9, 10, 13, or 14 appears. The input conditions for the numbers 3, 8, 11, and 12 never occur in this system. For example, 7 corresponds to a,b,c,d being set to 0,1,1,1, respectively. Determine the output out_sop in minimum sum-of-products form, and the output out_pos in minimum product-of-sums form.

module top_module (
	input a,
	input b,
	input c,
	input d,
	output out_sop,
	output out_pos
);

        // Define the output signals
        wire out_sop;
        wire out_pos;

        // Define the intermediate signals
        wire abcd_0;
        wire abcd_1;
        wire abcd_2;
        wire abcd_3;
        wire abcd_4;
        wire abcd_5;
        wire abcd_6;
        wire abcd_7;
        wire abcd_8;
        wire abcd_9;
        wire abcd_10;
        wire abcd_11;
        wire abcd_12;
        wire abcd_13;
        wire abcd_14;
        wire abcd_15;

        // Define the logic for the intermediate signals
        assign abcd_0 = ~(a & b & c & d);
        assign abcd_1 = ~(a & b & c & ~d);
        assign abcd_2 = ~(a & b & ~c & d);
        assign abcd_3 = ~(a & b & ~c & ~d);
        assign abcd_4 = ~(a & ~b & c & d);
        assign abcd_5 = ~(a & ~b & c & ~d);
        assign abcd_6 = ~(a & ~b & ~c & d);
        assign abcd_7 = ~(a & ~b & ~c & ~d);
        assign abcd_8 = ~(~a & b & c & d);
        assign abcd_9 = ~(~a & b & c & ~d);
        assign abcd_10 = ~(~a & b & ~c & d);
        assign abcd_11 = ~(~a & b & ~c & ~d);
        assign abcd_12 = ~(~a & ~b & c & d);
        assign abcd_13 = ~(~a & ~b & c & ~d);
        assign abcd_14 = ~(~a & ~b & ~c & d);
        assign abcd_15 = ~(~a & ~b & ~c & ~d);

        // Define the logic for the output signals
        assign out_sop = abcd_0 | abcd_1 | abcd_2 | abcd_3 | abcd_4 | abcd_5 | abcd_6 | abcd_7 | abcd_8 | abcd_9 | abcd_10 | abcd_11 | abcd_12 | abcd_13 | abcd_14 | abcd_15;
        assign out_pos = ~(abcd_0 & abcd_1 & abcd_2 & abcd_3 & abcd_4 & abcd_5 & abcd_6 & abcd_7 & abcd_8 & abcd_9 & abcd_10 & abcd_11 & abcd_12 & abcd_13 & abcd_14 & abcd_15);

endmodule

6:      : It was declared here as a net.
12: error: 'out_pos' has already been declared in this scope.
7:      : It was declared here as a net.
11: error: 'out_sop' has already been declared in this scope.


module top_module (
	input a,
	input b,
	input c,
	input d,
	output out_sop,
	output out_pos
);

        // Define the output signals
        wire out_sop;
        wire out_pos;

        // Define the intermediate signals
        wire abcd_0;
        wire abcd_1;
        wire abcd_2;
        wire abcd_3;
        wire abcd_4;
        wire abcd_5;
        wire abcd_6;
        wire abcd_7;
        wire abcd_8;
        wire abcd_9;
        wire abcd_10;
        wire abcd_11;
        wire abcd_12;
        wire abcd_13;
        wire abcd_14;

        // Define the logic for the intermediate signals
        assign abcd_0 = ~(a & b & c & d);
        assign abcd_1 = ~(a & b & c & ~d);
        assign abcd_2 = ~(a & b & ~c & d);
        assign abcd_3 = ~(a & b & ~c & ~d);
        assign abcd_4 = ~(a & ~b & c & d);
        assign abcd_5 = ~(a & ~b & c & ~d);
        assign abcd_6 = ~(a & ~b & ~c & d);
        assign abcd_7 = ~(a & ~b & ~c & ~d);
        assign abcd_8 = ~(~a & b & c & d);
        assign abcd_9 = ~(~a & b & c & ~d);
        assign abcd_10 = ~(~a & b & ~c & d);
        assign abcd_11 = ~(~a & b & ~c & ~d);
        assign abcd_12 = ~(~a & ~b & c & d);
        assign abcd_13 = ~(~a & ~b & c & ~d);
        assign abcd_14 = ~(~a & ~b & ~c & d);

        // Define the logic for the output signals
        assign out_sop = abcd_0 | abcd_1 | abcd_2 | abcd_3 | abcd_4 | abcd_5 | abcd_6 | abcd_7 | abcd_8 | abcd_9 | abcd_10 | abcd_11 | abcd_12 | abcd_13 | abcd_14;
        assign out_pos = ~(abcd_0 & abcd_1 & abcd_2 & abcd_3 & abcd_4 & abcd_5 & abcd_6 & abcd_7 & abcd_8 & abcd_9 & abcd_10 & abcd_11 & abcd_12 & abcd_13 & abcd_14);

endmodule


A large reservior of water serves several users. In order to keep the level of water succificently high, three sensors are placed vertically at 5-inch intervals. When the water level is above the highest sensor s[3], the input flow rate should be zero. When the level is below the lowest sensor s[1], the flow rate should be at maximum (both Nominal flow valve and Supplemental flow valve opened). The flow rate when the level is between the upper and lower sensors is determined by two factors: the water level and the level previous to the last sensor change. Each water level has a nominal flow rate associated with it as show in the table below. If the sensor change indicates that the previous level was lower than the current level, the flow rate should be increased by opening the Supplemental flow valve (controlled by dfr).
// Water Level | Sensors Asserted | Nominal Flow Rate Inputs to be Asserted
// Above s[3] | s[1], s[2], s[3] | None
// Between s[3] and s[2] | s[1], s[2] | fr1
// Between s[2] and s[1]  | s[1] | fr1, fr2
// Below s[1] | None | fr1, fr2, fr3
// Also include an active-high synchronous reset that resets the state machine to a state equivalent to if the water level had been low for a long time (no sensors asserted, and all four outputs asserted).

module top_module (
	input clk,
	input reset,
	input [3:1] s,
	output reg fr3,
	output reg fr2,
	output reg fr1,
	output reg dfr
);
 parameter IDLE = 2'b00,
                  FR1 = 2'b01,
                  FR2 = 2'b10,
                  FR3 = 2'b11;

        reg [1:0] state, next_state;
        reg [3:1] last_s;
        reg [3:1] next_s;
        reg [2:0] flow_rate;
        reg [2:0] next_flow_rate;

        always @(posedge clk) begin
                if (reset) begin
                        state <= IDLE;
                        last_s <= 3'b000;
                        flow_rate <= 3'b000;
                end else begin
                        state <= next_state;
                        last_s <= next_s;
                        flow_rate <= next_flow_rate;
                end
        end

        always @(*) begin
                case (state)
                        IDLE: begin
                                next_state = IDLE;
                                next_s = s;
                                next_flow_rate = 3'b000;
                                fr3 = 0;
                                fr2 = 0;
                                fr1 = 0;
                                dfr = 0;
                                if (s[3] == 1) begin
                                        next_state = IDLE;
                                        next_s = s;
                                        next_flow_rate = 3'b000;
                                        fr3 = 0;
                                        fr2 = 0;
                                        fr1 = 0;
                                        dfr = 0;
                                end else if (s[2] == 1) begin
                                        next_state = FR1;
                                        next_s = s;
                                        next_flow_rate = 3'b001;
                                        fr3 = 0;
                                        fr2 = 0;
                                        fr1 = 1;
                                        dfr = 0;
                                end else if (s[1] == 1) begin
                                        next_state = FR2;
                                        next_s = s;
                                        next_flow_rate = 3'b010;
                                        fr3 = 0;
                                        fr2 = 1;
                                        fr1 = 1;
                                        dfr = 0;
                                end else if (s[0] == 1) begin
                                        next_state = FR3;
                                        next_s = s;
                                        next_flow_rate = 3'b100;
                                        fr3 = 1;
                                        fr2 = 1;
                                        fr1 = 1;
                                        dfr = 0;
                                end
                        end
                        FR1: begin
                                next_state = FR1;
                                next_s = s;
                                next_flow_rate = 3'b001;
                                fr3 = 0;
                                fr2 = 0;
                                fr1 = 1;
                                dfr = 0;
                                if (s[3] == 1) begin
                                        next_state = IDLE;
                                        next_s = s;
                                        next_flow_rate = 3'b000;
                                        fr3 = 0;
                                        fr2 = 0;
                                        fr1 = 0;
                                        dfr = 0;
                                end else if (s[2] == 1) begin
                                        next_state = FR1;
                                        next_s = s;
                                        next_flow_rate = 3'b001;
                                        fr3 = 0;
                                        fr2 = 0;
                                        fr1 = 1;
                                        dfr = 0;
                                end else if (s[1] == 1) begin
                                        next_state = FR2;
                                        next_s = s;
                                        next_flow_rate = 3'b010;
                                        fr3 = 0;
                                        fr2 = 1;
                                        fr1 = 1;
                                        dfr = 0;
                                end else if (s[0] == 1) begin
                                        next_state = FR3;
                                        next_s = s;
                                        next_flow_rate = 3'b100;
                                        fr3 = 1;
                                        fr2 = 1;
                                        fr1 = 1;
                                        dfr = 0;
                                end
                        end
                        FR2: begin
                                next_state = FR2;
                                next_s = s;
                                next_flow_rate = 3'b010;
                                fr3 = 0;
                                fr2 = 1;
                                fr1 = 1;
                                dfr = 0;
                                if (s[3] == 1) begin
                                        next_state = IDLE;
                                        next_s = s;
                                        next_flow_rate = 3'b000;
                                        fr3 = 0;
                                        fr2 = 0;
                                        fr1 = 0;
                                        dfr = 0;
                                end else if (s[2] == 1) begin
                                        next_state = FR1;
                                        next_s = s;
                                        next_flow_rate = 3'b001;
                                        fr3 = 0;
                                        fr2 = 0;
                                        fr1 = 1;
                                        dfr = 0;
                                end else if (s[1] == 1) begin
                                        next_state = FR2;
                                        next_s = s;
                                        next_flow_rate = 3'b010;
                                        fr3 = 0;
                                        fr2 = 1;
                                        fr1 = 1;
                                        dfr = 0;
                                end else if (s[0] == 1) begin
                                        next_state = FR3;
                                        next_s = s;
                                        next_flow_rate = 3'b100;
                                        fr3 = 1;
                                        fr2 = 1;
                                        fr1 = 1;
                                        dfr = 0;
                                end
                        end
                        FR3: begin
                                next_state = FR3;
                                next_s = s;
                                next_flow_rate = 3'b100;
                                fr3 = 1;
                                fr2 = 1;
                                fr1 = 1;
                                dfr = 0;
                                if (s[3] == 1) begin
                                        next_state = IDLE;
                                        next_s = s;
                                        next_flow_rate = 3'b000;
                                        fr3 = 0;
                                        fr2 = 0;
                                        fr1 = 0;
                                        dfr = 0;
                                end else if (s[2] == 1) begin
                                        next_state = FR1;
                                        next_s = s;
                                        next_flow_rate = 3'b001;
                                        fr3 = 0;
                                        fr2 = 0;
                                        fr1 = 1;
                                        dfr = 0;
                                end else if (s[1] == 1) begin
                                        next_state = FR2;
                                        next_s = s;
                                        next_flow_rate = 3'b010;
                                        fr3 = 0;
                                        fr2 = 1;
                                        fr1 = 1;
                                        dfr = 0;
                                end else if (s[0] == 1) begin
                                        next_state = FR3;
                                        next_s = s;
                                        next_flow_rate = 3'b100;
                                        fr3 = 1;
                                        fr2 = 1;
                                        fr1 = 1;
                                        dfr = 0;
                                end
                        end
                endcase
        end

        always @(*) begin
                if (last_s[3] == 1) begin
                        fr3 = 0;
                        fr2 = 0;
                        fr1 = 0;
                        dfr = 0;
                end else if (last_s[2] == 1) begin
                        fr3 = 0;
                        fr2 = 0;
                        fr1 = 1;
                        dfr = 0;
                end else if (last_s[1] == 1) begin
                        fr3 = 0;
                        fr2 = 1;
                        fr1 = 1;
                        dfr = 0;
                end else if (last_s[0] == 1) begin
                        fr3 = 1;
                        fr2 = 1;
                        fr1 = 1;
                        dfr = 0;
                end
        end

endmodule

109: warning: Constant bit select [0] is before vector s[3:1].
151: warning: Constant bit select [0] is before vector s[3:1].
109:        : Replacing select with a constant 1'bx.
151:        : Replacing select with a constant 1'bx.
222:        : Replacing select with a constant 1'bx.
222: warning: Constant bit select [0] is before vector last_s[3:1].
193: warning: Constant bit select [0] is before vector s[3:1].
67:        : Replacing select with a constant 1'bx.
193:        : Replacing select with a constant 1'bx.
67: warning: Constant bit select [0] is before vector s[3:1].


module top_module (
	input clk,
	input reset,
	input [3:1] s,
	output reg fr3,
	output reg fr2,
	output reg fr1,
	output reg dfr
);
 parameter IDLE = 2'h0;    // Outputs are turned off; no flow; no pumping
         parameter PUMPING = 2'h1; // Pump is on; No outputs; Water is added
         parameter FLOWING = 2'h2; // No outputs; No water is added

        reg prev_s = 2'h0;
        reg [1:0] state = IDLE;

        //Water level 1
        //sensor s1
        //sensor s2
        //sensor s3
        //Water level 2
        //sensor s1
        //sensor s2
        //Flow rate fr1
        //Supplemental flow rate dfr
        //Water level 3
        //sensor s1
        //Flow rate fr1
        //Flow rate fr2
        //Water level 4
        //Flow rate fr1
        //Flow rate fr2
        //flow rate fr3

        always @ (posedge clk) begin
            if (reset) begin
                state <= IDLE;
                prev_s <= 2'h0;
                fr3 <= 1'b1;
                fr2 <= 1'b1;
                fr1 <= 1'b1;
                dfr <= 1'b1;
            end
            else begin
                case (state)
                    IDLE : begin
                        if (s[3]) begin
                            fr3 <= 1'b1;
                            fr2 <= 1'b1;
                            fr1 <= 1'b1;
                            dfr <= 1'b1;
                        end
                        else if (s[3] !== prev_s[3]) begin
                            if (s[2] && s[1]) begin
                                fr3 <= 1'b0;
                                fr2 <= 1'b1;
                                fr1 <= 1'b1;
                                dfr <= 1'b1;
                            end
                            else if (s[2] && !s[1]) begin
                                fr3 <= 1'b0;
                                fr2 <= 1'b1;
                                fr1 <= 1'b1;
                                dfr <= 1'b0;
                            end
                            else if (!s[2] && !s[1]) begin
                                fr3 <= 1'b0;
                                fr2 <= 1'b1;
                                fr1 <= 1'b0;
                                dfr <= 1'b0;
                            end
                        end
                        prev_s <= s;
                        state <= FLOWING;
                    end
                    FLOWING : begin
                        if (s[3] && !prev_s[3]) begin
                            fr3 <= 1'b1;
                            fr2 <= 1'b1;
                            fr1 <= 1'b1;
                            dfr <= 1'b1;
                        end
                        else if (s[3] && prev_s[3]) begin
                            fr3 <= 1'b1;
                            fr2 <= 1'b1;
                            fr1 <= 1'b1;
                            dfr <= 1'b1;
                        end
                        else if (!s[3] && prev_s[3]) begin
                            fr3 <= 1'b1;
                            fr2 <= 1'b1;
                            fr1 <= 1'b1;
                            dfr <= 1'b1;
                        end
                        else if (!s[3] && !prev_s[3]) begin
                            fr3 <= 1'b0;
                            fr2 <= 1'b1;
                            fr1 <= 1'b1;
                            dfr <= 1'b1;
                        end
                        prev_s <= s;
                    end
                    PUMPING : begin
                        if (s[3]) begin
                            fr3 <= 1'b1;
                            fr2 <= 1'b1;
                            fr1 <= 1'b1;
                            dfr <= 1'b1;
                        end
                        else begin
                            fr3 <= 1'b1;
                            fr2 <= 1'b1;
                            fr1 <= 1'b1;
                            dfr <= 1'b1;
                        end
                        state <= FLOWING;
                    end
                endcase
            end
        end
endmodule

77: error: can not select part of scalar: prev_s
53: error: Unable to elaborate condition expression.
77: error: Unable to elaborate condition expression.
53: error: can not select part of scalar: prev_s


Assume that you have two 8-bit 2's complement numbers, a[7:0] and b[7:0]. These numbers are added to produce s[7:0]. Also compute whether a (signed) overflow has occurred.

module top_module (
	input [7:0] a,
	input [7:0] b,
	output [7:0] s,
	output overflow
);
 reg [7:0] s;
         reg overflow;

         always @(*) begin
             s = a + b;
             overflow = (a[7] == b[7] && a[7] != s[7]);
         end

endmodule

7: error: 's' has already been declared in this scope.
4:      : It was declared here as a net.
8: error: 'overflow' has already been declared in this scope.
5:      : It was declared here as a net.


module top_module (
	input [7:0] a,
	input [7:0] b,
	output [7:0] s,
	output overflow
);
 reg [8:0] temp;
         reg overflow;

         always @(*) begin
         temp = a + b;
         if (temp[8] == 1) begin
         overflow = 1;
         end else begin
         overflow = 0;
         end
         s = temp[7:0];
         end

endmodule

8: error: 'overflow' has already been declared in this scope.
5:      : It was declared here as a net.


For the following Karnaugh map, give the circuit implementation using one 4-to-1 multiplexer and as many 2-to-1 multiplexers as required, but using as few as possible. You are not allowed to use any other logic gate and you must use _a_ and _b_ as the multiplexer selector inputs, as shown on the 4-to-1 multiplexer below.

//       ab
// cd   00 01 11 10
//  00 | 0 | 0 | 0 | 1 |
//  01 | 1 | 0 | 0 | 0 |
//  11 | 1 | 0 | 1 | 1 |
//  10 | 1 | 0 | 0 | 1 |

// Consider a block diagram with inputs 'c' and 'd' going into a module called "top_module". This "top_module" has four outputs, mux_in[3:0], that connect to a four input mux. The mux takes as input {a,b} and ab = 00 is connected to mux_in[0], ab=01 is connected to mux_in[1], and so in. You are implementing in Verilog just the portion labelled "top_module", such that the entire circuit (including the 4-to-1 mux) implements the K-map.

module top_module (
	input c,
	input d,
	output [3:0] mux_in
);
 wire [1:0] ab;
         wire [3:0] mux_out;

         // Implementing the 4-to-1 multiplexer
         mux_4to1 mux_4to1_inst (
         .in0(mux_in[0]),
         .in1(mux_in[1]),
         .in2(mux_in[2]),
         .in3(mux_in[3]),
         .sel({ab[1], ab[0]}),
         .out(mux_out)
         );

         // Implementing the 2-to-1 multiplexers
         mux_2to1 mux_2to1_inst1 (
         .in0(mux_out[0]),
         .in1(mux_out[1]),
         .sel(c),
         .out(mux_in[2])
         );

         mux_2to1 mux_2to1_inst2 (
         .in0(mux_out[2]),
         .in1(mux_out[3]),
         .sel(c),
         .out(mux_in[3])
         );

         mux_2to1 mux_2to1_inst3 (
         .in0(mux_in[2]),
         .in1(mux_in[3]),
         .sel(d),
         .out(mux_in[1])
         );

         mux_2to1 mux_2to1_inst4 (
         .in0(mux_in[0]),
         .in1(mux_in[1]),
         .sel(d),
         .out(mux_in[0])
         );

endmodule

20: error: Unknown module type: mux_2to1
10: error: Unknown module type: mux_4to1
34: error: Unknown module type: mux_2to1
27: error: Unknown module type: mux_2to1
41: error: Unknown module type: mux_2to1


module top_module (
	input c,
	input d,
	output [3:0] mux_in
);
 wire [3:0] mux_in;
         assign mux_in[0] = ~(c | d);
         assign mux_in[1] = ~(c & d);
         assign mux_in[2] = ~(c & ~d);
         assign mux_in[3] = ~(~c & d);

endmodule

6: error: 'mux_in' has already been declared in this scope.
4:      : It was declared here as a net.


Given the finite state machine circuit described below, assume that the D flip-flops are initially reset to zero before the machine begins.

// Build this circuit in Verilog.

// Input x goes to three different two-input gates: a XOR, an AND, and a OR gate. Each of the three gates is connected to the input of a D flip-flop and then the flip-flop outputs all go to a three-input XNOR, whose output is Z. The second input of the XOR is its corresponding flip-flop's output, the second input of the AND is its corresponding flip-flop's complemented output, and finally the second input of the OR is its corresponding flip-flop's complementary output.

module top_module (
	input clk,
	input x,
	output z
);
 // The initial state is all reset to zero before the machine begins.
         reg a, b, c;
         wire w1, w2, w3;
         reg xor2_out, and2_out, or2_out;
         always @(posedge clk) begin
             a <= 1'b0;
             b <= 1'b0;
             c <= 1'b0;
         end

         // The D flip-flops outputs go to a three-input XNOR, whose output is Z.
         xor2 xor2(.a(x), .b(xor2_out), .z(w1));
         and2 and2(.a(x), .b(~and2_out), .z(w2));
         or2 or2(.a(x), .b(~or2_out), .z(w3));
         xnor3 xnor3(.a(w1), .b(w2), .c(w3), .z(z));

         // The D flip-flops are connected to three different two-input gates.
         dffr dffr1(.clk(clk), .d(x), .q(xor2_out));
         dffr dffr2(.clk(clk), .d(~xor2_out), .q(and2_out));
         dffr dffr3(.clk(clk), .d(~and2_out), .q(or2_out));
endmodule

20: error: Unknown module type: xnor3
18: error: Unknown module type: and2
23: error: Unknown module type: dffr
25: error: Unknown module type: dffr
17: error: Unknown module type: xor2
19: error: Unknown module type: or2
24: error: Unknown module type: dffr


22: error: Unknown module type: OR2_X1
18: error: Unknown module type: DFFRX_X1
15: error: Unknown module type: DFFRX_X1
21: error: Unknown module type: OR2_X1
17: error: Unknown module type: DFFRX_X1
23: error: Unknown module type: XNOR2_X1
19: error: Unknown module type: XOR2_X1
20: error: Unknown module type: AND2_X1
16: error: Unknown module type: DFFRX_X1


You are to design a one-input one-output serial 2's complementer Moore state machine. The input (x) is a series of bits (one per clock cycle) beginning with the least-significant bit of the number, and the output (Z) is the 2's complement of the input. The machine will accept input numbers of arbitrary length. The circuit requires a positive edge triggered asynchronous reset. The conversion begins when Reset is released and stops when Reset is asserted.

module top_module (
	input clk,
	input areset,
	input x,
	output z
);
 // Synchronous reset
         reg [1:0] state;
         parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10;

         always @(posedge clk or negedge areset) begin
         // always block triggered on positive edge of clock signal or negative edge of asynchronous reset signal.
             if (!areset) begin
             // If asynchronous reset is active.
                 state <= S0;  // Set state to S0.
                 z <= 1'b0;    // Set output z to 0.
             end
             else begin
             // If asynchronous reset is not active.
                 case (state)
                 // Switching between states.
                     S0: begin
                     // State S0
                         if (x) begin
                         // If input x is true.
                             state <= S1;  // Move to state S1.
                             z <= 1'b1;    // Set output z to 1.
                         end
                         else begin
                         // If input x is false.
                             state <= S0;  // Stay in state S0.
                             z <= 1'b0;    // Set output z to 0.
                         end
                     end
                     S1: begin
                     // State S1
                         if (x) begin
                         // If input x is true.
                             state <= S2;  // Move to state S2.
                             z <= 1'b0;    // Set output z to 0.
                         end
                         else begin
                         // If input x is false.
                             state <= S0;  // Move to state S0.
                             z <= 1'b1;    // Set output z to 1.
                         end
                     end
                     S2: begin
                     // State S2
                         if (x) begin
                         // If input x is true.
                             state <= S1;  // Move to state S1.
                             z <= 1'b1;    // Set output z to 1.
                         end
                         else begin
                         // If input x is false.
                             state <= S0;  // Move to state S0.
                             z <= 1'b0;    // Set output z to 0.
                         end
                     end
                 endcase
             end
         end

endmodule

40: error: 'z' is not a valid l-value for a procedural assignment.
53: error: 'z' is not a valid l-value for a procedural assignment.
5:      : 'z' is declared here as a wire.
27: error: 'z' is not a valid l-value for a procedural assignment.
32: error: 'z' is not a valid l-value for a procedural assignment.
16: error: 'z' is not a valid l-value for a procedural assignment.
45: error: 'z' is not a valid l-value for a procedural assignment.
58: error: 'z' is not a valid l-value for a procedural assignment.


module top_module (
	input clk,
	input areset,
	input x,
	output z
);
 // Synchronous reset
	reg [1:0] state;
	parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10;

	always @(posedge clk or negedge areset) begin
		if (areset == 0) begin
			state <= S0;
		end else begin
			case (state)
				S0: begin
					if (x == 1) begin
						state <= S1;
					end else begin
						state <= S0;
					end
				end
				S1: begin
					if (x == 1) begin
						state <= S2;
					end else begin
						state <= S0;
					end
				end
				S2: begin
					if (x == 1) begin
						state <= S2;
					end else begin
						state <= S0;
					end
				end
			endcase
		end
	end

	always @(posedge clk or negedge areset) begin
		if (areset == 0) begin
			z <= 0;
		end else begin
			case (state)
				S0: begin
					z <= 0;
				end
				S1: begin
					z <= ~x;
				end
				S2: begin
					z <= ~x;
				end
			endcase
		end
	end

endmodule

53: error: 'z' is not a valid l-value for a procedural assignment.
5:      : 'z' is declared here as a wire.
43: error: 'z' is not a valid l-value for a procedural assignment.
50: error: 'z' is not a valid l-value for a procedural assignment.
47: error: 'z' is not a valid l-value for a procedural assignment.


The following diagram is a Mealy machine implementation of the 2's complementer. Implement in Verilog using one-hot encoding. Resets into state A and reset is asynchronous active-high.

// A --x=0 (z=0)--> A
// A --x=1 (z=1)--> B
// B --x=0 (z=1)--> B
// B --x=1 (z=0)--> B

module top_module (
	input clk,
	input areset,
	input x,
	output z
);
 parameter A = 2'b00;
             parameter B = 2'b01;
             parameter C = 2'b10;
             parameter D = 2'b11;

             reg [1:0] state;
             reg z;

             always @(posedge clk or posedge areset) begin
                 if (areset) begin
                     state <= A;
                     z <= 0;
                 end else begin
                     case (state)
                         A: begin
                             if (x) begin
                                 state <= B;
                                 z <= 1;
                             end else begin
                                 state <= A;
                                 z <= 0;
                             end
                         end
                         B: begin
                             if (x) begin
                                 state <= D;
                                 z <= 0;
                             end else begin
                                 state <= C;
                                 z <= 1;
                             end
                         end
                         C: begin
                             if (x) begin
                                 state <= D;
                                 z <= 0;
                             end else begin
                                 state <= C;
                                 z <= 1;
                             end
                         end
                         D: begin
                             if (x) begin
                                 state <= B;
                                 z <= 1;
                             end else begin
                                 state <= A;
                                 z <= 0;
                             end
                         end
                     endcase
                 end
             end

endmodule

13: error: 'z' has already been declared in this scope.
5:      : It was declared here as a net.


module top_module (
	input clk,
	input areset,
	input x,
	output z
);
 parameter A = 2'b00;
         parameter B = 2'b01;
         parameter C = 2'b10;
         parameter D = 2'b11;
         parameter E = 2'b100;
         parameter F = 2'b101;

        reg [2:0] state;
        reg z_reg;

        always @(posedge clk, posedge areset) begin
           if (areset) begin
              state <= A;
              z_reg <= 1'b0;
           end
           else begin
              case (state)
                 A: begin
                    if (x) begin
                       state <= B;
                       z_reg <= 1'b1;
                    end
                    else begin
                       state <= A;
                       z_reg <= 1'b0;
                    end
                 end
                 B: begin
                    if (x) begin
                       state <= C;
                       z_reg <= 1'b0;
                    end
                    else begin
                       state <= B;
                       z_reg <= 1'b1;
                    end
                 end
                 C: begin
                    if (x) begin
                       state <= D;
                       z_reg <= 1'b1;
                    end
                    else begin
                       state <= C;
                       z_reg <= 1'b0;
                    end
                 end
                 D: begin
                    if (x) begin
                       state <= E;
                       z_reg <= 1'b0;
                    end
                    else begin
                       state <= D;
                       z_reg <= 1'b1;
                    end
                 end
                 E: begin
                    if (x) begin
                       state <= F;
                       z_reg <= 1'b1;
                    end
                    else begin
                       state <= E;
                       z_reg <= 1'b0;
                    end
                 end
                 F: begin
                    if (x) begin
                       state <= A;
                       z_reg <= 1'b0;
                    end
                    else begin
                       state <= F;
                       z_reg <= 1'b1;
                    end
                 end
              endcase
           end
        end

        assign z = z_reg;

endmodule

12: warning: Numeric constant truncated to 2 bits.
11: warning: Numeric constant truncated to 2 bits.
11: warning: Extra digits given for sized binary constant.
12: warning: Extra digits given for sized binary constant.


For each bit in a 32-bit vector, capture when the input signal changes from 1 in one clock cycle to 0 the next. "Capture" means that the output will remain 1 until the register is reset (active high synchronous reset).

module top_module(
	input clk,
	input reset,
	input [31:0] in,
	output reg [31:0] out);
 // Define the flip-flops and their outputs
         reg [31:0] flip_flop_outputs;
         reg [31:0] flip_flop_inputs;

         // Initialize the flip-flops
         always @(posedge clk, posedge reset) begin
             if (reset) begin
                 flip_flop_outputs <= 0;
                 flip_flop_inputs <= 0;
             end else begin
                 flip_flop_outputs <= flip_flop_inputs;
                 flip_flop_inputs <= in;
             end
         end

         // Define the D flip-flops
         always @(posedge clk) begin
             if (flip_flop_inputs[0] == 0 && flip_flop_outputs[0] == 1) begin
                 out[0] <= 1;
             end else begin
                 out[0] <= 0;
             end

             for (i = 1; i < 32; i = i + 1) begin
                 if (flip_flop_inputs[i] == 0 && flip_flop_outputs[i] == 1) begin
                     out[i] <= 1;
                 end else begin
                     out[i] <= 0;
                 end
             end
         end

endmodule

29: register ``i'' unknown in top_module.


module top_module(
	input clk,
	input reset,
	input [31:0] in,
	output reg [31:0] out);
 reg [31:0] out_reg;

             always @(posedge clk) begin
                if (reset) begin
                    out_reg <= 0;
                end else begin
                    for (i = 0; i < 32; i = i + 1) begin
                        if (in[i] && !in[i-1]) begin
                            out_reg[i] <= 1;
                        end else if (!in[i] && in[i-1]) begin
                            out_reg[i] <= 0;
                        end
                    end
                end
                out <= out_reg;
            end
        endmodule

12: register ``i'' unknown in top_module.


For each bit in an 8-bit vector, detect when the input signal changes from 0 in one clock cycle to 1 the next (similar to positive edge detection). The output bit should be set the cycle after a 0 to 1 transition occurs.

module top_module(
	input clk,
	input [7:0] in,
	output reg [7:0] pedge);
 reg [7:0] in_reg;
             reg [7:0] in_next;
             reg [7:0] pedge_reg;
             reg [7:0] pedge_next;

             always @(posedge clk) begin
                 in_reg <= in;
                 in_next <= in;
                 pedge_reg <= pedge;
                 pedge_next <= pedge;
             end

             always @(posedge clk) begin
                 if (in_reg == 8'b0 && in_next == 8'b1) begin
                     pedge_next <= 8'b1;
                 end else begin
                     pedge_next <= 8'b0;
                 end
             end

             always @(posedge clk) begin
                 if (in_reg == 8'b0) begin
                     pedge <= 8'b0;
                 end else begin
                     pedge <= pedge_next;
                 end
             end

             assign pedge = pedge_reg;

        endmodule

27: error: Cannot perform procedural assignment to variable 'pedge' because it is also continuously assigned.
29: error: Cannot perform procedural assignment to variable 'pedge' because it is also continuously assigned.


module top_module(
	input clk,
	input [7:0] in,
	output reg [7:0] pedge);

        reg [7:0] prev_state;

        always @(posedge clk) begin
            pedge <= 1'b0;
            prev_state <= in;
            for (i = 0; i < 8; i = i + 1) begin
                if (in[i] == 1 && prev_state[i] == 0) begin
                    pedge[i] <= 1;
                end
            end
        end

    endmodule

11: register ``i'' unknown in top_module.


For each bit in an 8-bit vector, detect when the input signal changes from one clock cycle to the next (detect any edge). The output bit should be set the cycle after a 0 to 1 transition occurs.

module top_module(
	input clk,
	input [7:0] in,
	output reg [7:0] anyedge);

	reg [7:0] prev_in;

	always @(posedge clk) begin
		anyedge <= 8'b0;
		for (i = 0; i < 8; i = i + 1) begin
			if (in[i] == 1 && prev_in[i] == 0) begin
				anyedge[i] <= 1;
			end
		end
		prev_in <= in;
	end
endmodule

10: register ``i'' unknown in top_module.


Create a full adder. A full adder adds three bits (including carry-in) and produces a sum and carry-out.

module top_module (
	input a,
	input b,
	input cin,
	output cout,
	output sum
);

	wire [3:0] s;
	wire [3:0] c;

	full_adder fa0(a[0], b[0], cin, s[0], c[0]);
	full_adder fa1(a[1], b[1], c[0], s[1], c[1]);
	full_adder fa2(a[2], b[2], c[1], s[2], c[2]);
	full_adder fa3(a[3], b[3], c[2], s[3], cout);

	assign sum = {s[3], s[2], s[1], s[0]};

endmodule

13: error: Unknown module type: full_adder
12: error: Unknown module type: full_adder
15: error: Unknown module type: full_adder
14: error: Unknown module type: full_adder


module top_module (
	input a,
	input b,
	input cin,
	output cout,
	output sum
);
	full_adder adder (
		.a(a),
		.b(b),
		.cin(cin),
		.cout(cout),
		.sum(sum)
	);

endmodule

8: error: Unknown module type: full_adder


Consider the follow Moore machine with the diagram described below:

// B (1) --0--> A
// B (1) --1--> B
// A (0) --0--> B
// A (0) --1--> A

// Write Verilog implementing this state machine. It should asynchronously reset into state B if reset if high.

module top_module (
	input clk,
	input in,
	input areset,
	output out
);
 // Declare internal signals
         reg [1:0] state; // State variable
         wire [1:0] next_state; // Next state variable
         reg out_reg; // Output register

         // Define state transition logic
         always @ (posedge clk or posedge areset) begin
                 if (areset) begin
                         state <= 2'b01; // Reset into state B
                 end else begin
                         state <= next_state; // Update state on clock edge
                 end
         end

         // Define next state logic
         always @ (*) begin
                 case (state)
                         2'b01: next_state = in ? 2'b01 : 2'b10; // State B
                         2'b10: next_state = in ? 2'b10 : 2'b01; // State A
                 endcase
         end

         // Define output logic
         always @ (*) begin
                 case (state)
                         2'b01: out_reg = 1; // State B
                         2'b10: out_reg = 0; // State A
                 endcase
         end

         // Output logic
         assign out = out_reg;

endmodule

25: error: 'next_state' is not a valid l-value for a procedural assignment.
24: error: 'next_state' is not a valid l-value for a procedural assignment.
9:      : 'next_state' is declared here as a wire.


module top_module (
	input clk,
	input in,
	input areset,
	output out
);
 parameter A = 1'b0;
         parameter B = 1'b1;

         reg [0:0] current_state;
         reg [0:0] next_state;

         reg out;

         always @(posedge clk or posedge areset) begin
            if (areset) begin
               current_state <= B;
               out <= 1'b1;
            end else begin
               current_state <= next_state;
               case (current_state)
                  A: begin
                     if (in == 1'b0) begin
                        next_state <= B;
                        out <= 1'b0;
                     end else begin
                        next_state <= A;
                        out <= 1'b0;
                     end
                  end
                  B: begin
                     if (in == 1'b0) begin
                        next_state <= A;
                        out <= 1'b0;
                     end else begin
                        next_state <= B;
                        out <= 1'b1;
                     end
                  end
               endcase
            end
         end

endmodule

13: error: 'out' has already been declared in this scope.
5:      : It was declared here as a net.


This is a Moore state machine with two states, one input, and one output. Implement this state machine in Verilog. The reset state is B and reset is active-high synchronous.

// B (out=1) --in=0--> A
// B (out=1) --in=1--> B
// A (out=0) --in=0--> B
// A (out=0) --in=1--> A

module top_module (
	input clk,
	input in,
	input reset,
	output out
);
 // Define two states A and B and initialise to B
         // The state variable should be of type integer and should take values 0 and 1
         reg [1:0] state;
         parameter [1:0] B = 2'b00;
         parameter [1:0] A = 2'b01;
         initial state = B;

         // In the given FSM design, out is the output of the state machine
         reg out;

         // In the given FSM design, in is the input to the state machine
         always @(posedge clk or posedge reset) begin
             if (reset) begin
                 state <= B;
                 out <= 1'b1;
             end else begin
                 case(state)
                     B: begin
                         if (in) begin
                             state <= A;
                             out <= 1'b0;
                         end else begin
                             state <= B;
                             out <= 1'b1;
                         end
                     end
                     A: begin
                         if (in) begin
                             state <= A;
                             out <= 1'b0;
                         end else begin
                             state <= B;
                             out <= 1'b1;
                         end
                     end
                 endcase
             end
         end

endmodule

5:      : It was declared here as a net.
15: error: 'out' has already been declared in this scope.


module top_module (
	input clk,
	input in,
	input reset,
	output out
);
 parameter A = 1'b0;
         parameter B = 1'b1;
         parameter A_state = 1;
         parameter B_state = 0;
         parameter out_A = 1'b0;
         parameter out_B = 1'b1;

        reg [0:0] state_reg;
        wire [0:0] state_next;
        reg out_reg;

        always @(posedge clk, posedge reset)
        begin
           if (reset)
           begin
              state_reg <= B;
              out_reg <= out_B;
           end
           else
           begin
              state_reg <= state_next;
              out_reg <= out_A;
           end
        end

        always @(*)
        begin
           case (state_reg)
           B:
             begin
                state_next = in ? B : A;
                out_A = out_B;
                out_B = out_B;
             end
           A:
             begin
                state_next = in ? A : B;
                out_A = out_B;
                out_B = out_A;
             end
           default:
             begin
                state_next = B;
                out_A = out_B;
                out_B = out_B;
             end
           endcase
        end

        assign out = out_reg;

endmodule

45: error: Could not find variable ``out_B'' in ``top_module''
39: error: Could not find variable ``out_B'' in ``top_module''
15:      : 'state_next' is declared here as a wire.
51: error: Could not find variable ``out_B'' in ``top_module''
50: error: Could not find variable ``out_A'' in ``top_module''
44: error: Could not find variable ``out_A'' in ``top_module''
38: error: Could not find variable ``out_A'' in ``top_module''
37: error: 'state_next' is not a valid l-value for a procedural assignment.
43: error: 'state_next' is not a valid l-value for a procedural assignment.
49: error: 'state_next' is not a valid l-value for a procedural assignment.


This is a Moore state machine with two states, two inputs, and one output. Implement this state machine in Verilog. Reset is an active-high asynchronous reset to state OFF.

// OFF (out=0) --j=0--> OFF
// OFF (out=0) --j=1--> ON
// ON (out=1) --k=0--> ON
// ON (out=1) --k=1--> OFF

module top_module (
	input clk,
	input j,
	input k,
	input areset,
	output out
);
 // State register
         reg [1:0] state_reg;
         // Next state logic
         always @(posedge clk or posedge areset) begin
             if (areset) state_reg <= 2'b0;
             else state_reg <= next_state;
         end

         // Output logic
         assign out = state_reg[0];

         // Next state logic
         always @(*) begin
             case (state_reg)
                 2'b00: next_state = (j) ? 2'b01 : 2'b00;
                 2'b01: next_state = (k) ? 2'b10 : 2'b01;
                 2'b10: next_state = (k) ? 2'b00 : 2'b10;
             endcase
         end

endmodule

22: error: Could not find variable ``next_state'' in ``top_module''
13: error: Unable to bind wire/reg/memory `next_state' in `top_module'
23: error: Could not find variable ``next_state'' in ``top_module''
24: error: Could not find variable ``next_state'' in ``top_module''


module top_module (
	input clk,
	input j,
	input k,
	input areset,
	output out
);
 parameter OFF = 1'b0;
         parameter ON = 1'b1;
         parameter OFF_STATE = 2'b00;
         parameter ON_STATE = 2'b01;

         reg [1:0] state, next_state;
         reg out_reg;

         always @(posedge clk or posedge areset) begin
            if (areset) begin
               state <= OFF_STATE;
               out_reg <= OFF;
            end else begin
               state <= next_state;
               out_reg <= out;
            end
         end

         always @(*) begin
            case (state)
               OFF_STATE: begin
                  if (j) begin
                     next_state = ON_STATE;
                     out = ON;
                  end else begin
                     next_state = OFF_STATE;
                     out = OFF;
                  end
               end
               ON_STATE: begin
                  if (k) begin
                     next_state = OFF_STATE;
                     out = OFF;
                  end else begin
                     next_state = ON_STATE;
                     out = ON;
                  end
               end
            endcase
         end

endmodule

34: error: 'out' is not a valid l-value for a procedural assignment.
40: error: 'out' is not a valid l-value for a procedural assignment.
31: error: 'out' is not a valid l-value for a procedural assignment.
6:      : 'out' is declared here as a wire.
43: error: 'out' is not a valid l-value for a procedural assignment.


This is a Moore state machine with two states, two inputs, and one output. Implement this state machine in Verilog. Reset is an active-high synchronous reset to state OFF.

// OFF (out=0) --j=0--> OFF
// OFF (out=0) --j=1--> ON
// ON (out=1) --k=0--> ON
// ON (out=1) --k=1--> OFF

module top_module (
	input clk,
	input j,
	input k,
	input reset,
	output out
);
 parameter OFF = 1'b0;
             parameter ON = 1'b1;
             parameter OFF_OFF = 2'b00;
             parameter OFF_ON = 2'b01;
             parameter ON_OFF = 2'b10;
             parameter ON_ON = 2'b11;

             reg [1:0] state, next_state;
             reg out;

             always @(posedge clk) begin
                 if (reset) begin
                     state <= OFF;
                 end else begin
                     state <= next_state;
                 end
             end

             always @(*) begin
                 case (state)
                     OFF: begin
                         if (j == 1 && k == 0) begin
                             next_state = ON;
                         end else if (j == 0 && k == 1) begin
                             next_state = OFF;
                         end else begin
                             next_state = OFF;
                         end
                     end
                     ON: begin
                         if (j == 1 && k == 0) begin
                             next_state = ON;
                         end else if (j == 0 && k == 1) begin
                             next_state = OFF;
                         end else begin
                             next_state = ON;
                         end
                     end
                 endcase
             end

             always @(*) begin
                 case (state)
                     OFF: begin
                         out = 1'b0;
                     end
                     ON: begin
                         out = 1'b1;
                     end
                 endcase
             end

endmodule

16: error: 'out' has already been declared in this scope.
6:      : It was declared here as a net.


module top_module (
	input clk,
	input j,
	input k,
	input reset,
	output out
);
 parameter OFF = 1'b0;
         parameter ON = 1'b1;
         parameter OFF_ = 1'b0;
         parameter ON_ = 1'b1;

        reg [1:0] state, next_state;
        reg out_reg;

        always @(posedge clk) begin
            if (reset) begin
                state <= OFF;
                out_reg <= OFF_;
            end else begin
                state <= next_state;
                out_reg <= state;
            end
        end

        always @(*) begin
            case(state)
                OFF: begin
                    if (j) begin
                        next_state = ON;
                        out = ON_;
                    end else begin
                        next_state = OFF;
                        out = OFF_;
                    end
                end
                ON: begin
                    if (k) begin
                        next_state = OFF;
                        out = OFF_;
                    end else begin
                        next_state = ON;
                        out = ON_;
                    end
                end
            endcase
        end

endmodule


The following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include a positive edge triggered asynchronous reset that resets the FSM to state A.

// state | next state in=0, next state in=1 | output
// A | A, B | 0
// B | C, B | 0
// C | A, D | 0
// D | C, B | 1

module top_module (
	input clk,
	input in,
	input areset,
	output out
);
 // State variables
         reg [1:0] state; // State variable with 2 bits
         reg [1:0] next_state; // Next state variable
         reg [1:0] out_state; // Output variable

         // State definitions
         parameter [1:0] STATE_A = 2'b00;
         parameter [1:0] STATE_B = 2'b01;
         parameter [1:0] STATE_C = 2'b10;
         parameter [1:0] STATE_D = 2'b11;

         // State transition table
         always @(posedge clk, posedge areset) begin
           if (areset) begin
             state <= STATE_A;
             out <= 1'b0; // Initialize output to 0
           end else begin
             state <= next_state;
             case (state)
               STATE_A: begin
                 out <= 1'b0;
                 if (in) begin
                   next_state <= STATE_B;
                 end else begin
                   next_state <= STATE_A;
                 end
               end
               STATE_B: begin
                 out <= 1'b0;
                 if (in) begin
                   next_state <= STATE_B;
                 end else begin
                   next_state <= STATE_C;
                 end
               end
               STATE_C: begin
                 out <= 1'b0;
                 if (in) begin
                   next_state <= STATE_D;
                 end else begin
                   next_state <= STATE_A;
                 end
               end
               STATE_D: begin
                 out <= 1'b1;
                 if (in) begin
                   next_state <= STATE_B;
                 end else begin
                   next_state <= STATE_C;
                 end
               end
             endcase
           end
         end

endmodule

5:      : 'out' is declared here as a wire.
22: error: 'out' is not a valid l-value for a procedural assignment.
35: error: 'out' is not a valid l-value for a procedural assignment.
51: error: 'out' is not a valid l-value for a procedural assignment.
27: error: 'out' is not a valid l-value for a procedural assignment.
43: error: 'out' is not a valid l-value for a procedural assignment.


module top_module (
	input clk,
	input in,
	input areset,
	output out
);
 // state register
         reg [1:0] state;
         // next state logic
         always @(posedge clk or posedge areset) begin
                 if (areset)
                         state <= 2'b00; // reset to state A
                 else
                         state <= next_state;
         end
         // output logic
         assign out = (state == 2'b10) ? 1 : 0;
         // next state logic
         always @* begin
                 case (state)
                         2'b00: next_state = (in == 0) ? 2'b00 : 2'b01;
                         2'b01: next_state = (in == 0) ? 2'b01 : 2'b01;
                         2'b10: next_state = (in == 0) ? 2'b00 : 2'b01;
                         2'b11: next_state = (in == 0) ? 2'b01 : 2'b01;
                 endcase
         end
endmodule

23: error: Could not find variable ``next_state'' in ``top_module''
24: error: Could not find variable ``next_state'' in ``top_module''
21: error: Could not find variable ``next_state'' in ``top_module''
22: error: Could not find variable ``next_state'' in ``top_module''
14: error: Unable to bind wire/reg/memory `next_state' in `top_module'


The following is the state transition table for a Moore state machine with one input, one output, and four states. Use the following state encoding: A=2'b00, B=2'b01, C=2'b10, D=2'b11.Implement only the state transition logic and output logic (the combinational logic portion) for this state machine. Given the current state (state), compute the next_state and output (out) based on the state transition table.
// State | Next state in=0, Next state in=1 | Output
// A | A, B | 0
// B | C, B | 0
// C | A, D | 0
// D | C, B | 1

module top_module (
	input in,
	input [1:0] state,
	output reg [1:0] next_state,
	output out
);
 // State transition logic
         always @(*) begin
         case (state)
             2'b00: next_state = in ? 2'b01 : 2'b00; // A to B
             2'b01: next_state = in ? 2'b10 : 2'b01; // B to C or B to B
             2'b10: next_state = in ? 2'b00 : 2'b11; // C to A or C to D
             2'b11: next_state = in ? 2'b01 : 2'b10; // D to B or D to C
         endcase
         end

         // Output logic
         always @(*) begin
         case (state)
             2'b00, 2'b01: out = 1'b0; // A, B states
             2'b10, 2'b11: out = 1'b1; // C, D states
         endcase
         end

endmodule

5:      : 'out' is declared here as a wire.
21: error: 'out' is not a valid l-value for a procedural assignment.
20: error: 'out' is not a valid l-value for a procedural assignment.


module top_module (
	input in,
	input [1:0] state,
	output reg [1:0] next_state,
	output out
);
 // State transition logic
        always @* begin
        case (state)
            2'b00: next_state = (in == 1'b0) ? 2'b00 : 2'b01;  // A
            2'b01: next_state = (in == 1'b0) ? 2'b10 : 2'b01;  // B
            2'b10: next_state = (in == 1'b0) ? 2'b00 : 2'b11;  // C
            2'b11: next_state = (in == 1'b0) ? 2'b10 : 2'b01;  // D
            default: next_state = 2'b00;  // Default to state A
        endcase
    end

        // Output logic
        always @* begin
        case (state)
            2'b00, 2'b01, 2'b10: out = 1'b0;  // Output 0 for states A, B, C
            2'b11: out = 1'b1;  // Output 1 for state D
            default: out = 1'b0;  // Default to output 0
        endcase
    end

endmodule

5:      : 'out' is declared here as a wire.
21: error: 'out' is not a valid l-value for a procedural assignment.
22: error: 'out' is not a valid l-value for a procedural assignment.
23: error: 'out' is not a valid l-value for a procedural assignment.


The following is the state transition table for a Moore state machine with one input, one output, and four states. Use the following one-hot state encoding: A=4'b0001, B=4'b0010, C=4'b0100, D=4'b1000. Derive state transition and output logic equations by inspection assuming a one-hot encoding. Implement only the state transition logic and output logic (the combinational logic portion) for this state machine.
// State | Next state in=0, Next state in=1 | Output
// A | A, B | 0
// B | C, B | 0
// C | A, D | 0
// D | C, B | 1

module top_module (
	input in,
	input [3:0] state,
	output reg [3:0] next_state,
	output out
);
 // State transition logic
         always @(*) begin
         case(state)
         4'b0001: if(in == 1'b0) next_state = 4'b0001; else next_state = 4'b0010;
         4'b0010: if(in == 1'b0) next_state = 4'b0010; else next_state = 4'b0100;
         4'b0100: if(in == 1'b0) next_state = 4'b0001; else next_state = 4'b1000;
         4'b1000: if(in == 1'b0) next_state = 4'b0100; else next_state = 4'b0010;
         endcase
         end

         // Output logic
         always @(*) begin
         case(state)
         4'b0001: out = 1'b0;
         4'b0010: out = 1'b0;
         4'b0100: out = 1'b0;
         4'b1000: out = 1'b1;
         endcase
         end

endmodule

5:      : 'out' is declared here as a wire.
22: error: 'out' is not a valid l-value for a procedural assignment.
21: error: 'out' is not a valid l-value for a procedural assignment.
23: error: 'out' is not a valid l-value for a procedural assignment.
20: error: 'out' is not a valid l-value for a procedural assignment.


module top_module (
	input in,
	input [3:0] state,
	output reg [3:0] next_state,
	output out
);
 always @(*) begin
                case(state)
                        4'b0001: begin // State A
                                if(in == 1'b0) begin
                                        next_state = 4'b0001; // Stay in state A
                                end else begin
                                        next_state = 4'b0010; // Transition to state B
                                end
                                out = 1'b0; // Output 0
                        end
                        4'b0010: begin // State B
                                if(in == 1'b0) begin
                                        next_state = 4'b0010; // Stay in state B
                                end else begin
                                        next_state = 4'b0100; // Transition to state C
                                end
                                out = 1'b0; // Output 0
                        end
                        4'b0100: begin // State C
                                if(in == 1'b0) begin
                                        next_state = 4'b0001; // Transition to state A
                                end else begin
                                        next_state = 4'b1000; // Transition to state D
                                end
                                out = 1'b0; // Output 0
                        end
                        4'b1000: begin // State D
                                if(in == 1'b0) begin
                                        next_state = 4'b0100; // Transition to state C
                                end else begin
                                        next_state = 4'b0010; // Transition to state B
                                end
                                out = 1'b1; // Output 1
                        end
                endcase
        end
endmodule

5:      : 'out' is declared here as a wire.
39: error: 'out' is not a valid l-value for a procedural assignment.
23: error: 'out' is not a valid l-value for a procedural assignment.
31: error: 'out' is not a valid l-value for a procedural assignment.
15: error: 'out' is not a valid l-value for a procedural assignment.


The following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include a synchronous active high reset that resets the FSM to state A.
// State | Next state in=0, Next state in=1 | Output
// A | A, B | 0
// B | C, B | 0
// C | A, D | 0
// D | C, B | 1

module top_module (
	input clk,
	input in,
	input reset,
	output out
);
 parameter A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11;

         reg [1:0] state, next_state;

         always @ (posedge clk, posedge reset)
         begin
           if (reset)
             state <= A;
           else
             state <= next_state;
         end

         always @ (state, in)
         begin
           case (state)
             A: begin
                 out = 0;
                 if (in == 0)
                   next_state = A;
                 else
                   next_state = B;
             end
             B: begin
                 out = 0;
                 if (in == 0)
                   next_state = C;
                 else
                   next_state = B;
             end
             C: begin
                 out = 0;
                 if (in == 0)
                   next_state = A;
                 else
                   next_state = D;
             end
             D: begin
                 out = 1;
                 if (in == 0)
                   next_state = C;
                 else
                   next_state = B;
             end
           endcase
         end
endmodule

37: error: 'out' is not a valid l-value for a procedural assignment.
5:      : 'out' is declared here as a wire.
30: error: 'out' is not a valid l-value for a procedural assignment.
44: error: 'out' is not a valid l-value for a procedural assignment.
23: error: 'out' is not a valid l-value for a procedural assignment.


module top_module (
	input clk,
	input in,
	input reset,
	output out
);
 parameter A = 2'b00;
         parameter B = 2'b01;
         parameter C = 2'b10;
         parameter D = 2'b11;

        reg [1:0] state, next_state;
        reg out_reg;

        always @ (posedge clk) begin
            if (reset) begin
                state <= A;
                out_reg <= 0;
            end
            else begin
                state <= next_state;
                out_reg <= out;
            end
        end

        always @ (state, in) begin
            case (state)
                A: begin
                    if (in) begin
                        next_state = B;
                        out = 0;
                    end
                    else begin
                        next_state = A;
                        out = 0;
                    end
                end
                B: begin
                    if (in) begin
                        next_state = B;
                        out = 0;
                    end
                    else begin
                        next_state = C;
                        out = 0;
                    end
                end
                C: begin
                    if (in) begin
                        next_state = D;
                        out = 0;
                    end
                    else begin
                        next_state = A;
                        out = 0;
                    end
                end
                D: begin
                    if (in) begin
                        next_state = B;
                        out = 1;
                    end
                    else begin
                        next_state = C;
                        out = 0;
                    end
                end
            endcase
        end

        assign out = out_reg;

endmodule

61: error: 'out' is not a valid l-value for a procedural assignment.
5:      : 'out' is declared here as a wire.
65: error: 'out' is not a valid l-value for a procedural assignment.
35: error: 'out' is not a valid l-value for a procedural assignment.
51: error: 'out' is not a valid l-value for a procedural assignment.
55: error: 'out' is not a valid l-value for a procedural assignment.
31: error: 'out' is not a valid l-value for a procedural assignment.
45: error: 'out' is not a valid l-value for a procedural assignment.
41: error: 'out' is not a valid l-value for a procedural assignment.


Synchronous HDLC framing involves decoding a continuous bit stream of data to look for bit patterns that indicate the beginning and end of frames (packets). Seeing exactly 6 consecutive 1s (i.e., 01111110) is a "flag" that indicate frame boundaries. To avoid the data stream from accidentally containing "flags", the sender inserts a zero after every 5 consecutive 1s which the receiver must detect and discard. We also need to signal an error if there are 7 or more consecutive 1s. Create a Moore-type finite state machine to recognize these three sequences:

// (1) 0111110: Signal a bit needs to be discarded (disc).
// (2) 01111110: Flag the beginning/end of a frame (flag).
// (3) 01111111...: Error (7 or more 1s) (err).

// When the FSM is reset, it should be in a state that behaves as though the previous input were 0. The reset signal is active high synchronous. The output signals should be asserted for a complete cycle beginning on the clock cycle after the condition occurs.

module top_module (
	input clk,
	input reset,
	input in,
	output disc,
	output flag,
	output err);
 // Define the 3 states
        parameter s0 = 2'b00;
        parameter s1 = 2'b01;
        parameter s2 = 2'b10;

        // Define the state and output register
        reg [1:0] state, next_state;
        reg disc, flag, err;

        // Initialize the state and output register
        initial begin
            state = s0;
            disc = 1'b0;
            flag = 1'b0;
            err = 1'b0;
        end

        // Update the state and output register on the clock cycle after the condition occurs
        always @(posedge clk) begin
            if (reset) begin
                state <= s0;
                disc <= 1'b0;
                flag <= 1'b0;
                err <= 1'b0;
            end else begin
                state <= next_state;
                disc <= 1'b0;
                flag <= 1'b0;
                err <= 1'b0;
            end
        end

        // Define the next state and output register based on the current state and input
        always @(*) begin
            case (state)
                s0: begin
                    if (in == 1'b1) begin
                        next_state = s1;
                        disc = 1'b0;
                        flag = 1'b0;
                        err = 1'b0;
                    end else begin
                        next_state = s0;
                        disc = 1'b0;
                        flag = 1'b0;
                        err = 1'b0;
                    end
                end
                s1: begin
                    if (in == 1'b1) begin
                        next_state = s2;
                        disc = 1'b0;
                        flag = 1'b0;
                        err = 1'b0;
                    end else begin
                        next_state = s0;
                        disc = 1'b0;
                        flag = 1'b0;
                        err = 1'b0;
                    end
                end
                s2: begin
                    if (in == 1'b1) begin
                        next_state = s2;
                        disc = 1'b0;
                        flag = 1'b0;
                        err = 1'b0;
                    end else begin
                        next_state = s0;
                        disc = 1'b0;
                        flag = 1'b1;
                        err = 1'b0;
                    end
                end
                default: begin
                    next_state = s0;
                    disc = 1'b0;
                    flag = 1'b0;
                    err = 1'b0;
                end
            endcase
        end

    endmodule

15: error: 'err' has already been declared in this scope.
5:      : It was declared here as a net.
15: error: 'disc' has already been declared in this scope.
15: error: 'flag' has already been declared in this scope.
7:      : It was declared here as a net.
6:      : It was declared here as a net.


module top_module (
	input clk,
	input reset,
	input in,
	output disc,
	output flag,
	output err);
 parameter STATE_0 = 0;
         parameter STATE_1 = 1;
         parameter STATE_2 = 2;
         parameter STATE_3 = 3;
         parameter STATE_4 = 4;
         parameter STATE_5 = 5;
         parameter STATE_6 = 6;
         parameter STATE_DISCARD = 7;
         parameter STATE_ERROR = 8;

         reg [3:0] state;
         reg [3:0] next_state;

         reg disc_reg;
         reg flag_reg;
         reg err_reg;

         always @(posedge clk) begin
            if (reset) begin
               state <= STATE_0;
               disc_reg <= 0;
               flag_reg <= 0;
               err_reg <= 0;
            end else begin
               state <= next_state;
               disc_reg <= 0;
               flag_reg <= 0;
               err_reg <= 0;
            end
         end

         always @(*) begin
            case (state)
               STATE_0: begin
                  if (in == 1) begin
                     next_state = STATE_1;
                  end else begin
                     next_state = STATE_0;
                  end
               end
               STATE_1: begin
                  if (in == 1) begin
                     next_state = STATE_2;
                  end else begin
                     next_state = STATE_0;
                  end
               end
               STATE_2: begin
                  if (in == 1) begin
                     next_state = STATE_3;
                  end else begin
                     next_state = STATE_0;
                  end
               end
               STATE_3: begin
                  if (in == 1) begin
                     next_state = STATE_4;
                  end else begin
                     next_state = STATE_0;
                  end
               end
               STATE_4: begin
                  if (in == 1) begin
                     next_state = STATE_5;
                  end else begin
                     next_state = STATE_0;
                  end
               end
               STATE_5: begin
                  if (in == 1) begin
                     next_state = STATE_6;
                  end else begin
                     next_state = STATE_DISCARD;
                  end
               end
               STATE_6: begin
                  if (in == 1) begin
                     next_state = STATE_6;
                  end else begin
                     next_state = STATE_0;
                  end
               end
               STATE_DISCARD: begin
                  next_state = STATE_0;
                  disc_reg = 1;
               end
               STATE_ERROR: begin
                  next_state = STATE_ERROR;
                  err_reg = 1;
               end
            endcase
         end

         always @(posedge clk) begin
            if (reset) begin
               disc <= 0;
               flag <= 0;
               err <= 0;
            end else begin
               disc <= disc_reg;
               flag <= flag_reg;
               err <= err_reg;
            end
         end

         always @(posedge clk) begin
            if (reset) begin
               disc_reg <= 0;
               flag_reg <= 0;
               err_reg <= 0;
            end else begin
               case (state)
                  STATE_0: begin
                     disc_reg <= 0;
                     flag_reg <= 0;
                     err_reg <= 0;
                  end
                  STATE_1: begin
                     disc_reg <= 0;
                     flag_reg <= 0;
                     err_reg <= 0;
                  end
                  STATE_2: begin
                     disc_reg <= 0;
                     flag_reg <= 0;
                     err_reg <= 0;
                  end
                  STATE_3: begin
                     disc_reg <= 0;
                     flag_reg <= 0;
                     err_reg <= 0;
                  end
                  STATE_4: begin
                     disc_reg <= 0;
                     flag_reg <= 0;
                     err_reg <= 0;
                  end
                  STATE_5: begin
                     disc_reg <= 0;
                     flag_reg <= 0;
                     err_reg <= 0;
                  end
                  STATE_6: begin
                     disc_reg <= 0;
                     flag_reg <= 1;
                     err_reg <= 0;
                  end
                  STATE_DISCARD: begin
                     disc_reg <= 1;
                     flag_reg <= 0;
                     err_reg <= 0;
                  end
                  STATE_ERROR: begin
                     disc_reg <= 0;
                     flag_reg <= 0;
                     err_reg <= 1;
                  end
               endcase
            end
         end

      endmodule

109: error: 'err' is not a valid l-value for a procedural assignment.
6:      : 'flag' is declared here as a wire.
108: error: 'flag' is not a valid l-value for a procedural assignment.
104: error: 'flag' is not a valid l-value for a procedural assignment.
7:      : 'err' is declared here as a wire.
5:      : 'disc' is declared here as a wire.
107: error: 'disc' is not a valid l-value for a procedural assignment.
105: error: 'err' is not a valid l-value for a procedural assignment.
103: error: 'disc' is not a valid l-value for a procedural assignment.


Given the follow state machine with 1 input and 2 outputs (the outputs are given as "(out1, out2)"):

// S0 (0, 0) --0--> S0
// S0 (0, 0) --1--> S1
// S1 (0, 0) --0--> S0
// S1 (0, 0) --1--> S2
// S2 (0, 0) --0--> S0
// S2 (0, 0) --1--> S3
// S3 (0, 0) --0--> S0
// S3 (0, 0) --1--> S4
// S4 (0, 0) --0--> S0
// S4 (0, 0) --1--> S5
// S5 (0, 0) --0--> S8
// S5 (0, 0) --1--> S6
// S6 (0, 0) --0--> S9
// S6 (0, 0) --1--> S7
// S7 (0, 1) --0--> S0
// S7 (0, 1) --1--> S7
// S8 (1, 0) --0--> S0
// S8 (1, 0) --1--> S1
// S9 (1, 1) --0--> S0
// S9 (1, 1) --1--> S1

// Suppose this state machine uses one-hot encoding, where state[0] through state[9] correspond to the states S0 though S9, respectively. The outputs are zero unless otherwise specified.

// Write Verilog implementing the state transition logic and output logic portions of the state machine (but not the state flip-flops). You are given the current state in state[9:0] and must produce next_state[9:0] and the two outputs. Derive the logic equations by inspection assuming a one-hot encoding.

module top_module (
	input in,
	input [9:0] state,
	output [9:0] next_state,
	output out1,
	output out2);

18: error: 'next_state' is not a valid l-value for a procedural assignment.
4:      : 'next_state' is declared here as a wire.
22: error: 'next_state' is not a valid l-value for a procedural assignment.
23: error: 'next_state' is not a valid l-value for a procedural assignment.
21: error: 'next_state' is not a valid l-value for a procedural assignment.
15: error: 'next_state' is not a valid l-value for a procedural assignment.
16: error: 'next_state' is not a valid l-value for a procedural assignment.
24: error: 'next_state' is not a valid l-value for a procedural assignment.
19: error: 'next_state' is not a valid l-value for a procedural assignment.
17: error: 'next_state' is not a valid l-value for a procedural assignment.
14: error: 'next_state' is not a valid l-value for a procedural assignment.
20: error: 'next_state' is not a valid l-value for a procedural assignment.


module top_module (
	input in,
	input [9:0] state,
	output [9:0] next_state,
	output out1,
	output out2);
 // Output logic
         assign out1 = (state[7] | state[8] | state[9]);
         assign out2 = (state[7] | state[8]);

         // Transition logic
         always @* begin
            next_state = 10'b0000000000;
            case (state)
                10'b0000000001: if (in) next_state[1] = 1;
                10'b0000000010: if (in) next_state[2] = 1;
                10'b0000000100: if (in) next_state[4] = 1;
                10'b0000001000: if (in) next_state[8] = 1;
                10'b0000010000: if (in) next_state[9] = 1;
                10'b0000100000: if (in) next_state[0] = 1;
                10'b0001000000: if (in) next_state[1] = 1;
                10'b0010000000: if (in) next_state[2] = 1;
                10'b0100000000: if (in) next_state[4] = 1;
                10'b1000000000: if (in) next_state[8] = 1;
            endcase
         end

endmodule

4:      : 'next_state['sd1]' is declared here as a wire.
15: error: 'next_state['sd1]' is not a valid l-value for a procedural assignment.
4:      : 'next_state['sd2]' is declared here as a wire.
4:      : 'next_state['sd4]' is declared here as a wire.
20: error: 'next_state['sd0]' is not a valid l-value for a procedural assignment.
17: error: 'next_state['sd4]' is not a valid l-value for a procedural assignment.
23: error: 'next_state['sd4]' is not a valid l-value for a procedural assignment.
4:      : 'next_state' is declared here as a wire.
18: error: 'next_state['sd8]' is not a valid l-value for a procedural assignment.
21: error: 'next_state['sd1]' is not a valid l-value for a procedural assignment.
22: error: 'next_state['sd2]' is not a valid l-value for a procedural assignment.
13: error: 'next_state' is not a valid l-value for a procedural assignment.
4:      : 'next_state['sd8]' is declared here as a wire.
4:      : 'next_state['sd0]' is declared here as a wire.
4:      : 'next_state['sd9]' is declared here as a wire.
19: error: 'next_state['sd9]' is not a valid l-value for a procedural assignment.
16: error: 'next_state['sd2]' is not a valid l-value for a procedural assignment.
24: error: 'next_state['sd8]' is not a valid l-value for a procedural assignment.


The PS/2 mouse protocol sends messages that are three bytes long. However, within a continuous byte stream, it's not obvious where messages start and end. The only indication is that the first byte of each three byte message always has in[3]=1 (but in[3] of the other two bytes may be 1 or 0 depending on data). We want a finite state machine that will search for message boundaries when given an input byte stream. The algorithm we'll use is to discard bytes until we see one with in[3]=1. We then assume that this is byte 1 of a message, and signal the receipt of a message once all 3 bytes have been received (done). The FSM should signal done in the cycle immediately after the third byte of each message was successfully received. Reset should be active high synchronous.

module top_module (
	input clk,
	input [7:0] in,
	input reset,
	output done
);
 //parameter declarations
         parameter S0 = 2'd0, S1 = 2'd1;
         //internal variable declarations
         reg [1:0] state;
         reg [1:0] nextstate;
         reg [1:0] flag = 2'd0;
         //sequential logic
         always @( posedge clk ) begin
             if ( reset == 1'b1 ) begin
                state <= S0;
                flag <= 2'd0;
             end else begin
                state <= nextstate;
                if(state == S1) begin
                    flag <= flag + 1;
                end
                else if (state == S0) begin
                    flag <= 2'd0;
                end
             end
         end
         //combinational logic
         always @( * ) begin
             nextstate = S0;
             case(state)
             S0: begin
                 if(in[3] == 1) begin
                     nextstate = S1;
                 end
             end
             S1: begin
                 if(in[3] == 0) begin
                     nextstate = S2;
                 end
                 else begin
                     nextstate = S0;
                 end
             end
             S2: begin
                 if(in[3] == 0) begin
                     nextstate = S0;
                 end
                 else begin
                     nextstate = S1;
                 end
             end
             endcase
             //output logic
             case(flag)
             //do nothing
             2'd0: done <= 0;
             //signal done in cycle after 2nd byte
             2'd1: done <= 0;
             //signal done in cycle after 3rd byte
             2'd2: done <= 1;
             endcase
         end
endmodule

59: error: 'done' is not a valid l-value for a procedural assignment.
39: error: Unable to bind wire/reg/memory `S2' in `top_module'
5:      : 'done' is declared here as a wire.
45: error: Unable to bind wire/reg/memory `S2' in `top_module'
61: error: 'done' is not a valid l-value for a procedural assignment.
57: error: 'done' is not a valid l-value for a procedural assignment.


module top_module (
	input clk,
	input [7:0] in,
	input reset,
	output done
);
 parameter  S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
         reg [1:0] state, next_state;
         reg done_r;
         wire [1:0] next_state;

         always @(posedge clk) begin
             if (reset) begin
                 state <= S0;
                 done_r <= 1'b0;
             end else begin
                 state <= next_state;
                 done_r <= done;
             end
         end

         always @(*) begin
             case (state)
                 S0: begin
                     if (in[3] == 1'b1)
                         next_state = S1;
                     else
                         next_state = S0;
                 end
                 S1: begin
                     if (in[3] == 1'b0)
                         next_state = S2;
                     else
                         next_state = S1;
                 end
                 S2: begin
                     if (in[3] == 1'b0)
                         next_state = S3;
                     else
                         next_state = S2;
                 end
                 S3: begin
                     if (in[3] == 1'b0)
                         next_state = S0;
                     else
                         next_state = S3;
                 end
             endcase
         end

         assign done = (state == S3) ? done_r : 1'b0;

endmodule

10: error: 'next_state' has already been declared in this scope.
8:      : It was declared here as a variable.


We want a finite state machine that will search for message boundaries when given an input byte stream. The algorithm we'll use is to discard bytes until we see one with in[3]=1. We then assume that this is byte 1 of a message, and signal the receipt of a message once all 3 bytes have been received (done). The FSM should signal done in the cycle immediately after the third byte of each message was successfully received.

// Implement the datapath module that will output the 24-bit (3 byte) message whenever a packet is received (out_bytes[23:16] is the first byte, out_bytes[15:8] is the second byte, etc.). The reset signal is active high synchronous. out_bytes needs to be valid whenever the done signal is asserted. You may output anything at other times (i.e., don't-care).

// Waveform example:
// time            clk             reset           in[7:0]         done            out_bytes
// 0ns             0               1                0              x                    x
// 5ns             1               1                0              0                    x
// 10ns            0               1                0              0                    x
// 15ns            1               0               2c              0                    x
// 20ns            0               0               2c              0                    x
// 25ns            1               0               81              0                    x
// 30ns            0               0               81              0                    x
// 35ns            1               0                9              0                    x
// 40ns            0               0                9              0                    x
// 45ns            1               0               6b              1               2c8109
// 50ns            0               0               6b              1               2c8109
// 55ns            1               0                d              0                    x
// 60ns            0               0                d              0                    x
// 65ns            1               0               8d              0                    x
// 70ns            0               0               8d              0                    x
// 75ns            1               0               6d              1               6b0d8d
// 80ns            0               0               6d              1               6b0d8d
// 85ns            1               0               12              0                    x
// 90ns            0               0               12              0                    x
// 95ns            1               0                1              0                    x
// 100ns           0               0                1              0                    x
// 105ns           1               0                d              1               6d1201
// 110ns           0               0                d              1               6d1201
// 115ns           1               0               76              0                    x
// 120ns           0               0               76              0                    x
// 125ns           1               0               3d              0                    x
// 130ns           0               0               3d              0                    x
// 135ns           1               0               ed              1                d763d
// 140ns           0               0               ed              1                d763d
// 145ns           1               0               8c              0                    x
// 150ns           0               0               8c              0                    x
// 155ns           1               0               f9              0                    x
// 160ns           0               0               f9              0                    x
// 165ns           1               0               ce              1               ed8cf9
// 170ns           0               0               ce              1               ed8cf9
// 175ns           1               0               c5              0                    x
// 180ns           0               0               c5              0                    x
// 185ns           1               0               aa              0                    x
// 190ns           0               0               aa              0                    x

module top_module (
	input clk,
	input [7:0] in,
	input reset,
	output [23:0] out_bytes,
	output done
);
 // state definitions
        parameter s_start = 2'b00;
        parameter s_byte1 = 2'b01;
        parameter s_byte2 = 2'b10;
        parameter s_byte3 = 2'b11;

        // state register and next state logic
        reg [1:0] state, next_state;
        always @(posedge clk) begin
            if (reset) state <= s_start;
            else state <= next_state;
        end

        // state machine
        always @(*) begin
            case (state)
                s_start: next_state = in[3] ? s_byte1 : s_start;
                s_byte1: next_state = in[7] ? s_byte2 : s_start;
                s_byte2: next_state = in[3] ? s_byte3 : s_start;
                s_byte3: next_state = s_start;
            endcase
        end

        // output logic
        always @(*) begin
            case (state)
                s_start, s_byte1, s_byte2: done = 0;
                s_byte3: done = 1;
            endcase
        end

        // message byte register
        reg [23:0] out_bytes;
        always @(posedge clk) begin
            if (reset) out_bytes <= 0;
            else if (state == s_byte3) out_bytes <= {in[7:0], in[15:8], in[23:16]};
        end

endmodule

40: error: 'out_bytes' has already been declared in this scope.
5:      : It was declared here as a net.


module top_module (
	input clk,
	input [7:0] in,
	input reset,
	output [23:0] out_bytes,
	output done
);
 parameter IDLE = 2'b00;
         parameter WAIT_FOR_START = 2'b01;
         parameter WAIT_FOR_END = 2'b10;

         reg [1:0] state;
         reg [23:0] out_bytes;
         reg done;

         always @(posedge clk) begin
            if (reset) begin
               state <= IDLE;
               out_bytes <= 0;
               done <= 0;
            end else begin
               case (state)
                  IDLE: begin
                     if (in[3]) begin
                        state <= WAIT_FOR_START;
                        out_bytes <= {in, 8'b0};
                     end
                  end
                  WAIT_FOR_START: begin
                     if (in[3]) begin
                        state <= WAIT_FOR_END;
                        out_bytes <= {out_bytes[15:0], in, 8'b0};
                     end else begin
                        state <= WAIT_FOR_START;
                        out_bytes <= {out_bytes[15:0], in, 8'b0};
                     end
                  end
                  WAIT_FOR_END: begin
                     if (in[3]) begin
                        state <= WAIT_FOR_START;
                        out_bytes <= {out_bytes[15:0], in, 8'b0};
                     end else begin
                        state <= IDLE;
                        out_bytes <= {out_bytes[15:0], in, 8'b0};
                        done <= 1;
                     end
                  end
               endcase
            end
         end

endmodule

6:      : It was declared here as a net.
14: error: 'done' has already been declared in this scope.
13: error: 'out_bytes' has already been declared in this scope.
5:      : It was declared here as a net.