Consider the function f shown in the Karnaugh map below. Implement this function.
//        x[1]x[2]
// x[3]x[4]   00 01 11 10
//  00 | 1 | 0 | 0 | 1 |
//  01 | 0 | 0 | 0 | 0 |
//  11 | 1 | 1 | 1 | 0 |
//  10 | 1 | 1 | 0 | 1 |

module top_module (
	input [4:1] x,
	output logic f
);

6: error: Unable to bind wire/reg/memory `x1' in `top_module'
6: error: Unable to bind wire/reg/memory `x2' in `top_module'
6: error: Unable to bind wire/reg/memory `x3' in `top_module'
6: error: Unable to bind wire/reg/memory `x4' in `top_module'
6: error: Unable to elaborate this case expression.
6: error: Concatenation/replication may not have zero width in this context.


module top_module (
	input [4:1] x,
	output logic f
);
 logic [1:0] x21;
             logic [1:0] x12;
             logic [1:0] x20;
             logic [1:0] x10;

             assign x21 = {x[2], x[1]};
             assign x12 = {x[1], x[2]};
             assign x20 = {x[2], x[0]};
             assign x10 = {x[1], x[0]};

             always_comb begin
                 case (x21)
                     2'b00: f = 1;
                     2'b01: f = 0;
                     2'b10: f = 0;
                     2'b11: f = 1;
                 endcase
             end

endmodule

13: warning: Constant bit select [0] is before vector x[4:1].
13:        : Replacing select with a constant 1'bx.
12:        : Replacing select with a constant 1'bx.
12: warning: Constant bit select [0] is before vector x[4:1].


// Consider the state machine shown below:

// A (0) --1--> B
// A (0) --0--> A
// B (0) --1--> C
// B (0) --0--> D
// C (0) --1--> E
// C (0) --0--> D
// D (0) --1--> F
// D (0) --0--> A
// E (1) --1--> E
// E (1) --0--> D
// F (1) --1--> C
// F (1) --0--> D

// Assume that a one-hot code is used with the state assignment y[5:0] = 000001(A), 000010(B), 000100(C), 001000(D), 010000(E), 100000(F)

// Write a Verilog for the signal Y1, which is the input of state flip-flop y[1], for the signal Y3, which is the input of state flip-flop y[3]. Derive the Verilog by inspection assuming a one-hot encoding.

module top_module (
	input [5:0] y,
	input w,
	output Y1,
	output Y3
);

4:      : It was declared here as a net.
8: error: 'Y3' has already been declared in this scope.
5:      : It was declared here as a net.
7: error: 'Y1' has already been declared in this scope.


module top_module (
	input [5:0] y,
	input w,
	output Y1,
	output Y3
);

        // Y1 is the input of state flip-flop y[1]
        assign Y1 = y1;

        // Y3 is the input of state flip-flop y[3]
        assign Y3 = y3;

endmodule

12: error: Unable to elaborate r-value: y3
12: error: Unable to bind wire/reg/memory `y3' in `top_module'
9: error: Unable to bind wire/reg/memory `y1' in `top_module'
9: error: Unable to elaborate r-value: y1


Consider the state machine shown below:

// A (0) --1--> B
// A (0) --0--> A
// B (0) --1--> C
// B (0) --0--> D
// C (0) --1--> E
// C (0) --0--> D
// D (0) --1--> F
// D (0) --0--> A
// E (1) --1--> E
// E (1) --0--> D
// F (1) --1--> C
// F (1) --0--> D

// Reset resets into state A and is synchronous active-high.

// Write complete Verilog code that represents this FSM. Use separate **always** blocks for the state table and the state flip-flops. Describe the FSM output, which is called _z_, using either continuous assignment statement(s) or an **always** block (at your discretion). Assign any state codes that you wish to use.

module top_module (
	input clk,
	input reset,
	input w,
	output z
);
 // Define state codes
         parameter A = 2'b00;
         parameter B = 2'b01;
         parameter C = 2'b10;
         parameter D = 2'b11;
         parameter E = 2'b01;
         parameter F = 2'b10;

         // Define state flip-flops
         reg [1:0] state;
         always @(posedge clk) begin
         if (reset) begin
             state <= A;
         end else begin
             case (state)
                 A: begin
                     if (w) begin
                         state <= B;
                     end else begin
                         state <= A;
                     end
                 end
                 B: begin
                     if (w) begin
                         state <= C;
                     end else begin
                         state <= D;
                     end
                 end
                 C: begin
                     if (w) begin
                         state <= E;
                     end else begin
                         state <= D;
                     end
                 end
                 D: begin
                     if (w) begin
                         state <= F;
                     end else begin
                         state <= A;
                     end
                 end
                 E: begin
                     if (w) begin
                         state <= E;
                     end else begin
                         state <= D;
                     end
                 end
                 F: begin
                     if (w) begin
                         state <= C;
                     end else begin
                         state <= D;
                     end
                 end
             endcase
         end
         end

         // Define state table
         always @(*) begin
         case (state)
             A: z = 1'b0;
             B: z = 1'b0;
             C: z = 1'b0;
             D: z = 1'b0;
             E: z = 1'b1;
             F: z = 1'b0;
         endcase
         end

endmodule

71: error: 'z' is not a valid l-value for a procedural assignment.
76: error: 'z' is not a valid l-value for a procedural assignment.
72: error: 'z' is not a valid l-value for a procedural assignment.
5:      : 'z' is declared here as a wire.
73: error: 'z' is not a valid l-value for a procedural assignment.
75: error: 'z' is not a valid l-value for a procedural assignment.
74: error: 'z' is not a valid l-value for a procedural assignment.


module top_module (
	input clk,
	input reset,
	input w,
	output z
);
 // Define state codes
         parameter A = 2'b00;
         parameter B = 2'b01;
         parameter C = 2'b10;
         parameter D = 2'b11;
         parameter E = 2'b100;
         parameter F = 2'b101;

         // Define state flip-flops
         reg [2:0] state;

         // Define state table
         always @(posedge clk) begin
         // always block triggered on positive edge of clock signal.
            if (reset) begin
            // If reset signal is high.
               state <= A; // Set state to A.
            end else begin
            // If reset signal is low.
               case (state)
               // Switching between states.
                  A: if (w) state <= B; else state <= A; // Transition based on input w.
                  B: if (w) state <= C; else state <= D; // Transition based on input w.
                  C: if (w) state <= E; else state <= D; // Transition based on input w.
                  D: if (w) state <= F; else state <= A; // Transition based on input w.
                  E: if (w) state <= E; else state <= D; // Transition based on input w.
                  F: if (w) state <= C; else state <= D; // Transition based on input w.
               endcase
            end
         end

         // Define output
         assign z = (state == E); // Output z is high when state is E.

endmodule

13: warning: Numeric constant truncated to 2 bits.
13: warning: Extra digits given for sized binary constant.
12: warning: Numeric constant truncated to 2 bits.
12: warning: Extra digits given for sized binary constant.


Consider the FSM described by the state diagram shown below:

// A --r1=0,r2=0,r3=0--> A
// A --r1=1--> B
// A --r1=0,r2=1--> C
// A --r1=0,r2=0,r3=0--> D
// B (g1=1) --r1=1--> B
// B (g1=1) --r1=0--> A
// C (g2=1) --r2=1--> C
// C (g2=1) --r2=0--> A

// Resetn is an active-low synchronous reset that resets into state A. This FSM acts as an arbiter circuit, which controls access to some type of resource by three requesting devices. Each device makes its request for the resource by setting a signal _r[i]_ = 1, where _r[i]_ is either _r[1]_, _r[2]_, or _r[3]_. Each r[i] is an input signal to the FSM, and represents one of the three devices. The FSM stays in state _A_ as long as there are no requests. When one or more request occurs, then the FSM decides which device receives a grant to use the resource and changes to a state that sets that device's _g[i]_ signal to 1. Each _g[i]_ is an output from the FSM. There is a priority system, in that device 1 has a higher priority than device 2, and device 3 has the lowest priority. Hence, for example, device 3 will only receive a grant if it is the only device making a request when the FSM is in state _A_. Once a device, _i_, is given a grant by the FSM, that device continues to receive the grant as long as its request, _r[i]_ = 1.

// Write complete Verilog code that represents this FSM. Use separate always blocks for the state table and the state flip-flops, as done in lectures. Describe the FSM outputs, _g[i]_, using either continuous assignment statement(s) or an always block (at your discretion). Assign any state codes that you wish to use.

module top_module (
	input clk,
	input resetn,
	input [3:1] r,
	output [3:1] g
);
 // Define state codes
         parameter A = 2'b00;
         parameter B = 2'b01;
         parameter C = 2'b10;
         parameter D = 2'b11;

         // Define state flip-flops
         reg [1:0] state;
         always @(posedge clk or negedge resetn) begin
         // always block triggered on positive edge of clock signal or negative edge of reset signal.
            if (!resetn) begin
            // If reset signal is active low.
               state <= A; // Set state to A.
            end else begin
            // If reset signal is not active low.
               case (state)
               // Switching between states.
                  A: begin
                     if (r[1] && !r[2] && !r[3]) begin
                     // If condition for state transition from A to B.
                        state <= B; // Move to state B.
                     end else if (!r[1] && r[2] && !r[3]) begin
                     // If condition for state transition from A to C.
                        state <= C; // Move to state C.
                     end else if (!r[1] && !r[2] && r[3]) begin
                     // If condition for state transition from A to D.
                        state <= D; // Move to state D.
                     end
                  end
                  B: begin
                     if (r[1]) begin
                     // If condition for state transition from B to B.
                        state <= B; // Stay in state B.
                     end else begin
                     // If condition for state transition from B to A.
                        state <= A; // Move to state A.
                     end
                  end
                  C: begin
                     if (r[2]) begin
                     // If condition for state transition from C to C.
                        state <= C; // Stay in state C.
                     end else begin
                     // If condition for state transition from C to A.
                        state <= A; // Move to state A.
                     end
                  end
                  D: begin
                     if (r[3]) begin
                     // If condition for state transition from D to D.
                        state <= D; // Stay in state D.
                     end else begin
                     // If condition for state transition from D to A.
                        state <= A; // Move to state A.
                     end
                  end
               endcase
            end
         end

         // Define state table
         always @(*) begin
         // Combinational logic based on current state.
            case (state)
            // Switching between states.
               A: begin
                  g[1] = 0; // Grant to device 1.
                  g[2] = 0; // Grant to device 2.
                  g[3] = 0; // Grant to device 3.
               end
               B: begin
                  g[1] = 1; // Grant to device 1.
                  g[2] = 0; // Grant to device 2.
                  g[3] = 0; // Grant to device 3.
               end
               C: begin
                  g[1] = 0; // Grant to device 1.
                  g[2] = 1; // Grant to device 2.
                  g[3] = 0; // Grant to device 3.
               end
               D: begin
                  g[1] = 0; // Grant to device 1.
                  g[2] = 0; // Grant to device 2.
                  g[3] = 1; // Grant to device 3.
               end
            endcase
         end

endmodule

73: error: 'g['sd1]' is not a valid l-value for a procedural assignment.
80: error: 'g['sd3]' is not a valid l-value for a procedural assignment.
5:      : 'g['sd1]' is declared here as a wire.
79: error: 'g['sd2]' is not a valid l-value for a procedural assignment.
83: error: 'g['sd1]' is not a valid l-value for a procedural assignment.
85: error: 'g['sd3]' is not a valid l-value for a procedural assignment.
5:      : 'g['sd2]' is declared here as a wire.
75: error: 'g['sd3]' is not a valid l-value for a procedural assignment.
78: error: 'g['sd1]' is not a valid l-value for a procedural assignment.
88: error: 'g['sd1]' is not a valid l-value for a procedural assignment.
84: error: 'g['sd2]' is not a valid l-value for a procedural assignment.
74: error: 'g['sd2]' is not a valid l-value for a procedural assignment.
89: error: 'g['sd2]' is not a valid l-value for a procedural assignment.
90: error: 'g['sd3]' is not a valid l-value for a procedural assignment.
5:      : 'g['sd3]' is declared here as a wire.


module top_module (
	input clk,
	input resetn,
	input [3:1] r,
	output [3:1] g
);
 // State codes
         parameter A = 2'b00;
         parameter B = 2'b01;
         parameter C = 2'b10;
         parameter D = 2'b11;

         // State flip-flops
         reg [1:0] state;
         always @(posedge clk, negedge resetn) begin
         if (!resetn) begin
            state <= A;
         end else begin
            case (state)
               A: begin
                  if (r[1] || r[2] || r[3]) begin
                     if (r[1] && !r[2] && !r[3]) begin
                        state <= B;
                     end else if (!r[1] && r[2] && !r[3]) begin
                        state <= C;
                     end else if (!r[1] && !r[2] && r[3]) begin
                        state <= D;
                     end
                  end
               end
               B: begin
                  if (r[1] || r[2] || r[3]) begin
                     if (r[1] && !r[2] && !r[3]) begin
                        state <= B;
                     end else if (!r[1] && r[2] && !r[3]) begin
                        state <= C;
                     end else if (!r[1] && !r[2] && r[3]) begin
                        state <= D;
                     end
                  end else begin
                     state <= A;
                  end
               end
               C: begin
                  if (r[1] || r[2] || r[3]) begin
                     if (r[1] && !r[2] && !r[3]) begin
                        state <= B;
                     end else if (!r[1] && r[2] && !r[3]) begin
                        state <= C;
                     end else if (!r[1] && !r[2] && r[3]) begin
                        state <= D;
                     end
                  end else begin
                     state <= A;
                  end
               end
               D: begin
                  if (r[1] || r[2] || r[3]) begin
                     if (r[1] && !r[2] && !r[3]) begin
                        state <= B;
                     end else if (!r[1] && r[2] && !r[3]) begin
                        state <= C;
                     end else if (!r[1] && !r[2] && r[3]) begin
                        state <= D;
                     end
                  end else begin
                     state <= A;
                  end
               end
            endcase
         end
      end

      // State table
      always @(*) begin
         case (state)
            A: begin
               g[1] = 0;
               g[2] = 0;
               g[3] = 0;
            end
            B: begin
               g[1] = 1;
               g[2] = 0;
               g[3] = 0;
            end
            C: begin
               g[1] = 0;
               g[2] = 1;
               g[3] = 0;
            end
            D: begin
               g[1] = 0;
               g[2] = 0;
               g[3] = 1;
            end
         endcase
      end

endmodule

80: error: 'g['sd3]' is not a valid l-value for a procedural assignment.
79: error: 'g['sd2]' is not a valid l-value for a procedural assignment.
5:      : 'g['sd1]' is declared here as a wire.
83: error: 'g['sd1]' is not a valid l-value for a procedural assignment.
85: error: 'g['sd3]' is not a valid l-value for a procedural assignment.
5:      : 'g['sd2]' is declared here as a wire.
78: error: 'g['sd1]' is not a valid l-value for a procedural assignment.
88: error: 'g['sd1]' is not a valid l-value for a procedural assignment.
84: error: 'g['sd2]' is not a valid l-value for a procedural assignment.
89: error: 'g['sd2]' is not a valid l-value for a procedural assignment.
90: error: 'g['sd3]' is not a valid l-value for a procedural assignment.
94: error: 'g['sd2]' is not a valid l-value for a procedural assignment.
95: error: 'g['sd3]' is not a valid l-value for a procedural assignment.
5:      : 'g['sd3]' is declared here as a wire.
93: error: 'g['sd1]' is not a valid l-value for a procedural assignment.


Consider a finite state machine that is used to control some type of motor. The FSM has inputs x and y, which come from the motor, and produces outputs f and g, which control the motor. There is also a clock input called clk and a reset input (synchronous, active low) called resetn. The FSM has to work as follows. As long as the reset input is asserted, the FSM stays in a beginning state, called state A. When the reset signal is de-asserted, then after the next clock edge the FSM has to set the output f to 1 for one clock cycle. Then, the FSM has to monitor the x input. When x has produced the values 1, 0, 1 in three successive clock cycles, then g should be set to 1 on the following clock cycle. While maintaining g = 1 the FSM has to monitor the y input. If y has the value 1 within at most two clock cycles, then the FSM should maintain g = 1 permanently (that is, until reset). But if y does not become 1 within two clock cycles, then the FSM should set g = 0 permanently (until reset).

module top_module (
	input clk,
	input resetn,
	input x,
	input y,
	output f,
	output g
);
 parameter A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11;
         reg [1:0] state, next_state;
         reg [1:0] x_prev, y_prev;
         reg [1:0] x_prev_prev, y_prev_prev;
         reg [1:0] count;
         reg g_prev;
         wire g;
         assign g = g_prev;
         reg f_prev;
         wire f;
         assign f = f_prev;

         always @(posedge clk or negedge resetn) begin
            if (!resetn) begin
               state <= A;
               x_prev <= 2'b00;
               y_prev <= 2'b00;
               x_prev_prev <= 2'b00;
               y_prev_prev <= 2'b00;
               count <= 2'b00;
               g_prev <= 1'b0;
               f_prev <= 1'b0;
            end else begin
               state <= next_state;
               x_prev_prev <= x_prev;
               x_prev <= x;
               y_prev_prev <= y_prev;
               y_prev <= y;
               count <= count + 1;
               if (x == 1) begin
                  count <= 2'b01;
               end else if (x != x_prev) begin
                  count <= 2'b00;
               end
               if (y == 1 && count <= 2) begin
                  g_prev <= 1'b1;
               end else begin
                  g_prev <= 1'b0;
               end
               if (state == C) begin
                  f_prev <= 1'b1;
               end else begin
                  f_prev <= 1'b0;
               end
            end
         end

         always @(*) begin
            case (state)
               A: begin
                  next_state = B;
                  f_prev = 1'b0;
               end
               B: begin
                  next_state = C;
                  f_prev = 1'b1;
               end
               C: begin
                  next_state = D;
                  f_prev = 1'b0;
               end
               D: begin
                  next_state = A;
                  f_prev = 1'b0;
               end
            endcase
         end

endmodule

15: error: 'g' has already been declared in this scope.
18: error: 'f' has already been declared in this scope.
7:      : It was declared here as a net.
6:      : It was declared here as a net.


module top_module (
	input clk,
	input resetn,
	input x,
	input y,
	output f,
	output g
);
 parameter A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11;
         reg [1:0] state, next_state;

         reg [1:0] count;
         reg [1:0] next_count;

         reg f_reg, g_reg;

         always @(posedge clk) begin
            if (!resetn) begin
               state <= A;
               count <= 2'b00;
               f_reg <= 1'b0;
               g_reg <= 1'b0;
            end
            else begin
               state <= next_state;
               count <= next_count;
               f_reg <= f;
               g_reg <= g;
            end
         end

         always @(*) begin
            case (state)
               A: begin
                  f = 1'b0;
                  g = 1'b0;
                  next_state = B;
                  next_count = 2'b00;
               end
               B: begin
                  f = 1'b1;
                  g = 1'b0;
                  next_state = C;
                  next_count = 2'b00;
               end
               C: begin
                  f = 1'b0;
                  g = 1'b0;
                  next_state = D;
                  next_count = 2'b00;
               end
               D: begin
                  f = 1'b0;
                  g = 1'b0;
                  if (x == 1) begin
                     next_state = D;
                     next_count = count + 1;
                  end
                  else begin
                     next_state = A;
                     next_count = 2'b00;
                  end
               end
            endcase
         end

         always @(*) begin
            if (y == 1) begin
               g = 1'b1;
            end
            else begin
               g = 1'b0;
            end
         end

         always @(*) begin
            if (count == 2'b11) begin
               f = 1'b1;
            end
            else begin
               f = 1'b0;
            end
         end

endmodule

69: error: 'g' is not a valid l-value for a procedural assignment.
7:      : 'g' is declared here as a wire.
78: error: 'f' is not a valid l-value for a procedural assignment.
72: error: 'g' is not a valid l-value for a procedural assignment.
42: error: 'g' is not a valid l-value for a procedural assignment.
47: error: 'f' is not a valid l-value for a procedural assignment.
81: error: 'f' is not a valid l-value for a procedural assignment.
6:      : 'f' is declared here as a wire.
36: error: 'g' is not a valid l-value for a procedural assignment.
41: error: 'f' is not a valid l-value for a procedural assignment.
48: error: 'g' is not a valid l-value for a procedural assignment.
54: error: 'g' is not a valid l-value for a procedural assignment.
53: error: 'f' is not a valid l-value for a procedural assignment.
35: error: 'f' is not a valid l-value for a procedural assignment.


Given the state-assigned table shown below, implement the logic functions Y[0] and z.
// Present state y[2:0] | Next state Y[2:0] x=0, Next state Y[2:0] x=1 | Output z
// 000 | 000, 001 | 0
// 001 | 001, 100 | 0
// 010 | 010, 001 | 0
// 011 | 001, 010 | 1
// 100 | 011, 100 | 1

module top_module (
	input clk,
	input x,
	input [2:0] y,
	output reg Y0,
	output reg z
);
 wire [2:0] next_state_x0;
         wire [2:0] next_state_x1;
         wire [2:0] current_state;

         // Mapping to next state Y[2:0] x=0
         always @(*) begin
          case (y)
           3'b000: next_state_x0 = 3'b000;
           3'b001: next_state_x0 = 3'b001;
           3'b010: next_state_x0 = 3'b001;
           3'b011: next_state_x0 = 3'b010;
           3'b100: next_state_x0 = 3'b011;
           default: next_state_x0 = 3'b000;
          endcase
         end

         // Mapping to next state Y[2:0] x=1
         always @(*) begin
          case (y)
           3'b000: next_state_x1 = 3'b001;
           3'b001: next_state_x1 = 3'b100;
           3'b010: next_state_x1 = 3'b001;
           3'b011: next_state_x1 = 3'b010;
           3'b100: next_state_x1 = 3'b100;
           default: next_state_x1 = 3'b000;
          endcase
         end

         // Current state
         always @(posedge clk) begin
          current_state <= y;
         end

         // Output Y0
         always @(*) begin
          case (current_state)
           3'b000: Y0 = next_state_x0[0];
           3'b001: Y0 = next_state_x0[1];
           3'b010: Y0 = next_state_x0[0];
           3'b011: Y0 = next_state_x0[1];
           3'b100: Y0 = next_state_x0[1];
           default: Y0 = 1'b0;
          endcase
         end

         // Output z
         always @(*) begin
          case (current_state)
           3'b000: z = next_state_x1[0];
           3'b001: z = next_state_x1[1];
           3'b010: z = next_state_x1[0];
           3'b011: z = next_state_x1[1];
           3'b100: z = next_state_x1[1];
           default: z = 1'b0;
          endcase
         end

endmodule

30: error: 'next_state_x1' is not a valid l-value for a procedural assignment.
18: error: 'next_state_x0' is not a valid l-value for a procedural assignment.
19: error: 'next_state_x0' is not a valid l-value for a procedural assignment.
20: error: 'next_state_x0' is not a valid l-value for a procedural assignment.
8:      : 'next_state_x0' is declared here as a wire.
16: error: 'next_state_x0' is not a valid l-value for a procedural assignment.
27: error: 'next_state_x1' is not a valid l-value for a procedural assignment.
9:      : 'next_state_x1' is declared here as a wire.
29: error: 'next_state_x1' is not a valid l-value for a procedural assignment.
32: error: 'next_state_x1' is not a valid l-value for a procedural assignment.
38: error: 'current_state' is not a valid l-value for a procedural assignment.
10:      : 'current_state' is declared here as a wire.
17: error: 'next_state_x0' is not a valid l-value for a procedural assignment.
28: error: 'next_state_x1' is not a valid l-value for a procedural assignment.
31: error: 'next_state_x1' is not a valid l-value for a procedural assignment.
15: error: 'next_state_x0' is not a valid l-value for a procedural assignment.


module top_module (
	input clk,
	input x,
	input [2:0] y,
	output reg Y0,
	output reg z
);

        reg [3:0] prev_state, next_state;
        reg [2:0] curr_state;
        reg [2:0] next_state_y2;
        reg [2:0] next_state_y1;
        reg [2:0] next_state_y0;
        reg [2:0] Y0_next;
        reg [2:0] Y1_next;
        reg [2:0] Y2_next;
        reg [2:0] z_next;
        reg [1:0] y_prev;
        reg [1:0] y_next;
        reg [1:0] x_prev;
        reg [1:0] x_next;

        always @(posedge clk) begin
            if (prev_state == 4'b0000) begin
                curr_state <= 3'b000;
            end else begin
                curr_state <= prev_state[3:1];
            end
            if (y[2:1] == 2'b00) begin
                next_state_y2 <= 3'b000;
                next_state_y1 <= 3'b001;
                next_state_y0 <= 3'b000;
            end else if (y[2:1] == 2'b01) begin
                next_state_y2 <= 3'b001;
                next_state_y1 <= 3'b100;
                next_state_y0 <= 3'b000;
            end else if (y[2:1] == 2'b10) begin
                next_state_y2 <= 3'b010;
                next_state_y1 <= 3'b001;
                next_state_y0 <= 3'b000;
            end else begin // y[2:1] == 2'b11
                next_state_y2 <= 3'b001;
                next_state_y1 <= 3'b010;
                next_state_y0 <= 3'b001;
            end
            Y0_next <= curr_state[2];
            Y1_next <= next_state_y1[2];
            Y2_next <= next_state_y2[2];
            z_next <= next_state_y0[2];
            if (x == 1'b0) begin
                Y0 <= Y0_next;
                Y1 <= Y1_next;
                Y2 <= Y2_next;
                z <= z_next;
            end else begin // x == 1'b1
                Y0 <= y[2];
                Y1 <= y[1];
                Y2 <= y[0];
                z <= 1'b1;
            end
            x_next <= x;
            y_next <= y;
            prev_state <= {x_prev, y_prev, curr_state[2:0], z};
            x_prev <= x_next;
            y_prev <= y_next;
        end
endmodule

57: error: Could not find variable ``Y1'' in ``top_module''
53: error: Could not find variable ``Y2'' in ``top_module''
58: error: Could not find variable ``Y2'' in ``top_module''
52: error: Could not find variable ``Y1'' in ``top_module''


Consider a finite state machine with inputs s and w. Assume that the FSM begins in a reset state called A, as depicted below. The FSM remains in state A as long as s = 0, and it moves to state B when s = 1. Once in state B the FSM examines the value of the input w in the next three clock cycles. If w = 1 in exactly two of these clock cycles, then the FSM has to set an output z to 1 in the following clock cycle. Otherwise z has to be 0. The FSM continues checking w for the next three clock cycles, and so on. Use as few states as possible. Note that the s input is used only in state A, so you need to consider just the w input. Assume reset is active high synchronous.

module top_module (
	input clk,
	input reset,
	input s,
	input w,
	output reg z
);
 parameter A = 2'b00;
         parameter B = 2'b01;
         parameter C = 2'b10;
         parameter D = 2'b11;
         parameter E = 2'b100;
         parameter F = 2'b101;
         parameter G = 2'b110;
         parameter H = 2'b111;
         parameter I = 2'b1000;
         parameter J = 2'b1001;
         parameter K = 2'b1010;
         parameter L = 2'b1011;
         parameter M = 2'b1100;
         parameter N = 2'b1101;
         parameter O = 2'b1110;
         parameter P = 2'b1111;

         reg [3:0] state, next_state;

         always @ (posedge clk or posedge reset) begin
            if (reset) begin
               state <= A;
               z <= 0;
            end else begin
               state <= next_state;
               case (state)
                  A: begin
                     if (s == 1) begin
                        next_state <= B;
                     end else begin
                        next_state <= A;
                     end
                  end
                  B: begin
                     if (w == 1) begin
                        next_state <= C;
                     end else begin
                        next_state <= B;
                     end
                  end
                  C: begin
                     if (w == 1) begin
                        next_state <= D;
                     end else begin
                        next_state <= B;
                     end
                  end
                  D: begin
                     if (w == 1) begin
                        next_state <= E;
                     end else begin
                        next_state <= B;
                     end
                  end
                  E: begin
                     if (w == 1) begin
                        next_state <= F;
                     end else begin
                        next_state <= B;
                     end
                  end
                  F: begin
                     if (w == 1) begin
                        next_state <= G;
                     end else begin
                        next_state <= B;
                     end
                  end
                  G: begin
                     if (w == 1) begin
                        next_state <= H;
                     end else begin
                        next_state <= B;
                     end
                  end
                  H: begin
                     if (w == 1) begin
                        next_state <= I;
                     end else begin
                        next_state <= B;
                     end
                  end
                  I: begin
                     if (w == 1) begin
                        next_state <= J;
                     end else begin
                        next_state <= B;
                     end
                  end
                  J: begin
                     if (w == 1) begin
                        next_state <= K;
                     end else begin
                        next_state <= B;
                     end
                  end
                  K: begin
                     if (w == 1) begin
                        next_state <= L;
                     end else begin
                        next_state <= B;
                     end
                  end
                  L: begin
                     if (w == 1) begin
                        next_state <= M;
                     end else begin
                        next_state <= B;
                     end
                  end
                  M: begin
                     if (w == 1) begin
                        next_state <= N;
                     end else begin
                        next_state <= B;
                     end
                  end
                  N: begin
                     if (w == 1) begin
                        next_state <= O;
                     end else begin
                        next_state <= B;
                     end
                  end
                  O: begin
                     if (w == 1) begin
                        next_state <= P;
                     end else begin
                        next_state <= B;
                     end
                  end
                  P: begin
                     if (w == 1) begin
                        next_state <= B;
                     end else begin
                        next_state <= A;
                     end
                  end
               endcase
            end
         end

         always @ (posedge clk or posedge reset) begin
            if (reset) begin
               z <= 0;
            end else begin
               case (state)
                  B: begin
                     if (w == 1) begin
                        z <= 1;
                     end else begin
                        z <= 0;
                     end
                  end
                  C: begin
                     if (w == 1) begin
                        z <= 1;
                     end else begin
                        z <= 0;
                     end
                  end
                  D: begin
                     if (w == 1) begin
                        z <= 1;
                     end else begin
                        z <= 0;
                     end
                  end
                  E: begin
                     if (w == 1) begin
                        z <= 1;
                     end else begin
                        z <= 0;
                     end
                  end
                  F: begin
                     if (w == 1) begin
                        z <= 1;
                     end else begin
                        z <= 0;
                     end
                  end
                  G: begin
                     if (w == 1) begin
                        z <= 1;
                     end else begin
                        z <= 0;
                     end
                  end
                  H: begin
                     if (w == 1) begin
                        z <= 1;
                     end else begin
                        z <= 0;
                     end
                  end
                  I: begin
                     if (w == 1) begin
                        z <= 1;
                     end else begin
                        z <= 0;
                     end
                  end
                  J: begin
                     if (w == 1) begin
                        z <= 1;
                     end else begin
                        z <= 0;
                     end
                  end
                  K: begin
                     if (w == 1) begin
                        z <= 1;
                     end else begin
                        z <= 0;
                     end
                  end
                  L: begin
                     if (w == 1) begin
                        z <= 1;
                     end else begin
                        z <= 0;
                     end
                  end
                  M: begin
                     if (w == 1) begin
                        z <= 1;
                     end else begin
                        z <= 0;
                     end
                  end
                  N: begin
                     if (w == 1) begin
                        z <= 1;
                     end else begin
                        z <= 0;
                     end
                  end
                  O: begin
                     if (w == 1) begin
                        z <= 1;
                     end else begin
                        z <= 0;
                     end
                  end
                  P: begin
                     if (w == 1) begin
                        z <= 1;
                     end else begin
                        z <= 0;
                     end
                  end
               endcase
            end
         end

endmodule

16: warning: Extra digits given for sized binary constant.
12: warning: Numeric constant truncated to 2 bits.
19: warning: Extra digits given for sized binary constant.
13: warning: Extra digits given for sized binary constant.
18: warning: Extra digits given for sized binary constant.
21: warning: Numeric constant truncated to 2 bits.
19: warning: Numeric constant truncated to 2 bits.
15: warning: Numeric constant truncated to 2 bits.
17: warning: Numeric constant truncated to 2 bits.
12: warning: Extra digits given for sized binary constant.
22: warning: Numeric constant truncated to 2 bits.
15: warning: Extra digits given for sized binary constant.
13: warning: Numeric constant truncated to 2 bits.
23: warning: Numeric constant truncated to 2 bits.
20: warning: Extra digits given for sized binary constant.
14: warning: Numeric constant truncated to 2 bits.
14: warning: Extra digits given for sized binary constant.
16: warning: Numeric constant truncated to 2 bits.
22: warning: Extra digits given for sized binary constant.
21: warning: Extra digits given for sized binary constant.
18: warning: Numeric constant truncated to 2 bits.
20: warning: Numeric constant truncated to 2 bits.
23: warning: Extra digits given for sized binary constant.
17: warning: Extra digits given for sized binary constant.


module top_module (
	input clk,
	input reset,
	input s,
	input w,
	output reg z
);
 parameter A = 2'b00;
         parameter B = 2'b01;
         parameter C = 2'b10;
         parameter D = 2'b11;
         parameter E = 2'b100;

         reg [2:0] currentState;

         always @(posedge clk) begin
            if (reset) begin
               currentState <= A;
               z <= 0;
            end else begin
               case (currentState)
                  A: begin
                     if (s) begin
                        currentState <= B;
                     end
                  end
                  B: begin
                     currentState <= C;
                  end
                  C: begin
                     currentState <= D;
                  end
                  D: begin
                     if (w == 1) begin
                        currentState <= E;
                     end else begin
                        currentState <= B;
                     end
                  end
                  E: begin
                     if (w == 1) begin
                        z <= 1;
                     end else begin
                        z <= 0;
                     end
                     currentState <= B;
                  end
               endcase
            end
         end

endmodule

12: warning: Numeric constant truncated to 2 bits.
12: warning: Extra digits given for sized binary constant.


Consider an n-bit shift register circuit. Inputs E are for enabling shift, R for value to load, L is asserted when it should load, and w is the input to the first stage of the shift register. Write a Verilog module named top_module for one stage of this circuit, including both the flip-flop and multiplexers.

module top_module (
	input clk,
	input w,
	input R,
	input E,
	input L,
	output reg Q
);
 always @(posedge clk) begin
            if (E) begin
                Q <= {Q[0], w};
            end else if (L) begin
                Q <= R;
            end
        end

endmodule

11: error: can not select part of scalar: Q


module top_module (
	input clk,
	input w,
	input R,
	input E,
	input L,
	output reg Q
);
 flip_flop ff(clk, E, w, Q);
         mux_2to1 mux(Q, R, L, Q);

endmodule

10: error: Unknown module type: mux_2to1
9: error: Unknown module type: flip_flop


The 7400-series integrated circuits are a series of digital chips with a few gates each. The 7420 is a chip with two 4-input NAND gates.

// Create a module with the same functionality as the 7420 chip. It has 8 inputs and 2 outputs.

module top_module(
	input p1a,
	input p1b,
	input p1c,
	input p1d,
	output p1y,
	input p2a,
	input p2b,
	input p2c,
	input p2d,
	output p2y
);
 sky130_fd_sc_hdll__nand2_1 nand1 (
                .A(p1a),
                .B(p1b),
                .Y(p1y)
            );

             sky130_fd_sc_hdll__nand2_1 nand2 (
                .A(p2a),
                .B(p2b),
                .Y(p2y)
            );

             sky130_fd_sc_hdll__not_1 not1 (
                .A(p1y),
                .Y(p1y)
            );

             sky130_fd_sc_hdll__not_1 not2 (
                .A(p2y),
                .Y(p2y)
            );

endmodule

19: error: Unknown module type: sky130_fd_sc_hdll__nand2_1
30: error: Unknown module type: sky130_fd_sc_hdll__not_1
13: error: Unknown module type: sky130_fd_sc_hdll__nand2_1
25: error: Unknown module type: sky130_fd_sc_hdll__not_1


module top_module(
	input p1a,
	input p1b,
	input p1c,
	input p1d,
	output p1y,
	input p2a,
	input p2b,
	input p2c,
	input p2d,
	output p2y
);
 wire nand1_out;
         wire nand2_out;

         sky130_fd_sc_hd__nand2_1 nand1 (nand1_out, p1a, p1b);
         sky130_fd_sc_hd__nand2_1 nand2 (nand2_out, p2a, p2b);
         sky130_fd_sc_hd__nand2_1 nand3 (p1y, nand1_out, p1c, p1d);
         sky130_fd_sc_hd__nand2_1 nand4 (p2y, nand2_out, p2c, p2d);
endmodule

18: error: Unknown module type: sky130_fd_sc_hd__nand2_1
19: error: Unknown module type: sky130_fd_sc_hd__nand2_1
16: error: Unknown module type: sky130_fd_sc_hd__nand2_1
17: error: Unknown module type: sky130_fd_sc_hd__nand2_1


The 7458 is a chip with four AND gates and two OR gates. Create a module in Verilog with the same functionality as the 7458 chip. It has 10 inputs and 2 outputs. You may choose to use an `assign` statement to drive each of the output wires, or you may choose to declare (four) wires for use as intermediate signals, where each internal wire is driven by the output of one of the AND gates.

// In this circuit, p1y should be the OR of two 3-input AND gates: one that ANDs p1a, p1b, and p1c, and the second that ANDs p1d, p1e, and p1f. The output p2y is the OR of two 2-input AND gates: one that ANDs p2a and p2b, and the second that ANDs p2c and p2d.

module top_module(
	input p1a,
	input p1b,
	input p1c,
	input p1d,
	input p1e,
	input p1f,
	output p1y,
	input p2a,
	input p2b,
	input p2c,
	input p2d,
	output p2y
);
wire p1y_temp;
 assign p1y = p1y_temp;
 always @(p1a or p1b or p1c or p1d or p1e or p1f) begin
 	p1y_temp = (p1a & p1b & p1c) | (p1d & p1e & p1f);
 end

 wire p2y_temp;
 assign p2y = p2y_temp;
 always @(p2a or p2b or p2c or p2d) begin
 	p2y_temp = (p2a & p2b) | (p2c & p2d);
 end

endmodule

24: error: 'p2y_temp' is not a valid l-value for a procedural assignment.
18: error: 'p1y_temp' is not a valid l-value for a procedural assignment.
21:      : 'p2y_temp' is declared here as a wire.
15:      : 'p1y_temp' is declared here as a wire.


Create a 6-to-1 multiplexer. When sel is between 0 and 5, choose the corresponding data input. Otherwise, output 0. The data inputs and outputs are all 4 bits wide.

module top_module (
	input [2:0] sel,
	input [3:0] data0,
	input [3:0] data1,
	input [3:0] data2,
	input [3:0] data3,
	input [3:0] data4,
	input [3:0] data5,
	output reg [3:0] out
);
 parameter DATA_WIDTH = 4;
         parameter SEL_WIDTH = 3;
         parameter NUM_DATA_INPUTS = 6;

         wire [DATA_WIDTH-1:0] data_inputs [0:NUM_DATA_INPUTS-1];
         wire [SEL_WIDTH-1:0] sel_input;
         assign sel_input = sel;

         // Assign data inputs to data_inputs array
         assign data_inputs[0] = data0;
         assign data_inputs[1] = data1;
         assign data_inputs[2] = data2;
         assign data_inputs[3] = data3;
         assign data_inputs[4] = data4;
         assign data_inputs[5] = data5;

         // Assign out to data_inputs[sel_input] if sel_input is within bounds, otherwise assign out to 0
         always @(*) begin
             if (sel_input >= 0 && sel_input <= NUM_DATA_INPUTS-1) begin
                 out = data_inputs[sel_input];
             end else begin
                 out = 0;
             end
         end

endmodule

30: warning: @* is sensitive to all 6 words in array 'data_inputs'.


Build a priority encoder for 8-bit inputs. Given an 8-bit vector, the output should report the first (least significant) bit in the vector that is 1. Report zero if the input vector has no bits that are high. For example, the input 8'b10010000 should output 3'd4, because bit[4] is first bit that is high.

module top_module (
	input [7:0] in,
	output reg [2:0] pos
);
 always @ (in) begin
          pos = 0;
          for (i = 0; i < 8; i = i + 1) begin
            if (in[i] == 1) begin
              pos = i;
              break;
            end
          end
        end

endmodule

7: register ``i'' unknown in top_module.


module top_module (
	input [7:0] in,
	output reg [2:0] pos
);
 always @ (posedge clk) begin
            if (in[0]) pos <= 0;
            else if (in[1]) pos <= 1;
            else if (in[2]) pos <= 2;
            else if (in[3]) pos <= 3;
            else if (in[4]) pos <= 4;
            else if (in[5]) pos <= 5;
            else if (in[6]) pos <= 6;
            else if (in[7]) pos <= 7;
            else pos <= 0;
        end

endmodule

5: error: Failed to evaluate event expression 'posedge clk'.
5: error: Unable to bind wire/reg/memory `clk' in `top_module'


Build a 2-to-1 mux that chooses between a and b. Choose b if both sel_b1 and sel_b2 are true. Otherwise, choose a. Do the same twice, once using assign statements and once using a procedural if statement.

module top_module (
	input a,
	input b,
	input sel_b1,
	input sel_b2,
	output out_assign,
	output reg out_always
);
 assign out_assign = (sel_b1 && sel_b2) ? b : a;

             always @(posedge clk) begin
                 if (sel_b1 && sel_b2) begin
                     out_always <= b;
                 end else begin
                     out_always <= a;
                 end
             end

endmodule

11: error: Failed to evaluate event expression 'posedge clk'.
11: error: Unable to bind wire/reg/memory `clk' in `top_module'


Fix any and all bugs in this code:

// module top_module (
//     input      cpu_overheated,
//     output reg shut_off_computer,
//     input      arrived,
//     input      gas_tank_empty,
//     output reg keep_driving  ); //

//     always @(*) begin
//         if (cpu_overheated)
//            shut_off_computer = 1;
//     end

//     always @(*) begin
//         if (~arrived)
//            keep_driving = ~gas_tank_empty;
//     end

// endmodule

module top_module (
	input cpu_overheated,
	output reg shut_off_computer,
	input arrived,
	input gas_tank_empty,
	output reg keep_driving
);
 parameter C_RESET_ACTIVE = 1'b1;

    // synthesis attribute async_register then_port="*"
    reg                         reset_r;
    always @ (posedge clk)  begin
        if (rst) begin
            reset_r <= C_RESET_ACTIVE;
        end else begin
            reset_r <= 1'b0;
        end
    end

    always @ (*) begin
        if (cpu_overheated)
            shut_off_computer = 1;
        else
            shut_off_computer = reset_r;
    end

    always @ (*) begin
        if (~arrived)
            keep_driving = ~gas_tank_empty;
        else
            keep_driving = 1'b0;
    end

endmodule

13: error: Unable to bind wire/reg/memory `rst' in `top_module'
13: error: Unable to elaborate condition expression.


module top_module (
	input cpu_overheated,
	output reg shut_off_computer,
	input arrived,
	input gas_tank_empty,
	output reg keep_driving
);
 parameter cpu_overheated = 1'b0;
         parameter arrived = 1'b0;
         parameter gas_tank_empty = 1'b0;

         always @(cpu_overheated) begin
            if (cpu_overheated) begin
               shut_off_computer <= 1'b1;
            end else begin
               shut_off_computer <= 1'b0;
            end
         end

         always @(arrived or gas_tank_empty) begin
            if (~arrived) begin
               keep_driving <= ~gas_tank_empty;
            end else begin
               keep_driving <= 1'b0;
            end
         end

endmodule

4:      : It was declared here as a net.
2:      : It was declared here as a net.
5:      : It was declared here as a net.
10: error: 'gas_tank_empty' has already been declared in this scope.
8: error: 'cpu_overheated' has already been declared in this scope.
9: error: 'arrived' has already been declared in this scope.


Suppose you're building a circuit to process scancodes from a PS/2 keyboard for a game. Given the last two bytes of scancodes received, you need to indicate whether one of the arrow keys on the keyboard have been pressed. This involves a fairly simple mapping, which can be implemented as a case statement (or if-elseif) with four cases.
// Scancode[15:0] | Arrow key
// 16'he06b | left arrow
// 16'he072 | down arrow
// 16'he074 | right arrow
// 16'he075 | up arrow
// Anything else | none
// Your circuit has one 16-bit input, and four outputs. Build this circuit that recognizes these four scancodes and asserts the correct output.

module top_module (
	input [15:0] scancode,
	output reg left,
	output reg down,
	output reg right,
	output reg up
);
 always @(posedge clk) begin
		case (scancode)
			16'h004B: left <= 1;
			16'h0050: down <= 1;
			16'h004D: right <= 1;
			16'h0052: up <= 1;
			default: begin
				left <= 0;
				down <= 0;
				right <= 0;
				up <= 0;
			end
		endcase
             end
endmodule

8: error: Failed to evaluate event expression 'posedge clk'.
8: error: Unable to bind wire/reg/memory `clk' in `top_module'


Create a module that implements an AND gate.

module top_module(
	input a,
	input b,
	output out
);
 and_gate and_inst(
                .a(a),
                .b(b),
                .out(out)
            );

endmodule


This combinational circuit is supposed to recognize 8-bit keyboard scancodes for keys 0 through 9. It should indicate whether one of the 10 cases were recognized (valid), and if so, which key was detected. If the 8-bit input is 8'h45, 8'h16, 8'h1e, 8'h26, 8'h25, 8'h2e, 8'h36, 8'h3d, 8'h3e, or 8'h46, the 4-bit output will be set to 0, 1, 2, 3, 4, 5, 6, 7, 8, or 9 respectively, the 1-bit valid would be set to 1. If the input does not match any of the cases, both output signals would be set to 0.

module top_module (
	input [7:0] code,
	output reg [3:0] out,
	output reg valid
);

        wire [7:0] code_i = code;
        wire [3:0] out_i = out;
        wire valid_i = valid;

        assign valid = valid_i;
        assign out = out_i;

        always @* begin
            case (code_i)
                8'h45: out_i = 0;
                8'h16: out_i = 1;
                8'h1e: out_i = 2;
                8'h26: out_i = 3;
                8'h25: out_i = 4;
                8'h2e: out_i = 5;
                8'h36: out_i = 6;
                8'h3d: out_i = 7;
                8'h3e: out_i = 8;
                8'h46: out_i = 9;
                default: begin
                    out_i = 0;
                    valid_i = 0;
                end
            endcase
        end
endmodule

17: error: 'out_i' is not a valid l-value for a procedural assignment.
19: error: 'out_i' is not a valid l-value for a procedural assignment.
20: error: 'out_i' is not a valid l-value for a procedural assignment.
22: error: 'out_i' is not a valid l-value for a procedural assignment.
23: error: 'out_i' is not a valid l-value for a procedural assignment.
24: error: 'out_i' is not a valid l-value for a procedural assignment.
16: error: 'out_i' is not a valid l-value for a procedural assignment.
9:      : 'valid_i' is declared here as a wire.
8:      : 'out_i' is declared here as a wire.
25: error: 'out_i' is not a valid l-value for a procedural assignment.
18: error: 'out_i' is not a valid l-value for a procedural assignment.
21: error: 'out_i' is not a valid l-value for a procedural assignment.
27: error: 'out_i' is not a valid l-value for a procedural assignment.
28: error: 'valid_i' is not a valid l-value for a procedural assignment.


Find the bug and fix this 8-bit wide 2-to-1 mux.

// module top_module (
//     input sel,
//     input [7:0] a,
//     input [7:0] b,
//     output out  );

//     assign out = (~sel & a) | (sel & b);

// endmodule

module top_module (
	input sel,
	input [7:0] a,
	input [7:0] b,
	output reg [7:0] out
);
 assign out = {out[0], out[1], out[2], out[3], out[4], out[5], out[6], out[7]} & {sel, sel, sel, sel, sel, sel, sel, sel};

             always @(*) begin
		if (sel == 1'b0)
			out = a;
		else
			out = b;
             end

endmodule

13: error: Cannot perform procedural assignment to variable 'out' because it is also continuously assigned.
11: error: Cannot perform procedural assignment to variable 'out' because it is also continuously assigned.


This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.

// time            a               b               q
// 0ns             0               0               0
// 5ns             0               0               0
// 10ns            0               0               0
// 15ns            0               0               0
// 20ns            0               0               0
// 25ns            0               1               0
// 30ns            0               1               0
// 35ns            1               0               0
// 40ns            1               0               0
// 45ns            1               1               1
// 50ns            1               1               1
// 55ns            0               0               0
// 60ns            0               0               0
// 65ns            0               1               0
// 70ns            0               1               0
// 75ns            1               0               0
// 80ns            1               0               0
// 85ns            1               1               1
// 90ns            1               1               1

module top_module (
	input a,
	input b,
	output q
);
always @(*)
begin
	q = (a & b) | (a & ~b) | (~a & b);
end

endmodule

4:      : 'q' is declared here as a wire.
8: error: 'q' is not a valid l-value for a procedural assignment.


This is a sequential circuit. The circuit consists of combinational logic and one bit of memory (i.e., one flip-flop). The output of the flip-flop has been made observable through the output state.

// Read the simulation waveforms to determine what the circuit does, then implement it.

// time            clk             a               b               state           q
// 0ns             0               1               x               x               x
// 5ns             1               1               x               x               x
// 10ns            0               0               0               x               x
// 15ns            1               0               0               0               0
// 20ns            0               0               0               0               0
// 25ns            1               0               0               0               0
// 30ns            0               0               0               0               0
// 35ns            1               0               0               0               0
// 40ns            0               0               0               0               0
// 45ns            1               0               1               0               1
// 50ns            0               0               1               0               1
// 55ns            1               1               0               0               1
// 60ns            0               1               0               0               1
// 65ns            1               1               1               0               0
// 70ns            0               1               1               0               0
// 75ns            1               0               0               1               1
// 80ns            0               0               0               1               1
// 85ns            1               1               1               0               0
// 90ns            0               1               1               0               0
// 95ns            1               1               1               1               1
// 100ns           0               1               1               1               1
// 105ns           1               1               1               1               1
// 110ns           0               1               1               1               1
// 115ns           1               1               0               1               0
// 120ns           0               1               0               1               0
// 125ns           1               0               1               1               0
// 130ns           0               0               1               1               0
// 135ns           1               0               0               1               1
// 140ns           0               0               0               1               1
// 145ns           1               0               0               0               0
// 150ns           0               0               0               0               0
// 155ns           1               0               0               0               0
// 160ns           0               0               0               0               0
// 165ns           1               0               0               0               0
// 170ns           0               0               0               0               0
// 175ns           1               0               0               0               0
// 180ns           0               0               0               0               0
// 185ns           1               0               0               0               0
// 190ns           0               0               0               0               0

module top_module (
	input clk,
	input a,
	input b,
	output q,
	output state
);
 assign state = (a) ? 1'b1 : ((b) ? 1'b1 : 1'b0);
         always @(posedge clk)
             q <= state;

endmodule

10: error: 'q' is not a valid l-value for a procedural assignment.
5:      : 'q' is declared here as a wire.


module top_module (
	input clk,
	input a,
	input b,
	output q,
	output state
);
 parameter [0:0] STATE_INIT = 1'b0;
         parameter [0:0] STATE_A = 1'b1;

         reg [0:0] state_reg;
         wire [0:0] state_next;

         assign state = state_reg;

         always @* begin
            state_next = state_reg;
            case (state_reg)
               STATE_INIT: begin
                  if (a) begin
                     state_next = STATE_A;
                  end
               end
               STATE_A: begin
                  if (!a) begin
                     state_next = STATE_INIT;
                  end
               end
            endcase
         end

         always @(posedge clk) begin
            state_reg <= state_next;
         end

         assign q = (state_reg == STATE_A) ? 1'b1 : 1'b0;

endmodule

21: error: 'state_next' is not a valid l-value for a procedural assignment.
12:      : 'state_next' is declared here as a wire.
26: error: 'state_next' is not a valid l-value for a procedural assignment.
17: error: 'state_next' is not a valid l-value for a procedural assignment.


This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.

// time            a               b               c               d               q
// 0ns             0               0               0               0               0
// 5ns             0               0               0               0               0
// 10ns            0               0               0               0               0
// 15ns            0               0               0               0               0
// 20ns            0               0               0               1               0
// 25ns            0               0               1               0               0
// 30ns            0               0               1               1               0
// 35ns            0               1               0               0               0
// 40ns            0               1               0               1               1
// 45ns            0               1               1               0               1
// 50ns            0               1               1               1               1
// 55ns            1               0               0               0               0
// 60ns            1               0               0               1               1
// 65ns            1               0               1               0               1
// 70ns            1               0               1               1               1
// 75ns            1               1               0               0               0
// 80ns            1               1               0               1               1
// 85ns            1               1               1               0               1
// 90ns            1               1               1               1               1

module top_module (
	input a,
	input b,
	input c,
	input d,
	output q
);
 reg q_reg;

             always @(posedge clk) begin
                 if (c && !d) begin
                     q_reg <= 0;
                 end else if (!c && d) begin
                     q_reg <= 1;
                 end else if (c && d) begin
                     q_reg <= a;
                 end else begin
                     q_reg <= b;
                 end
             end

             assign q = q_reg;

endmodule

10: error: Failed to evaluate event expression 'posedge clk'.
10: error: Unable to bind wire/reg/memory `clk' in `top_module'


This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.

// time            a               b               c               d               q
// 0ns             0               0               0               0               0
// 5ns             0               0               0               0               0
// 10ns            0               0               0               0               0
// 15ns            0               0               0               0               0
// 20ns            0               0               0               1               0
// 25ns            0               0               1               0               1
// 30ns            0               0               1               1               1
// 35ns            0               1               0               0               1
// 40ns            0               1               0               1               1
// 45ns            0               1               1               0               1
// 50ns            0               1               1               1               1
// 55ns            1               0               0               0               0
// 60ns            1               0               0               1               0
// 65ns            1               0               1               0               1
// 70ns            1               0               1               1               1
// 75ns            1               1               0               0               1
// 80ns            1               1               0               1               1
// 85ns            1               1               1               0               1
// 90ns            1               1               1               1               1

module top_module (
	input a,
	input b,
	input c,
	input d,
	output q
);
 reg q_reg;
             always @(posedge clk) begin
                 if (c && !d) begin
                     q_reg <= 0;
                 end else if (!c && d) begin
                     q_reg <= 1;
                 end else if (c && d) begin
                     q_reg <= a;
                 end else begin
                     q_reg <= b;
                 end
             end
             assign q = q_reg;

endmodule

9: error: Failed to evaluate event expression 'posedge clk'.
9: error: Unable to bind wire/reg/memory `clk' in `top_module'


module top_module (
	input a,
	input b,
	input c,
	input d,
	output q
);

        parameter logic [0:0] q_default = 1'b0;
        assign q = (a & b & ~c & d) | (~a & ~b & c & d) | (a & ~b & ~c & ~d) | (~a & b & c & ~d) | (a & b & c & d) | (~a & ~b & ~c & d) | (~a & b & ~c & ~d) | (a & ~b & c & ~d);
        initial begin
        q = q_default;
        end
        always @(a or b or c or d) begin
        q = (a & b & ~c & d) | (~a & ~b & c & d) | (a & ~b & ~c & ~d) | (~a & b & c & ~d) | (a & b & c & d) | (~a & ~b & ~c & d) | (~a & b & ~c & ~d) | (a & ~b & c & ~d);
        end

endmodule

15: error: 'q' is not a valid l-value for a procedural assignment.
12: error: 'q' is not a valid l-value for a procedural assignment.
6:      : 'q' is declared here as a wire.


This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.

// time            a               b               c               d               e               q
// 0ns             x               x               x               x               x               x
// 5ns             x               x               x               x               x               x
// 10ns            x               x               x               x               x               x
// 15ns            a               b               0               d               e               b
// 20ns            a               b               1               d               e               e
// 25ns            a               b               2               d               e               a
// 30ns            a               b               3               d               e               d
// 35ns            a               b               4               d               e               f
// 40ns            a               b               5               d               e               f
// 45ns            a               b               6               d               e               f
// 50ns            a               b               7               d               e               f
// 55ns            a               b               8               d               e               f
// 60ns            a               b               9               d               e               f
// 65ns            a               b               a               d               e               f
// 70ns            a               b               b               d               e               f
// 75ns            a               b               c               d               e               f
// 80ns            a               b               d               d               e               f
// 85ns            a               b               e               d               e               f
// 90ns            a               b               f               d               e               f

module top_module (
	input [3:0] a,
	input [3:0] b,
	input [3:0] c,
	input [3:0] d,
	input [3:0] e,
	output reg [3:0] q
);

26: error: Unable to bind wire/reg/memory `f' in `top_module'
21: error: Unable to bind wire/reg/memory `f' in `top_module'
22: error: Unable to bind wire/reg/memory `f' in `top_module'
16: error: Unable to bind wire/reg/memory `f' in `top_module'
18: error: Unable to bind wire/reg/memory `f' in `top_module'
23: error: Unable to bind wire/reg/memory `f' in `top_module'
25: error: Unable to bind wire/reg/memory `f' in `top_module'
24: error: Unable to bind wire/reg/memory `f' in `top_module'
20: error: Unable to bind wire/reg/memory `f' in `top_module'
17: error: Unable to bind wire/reg/memory `f' in `top_module'
15: error: Unable to bind wire/reg/memory `f' in `top_module'
19: error: Unable to bind wire/reg/memory `f' in `top_module'


43: error: Unable to bind wire/reg/memory `f' in `top_module'
41: error: Unable to bind wire/reg/memory `f' in `top_module'
22: error: Unable to bind wire/reg/memory `f' in `top_module'
16: error: Unable to bind wire/reg/memory `f' in `top_module'
18: error: Unable to bind wire/reg/memory `f' in `top_module'
40: error: Unable to bind wire/reg/memory `f' in `top_module'
38: error: Unable to bind wire/reg/memory `f' in `top_module'
21: error: Unable to bind wire/reg/memory `f' in `top_module'
33: error: Unable to bind wire/reg/memory `f' in `top_module'
23: error: Unable to bind wire/reg/memory `f' in `top_module'
32: error: Unable to bind wire/reg/memory `f' in `top_module'
25: error: Unable to bind wire/reg/memory `f' in `top_module'
35: error: Unable to bind wire/reg/memory `f' in `top_module'
15: error: Unable to bind wire/reg/memory `f' in `top_module'
26: error: Unable to bind wire/reg/memory `f' in `top_module'
28: error: Unable to bind wire/reg/memory `f' in `top_module'
42: error: Unable to bind wire/reg/memory `f' in `top_module'
24: error: Unable to bind wire/reg/memory `f' in `top_module'
36: error: Unable to bind wire/reg/memory `f' in `top_module'
17: error: Unable to bind wire/reg/memory `f' in `top_module'
19: error: Unable to bind wire/reg/memory `f' in `top_module'
27: error: Unable to bind wire/reg/memory `f' in `top_module'
37: error: Unable to bind wire/reg/memory `f' in `top_module'
29: error: Unable to bind wire/reg/memory `f' in `top_module'
39: error: Unable to bind wire/reg/memory `f' in `top_module'
30: error: Unable to bind wire/reg/memory `f' in `top_module'
20: error: Unable to bind wire/reg/memory `f' in `top_module'
34: error: Unable to bind wire/reg/memory `f' in `top_module'
31: error: Unable to bind wire/reg/memory `f' in `top_module'


The "game" is played on a two-dimensional grid of cells, where each cell is either 1 (alive) or 0 (dead). At each time step, each cell changes state depending on how many neighbours it has:
// (1) 0-1 neighbour: Cell becomes 0.
// (2) 2 neighbours: Cell state does not change.
// (3) 3 neighbours: Cell becomes 1.
// (4) 4+ neighbours: Cell becomes 0.
// The game is formulated for an infinite grid. In this circuit, we will use a 16x16 grid. To make things more interesting, we will use a 16x16 toroid, where the sides wrap around to the other side of the grid. For example, the corner cell (0,0) has 8 neighbours: (15,1), (15,0), (15,15), (0,1), (0,15), (1,1), (1,0), and (1,15). The 16x16 grid is represented by a length 256 vector, where each row of 16 cells is represented by a sub-vector: q[15:0] is row 0, q[31:16] is row 1, etc.
// (1) load: Loads data into q at the next clock edge, for loading initial state. Active high synchronous.
// (2) q: The 16x16 current state of the game, updated every clock cycle.
// The game state should advance by one timestep every clock cycle.

module top_module(
	input clk,
	input load,
	input [255:0] data,
	output reg [255:0] q);
 reg [15:0] row;
         reg [15:0] col;
         reg [15:0] neighbours;
         reg [15:0] new_state;

         always @(posedge clk) begin
             if (load) begin
                 q <= data;
                 row <= 0;
                 col <= 0;
             end else begin
                 if (col == 15) begin
                     col <= 0;
                     row <= row + 1;
                 end else begin
                     col <= col + 1;
                 end

                 neighbours <= (q[row][col-1:0] + q[row][col+1:0] + q[(row-1)&15][col] + q[(row+1)&15][col] + q[(row-1)&15][col-1:0] + q[(row-1)&15][col+1:0] + q[(row+1)&15][col-1:0] + q[(row+1)&15][col+1:0]) % 2;

                 if (neighbours == 2) begin
                     new_state <= q[row][col];
                 end else if (neighbours == 3) begin
                     new_state <= 1;
                 end else begin
                     new_state <= 0;
                 end

                 q[row][col] <= new_state;
             end
         end

         always @(posedge clk) begin
             if (load) begin
                 row <= 0;
                 col <= 0;
             end else begin
                 if (col == 15) begin
                     col <= 0;
                     row <= row + 1;
                 end else begin
                     col <= col + 1;
                 end

                 neighbours <= (q[row][col-1:0] + q[row][col+1:0] + q[(row-1)&15][col] + q[(row+1)&15][col] + q[(row-1)&15][col-1:0] + q[(row-1)&15][col+1:0] + q[(row+1)&15][col-1:0] + q[(row+1)&15][col+1:0]) % 2;

                 if (neighbours == 2) begin
                     new_state <= q[row][col];
                 end else if (neighbours == 3) begin
                     new_state <= 1;
                 end else begin
                     new_state <= 0;
                 end

                 q[row][col] <= new_state;
             end
         end
endmodule

50: error: A reference to a net or variable (`row') is not allowed in a constant expression.
50: error: A reference to a net or variable (`col') is not allowed in a constant expression.
34: error: the number of indices (2) is greater than the number of dimensions (1).
27: error: Array index expressions must be constant here.
53: error: A reference to a net or variable (`row') is not allowed in a constant expression.
24: error: A reference to a net or variable (`col') is not allowed in a constant expression.
60: error: the number of indices (2) is greater than the number of dimensions (1).
50:      : The msb expression violates that rule: (col)+('sd1)
53: error: Array index expressions must be constant here.
24: error: A reference to a net or variable (`row') is not allowed in a constant expression.
24:      : The msb expression violates that rule: (col)-('sd1)
50: error: Part select expressions must be constant integral values.
24: error: Part select expressions must be constant integral values.
24:      : The msb expression violates that rule: (col)+('sd1)
27: error: A reference to a net or variable (`row') is not allowed in a constant expression.
50:      : The msb expression violates that rule: (col)-('sd1)
24: error: Array index expressions must be constant here.
50: error: Array index expressions must be constant here.


module top_module(
	input clk,
	input load,
	input [255:0] data,
	output reg [255:0] q);
 reg [255:0] q_next;
         reg [255:0] neighbours;
         reg [7:0] x, y;
         integer i, j, k, l;

         always @ (posedge clk) begin
             if (load) begin
                 q <= data;
             end else begin
                 q_next <= q;
                 for (i = 0; i < 256; i = i + 1) begin
                     x = i % 16;
                     y = i / 16;
                     neighbours = 0;
                     for (k = -1; k <= 1; k = k + 1) begin
                         for (l = -1; l <= 1; l = l + 1) begin
                             if (k == 0 && l == 0) begin
                                 continue;
                             end else begin
                                 j = (y + k + 16) % 16;
                                 j = (x + l + 16) % 16;
                                 neighbours = neighbours | (q[j + 16 * j] << (k + 1) * 4 + (l + 1) * 4);
                             end
                         end
                     end
                     if (neighbours[0:1] == 0 || neighbours[0:1] == 2 || neighbours[0:1] == 4) begin
                         q_next[i] = 0;
                     end else if (neighbours[0:1] == 1 || neighbours[0:1] == 3 || neighbours[0:1] == 5) begin
                         q_next[i] = 1;
                     end
                 end
                 q <= q_next;
             end
         end
     endmodule

33: error: part select neighbours[0:1] is out of order.
31: error: part select neighbours[0:1] is out of order.


Build a 4-bit binary counter that counts from 0 through 15, inclusive, with a period of 16. The reset input is active high synchronous, and should reset the counter to 0.

module top_module(
	input clk,
	input reset,
	output reg [3:0] q);
 counter counter_inst(
            .clk(clk),
            .reset(reset),
            .q(q));

endmodule


Make a decade counter that counts 1 through 10, inclusive. The reset input is active high synchronous, and should reset the counter to 1.

module top_module(
	input clk,
	input reset,
	output reg [3:0] q);

        always @(posedge clk) begin
          if (reset) begin
            q <= 4'b0001;
          end else if (q == 4'b1010) begin
            q <= 4'b0001;
          end else begin
            q <= q + 1;
          end
        end

        assign q_out = q;

      endmodule

16: warning: implicit definition of wire 'q_out'.


Create a set of counters suitable for use as a 12-hour clock (with am/pm indicator). Your counters are clocked by a fast-running clk, with a pulse on ena whenever your clock should increment (i.e., once per second, while "clk" is much faster than once per second). The signal "pm" is asserted if the clock is PM, or is otherwise AM. hh, mm, and ss are two BCD (Binary-Coded Decimal) digits each for hours (01-12), minutes (00-59), and seconds (00-59). Reset is the active high synchronous signal that resets the clock to "12:00 AM." Reset has higher priority than enable and can occur even when not enabled.

module top_module(
	input clk,
	input reset,
	input ena,
	output reg pm,
	output reg [7:0] hh,
	output reg [7:0] mm,
	output reg [7:0] ss);
 reg [5:0] counter;
         reg [5:0] counter_100;
         reg [5:0] counter_1000;

         always @(posedge clk) begin
            if (reset) begin
               counter <= 6'd0;
               counter_100 <= 6'd0;
               counter_1000 <= 6'd0;
               pm <= 1'b0;
               hh <= 8'd12;
               mm <= 8'd0;
               ss <= 8'd0;
            end
            else if (ena) begin
               counter <= counter + 6'd1;
               if (counter == 6'd99) begin
                  counter <= 6'd0;
                  counter_100 <= counter_100 + 6'd1;
               end
               if (counter_100 == 6'd99) begin
                  counter_100 <= 6'd0;
                  counter_1000 <= counter_1000 + 6'd1;
               end
               if (counter_1000 == 6'd5) begin
                  counter_1000 <= 6'd0;
                  if (pm) begin
                     if (hh == 8'd12) begin
                        hh <= 8'd1;
                     end
                     else begin
                        hh <= hh + 8'd1;
                     end
                     pm <= 1'b0;
                  end
                  else begin
                     if (hh == 8'd12) begin
                        hh <= 8'd1;
                        pm <= 1'b1;
                     end
                     else begin
                        hh <= hh + 8'd1;
                     end
                  end
               end
               if (ss == 8'd59) begin
                  ss <= 8'd0;
                  if (mm == 8'd59) begin
                     mm <= 8'd0;
                  end
                  else begin
                     mm <= mm + 8'd1;
                  end
               end
               else begin
                  ss <= ss + 8'd1;
               end
            end
         end
      endmodule

29: warning: Numeric constant truncated to 6 bits.
25: warning: Numeric constant truncated to 6 bits.


module top_module(
	input clk,
	input reset,
	input ena,
	output reg pm,
	output reg [7:0] hh,
	output reg [7:0] mm,
	output reg [7:0] ss);

        reg [5:0] count_ss;
        reg [5:0] count_mm;
        reg [4:0] count_hh;
        reg [1:0] count_pm;

        always @(posedge clk) begin
            if (reset) begin
                count_ss <= 0;
                count_mm <= 0;
                count_hh <= 0;
                count_pm <= 0;
                pm <= 0;
                hh <= 8'b00001010; // 10 in BCD
                mm <= 8'b00000000; // 00 in BCD
                ss <= 8'b00000000; // 00 in BCD
            end else if (ena) begin
                if (count_ss == 59) begin
                    count_ss <= 0;
                    if (count_mm == 59) begin
                        count_mm <= 0;
                        if (count_hh == 11) begin
                            count_hh <= 0;
                            count_pm <= 1;
                        end else begin
                            count_hh <= count_hh + 1;
                            count_pm <= 0;
                        end
                    end else begin
                        count_mm <= count_mm + 1;
                    end
                end else begin
                    count_ss <= count_ss + 1;
                end
                pm <= count_pm;
                hh <= (count_hh == 0) ? 8'b00001010 : // 10 in BCD
                     (count_hh == 1) ? 8'b00001100 : // 12 in BCD
                     (count_hh == 2) ? 8'b00001101 : // 13 in BCD
                     (count_hh == 3) ? 8'b00001110 : // 14 in BCD
                     (count_hh == 4) ? 8'b00001111 : // 15 in BCD
                     (count_hh == 5) ? 8'b00010000 : // 16 in BCD
                     (count_hh == 6) ? 8'b00010001 : // 17 in BCD
                     (count_hh == 7) ? 8'b00010010 : // 18 in BCD
                     (count_hh == 8) ? 8'b00010011 : // 19 in BCD
                     (count_hh == 9) ? 8'b00010100 : // 20 in BCD
                     (count_hh == 10) ? 8'b00010101 : // 21 in BCD
                     (count_hh == 11) ? 8'b00010110 : // 22 in BCD
                     8'b00000000; // 00 in BCD
                mm <= (count_mm < 10) ? {1'b0, count_mm} : // 00-09 in BCD
                     (count_mm < 20) ? {1'b1, count_mm - 10} : // 10-19 in BCD
                     (count_mm < 30) ? {1'b1, count_mm - 20} : // 20-29 in BCD
                     (count_mm < 40) ? {1'b1, count_mm - 30} : // 30-39 in BCD
                     (count_mm < 50) ? {1'b1, count_mm - 40} : // 40-49 in BCD
                     (count_mm < 59) ? {1'b1, count_mm - 50} : // 50-59 in BCD
                     8'b00000000; // 00 in BCD
                ss <= (count_ss < 10) ? {1'b0, count_ss} : // 00-09 in BCD
                     (count_ss < 20) ? {1'b1, count_ss - 10} : // 10-19 in BCD
                     (count_ss < 30) ? {1'b1, count_ss - 20} : // 20-29 in BCD
                     (count_ss < 40) ? {1'b1, count_ss - 30} : // 30-39 in BCD
                     (count_ss < 50) ? {1'b1, count_ss - 40} : // 40-49 in BCD
                     (count_ss < 59) ? {1'b1, count_ss - 50} : // 50-59 in BCD
                     8'b00000000; // 00 in BCD
            end
        end
    endmodule

65: error: Concatenation operand "(count_ss)-('sd10)" has indefinite width.
58: error: Concatenation operand "(count_mm)-('sd10)" has indefinite width.


Build a 4-digit BCD (binary-coded decimal) counter. Each decimal digit is encoded using 4 bits: q[3:0] is the ones digit, q[7:4] is the tens digit, etc. For digits [3:1], also output an enable signal indicating when each of the upper three digits should be incremented. Include a synchronous active-high reset.

module top_module(
	input clk,
	input reset,
	output [3:1] ena,
	output reg [15:0] q);
 // Internal registers for holding intermediate values of the counter
         reg [3:0] ones;
         reg [3:0] tens;
         reg [3:0] hundreds;
         reg [3:0] thousands;

         // Counter increment logic
         always @(posedge clk) begin
            if (reset) begin
               ones <= 4'b0000;
               tens <= 4'b0000;
               hundreds <= 4'b0000;
               thousands <= 4'b0000;
            end else begin
               if (ones == 4'b1001) begin
                  ones <= 4'b0000;
                  ena[1] <= 1;
               end else begin
                  ones <= ones + 1;
                  ena[1] <= 0;
               end

               if (tens == 4'b1001) begin
                  tens <= 4'b0000;
                  ena[2] <= 1;
               end else begin
                  tens <= tens + 1;
                  ena[2] <= 0;
               end

               if (hundreds == 4'b1001) begin
                  hundreds <= 4'b0000;
                  ena[3] <= 1;
               end else begin
                  hundreds <= hundreds + 1;
                  ena[3] <= 0;
               end

               if (thousands == 4'b1001) begin
                  thousands <= 4'b0000;
               end else begin
                  thousands <= thousands + 1;
               end
            end
         end

         // Output register for storing the BCD counter value
         always @(posedge clk) begin
            if (reset) begin
               q <= 16'b0000000000000000;
            end else begin
               q <= {thousands, hundreds, tens, ones};
            end
         end

      endmodule

30: error: 'ena['sd2]' is not a valid l-value for a procedural assignment.
4:      : 'ena['sd1]' is declared here as a wire.
41: error: 'ena['sd3]' is not a valid l-value for a procedural assignment.
22: error: 'ena['sd1]' is not a valid l-value for a procedural assignment.
4:      : 'ena['sd2]' is declared here as a wire.
4:      : 'ena['sd3]' is declared here as a wire.
25: error: 'ena['sd1]' is not a valid l-value for a procedural assignment.
38: error: 'ena['sd3]' is not a valid l-value for a procedural assignment.
33: error: 'ena['sd2]' is not a valid l-value for a procedural assignment.


module top_module(
	input clk,
	input reset,
	output [3:1] ena,
	output reg [15:0] q);
 always @(posedge clk) begin
                if (reset) begin
                    q <= 16'b0;
                    ena <= 3'b0;
                end else begin
                    q <= q + 1;
                    if (q[15:12] == 4'b1001) begin
                        ena <= 3'b1;
                    end else begin
                        ena <= 3'b0;
                    end
                end
            end
        endmodule

15: error: 'ena' is not a valid l-value for a procedural assignment.
4:      : 'ena' is declared here as a wire.
9: error: 'ena' is not a valid l-value for a procedural assignment.
13: error: 'ena' is not a valid l-value for a procedural assignment.


Build a two-bit saturating counter. The counter increments (up to a maximum of 3) when train_valid = 1 and train_taken = 1. It decrements (down to a minimum of 0) when train_valid = 1 and train_taken = 0. When not training (train_valid = 0), the counter keeps its value unchanged. areset is a positive edge triggered asynchronous reset that resets the counter to weakly not-taken (2'b01). Output state[1:0] is the two-bit counter value.

module top_module(
    input clk,
    input areset,
    input train_valid,
    input train_taken,
    output logic [1:0] state
);
 always @ (posedge clk) begin
            if (areset) begin
                state <= 2'b01;
            end else if (train_valid == 1) begin
                if (train_taken == 1) begin
                    state <= (state == 2'b11) ? 2'b11 : state + 1;
                end else begin
                    state <= (state == 2'b00) ? 2'b00 : state - 1;
                end
            end
        end

        // If training is valid and not taken, counter cannot go below 0
        assign state = (train_valid == 1 && train_taken == 0 && state == 2'b00) ? 2'b00 : state;

        // If training is valid and taken, counter cannot go above 3
        assign state = (train_valid == 1 && train_taken == 1 && state == 2'b11) ? 2'b11 : state;

endmodule

24: error: Variable 'state' cannot have multiple drivers.
13: error: Cannot perform procedural assignment to variable 'state' because it is also continuously assigned.
15: error: Cannot perform procedural assignment to variable 'state' because it is also continuously assigned.
10: error: Cannot perform procedural assignment to variable 'state' because it is also continuously assigned.


module top_module(
    input clk,
    input areset,
    input train_valid,
    input train_taken,
    output logic [1:0] state
);
 sat_counter #( .AWIDTH(2) ) sat_cntr( .clk(clk), .areset(areset), .train_valid(train_valid), .train_taken(train_taken), .state(state) );

endmodule

8: error: Unknown module type: sat_counter


Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is active high synchronous, and should reset the counter to 0. We want to be able to pause the counter rather than always incrementing every clock cycle, so the "slowena" input if high indicates when the counter should increment.

module top_module(
	input clk,
	input slowena,
	input reset,
	output reg [3:0] q);
 always @(posedge clk) begin
            if (reset) begin
                q <= 4'b0000;
            end
            else if (slowena) begin
                q <= q + 1;
            end
        end

        assign q = q;

        always @(posedge clk) begin
            if (reset) begin
                q <= 4'b0000;
            end
            else if (slowena) begin
                q <= q + 1;
            end
        end

endmodule

8: error: Cannot perform procedural assignment to variable 'q' because it is also continuously assigned.
11: error: Cannot perform procedural assignment to variable 'q' because it is also continuously assigned.
22: error: Cannot perform procedural assignment to variable 'q' because it is also continuously assigned.
19: error: Cannot perform procedural assignment to variable 'q' because it is also continuously assigned.


module top_module(
	input clk,
	input slowena,
	input reset,
	output reg [3:0] q);
 reg [4:0] counter = 0;
         reg [3:0] next_q;

         always @(posedge clk or posedge reset) begin
             if (reset) begin
                 counter <= 0;
             end
             else if (slowena) begin
                 counter <= counter + 1;
             end
         end

         always @(counter) begin
             case(counter)
                 0: next_q = 4'b0000;
                 1: next_q = 4'b0001;
                 2: next_q = 4'b0010;
                 3: next_q = 4'b0011;
                 4: next_q = 4'b0100;
                 5: next_q = 4'b0101;
                 6: next_q = 4'b0110;
                 7: next_q = 4'b0111;
                 8: next_q = 4'b1000;
                 9: next_q = 4'b1001;
                 default: next_q = 4'b0000;
             endcase
         end

         always @(posedge clk or posedge reset) begin
             if (reset) begin
                 q <= 0;
             end
             else if (slowena) begin
                 q <= next_q;
             end
         end

         // Output a pulse every time the counter increments
         reg pulse = 0;
         always @(posedge clk or posedge reset) begin
             if (reset) begin
                 pulse <= 0;
             end
             else if (counter > 0) begin
                 pulse <= 1;
             end
         end

         // Output a 1 when the counter is at a multiple of 2
         reg mult2 = 0;
         always @(posedge clk or posedge reset) begin
             if (reset) begin
                 mult2 <= 0;
             end
             else if (counter % 2 == 0) begin
                 mult2 <= 1;
             end
         end

         // Output a 1 when the counter is at a multiple of 3
         reg mult3 = 0;
         always @(posedge clk or posedge reset) begin
             if (reset) begin
                 mult3 <= 0;
             end
             else if (counter % 3 == 0) begin
                 mult3 <= 1;
             end
         end

         // Output a 1 when the counter is at a multiple of 4
         reg mult4 = 0;
         always @(posedge clk or posedge reset) begin
             if (reset) begin
                 mult4 <= 0;
             end
             else if (counter % 4 == 0) begin
                 mult4 <= 1;
             end
         end

         // Output a 1 when the counter is at a multiple of 5
         reg mult5 = 0;
         always @(posedge clk or posedge reset) begin
             if (reset) begin
                 mult5 <= 0;
             end
             else if (counter % 5 == 0) begin
                 mult5 <= 1;
             end
         end

         // Output a 1 when the counter is at a multiple of 6
         reg mult6 = 0;
         always @(posedge clk or posedge reset) begin
             if (reset) begin
                 mult6 <= 0;
             end
             else if (counter % 6 == 0) begin
                 mult6 <= 1;
             end
         end

         // Output a 1 when the counter is at a multiple of 7
         reg mult7 = 0;
         always @(posedge clk or posedge reset) begin
             if (reset) begin
                 mult7 <= 0;
             end
             else if (counter % 7 == 0) begin
                 mult7 <= 1;
             end
         end

         // Output a 1 when the counter is at a multiple of 8
         reg mult8 = 0;
         always @(posedge clk or posedge reset) begin
             if (reset) begin
                 mult8 <= 0;
             end
             else if (counter % 8 == 0) begin
                 mult8 <= 1;
             end
         end

         // Output a 1 when the counter is at a multiple of 9
         reg mult9 = 0;
         always @(posedge clk or posedge reset) begin
             if (reset) begin
                 mult9 <= 0;
             end
             else if (counter % 9 == 0) begin
                 mult9 <= 1;
             end
         end

         // Output a 1 when the counter is at a multiple of 10
         reg mult10 = 0;
         always @(posedge clk or posedge reset) begin
             if (reset) begin
                 mult10 <= 0;
             end
             else if (counter % 10 == 0) begin
                 mult10 <= 1;
             end
         end

         // Output all of the multiples
         assign pulse_out = pulse;
         assign mult2_out = mult2;
         assign mult3_out = mult3;
         assign mult4_out = mult4;
         assign mult5_out = mult5;
         assign mult6_out = mult6;
         assign mult7_out = mult7;
         assign mult8_out = mult8;
         assign mult9_out = mult9;
         assign mult10_out = mult10;

         // Output the current counter value
         assign out = counter;

         // Output a 1 when the counter is at 9
         assign end_out = (counter == 9);

         // Output a 1 when the counter is at 0
         assign begin_out = (counter == 0);

         // Output a 1 when the pulse is active
         assign pulse_out = pulse;

         // Output a 1 when the counter is at a multiple of 10
         assign mult10_out = (counter % 10 == 0);

         // Output a 1 when the counter is at a multiple of 9
         assign mult9_out = (counter % 9 == 0);

         // Output a 1 when the counter is at a multiple of 8
         assign mult8_out = (counter % 8 == 0);

         // Output a 1 when the counter is at a multiple of 7
         assign mult7_out = (counter % 7 == 0);

         // Output a 1 when the counter is at a multiple of 6
         assign mult6_out = (counter % 6 == 0);

         // Output a 1 when the counter is at a multiple of 5
         assign mult5_out = (counter % 5 == 0);

         // Output a 1 when the counter is at a multiple of 4
         assign mult4_out = (counter % 4 == 0);

         // Output a 1 when the counter is at a multiple of 3
         assign mult3_out = (counter % 3 == 0);

         // Output a 1 when the counter is at a multiple of 2
         assign mult2_out = (counter % 2 == 0);

         // Output a 1 when the counter is at 9
         assign end_out = (counter == 9);

         // Output a 1 when the counter is at 0
         assign begin_out = (counter == 0);
      endmodule

161: warning: implicit definition of wire 'mult8_out'.
172: warning: implicit definition of wire 'begin_out'.
154: warning: implicit definition of wire 'pulse_out'.
155: warning: implicit definition of wire 'mult2_out'.
157: warning: implicit definition of wire 'mult4_out'.
163: warning: implicit definition of wire 'mult10_out'.
158: warning: implicit definition of wire 'mult5_out'.
156: warning: implicit definition of wire 'mult3_out'.
162: warning: implicit definition of wire 'mult9_out'.
166: warning: implicit definition of wire 'out'.
160: warning: implicit definition of wire 'mult7_out'.
169: warning: implicit definition of wire 'end_out'.
159: warning: implicit definition of wire 'mult6_out'.


Create a single D flip-flop.

module top_module(
	input clk,
	input d,
	output reg q);
 clock_divider clk_div(
           .clk(clk),
           .clk_out(clk_out)
         );

         always @(posedge clk_out) begin
           q <= d;
         end

	endmodule

5: error: Unknown module type: clock_divider
7: warning: implicit definition of wire 'clk_out'.


Create a single D flip-flop.

module top_module(
	input clk,
	input d,
	output reg q);

        reg q_next;

        always @(posedge clk) begin
            q_next <= d;
        end

        // Asynchronous load
        always @(d) begin
            q <= d;
        end

        // Output
        assign q = q_next;

    endmodule

14: error: Cannot perform procedural assignment to variable 'q' because it is also continuously assigned.