Module A implements the boolean function z = (x^y) & x.

// Module B can be described by the following simulation waveform:

// time            x               y               z
// 0ns             0               0               1
// 5ns             0               0               1
// 10ns            0               0               1
// 15ns            0               0               1
// 20ns            0               0               1
// 25ns            1               0               0
// 30ns            1               0               0
// 35ns            0               1               0
// 40ns            0               1               0
// 45ns            1               1               1
// 50ns            1               1               1
// 55ns            0               0               1
// 60ns            0               1               0
// 65ns            0               1               0
// 70ns            1               1               1
// 75ns            0               1               0
// 80ns            0               1               0
// 85ns            0               1               0
// 90ns            1               0               0

// Now consider a top-level that uses two A submodules and two B submodules. The first input of all four submodules is connect to input 'x', and the second input of all four submodules is connected to 'y'. The output of the first A submodule is connected to a two-input OR, along with the output of the first B submodule. The second pair of A and B submodules is similarly connected to an AND gate. The output of the OR and the AND is connected to an XOR, whose output is 'z'.

// Implement this circuit in Verilog.

module top_module(
	input x,
	input y,
	output z);
 // Instantiate submodule A
         wire a_out1;
         wire a_out2;
         A a_inst1(.x(x), .y(y), .z1(a_out1), .z2(a_out2));

         // Instantiate submodule B
         wire b_out;
         B b_inst(.x(x), .y(y), .z(b_out));

         // Connect inputs to submodules
         assign a_inst1.x = x;
         assign a_inst1.y = y;
         assign b_inst.x = x;
         assign b_inst.y = y;

         // Perform logical operations
         assign z = (a_out1 | b_out) & (a_out2 & b_out);

endmodule

12: error: Unknown module type: B
8: error: Unknown module type: A


module top_module(
	input x,
	input y,
	output z);
 // Instantiate two A submodules and two B submodules
         A a1(x, y, z1);
         A a2(x, y, z2);
         B b1(x, y, z3);
         B b2(x, y, z4);

         // Connect the outputs of the A submodules to an OR gate
         assign or_out = z1 | z2;

         // Connect the outputs of the B submodules to an AND gate
         assign and_out = z3 & z4;

         // Connect the outputs of the OR and AND gates to an XOR gate
         assign z = or_out ^ and_out;

	endmodule

6: warning: implicit definition of wire 'z1'.
8: warning: implicit definition of wire 'z3'.
7: warning: implicit definition of wire 'z2'.
9: error: Unknown module type: B
7: error: Unknown module type: A
8: error: Unknown module type: B
15: warning: implicit definition of wire 'and_out'.
6: error: Unknown module type: A
12: warning: implicit definition of wire 'or_out'.
9: warning: implicit definition of wire 'z4'.


The module can be described by the following simulation waveform:

// time            x               y               z
// 0ns             0               0               1
// 5ns             0               0               1
// 10ns            0               0               1
// 15ns            0               0               1
// 20ns            0               0               1
// 25ns            1               0               0
// 30ns            1               0               0
// 35ns            0               1               0
// 40ns            0               1               0
// 45ns            1               1               1
// 50ns            1               1               1
// 55ns            0               0               1
// 60ns            0               1               0
// 65ns            0               1               0
// 70ns            1               1               1
// 75ns            0               1               0
// 80ns            0               1               0
// 85ns            0               1               0
// 90ns            1               0               0

module top_module(
	input x,
	input y,
	output z);
 // Initial state of z is 1
         reg z = 1'b1;

         // Counter to keep track of time in current state
         reg [31:0] counter = 0;

         // State machine to handle input sequence
         always @(x or y) begin
              // Reset counter if in default state
              if (x == 0 && y == 0) begin
                   counter <= 0;
              end else begin
                   // Increment counter for current state
                   counter <= counter + 1;
              end

              // Check for single input high
              if ((x == 1 && y == 0) || (x == 0 && y == 1)) begin
                   z <= 1'b0;
              end else if (x == 1 && y == 1) begin
                   // Reset counter if both inputs are high
                   counter <= 0;
                   z <= 1'b1;
              end else begin
                   // Maintain current state if no conditions met
                   z <= z;
              end
         end

         // Reset z to 1 after 20ns of default state
         always @(counter) begin
              if (counter >= 20) begin
                   z <= 1'b1;
              end
         end

endmodule

4:      : It was declared here as a net.
6: error: 'z' has already been declared in this scope.


module top_module(
	input x,
	input y,
	output z);
// Initial state of z is 1
         reg z = 1'b1;

         // Counter to keep track of time in current state
         reg [31:0] counter = 0;

         // State machine to handle input sequence
         always @(x or y) begin
              // Reset counter if in default state
              if (x == 0 && y == 0) begin
                   counter <= 0;
              end else begin
                   // Increment counter for current state
                   counter <= counter + 1;
              end

              // Check for single input high
              if ((x == 1 && y == 0) || (x == 0 && y == 1)) begin
                   z <= 1'b0;
              end else if (x == 1 && y == 1) begin
                   // Reset counter if both inputs are high
                   counter <= 0;
                   z <= 1'b1;
              end else begin
                   // Maintain current state if no conditions met
                   z <= z;
              end
         end

         // Reset z to 1 after 20ns of default state
         always @(counter) begin
              if (counter >= 20) begin
                   z <= 1'b1;
              end
         end

endmodule


Create a 1-bit wide, 256-to-1 multiplexer. The 256 inputs are all packed into a single 256-bit input vector. sel=0 should select in[0], sel=1 selects bits in[1], sel=2 selects bits in[2], etc.

module top_module (
	input [255:0] in,
	input [7:0] sel,
	output  out
);
 assign out = insel;

endmodule

6: error: Unable to bind wire/reg/memory `insel' in `top_module'
6: error: Unable to elaborate r-value: insel


4:      : It was declared here as a net.
6: error: 'out' has already been declared in this scope.


Create a 4-bit wide, 256-to-1 multiplexer. The 256 4-bit inputs are all packed into a single 1024-bit input vector. sel=0 should select bits in[3:0], sel=1 selects bits in[7:4], sel=2 selects bits in[11:8], etc.

module top_module (
	input [1023:0] in,
	input [7:0] sel,
	output [3:0] out
);
 assign out = in[(sel*4)+3 : (sel*4)];

endmodule

6: error: Part select expressions must be constant integral values.
6:      : The msb expression violates that rule: ((sel)*('sd4))+('sd3)
6: error: A reference to a net or variable (`sel') is not allowed in a constant expression.
6:      : The lsb expression violates that rule: (sel)*('sd4)


module top_module (
	input [1023:0] in,
	input [7:0] sel,
	output [3:0] out
);
 assign out = in[(sel*4)+3:(sel*4)];

endmodule


Create a one-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When sel=1, choose b.

module top_module (
	input a,
	input b,
	input sel,
	output out
);
always @(*) begin
	if (sel == 1'b0)
		out = a;
	else
		out = b;
end

endmodule

11: error: 'out' is not a valid l-value for a procedural assignment.
5:      : 'out' is declared here as a wire.
9: error: 'out' is not a valid l-value for a procedural assignment.


Create a 2-1 multiplexer. When sel=0, choose a. When sel=1, choose b.

module top_module (
	input [99:0] a,
	input [99:0] b,
	input sel,
	output [99:0] out
);
 always @(*) begin
            if (sel == 1'b0) begin
                out = a;
            end else begin
                out = b;
            end
         end

endmodule


Create a module that implements a NOR gate.

module top_module(
	input a,
	input b,
	output out
);
 sky130_fd_sc_hd__nor2b base(
	     .A(a),
	     .B(b),
	     .OUT(out)
        );

        endmodule

6: error: Unknown module type: sky130_fd_sc_hd__nor2b


module top_module(
	input a,
	input b,
	output out
);
 sky130_fd_sc_hdll__nor2b nor_gate(
         .A(a),
         .B(b),
         .Y(out)
         );

endmodule

6: error: Unknown module type: sky130_fd_sc_hdll__nor2b


Create a module that implements a NOT gate.

module top_module(
	input in,
	output out
);
reg out;

always @(posedge clk or posedge reset)
begin
	if(reset)
		out <= 1'b0;
	else
		out <= w;
end

assign z = out;

endmodule

15: warning: implicit definition of wire 'z'.
5: error: 'out' has already been declared in this scope.
3:      : It was declared here as a net.


A "population count" circuit counts the number of '1's in an input vector. Build a population count circuit for a 255-bit input vector.

module top_module (
	input [254:0] in,
	output reg [7:0] out
);
 // 255-bit input vector
         // 8-bit output vector

         // 8-bit adder for each 32-bit chunk
         wire [7:0] adder0, adder1, adder2, adder3, adder4, adder5, adder6, adder7;

         // 32-bit chunks of the input vector
         wire [31:0] chunk0, chunk1, chunk2, chunk3, chunk4, chunk5, chunk6, chunk7;

         // 8-bit chunks of the output vector
         wire [7:0] chunk0_out, chunk1_out, chunk2_out, chunk3_out, chunk4_out, chunk5_out, chunk6_out, chunk7_out;

         // Split the input vector into 8 32-bit chunks
         assign chunk0 = in[31:0];
         assign chunk1 = in[63:32];
         assign chunk2 = in[95:64];
         assign chunk3 = in[127:96];
         assign chunk4 = in[159:128];
         assign chunk5 = in[191:160];
         assign chunk6 = in[223:192];
         assign chunk7 = in[255:224];

         // Count the number of '1's in each 32-bit chunk
         assign chunk0_out = chunk0 ^ (chunk0 >> 1);
         assign chunk1_out = chunk1 ^ (chunk1 >> 1);
         assign chunk2_out = chunk2 ^ (chunk2 >> 1);
         assign chunk3_out = chunk3 ^ (chunk3 >> 1);
         assign chunk4_out = chunk4 ^ (chunk4 >> 1);
         assign chunk5_out = chunk5 ^ (chunk5 >> 1);
         assign chunk6_out = chunk6 ^ (chunk6 >> 1);
         assign chunk7_out = chunk7 ^ (chunk7 >> 1);

         // Add the counts from each 32-bit chunk
         assign adder0 = chunk0_out[0] + chunk1_out[0] + chunk2_out[0] + chunk3_out[0] + chunk4_out[0] + chunk5_out[0] + chunk6_out[0] + chunk7_out[0];
         assign adder1 = chunk0_out[1] + chunk1_out[1] + chunk2_out[1] + chunk3_out[1] + chunk4_out[1] + chunk5_out[1] + chunk6_out[1] + chunk7_out[1];
         assign adder2 = chunk0_out[2] + chunk1_out[2] + chunk2_out[2] + chunk3_out[2] + chunk4_out[2] + chunk5_out[2] + chunk6_out[2] + chunk7_out[2];
         assign adder3 = chunk0_out[3] + chunk1_out[3] + chunk2_out[3] + chunk3_out[3] + chunk4_out[3] + chunk5_out[3] + chunk6_out[3] + chunk7_out[3];
         assign adder4 = chunk0_out[4] + chunk1_out[4] + chunk2_out[4] + chunk3_out[4] + chunk4_out[4] + chunk5_out[4] + chunk6_out[4] + chunk7_out[4];
         assign adder5 = chunk0_out[5] + chunk1_out[5] + chunk2_out[5] + chunk3_out[5] + chunk4_out[5] + chunk5_out[5] + chunk6_out[5] + chunk7_out[5];
         assign adder6 = chunk0_out[6] + chunk1_out[6] + chunk2_out[6] + chunk3_out[6] + chunk4_out[6] + chunk5_out[6] + chunk6_out[6] + chunk7_out[6];
         assign adder7 = chunk0_out[7] + chunk1_out[7] + chunk2_out[7] + chunk3_out[7] + chunk4_out[7] + chunk5_out[7] + chunk6_out[7] + chunk7_out[7];

         // Output the sum of the counts from each 32-bit chunk
         assign out = adder0 + adder1 + adder2 + adder3 + adder4 + adder5 + adder6 + adder7;

endmodule

25: warning: Part select [255:224] is selecting after the vector in[254:0].
25:        : Replacing the out of bound bits with 'bx.


module top_module (
	input [254:0] in,
	output reg [7:0] out
);
 // 255-bit input vector
         // 8-bit output vector

         // 8-bit adder for each 32-bit chunk
         wire [7:0] adder_out [7:0];

         // 32-bit chunks of the input vector
         wire [31:0] chunk [7:0];

         // Split the input vector into 32-bit chunks
         assign chunk[0] = in[31:0];
         assign chunk[1] = in[63:32];
         assign chunk[2] = in[95:64];
         assign chunk[3] = in[127:96];
         assign chunk[4] = in[159:128];
         assign chunk[5] = in[191:160];
         assign chunk[6] = in[223:192];
         assign chunk[7] = in[255:224];

         // Add up the '1's in each chunk
         assign adder_out[0] = chunk[0] + chunk[1] + chunk[2] + chunk[3] + chunk[4] + chunk[5] + chunk[6] + chunk[7];
         assign adder_out[1] = chunk[8] + chunk[9] + chunk[10] + chunk[11] + chunk[12] + chunk[13] + chunk[14] + chunk[15];
         assign adder_out[2] = chunk[16] + chunk[17] + chunk[18] + chunk[19] + chunk[20] + chunk[21] + chunk[22] + chunk[23];
         assign adder_out[3] = chunk[24] + chunk[25] + chunk[26] + chunk[27] + chunk[28] + chunk[29] + chunk[30] + chunk[31];
         assign adder_out[4] = chunk[32] + chunk[33] + chunk[34] + chunk[35] + chunk[36] + chunk[37] + chunk[38] + chunk[39];
         assign adder_out[5] = chunk[40] + chunk[41] + chunk[42] + chunk[43] + chunk[44] + chunk[45] + chunk[46] + chunk[47];
         assign adder_out[6] = chunk[48] + chunk[49] + chunk[50] + chunk[51] + chunk[52] + chunk[53] + chunk[54] + chunk[55];
         assign adder_out[7] = chunk[56] + chunk[57] + chunk[58] + chunk[59] + chunk[60] + chunk[61] + chunk[62] + chunk[63];

         // Output the sum of the '1's in each chunk
         always @(*) begin
         // always block triggered whenever there is a change in any of the inputs
            out = adder_out[0] + adder_out[1] + adder_out[2] + adder_out[3] + adder_out[4] + adder_out[5] + adder_out[6] + adder_out[7];
         end

endmodule

32: warning: returning 'bx for out of bounds array access chunk[57].
26: warning: returning 'bx for out of bounds array access chunk[9].
32: warning: returning 'bx for out of bounds array access chunk[62].
28: warning: returning 'bx for out of bounds array access chunk[29].
26: warning: returning 'bx for out of bounds array access chunk[10].
26: warning: returning 'bx for out of bounds array access chunk[15].
26: warning: returning 'bx for out of bounds array access chunk[14].
30: warning: returning 'bx for out of bounds array access chunk[44].
30: warning: returning 'bx for out of bounds array access chunk[47].
31: warning: returning 'bx for out of bounds array access chunk[55].
31: warning: returning 'bx for out of bounds array access chunk[50].
32: warning: returning 'bx for out of bounds array access chunk[60].
28: warning: returning 'bx for out of bounds array access chunk[27].
37: warning: @* is sensitive to all 8 words in array 'adder_out'.
30: warning: returning 'bx for out of bounds array access chunk[42].
29: warning: returning 'bx for out of bounds array access chunk[38].
32: warning: returning 'bx for out of bounds array access chunk[59].
26: warning: returning 'bx for out of bounds array access chunk[13].
27: warning: returning 'bx for out of bounds array access chunk[21].
31: warning: returning 'bx for out of bounds array access chunk[54].
28: warning: returning 'bx for out of bounds array access chunk[28].
26: warning: returning 'bx for out of bounds array access chunk[11].
29: warning: returning 'bx for out of bounds array access chunk[33].
29: warning: returning 'bx for out of bounds array access chunk[35].
31: warning: returning 'bx for out of bounds array access chunk[48].
31: warning: returning 'bx for out of bounds array access chunk[52].
26: warning: returning 'bx for out of bounds array access chunk[12].
29: warning: returning 'bx for out of bounds array access chunk[34].
27: warning: returning 'bx for out of bounds array access chunk[17].
32: warning: returning 'bx for out of bounds array access chunk[61].
26: warning: returning 'bx for out of bounds array access chunk[8].
31: warning: returning 'bx for out of bounds array access chunk[53].
27: warning: returning 'bx for out of bounds array access chunk[22].
29: warning: returning 'bx for out of bounds array access chunk[39].
28: warning: returning 'bx for out of bounds array access chunk[31].
32: warning: returning 'bx for out of bounds array access chunk[63].
31: warning: returning 'bx for out of bounds array access chunk[49].
27: warning: returning 'bx for out of bounds array access chunk[20].
27: warning: returning 'bx for out of bounds array access chunk[16].
28: warning: returning 'bx for out of bounds array access chunk[30].
29: warning: returning 'bx for out of bounds array access chunk[32].
30: warning: returning 'bx for out of bounds array access chunk[40].
28: warning: returning 'bx for out of bounds array access chunk[26].
22: warning: Part select [255:224] is selecting after the vector in[254:0].
28: warning: returning 'bx for out of bounds array access chunk[25].
29: warning: returning 'bx for out of bounds array access chunk[36].
27: warning: returning 'bx for out of bounds array access chunk[23].
30: warning: returning 'bx for out of bounds array access chunk[41].
32: warning: returning 'bx for out of bounds array access chunk[56].
22:        : Replacing the out of bound bits with 'bx.
27: warning: returning 'bx for out of bounds array access chunk[18].
28: warning: returning 'bx for out of bounds array access chunk[24].
29: warning: returning 'bx for out of bounds array access chunk[37].
30: warning: returning 'bx for out of bounds array access chunk[45].
32: warning: returning 'bx for out of bounds array access chunk[58].
30: warning: returning 'bx for out of bounds array access chunk[43].
31: warning: returning 'bx for out of bounds array access chunk[51].
27: warning: returning 'bx for out of bounds array access chunk[19].
30: warning: returning 'bx for out of bounds array access chunk[46].


A "population count" circuit counts the number of '1's in an input vector. Build a population count circuit for a 3-bit input vector.

module top_module (
	input [2:0] in,
	output [1:0] out
);
 assign out = {in0 & in1 & in2, in0 & in1 | in0 & in2 | in1 & in2};

endmodule

5: error: Unable to bind wire/reg/memory `in0' in `top_module'
5: error: Unable to bind wire/reg/memory `in2' in `top_module'
5: error: Unable to elaborate r-value: {((in0)&(in1))&(in2), (((in0)&(in1))|((in0)&(in2)))|((in1)&(in2))}
5: error: Unable to bind wire/reg/memory `in1' in `top_module'
5: error: Concatenation/replication may not have zero width in this context.


module top_module (
	input [2:0] in,
	output [1:0] out
);
 assign out[1:0] = $popcount(in);

endmodule

5: error: System function $popcount not defined in system table or SFT file(s).
5: internal error: Failed to synthesize expression: $popcount(in[2:0])


Parity checking is often used as a simple method of detecting errors when transmitting data through an imperfect channel. Create a circuit that will compute a parity bit for a 8-bit byte (which will add a 9th bit to the byte). We will use "even" parity, where the parity bit is just the XOR of all 8 data bits.

module top_module (
	input [7:0] in,
	output parity
);
 parity_bit parity_bit_inst(
             .in(in),
             .parity(parity)
         );

endmodule

5: error: Unknown module type: parity_bit


Build a counter that counts from 0 to 999, inclusive, with a period of 1000 cycles. The reset input is active high synchronous, and should reset the counter to 0.

module top_module(
	input clk,
	input reset,
	output reg [9:0] q);
 assign q = (count == 999) ? 0 : count + 1;

      always @(posedge clk, posedge reset) begin
          if (reset)
              count <= 0;
          else if (count == 999)
              count <= 0;
          else
              count <= count + 1;
      end

endmodule

5: error: Unable to elaborate r-value: ((count)==('sd999))?('sd0):((count)+('sd1))
10: error: Unable to bind wire/reg/memory `count' in `top_module'
5: error: Unable to bind wire/reg/memory `count' in `top_module'
10: error: Unable to elaborate condition expression.
9: error: Could not find variable ``count'' in ``top_module''


module top_module(
	input clk,
	input reset,
	output reg [9:0] q);
 counter counter_inst (
	     .clk(clk),
	     .reset(reset),
	     .q(q));

        always @(posedge clk) begin
            if (reset) begin
                q <= 10'b0;
            end else if (q == 10'd999) begin
                q <= 10'b0;
            end else begin
                q <= q + 10'b1;
            end
        end

endmodule


We want to create a timer with one input that:

// (1) is started when a particular input pattern (1101) is detected,
// (2) shifts in 4 more bits to determine the duration to delay,
// (3) waits for the counters to finish counting, and
// (4) notifies the user and waits for the user to acknowledge the timer.

// The serial data is available on the data input pin. When the pattern 1101 is received, the circuit must then shift in the next 4 bits, most-significant-bit first. These 4 bits determine the duration of the timer delay, referred to as delay[3:0]. After that, the state machine asserts its counting output to indicate it is counting. Once the 1101 and delay[3:0] have been read, the circuit no longer looks at the data input until it resumes searching after everything else is done.

// The state machine must count for exactly (delay[3:0] + 1) * 1000 clock cycles. e.g., delay=0 means count 1000 cycles, and delay=5 means count 6000 cycles. Also output the current remaining time. This should be equal to delay for 1000 cycles, then delay-1 for 1000 cycles, and so on until it is 0 for 1000 cycles.

// When the circuit isn't counting, the count[3:0] output is don't-care (whatever value is convenient for you to implement). At that point, the circuit must assert done to notify the user the timer has timed out, and waits until input ack is 1 before being reset to look for the next occurrence of the start sequence (1101).

// The circuit should reset into a state where it begins searching for the input sequence 1101. The reset signal is active high synchronous.

module top_module(
	input wire clk,
	input wire reset,
	input wire data,
    output wire [3:0] count,
    output reg counting,
    output reg done,
    input wire ack );
 parameter IDLE=0, SEARCH=1, SHIFT=2, COUNT=3;

         reg [3:0] duration;
         reg [15:0] counter;
         reg [1:0] state;

         reg [3:0] current_count;
         wire [3:0] next_count;

         assign next_count = current_count - 1;

         always @(posedge clk) begin
            if (reset) begin
                state <= IDLE;
                counter <= 0;
                current_count <= 0;
                counting <= 0;
                done <= 0;
            end else begin
                case(state)
                    IDLE: begin
                        if (data == 0) begin
                            state <= SEARCH;
                        end
                    end
                    SEARCH: begin
                        if (data == 1 && counter == 1 && duration == 0) begin
                            state <= SHIFT;
                            counter <= 0;
                        end else begin
                            counter <= counter + 1;
                        end
                    end
                    SHIFT: begin
                        duration <= {data, duration[3:1]};
                        counter <= 0;
                        state <= COUNT;
                        current_count <= duration + 1;
                        counting <= 1;
                    end
                    COUNT: begin
                        if (counter == 0 && current_count == 0) begin
                            state <= IDLE;
                            counting <= 0;
                            done <= 1;
                        end else if (counter == 0 && current_count != 0) begin
                            current_count <= next_count;
                            counter <= duration;
                        end else begin
                            counter <= counter - 1;
                        end
                    end
                endcase
            end
         end

         always @(posedge clk) begin
            if (reset) begin
                count <= 0;
            end else begin
                if (counting) begin
                    count <= current_count;
                end else begin
                    count <= 0;
                end
            end
         end

         always @(posedge clk) begin
            if (reset) begin
                counting <= 0;
                done <= 0;
            end else begin
                if (counting && ack) begin
                    counting <= 0;
                    done <= 0;
                end else if (state == IDLE && !counting) begin
                    counting <= 0;
                    done <= 0;
                end
            end
         end

    endmodule

5:      : 'count' is declared here as a wire.
67: error: 'count' is not a valid l-value for a procedural assignment.
72: error: 'count' is not a valid l-value for a procedural assignment.
70: error: 'count' is not a valid l-value for a procedural assignment.


module top_module(
	input wire clk,
	input wire reset,
	input wire data,
    output wire [3:0] count,
    output reg counting,
    output reg done,
    input wire ack );
 reg [3:0] delay;
         reg [3:0] remaining;
         reg [1:0] state;

         // States
         parameter [1:0] IDLE = 2'b00,
                       START = 2'b01,
                       WAIT = 2'b10;

         // Outputs
         wire [3:0] count_out;
         wire counting_out;

         // Instantiate the timer module
         timer t(.clk(clk), .reset(reset), .data(data), .delay(delay), .remaining(remaining), .state(state), .count(count_out), .counting(counting_out), .done(done));

         // State machine
         always @(posedge clk) begin
             if (reset) begin
                 state <= IDLE;
                 delay <= 0;
                 remaining <= 0;
                 counting <= 0;
                 done <= 0;
             end
             else begin
                 case (state)
                     IDLE: begin
                         if (data == 4'b1101) begin
                             state <= START;
                         end
                     end
                     START: begin
                         delay <= {data, delay[3:1]};
                         state <= WAIT;
                     end
                     WAIT: begin
                         if (remaining == 0) begin
                             counting <= 0;
                             done <= 1;
                             state <= IDLE;
                         end
                         else begin
                             counting <= 1;
                             remaining <= remaining - 1;
                         end
                     end
                 endcase
             end
         end

         assign count = count_out;
         assign counting = counting_out;

         // Reset the timer when the input is acknowledged
         always @(posedge clk) begin
             if (ack) begin
                 delay <= 0;
                 remaining <= 0;
                 counting <= 0;
                 done <= 0;
             end
         end

endmodule


We want to create a timer that:
// (1) is started when a particular pattern (1101) is detected,
// (2) shifts in 4 more bits to determine the duration to delay,
// (3) waits for the counters to finish counting, and
// (4) notifies the user and waits for the user to acknowledge the timer.
// In this problem, implement just the finite-state machine that controls the timer. The data path (counters and some comparators) are not included here.
// The serial data is available on the data input pin. When the pattern 1101 is received, the state machine must then assert output shift_ena for exactly 4 clock cycles. After that, the state machine asserts its counting output to indicate it is waiting for the counters, and waits until input done_counting is high.At that point, the state machine must assert done to notify the user the timer has timed out, and waits until input ack is 1 before being reset to look for the next occurrence of the start sequence (1101). The state machine should have a active high synchronous reset, setting the state to where it begins searching for the input sequence 1101.

module top_module(
	input clk,
	input reset,
	input data,
    output reg shift_ena,
    output reg counting,
    input done_counting,
    output reg done,
    input ack );
 parameter IDLE = 2'b00;
         parameter WAIT_DATA = 2'b01;
         parameter WAIT_COUNT = 2'b10;
         parameter WAIT_ACK = 2'b11;
         parameter [1:0] STATE = IDLE;

         always @(posedge clk) begin
             if (reset) begin
                 STATE <= IDLE;
                 shift_ena <= 1'b0;
                 counting <= 1'b0;
                 done <= 1'b0;
             end
             else begin
                 case (STATE)
                     IDLE: begin
                         if (data == 1'b1) begin
                             STATE <= WAIT_DATA;
                             shift_ena <= 1'b1;
                         end
                     end
                     WAIT_DATA: begin
                         if (shift_ena == 1'b1) begin
                             STATE <= WAIT_COUNT;
                             shift_ena <= 1'b0;
                             counting <= 1'b1;
                         end
                     end
                     WAIT_COUNT: begin
                         if (done_counting == 1'b1) begin
                             STATE <= WAIT_ACK;
                             counting <= 1'b0;
                             done <= 1'b1;
                         end
                     end
                     WAIT_ACK: begin
                         if (ack == 1'b1) begin
                             STATE <= IDLE;
                             done <= 1'b0;
                         end
                     end
                 endcase
             end
         end
     endmodule

33: error: Could not find variable ``STATE'' in ``top_module''
40: error: Could not find variable ``STATE'' in ``top_module''
47: error: Could not find variable ``STATE'' in ``top_module''
27: error: Could not find variable ``STATE'' in ``top_module''
18: error: Could not find variable ``STATE'' in ``top_module''


module top_module(
	input clk,
	input reset,
	input data,
    output reg shift_ena,
    output reg counting,
    input done_counting,
    output reg done,
    input ack );
 reg [1:0] state;
             reg [3:0] pattern;

             always @(posedge clk) begin
                 if (reset) begin
                     state <= 2'b00;
                     pattern <= 4'b0000;
                 end else begin
                     case (state)
                         2'b00: begin // searching for the start sequence 1101
                             if (pattern == 4'b1101) begin
                                 shift_ena <= 1'b1;
                                 state <= 2'b01;
                             end else begin
                                 pattern <= {pattern[2:0], data};
                             end
                         end
                         2'b01: begin // waiting for the shift enable signal
                             if (shift_ena) begin
                                 state <= 2'b10;
                             end
                         end
                         2'b10: begin // waiting for the counters to finish counting
                             if (done_counting) begin
                                 done <= 1'b1;
                                 state <= 2'b11;
                             end
                         end
                         2'b11: begin // waiting for the user to acknowledge the timer
                             if (ack) begin
                                 state <= 2'b00;
                                 pattern <= 4'b0000;
                             end
                         end
                     endcase
                 end
             end

             always @(posedge clk) begin
                 if (reset) begin
                     counting <= 1'b0;
                 end else begin
                     case (state)
                         2'b00: begin // searching for the start sequence 1101
                             counting <= 1'b0;
                         end
                         2'b01: begin // waiting for the shift enable signal
                             counting <= 1'b1;
                         end
                         2'b10: begin // waiting for the counters to finish counting
                             counting <= 1'b1;
                         end
                         2'b11: begin // waiting for the user to acknowledge the timer
                             counting <= 1'b0;
                         end
                     endcase
                 end
             end

             always @(posedge clk) begin
                 if (reset) begin
                     shift_ena <= 1'b0;
                 end else begin
                     case (state)
                         2'b00: begin // searching for the start sequence 1101
                             shift_ena <= 1'b0;
                         end
                         2'b01: begin // waiting for the shift enable signal
                             shift_ena <= 1'b1;
                         end
                         2'b10: begin // waiting for the counters to finish counting
                             shift_ena <= 1'b0;
                         end
                         2'b11: begin // waiting for the user to acknowledge the timer
                             shift_ena <= 1'b0;
                         end
                     endcase
                 end
             end

             always @(posedge clk) begin
                 if (reset) begin
                     done <= 1'b0;
                 end else begin
                     case (state)
                         2'b00: begin // searching for the start sequence 1101
                             done <= 1'b0;
                         end
                         2'b01: begin // waiting for the shift enable signal
                             done <= 1'b0;
                         end
                         2'b10: begin // waiting for the counters to finish counting
                             done <= 1'b1;
                         end
                         2'b11: begin // waiting for the user to acknowledge the timer
                             done <= 1'b0;
                         end
                     endcase
                 end
             end

             always @(posedge clk) begin
                 if (reset) begin
                     ack <= 1'b0;
                 end else begin
                     case (state)
                         2'b00: begin // searching for the start sequence 1101
                             ack <= 1'b0;
                         end
                         2'b01: begin // waiting for the shift enable signal
                             ack <= 1'b0;
                         end
                         2'b10: begin // waiting for the counters to finish counting
                             ack <= 1'b0;
                         end
                         2'b11: begin // waiting for the user to acknowledge the timer
                             ack <= 1'b1;
                         end
                     endcase
                 end
             end

         endmodule

113: error: 'ack' is not a valid l-value for a procedural assignment.
9:      : 'ack' is declared here as a wire.
126: error: 'ack' is not a valid l-value for a procedural assignment.
123: error: 'ack' is not a valid l-value for a procedural assignment.
120: error: 'ack' is not a valid l-value for a procedural assignment.
117: error: 'ack' is not a valid l-value for a procedural assignment.


Given the following Moore state machine with 3 input (d, done_counting, ack) and 3 outputs (shift_ena, counting, done). Unless otherwise stated in the diagram below, assume outputs are 0 and inputs are don't cares.

// S () --d=0--> S
// S () --d=1--> S1
// S1 () --d=0--> S
// S1 () --d=1--> S11
// S11 () --d=0--> S110
// S11 () --d=1--> S11
// S110 () --d=0--> S
// S110 () --d=1--> B0
// B0 (shift_ena=1) -- (always go to next cycle) --> B1
// B1 (shift_ena=1) -- (always go to next cycle) --> B2
// B2 (shift_ena=1) -- (always go to next cycle) --> B3
// B3 (shift_ena=1) -- (always go to next cycle) --> Count
// Count (counting=1) --!(done_counting)--> Count
// Count (counting=1) --(done_counting)--> Wait
// Wait (done=1) --ack=0--> Wait
// Wait (done=1) --ack=1--> S

// At reset, the state machine starts in state "S". Derive next-state logic equations and output logic equations by inspection assuming the following one-hot encoding is used: (S, S1, S11, S110, B0, B1, B2, B3, Count, Wait) = (10'b0000000001, 10'b0000000010, 10'b0000000100, ... , 10'b1000000000)

// Derive state transition and output logic equations by inspection assuming a one-hot encoding. Implement only the state transition logic and output logic (the combinational logic portion) for this state machine.

// Write code that generates the following equations:

// - B3_next -- next-state logic for state B3
// - S_next
// - S1_next
// - Count_next
// - Wait_next
// - done -- output logic
// - counting
// - shift_ena

module top_module(
    input d,
    input done_counting,
    input ack,
    input [9:0] state,    // 10-bit one-hot current state
    output B3_next,
    output S_next,
    output S1_next,
    output Count_next,
    output Wait_next,
    output done,
    output counting,
    output shift_ena
 );
 // State transition logic
         wire [9:0] S_next_wire = (state[0] & ~d) ? 10'b0000000001 : 10'b0000000000;
         wire [9:0] S1_next_wire = (state[1] & d) ? 10'b0000000010 : 10'b0000000000;
         wire [9:0] S11_next_wire = (state[2] & d) ? 10'b0000000100 : 10'b0000000000;
         wire [9:0] S110_next_wire = (state[3] & ~d) ? 10'b0000001000 : 10'b0000000000;
         wire [9:0] B0_next_wire = (state[4]) ? 10'b0000010000 : 10'b0000000000;
         wire [9:0] B1_next_wire = (state[5]) ? 10'b0000100000 : 10'b0000000000;
         wire [9:0] B2_next_wire = (state[6]) ? 10'b0001000000 : 10'b0000000000;
         wire [9:0] B3_next_wire = (state[7]) ? 10'b0010000000 : 10'b0000000000;
         wire [9:0] Count_next_wire = (state[8] & ~done_counting) ? 10'b0100000000 : 10'b0000000000;
         wire [9:0] Wait_next_wire = (state[9] & ~ack) ? 10'b1000000000 : 10'b0000000000;

         // Output assignment logic
         assign shift_ena = (B0_next_wire | B1_next_wire | B2_next_wire | B3_next_wire);
         assign counting = (Count_next_wire);
         assign done = (Wait_next_wire);

         // Triggering conditions for always blocks
         always @(posedge clk) begin
            B3_next <= B3_next_wire;
            S_next <= S_next_wire;
            S1_next <= S1_next_wire;
            Count_next <= Count_next_wire;
            Wait_next <= Wait_next_wire;
         end

 endmodule

35: error: 'S_next' is not a valid l-value for a procedural assignment.
38: error: 'Wait_next' is not a valid l-value for a procedural assignment.
8:      : 'S1_next' is declared here as a wire.
6:      : 'B3_next' is declared here as a wire.
7:      : 'S_next' is declared here as a wire.
34: error: 'B3_next' is not a valid l-value for a procedural assignment.
33: error: Failed to evaluate event expression 'posedge clk'.
36: error: 'S1_next' is not a valid l-value for a procedural assignment.
33: error: Unable to bind wire/reg/memory `clk' in `top_module'
37: error: 'Count_next' is not a valid l-value for a procedural assignment.
10:      : 'Wait_next' is declared here as a wire.
9:      : 'Count_next' is declared here as a wire.


module top_module(
    input d,
    input done_counting,
    input ack,
    input [9:0] state,    // 10-bit one-hot current state
    output B3_next,
    output S_next,
    output S1_next,
    output Count_next,
    output Wait_next,
    output done,
    output counting,
    output shift_ena
 );
 parameter S = 10'b0000000001, S1 = 10'b0000000010, S11 = 10'b0000000100, S110 = 10'b0000001000, B0 = 10'b0000010000, B1 = 10'b0000100000, B2 = 10'b0001000000, B3 = 10'b0010000000, Count = 10'b0100000000, Wait = 10'b1000000000;

        assign S_next = (state == S) && ~d;
        assign S1_next = (state == S1) && ~d;
        assign S11_next = (state == S11) && ~d;
        assign S110_next = (state == S110) && ~d;
        assign B0_next = (state == B0);
        assign B1_next = (state == B1);
        assign B2_next = (state == B2);
        assign B3_next = (state == B3);
        assign Count_next = (state == Count) && ~done_counting;
        assign Wait_next = (state == Wait) && ack;

        assign done = (state == Wait);
        assign counting = (state == Count);
        assign shift_ena = (state == B3 || state == B2 || state == B1 || state == B0);

endmodule

22: warning: implicit definition of wire 'B1_next'.
23: warning: implicit definition of wire 'B2_next'.
19: warning: implicit definition of wire 'S11_next'.
20: warning: implicit definition of wire 'S110_next'.
21: warning: implicit definition of wire 'B0_next'.


Build a finite-state machine that searches for the sequence 1101 in an input bit stream. When the sequence is found, it should set start_shifting to 1, forever, until reset. Reset is active high synchronous.

module top_module(
	input clk,
	input reset,
	input data,
	output start_shifting);
 parameter IDLE = 2'b00, SEQ1 = 2'b01, SEQ2 = 2'b10, SEQ3 = 2'b11;

         reg [1:0] state, next_state;

         always @(posedge clk, posedge reset)
           if(reset)
             state <= IDLE;
           else
             state <= next_state;

         always @* begin
             next_state = IDLE;
             start_shifting = 0;
             case(state)
               IDLE: begin
                  if(data == 1)
                    next_state = SEQ1;
                  else if(data == 0)
                    next_state = IDLE;
               end
               SEQ1: begin
                  if(data == 1)
                    next_state = SEQ2;
                  else if(data == 0)
                    next_state = IDLE;
               end
               SEQ2: begin
                  if(data == 0)
                    next_state = SEQ3;
                  else if(data == 1)
                    next_state = SEQ1;
               end
               SEQ3: begin
                  if(data == 1)
                    next_state = SEQ1;
                  else if(data == 0)
                    next_state = IDLE;
                  start_shifting = 1;
               end
             endcase
         end
 endmodule

43: error: 'start_shifting' is not a valid l-value for a procedural assignment.
18: error: 'start_shifting' is not a valid l-value for a procedural assignment.
5:      : 'start_shifting' is declared here as a wire.


module top_module(
	input clk,
	input reset,
	input data,
	output start_shifting);
 parameter IDLE = 2'b00,
                   SEQ1 = 2'b01,
                   SEQ2 = 2'b10,
                   SEQ3 = 2'b11,
                   SEQ4 = 2'b11;

        reg [1:0] state, next_state;

        always @(posedge clk) begin
                if(reset) begin
                        state <= IDLE;
                        start_shifting <= 0;
                end
                else begin
                        state <= next_state;
                end
        end

        always @(*) begin
                case(state)
                        IDLE: begin
                                if(data) begin
                                        next_state = SEQ1;
                                        start_shifting = 0;
                                end
                                else begin
                                        next_state = IDLE;
                                        start_shifting = 0;
                                end
                        end
                        SEQ1: begin
                                if(data) begin
                                        next_state = SEQ2;
                                        start_shifting = 0;
                                end
                                else begin
                                        next_state = IDLE;
                                        start_shifting = 0;
                                end
                        end
                        SEQ2: begin
                                if(data) begin
                                        next_state = SEQ3;
                                        start_shifting = 0;
                                end
                                else begin
                                        next_state = IDLE;
                                        start_shifting = 0;
                                end
                        end
                        SEQ3: begin
                                if(data) begin
                                        next_state = SEQ4;
                                        start_shifting = 1;
                                end
                                else begin
                                        next_state = IDLE;
                                        start_shifting = 0;
                                end
                        end
                        SEQ4: begin
                                if(data) begin
                                        next_state = IDLE;
                                        start_shifting = 0;
                                end
                                else begin
                                        next_state = IDLE;
                                        start_shifting = 0;
                                end
                        end
                endcase
        end

endmodule

29: error: 'start_shifting' is not a valid l-value for a procedural assignment.
43: error: 'start_shifting' is not a valid l-value for a procedural assignment.
59: error: 'start_shifting' is not a valid l-value for a procedural assignment.
63: error: 'start_shifting' is not a valid l-value for a procedural assignment.
69: error: 'start_shifting' is not a valid l-value for a procedural assignment.
39: error: 'start_shifting' is not a valid l-value for a procedural assignment.
33: error: 'start_shifting' is not a valid l-value for a procedural assignment.
73: error: 'start_shifting' is not a valid l-value for a procedural assignment.
5:      : 'start_shifting' is declared here as a wire.
53: error: 'start_shifting' is not a valid l-value for a procedural assignment.
49: error: 'start_shifting' is not a valid l-value for a procedural assignment.
17: error: 'start_shifting' is not a valid l-value for a procedural assignment.


This module is a part of the FSM for controlling the shift register, we want the ability to enable the shift register for exactly 4 clock cycles whenever the proper bit pattern is detected. Whenever the FSM is reset, assert shift_ena for 4 cycles, then 0 forever (until reset). Reset should be active high synchronous.

module top_module(
	input clk,
	input reset,
	output shift_ena);
 parameter SHIFT_ENA_CYCLES = 4;

         reg [31:0] shift_ena_counter;

         always @(posedge clk) begin
            if (reset) begin
               shift_ena_counter <= 0;
               shift_ena <= 1'b1;
            end else begin
               if (shift_ena_counter < SHIFT_ENA_CYCLES) begin
                  shift_ena_counter <= shift_ena_counter + 1;
                  shift_ena <= 1'b1;
               end else begin
                  shift_ena <= 1'b0;
               end
            end
         end
      endmodule

18: error: 'shift_ena' is not a valid l-value for a procedural assignment.
16: error: 'shift_ena' is not a valid l-value for a procedural assignment.
4:      : 'shift_ena' is declared here as a wire.
12: error: 'shift_ena' is not a valid l-value for a procedural assignment.


module top_module(
	input clk,
	input reset,
	output shift_ena);
 reg [1:0] state;
             parameter SHIFT = 2'b00, WAIT = 2'b01;
             parameter SHIFT_ENA = 4'b1111;

             always @(posedge clk) begin
                 if (reset) begin
                     state <= SHIFT;
                     shift_ena <= 1'b1;
                 end else begin
                     case (state)
                         SHIFT: begin
                             shift_ena <= SHIFT_ENA;
                             state <= WAIT;
                         end
                         WAIT: begin
                             shift_ena <= 1'b0;
                             if (reset) begin
                                 state <= SHIFT;
                             end
                         end
                     endcase
                 end
             end

endmodule

20: error: 'shift_ena' is not a valid l-value for a procedural assignment.
16: error: 'shift_ena' is not a valid l-value for a procedural assignment.
4:      : 'shift_ena' is declared here as a wire.
12: error: 'shift_ena' is not a valid l-value for a procedural assignment.


Suppose you are designing a circuit to control a cellphone's ringer and vibration motor. Whenever the phone needs to ring from an incoming call (input ring), your circuit must either turn on the ringer (output ringer = 1) or the motor (output motor = 1), but not both. If the phone is in vibrate mode (input vibrate_mode = 1), turn on the motor. Otherwise, turn on the ringer.

module top_module(
	input ring,
	input vibrate_mode,
	output ringer,
	output motor
);
 assign ringer = (ring && !vibrate_mode) ? 1'b1 : 0'b0;
         assign motor = (ring && vibrate_mode) ? 1'b1 : 0'b0;

endmodule

8: error: Sized numeric constant must have a size greater than zero.
7: error: Sized numeric constant must have a size greater than zero.


module top_module(
	input ring,
	input vibrate_mode,
	output ringer,
	output motor
);
 reg ringer;
             reg motor;

             always @(posedge ring) begin
                 if (ring == 1'b1) begin
                     if (vibrate_mode == 1'b0) begin
                         ringer <= 1'b1;
                         motor <= 1'b0;
                     end else begin
                         ringer <= 1'b0;
                         motor <= 1'b1;
                     end
                 end else begin
                     ringer <= 1'b0;
                     motor <= 1'b0;
                 end
             end

endmodule

4:      : It was declared here as a net.
8: error: 'motor' has already been declared in this scope.
7: error: 'ringer' has already been declared in this scope.
5:      : It was declared here as a net.


Build a 100-bit left/right rotator, with synchronous load and left/right enable. A rotator shifts-in the shifted-out bit from the other end of the register, unlike a shifter that discards the shifted-out bit and shifts in a zero. If enabled, a rotator rotates the bits around and does not modify/discard them.
// (1) load: Loads shift register with data[99:0] instead of rotating. Synchronous active high.
// (2) ena[1:0]: Synchronous. Chooses whether and which direction to rotate:
//     (a) 2'b01 rotates right by one bit,
//     (b) 2'b10 rotates left by one bit,
//     (c) 2'b00 and 2'b11 do not rotate.
// (3) q: The contents of the rotator.

module top_module(
	input clk,
	input load,
	input [1:0] ena,
	input [99:0] data,
	output reg [99:0] q);
 reg [99:0] reg_q;
             reg [1:0] reg_ena;

             always @(posedge clk) begin
                 if (load) begin
                     reg_q <= data;
                 end else begin
                     case (ena)
                         2'b01: reg_q <= {reg_q[98:0], reg_q[99]};
                         2'b10: reg_q <= {reg_q[1:99], reg_q[0]};
                         default: reg_q <= reg_q;
                     endcase
                 end
             end

             assign q = reg_q;

         endmodule

16: error: part select reg_q[1:99] is out of order.


module top_module(
	input clk,
	input load,
	input [1:0] ena,
	input [99:0] data,
	output reg [99:0] q);
 reg [99:0] reg_q;
         always @(posedge clk) begin
                if (load) begin
                        reg_q <= data; // load data
                end
                else begin
                        case (ena)
                                2'b01: begin
                                        reg_q[0] <= reg_q[99]; // rotate right by one bit
                                        reg_q[99:1] <= reg_q[98:0];
                                end
                                2'b10: begin
                                        reg_q[99] <= reg_q[0]; // rotate left by one bit
                                        reg_q[0:98] <= reg_q[1:99];
                                end
                        endcase
                end
         end
         assign q = reg_q;

endmodule

20: error: part select reg_q[0:98] is reversed.
20: error: part select reg_q[1:99] is out of order.


Rule 110 is a one-dimensional cellular automaton with interesting properties (such as being Turing-complete). There is a one-dimensional array of cells (on or off). At each time step, the state of each cell changes. In Rule 110, the next state of each cell depends only on itself and its two neighbours, according to the following table:
// Left | Center | Right | Center's next state
// 1 | 1 | 1 | 0
// 1 | 1 | 0 | 1
// 1 | 0 | 1 | 1
// 1 | 0 | 0 | 0
// 0 | 1 | 1 | 1
// 0 | 1 | 0 | 1
// 0 | 0 | 1 | 1
// 0 | 0 | 0 | 0
// In this circuit, create a 512-cell system (q[511:0]), and advance by one time step each clock cycle. The synchronous active high load input indicates the state of the system should be loaded with data[511:0]. Assume the boundaries (q[-1] and q[512]) are both zero (off).

module top_module(
	input clk,
	input load,
	input [511:0] data,
	output reg [511:0] q);
 // Define the rule as a function
         always @(*) begin
            q = {q[510:0], ((q[511:510] & q[509:508]) | (~q[511:510] & ~q[509:508])) & (q[509:508] ^ q[511:510])};
         end

         // Load new data into q on a rising edge of load
         always @(posedge clk) begin
            if (load) begin
               q <= data;
            end
         end

      // Boundaries are always 0
      assign q[-1] = 0;
      assign q[512] = 0;

endmodule

14: error: Cannot perform procedural assignment to variable 'q' because it is also continuously assigned.
19: sorry: part selects straddling the start of signal (q[-('sd1)]) are not currently supported.
20: error: Index q[512] is out of range.
8: error: Cannot perform procedural assignment to variable 'q' because it is also continuously assigned.


module top_module(
	input clk,
	input load,
	input [511:0] data,
	output reg [511:0] q);

        always @(posedge clk) begin
        // always block triggered on positive edge of clock signal.
            if (load) begin
            // If load signal is high.
                q <= data; // Assign data to q.
            end else begin
            // If load signal is low.
                q[0] <= (q[1] & q[2]) | (~q[1] & ~q[2]); // Calculate new value for q[0].
                q[511] <= (q[510] & q[511]) | (~q[510] & ~q[511]); // Calculate new value for q[511].
                for (i = 1; i < 511; i = i + 1) begin
                // Loop through q from index 1 to 510.
                    q[i] <= (q[i-1] & q[i+1]) | (~q[i-1] & ~q[i+1]); // Calculate new value for each q[i].
                end
            end
        end
        // end of always block
        endmodule

16: register ``i'' unknown in top_module.


Rule 90 is a one-dimensional cellular automaton with interesting properties. The rules are simple. There is a one-dimensional array of cells (on or off). At each time step, the next state of each cell is the XOR of the cell's two current neighbours:
// Left | Center | Right | Center's next state
// 1 | 1 | 1 | 0
// 1 | 1 | 0 | 1
// 1 | 0 | 1 | 0
// 1 | 0 | 0 | 1
// 0 | 1 | 1 | 1
// 0 | 1 | 0 | 0
// 0 | 0 | 1 | 1
// 0 | 0 | 0 | 0
// In this circuit, create a 512-cell system (q[511:0]), and advance by one time step each clock cycle. The load input indicates the state of the system should be loaded with data[511:0]. Assume the boundaries (q[-1] and q[512]) are both zero (off).

module top_module(
	input clk,
	input load,
	input [511:0] data,
	output reg [511:0] q);
 // intermediate storage
        reg [513:0] current_state, next_state;
        reg [2:0] left, center, right;

        // load initial state
        always @(posedge clk) begin
            if (load) begin
                current_state <= {1'b0, data, 1'b0};
            end else begin
                current_state <= next_state;
            end
        end

        // calculate next state
        always @(*) begin
            next_state = {1'b0, current_state[511:1], 1'b0};
            for (i = 0; i < 512; i = i + 1) begin
                left = current_state[i-1:i-2];
                center = current_state[i:i+1];
                right = current_state[i+2:i+3];
                next_state[i+1] = (left ^ center ^ right);
            end
        end

        // output current state
        always @(posedge clk) begin
            q <= current_state[511:0];
        end

    endmodule

22: register ``i'' unknown in top_module.


module top_module(
	input clk,
	input load,
	input [511:0] data,
	output reg [511:0] q);
 always @(posedge clk) begin
            if (load) begin
                q <= data;
            end else begin
                q[0] <= q[1] ^ q[511];
                q[511] <= q[510] ^ q[0];
                for (i = 1; i < 511; i = i + 1) begin
                    q[i] <= q[i-1] ^ q[i+1];
                end
            end
        end

    endmodule

12: register ``i'' unknown in top_module.


Build a 64-bit arithmetic shift register, with synchronous load. The shifter can shift both left and right, and by 1 or 8 bit positions, selected by "amount." Assume the right shit is an arithmetic right shift.

// Signals are defined as below:
// (1) load: Loads shift register with data[63:0] instead of shifting. Active high.
// (2) ena: Chooses whether to shift. Active high.
// (3) amount: Chooses which direction and how much to shift.
//     (a) 2'b00: shift left by 1 bit.
//     (b) 2'b01: shift left by 8 bits.
//     (c) 2'b10: shift right by 1 bit.
//     (d) 2'b11: shift right by 8 bits.
// (4) q: The contents of the shifter.

module top_module(
	input clk,
	input load,
	input ena,
	input [1:0] amount,
	input [63:0] data,
	output reg [63:0] q);
 reg [63:0] shift_reg;

         always @(posedge clk) begin
             if (load) begin
                 shift_reg <= data;
             end else if (ena) begin
                 case (amount)
                     2'b00: shift_reg <= {shift_reg[62:0], 1'b0};
                     2'b01: shift_reg <= {shift_reg[47:0], 1'b0};
                     2'b10: shift_reg <= {1'b1, shift_reg[63:1]};
                     2'b11: shift_reg <= {8'b11111111, shift_reg[7:8]};
                 endcase
             end
         end

         assign q = shift_reg;

endmodule

18: error: part select shift_reg[7:8] is out of order.


Build a circuit with no inputs and one output. That output should always drive 1 (or logic high).

module top_module(
	output one);
 // Module is supply voltage agnostic, over-voltage and under-voltage safe
         supply1 VPWR;
         supply0 VGND;
         supply1 VPB ;
         supply0 VNB ;

        always @(*) begin
            one = 1'b1;
        end
    endmodule

10: error: 'one' is not a valid l-value for a procedural assignment.
2:      : 'one' is declared here as a wire.


module top_module(
	output one);
 reg one;

             always @(posedge clk)
             begin
                 one <= 1'b1;
             end

        endmodule

3: error: 'one' has already been declared in this scope.
2:      : It was declared here as a net.


A heating/cooling thermostat controls both a heater (during winter) and an air conditioner (during summer). Implement a circuit that will turn on and off the heater, air conditioning, and blower fan as appropriate. The thermostat can be in one of two modes: heating (mode = 1) and cooling (mode = 0). In heating mode, turn the heater on when it is too cold (too_cold = 1) but do not use the air conditioner. In cooling mode, turn the air conditioner on when it is too hot (too_hot = 1), but do not turn on the heater. When the heater or air conditioner are on, also turn on the fan to circulate the air. In addition, the user can also request the fan to turn on (fan_on = 1), even if the heater and air conditioner are off.

module top_module(
	input mode,
	input too_cold,
	input too_hot,
	input fan_on,
	output heater,
	output aircon,
	output fan
);
 parameter mode = 1;
         parameter too_cold = 1;
         parameter too_hot = 0;
         parameter fan_on = 0;

         reg heater_reg;
         reg aircon_reg;
         reg fan_reg;

         always @(posedge clk) begin
            if (mode == 1 && too_cold == 1) begin
               heater_reg <= 1;
               fan_reg <= 1;
            end else if (mode == 0 && too_hot == 1) begin
               aircon_reg <= 1;
               fan_reg <= 1;
            end else if (fan_on == 1) begin
               fan_reg <= 1;
            end else begin
               heater_reg <= 0;
               aircon_reg <= 0;
               fan_reg <= 0;
            end
         end

         assign heater = heater_reg;
         assign aircon = aircon_reg;
         assign fan = fan_reg;

      endmodule

11: error: 'too_cold' has already been declared in this scope.
4:      : It was declared here as a net.
2:      : It was declared here as a net.
10: error: 'mode' has already been declared in this scope.
13: error: 'fan_on' has already been declared in this scope.
5:      : It was declared here as a net.
12: error: 'too_hot' has already been declared in this scope.
3:      : It was declared here as a net.


module top_module(
	input mode,
	input too_cold,
	input too_hot,
	input fan_on,
	output heater,
	output aircon,
	output fan
);
 reg heater;
             reg aircon;
             reg fan;

             always @(posedge clk) begin
                 if (mode == 1'b1) begin // cooling mode
                     if (too_hot == 1'b1) begin
                         heater <= 1'b0;
                         aircon <= 1'b1;
                     end else begin
                         heater <= 1'b0;
                         aircon <= 1'b0;
                     end
                 end else begin // heating mode
                     if (too_cold == 1'b1) begin
                         heater <= 1'b1;
                         aircon <= 1'b0;
                     end else begin
                         heater <= 1'b0;
                         aircon <= 1'b0;
                     end
                 end
                 if (fan_on == 1'b1 || heater == 1'b1 || aircon == 1'b1) begin
                     fan <= 1'b1;
                 end else begin
                     fan <= 1'b0;
                 end
             end

endmodule

11: error: 'aircon' has already been declared in this scope.
10: error: 'heater' has already been declared in this scope.
8:      : It was declared here as a net.
12: error: 'fan' has already been declared in this scope.
7:      : It was declared here as a net.
6:      : It was declared here as a net.


Implement a timer that counts down for a given number of clock cycles, then asserts a signal to indicate that the given duration has elapsed. A good way to implement this is with a down-counter that asserts an output signal when the count becomes 0. At each clock cycle:
// (1) If load = 1, load the internal counter with the 10-bit data, the number of clock cycles the timer should count before timing out. The counter can be loaded at any time, including when it is still counting and has not yet reached 0.
// (2) If load = 0, the internal counter should decrement by 1. The output signal tc ("terminal count") indicates whether the internal counter has reached 0. Once the internal counter has reached 0, it should stay 0 (stop counting) until the counter is loaded again.

module top_module(
	input clk,
	input load,
	input [9:0] data,
	output tc
);
 // Your code here
        reg [9:0] count;
        reg tc_reg;
        always @(posedge clk) begin
            if (load) begin
                count <= data;
                tc_reg <= 0;
            end else if (count > 0) begin
                count <= count - 1;
                tc_reg <= 0;
            end else begin
                tc_reg <= 1;
            end
        end
        assign tc = tc_reg;
        assign tc_reg = (count == 0) ? 1'b1 : 1'b0;
endmodule

13: error: Cannot perform procedural assignment to variable 'tc_reg' because it is also continuously assigned.
18: error: Cannot perform procedural assignment to variable 'tc_reg' because it is also continuously assigned.
16: error: Cannot perform procedural assignment to variable 'tc_reg' because it is also continuously assigned.


module top_module(
	input clk,
	input load,
	input [9:0] data,
	output tc
);
 reg [9:0] count;

             always @(posedge clk) begin
                 if (load) begin
                     count <= data;
                 end else begin
                     count <= count - 1;
                 end
                 if (count == 0) begin
                     tc <= 1;
                 end else begin
                     tc <= 0;
                 end
             end

endmodule

16: error: 'tc' is not a valid l-value for a procedural assignment.
5:      : 'tc' is declared here as a wire.
18: error: 'tc' is not a valid l-value for a procedural assignment.


Create a combinational circuit that implements the truth table.

// x3 | x2 | x1 | f
// 0 | 0 | 0 | 0
// 0 | 0 | 1 | 0
// 0 | 1 | 0 | 1
// 0 | 1 | 1 | 1
// 1 | 0 | 0 | 0
// 1 | 0 | 1 | 1
// 1 | 1 | 0 | 0
// 1 | 1 | 1 | 1

module top_module (
	input x3,
	input x2,
	input x1,
	output f
);
 parameter SIZE = 8;
             reg [SIZE-1:0] f;

             always @* begin
                if (x3 && x2 && x1)
                    f = 8'b11111111;
                else if (x3 && x2)
                    f = 8'b11111110;
                else if (x3 && x1)
                    f = 8'b11111100;
                else if (x2 && x1)
                    f = 8'b11111000;
                else if (x3)
                    f = 8'b11110000;
                else if (x2)
                    f = 8'b11100000;
                else if (x1)
                    f = 8'b11000000;
                else
                    f = 8'b00000000;
             end

endmodule

8: error: 'f' has already been declared in this scope.
5:      : It was declared here as a net.


module top_module (
	input x3,
	input x2,
	input x1,
	output f
);
 parameter [0:1] x3_values = 2'b00;
         parameter [0:1] x2_values = 2'b00;
         parameter [0:1] x1_values = 2'b00;
         parameter [0:1] f_values = 2'b00;

         always @(*) begin
            if (x3 == x3_values[0] && x2 == x2_values[0] && x1 == x1_values[0])
                f = f_values[0];
            else if (x3 == x3_values[0] && x2 == x2_values[0] && x1 == x1_values[1])
                f = f_values[1];
            else if (x3 == x3_values[0] && x2 == x2_values[1] && x1 == x1_values[0])
                f = f_values[2];
            else if (x3 == x3_values[0] && x2 == x2_values[1] && x1 == x1_values[1])
                f = f_values[3];
            else if (x3 == x3_values[1] && x2 == x2_values[0] && x1 == x1_values[0])
                f = f_values[4];
            else if (x3 == x3_values[1] && x2 == x2_values[0] && x1 == x1_values[1])
                f = f_values[5];
            else if (x3 == x3_values[1] && x2 == x2_values[1] && x1 == x1_values[0])
                f = f_values[6];
            else if (x3 == x3_values[1] && x2 == x2_values[1] && x1 == x1_values[1])
                f = f_values[7];
         end

endmodule

22: error: 'f' is not a valid l-value for a procedural assignment.
24: error: 'f' is not a valid l-value for a procedural assignment.
18: error: 'f' is not a valid l-value for a procedural assignment.
20: error: 'f' is not a valid l-value for a procedural assignment.
26: error: 'f' is not a valid l-value for a procedural assignment.
14: error: 'f' is not a valid l-value for a procedural assignment.
5:      : 'f' is declared here as a wire.
16: error: 'f' is not a valid l-value for a procedural assignment.
28: error: 'f' is not a valid l-value for a procedural assignment.


Build a circuit that has one 3-bit input, then outputs the same vector, and also splits it into three separate 1-bit outputs. Connect output o0 to the input vector's position 0, o1 to position 1, etc.

module top_module(
	input [2:0] vec,
	output [2:0] outv,
	output o2,
	output o1,
	output o0
);
 assign outv = vec;
         assign o2 = vec2;
         assign o1 = vec1;
         assign o0 = vec0;

endmodule

11: error: Unable to elaborate r-value: vec0
11: error: Unable to bind wire/reg/memory `vec0' in `top_module'
10: error: Unable to bind wire/reg/memory `vec1' in `top_module'
9: error: Unable to elaborate r-value: vec2
10: error: Unable to elaborate r-value: vec1
9: error: Unable to bind wire/reg/memory `vec2' in `top_module'


Given a 100-bit input vector [99:0], reverse its bit ordering.

module top_module (
	input [99:0] in,
	output reg [99:0] out
);
 integer i;

         always @(*) begin
         // always block triggered when any input changes.
         // Perform bit reversal operation on input.
         for (i = 0; i < 100; i = i + 1) begin
         // Loop through each bit of the input.
         outi = ini;
         // Assign the input bit to the output in reversed order.
         end
         end

endmodule

12: error: Could not find variable ``outi'' in ``top_module''


module top_module (
	input [99:0] in,
	output reg [99:0] out
);
 reverse_module reverse_inst (
            .in(in),
            .out(out)
        );

endmodule

5: error: Unknown module type: reverse_module


Build a circuit that reverses the byte order of a 32-bit vector.

module top_module (
	input [31:0] in,
	output [31:0] out
);
 // Temporary 8-bit register
         reg [7:0] temp;

         // State transition logic
         always @(posedge clk) begin
            // Extract the four bytes
            temp[7:0] = in[7:0];
            temp[15:8] = in[15:8];
            temp[23:16] = in[23:16];
            temp[31:24] = in[31:24];

            // Reverse their order
            out[7:0] = temp[31:24];
            out[15:8] = temp[23:16];
            out[23:16] = temp[15:8];
            out[31:24] = temp[7:0];
         end

endmodule

19: error: 'out['sd23:'sd16]' is not a valid l-value for a procedural assignment.
3:      : 'out['sd23:'sd16]' is declared here as a wire.
20: error: 'out['sd31:'sd24]' is not a valid l-value for a procedural assignment.
3:      : 'out['sd7:'sd0]' is declared here as a wire.
3:      : 'out['sd15:'sd8]' is declared here as a wire.
18: error: 'out['sd15:'sd8]' is not a valid l-value for a procedural assignment.
12: warning: Part select temp[15:8] is out of range.
3:      : 'out['sd31:'sd24]' is declared here as a wire.
13: warning: Part select temp[23:16] is out of range.
9: error: Failed to evaluate event expression 'posedge clk'.
17: error: 'out['sd7:'sd0]' is not a valid l-value for a procedural assignment.
9: error: Unable to bind wire/reg/memory `clk' in `top_module'
14: warning: Part select temp[31:24] is out of range.


module top_module (
	input [31:0] in,
	output [31:0] out
);
 string out_str;
         byte byte1;
         byte byte2;
         byte byte3;
         byte byte4;

         always @(*) begin
           byte1 = in[7:0];
           byte2 = in[15:8];
           byte3 = in[23:16];
           byte4 = in[31:24];

           out = {byte1, byte2, byte3, byte4};

         end

endmodule

17: error: 'out' is not a valid l-value for a procedural assignment.
3:      : 'out' is declared here as a wire.


Given several input vectors, concatenate them together then split them up into several output vectors. There are six 5-bit input vectors: a, b, c, d, e, and f, for a total of 30 bits of input. There are four 8-bit output vectors: w, x, y, and z, for 32 bits of output. The output should be a concatenation of the input vectors followed by two 1 bits (the two 1 bits should be in the LSB positions).

module top_module (
	input [4:0] a,
	input [4:0] b,
	input [4:0] c,
	input [4:0] d,
	input [4:0] e,
	input [4:0] f,
	output [7:0] w,
	output [7:0] x,
	output [7:0] y,
	output [7:0] z
);
 assign w = { a, b, c, d, e, f, 2'b11 };
         assign x = w[15:8];
         assign y = w[23:16];
         assign z = w[31:24];

endmodule

16:        : Replacing the out of bound bits with 'bx.
16: warning: Part select [31:24] is selecting after the vector w[7:0].
15: warning: Part select [23:16] is selecting after the vector w[7:0].
15:        : Replacing the out of bound bits with 'bx.
14:        : Replacing the out of bound bits with 'bx.
14: warning: Part select [15:8] is selecting after the vector w[7:0].


module top_module (
	input [4:0] a,
	input [4:0] b,
	input [4:0] c,
	input [4:0] d,
	input [4:0] e,
	input [4:0] f,
	output [7:0] w,
	output [7:0] x,
	output [7:0] y,
	output [7:0] z
);
 assign w = {a, b, c, d, e, f, 2'b01};
         assign x = w[15:8];
         assign y = w[23:16];
         assign z = w[31:24];

endmodule


One common place to see a replication operator is when sign-extending a smaller number to a larger one, while preserving its signed value. This is done by replicating the sign bit (the most significant bit) of the smaller number to the left. For example, sign-extending 4'b0101 (5) to 8 bits results in 8'b00000101 (5), while sign-extending 4'b1101 (-3) to 8 bits results in 8'b11111101 (-3). Build a circuit that sign-extends an 8-bit number to 32 bits. This requires a concatenation of 24 copies of the sign bit (i.e., replicate bit[7] 24 times) followed by the 8-bit number itself.

module top_module (
	input [7:0] in,
	output [31:0] out
);
 sign_extend sign_extend_inst (
                .in(in),
                .out(out)
            );

        endmodule

5: error: Unknown module type: sign_extend


Given five 1-bit signals (a, b, c, d, and e), compute all 25 pairwise one-bit comparisons in the 25-bit output vector. The output should be 1 if the two bits being compared are equal. Example: out[24] = ~a ^ a; out[23] = ~a ^ b; out[22] = ~a ^ c; ... out[ 1] = ~e ^ d; out[ 0] = ~e ^ e.

module top_module (
	input a,
	input b,
	input c,
	input d,
	input e,
	output [24:0] out
);
 // 25-bit output vector
	wire [24:0] out;

	// pairwise one-bit comparisons
	assign out[24] = ~a ^ a;
	assign out[23] = ~a ^ b;
	assign out[22] = ~a ^ c;
	assign out[21] = ~a ^ d;
	assign out[20] = ~a ^ e;
	assign out[19] = ~b ^ a;
	assign out[18] = ~b ^ b;
	assign out[17] = ~b ^ c;
	assign out[16] = ~b ^ d;
	assign out[15] = ~b ^ e;
	assign out[14] = ~c ^ a;
	assign out[13] = ~c ^ b;
	assign out[12] = ~c ^ c;
	assign out[11] = ~c ^ d;
	assign out[10] = ~c ^ e;
	assign out[9] = ~d ^ a;
	assign out[8] = ~d ^ b;
	assign out[7] = ~d ^ c;
	assign out[6] = ~d ^ d;
	assign out[5] = ~d ^ e;
	assign out[4] = ~e ^ a;
	assign out[3] = ~e ^ b;
	assign out[2] = ~e ^ c;
	assign out[1] = ~e ^ d;
	assign out[0] = ~e ^ e;

endmodule

10: error: 'out' has already been declared in this scope.
7:      : It was declared here as a net.


module top_module (
	input a,
	input b,
	input c,
	input d,
	input e,
	output [24:0] out
);
 always @(*) begin
            out[24] = ~a ^ e;
            out[23] = ~a ^ d;
            out[22] = ~a ^ c;
            out[21] = ~a ^ b;
            out[20] = ~b ^ e;
            out[19] = ~b ^ d;
            out[18] = ~b ^ c;
            out[17] = ~b ^ a;
            out[16] = ~c ^ e;
            out[15] = ~c ^ d;
            out[14] = ~c ^ b;
            out[13] = ~c ^ a;
            out[12] = ~d ^ e;
            out[11] = ~d ^ b;
            out[10] = ~d ^ a;
            out[9] = ~e ^ c;
            out[8] = ~e ^ b;
            out[7] = ~e ^ a;
            out[6] = b ^ c;
            out[5] = b ^ d;
            out[4] = b ^ e;
            out[3] = c ^ d;
            out[2] = c ^ e;
            out[1] = d ^ e;
            out[0] = e ^ e;
        end

endmodule

7:      : 'out['sd13]' is declared here as a wire.
23: error: 'out['sd11]' is not a valid l-value for a procedural assignment.
29: error: 'out['sd5]' is not a valid l-value for a procedural assignment.
7:      : 'out['sd11]' is declared here as a wire.
15: error: 'out['sd19]' is not a valid l-value for a procedural assignment.
31: error: 'out['sd3]' is not a valid l-value for a procedural assignment.
7:      : 'out['sd23]' is declared here as a wire.
7:      : 'out['sd7]' is declared here as a wire.
7:      : 'out['sd16]' is declared here as a wire.
21: error: 'out['sd13]' is not a valid l-value for a procedural assignment.
19: error: 'out['sd15]' is not a valid l-value for a procedural assignment.
27: error: 'out['sd7]' is not a valid l-value for a procedural assignment.
7:      : 'out['sd1]' is declared here as a wire.
7:      : 'out['sd22]' is declared here as a wire.
26: error: 'out['sd8]' is not a valid l-value for a procedural assignment.
7:      : 'out['sd12]' is declared here as a wire.
30: error: 'out['sd4]' is not a valid l-value for a procedural assignment.
7:      : 'out['sd20]' is declared here as a wire.
12: error: 'out['sd22]' is not a valid l-value for a procedural assignment.
33: error: 'out['sd1]' is not a valid l-value for a procedural assignment.
7:      : 'out['sd8]' is declared here as a wire.
7:      : 'out['sd17]' is declared here as a wire.
16: error: 'out['sd18]' is not a valid l-value for a procedural assignment.
7:      : 'out['sd19]' is declared here as a wire.
7:      : 'out['sd0]' is declared here as a wire.
11: error: 'out['sd23]' is not a valid l-value for a procedural assignment.
7:      : 'out['sd9]' is declared here as a wire.
7:      : 'out['sd18]' is declared here as a wire.
7:      : 'out['sd21]' is declared here as a wire.
7:      : 'out['sd5]' is declared here as a wire.
18: error: 'out['sd16]' is not a valid l-value for a procedural assignment.
22: error: 'out['sd12]' is not a valid l-value for a procedural assignment.
10: error: 'out['sd24]' is not a valid l-value for a procedural assignment.
34: error: 'out['sd0]' is not a valid l-value for a procedural assignment.
17: error: 'out['sd17]' is not a valid l-value for a procedural assignment.
7:      : 'out['sd10]' is declared here as a wire.
13: error: 'out['sd21]' is not a valid l-value for a procedural assignment.
20: error: 'out['sd14]' is not a valid l-value for a procedural assignment.
7:      : 'out['sd6]' is declared here as a wire.
7:      : 'out['sd3]' is declared here as a wire.
7:      : 'out['sd4]' is declared here as a wire.
7:      : 'out['sd24]' is declared here as a wire.
32: error: 'out['sd2]' is not a valid l-value for a procedural assignment.
7:      : 'out['sd15]' is declared here as a wire.
9: warning: @* found no sensitivities so it will never trigger.
25: error: 'out['sd9]' is not a valid l-value for a procedural assignment.
7:      : 'out['sd14]' is declared here as a wire.
7:      : 'out['sd2]' is declared here as a wire.
28: error: 'out['sd6]' is not a valid l-value for a procedural assignment.
14: error: 'out['sd20]' is not a valid l-value for a procedural assignment.
24: error: 'out['sd10]' is not a valid l-value for a procedural assignment.


Build a circuit that has two 3-bit inputs that computes the bitwise-OR of the two vectors, the logical-OR of the two vectors, and the inverse (NOT) of both vectors. Place the inverse of b in the upper half of out_not (i.e., bits [5:3]), and the inverse of a in the lower half.

module top_module(
	input [2:0] a,
	input [2:0] b,
	output [2:0] out_or_bitwise,
	output out_or_logical,
	output [5:0] out_not
);

        reg [2:0] a_reg;
        reg [2:0] b_reg;
        reg [2:0] out_or_bitwise_reg;
        reg out_or_logical_reg;
        reg [5:0] out_not_reg;

        always @(posedge clk) begin
            a_reg <= a;
            b_reg <= b;
            out_or_bitwise_reg <= a_reg | b_reg;
            out_or_logical_reg <= |(a_reg | b_reg);
            out_not_reg[5:3] <= ~b_reg;
            out_not_reg[2:0] <= ~a_reg;
        end

        assign out_or_bitwise = out_or_bitwise_reg;
        assign out_or_logical = out_or_logical_reg;
        assign out_not = out_not_reg;

endmodule

15: error: Failed to evaluate event expression 'posedge clk'.
15: error: Unable to bind wire/reg/memory `clk' in `top_module'


Given an 8-bit input vector [7:0], reverse its bit ordering.

module top_module (
	input [7:0] in,
	output [7:0] out
);
 assign out = {in0, in1, in2, in3, in4, in5, in6, in7};

endmodule

5: error: Unable to bind wire/reg/memory `in0' in `top_module'
5: error: Unable to bind wire/reg/memory `in2' in `top_module'
5: error: Unable to bind wire/reg/memory `in1' in `top_module'
5: error: Unable to bind wire/reg/memory `in5' in `top_module'
5: error: Unable to elaborate r-value: {in0, in1, in2, in3, in4, in5, in6, in7}
5: error: Unable to bind wire/reg/memory `in3' in `top_module'
5: error: Unable to bind wire/reg/memory `in4' in `top_module'
5: error: Concatenation/replication may not have zero width in this context.
5: error: Unable to bind wire/reg/memory `in6' in `top_module'
5: error: Unable to bind wire/reg/memory `in7' in `top_module'


module top_module (
	input [7:0] in,
	output [7:0] out
);
 integer i;
             reg [7:0] temp;

             always @(*) begin
                 for (i = 0; i < 8; i = i + 1) begin
                     temp[i] = in[7-i];
                 end
                 out = temp;
             end

endmodule

12: error: 'out' is not a valid l-value for a procedural assignment.
3:      : 'out' is declared here as a wire.


Create a module with 3 inputs and 4 outputs that behaves like wires that makes these connections: a -> w
// ; b -> x; b -> y; c -> z.

module top_module (
	input a,
	input b,
	input c,
	output w,
	output x,
	output y,
	output z  );
 wire a;
         wire b;
         wire c;
         wire w;
         wire x;
         wire y;
         wire z;

         assign w = a;
         assign x = b;
         assign y = b;
         assign z = c;

endmodule

14: error: 'y' has already been declared in this scope.
4:      : It was declared here as a net.
15: error: 'z' has already been declared in this scope.
2:      : It was declared here as a net.
8:      : It was declared here as a net.
13: error: 'x' has already been declared in this scope.
9: error: 'a' has already been declared in this scope.
10: error: 'b' has already been declared in this scope.
5:      : It was declared here as a net.
12: error: 'w' has already been declared in this scope.
7:      : It was declared here as a net.
11: error: 'c' has already been declared in this scope.
3:      : It was declared here as a net.
6:      : It was declared here as a net.


Implement the following circuit. Create two intermediate wires (named anything you want) to connect the AND and OR gates together. Note that the wire that feeds the NOT gate is really wire `out`, so you do not necessarily need to declare a third wire here. Notice how wires are driven by exactly one source (output of a gate), but can feed multiple inputs.

// The circuit is composed of two layers. The first layer, counting from the input, is two AND gates: one whose input is connected to a and b, and the second is connected to c and d. The second layer there is an OR gate to OR the two AND outputs, connected the output 'out'. Additionally, there is an inverted output 'out_n'.

module top_module (
	input a,
	input b,
	input c,
	input d,
	output out,
	output out_n );
 wire and0_out;
             wire and1_out;
             wire or0_out;

             and and0 (
                .a(a),
                .b(b),
                .out(and0_out)
            );

             and and1 (
                .a(c),
                .b(d),
                .out(and1_out)
            );

             or or0 (
                .a(and0_out),
                .b(and1_out),
                .out(or0_out)
            );

             not not0 (
                .a(or0_out),
                .out(out_n)
            );

             buf buf0 (
                .in(or0_out),
                .out(out)
            );

        endmodule

30: error: Gates do not have port names.
24: error: Gates do not have port names.
35: error: Gates do not have port names.
18: error: Gates do not have port names.
12: error: Gates do not have port names.


module top_module (
	input a,
	input b,
	input c,
	input d,
	output out,
	output out_n );
 wire and0_out;
         wire and1_out;
         wire or0_out;

         and and0 (
           .a(a),
           .b(b),
           .o(and0_out)
         );
         and and1 (
           .a(c),
           .b(d),
           .o(and1_out)
         );
         or or0 (
           .a(and0_out),
           .b(and1_out),
           .o(or0_out)
         );
         assign out = or0_out;
         assign out_n = ~or0_out;
       endmodule

17: error: Gates do not have port names.
22: error: Gates do not have port names.
12: error: Gates do not have port names.


Build a circuit that always outputs a LOW.

module top_module(
	output zero);
 // Output port is declared as
         // a wire since it is not connected to
         // any of the logic elements in the design
         wire zero;

         // Assigning a constant value of 1'b0 to the output port
         assign zero = 1'b0;

        endmodule

2:      : It was declared here as a net.
6: error: 'zero' has already been declared in this scope.


module top_module(
	output zero);
 // Output port is declared as
         // a wire.
	wire zero;

	assign zero = 1'b0;

	endmodule

2:      : It was declared here as a net.
5: error: 'zero' has already been declared in this scope.