diff --git "a/build/webgpu/test.json" "b/build/webgpu/test.json" --- "a/build/webgpu/test.json" +++ "b/build/webgpu/test.json" @@ -959,7 +959,7 @@ { "name": "relu_3x3_dense_c256m256_8x8", "provenance": { - "notes": "A compact 3x3 convolution with 256 input and output channels preserves the wide im2col reduction and output-channel dimensions of the subgroup-matrix fallback regime." + "notes": "A 3x3 Relu-activated convolution with 256 input and 256 output channels over an 8x8 spatial output checks a 2304-element reduction." }, "attrs": { "activation": "Relu", "strides": [1, 1], "pads": [1, 1, 1, 1] }, "tolerance": 0.001, @@ -1016,7 +1016,7 @@ { "name": "same_upper_stride2_autopad", "provenance": { - "source": "ONNX Runtime com.microsoft.FusedConv CPUExecutionProvider", + "source": "ONNX Runtime's CPU provider (com.microsoft.FusedConv)", "notes": "FusedConv inherits Conv auto_pad semantics. SAME_UPPER with stride 2 requires trailing padding and a 2x2 output here, exercising padding derived from the official auto_pad and strides attributes." }, "attrs": { "auto_pad": "SAME_UPPER", "activation": "Relu", "strides": [2, 2] }, @@ -1040,7 +1040,7 @@ { "name": "conv1d_relu_direct", "provenance": { - "source": "ONNX Runtime com.microsoft.FusedConv (CPUExecutionProvider)", + "source": "ONNX Runtime's CPU provider (com.microsoft.FusedConv)", "notes": "A compact rank-3 NCW case accepted by ORT evaluates `Relu(Conv1D(X, W))` on the direct one-dimensional path." }, "attrs": { "activation": "Relu" }, @@ -1298,7 +1298,7 @@ { "name": "relu_2x2_im2col_padded_z_n49_c8m32", "provenance": { - "notes": "outputPixels=49 breaks the %64 N alignment the exact im2col subgroup-matrix path demands, so the zero-padded subgroup-matrix GEMM (N padded 49 -> 64) takes the no-bias z-residual route." + "notes": "A 2x2 convolution with 49 output positions, residual input, and fused Relu checks the final partial output tile." }, "attrs": { "activation": "Relu", "strides": [1, 1] }, "tolerance": 0.002, @@ -1375,7 +1375,7 @@ { "name": "group2_3x3_direct_bias_z_inchan4_4x4", "provenance": { - "notes": "Grouped conv carrying both a bias and a z-residual: pins the direct unrolled kernel's full epilogue (bias then residual then activation)." + "notes": "Grouped 3x3 convolution with bias and z-residual checks the complete epilogue order: bias, residual, then activation." }, "attrs": { "group": 2, "activation": "Relu", "strides": [1, 1], "pads": [1, 1, 1, 1] }, "inputs": { @@ -1405,7 +1405,7 @@ { "name": "same_lower_stride2_autopad", "provenance": { - "source": "ONNX Runtime com.microsoft.FusedConv CPUExecutionProvider", + "source": "ONNX Runtime's CPU provider (com.microsoft.FusedConv)", "notes": "ONNX `SAME_LOWER` places an odd padding element at the start of the axis. The nonzero leading pad must be derived from `auto_pad` and strides rather than from explicit pad attributes." }, "attrs": { "auto_pad": "SAME_LOWER", "activation": "Relu", "strides": [2, 2] }, @@ -1487,7 +1487,7 @@ { "name": "implicit_sgmat_identity_tails", "provenance": { - "notes": "Direct-gather boundary lock: K27 pads to32, M tail where nonmultiple, N4097 ends in a one-column output tile; optional bias and residual precede activation in f32 before the single output cast. Nonzero residual/bias prevents a missing epilogue from matching. Uses the narrowed default spatial floor, without forcing tunables." + "notes": "A 27-tap (3x3x3) reduction produces 33 output channels, one more than a multiple of 32, over a 4097-element (17x241) spatial output; no bias, residual or activation is applied." }, "inputs": { "x": { @@ -1508,7 +1508,7 @@ { "name": "implicit_sgmat_relu_bias_direct_tail", "provenance": { - "notes": "Direct-gather boundary lock: K27 pads to32, M tail where nonmultiple, N4097 ends in a one-column output tile; optional bias and residual precede activation in f32 before the single output cast. Nonzero residual/bias prevents a missing epilogue from matching. Uses the narrowed default spatial floor, without forcing tunables." + "notes": "A Relu-activated 3x3 convolution over 3 input channels produces 64 output channels, a multiple of 32, over a 4097-element (17x241) spatial output; a 64-element bias is added before the activation, with no residual." }, "inputs": { "x": { @@ -1535,7 +1535,7 @@ { "name": "implicit_sgmat_tanh_residual_tails", "provenance": { - "notes": "Direct-gather boundary lock: K27 pads to32, M tail where nonmultiple, N4097 ends in a one-column output tile; optional bias and residual precede activation in f32 before the single output cast. Nonzero residual/bias prevents a missing epilogue from matching. Uses the narrowed default spatial floor, without forcing tunables." + "notes": "A Tanh-activated 3x3 convolution over 3 input channels produces 33 output channels, one more than a multiple of 32, over a 4097-element (17x241) spatial output; a matching-shape residual is added before the activation, with no bias." }, "inputs": { "x": { @@ -1562,7 +1562,7 @@ { "name": "implicit_sgmat_leaky_bias_residual_batch_tails", "provenance": { - "notes": "Direct-gather boundary lock: K27 pads to32, M tail where nonmultiple, N4097 ends in a one-column output tile; optional bias and residual precede activation in f32 before the single output cast. Nonzero residual/bias prevents a missing epilogue from matching. Uses the narrowed default spatial floor, without forcing tunables." + "notes": "A LeakyRelu (alpha 0.25) 3x3 convolution over 3 input channels and batch 2 produces 65 output channels, one more than a multiple of 64, over a 4097-element (17x241) spatial output; both a 65-element bias and a matching-shape residual are added before the activation." }, "inputs": { "x": { @@ -1594,7 +1594,7 @@ { "name": "implicit_sgmat_f16_relu_tails", "provenance": { - "notes": "Direct-gather boundary lock: K27 pads to32, M tail where nonmultiple, N4097 ends in a one-column output tile; optional bias and residual precede activation in f32 before the single output cast. Nonzero residual/bias prevents a missing epilogue from matching. Uses the narrowed default spatial floor, without forcing tunables." + "notes": "A float16 Relu-activated 3x3 convolution over 3 input channels produces 33 output channels, one more than a multiple of 32, over a 4097-element (17x241) spatial output; no bias or residual is applied." }, "inputs": { "x": { @@ -1614,7 +1614,7 @@ { "name": "implicit_sgmat_relu_bias_direct_tail_f16", "provenance": { - "notes": "Float16 bias/residual counterpart for the dtype-specific implicit subgroup-matrix config route. M33 stays within the two-tile f16 gate and exercises guarded output storage." + "notes": "A float16 Relu-activated 3x3 convolution over 3 input channels produces 33 output channels, one more than a multiple of 32, over a 4097-element (17x241) spatial output; a 33-element bias is added before the activation, with no residual." }, "inputs": { "x": { @@ -1639,7 +1639,7 @@ { "name": "implicit_sgmat_tanh_residual_tails_f16", "provenance": { - "notes": "Float16 bias/residual counterpart for the dtype-specific implicit subgroup-matrix config route. M33 stays within the two-tile f16 gate and exercises guarded output storage." + "notes": "A float16 Tanh-activated 3x3 convolution over 3 input channels produces 33 output channels, one more than a multiple of 32, over a 4097-element (17x241) spatial output; a matching-shape residual is added before the activation, with no bias." }, "inputs": { "x": { @@ -1664,7 +1664,7 @@ { "name": "implicit_sgmat_leaky_bias_residual_batch_tails_f16", "provenance": { - "notes": "Float16 bias/residual counterpart for the dtype-specific implicit subgroup-matrix config route. M33 stays within the two-tile f16 gate and exercises guarded output storage." + "notes": "A float16 LeakyRelu (alpha 0.25) 3x3 convolution over 3 input channels and batch 2 produces 33 output channels, one more than a multiple of 32, over a 4097-element (17x241) spatial output; both a 33-element bias and a matching-shape residual are added before the activation." }, "inputs": { "x": { @@ -1708,9 +1708,7 @@ }, "outputs": { "y": { "dtype": "float32", "shape": [1, 96, 3, 43], "tolerance": 0.0001, "relTolerance": 0.00002 } }, "tunables": { "IMPLICIT_SGMAT_MAX_M_TILES": 4, "IMPLICIT_SGMAT_MIN_OUTPUT_PIXELS": 128 }, - "provenance": { - "notes": "Compact multi-tile implicit gather with K/N tails. Tunables exercise the kernel without allocating the large memory-boundary workload; selector unit tests separately pin the actual device-limit boundary." - } + "provenance": { "notes": "Compact convolution with partial reduction and output-channel tiles." } }, { "name": "implicit_buffer_fallback_compact_float16", @@ -1729,9 +1727,7 @@ }, "outputs": { "y": { "dtype": "float16", "shape": [1, 96, 3, 43], "tolerance": 0.001, "relTolerance": 0.001 } }, "tunables": { "IMPLICIT_SGMAT_MAX_M_TILES": 4, "IMPLICIT_SGMAT_MIN_OUTPUT_PIXELS": 128 }, - "provenance": { - "notes": "Compact multi-tile implicit gather with K/N tails. Tunables exercise the kernel without allocating the large memory-boundary workload; selector unit tests separately pin the actual device-limit boundary." - } + "provenance": { "notes": "Compact convolution with partial reduction and output-channel tiles." } }, { "name": "implicit_splitk_preferred_grid16_k144", @@ -1750,7 +1746,7 @@ }, "outputs": { "y": { "dtype": "float32", "shape": [1, 64, 32, 32], "tolerance": 0.0001, "relTolerance": 0.0001 } }, "provenance": { - "notes": "Selects the preferred implicit split-K route at its output-grid boundary; nonuniform data exercises reduction and fused activation." + "notes": "Nonuniform 3x3 convolution data at a compact output-grid boundary checks reduction and fused activation." } }, { @@ -1775,13 +1771,13 @@ }, "outputs": { "y": { "dtype": "float32", "shape": [1, 65, 32, 32], "tolerance": 0.0001, "relTolerance": 0.0001 } }, "provenance": { - "notes": "Selects the preferred implicit split-K route at its output-grid boundary; nonuniform data exercises reduction and fused activation." + "notes": "Nonuniform 3x3 convolution data at a compact output-grid boundary checks reduction and fused activation." } }, { "name": "direct_matrix_inputs_m32_c32_h8_w8_mode0", "provenance": { - "notes": "Aligned materialized-input matrix geometry and adjacent rejection boundaries; bias and residual are nonzero and precede activation in f32. Original portable and staged paths remain the oracle controls." + "notes": "Aligned materialized-input matrix geometry and adjacent rejection boundaries; bias and residual are nonzero and precede activation in f32. The portable and staged paths serve as controls." }, "inputs": { "x": { @@ -1807,7 +1803,7 @@ { "name": "direct_matrix_inputs_m32_c32_h8_w8_mode1", "provenance": { - "notes": "Aligned materialized-input matrix geometry and adjacent rejection boundaries; bias and residual are nonzero and precede activation in f32. Original portable and staged paths remain the oracle controls." + "notes": "Aligned materialized-input matrix geometry and adjacent rejection boundaries; bias and residual are nonzero and precede activation in f32. The portable and staged paths serve as controls." }, "inputs": { "x": { @@ -1838,7 +1834,7 @@ { "name": "direct_matrix_inputs_m32_c32_h8_w8_mode2", "provenance": { - "notes": "Aligned materialized-input matrix geometry and adjacent rejection boundaries; bias and residual are nonzero and precede activation in f32. Original portable and staged paths remain the oracle controls." + "notes": "Aligned materialized-input matrix geometry and adjacent rejection boundaries; bias and residual are nonzero and precede activation in f32. The portable and staged paths serve as controls." }, "inputs": { "x": { @@ -1875,7 +1871,7 @@ { "name": "direct_matrix_inputs_m32_c32_h8_w8_mode3", "provenance": { - "notes": "Aligned materialized-input matrix geometry and adjacent rejection boundaries; bias and residual are nonzero and precede activation in f32. Original portable and staged paths remain the oracle controls." + "notes": "Aligned materialized-input matrix geometry and adjacent rejection boundaries; bias and residual are nonzero and precede activation in f32. The portable and staged paths serve as controls." }, "inputs": { "x": { @@ -1917,7 +1913,7 @@ { "name": "direct_matrix_inputs_m64_c32_h8_w8_mode0", "provenance": { - "notes": "Aligned materialized-input matrix geometry and adjacent rejection boundaries; bias and residual are nonzero and precede activation in f32. Original portable and staged paths remain the oracle controls." + "notes": "Aligned materialized-input matrix geometry and adjacent rejection boundaries; bias and residual are nonzero and precede activation in f32. The portable and staged paths serve as controls." }, "inputs": { "x": { @@ -1943,7 +1939,7 @@ { "name": "direct_matrix_inputs_m64_c32_h8_w8_mode1", "provenance": { - "notes": "Aligned materialized-input matrix geometry and adjacent rejection boundaries; bias and residual are nonzero and precede activation in f32. Original portable and staged paths remain the oracle controls." + "notes": "Aligned materialized-input matrix geometry and adjacent rejection boundaries; bias and residual are nonzero and precede activation in f32. The portable and staged paths serve as controls." }, "inputs": { "x": { @@ -1974,7 +1970,7 @@ { "name": "direct_matrix_inputs_m64_c32_h8_w8_mode2", "provenance": { - "notes": "Aligned materialized-input matrix geometry and adjacent rejection boundaries; bias and residual are nonzero and precede activation in f32. Original portable and staged paths remain the oracle controls." + "notes": "Aligned materialized-input matrix geometry and adjacent rejection boundaries; bias and residual are nonzero and precede activation in f32. The portable and staged paths serve as controls." }, "inputs": { "x": { @@ -2011,7 +2007,7 @@ { "name": "direct_matrix_inputs_m64_c32_h8_w8_mode3", "provenance": { - "notes": "Aligned materialized-input matrix geometry and adjacent rejection boundaries; bias and residual are nonzero and precede activation in f32. Original portable and staged paths remain the oracle controls." + "notes": "Aligned materialized-input matrix geometry and adjacent rejection boundaries; bias and residual are nonzero and precede activation in f32. The portable and staged paths serve as controls." }, "inputs": { "x": { @@ -2053,7 +2049,7 @@ { "name": "direct_matrix_inputs_m128_c32_h8_w8_mode0", "provenance": { - "notes": "Aligned materialized-input matrix geometry and adjacent rejection boundaries; bias and residual are nonzero and precede activation in f32. Original portable and staged paths remain the oracle controls." + "notes": "Aligned materialized-input matrix geometry and adjacent rejection boundaries; bias and residual are nonzero and precede activation in f32. The portable and staged paths serve as controls." }, "inputs": { "x": { @@ -2079,7 +2075,7 @@ { "name": "direct_matrix_inputs_m128_c32_h8_w8_mode1", "provenance": { - "notes": "Aligned materialized-input matrix geometry and adjacent rejection boundaries; bias and residual are nonzero and precede activation in f32. Original portable and staged paths remain the oracle controls." + "notes": "Aligned materialized-input matrix geometry and adjacent rejection boundaries; bias and residual are nonzero and precede activation in f32. The portable and staged paths serve as controls." }, "inputs": { "x": { @@ -2110,7 +2106,7 @@ { "name": "direct_matrix_inputs_m128_c32_h8_w8_mode2", "provenance": { - "notes": "Aligned materialized-input matrix geometry and adjacent rejection boundaries; bias and residual are nonzero and precede activation in f32. Original portable and staged paths remain the oracle controls." + "notes": "Aligned materialized-input matrix geometry and adjacent rejection boundaries; bias and residual are nonzero and precede activation in f32. The portable and staged paths serve as controls." }, "inputs": { "x": { @@ -2147,7 +2143,7 @@ { "name": "direct_matrix_inputs_m128_c32_h8_w8_mode3", "provenance": { - "notes": "Aligned materialized-input matrix geometry and adjacent rejection boundaries; bias and residual are nonzero and precede activation in f32. Original portable and staged paths remain the oracle controls." + "notes": "Aligned materialized-input matrix geometry and adjacent rejection boundaries; bias and residual are nonzero and precede activation in f32. The portable and staged paths serve as controls." }, "inputs": { "x": { @@ -2189,7 +2185,7 @@ { "name": "direct_matrix_inputs_m31_c32_h8_w8_mode0", "provenance": { - "notes": "Aligned materialized-input matrix geometry and adjacent rejection boundaries; bias and residual are nonzero and precede activation in f32. Original portable and staged paths remain the oracle controls." + "notes": "Aligned materialized-input matrix geometry and adjacent rejection boundaries; bias and residual are nonzero and precede activation in f32. The portable and staged paths serve as controls." }, "inputs": { "x": { @@ -2215,7 +2211,7 @@ { "name": "direct_matrix_inputs_m33_c32_h8_w8_mode0", "provenance": { - "notes": "Aligned materialized-input matrix geometry and adjacent rejection boundaries; bias and residual are nonzero and precede activation in f32. Original portable and staged paths remain the oracle controls." + "notes": "Aligned materialized-input matrix geometry and adjacent rejection boundaries; bias and residual are nonzero and precede activation in f32. The portable and staged paths serve as controls." }, "inputs": { "x": { @@ -2241,7 +2237,7 @@ { "name": "direct_matrix_inputs_m65_c32_h8_w8_mode0", "provenance": { - "notes": "Aligned materialized-input matrix geometry and adjacent rejection boundaries; bias and residual are nonzero and precede activation in f32. Original portable and staged paths remain the oracle controls." + "notes": "Aligned materialized-input matrix geometry and adjacent rejection boundaries; bias and residual are nonzero and precede activation in f32. The portable and staged paths serve as controls." }, "inputs": { "x": { @@ -2267,7 +2263,7 @@ { "name": "direct_matrix_inputs_m64_c31_h8_w8_mode0", "provenance": { - "notes": "Aligned materialized-input matrix geometry and adjacent rejection boundaries; bias and residual are nonzero and precede activation in f32. Original portable and staged paths remain the oracle controls." + "notes": "Aligned materialized-input matrix geometry and adjacent rejection boundaries; bias and residual are nonzero and precede activation in f32. The portable and staged paths serve as controls." }, "inputs": { "x": { @@ -2293,7 +2289,7 @@ { "name": "direct_matrix_inputs_m64_c32_h7_w9_mode0", "provenance": { - "notes": "Aligned materialized-input matrix geometry and adjacent rejection boundaries; bias and residual are nonzero and precede activation in f32. Original portable and staged paths remain the oracle controls." + "notes": "Aligned materialized-input matrix geometry and adjacent rejection boundaries; bias and residual are nonzero and precede activation in f32. The portable and staged paths serve as controls." }, "inputs": { "x": { @@ -2319,7 +2315,7 @@ { "name": "half_direct_matrix_inputs_m32_c32_h8_w8_mode0", "provenance": { - "notes": "Aligned f16 materialized columns select direct subgroup-matrix inputs with half-sized scratch. Exercise row groups, batch indexing and each fused epilogue while retaining the existing f32 accumulation and f16 oracle tolerance." + "notes": "Aligned float16 3x3 convolution with 32 output channels, batch one, and no bias, residual, or activation checks float32 accumulation at float16 reference tolerance." }, "inputs": { "x": { @@ -2345,7 +2341,7 @@ { "name": "half_direct_matrix_inputs_m32_c32_h8_w8_mode1", "provenance": { - "notes": "Aligned f16 materialized columns select direct subgroup-matrix inputs with half-sized scratch. Exercise row groups, batch indexing and each fused epilogue while retaining the existing f32 accumulation and f16 oracle tolerance." + "notes": "Aligned float16 3x3 convolution with 32 output channels, batch one, channel bias, and fused Relu checks float32 accumulation at float16 reference tolerance." }, "inputs": { "x": { @@ -2376,7 +2372,7 @@ { "name": "half_direct_matrix_inputs_m32_c32_h8_w8_mode2", "provenance": { - "notes": "Aligned f16 materialized columns select direct subgroup-matrix inputs with half-sized scratch. Exercise row groups, batch indexing and each fused epilogue while retaining the existing f32 accumulation and f16 oracle tolerance." + "notes": "Aligned float16 3x3 convolution with 32 output channels, batch one, a residual input, and fused Tanh checks float32 accumulation at float16 reference tolerance." }, "inputs": { "x": { @@ -2413,7 +2409,7 @@ { "name": "half_direct_matrix_inputs_m32_c32_h8_w8_mode3", "provenance": { - "notes": "Aligned f16 materialized columns select direct subgroup-matrix inputs with half-sized scratch. Exercise row groups, batch indexing and each fused epilogue while retaining the existing f32 accumulation and f16 oracle tolerance." + "notes": "Aligned float16 convolution inputs with fused epilogues check row groups, batch indexing, and float32 accumulation at float16 reference tolerance." }, "inputs": { "x": { @@ -2455,7 +2451,7 @@ { "name": "half_direct_matrix_inputs_m64_c32_h8_w8_mode0", "provenance": { - "notes": "Aligned f16 materialized columns select direct subgroup-matrix inputs with half-sized scratch. Exercise row groups, batch indexing and each fused epilogue while retaining the existing f32 accumulation and f16 oracle tolerance." + "notes": "Aligned float16 3x3 convolution with 64 output channels, batch one, and no bias, residual, or activation checks float32 accumulation at float16 reference tolerance." }, "inputs": { "x": { @@ -2481,7 +2477,7 @@ { "name": "half_direct_matrix_inputs_m64_c32_h8_w8_mode1", "provenance": { - "notes": "Aligned f16 materialized columns select direct subgroup-matrix inputs with half-sized scratch. Exercise row groups, batch indexing and each fused epilogue while retaining the existing f32 accumulation and f16 oracle tolerance." + "notes": "Aligned float16 3x3 convolution with 64 output channels, batch one, channel bias, and fused Relu checks float32 accumulation at float16 reference tolerance." }, "inputs": { "x": { @@ -2512,7 +2508,7 @@ { "name": "half_direct_matrix_inputs_m64_c32_h8_w8_mode2", "provenance": { - "notes": "Aligned f16 materialized columns select direct subgroup-matrix inputs with half-sized scratch. Exercise row groups, batch indexing and each fused epilogue while retaining the existing f32 accumulation and f16 oracle tolerance." + "notes": "Aligned float16 3x3 convolution with 64 output channels, batch one, a residual input, and fused Tanh checks float32 accumulation at float16 reference tolerance." }, "inputs": { "x": { @@ -2549,7 +2545,7 @@ { "name": "half_direct_matrix_inputs_m64_c32_h8_w8_mode3", "provenance": { - "notes": "Aligned f16 materialized columns select direct subgroup-matrix inputs with half-sized scratch. Exercise row groups, batch indexing and each fused epilogue while retaining the existing f32 accumulation and f16 oracle tolerance." + "notes": "Aligned float16 convolution inputs with fused epilogues check row groups, batch indexing, and float32 accumulation at float16 reference tolerance." }, "inputs": { "x": { @@ -2591,7 +2587,7 @@ { "name": "half_direct_matrix_inputs_m96_c32_h8_w8_mode0", "provenance": { - "notes": "Aligned f16 materialized columns select direct subgroup-matrix inputs with half-sized scratch. Exercise row groups, batch indexing and each fused epilogue while retaining the existing f32 accumulation and f16 oracle tolerance." + "notes": "Aligned float16 3x3 convolution with 96 output channels, batch one, and no bias, residual, or activation checks float32 accumulation at float16 reference tolerance." }, "inputs": { "x": { @@ -2617,7 +2613,7 @@ { "name": "half_direct_matrix_inputs_m96_c32_h8_w8_mode1", "provenance": { - "notes": "Aligned f16 materialized columns select direct subgroup-matrix inputs with half-sized scratch. Exercise row groups, batch indexing and each fused epilogue while retaining the existing f32 accumulation and f16 oracle tolerance." + "notes": "Aligned float16 3x3 convolution with 96 output channels, batch one, channel bias, and fused Relu checks float32 accumulation at float16 reference tolerance." }, "inputs": { "x": { @@ -2648,7 +2644,7 @@ { "name": "half_direct_matrix_inputs_m96_c32_h8_w8_mode2", "provenance": { - "notes": "Aligned f16 materialized columns select direct subgroup-matrix inputs with half-sized scratch. Exercise row groups, batch indexing and each fused epilogue while retaining the existing f32 accumulation and f16 oracle tolerance." + "notes": "Aligned float16 3x3 convolution with 96 output channels, batch one, a residual input, and fused Tanh checks float32 accumulation at float16 reference tolerance." }, "inputs": { "x": { @@ -2685,7 +2681,7 @@ { "name": "half_direct_matrix_inputs_m96_c32_h8_w8_mode3", "provenance": { - "notes": "Aligned f16 materialized columns select direct subgroup-matrix inputs with half-sized scratch. Exercise row groups, batch indexing and each fused epilogue while retaining the existing f32 accumulation and f16 oracle tolerance." + "notes": "Aligned float16 convolution inputs with fused epilogues check row groups, batch indexing, and float32 accumulation at float16 reference tolerance." }, "inputs": { "x": { @@ -2727,7 +2723,7 @@ { "name": "half_direct_matrix_inputs_m128_c32_h8_w8_mode0", "provenance": { - "notes": "Aligned f16 materialized columns select direct subgroup-matrix inputs with half-sized scratch. Exercise row groups, batch indexing and each fused epilogue while retaining the existing f32 accumulation and f16 oracle tolerance." + "notes": "Aligned float16 3x3 convolution with 128 output channels, batch one, and no bias, residual, or activation checks float32 accumulation at float16 reference tolerance." }, "inputs": { "x": { @@ -2753,7 +2749,7 @@ { "name": "half_direct_matrix_inputs_m128_c32_h8_w8_mode1", "provenance": { - "notes": "Aligned f16 materialized columns select direct subgroup-matrix inputs with half-sized scratch. Exercise row groups, batch indexing and each fused epilogue while retaining the existing f32 accumulation and f16 oracle tolerance." + "notes": "Aligned float16 3x3 convolution with 128 output channels, batch one, channel bias, and fused Relu checks float32 accumulation at float16 reference tolerance." }, "inputs": { "x": { @@ -2784,7 +2780,7 @@ { "name": "half_direct_matrix_inputs_m128_c32_h8_w8_mode2", "provenance": { - "notes": "Aligned f16 materialized columns select direct subgroup-matrix inputs with half-sized scratch. Exercise row groups, batch indexing and each fused epilogue while retaining the existing f32 accumulation and f16 oracle tolerance." + "notes": "Aligned float16 3x3 convolution with 128 output channels, batch one, a residual input, and fused Tanh checks float32 accumulation at float16 reference tolerance." }, "inputs": { "x": { @@ -2821,7 +2817,7 @@ { "name": "half_direct_matrix_inputs_m128_c32_h8_w8_mode3", "provenance": { - "notes": "Aligned f16 materialized columns select direct subgroup-matrix inputs with half-sized scratch. Exercise row groups, batch indexing and each fused epilogue while retaining the existing f32 accumulation and f16 oracle tolerance." + "notes": "Aligned float16 convolution inputs with fused epilogues check row groups, batch indexing, and float32 accumulation at float16 reference tolerance." }, "inputs": { "x": { @@ -2863,7 +2859,7 @@ { "name": "half_direct_matrix_inputs_m31_c32_h8_w8_mode0", "provenance": { - "notes": "The direct f16 column path rejects incomplete output rows, reduction tiles and spatial tiles; retain the existing guarded fallback and oracle tolerance." + "notes": "The direct f16 column path rejects incomplete output rows, reduction tiles and spatial tiles, which take the guarded fallback at the same reference tolerance." }, "inputs": { "x": { @@ -2889,7 +2885,7 @@ { "name": "half_direct_matrix_inputs_m33_c32_h8_w8_mode0", "provenance": { - "notes": "The direct f16 column path rejects incomplete output rows, reduction tiles and spatial tiles; retain the existing guarded fallback and oracle tolerance." + "notes": "The direct f16 column path rejects incomplete output rows, reduction tiles and spatial tiles, which take the guarded fallback at the same reference tolerance." }, "inputs": { "x": { @@ -2915,7 +2911,7 @@ { "name": "half_direct_matrix_inputs_m65_c32_h8_w8_mode0", "provenance": { - "notes": "The direct f16 column path rejects incomplete output rows, reduction tiles and spatial tiles; retain the existing guarded fallback and oracle tolerance." + "notes": "The direct f16 column path rejects incomplete output rows, reduction tiles and spatial tiles, which take the guarded fallback at the same reference tolerance." }, "inputs": { "x": { @@ -2941,7 +2937,7 @@ { "name": "half_direct_matrix_inputs_m64_c31_h8_w8_mode0", "provenance": { - "notes": "The direct f16 column path rejects incomplete output rows, reduction tiles and spatial tiles; retain the existing guarded fallback and oracle tolerance." + "notes": "The direct f16 column path rejects incomplete output rows, reduction tiles and spatial tiles, which take the guarded fallback at the same reference tolerance." }, "inputs": { "x": { @@ -2967,7 +2963,7 @@ { "name": "half_direct_matrix_inputs_m64_c32_h7_w9_mode0", "provenance": { - "notes": "The direct f16 column path rejects incomplete output rows, reduction tiles and spatial tiles; retain the existing guarded fallback and oracle tolerance." + "notes": "The direct f16 column path rejects incomplete output rows, reduction tiles and spatial tiles, which take the guarded fallback at the same reference tolerance." }, "inputs": { "x": { @@ -2993,7 +2989,7 @@ { "name": "direct_1x1_float32_m32_k32_n64_mode0", "provenance": { - "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles retain guarded staging or the existing fallback; device limits determine the row tile." + "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles take guarded staging or the fallback route; device limits determine the row tile." }, "attrs": { "pads": [0, 0, 0, 0] }, "inputs": { @@ -3013,7 +3009,7 @@ { "name": "direct_1x1_float32_m32_k32_n64_mode1", "provenance": { - "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles retain guarded staging or the existing fallback; device limits determine the row tile." + "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles take guarded staging or the fallback route; device limits determine the row tile." }, "attrs": { "pads": [0, 0, 0, 0], "activation": "Relu" }, "inputs": { @@ -3038,7 +3034,7 @@ { "name": "direct_1x1_float32_m32_k32_n64_mode2", "provenance": { - "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles retain guarded staging or the existing fallback; device limits determine the row tile." + "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles take guarded staging or the fallback route; device limits determine the row tile." }, "attrs": { "pads": [0, 0, 0, 0], "activation": "Tanh" }, "inputs": { @@ -3063,7 +3059,7 @@ { "name": "direct_1x1_float32_m32_k32_n64_mode3", "provenance": { - "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles retain guarded staging or the existing fallback; device limits determine the row tile." + "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles take guarded staging or the fallback route; device limits determine the row tile." }, "attrs": { "pads": [0, 0, 0, 0], "activation": "LeakyRelu", "activation_params": [0.25] }, "inputs": { @@ -3093,7 +3089,7 @@ { "name": "direct_1x1_float32_m64_k32_n64_mode0", "provenance": { - "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles retain guarded staging or the existing fallback; device limits determine the row tile." + "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles take guarded staging or the fallback route; device limits determine the row tile." }, "attrs": { "pads": [0, 0, 0, 0] }, "inputs": { @@ -3113,7 +3109,7 @@ { "name": "direct_1x1_float32_m64_k32_n64_mode1", "provenance": { - "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles retain guarded staging or the existing fallback; device limits determine the row tile." + "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles take guarded staging or the fallback route; device limits determine the row tile." }, "attrs": { "pads": [0, 0, 0, 0], "activation": "Relu" }, "inputs": { @@ -3138,7 +3134,7 @@ { "name": "direct_1x1_float32_m64_k32_n64_mode2", "provenance": { - "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles retain guarded staging or the existing fallback; device limits determine the row tile." + "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles take guarded staging or the fallback route; device limits determine the row tile." }, "attrs": { "pads": [0, 0, 0, 0], "activation": "Tanh" }, "inputs": { @@ -3163,7 +3159,7 @@ { "name": "direct_1x1_float32_m64_k32_n64_mode3", "provenance": { - "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles retain guarded staging or the existing fallback; device limits determine the row tile." + "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles take guarded staging or the fallback route; device limits determine the row tile." }, "attrs": { "pads": [0, 0, 0, 0], "activation": "LeakyRelu", "activation_params": [0.25] }, "inputs": { @@ -3193,7 +3189,7 @@ { "name": "direct_1x1_float32_m33_k32_n64_mode0", "provenance": { - "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles retain guarded staging or the existing fallback; device limits determine the row tile." + "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles take guarded staging or the fallback route; device limits determine the row tile." }, "attrs": { "pads": [0, 0, 0, 0] }, "inputs": { @@ -3213,7 +3209,7 @@ { "name": "direct_1x1_float32_m65_k32_n64_mode0", "provenance": { - "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles retain guarded staging or the existing fallback; device limits determine the row tile." + "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles take guarded staging or the fallback route; device limits determine the row tile." }, "attrs": { "pads": [0, 0, 0, 0] }, "inputs": { @@ -3233,7 +3229,7 @@ { "name": "direct_1x1_float32_m96_k32_n64_mode0", "provenance": { - "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles retain guarded staging or the existing fallback; device limits determine the row tile." + "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles take guarded staging or the fallback route; device limits determine the row tile." }, "attrs": { "pads": [0, 0, 0, 0] }, "inputs": { @@ -3253,7 +3249,7 @@ { "name": "direct_1x1_float32_m64_k31_n64_mode0", "provenance": { - "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles retain guarded staging or the existing fallback; device limits determine the row tile." + "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles take guarded staging or the fallback route; device limits determine the row tile." }, "attrs": { "pads": [0, 0, 0, 0] }, "inputs": { @@ -3273,7 +3269,7 @@ { "name": "direct_1x1_float32_m64_k33_n64_mode0", "provenance": { - "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles retain guarded staging or the existing fallback; device limits determine the row tile." + "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles take guarded staging or the fallback route; device limits determine the row tile." }, "attrs": { "pads": [0, 0, 0, 0] }, "inputs": { @@ -3293,7 +3289,7 @@ { "name": "direct_1x1_float32_m64_k32_n63_mode0", "provenance": { - "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles retain guarded staging or the existing fallback; device limits determine the row tile." + "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles take guarded staging or the fallback route; device limits determine the row tile." }, "attrs": { "pads": [0, 0, 0, 0] }, "inputs": { @@ -3313,7 +3309,7 @@ { "name": "direct_1x1_float32_m64_k32_n65_mode0", "provenance": { - "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles retain guarded staging or the existing fallback; device limits determine the row tile." + "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles take guarded staging or the fallback route; device limits determine the row tile." }, "attrs": { "pads": [0, 0, 0, 0] }, "inputs": { @@ -3333,7 +3329,7 @@ { "name": "direct_1x1_float16_m32_k32_n64_mode0", "provenance": { - "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles retain guarded staging or the existing fallback; device limits determine the row tile." + "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles take guarded staging or the fallback route; device limits determine the row tile." }, "attrs": { "pads": [0, 0, 0, 0] }, "inputs": { @@ -3353,7 +3349,7 @@ { "name": "direct_1x1_float16_m32_k32_n64_mode1", "provenance": { - "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles retain guarded staging or the existing fallback; device limits determine the row tile." + "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles take guarded staging or the fallback route; device limits determine the row tile." }, "attrs": { "pads": [0, 0, 0, 0], "activation": "Relu" }, "inputs": { @@ -3378,7 +3374,7 @@ { "name": "direct_1x1_float16_m32_k32_n64_mode2", "provenance": { - "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles retain guarded staging or the existing fallback; device limits determine the row tile." + "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles take guarded staging or the fallback route; device limits determine the row tile." }, "attrs": { "pads": [0, 0, 0, 0], "activation": "Tanh" }, "inputs": { @@ -3403,7 +3399,7 @@ { "name": "direct_1x1_float16_m32_k32_n64_mode3", "provenance": { - "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles retain guarded staging or the existing fallback; device limits determine the row tile." + "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles take guarded staging or the fallback route; device limits determine the row tile." }, "attrs": { "pads": [0, 0, 0, 0], "activation": "LeakyRelu", "activation_params": [0.25] }, "inputs": { @@ -3433,7 +3429,7 @@ { "name": "direct_1x1_float16_m64_k32_n64_mode0", "provenance": { - "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles retain guarded staging or the existing fallback; device limits determine the row tile." + "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles take guarded staging or the fallback route; device limits determine the row tile." }, "attrs": { "pads": [0, 0, 0, 0] }, "inputs": { @@ -3453,7 +3449,7 @@ { "name": "direct_1x1_float16_m64_k32_n64_mode1", "provenance": { - "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles retain guarded staging or the existing fallback; device limits determine the row tile." + "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles take guarded staging or the fallback route; device limits determine the row tile." }, "attrs": { "pads": [0, 0, 0, 0], "activation": "Relu" }, "inputs": { @@ -3478,7 +3474,7 @@ { "name": "direct_1x1_float16_m64_k32_n64_mode2", "provenance": { - "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles retain guarded staging or the existing fallback; device limits determine the row tile." + "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles take guarded staging or the fallback route; device limits determine the row tile." }, "attrs": { "pads": [0, 0, 0, 0], "activation": "Tanh" }, "inputs": { @@ -3503,7 +3499,7 @@ { "name": "direct_1x1_float16_m64_k32_n64_mode3", "provenance": { - "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles retain guarded staging or the existing fallback; device limits determine the row tile." + "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles take guarded staging or the fallback route; device limits determine the row tile." }, "attrs": { "pads": [0, 0, 0, 0], "activation": "LeakyRelu", "activation_params": [0.25] }, "inputs": { @@ -3533,7 +3529,7 @@ { "name": "direct_1x1_float16_m33_k32_n64_mode0", "provenance": { - "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles retain guarded staging or the existing fallback; device limits determine the row tile." + "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles take guarded staging or the fallback route; device limits determine the row tile." }, "attrs": { "pads": [0, 0, 0, 0] }, "inputs": { @@ -3553,7 +3549,7 @@ { "name": "direct_1x1_float16_m65_k32_n64_mode0", "provenance": { - "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles retain guarded staging or the existing fallback; device limits determine the row tile." + "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles take guarded staging or the fallback route; device limits determine the row tile." }, "attrs": { "pads": [0, 0, 0, 0] }, "inputs": { @@ -3573,7 +3569,7 @@ { "name": "direct_1x1_float16_m96_k32_n64_mode0", "provenance": { - "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles retain guarded staging or the existing fallback; device limits determine the row tile." + "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles take guarded staging or the fallback route; device limits determine the row tile." }, "attrs": { "pads": [0, 0, 0, 0] }, "inputs": { @@ -3593,7 +3589,7 @@ { "name": "direct_1x1_float16_m64_k31_n64_mode0", "provenance": { - "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles retain guarded staging or the existing fallback; device limits determine the row tile." + "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles take guarded staging or the fallback route; device limits determine the row tile." }, "attrs": { "pads": [0, 0, 0, 0] }, "inputs": { @@ -3613,7 +3609,7 @@ { "name": "direct_1x1_float16_m64_k33_n64_mode0", "provenance": { - "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles retain guarded staging or the existing fallback; device limits determine the row tile." + "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles take guarded staging or the fallback route; device limits determine the row tile." }, "attrs": { "pads": [0, 0, 0, 0] }, "inputs": { @@ -3633,7 +3629,7 @@ { "name": "direct_1x1_float16_m64_k32_n63_mode0", "provenance": { - "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles retain guarded staging or the existing fallback; device limits determine the row tile." + "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles take guarded staging or the fallback route; device limits determine the row tile." }, "attrs": { "pads": [0, 0, 0, 0] }, "inputs": { @@ -3653,7 +3649,7 @@ { "name": "direct_1x1_float16_m64_k32_n65_mode0", "provenance": { - "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles retain guarded staging or the existing fallback; device limits determine the row tile." + "notes": "Batched direct 1x1 matrix loads cover both scalar widths and fused epilogues. Neighboring incomplete M/K/N tiles take guarded staging or the fallback route; device limits determine the row tile." }, "attrs": { "pads": [0, 0, 0, 0] }, "inputs": { @@ -3669,6 +3665,5959 @@ } }, "outputs": { "y": { "dtype": "float16", "shape": [2, 64, 1, 65], "tolerance": 0.001, "relTolerance": 0.001 } } + }, + { + "name": "half_columns_short_k_batched", + "provenance": { + "notes": "Float16 convolution with spatial and channel tails, batches, padding and epilogues checks full-output parity against the CPU reference." + }, + "attrs": { "strides": [1, 1], "pads": [1, 1, 1, 1], "dilations": [1, 1] }, + "inputs": { + "x": { + "dtype": "float16", + "shape": [2, 1, 1, 513], + "data": { "kind": "fillFloat32", "sinStep": 0.013, "cosStep": 0.027, "scale": 0.2, "offset": 0.0 } + }, + "w": { + "dtype": "float16", + "shape": [512, 1, 3, 3], + "data": { "kind": "fillFloat32", "sinStep": 0.017, "cosStep": 0.03, "scale": 0.1, "offset": 0.0 } + } + }, + "outputs": { "y": { "dtype": "float16", "shape": [2, 512, 1, 513], "tolerance": 0.001, "relTolerance": 0.001 } } + }, + { + "name": "half_columns_batch_channel_tails", + "provenance": { + "notes": "Float16 convolution with spatial and channel tails, batches, padding and epilogues checks full-output parity against the CPU reference." + }, + "attrs": { "strides": [1, 1], "pads": [1, 1, 1, 1], "dilations": [1, 1], "activation": "Relu" }, + "inputs": { + "x": { + "dtype": "float16", + "shape": [2, 3, 17, 31], + "data": { "kind": "fillFloat32", "sinStep": 0.013, "cosStep": 0.027, "scale": 0.2, "offset": 0.0 } + }, + "w": { + "dtype": "float16", + "shape": [257, 3, 3, 3], + "data": { "kind": "fillFloat32", "sinStep": 0.017, "cosStep": 0.03, "scale": 0.1, "offset": 0.0 } + }, + "bias": { + "dtype": "float16", + "shape": [257], + "data": { + "kind": "fillFloat32", + "sinStep": 0.020999999999999998, + "cosStep": 0.033, + "scale": 0.05, + "offset": 0.03 + } + } + }, + "outputs": { "y": { "dtype": "float16", "shape": [2, 257, 17, 31], "tolerance": 0.001, "relTolerance": 0.001 } } + }, + { + "name": "half_columns_leakyrelu_odd_k", + "provenance": { + "notes": "Float16 convolution with spatial and channel tails, batches, padding and epilogues checks full-output parity against the CPU reference." + }, + "attrs": { + "strides": [1, 1], + "pads": [1, 1, 1, 1], + "dilations": [1, 1], + "activation": "LeakyRelu", + "activation_params": [0.25] + }, + "inputs": { + "x": { + "dtype": "float16", + "shape": [1, 7, 17, 31], + "data": { "kind": "fillFloat32", "sinStep": 0.013, "cosStep": 0.027, "scale": 0.2, "offset": 0.0 } + }, + "w": { + "dtype": "float16", + "shape": [512, 7, 3, 3], + "data": { "kind": "fillFloat32", "sinStep": 0.017, "cosStep": 0.03, "scale": 0.1, "offset": 0.0 } + }, + "bias": { + "dtype": "float16", + "shape": [512], + "data": { + "kind": "fillFloat32", + "sinStep": 0.020999999999999998, + "cosStep": 0.033, + "scale": 0.05, + "offset": 0.03 + } + } + }, + "outputs": { "y": { "dtype": "float16", "shape": [1, 512, 17, 31], "tolerance": 0.001, "relTolerance": 0.001 } } + }, + { + "name": "half_columns_even_k", + "provenance": { + "notes": "Float16 convolution with spatial and channel tails, batches, padding and epilogues checks full-output parity against the CPU reference." + }, + "attrs": { "strides": [1, 1], "pads": [1, 1, 1, 1], "dilations": [1, 1] }, + "inputs": { + "x": { + "dtype": "float16", + "shape": [1, 32, 16, 32], + "data": { "kind": "fillFloat32", "sinStep": 0.013, "cosStep": 0.027, "scale": 0.2, "offset": 0.0 } + }, + "w": { + "dtype": "float16", + "shape": [512, 32, 3, 3], + "data": { "kind": "fillFloat32", "sinStep": 0.017, "cosStep": 0.03, "scale": 0.1, "offset": 0.0 } + } + }, + "outputs": { "y": { "dtype": "float16", "shape": [1, 512, 16, 32], "tolerance": 0.001, "relTolerance": 0.001 } } + }, + { + "name": "half_columns_odd_k", + "provenance": { + "notes": "Float16 convolution with spatial and channel tails, batches, padding and epilogues checks full-output parity against the CPU reference." + }, + "attrs": { "strides": [1, 1], "pads": [1, 1, 1, 1], "dilations": [1, 1], "activation": "Relu" }, + "inputs": { + "x": { + "dtype": "float16", + "shape": [1, 33, 17, 31], + "data": { "kind": "fillFloat32", "sinStep": 0.013, "cosStep": 0.027, "scale": 0.2, "offset": 0.0 } + }, + "w": { + "dtype": "float16", + "shape": [512, 33, 3, 3], + "data": { "kind": "fillFloat32", "sinStep": 0.017, "cosStep": 0.03, "scale": 0.1, "offset": 0.0 } + } + }, + "outputs": { "y": { "dtype": "float16", "shape": [1, 512, 17, 31], "tolerance": 0.001, "relTolerance": 0.001 } } + }, + { + "name": "half_columns_stride2_asymmetric_pad", + "provenance": { + "notes": "Float16 convolution with spatial and channel tails, batches, padding and epilogues checks full-output parity against the CPU reference." + }, + "attrs": { "strides": [2, 2], "pads": [1, 2, 1, 0], "dilations": [1, 1], "activation": "Relu" }, + "inputs": { + "x": { + "dtype": "float16", + "shape": [2, 3, 33, 61], + "data": { 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Checks shared row-window reuse and output coverage." + }, + "attrs": { + "group": 3, + "pads": [6, 6, 7, 8], + "strides": [1, 1], + "dilations": [2, 2], + "activation": "HardSigmoid", + "activation_params": [0.2, 0.5] + }, + "inputs": { + "x": { + "dtype": "float16", + "shape": [2, 9, 17, 29], + "data": { "kind": "fillFloat32", "sinStep": 0.137, "cosStep": 0.193, "scale": 2.0, "offset": 0.0 } + }, + "w": { + "dtype": "float16", + "shape": [18, 3, 7, 7], + "data": { + "kind": "fillFloat32", + "sinStep": 0.20800000000000002, + "cosStep": 0.246, + "scale": 0.4, + "offset": 0.0 + } + }, + "bias": { + "dtype": "float16", + "shape": [18], + "data": { "kind": "fillFloat32", "sinStep": 0.279, "cosStep": 0.299, "scale": 0.5, "offset": 0.017 } + } + }, + "outputs": { "y": { "dtype": "float16", "shape": [2, 18, 18, 31], "tolerance": 0.001, "relTolerance": 0.001 } } + }, + { + "name": "fused-grouped_float16_b2_g3_c3_m6_17x29_k7x7_d2x2_s1x1_bias1_asym1-HardSwish", + "provenance": { + "notes": "Grouped 7x7 convolution with 3 input and 6 output channels per group, dilation 2x2, stride 1x1, bias and HardSwish activation. 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Checks complete output coverage for multi-channel and depthwise groups with 7x7, 9x9 and 11x11 filters." + }, + "attrs": { + "group": 4, + "pads": [5, 5, 5, 5], + "strides": [1, 1], + "dilations": [1, 1], + "activation": "LeakyRelu", + "activation_params": [0.2] + }, + "inputs": { + "x": { + "dtype": "float16", + "shape": [1, 12, 16, 15], + "data": { "kind": "fillFloat32", "sinStep": 0.137, "cosStep": 0.193, "scale": 0.2 } + }, + "w": { + "dtype": "float16", + "shape": [8, 3, 11, 11], + "data": { "kind": "fillFloat32", "sinStep": 0.20800000000000002, "cosStep": 0.246, "scale": 0.02 } + } + }, + "outputs": { "y": { "dtype": "float16", "shape": [1, 8, 16, 15], "tolerance": 0.001, "relTolerance": 0.001 } } + }, + { + "name": "coverage-fused-grouped_float16_b1_g4_c3_m2_16x16_k11x11_d1x1_s1x1_bias0_asym0-LeakyRelu", + "provenance": { + "notes": "Grouped convolution at output widths 15, 16 and 17 with height 16. Checks complete output coverage for multi-channel and depthwise groups with 7x7, 9x9 and 11x11 filters." + }, + "attrs": { + "group": 4, + "pads": [5, 5, 5, 5], + "strides": [1, 1], + "dilations": [1, 1], + "activation": "LeakyRelu", + "activation_params": [0.2] + }, + "inputs": { + "x": { + "dtype": "float16", + "shape": [1, 12, 16, 16], + "data": { "kind": "fillFloat32", "sinStep": 0.137, "cosStep": 0.193, "scale": 0.2 } + }, + "w": { + "dtype": "float16", + "shape": [8, 3, 11, 11], + "data": { "kind": "fillFloat32", "sinStep": 0.20800000000000002, "cosStep": 0.246, "scale": 0.02 } + } + }, + "outputs": { "y": { "dtype": "float16", "shape": [1, 8, 16, 16], "tolerance": 0.001, "relTolerance": 0.001 } } + }, + { + "name": "coverage-fused-grouped_float16_b1_g4_c3_m2_16x17_k11x11_d1x1_s1x1_bias0_asym0-LeakyRelu", + "provenance": { + "notes": "Grouped convolution at output widths 15, 16 and 17 with height 16. Checks complete output coverage for multi-channel and depthwise groups with 7x7, 9x9 and 11x11 filters." + }, + "attrs": { + "group": 4, + "pads": [5, 5, 5, 5], + "strides": [1, 1], + "dilations": [1, 1], + "activation": "LeakyRelu", + "activation_params": [0.2] + }, + "inputs": { + "x": { + "dtype": "float16", + "shape": [1, 12, 16, 17], + "data": { "kind": "fillFloat32", "sinStep": 0.137, "cosStep": 0.193, "scale": 0.2 } + }, + "w": { + "dtype": "float16", + "shape": [8, 3, 11, 11], + "data": { "kind": "fillFloat32", "sinStep": 0.20800000000000002, "cosStep": 0.246, "scale": 0.02 } + } + }, + "outputs": { "y": { "dtype": "float16", "shape": [1, 8, 16, 17], "tolerance": 0.001, "relTolerance": 0.001 } } + }, + { + "name": "grouped_residual_direct_control", + "provenance": { + "notes": "Grouped convolution with a residual input checks that Z is included before activation at a large spatial extent." + }, + "attrs": { "group": 2, "activation": "Relu", "pads": [1, 1, 1, 1], "strides": [1, 1] }, + "inputs": { + "x": { + "dtype": "float32", + "shape": [1, 8, 16, 17], + "data": { "kind": "fillFloat32", "sinStep": 0.137, "cosStep": 0.193, "scale": 0.2 } + }, + "w": { + "dtype": "float32", + "shape": [8, 4, 3, 3], + "data": { "kind": "fillFloat32", "sinStep": 0.071, "cosStep": 0.153, "scale": 0.02 } + }, + "zResidual": { + "dtype": "float32", + "shape": [1, 8, 16, 17], + "data": { "kind": "fillFloat32", "sinStep": 0.173, "cosStep": 0.113, "scale": 0.2 } + } + }, + "outputs": { "y": { "dtype": "float32", "shape": [1, 8, 16, 17], "tolerance": 0.0001, "relTolerance": 0.0001 } } + }, + { + "name": "grouped_bias_residual_direct_control", + "provenance": { + "notes": "Grouped convolution with a residual input checks that Z is included before activation at a large spatial extent." + }, + "attrs": { "group": 2, "activation": "Relu", "pads": [1, 1, 1, 1], "strides": [1, 1] }, + "inputs": { + "x": { + "dtype": "float32", + "shape": [1, 8, 16, 17], + "data": { "kind": "fillFloat32", "sinStep": 0.137, "cosStep": 0.193, "scale": 0.2 } + }, + "w": { + "dtype": "float32", + "shape": [8, 4, 3, 3], + "data": { "kind": "fillFloat32", "sinStep": 0.071, "cosStep": 0.153, "scale": 0.02 } + }, + "zResidual": { + "dtype": "float32", + "shape": [1, 8, 16, 17], + "data": { "kind": "fillFloat32", "sinStep": 0.173, "cosStep": 0.113, "scale": 0.2 } + }, + "bias": { + "dtype": "float32", + "shape": [8], + "data": { "kind": "fillFloat32", "sinStep": 0.071, "cosStep": 0.193, "scale": 0.03 } + } + }, + "outputs": { "y": { "dtype": "float32", "shape": [1, 8, 16, 17], "tolerance": 0.0001, "relTolerance": 0.0001 } } + }, + { + "name": "fused-bias-adjacent-float32-b1-c64-m64-g4-32x32-k7", + "provenance": { + "notes": "Grouped 7x7 convolution with 16 input and output channels per group, width 32, unit dilation, bias and ReLU. Checks the adjacent four-column layout with a complete output vector." + }, + "attrs": { "group": 4, "pads": [3, 3, 3, 3], "strides": [1, 1], "dilations": [1, 1], "activation": "Relu" }, + "inputs": { + "x": { + "dtype": "float32", + "shape": [1, 64, 32, 32], + "data": { "kind": "fillFloat32", "sinStep": 0.137, "cosStep": 0.193, "scale": 0.2, "offset": 0.0 } + }, + "w": { + "dtype": "float32", + "shape": [64, 16, 7, 7], + "data": { + "kind": "fillFloat32", + "sinStep": 0.20800000000000002, + "cosStep": 0.246, + "scale": 0.02, + "offset": 0.0 + } + }, + "bias": { + "dtype": "float32", + "shape": [64], + "data": { "kind": "fillFloat32", "sinStep": 0.279, "cosStep": 0.299, "scale": 0.03, "offset": 0.017 } + } + }, + "outputs": { "y": { "dtype": "float32", "shape": [1, 64, 32, 32], "tolerance": 0.0001, "relTolerance": 0.0001 } } + }, + { + "name": "fused-bias-adjacent-float16-b1-c64-m64-g4-32x32-k7", + "provenance": { + "notes": "Grouped 7x7 convolution with 16 input and output channels per group, width 32, unit dilation, bias and ReLU. Checks the adjacent four-column layout with a complete output vector." + }, + "attrs": { "group": 4, "pads": [3, 3, 3, 3], "strides": [1, 1], "dilations": [1, 1], "activation": "Relu" }, + "inputs": { + "x": { + "dtype": "float16", + "shape": [1, 64, 32, 32], + "data": { "kind": "fillFloat32", "sinStep": 0.137, "cosStep": 0.193, "scale": 0.2, "offset": 0.0 } + }, + "w": { + "dtype": "float16", + "shape": [64, 16, 7, 7], + "data": { + "kind": "fillFloat32", + "sinStep": 0.20800000000000002, + "cosStep": 0.246, + "scale": 0.02, + "offset": 0.0 + } + }, + "bias": { + "dtype": "float16", + "shape": [64], + "data": { "kind": "fillFloat32", "sinStep": 0.279, "cosStep": 0.299, "scale": 0.03, "offset": 0.017 } + } + }, + "outputs": { "y": { "dtype": "float16", "shape": [1, 64, 32, 32], "tolerance": 0.001, "relTolerance": 0.001 } } + }, + { + "name": "ort_conv2d_quickgelu_fusion_parity", + "provenance": { + "source": "onnxruntime/test/optimizer/graph_transform_test.cc", + "test": "GraphTransformationTests.WebGpuIm2ColConvQuickGeluFusionMatchesUnfusedResults", + "notes": "ORT builds x*sigmoid(alpha*x) after a Conv and checks the fused result against the unfused graph on random data in [-3,3]; transcribed here with the same shapes and a deterministic fill. alpha 1.4 as in the upstream test." + }, + "attrs": { + "activation": "QuickGelu", + "activation_params": [1.4], + "kernel_shape": [3, 3], + "pads": [1, 1, 1, 1], + "strides": [1, 1], + "dilations": [1, 1] + }, + "inputs": { + "x": { + "dtype": "float32", + "shape": [1, 4, 14, 14], + "data": { "kind": "fillFloat32", "sinStep": 0.23, "cosStep": 0.41, "scale": 3.0 } + }, + "w": { + "dtype": "float32", + "shape": [8, 4, 3, 3], + "data": { "kind": "fillFloat32", "sinStep": 0.019, "cosStep": 0.031, "scale": 0.5 } + }, + "bias": { + "dtype": "float32", + "shape": [8], + "data": { "kind": "fillFloat32", "sinStep": 0.007, "cosStep": 0.017, "scale": 0.5 } + } + }, + "outputs": { + "y": { "dtype": "float32", "shape": [1, 8, 14, 14], "tolerance": 0.000001, "relTolerance": 0.00001 } + } + }, + { + "name": "ort_conv2d_quickgelu_unit_alpha_silu_parity", + "provenance": { + "source": "onnxruntime/test/optimizer/graph_transform_test.cc", + "test": "GraphTransformationTests.WebGpuIm2ColConvQuickGeluUnitAlphaFusionMatchesUnfusedResults", + "notes": "With alpha 1, QuickGelu computes x*sigmoid(x); the expected values distinguish it from other activation settings." + }, + "attrs": { + "activation": "QuickGelu", + "activation_params": [1], + "kernel_shape": [3, 3], + "pads": [1, 1, 1, 1], + "strides": [1, 1], + "dilations": [1, 1] + }, + "inputs": { + "x": { + "dtype": "float32", + "shape": [1, 4, 14, 14], + "data": { "kind": "fillFloat32", "sinStep": 0.29, "cosStep": 0.37, "scale": 3.0 } + }, + "w": { + "dtype": "float32", + "shape": [8, 4, 3, 3], + "data": { "kind": "fillFloat32", "sinStep": 0.023, "cosStep": 0.013, "scale": 0.5 } + }, + "bias": { + "dtype": "float32", + "shape": [8], + "data": { "kind": "fillFloat32", "sinStep": 0.011, "cosStep": 0.019, "scale": 0.5 } + } + }, + "outputs": { + "y": { "dtype": "float32", "shape": [1, 8, 14, 14], "tolerance": 0.000001, "relTolerance": 0.00001 } + } + }, + { + "name": "ort_conv2d_fused_quickgelu_parity", + "provenance": { + "source": "onnxruntime/core/providers/webgpu/nn/fuse_utils.cc", + "test": "GetActivationSnippet / ConvFp16Test.WebGpuSubgroupPointwiseNhwcFusedConvNewActivations", + "notes": "Transcribed from ORT's fused activation set. Formula: value * sigmoid(alpha*value), alpha default 1.702; alpha==1 is SiLU/Swish. alpha == 1 is a distinct case because the multiply drops out. Shapes follow RunWebGpuConvActivationParity (x [1,4,14,14], w [8,4,3,3], bias [8], input spanning [-3,3] so asymmetric activations see both signs); the upstream test uses random data, replaced here with a deterministic fill." + }, + "attrs": { + "activation": "QuickGelu", + "kernel_shape": [3, 3], + "pads": [1, 1, 1, 1], + "strides": [1, 1], + "dilations": [1, 1], + "activation_params": [1.702] + }, + "inputs": { + "x": { + "dtype": "float32", + "shape": [1, 4, 14, 14], + "data": { "kind": "fillFloat32", "sinStep": 0.23, "cosStep": 0.41, "scale": 3.0 } + }, + "w": { + "dtype": "float32", + "shape": [8, 4, 3, 3], + "data": { "kind": "fillFloat32", "sinStep": 0.019, "cosStep": 0.031, "scale": 0.5 } + }, + "bias": { + "dtype": "float32", + "shape": [8], + "data": { "kind": "fillFloat32", "sinStep": 0.007, "cosStep": 0.017, "scale": 0.5 } + } + }, + "outputs": { + "y": { "dtype": "float32", "shape": [1, 8, 14, 14], "tolerance": 0.000001, "relTolerance": 0.00001 } + } + }, + { + "name": "ort_conv2d_fused_elu_parity", + "provenance": { + "source": "onnxruntime/core/providers/webgpu/nn/fuse_utils.cc", + "test": "GetActivationSnippet / ConvFp16Test.WebGpuSubgroupPointwiseNhwcFusedConvNewActivations", + "notes": "Transcribed from ORT's fused activation set. Formula: select(alpha*(exp(v)-1), v, v >= 0). Shapes follow RunWebGpuConvActivationParity (x [1,4,14,14], w [8,4,3,3], bias [8], input spanning [-3,3] so asymmetric activations see both signs); the upstream test uses random data, replaced here with a deterministic fill." + }, + "attrs": { + "activation": "Elu", + "kernel_shape": [3, 3], + "pads": [1, 1, 1, 1], + "strides": [1, 1], + "dilations": [1, 1], + "activation_params": [0.5] + }, + "inputs": { + "x": { + "dtype": "float32", + "shape": [1, 4, 14, 14], + "data": { "kind": "fillFloat32", "sinStep": 0.29, "cosStep": 0.37, "scale": 3.0 } + }, + "w": { + "dtype": "float32", + "shape": [8, 4, 3, 3], + "data": { "kind": "fillFloat32", "sinStep": 0.019, "cosStep": 0.031, "scale": 0.5 } + }, + "bias": { + "dtype": "float32", + "shape": [8], + "data": { "kind": "fillFloat32", "sinStep": 0.007, "cosStep": 0.017, "scale": 0.5 } + } + }, + "outputs": { + "y": { "dtype": "float32", "shape": [1, 8, 14, 14], "tolerance": 0.000001, "relTolerance": 0.00001 } + } + }, + { + "name": "ort_conv2d_fused_gelu_parity", + "provenance": { + "source": "onnxruntime/core/providers/webgpu/nn/fuse_utils.cc", + "test": "GetActivationSnippet / ConvFp16Test.WebGpuSubgroupPointwiseNhwcFusedConvNewActivations", + "notes": "Transcribed from ORT's fused activation set. Formula: 0.5*v*(1+erf(v/sqrt2)); ORT encodes the approximation mode as activation_params[0] = 0 (erf) or 1 (tanh) and emits an Abramowitz-Stegun 7.1.26 erf helper as a module-scope declaration. Shapes follow RunWebGpuConvActivationParity (x [1,4,14,14], w [8,4,3,3], bias [8], input spanning [-3,3] so asymmetric activations see both signs); the upstream test uses random data, replaced here with a deterministic fill." + }, + "attrs": { + "activation": "Gelu", + "kernel_shape": [3, 3], + "pads": [1, 1, 1, 1], + "strides": [1, 1], + "dilations": [1, 1], + "activation_params": [0] + }, + "inputs": { + "x": { + "dtype": "float32", + "shape": [1, 4, 14, 14], + "data": { "kind": "fillFloat32", "sinStep": 0.31, "cosStep": 0.43, "scale": 3.0 } + }, + "w": { + "dtype": "float32", + "shape": [8, 4, 3, 3], + "data": { "kind": "fillFloat32", "sinStep": 0.019, "cosStep": 0.031, "scale": 0.5 } + }, + "bias": { + "dtype": "float32", + "shape": [8], + "data": { "kind": "fillFloat32", "sinStep": 0.007, "cosStep": 0.017, "scale": 0.5 } + } + }, + "outputs": { + "y": { "dtype": "float32", "shape": [1, 8, 14, 14], "tolerance": 0.000001, "relTolerance": 0.00001 } + } + }, + { + "name": "ort_conv2d_fused_gelutanh_parity", + "provenance": { + "source": "onnxruntime/core/providers/webgpu/nn/fuse_utils.cc", + "test": "GetActivationSnippet / ConvFp16Test.WebGpuSubgroupPointwiseNhwcFusedConvNewActivations", + "notes": "Transcribed from ORT's fused activation set. Formula: v*(0.5 + 0.5*tanh_safe(v*(0.035677408136300125*v*v + 0.79788456080286535))); ORT reaches it as Gelu with activation_params[0] == 1 or as FastGelu, and uses an overflow-safe tanh because WGSL tanh returns NaN for large inputs. Shapes follow RunWebGpuConvActivationParity (x [1,4,14,14], w [8,4,3,3], bias [8], input spanning [-3,3] so asymmetric activations see both signs); the upstream test uses random data, replaced here with a deterministic fill." + }, + "attrs": { + "activation": "Gelu", + "kernel_shape": [3, 3], + "pads": [1, 1, 1, 1], + "strides": [1, 1], + "dilations": [1, 1], + "activation_params": [1] + }, + "inputs": { + "x": { + "dtype": "float32", + "shape": [1, 4, 14, 14], + "data": { "kind": "fillFloat32", "sinStep": 0.17, "cosStep": 0.47, "scale": 3.0 } + }, + "w": { + "dtype": "float32", + "shape": [8, 4, 3, 3], + "data": { "kind": "fillFloat32", "sinStep": 0.019, "cosStep": 0.031, "scale": 0.5 } + }, + "bias": { + "dtype": "float32", + "shape": [8], + "data": { "kind": "fillFloat32", "sinStep": 0.007, "cosStep": 0.017, "scale": 0.5 } + } + }, + "outputs": { + "y": { "dtype": "float32", "shape": [1, 8, 14, 14], "tolerance": 0.000001, "relTolerance": 0.00001 } + } + }, + { + "name": "ort_conv2d_fused_softplus_parity", + "provenance": { + "source": "onnxruntime/core/providers/webgpu/nn/fuse_utils.cc", + "test": "GetActivationSnippet / ConvFp16Test.WebGpuSubgroupPointwiseNhwcFusedConvNewActivations", + "notes": "Transcribed from ORT's fused activation set. Formula: max(v,0) + log(1 + exp(-abs(v))) -- the overflow-safe form. Shapes follow RunWebGpuConvActivationParity (x [1,4,14,14], w [8,4,3,3], bias [8], input spanning [-3,3] so asymmetric activations see both signs); the upstream test uses random data, replaced here with a deterministic fill." + }, + "attrs": { + "activation": "Softplus", + "kernel_shape": [3, 3], + "pads": [1, 1, 1, 1], + "strides": [1, 1], + "dilations": [1, 1] + }, + "inputs": { + "x": { + "dtype": "float32", + "shape": [1, 4, 14, 14], + "data": { "kind": "fillFloat32", "sinStep": 0.13, "cosStep": 0.53, "scale": 3.0 } + }, + "w": { + "dtype": "float32", + "shape": [8, 4, 3, 3], + "data": { "kind": "fillFloat32", "sinStep": 0.019, "cosStep": 0.031, "scale": 0.5 } + }, + "bias": { + "dtype": "float32", + "shape": [8], + "data": { "kind": "fillFloat32", "sinStep": 0.007, "cosStep": 0.017, "scale": 0.5 } + } + }, + "outputs": { + "y": { "dtype": "float32", "shape": [1, 8, 14, 14], "tolerance": 0.000001, "relTolerance": 0.00001 } + } + }, + { + "name": "ort_conv2d_fused_thresholdedrelu_parity", + "provenance": { + "source": "onnxruntime/core/providers/webgpu/nn/fuse_utils.cc", + "test": "GetActivationSnippet / ConvFp16Test.WebGpuSubgroupPointwiseNhwcFusedConvNewActivations", + "notes": "Transcribed from ORT's fused activation set. Formula: select(0, v, v > alpha), alpha default 1.0. Shapes follow RunWebGpuConvActivationParity (x [1,4,14,14], w [8,4,3,3], bias [8], input spanning [-3,3] so asymmetric activations see both signs); the upstream test uses random data, replaced here with a deterministic fill." + }, + "attrs": { + "activation": "ThresholdedRelu", + "kernel_shape": [3, 3], + "pads": [1, 1, 1, 1], + "strides": [1, 1], + "dilations": [1, 1], + "activation_params": [0.6] + }, + "inputs": { + "x": { + "dtype": "float32", + "shape": [1, 4, 14, 14], + "data": { "kind": "fillFloat32", "sinStep": 0.11, "cosStep": 0.59, "scale": 3.0 } + }, + "w": { + "dtype": "float32", + "shape": [8, 4, 3, 3], + "data": { "kind": "fillFloat32", "sinStep": 0.019, "cosStep": 0.031, "scale": 0.5 } + }, + "bias": { + "dtype": "float32", + "shape": [8], + "data": { "kind": "fillFloat32", "sinStep": 0.007, "cosStep": 0.017, "scale": 0.5 } + } + }, + "outputs": { + "y": { "dtype": "float32", "shape": [1, 8, 14, 14], "tolerance": 0.000001, "relTolerance": 0.00001 } + } + }, + { + "name": "ort_conv2d_fused_erf_parity", + "provenance": { + "source": "onnxruntime/core/providers/webgpu/nn/fuse_utils.cc", + "test": "GetActivationSnippet / ConvFp16Test.WebGpuSubgroupPointwiseNhwcFusedConvNewActivations", + "notes": "Transcribed from ORT's fused activation set. Formula: erf(v), sharing the same A&S 7.1.26 helper as Gelu. Shapes follow RunWebGpuConvActivationParity (x [1,4,14,14], w [8,4,3,3], bias [8], input spanning [-3,3] so asymmetric activations see both signs); the upstream test uses random data, replaced here with a deterministic fill." + }, + "attrs": { + "activation": "Erf", + "kernel_shape": [3, 3], + "pads": [1, 1, 1, 1], + "strides": [1, 1], + "dilations": [1, 1] + }, + "inputs": { + "x": { + "dtype": "float32", + "shape": [1, 4, 14, 14], + "data": { "kind": "fillFloat32", "sinStep": 0.07, "cosStep": 0.61, "scale": 3.0 } + }, + "w": { + "dtype": "float32", + "shape": [8, 4, 3, 3], + "data": { "kind": "fillFloat32", "sinStep": 0.019, "cosStep": 0.031, "scale": 0.5 } + }, + "bias": { + "dtype": "float32", + "shape": [8], + "data": { "kind": "fillFloat32", "sinStep": 0.007, "cosStep": 0.017, "scale": 0.5 } + } + }, + "outputs": { + "y": { "dtype": "float32", "shape": [1, 8, 14, 14], "tolerance": 0.000001, "relTolerance": 0.00001 } + } + }, + { + "name": "tile_partial_float32_b1c4m8_14x14_k3", + "provenance": { + "notes": "Checks partial K-tile accumulation for fused 3x3 and pointwise convolution, including odd output channels and spatial tails. ELU retains both signs and bias is added after the dot product." + }, + "attrs": { + "activation": "Elu", + "activation_params": [0.5], + "kernel_shape": [3, 3], + "pads": [1, 1, 1, 1], + "strides": [1, 1], + "dilations": [1, 1] + }, + "inputs": { + "x": { + "dtype": "float32", + "shape": [1, 4, 14, 14], + "data": { "kind": "fillFloat32", "scale": 0.3, "sinStep": 0.17, "cosStep": 0.23 } + }, + "w": { + "dtype": "float32", + "shape": [8, 4, 3, 3], + "data": { "kind": "fillFloat32", "scale": 0.2, "sinStep": 0.28, "cosStep": 0.30000000000000004 } + }, + "bias": { + "dtype": "float32", + "shape": [8], + "data": { "kind": "fillFloat32", "scale": 0.3, "sinStep": 0.39, "cosStep": 0.37 } + } + }, + "outputs": { + "y": { "dtype": "float32", "shape": [1, 8, 14, 14], "tolerance": 0.000001, "relTolerance": 0.00001 } + } + }, + { + "name": "tile_partial_float32_b1c36m8_14x14_k1", + "provenance": { + "notes": "Checks partial K-tile accumulation for fused 3x3 and pointwise convolution, including odd output channels and spatial tails. ELU retains both signs and bias is added after the dot product." + }, + "attrs": { + "activation": "Elu", + "activation_params": [0.5], + "kernel_shape": [1, 1], + "pads": [0, 0, 0, 0], + "strides": [1, 1], + "dilations": [1, 1] + }, + "inputs": { + "x": { + "dtype": "float32", + "shape": [1, 36, 14, 14], + "data": { "kind": "fillFloat32", "scale": 0.3, "sinStep": 0.17, "cosStep": 0.23 } + }, + "w": { + "dtype": "float32", + "shape": [8, 36, 1, 1], + "data": { "kind": "fillFloat32", "scale": 0.2, "sinStep": 0.28, "cosStep": 0.30000000000000004 } + }, + "bias": { + "dtype": "float32", + "shape": [8], + "data": { "kind": "fillFloat32", "scale": 0.3, "sinStep": 0.39, "cosStep": 0.37 } + } + }, + "outputs": { + "y": { "dtype": "float32", "shape": [1, 8, 14, 14], "tolerance": 0.000001, "relTolerance": 0.00001 } + } + }, + { + "name": "tile_partial_float32_b1c5m17_13x15_k3", + "provenance": { + "notes": "Checks partial K-tile accumulation for fused 3x3 and pointwise convolution, including odd output channels and spatial tails. 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