Update model card for yolo11-seg

README.md

@@ -94,45 +94,45 @@ Row conventions in the table below:
 - **Decoder variants.** EdgeFirst ships three INT8 split-decoders. The table headlines the accuracy-recovering ones: **smart** (per-tensor rescaling — best accuracy, extra CPU ops add some latency) and, where a smart run is absent, **logical** (the latency-optimized default — no CPU overhead, slightly lower accuracy). The **combined** decoder is the *standard-quantization baseline* (equivalent to typical single-scale INT8, and how the reference numbers are produced); it loses the most accuracy — especially on segmentation, where box/mask dynamic range collapses under one scale — so it is published only as a downloadable reference artifact and in the metrics export, never headlined here. Smart and logical exist precisely to recover that loss. Full converter documentation: [EdgeFirst model conversion](https://doc.edgefirst.ai/latest/models/conversion/) — these are the converters used by this Model Zoo and the EdgeFirst Performance Index report.
 - **Platform-label suffixes.** `(FRDM)` / `(Phytec)` name the NXP i.MX 95 development board a session ran on. `— latency` / `— throughput` mark the two pipeline configurations the NXP i.MX 95 Neutron and NXP Ara240 targets run: the **latency** pipeline runs inference serially for the lowest per-frame latency; the **throughput** pipeline runs multiple inference workers for the highest FPS, which raises per-call inference time in exchange. Rows with neither suffix run a single pipeline.
 - **End-to-end (ms)** is the sequential per-image latency of the compute pipeline — preprocess → inference → postprocess. Image acquisition (camera or file load + JPEG decode) overlaps these stages and is excluded from this figure.
-- **Realized FPS vs Theoretical FPS.** **Realized FPS** is the *measured* steady-state throughput — the rate at which final results are actually delivered over the full validation pipeline. It normally exceeds `1000 / end-to-end` because the runtime overlaps stages across frames, and it is the **true, priority number**. **Theoretical FPS** (shown with a `~`) is the accelerator's **core** ceiling — `1000 / device-compute-time`, the rate the NPU/DNPU could sustain *if it were the only bottleneck* — so it is a **possibly-achievable note, not a claim**. It is read from the isolated device-compute stage, which (unlike the host capture/preprocess stages, whose measured time inflates when the pipeline is backpressured) is stable and load-independent. Whether a deployment approaches it depends on the surrounding pipeline, and two levers dominate: (1) **host bottlenecks** — these validation runs decode a JPEG per image, whereas a live **camera pipeline** skips that decode and can run closer to the ceiling; and (2) **confidence threshold** — validation runs at `0.001` to capture every detection for mAP, which makes NMS/decode heavy, while a deployment threshold of `0.25–0.75` produces far fewer candidate boxes and lighter postprocessing, raising realized FPS toward the ceiling.
-
-| Size | Platform | Box mAP@0.5 | Mask mAP@0.5-0.95 | Δ mask vs FP32 (pp) | Inference (ms) | End-to-end (ms) | Realized FPS | Theoretical FPS | Source |
-|------|----------|-------------|-------------------|---------------------|----------------|-----------------|--------------|-----------------|--------|
-| Nano | ONNX FP32 (Intel Core i9-13900F · 32-core) | 53.28% | 30.74% | -0.01 | 51.98 | 77.65 | 51.2 | ~58 | [v-a4a](https://edgefirst.studio/public/validation/v-a4a/details?mode=charts) |
-| Nano | ONNX FP32 (CUDA) | 53.28% | 30.75% | ref | 10.76 | 21.15 | 244.6 | ~353 | [v-a8c](https://edgefirst.studio/public/validation/v-a8c/details?mode=charts) |
-| Nano | ONNX FP16 (CUDA) | 53.29% | 30.74% | -0.01 | 8.42 | 19.60 | 305.4 | ~360 | [v-aa1](https://edgefirst.studio/public/validation/v-aa1/details?mode=charts) |
-| Nano | Apple M2 Max — CoreML Neural Engine (FP16) | 52.89% | 30.50% | -0.25 | 2.74 | 12.68 | 349.9 | ~646 | [v-9f0](https://edgefirst.studio/public/validation/v-9f0/details?mode=charts) |
-| Nano | Apple M2 Max — CoreML Metal GPU (FP16) | 51.85% | 29.94% | -0.81 | 6.86 | 18.07 | 290.7 | ~437 | [v-739](https://edgefirst.studio/public/validation/v-739/details?mode=charts) |
-| Nano | Apple M2 Max — CoreML CPU (FP16) | 52.85% | 30.51% | -0.24 | 20.86 | 29.03 | 90.6 | ~96 | [v-9f1](https://edgefirst.studio/public/validation/v-9f1/details?mode=charts) |
-| Nano | NXP i.MX 8M Plus + VeriSilicon NPU (FRDM) | 48.41% | 27.17% | -3.58 | 104.78 | 200.77 | 8.6 | ~10 | [v-8d1](https://edgefirst.studio/public/validation/v-8d1/details?mode=charts) |
+- **Realized FPS vs Core-throughput ceiling (FPS).** **Realized FPS** is the *measured* steady-state throughput — the rate at which final results are actually delivered over the full validation pipeline. It normally exceeds `1000 / end-to-end` because the runtime overlaps stages across frames, and it is the **true, priority number**. **Core-throughput ceiling (FPS)** (shown with a `~`) is the accelerator's **core** ceiling — `1000 / device-compute-time`, the rate the NPU/DNPU could sustain *if it were the only bottleneck* — so it is a **possibly-achievable note, not a claim**. It is read from the isolated device-compute stage, which (unlike the host capture/preprocess stages, whose measured time inflates when the pipeline is backpressured) is stable and load-independent. Whether a deployment approaches it depends on the surrounding pipeline, and two levers dominate: (1) **host bottlenecks** — these validation runs decode a JPEG per image, whereas a live **camera pipeline** skips that decode and can run closer to the ceiling; and (2) **confidence threshold** — validation runs at `0.001` to capture every detection for mAP, which makes NMS/decode heavy, while a deployment threshold of `0.25–0.75` produces far fewer candidate boxes and lighter postprocessing, raising realized FPS toward the ceiling.
+
+| Size | Platform | Box mAP@0.5 | Mask mAP@0.5-0.95 | Δ mask vs FP32 (pp) | Inference (ms) | End-to-end (ms) | Realized FPS | Core-throughput ceiling (FPS) | Source |
+|------|----------|-------------|-------------------|---------------------|----------------|-----------------|--------------|-------------------------------|--------|
+| Nano | ONNX FP32 (Intel Core i9-13900F · 32-core) | 53.28% | 30.74% | -0.01 | 51.98 | 77.65 | 51.2 | ~51 | [v-a4a](https://edgefirst.studio/public/validation/v-a4a/details?mode=charts) |
+| Nano | ONNX FP32 (CUDA) | 53.28% | 30.75% | ref | 10.76 | 21.15 | 244.6 | ~244 | [v-a8c](https://edgefirst.studio/public/validation/v-a8c/details?mode=charts) |
+| Nano | ONNX FP16 (CUDA) | 53.29% | 30.74% | -0.01 | 8.42 | 19.60 | 305.4 | ~305 | [v-aa1](https://edgefirst.studio/public/validation/v-aa1/details?mode=charts) |
+| Nano | Apple M2 Max — CoreML Neural Engine (FP16) | 52.89% | 30.50% | -0.25 | 2.74 | 12.68 | 349.9 | ~351 | [v-9f0](https://edgefirst.studio/public/validation/v-9f0/details?mode=charts) |
+| Nano | Apple M2 Max — CoreML Metal GPU (FP16) | 51.85% | 29.94% | -0.81 | 6.86 | 18.07 | 290.7 | ~291 | [v-739](https://edgefirst.studio/public/validation/v-739/details?mode=charts) |
+| Nano | Apple M2 Max — CoreML CPU (FP16) | 52.85% | 30.51% | -0.24 | 20.86 | 29.03 | 90.6 | ~91 | [v-9f1](https://edgefirst.studio/public/validation/v-9f1/details?mode=charts) |
+| Nano | NXP i.MX 8M Plus + VeriSilicon NPU (FRDM) | 48.41% | 27.17% | -3.58 | 104.78 | 200.77 | 8.6 | ~9 | [v-8d1](https://edgefirst.studio/public/validation/v-8d1/details?mode=charts) |
 | Nano | NXP i.MX 95 + eIQ Neutron NPU (FRDM) — latency | In progress | — | — | — | — | — | — | [v-8b9](https://edgefirst.studio/public/validation/v-8b9/details?mode=charts) |
 | Nano | NXP i.MX 95 + eIQ Neutron NPU (FRDM) — throughput | In progress | — | — | — | — | — | — | [v-8be](https://edgefirst.studio/public/validation/v-8be/details?mode=charts) |
 | Nano | NXP i.MX 95 + eIQ Neutron NPU (Phytec) — throughput | In progress | — | — | — | — | — | — | [v-89c](https://edgefirst.studio/public/validation/v-89c/details?mode=charts) |
 | Nano | NXP Ara240 (FRDM) — latency | 49.18% | 28.03% | -2.72 | 9.56 | 40.86 | 57.4 | ~63 | [v-a1a](https://edgefirst.studio/public/validation/v-a1a/details?mode=charts) |
 | Nano | NXP Ara240 (FRDM) — throughput | 49.18% | 28.03% | -2.72 | 9.80 | 61.08 | 58.1 | ~229 | [v-a1b](https://edgefirst.studio/public/validation/v-a1b/details?mode=charts) |
-| Nano | Raspberry Pi 5 + Hailo-8L NPU | 51.15% | 29.32% | -1.43 | 24.26 | 43.75 | 40.4 | ~41 | [v-a44](https://edgefirst.studio/public/validation/v-a44/details?mode=charts) |
+| Nano | Raspberry Pi 5 + Hailo-8L NPU | 51.15% | 29.32% | -1.43 | 24.26 | 43.75 | 40.4 | ~40 | [v-a44](https://edgefirst.studio/public/validation/v-a44/details?mode=charts) |
 | Nano | NVIDIA Jetson Orin Nano (TensorRT FP16) | 53.27% | 30.77% | +0.02 | 6.84 | 58.61 | 79.2 | ~66 | [v-91b](https://edgefirst.studio/public/validation/v-91b/details?mode=charts) |
-| Small | ONNX FP32 (Intel Core i9-13900F · 32-core) | 61.72% | 35.73% | +0.01 | 128.91 | 151.38 | 21.5 | ~23 | [v-a51](https://edgefirst.studio/public/validation/v-a51/details?mode=charts) |
-| Small | ONNX FP32 (CUDA) | 61.72% | 35.72% | ref | 19.67 | 30.87 | 153.4 | ~203 | [v-a93](https://edgefirst.studio/public/validation/v-a93/details?mode=charts) |
-| Small | ONNX FP16 (CUDA) | 61.69% | 35.73% | +0.01 | 13.04 | 25.38 | 224.4 | ~307 | [v-aa8](https://edgefirst.studio/public/validation/v-aa8/details?mode=charts) |
-| Small | Apple M2 Max — CoreML Neural Engine (FP16) | 60.16% | 34.89% | -0.83 | 6.81 | 13.26 | 253.7 | ~294 | [v-730](https://edgefirst.studio/public/validation/v-730/details?mode=charts) |
-| Small | Apple M2 Max — CoreML Metal GPU (FP16) | 61.03% | 35.29% | -0.43 | 21.32 | 29.98 | 134.1 | ~141 | [v-9f2](https://edgefirst.studio/public/validation/v-9f2/details?mode=charts) |
-| Small | Apple M2 Max — CoreML CPU (FP16) | 61.03% | 35.29% | -0.43 | 40.34 | 47.99 | 48.1 | ~50 | [v-9f3](https://edgefirst.studio/public/validation/v-9f3/details?mode=charts) |
+| Small | ONNX FP32 (Intel Core i9-13900F · 32-core) | 61.72% | 35.73% | +0.01 | 128.91 | 151.38 | 21.5 | ~21 | [v-a51](https://edgefirst.studio/public/validation/v-a51/details?mode=charts) |
+| Small | ONNX FP32 (CUDA) | 61.72% | 35.72% | ref | 19.67 | 30.87 | 153.4 | ~153 | [v-a93](https://edgefirst.studio/public/validation/v-a93/details?mode=charts) |
+| Small | ONNX FP16 (CUDA) | 61.69% | 35.73% | +0.01 | 13.04 | 25.38 | 224.4 | ~224 | [v-aa8](https://edgefirst.studio/public/validation/v-aa8/details?mode=charts) |
+| Small | Apple M2 Max — CoreML Neural Engine (FP16) | 60.16% | 34.89% | -0.83 | 6.81 | 13.26 | 253.7 | ~254 | [v-730](https://edgefirst.studio/public/validation/v-730/details?mode=charts) |
+| Small | Apple M2 Max — CoreML Metal GPU (FP16) | 61.03% | 35.29% | -0.43 | 21.32 | 29.98 | 134.1 | ~134 | [v-9f2](https://edgefirst.studio/public/validation/v-9f2/details?mode=charts) |
+| Small | Apple M2 Max — CoreML CPU (FP16) | 61.03% | 35.29% | -0.43 | 40.34 | 47.99 | 48.1 | ~48 | [v-9f3](https://edgefirst.studio/public/validation/v-9f3/details?mode=charts) |
 | Small | NXP i.MX 8M Plus + VeriSilicon NPU (FRDM) | 42.80% | 22.19% | -13.53 ⚠ | 198.08 | 285.44 | 4.8 | ~5 | [v-955](https://edgefirst.studio/public/validation/v-955/details?mode=charts) |
-| Small | NXP Ara240 (FRDM) — latency | 57.97% | 33.61% | -2.11 | 15.63 | 42.29 | 53.6 | ~64 | [v-a28](https://edgefirst.studio/public/validation/v-a28/details?mode=charts) |
+| Small | NXP Ara240 (FRDM) — latency | 57.97% | 33.61% | -2.11 | 15.63 | 42.29 | 53.6 | ~54 | [v-a28](https://edgefirst.studio/public/validation/v-a28/details?mode=charts) |
 | Small | NXP Ara240 (FRDM) — throughput | 57.97% | 33.61% | -2.11 | 16.15 | 66.74 | 63.7 | ~94 | [v-a29](https://edgefirst.studio/public/validation/v-a29/details?mode=charts) |
-| Small | Raspberry Pi 5 + Hailo-8L NPU | 59.50% | 34.43% | -1.29 | 38.47 | 57.35 | 23.8 | ~26 | [v-8ed](https://edgefirst.studio/public/validation/v-8ed/details?mode=charts) |
+| Small | Raspberry Pi 5 + Hailo-8L NPU | 59.50% | 34.43% | -1.29 | 38.47 | 57.35 | 23.8 | ~24 | [v-8ed](https://edgefirst.studio/public/validation/v-8ed/details?mode=charts) |
 | Small | NVIDIA Jetson Orin Nano (TensorRT FP16) | 61.68% | 35.73% | +0.01 | 15.14 | 64.68 | 88.1 | ~68 | [v-923](https://edgefirst.studio/public/validation/v-923/details?mode=charts) |
 | Medium | ONNX FP32 (Intel Core i9-13900F · 32-core) | 67.10% | 39.43% | +0.01 | 364.67 | 385.66 | 7.9 | ~8 | [v-a58](https://edgefirst.studio/public/validation/v-a58/details?mode=charts) |
-| Medium | ONNX FP32 (CUDA) | 67.11% | 39.42% | ref | 53.53 | 63.75 | 64.2 | ~75 | [v-a9a](https://edgefirst.studio/public/validation/v-a9a/details?mode=charts) |
-| Medium | ONNX FP16 (CUDA) | 67.10% | 39.44% | +0.02 | 28.97 | 42.38 | 114.2 | ~138 | [v-aaf](https://edgefirst.studio/public/validation/v-aaf/details?mode=charts) |
-| Medium | Apple M2 Max — CoreML Neural Engine (FP16) | 65.03% | 38.29% | -1.13 | 24.35 | 31.55 | 79.3 | ~82 | [v-7ff](https://edgefirst.studio/public/validation/v-7ff/details?mode=charts) |
-| Medium | Apple M2 Max — CoreML Metal GPU (FP16) | 65.99% | 38.70% | -0.72 | 62.30 | 70.45 | 47.2 | ~48 | [v-9e1](https://edgefirst.studio/public/validation/v-9e1/details?mode=charts) |
+| Medium | ONNX FP32 (CUDA) | 67.11% | 39.42% | ref | 53.53 | 63.75 | 64.2 | ~64 | [v-a9a](https://edgefirst.studio/public/validation/v-a9a/details?mode=charts) |
+| Medium | ONNX FP16 (CUDA) | 67.10% | 39.44% | +0.02 | 28.97 | 42.38 | 114.2 | ~114 | [v-aaf](https://edgefirst.studio/public/validation/v-aaf/details?mode=charts) |
+| Medium | Apple M2 Max — CoreML Neural Engine (FP16) | 65.03% | 38.29% | -1.13 | 24.35 | 31.55 | 79.3 | ~79 | [v-7ff](https://edgefirst.studio/public/validation/v-7ff/details?mode=charts) |
+| Medium | Apple M2 Max — CoreML Metal GPU (FP16) | 65.99% | 38.70% | -0.72 | 62.30 | 70.45 | 47.2 | ~47 | [v-9e1](https://edgefirst.studio/public/validation/v-9e1/details?mode=charts) |
 | Medium | Apple M2 Max — CoreML CPU (FP16) | 65.96% | 38.67% | -0.75 | 90.94 | 98.48 | 21.7 | ~22 | [v-9e0](https://edgefirst.studio/public/validation/v-9e0/details?mode=charts) |
 | Medium | NXP i.MX 8M Plus + VeriSilicon NPU (FRDM) | 54.71% | 30.31% | -9.11 ⚠ | 392.18 | 468.93 | 2.5 | ~3 | [v-9ab](https://edgefirst.studio/public/validation/v-9ab/details?mode=charts) |
-| Medium | NXP Ara240 (FRDM) — latency | 62.87% | 37.36% | -2.06 | 39.06 | 61.74 | 24.8 | ~26 | [v-a36](https://edgefirst.studio/public/validation/v-a36/details?mode=charts) |
+| Medium | NXP Ara240 (FRDM) — latency | 62.87% | 37.36% | -2.06 | 39.06 | 61.74 | 24.8 | ~25 | [v-a36](https://edgefirst.studio/public/validation/v-a36/details?mode=charts) |
 | Medium | NXP Ara240 (FRDM) — throughput | 62.85% | 37.35% | -2.07 | 39.18 | 63.09 | 29.1 | ~29 | [v-a37](https://edgefirst.studio/public/validation/v-a37/details?mode=charts) |
-| Medium | Raspberry Pi 5 + Hailo-8L NPU | 64.44% | 37.62% | -1.80 | 79.87 | 99.64 | 11.8 | ~13 | [v-934](https://edgefirst.studio/public/validation/v-934/details?mode=charts) |
+| Medium | Raspberry Pi 5 + Hailo-8L NPU | 64.44% | 37.62% | -1.80 | 79.87 | 99.64 | 11.8 | ~12 | [v-934](https://edgefirst.studio/public/validation/v-934/details?mode=charts) |
 | Medium | NVIDIA Jetson Orin Nano (TensorRT FP16) | 67.07% | 39.43% | +0.01 | 72.33 | 97.67 | 54.8 | ~55 | [v-92c](https://edgefirst.studio/public/validation/v-92c/details?mode=charts) |
 
 > **⚠ Below expectations — under investigation.** The rows marked ⚠ above measure more than 10 percentage points below the same training session's float reference: the model accuracy on that platform is below our expectations. We publish the measured numbers rather than hiding them, and we are investigating the results to make improvements — the next snapshot of this card will reflect any recovered accuracy.
@@ -150,7 +150,7 @@ These results are produced by the EdgeFirst on-target validation pipeline:
 
 Inference latency is reported as the on-accelerator inference time. End-to-end latency is the sequential per-image latency across the compute pipeline — preprocessing, inference, and postprocessing; image acquisition (file or camera load and JPEG decode) overlaps these stages and is excluded from this figure.
 
-Two throughput figures are reported. **Realized FPS** is the *measured* steady-state rate at which final results are emitted, computed from the Perfetto trace as `(N-1) / (t_last - t_first)` over the warmup-trimmed steady-state region; it is the true, priority number and generally exceeds `1000 / end-to-end` because the runtime overlaps stages across frames. **Theoretical FPS** is the accelerator's **core** ceiling — `1000 / device-compute-time`, i.e. the throughput if the accelerator were the *only* bottleneck. It is taken from the isolated device-compute stage (on transfer-split runtimes the trace separates host↔device transfers from device compute), which is load-independent — unlike the host capture/preprocess service times, whose measured cost inflates under pipeline backpressure (the same 5000 JPEGs cost ~7.8 ms/frame serialized but far more under throughput backpressure), so the slowest-stage figure would *understate* a fast accelerator. It is a possibly-achievable ceiling, not a measured result: reaching it depends on the deployment pipeline. A validation run decodes a JPEG per image and evaluates at a `0.001` confidence threshold (to capture every detection for mAP), both of which load the host and postprocess stages; a production camera pipeline (no JPEG decode) at a deployment threshold of `0.25–0.75` (far fewer candidate boxes through NMS) moves realized throughput toward the theoretical ceiling.
+Two throughput figures are reported. **Realized FPS** is the *measured* steady-state rate at which final results are emitted, measured directly from the profiler's per-frame result-emission timestamps over the steady-state stream — trace-independent; the Perfetto trace's own FPS is used only as a fallback on sessions where that scalar isn't available. It is the true, priority number and generally exceeds `1000 / end-to-end` because the runtime overlaps stages across frames. **Core-throughput ceiling (FPS)** is the accelerator's **core** ceiling — `1000 / device-compute-time`, i.e. the throughput if the accelerator were the *only* bottleneck. It is taken from the isolated device-compute stage (on transfer-split runtimes the trace separates host↔device transfers from device compute), which is load-independent — unlike the host capture/preprocess service times, whose measured cost inflates under pipeline backpressure (the same 5000 JPEGs cost ~7.8 ms/frame serialized but far more under throughput backpressure), so the slowest-stage figure would *understate* a fast accelerator. It is a possibly-achievable ceiling, not a measured result: reaching it depends on the deployment pipeline. A validation run decodes a JPEG per image and evaluates at a `0.001` confidence threshold (to capture every detection for mAP), both of which load the host and postprocess stages; a production camera pipeline (no JPEG decode) at a deployment threshold of `0.25–0.75` (far fewer candidate boxes through NMS) moves realized throughput toward the core-throughput ceiling.
 
 See [EdgeFirst Studio](https://edgefirst.studio) for the full validation pipeline.