EdgeFirst
/

yolov5-det

@@ -101,52 +101,52 @@ Row conventions in the table below:
 - **Decoder variants.** EdgeFirst ships three INT8 split-decoders. The table headlines the accuracy-recovering ones: **smart** (per-tensor rescaling — best accuracy, extra CPU ops add some latency) and, where a smart run is absent, **logical** (the latency-optimized default — no CPU overhead, slightly lower accuracy). The **combined** decoder is the *standard-quantization baseline* (equivalent to typical single-scale INT8, and how the reference numbers are produced); it loses the most accuracy — especially on segmentation, where box/mask dynamic range collapses under one scale — so it is published only as a downloadable reference artifact and in the metrics export, never headlined here. Smart and logical exist precisely to recover that loss. Full converter documentation: [EdgeFirst model conversion](https://doc.edgefirst.ai/latest/models/conversion/) — these are the converters used by this Model Zoo and the EdgeFirst Performance Index report.
 - **Platform-label suffixes.** `(FRDM)` / `(Phytec)` name the NXP i.MX 95 development board a session ran on. `— latency` / `— throughput` mark the two pipeline configurations the NXP i.MX 95 Neutron and NXP Ara240 targets run: the **latency** pipeline runs inference serially for the lowest per-frame latency; the **throughput** pipeline runs multiple inference workers for the highest FPS, which raises per-call inference time in exchange. Rows with neither suffix run a single pipeline.
 - **End-to-end (ms)** is the sequential per-image latency of the compute pipeline — preprocess → inference → postprocess. Image acquisition (camera or file load + JPEG decode) overlaps these stages and is excluded from this figure.
-- **Realized FPS vs Theoretical FPS.** **Realized FPS** is the *measured* steady-state throughput — the rate at which final results are actually delivered over the full validation pipeline. It normally exceeds `1000 / end-to-end` because the runtime overlaps stages across frames, and it is the **true, priority number**. **Theoretical FPS** (shown with a `~`) is the accelerator's **core** ceiling — `1000 / device-compute-time`, the rate the NPU/DNPU could sustain *if it were the only bottleneck* — so it is a **possibly-achievable note, not a claim**. It is read from the isolated device-compute stage, which (unlike the host capture/preprocess stages, whose measured time inflates when the pipeline is backpressured) is stable and load-independent. Whether a deployment approaches it depends on the surrounding pipeline, and two levers dominate: (1) **host bottlenecks** — these validation runs decode a JPEG per image, whereas a live **camera pipeline** skips that decode and can run closer to the ceiling; and (2) **confidence threshold** — validation runs at `0.001` to capture every detection for mAP, which makes NMS/decode heavy, while a deployment threshold of `0.25–0.75` produces far fewer candidate boxes and lighter postprocessing, raising realized FPS toward the ceiling.
-| Size | Platform | mAP@0.5 | Δ vs FP32 (pp) | mAP@0.5-0.95 | Inference (ms) | End-to-end (ms) | Realized FPS | Theoretical FPS | Source |
-|------|----------|---------|----------------|--------------|----------------|-----------------|--------------|-----------------|--------|
-| Nano | ONNX FP32 (Intel Core i9-13900F · 32-core) | 47.76% | +0.01 | 32.95% | 34.27 | 45.08 | 80.1 | ~88 | [v-a45](https://edgefirst.studio/public/validation/v-a45/details?mode=charts) |
-| Nano | ONNX FP32 (CUDA) | 47.75% | ref | 32.95% | 7.71 | 12.85 | 357.8 | ~519 | [v-a87](https://edgefirst.studio/public/validation/v-a87/details?mode=charts) |
-| Nano | ONNX FP16 (CUDA) | 47.75% | +0.00 | 32.93% | 6.00 | 11.65 | 456.8 | ~518 | [v-a9c](https://edgefirst.studio/public/validation/v-a9c/details?mode=charts) |
-| Nano | Apple M2 Max — CoreML Neural Engine (FP16) | 47.12% | -0.63 | 32.42% | 1.79 | 5.22 | 812.3 | ~1117 | [v-735](https://edgefirst.studio/public/validation/v-735/details?mode=charts) |
-| Nano | Apple M2 Max — CoreML Metal GPU (FP16) | 47.16% | -0.59 | 32.45% | 5.53 | 9.41 | 477.4 | ~542 | [v-9cb](https://edgefirst.studio/public/validation/v-9cb/details?mode=charts) |
-| Nano | Apple M2 Max — CoreML CPU (FP16) | 47.14% | -0.61 | 32.43% | 15.43 | 19.38 | 121.3 | ~130 | [v-9cc](https://edgefirst.studio/public/validation/v-9cc/details?mode=charts) |
 | Nano | NXP i.MX 8M Plus + VeriSilicon NPU (FRDM) | 46.53% | -1.22 | 31.89% | 57.78 | 110.65 | 14.6 | ~17 | [v-8bf](https://edgefirst.studio/public/validation/v-8bf/details?mode=charts) |
 | Nano | NXP i.MX 95 + eIQ Neutron NPU (FRDM) — latency | 45.86% | -1.89 | 31.14% | 12.95 | 43.75 | 55.2 | ~56 | [v-8ad](https://edgefirst.studio/public/validation/v-8ad/details?mode=charts) |
-| Nano | NXP i.MX 95 + eIQ Neutron NPU (FRDM) — throughput | 45.86% | -1.89 | 31.14% | 20.97 | 59.88 | 75.1 | ~121 | [v-8ae](https://edgefirst.studio/public/validation/v-8ae/details?mode=charts) |
-| Nano | NXP i.MX 95 + eIQ Neutron NPU (Phytec) — throughput | 45.86% | -1.89 | 31.14% | 25.10 | 58.30 | 84.0 | ~159 | [v-897](https://edgefirst.studio/public/validation/v-897/details?mode=charts) |
-| Nano | NXP Ara240 (FRDM) — latency | 45.00% | -2.75 | 30.12% | 8.28 | 20.52 | 104.1 | ~121 | [v-a10](https://edgefirst.studio/public/validation/v-a10/details?mode=charts) |
 | Nano | NXP Ara240 (FRDM) — throughput | 44.99% | -2.76 | 30.11% | 8.66 | 31.50 | 193.5 | ~194 | [v-a11](https://edgefirst.studio/public/validation/v-a11/details?mode=charts) |
-| Nano | Raspberry Pi 5 + Hailo-8L NPU | 45.97% | -1.78 | 31.57% | 14.67 | 26.44 | 66.6 | ~68 | [v-8de](https://edgefirst.studio/public/validation/v-8de/details?mode=charts) |
-| Nano | NVIDIA Jetson Orin Nano (TensorRT FP16) | 47.77% | +0.02 | 32.93% | 8.54 | 23.99 | 271.2 | ~276 | [v-919](https://edgefirst.studio/public/validation/v-919/details?mode=charts) |
-| Small | ONNX FP32 (Intel Core i9-13900F · 32-core) | 57.32% | -0.01 | 41.26% | 82.06 | 93.67 | 33.6 | ~37 | [v-a4c](https://edgefirst.studio/public/validation/v-a4c/details?mode=charts) |
-| Small | ONNX FP32 (CUDA) | 57.33% | ref | 41.26% | 13.69 | 19.29 | 224.0 | ~292 | [v-a8e](https://edgefirst.studio/public/validation/v-a8e/details?mode=charts) |
-| Small | ONNX FP16 (CUDA) | 57.33% | +0.00 | 41.22% | 9.73 | 15.36 | 319.3 | ~411 | [v-aa3](https://edgefirst.studio/public/validation/v-aa3/details?mode=charts) |
-| Small | Apple M2 Max — CoreML Neural Engine (FP16) | 56.72% | -0.61 | 40.68% | 4.31 | 7.85 | 394.1 | ~464 | [v-9ea](https://edgefirst.studio/public/validation/v-9ea/details?mode=charts) |
-| Small | Apple M2 Max — CoreML Metal GPU (FP16) | 56.75% | -0.58 | 40.76% | 13.81 | 17.34 | 205.1 | ~217 | [v-9eb](https://edgefirst.studio/public/validation/v-9eb/details?mode=charts) |
-| Small | Apple M2 Max — CoreML CPU (FP16) | 56.72% | -0.61 | 40.71% | 29.96 | 34.04 | 64.2 | ~67 | [v-9ec](https://edgefirst.studio/public/validation/v-9ec/details?mode=charts) |
 | Small | NXP i.MX 8M Plus + VeriSilicon NPU (FRDM) | 56.87% | -0.46 | 40.69% | 109.41 | 161.03 | 8.3 | ~9 | [v-939](https://edgefirst.studio/public/validation/v-939/details?mode=charts) |
-| Small | NXP i.MX 95 + eIQ Neutron NPU (FRDM) — latency | 56.67% | -0.66 | 40.36% | 33.73 | 67.63 | 27.3 | ~30 | [v-8fa](https://edgefirst.studio/public/validation/v-8fa/details?mode=charts) |
-| Small | NXP i.MX 95 + eIQ Neutron NPU (FRDM) — throughput | 56.67% | -0.66 | 40.36% | 124.58 | 159.61 | 31.2 | ~32 | [v-8fb](https://edgefirst.studio/public/validation/v-8fb/details?mode=charts) |
-| Small | NXP i.MX 95 + eIQ Neutron NPU (Phytec) — throughput | 56.67% | -0.66 | 40.36% | 121.68 | 154.45 | 32.0 | ~33 | [v-8f0](https://edgefirst.studio/public/validation/v-8f0/details?mode=charts) |
-| Small | NXP Ara240 (FRDM) — latency | 54.56% | -2.77 | 37.69% | 13.47 | 25.54 | 68.1 | ~74 | [v-a1e](https://edgefirst.studio/public/validation/v-a1e/details?mode=charts) |
 | Small | NXP Ara240 (FRDM) — throughput | 54.54% | -2.79 | 37.67% | 13.50 | 26.58 | 96.3 | ~96 | [v-a1f](https://edgefirst.studio/public/validation/v-a1f/details?mode=charts) |
-| Small | Raspberry Pi 5 + Hailo-8L NPU | 56.13% | -1.20 | 40.02% | 29.36 | 43.90 | 32.1 | ~34 | [v-8eb](https://edgefirst.studio/public/validation/v-8eb/details?mode=charts) |
-| Small | NVIDIA Jetson Orin Nano (TensorRT FP16) | 57.32% | -0.01 | 41.24% | 22.04 | 34.77 | 174.6 | ~182 | [v-921](https://edgefirst.studio/public/validation/v-921/details?mode=charts) |
-| Medium | ONNX FP32 (Intel Core i9-13900F · 32-core) | 63.29% | +0.00 | 46.99% | 200.15 | 211.96 | 14.1 | ~15 | [v-a53](https://edgefirst.studio/public/validation/v-a53/details?mode=charts) |
-| Medium | ONNX FP32 (CUDA) | 63.29% | ref | 46.99% | 33.81 | 40.48 | 97.0 | ~118 | [v-a95](https://edgefirst.studio/public/validation/v-a95/details?mode=charts) |
-| Medium | ONNX FP16 (CUDA) | 63.27% | -0.02 | 46.94% | 20.03 | 26.34 | 166.1 | ~200 | [v-aaa](https://edgefirst.studio/public/validation/v-aaa/details?mode=charts) |
-| Medium | Apple M2 Max — CoreML Neural Engine (FP16) | 62.78% | -0.51 | 46.53% | 11.53 | 15.16 | 162.2 | ~173 | [v-75b](https://edgefirst.studio/public/validation/v-75b/details?mode=charts) |
-| Medium | Apple M2 Max — CoreML Metal GPU (FP16) | 62.80% | -0.49 | 46.52% | 33.27 | 37.50 | 87.8 | ~90 | [v-765](https://edgefirst.studio/public/validation/v-765/details?mode=charts) |
 | Medium | Apple M2 Max — CoreML CPU (FP16) | 62.75% | -0.54 | 46.46% | 56.58 | 60.68 | 34.6 | ~35 | [v-9dc](https://edgefirst.studio/public/validation/v-9dc/details?mode=charts) |
 | Medium | NXP i.MX 8M Plus + VeriSilicon NPU (FRDM) | 62.79% | -0.50 | 46.34% | 206.67 | 258.59 | 4.6 | ~5 | [v-97b](https://edgefirst.studio/public/validation/v-97b/details?mode=charts) |
-| Medium | NXP i.MX 95 + eIQ Neutron NPU (FRDM) — latency | 62.77% | -0.52 | 46.30% | 78.06 | 110.95 | 12.3 | ~13 | [v-96b](https://edgefirst.studio/public/validation/v-96b/details?mode=charts) |
 | Medium | NXP i.MX 95 + eIQ Neutron NPU (FRDM) — throughput | 62.77% | -0.52 | 46.30% | 301.76 | 335.74 | 13.1 | ~13 | [v-96c](https://edgefirst.studio/public/validation/v-96c/details?mode=charts) |
 | Medium | NXP i.MX 95 + eIQ Neutron NPU (Phytec) — throughput | 62.77% | -0.52 | 46.30% | 297.44 | 329.30 | 13.2 | ~13 | [v-94b](https://edgefirst.studio/public/validation/v-94b/details?mode=charts) |
-| Medium | NXP Ara240 (FRDM) — latency | 60.72% | -2.57 | 43.55% | 24.38 | 36.41 | 39.0 | ~41 | [v-a2c](https://edgefirst.studio/public/validation/v-a2c/details?mode=charts) |
 | Medium | NXP Ara240 (FRDM) — throughput | 60.70% | -2.59 | 43.54% | 24.36 | 37.19 | 47.0 | ~47 | [v-a2d](https://edgefirst.studio/public/validation/v-a2d/details?mode=charts) |
-| Medium | Raspberry Pi 5 + Hailo-8L NPU | 62.40% | -0.89 | 46.17% | 57.38 | 72.71 | 16.2 | ~17 | [v-906](https://edgefirst.studio/public/validation/v-906/details?mode=charts) |
-| Medium | NVIDIA Jetson Orin Nano (TensorRT FP16) | 63.31% | +0.02 | 46.96% | 44.49 | 56.80 | 88.2 | ~90 | [v-92a](https://edgefirst.studio/public/validation/v-92a/details?mode=charts) |
@@ -162,7 +162,7 @@ These results are produced by the EdgeFirst on-target validation pipeline:
 Inference latency is reported as the on-accelerator inference time. End-to-end latency is the sequential per-image latency across the compute pipeline — preprocessing, inference, and postprocessing; image acquisition (file or camera load and JPEG decode) overlaps these stages and is excluded from this figure.
-Two throughput figures are reported. **Realized FPS** is the *measured* steady-state rate at which final results are emitted, computed from the Perfetto trace as `(N-1) / (t_last - t_first)` over the warmup-trimmed steady-state region; it is the true, priority number and generally exceeds `1000 / end-to-end` because the runtime overlaps stages across frames. **Theoretical FPS** is the accelerator's **core** ceiling — `1000 / device-compute-time`, i.e. the throughput if the accelerator were the *only* bottleneck. It is taken from the isolated device-compute stage (on transfer-split runtimes the trace separates host↔device transfers from device compute), which is load-independent — unlike the host capture/preprocess service times, whose measured cost inflates under pipeline backpressure (the same 5000 JPEGs cost ~7.8 ms/frame serialized but far more under throughput backpressure), so the slowest-stage figure would *understate* a fast accelerator. It is a possibly-achievable ceiling, not a measured result: reaching it depends on the deployment pipeline. A validation run decodes a JPEG per image and evaluates at a `0.001` confidence threshold (to capture every detection for mAP), both of which load the host and postprocess stages; a production camera pipeline (no JPEG decode) at a deployment threshold of `0.25–0.75` (far fewer candidate boxes through NMS) moves realized throughput toward the theoretical ceiling.
 See [EdgeFirst Studio](https://edgefirst.studio) for the full validation pipeline.

 - **Decoder variants.** EdgeFirst ships three INT8 split-decoders. The table headlines the accuracy-recovering ones: **smart** (per-tensor rescaling — best accuracy, extra CPU ops add some latency) and, where a smart run is absent, **logical** (the latency-optimized default — no CPU overhead, slightly lower accuracy). The **combined** decoder is the *standard-quantization baseline* (equivalent to typical single-scale INT8, and how the reference numbers are produced); it loses the most accuracy — especially on segmentation, where box/mask dynamic range collapses under one scale — so it is published only as a downloadable reference artifact and in the metrics export, never headlined here. Smart and logical exist precisely to recover that loss. Full converter documentation: [EdgeFirst model conversion](https://doc.edgefirst.ai/latest/models/conversion/) — these are the converters used by this Model Zoo and the EdgeFirst Performance Index report.
 - **Platform-label suffixes.** `(FRDM)` / `(Phytec)` name the NXP i.MX 95 development board a session ran on. `— latency` / `— throughput` mark the two pipeline configurations the NXP i.MX 95 Neutron and NXP Ara240 targets run: the **latency** pipeline runs inference serially for the lowest per-frame latency; the **throughput** pipeline runs multiple inference workers for the highest FPS, which raises per-call inference time in exchange. Rows with neither suffix run a single pipeline.
 - **End-to-end (ms)** is the sequential per-image latency of the compute pipeline — preprocess → inference → postprocess. Image acquisition (camera or file load + JPEG decode) overlaps these stages and is excluded from this figure.
+- **Realized FPS vs Core-throughput ceiling (FPS).** **Realized FPS** is the *measured* steady-state throughput — the rate at which final results are actually delivered over the full validation pipeline. It normally exceeds `1000 / end-to-end` because the runtime overlaps stages across frames, and it is the **true, priority number**. **Core-throughput ceiling (FPS)** (shown with a `~`) is the accelerator's **core** ceiling — `1000 / device-compute-time`, the rate the NPU/DNPU could sustain *if it were the only bottleneck* — so it is a **possibly-achievable note, not a claim**. It is read from the isolated device-compute stage, which (unlike the host capture/preprocess stages, whose measured time inflates when the pipeline is backpressured) is stable and load-independent. Whether a deployment approaches it depends on the surrounding pipeline, and two levers dominate: (1) **host bottlenecks** — these validation runs decode a JPEG per image, whereas a live **camera pipeline** skips that decode and can run closer to the ceiling; and (2) **confidence threshold** — validation runs at `0.001` to capture every detection for mAP, which makes NMS/decode heavy, while a deployment threshold of `0.25–0.75` produces far fewer candidate boxes and lighter postprocessing, raising realized FPS toward the ceiling.
+| Size | Platform | mAP@0.5 | Δ vs FP32 (pp) | mAP@0.5-0.95 | Inference (ms) | End-to-end (ms) | Realized FPS | Core-throughput ceiling (FPS) | Source |
+|------|----------|---------|----------------|--------------|----------------|-----------------|--------------|-------------------------------|--------|
+| Nano | ONNX FP32 (Intel Core i9-13900F · 32-core) | 47.76% | +0.01 | 32.95% | 34.27 | 45.08 | 80.1 | ~80 | [v-a45](https://edgefirst.studio/public/validation/v-a45/details?mode=charts) |
+| Nano | ONNX FP32 (CUDA) | 47.75% | ref | 32.95% | 7.71 | 12.85 | 357.8 | ~358 | [v-a87](https://edgefirst.studio/public/validation/v-a87/details?mode=charts) |
+| Nano | ONNX FP16 (CUDA) | 47.75% | +0.00 | 32.93% | 6.00 | 11.65 | 456.8 | ~457 | [v-a9c](https://edgefirst.studio/public/validation/v-a9c/details?mode=charts) |
+| Nano | Apple M2 Max — CoreML Neural Engine (FP16) | 47.12% | -0.63 | 32.42% | 1.79 | 5.22 | 812.3 | ~817 | [v-735](https://edgefirst.studio/public/validation/v-735/details?mode=charts) |
+| Nano | Apple M2 Max — CoreML Metal GPU (FP16) | 47.16% | -0.59 | 32.45% | 5.53 | 9.41 | 477.4 | ~477 | [v-9cb](https://edgefirst.studio/public/validation/v-9cb/details?mode=charts) |
+| Nano | Apple M2 Max — CoreML CPU (FP16) | 47.14% | -0.61 | 32.43% | 15.43 | 19.38 | 121.3 | ~121 | [v-9cc](https://edgefirst.studio/public/validation/v-9cc/details?mode=charts) |
 | Nano | NXP i.MX 8M Plus + VeriSilicon NPU (FRDM) | 46.53% | -1.22 | 31.89% | 57.78 | 110.65 | 14.6 | ~17 | [v-8bf](https://edgefirst.studio/public/validation/v-8bf/details?mode=charts) |
 | Nano | NXP i.MX 95 + eIQ Neutron NPU (FRDM) — latency | 45.86% | -1.89 | 31.14% | 12.95 | 43.75 | 55.2 | ~56 | [v-8ad](https://edgefirst.studio/public/validation/v-8ad/details?mode=charts) |
+| Nano | NXP i.MX 95 + eIQ Neutron NPU (FRDM) — throughput | 45.86% | -1.89 | 31.14% | 20.97 | 59.88 | 75.1 | ~45 | [v-8ae](https://edgefirst.studio/public/validation/v-8ae/details?mode=charts) |
+| Nano | NXP i.MX 95 + eIQ Neutron NPU (Phytec) — throughput | 45.86% | -1.89 | 31.14% | 25.10 | 58.30 | 84.0 | ~49 | [v-897](https://edgefirst.studio/public/validation/v-897/details?mode=charts) |
+| Nano | NXP Ara240 (FRDM) — latency | 45.00% | -2.75 | 30.12% | 8.28 | 20.52 | 104.1 | ~106 | [v-a10](https://edgefirst.studio/public/validation/v-a10/details?mode=charts) |
 | Nano | NXP Ara240 (FRDM) — throughput | 44.99% | -2.76 | 30.11% | 8.66 | 31.50 | 193.5 | ~194 | [v-a11](https://edgefirst.studio/public/validation/v-a11/details?mode=charts) |
+| Nano | Raspberry Pi 5 + Hailo-8L NPU | 45.97% | -1.78 | 31.57% | 14.67 | 26.44 | 66.6 | ~67 | [v-8de](https://edgefirst.studio/public/validation/v-8de/details?mode=charts) |
+| Nano | NVIDIA Jetson Orin Nano (TensorRT FP16) | 47.77% | +0.02 | 32.93% | 8.54 | 23.99 | 271.2 | ~271 | [v-919](https://edgefirst.studio/public/validation/v-919/details?mode=charts) |
+| Small | ONNX FP32 (Intel Core i9-13900F · 32-core) | 57.32% | -0.01 | 41.26% | 82.06 | 93.67 | 33.6 | ~34 | [v-a4c](https://edgefirst.studio/public/validation/v-a4c/details?mode=charts) |
+| Small | ONNX FP32 (CUDA) | 57.33% | ref | 41.26% | 13.69 | 19.29 | 224.0 | ~224 | [v-a8e](https://edgefirst.studio/public/validation/v-a8e/details?mode=charts) |
+| Small | ONNX FP16 (CUDA) | 57.33% | +0.00 | 41.22% | 9.73 | 15.36 | 319.3 | ~319 | [v-aa3](https://edgefirst.studio/public/validation/v-aa3/details?mode=charts) |
+| Small | Apple M2 Max — CoreML Neural Engine (FP16) | 56.72% | -0.61 | 40.68% | 4.31 | 7.85 | 394.1 | ~404 | [v-9ea](https://edgefirst.studio/public/validation/v-9ea/details?mode=charts) |
+| Small | Apple M2 Max — CoreML Metal GPU (FP16) | 56.75% | -0.58 | 40.76% | 13.81 | 17.34 | 205.1 | ~205 | [v-9eb](https://edgefirst.studio/public/validation/v-9eb/details?mode=charts) |
+| Small | Apple M2 Max — CoreML CPU (FP16) | 56.72% | -0.61 | 40.71% | 29.96 | 34.04 | 64.2 | ~64 | [v-9ec](https://edgefirst.studio/public/validation/v-9ec/details?mode=charts) |
 | Small | NXP i.MX 8M Plus + VeriSilicon NPU (FRDM) | 56.87% | -0.46 | 40.69% | 109.41 | 161.03 | 8.3 | ~9 | [v-939](https://edgefirst.studio/public/validation/v-939/details?mode=charts) |
+| Small | NXP i.MX 95 + eIQ Neutron NPU (FRDM) — latency | 56.67% | -0.66 | 40.36% | 33.73 | 67.63 | 27.3 | ~27 | [v-8fa](https://edgefirst.studio/public/validation/v-8fa/details?mode=charts) |
+| Small | NXP i.MX 95 + eIQ Neutron NPU (FRDM) — throughput | 56.67% | -0.66 | 40.36% | 124.58 | 159.61 | 31.2 | ~31 | [v-8fb](https://edgefirst.studio/public/validation/v-8fb/details?mode=charts) |
+| Small | NXP i.MX 95 + eIQ Neutron NPU (Phytec) — throughput | 56.67% | -0.66 | 40.36% | 121.68 | 154.45 | 32.0 | ~32 | [v-8f0](https://edgefirst.studio/public/validation/v-8f0/details?mode=charts) |
+| Small | NXP Ara240 (FRDM) — latency | 54.56% | -2.77 | 37.69% | 13.47 | 25.54 | 68.1 | ~68 | [v-a1e](https://edgefirst.studio/public/validation/v-a1e/details?mode=charts) |
 | Small | NXP Ara240 (FRDM) — throughput | 54.54% | -2.79 | 37.67% | 13.50 | 26.58 | 96.3 | ~96 | [v-a1f](https://edgefirst.studio/public/validation/v-a1f/details?mode=charts) |
+| Small | Raspberry Pi 5 + Hailo-8L NPU | 56.13% | -1.20 | 40.02% | 29.36 | 43.90 | 32.1 | ~32 | [v-8eb](https://edgefirst.studio/public/validation/v-8eb/details?mode=charts) |
+| Small | NVIDIA Jetson Orin Nano (TensorRT FP16) | 57.32% | -0.01 | 41.24% | 22.04 | 34.77 | 174.6 | ~174 | [v-921](https://edgefirst.studio/public/validation/v-921/details?mode=charts) |
+| Medium | ONNX FP32 (Intel Core i9-13900F · 32-core) | 63.29% | +0.00 | 46.99% | 200.15 | 211.96 | 14.1 | ~14 | [v-a53](https://edgefirst.studio/public/validation/v-a53/details?mode=charts) |
+| Medium | ONNX FP32 (CUDA) | 63.29% | ref | 46.99% | 33.81 | 40.48 | 97.0 | ~97 | [v-a95](https://edgefirst.studio/public/validation/v-a95/details?mode=charts) |
+| Medium | ONNX FP16 (CUDA) | 63.27% | -0.02 | 46.94% | 20.03 | 26.34 | 166.1 | ~166 | [v-aaa](https://edgefirst.studio/public/validation/v-aaa/details?mode=charts) |
+| Medium | Apple M2 Max — CoreML Neural Engine (FP16) | 62.78% | -0.51 | 46.53% | 11.53 | 15.16 | 162.2 | ~164 | [v-75b](https://edgefirst.studio/public/validation/v-75b/details?mode=charts) |
+| Medium | Apple M2 Max — CoreML Metal GPU (FP16) | 62.80% | -0.49 | 46.52% | 33.27 | 37.50 | 87.8 | ~88 | [v-765](https://edgefirst.studio/public/validation/v-765/details?mode=charts) |
 | Medium | Apple M2 Max — CoreML CPU (FP16) | 62.75% | -0.54 | 46.46% | 56.58 | 60.68 | 34.6 | ~35 | [v-9dc](https://edgefirst.studio/public/validation/v-9dc/details?mode=charts) |
 | Medium | NXP i.MX 8M Plus + VeriSilicon NPU (FRDM) | 62.79% | -0.50 | 46.34% | 206.67 | 258.59 | 4.6 | ~5 | [v-97b](https://edgefirst.studio/public/validation/v-97b/details?mode=charts) |
+| Medium | NXP i.MX 95 + eIQ Neutron NPU (FRDM) — latency | 62.77% | -0.52 | 46.30% | 78.06 | 110.95 | 12.3 | ~12 | [v-96b](https://edgefirst.studio/public/validation/v-96b/details?mode=charts) |
 | Medium | NXP i.MX 95 + eIQ Neutron NPU (FRDM) — throughput | 62.77% | -0.52 | 46.30% | 301.76 | 335.74 | 13.1 | ~13 | [v-96c](https://edgefirst.studio/public/validation/v-96c/details?mode=charts) |
 | Medium | NXP i.MX 95 + eIQ Neutron NPU (Phytec) — throughput | 62.77% | -0.52 | 46.30% | 297.44 | 329.30 | 13.2 | ~13 | [v-94b](https://edgefirst.studio/public/validation/v-94b/details?mode=charts) |
+| Medium | NXP Ara240 (FRDM) — latency | 60.72% | -2.57 | 43.55% | 24.38 | 36.41 | 39.0 | ~39 | [v-a2c](https://edgefirst.studio/public/validation/v-a2c/details?mode=charts) |
 | Medium | NXP Ara240 (FRDM) — throughput | 60.70% | -2.59 | 43.54% | 24.36 | 37.19 | 47.0 | ~47 | [v-a2d](https://edgefirst.studio/public/validation/v-a2d/details?mode=charts) |
+| Medium | Raspberry Pi 5 + Hailo-8L NPU | 62.40% | -0.89 | 46.17% | 57.38 | 72.71 | 16.2 | ~16 | [v-906](https://edgefirst.studio/public/validation/v-906/details?mode=charts) |
+| Medium | NVIDIA Jetson Orin Nano (TensorRT FP16) | 63.31% | +0.02 | 46.96% | 44.49 | 56.80 | 88.2 | ~88 | [v-92a](https://edgefirst.studio/public/validation/v-92a/details?mode=charts) |
 Inference latency is reported as the on-accelerator inference time. End-to-end latency is the sequential per-image latency across the compute pipeline — preprocessing, inference, and postprocessing; image acquisition (file or camera load and JPEG decode) overlaps these stages and is excluded from this figure.
+Two throughput figures are reported. **Realized FPS** is the *measured* steady-state rate at which final results are emitted, measured directly from the profiler's per-frame result-emission timestamps over the steady-state stream — trace-independent; the Perfetto trace's own FPS is used only as a fallback on sessions where that scalar isn't available. It is the true, priority number and generally exceeds `1000 / end-to-end` because the runtime overlaps stages across frames. **Core-throughput ceiling (FPS)** is the accelerator's **core** ceiling — `1000 / device-compute-time`, i.e. the throughput if the accelerator were the *only* bottleneck. It is taken from the isolated device-compute stage (on transfer-split runtimes the trace separates host↔device transfers from device compute), which is load-independent — unlike the host capture/preprocess service times, whose measured cost inflates under pipeline backpressure (the same 5000 JPEGs cost ~7.8 ms/frame serialized but far more under throughput backpressure), so the slowest-stage figure would *understate* a fast accelerator. It is a possibly-achievable ceiling, not a measured result: reaching it depends on the deployment pipeline. A validation run decodes a JPEG per image and evaluates at a `0.001` confidence threshold (to capture every detection for mAP), both of which load the host and postprocess stages; a production camera pipeline (no JPEG decode) at a deployment threshold of `0.25–0.75` (far fewer candidate boxes through NMS) moves realized throughput toward the core-throughput ceiling.
 See [EdgeFirst Studio](https://edgefirst.studio) for the full validation pipeline.