Update model card for yolov5-det
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README.md
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@@ -55,7 +55,7 @@ Part of the [EdgeFirst Model Zoo](https://huggingface.co/spaces/EdgeFirst/Models
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> [!NOTE]
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> Legacy architecture, wide deployment base.
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[](https://huggingface.co/spaces/EdgeFirst/Models) [](https://huggingface.co/spaces/EdgeFirst/Models) [](https://huggingface.co/spaces/EdgeFirst/Models) [](https://huggingface.co/spaces/EdgeFirst/Models) [ |
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| Small | NVIDIA Jetson Orin Nano (TensorRT FP16) | 57.34% | +0.00 | 41.25% | 13.33 | 22.72 | 124.6 | [v-4d6](https://edgefirst.studio/public/validation/v-4d6/details?mode=charts) |
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| Small | NVIDIA Jetson Orin Nano (TensorRT FP16) | 57.32% | -0.01 | 41.24% | 22.04 | 34.77 | 175.0 | [v-921](https://edgefirst.studio/public/validation/v-921/details?mode=charts) |
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| Medium | ONNX FP32 (AWS Graviton Β· 48-core) | 63.30% | +0.01 | 47.00% | 154.67 | 163.39 | 24.0 | [v-717](https://edgefirst.studio/public/validation/v-717/details?mode=charts) |
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| Medium | ONNX FP32 (CUDA) | 63.29% | ref | 46.99% | 33.90 | 40.43 | 96.0 | [v-6f6](https://edgefirst.studio/public/validation/v-6f6/details?mode=charts) |
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| Medium | ONNX FP16 (CUDA) | 63.27% | -0.02 | 46.93% | 20.12 | 26.31 | 167.0 | [v-6f7](https://edgefirst.studio/public/validation/v-6f7/details?mode=charts) |
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| Medium | macOS CoreML β Neural Engine (FP16) | 62.78% | -0.51 | 46.53% | 11.53 | 15.16 | 163.0 | [v-75b](https://edgefirst.studio/public/validation/v-75b/details?mode=charts) |
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| Medium | macOS CoreML β Metal GPU (FP16) | 62.80% | -0.49 | 46.52% | 33.27 | 37.50 | 87.0 | [v-765](https://edgefirst.studio/public/validation/v-765/details?mode=charts) |
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| Medium | macOS CoreML β CPU (FP16) | 62.75% | -0.54 | 46.46% | 56.58 | 60.68 | 34.0 | [v-9dc](https://edgefirst.studio/public/validation/v-9dc/details?mode=charts) |
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| Medium | NXP i.MX 8M Plus + VeriSilicon NPU | 59.62% | -3.67 | 41.74% | 212.31 | 245.94 | 4.0 | [v-777](https://edgefirst.studio/public/validation/v-777/details?mode=charts) |
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| Medium | NXP i.MX 8M Plus + VeriSilicon NPU | 61.97% | -1.32 | 45.77% | 206.33 | 256.67 | 5.0 | [v-760](https://edgefirst.studio/public/validation/v-760/details?mode=charts) |
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| Medium | NXP i.MX 8M Plus + VeriSilicon NPU (FRDM) | 62.79% | -0.50 | 46.34% | 206.67 | 258.59 | 5.0 | [v-97b](https://edgefirst.studio/public/validation/v-97b/details?mode=charts) |
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| Medium | NXP i.MX 8M Plus + VeriSilicon NPU (FRDM) | 59.62% | -3.67 | 41.74% | 212.49 | 247.33 | 4.0 | [v-975](https://edgefirst.studio/public/validation/v-975/details?mode=charts) |
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| Medium | NXP i.MX 95 + eIQ Neutron NPU β throughput | 59.40% | -3.89 | 41.61% | 300.00 | 311.83 | 13.0 | [v-76f](https://edgefirst.studio/public/validation/v-76f/details?mode=charts) |
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| Medium | NXP i.MX 95 + eIQ Neutron NPU β throughput | 61.95% | -1.34 | 45.73% | 301.77 | 325.55 | 13.0 | [v-75f](https://edgefirst.studio/public/validation/v-75f/details?mode=charts) |
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| Medium | NXP i.MX 95 + eIQ Neutron NPU (FRDM) β latency | 62.77% | -0.52 | 46.30% | 78.06 | 110.95 | 12.0 | [v-96b](https://edgefirst.studio/public/validation/v-96b/details?mode=charts) |
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| Medium | NXP i.MX 95 + eIQ Neutron NPU (FRDM) β latency | 59.40% | -3.89 | 41.61% | 112.99 | 127.12 | 9.0 | [v-966](https://edgefirst.studio/public/validation/v-966/details?mode=charts) |
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| Medium | NXP i.MX 95 + eIQ Neutron NPU (FRDM) β throughput | 62.77% | -0.52 | 46.30% | 301.76 | 335.74 | 13.0 | [v-96c](https://edgefirst.studio/public/validation/v-96c/details?mode=charts) |
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| Medium | NXP i.MX 95 + eIQ Neutron NPU (FRDM) β throughput | 59.40% | -3.89 | 41.61% | 304.16 | 320.96 | 13.0 | [v-967](https://edgefirst.studio/public/validation/v-967/details?mode=charts) |
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| Medium | NXP i.MX 95 + eIQ Neutron NPU (Phytec) β throughput | 62.77% | -0.52 | 46.30% | 297.44 | 329.30 | 13.0 | [v-94b](https://edgefirst.studio/public/validation/v-94b/details?mode=charts) |
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| Medium | NXP Ara240 | 60.70% | -2.59 | 43.54% | 24.48 | 41.38 | 47.0 | [v-796](https://edgefirst.studio/public/validation/v-796/details?mode=charts) |
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| Medium | NXP Ara240 (FRDM) | 60.70% | -2.59 | 43.54% | 24.34 | 37.15 | 47.0 | [v-907](https://edgefirst.studio/public/validation/v-907/details?mode=charts) |
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| Medium | Raspberry Pi 5 + Hailo-8L NPU | 62.40% | -0.89 | 46.17% | 57.38 | 72.71 | 16.0 | [v-906](https://edgefirst.studio/public/validation/v-906/details?mode=charts) |
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| Medium | NVIDIA Jetson Orin Nano (TensorRT FP16) | 63.31% | +0.02 | 46.96% | 44.25 | 56.88 | 88.5 | [v-6de](https://edgefirst.studio/public/validation/v-6de/details?mode=charts) |
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| Medium | NVIDIA Jetson Orin Nano (TensorRT FP16) | 63.31% | +0.02 | 46.96% | 44.49 | 56.80 | 88.0 | [v-92a](https://edgefirst.studio/public/validation/v-92a/details?mode=charts) |
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2. **EdgeFirst Validator** consumes the predictions and trace, computes `pycocotools` accuracy metrics and per-stage timing summaries, and publishes the results to the Studio validation session.
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3. **EdgeFirst HAL** ([open source](https://github.com/EdgeFirstAI/hal)) provides the hardware-accelerated preprocessing and post-decoding primitives used at both validation and deployment time, so the timings measured here reflect the same accelerated paths a production runtime would take.
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Inference latency is reported as the on-accelerator inference time. End-to-end latency is the sequential per-image
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See [EdgeFirst Studio](https://edgefirst.studio) for the full validation pipeline.
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Artifacts are organized by deployment target. Each model file embeds the EdgeFirst `edgefirst.json` metadata (training session, dataset version, calibration artifact, converter chain) so a single file is sufficient for deployment β no sidecar configuration required.
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---
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```
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[EdgeFirst HAL](https://github.com/EdgeFirstAI/hal) β Hardware abstraction layer with accelerated inference delegates.
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---
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## Traceability
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1. **ONNX export** β standard Ultralytics export with `simplify=True`
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2. **TF-wrapped ONNX** β box coordinates normalized to `[0, 1]` inside DFL decode
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3. **Split decoder** β boxes
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4. **Smart calibration** β calibration samples selected via greedy coverage maximization; the artifact is content-addressed by parameter hash and cached in Studio for deterministic reuse
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5. **Full integer INT8** β `uint8` input, `int8` output, MLIR quantizer
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## Limitations
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- **COCO bias** β models trained on COCO (80 classes) inherit the dataset's biases (Western-centric scenes, particular object distributions, limited weather/lighting diversity).
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- **
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- **Input resolution** β all models expect 640Γ640 input; other resolutions require letterboxing.
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---
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> [!NOTE]
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> Legacy architecture, wide deployment base.
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[](https://huggingface.co/spaces/EdgeFirst/Models) [](https://huggingface.co/spaces/EdgeFirst/Models) [](https://huggingface.co/spaces/EdgeFirst/Models) [](https://huggingface.co/spaces/EdgeFirst/Models) [](https://huggingface.co/spaces/EdgeFirst/Models) [](https://huggingface.co/spaces/EdgeFirst/Models) [](https://huggingface.co/spaces/EdgeFirst/Models) [](https://huggingface.co/spaces/EdgeFirst/Models)
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---
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## Reference accuracy β ONNX FP32
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| Large | 46.5M | 109.1 | β | β | β | β |
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| XLarge | 86.7M | 205.7 | β | β | β | β |
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> **Sizes.** The EdgeFirst Model Zoo currently validates **Nano, Small, and Medium**. The Large and XLarge variants are not evaluated at this time β their parameter and GFLOP counts are listed above for reference, with accuracy shown as `β`.
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### Accuracy methodology & relation to Ultralytics
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Every model in this zoo uses the **official Ultralytics pretrained weights, byte-for-byte** β there is no re-training. These are the *same models* Ultralytics ships, measured on the **deployment-realistic path**: a fixed-input ONNX graph (square letterbox, `rect=False`), stock `pycocotools` `AP@[maxDets=100]`, and COCO crowd regions scored as normal detections. Ultralytics' headline COCO numbers use their internal validator (rectangular inference, crowd-ignored, `maxDets=300`), so a small, fully-explained offset on identical weights is expected β not an accuracy deficit.
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Reconciling **nano** detection (COCO `val2017`, mAP@0.5:0.95, FP32):
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| Source | Nano mAP@0.5:0.95 | What it measures |
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|--------|-------------------|------------------|
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| **EdgeFirst (this zoo)** | 32.95% | Full deployment path β fixed-input ONNX + `pycocotools` |
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| Ultralytics-validator proxy | 33.71% | Portable re-implementation of the Ultralytics validator |
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| Ultralytics (official) | 34.3% | Ultralytics' published COCO figure |
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The ~1 pp spread decomposes into a ~0.6β0.7 pp **methodology** leg (square-letterbox / crowd / `maxDets`) and a ~0.5β0.9 pp **deployment-decode** leg. The methodology leg is measured, not assumed: a `rect=True` + crowd-ignored parity pass reproduces the official figure (e.g. YOLOv5n β 34.4 vs 34.3 official). The decode leg shrinks toward zero for the NMS-free YOLO26, which already matches its official number. None of the offset reflects a weight or training difference.
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---
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## On-target validation results
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Row conventions in the table below:
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- **Rows whose `Ξ` cell reads `ref`** are the float reference runs each quantized/compiled measurement is graded against.
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- **Rows without a number** under the metric columns are validation sessions currently in progress, or a session not yet linked to its ONNX FP32 reference. The Studio Source link tracks the current status.
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- **Rows whose `Ξ vs FP32` cell carries a β ** are below our accuracy expectations for that platform (more than 10 percentage points under the float reference). The numbers are real measurements on real hardware, reproducible from the linked Studio session, and we publish them as-is; we are investigating the results to make improvements, and the next snapshot of this card will reflect any recovered accuracy.
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- **Precision** varies by target: the ONNX reference rows are FP32; macOS CoreML and NVIDIA Jetson TensorRT run FP16; the NXP i.MX 8M Plus, NXP i.MX 95 Neutron, and Hailo NPUs run INT8. The NXP Ara240 DNPU runs a **mixed INT8/INT16** scheme β most of the model is INT8, with the box-regression path (and the ops feeding it) promoted to INT16 to improve localization accuracy.
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- **Decoder variants.** EdgeFirst ships three INT8 split-decoders. The table headlines the accuracy-recovering ones: **smart** (per-tensor rescaling β best accuracy, extra CPU ops add some latency) and, where a smart run is absent, **logical** (the latency-optimized default β no CPU overhead, slightly lower accuracy). The **combined** decoder is the *standard-quantization baseline* (equivalent to typical single-scale INT8, and how the reference numbers are produced); it loses the most accuracy β especially on segmentation, where box/mask dynamic range collapses under one scale β so it is published only as a downloadable reference artifact and in the metrics export, never headlined here. Smart and logical exist precisely to recover that loss.
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- **Platform-label suffixes.** `(FRDM)` / `(Phytec)` name the NXP i.MX 95 development board a session ran on. `β latency` / `β throughput` mark the two pipeline configurations the NXP i.MX 95 Neutron and NXP Ara240 targets run: the **latency** pipeline runs inference serially for the lowest per-frame latency; the **throughput** pipeline runs multiple inference workers for the highest FPS, which raises per-call inference time in exchange. Rows with neither suffix run a single pipeline.
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- **End-to-end (ms)** is the sequential per-image latency of the compute pipeline β preprocess β inference β postprocess. Image acquisition (camera or file load + JPEG decode) overlaps these stages and is excluded from this figure.
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- **Realized FPS vs Theoretical FPS.** **Realized FPS** is the *measured* steady-state throughput β the rate at which final results are actually delivered over the full validation pipeline. It normally exceeds `1000 / end-to-end` because the runtime overlaps stages across frames, and it is the **true, priority number**. **Theoretical FPS** (shown with a `~`) is the per-stage accelerator ceiling β the rate the NPU/DNPU could sustain *if it were the only bottleneck* β so it is a **possibly-achievable note, not a claim**. Whether a deployment approaches it depends on the surrounding pipeline, and two levers dominate: (1) **host bottlenecks** β these validation runs decode a JPEG per image, whereas a live **camera pipeline** skips that decode and can run closer to the ceiling; and (2) **confidence threshold** β validation runs at `0.001` to capture every detection for mAP, which makes NMS/decode heavy, while a deployment threshold of `0.25β0.75` produces far fewer candidate boxes and lighter postprocessing, raising realized FPS toward the ceiling.
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| Size | Platform | mAP@0.5 | Ξ vs FP32 (pp) | mAP@0.5-0.95 | Inference (ms) | End-to-end (ms) | Realized FPS | Theoretical FPS | Source |
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|------|----------|---------|----------------|--------------|----------------|-----------------|--------------|-----------------|--------|
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| Nano | ONNX FP32 (AWS Graviton Β· 48-core) | 47.74% | -0.01 | 32.94% | 28.38 | 37.06 | 131.4 | ~141 | [v-715](https://edgefirst.studio/public/validation/v-715/details?mode=charts) |
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| Nano | ONNX FP32 (CUDA) | 47.75% | ref | 32.95% | 7.71 | 12.97 | 357.9 | ~514 | [v-6f0](https://edgefirst.studio/public/validation/v-6f0/details?mode=charts) |
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| Nano | ONNX FP16 (CUDA) | 47.75% | +0.00 | 32.93% | 6.06 | 11.63 | 455.4 | ~530 | [v-6f3](https://edgefirst.studio/public/validation/v-6f3/details?mode=charts) |
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| Nano | Apple M2 Max β CoreML Neural Engine (FP16) | 47.12% | -0.63 | 32.42% | 1.79 | 5.22 | 812.3 | ~1117 | [v-735](https://edgefirst.studio/public/validation/v-735/details?mode=charts) |
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| Nano | Apple M2 Max β CoreML Metal GPU (FP16) | 47.16% | -0.59 | 32.45% | 5.53 | 9.41 | 477.4 | ~542 | [v-9cb](https://edgefirst.studio/public/validation/v-9cb/details?mode=charts) |
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| Nano | Apple M2 Max β CoreML CPU (FP16) | 47.14% | -0.61 | 32.43% | 15.43 | 19.38 | 121.3 | ~130 | [v-9cc](https://edgefirst.studio/public/validation/v-9cc/details?mode=charts) |
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| Nano | NXP i.MX 8M Plus + VeriSilicon NPU (FRDM) | 46.53% | -1.22 | 31.89% | 57.78 | 110.65 | 14.6 | ~17 | [v-8bf](https://edgefirst.studio/public/validation/v-8bf/details?mode=charts) |
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| Nano | NXP i.MX 95 + eIQ Neutron NPU β throughput | 45.20% | -2.55 | 30.66% | 35.41 | 64.22 | 88.3 | ~113 | [v-6bf](https://edgefirst.studio/public/validation/v-6bf/details?mode=charts) |
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| Nano | NXP i.MX 95 + eIQ Neutron NPU (FRDM) β latency | 45.86% | -1.89 | 31.14% | 12.95 | 43.75 | 55.2 | ~56 | [v-8ad](https://edgefirst.studio/public/validation/v-8ad/details?mode=charts) |
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| Nano | NXP i.MX 95 + eIQ Neutron NPU (FRDM) β throughput | 45.86% | -1.89 | 31.14% | 20.97 | 59.88 | 75.1 | ~121 | [v-8ae](https://edgefirst.studio/public/validation/v-8ae/details?mode=charts) |
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| Nano | NXP i.MX 95 + eIQ Neutron NPU (Phytec) β throughput | 45.86% | -1.89 | 31.14% | 25.10 | 58.30 | 84.0 | ~159 | [v-897](https://edgefirst.studio/public/validation/v-897/details?mode=charts) |
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| Nano | NXP Ara240 β throughput | 44.99% | -2.76 | 30.11% | 8.41 | 24.97 | 195.0 | ~524 | [v-6bd](https://edgefirst.studio/public/validation/v-6bd/details?mode=charts) |
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| Nano | NXP Ara240 (FRDM) β latency | 44.99% | -2.76 | 30.11% | 8.65 | 30.85 | 193.9 | ~194 | [v-896](https://edgefirst.studio/public/validation/v-896/details?mode=charts) |
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| Nano | Raspberry Pi 5 + Hailo-8L NPU | 45.97% | -1.78 | 31.57% | 14.67 | 26.44 | 66.6 | ~136 | [v-8de](https://edgefirst.studio/public/validation/v-8de/details?mode=charts) |
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| Nano | NVIDIA Jetson Orin Nano (TensorRT FP16) | 47.77% | +0.02 | 32.93% | 8.54 | 23.99 | 271.2 | ~276 | [v-919](https://edgefirst.studio/public/validation/v-919/details?mode=charts) |
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| Small | ONNX FP32 (AWS Graviton Β· 48-core) | 57.29% | -0.04 | 41.23% | 65.96 | 74.73 | 58.7 | ~61 | [v-716](https://edgefirst.studio/public/validation/v-716/details?mode=charts) |
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| Small | ONNX FP32 (CUDA) | 57.33% | ref | 41.26% | 13.84 | 19.50 | 223.1 | ~289 | [v-6f4](https://edgefirst.studio/public/validation/v-6f4/details?mode=charts) |
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| Small | ONNX FP16 (CUDA) | 57.33% | +0.00 | 41.22% | 9.68 | 15.26 | 317.7 | ~413 | [v-6f5](https://edgefirst.studio/public/validation/v-6f5/details?mode=charts) |
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| Small | Apple M2 Max β CoreML Neural Engine (FP16) | 56.72% | -0.61 | 40.68% | 4.31 | 7.85 | 394.1 | ~464 | [v-9ea](https://edgefirst.studio/public/validation/v-9ea/details?mode=charts) |
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| Small | Apple M2 Max β CoreML Metal GPU (FP16) | 56.75% | -0.58 | 40.76% | 13.81 | 17.34 | 205.1 | ~217 | [v-9eb](https://edgefirst.studio/public/validation/v-9eb/details?mode=charts) |
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| Small | Apple M2 Max β CoreML CPU (FP16) | 56.72% | -0.61 | 40.71% | 29.96 | 34.04 | 64.2 | ~67 | [v-9ec](https://edgefirst.studio/public/validation/v-9ec/details?mode=charts) |
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| Small | NXP i.MX 8M Plus + VeriSilicon NPU (FRDM) | 56.87% | -0.46 | 40.69% | 109.41 | 161.03 | 8.3 | ~9 | [v-939](https://edgefirst.studio/public/validation/v-939/details?mode=charts) |
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| Small | NXP i.MX 95 + eIQ Neutron NPU β throughput | 55.87% | -1.46 | 39.82% | 123.47 | 148.11 | 31.9 | ~32 | [v-6c3](https://edgefirst.studio/public/validation/v-6c3/details?mode=charts) |
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| Small | NXP i.MX 95 + eIQ Neutron NPU (FRDM) β latency | 56.67% | -0.66 | 40.36% | 33.73 | 67.63 | 27.3 | ~30 | [v-8fa](https://edgefirst.studio/public/validation/v-8fa/details?mode=charts) |
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| Small | NXP i.MX 95 + eIQ Neutron NPU (FRDM) β throughput | 56.67% | -0.66 | 40.36% | 124.58 | 159.61 | 31.2 | ~32 | [v-8fb](https://edgefirst.studio/public/validation/v-8fb/details?mode=charts) |
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| Small | NXP i.MX 95 + eIQ Neutron NPU (Phytec) β throughput | 56.67% | -0.66 | 40.36% | 121.68 | 154.45 | 32.0 | ~33 | [v-8f0](https://edgefirst.studio/public/validation/v-8f0/details?mode=charts) |
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| Small | NXP Ara240 β throughput | 54.54% | -2.79 | 37.67% | 13.51 | 26.74 | 96.5 | ~592 | [v-6be](https://edgefirst.studio/public/validation/v-6be/details?mode=charts) |
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| Small | NXP Ara240 (FRDM) β latency | 54.54% | -2.79 | 37.67% | 13.49 | 26.57 | 96.4 | ~96 | [v-8e3](https://edgefirst.studio/public/validation/v-8e3/details?mode=charts) |
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| Small | Raspberry Pi 5 + Hailo-8L NPU | 56.13% | -1.20 | 40.02% | 29.36 | 43.90 | 32.1 | ~68 | [v-8eb](https://edgefirst.studio/public/validation/v-8eb/details?mode=charts) |
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| Small | NVIDIA Jetson Orin Nano (TensorRT FP16) | 57.32% | -0.01 | 41.24% | 22.04 | 34.77 | 174.6 | ~182 | [v-921](https://edgefirst.studio/public/validation/v-921/details?mode=charts) |
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| 138 |
+
| Medium | ONNX FP32 (AWS Graviton Β· 48-core) | 63.30% | +0.01 | 47.00% | 154.67 | 163.39 | 25.3 | ~26 | [v-717](https://edgefirst.studio/public/validation/v-717/details?mode=charts) |
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| 139 |
+
| Medium | ONNX FP32 (CUDA) | 63.29% | ref | 46.99% | 33.90 | 40.43 | 97.0 | ~118 | [v-6f6](https://edgefirst.studio/public/validation/v-6f6/details?mode=charts) |
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| 140 |
+
| Medium | ONNX FP16 (CUDA) | 63.27% | -0.02 | 46.93% | 20.12 | 26.31 | 166.6 | ~199 | [v-6f7](https://edgefirst.studio/public/validation/v-6f7/details?mode=charts) |
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| 141 |
+
| Medium | Apple M2 Max β CoreML Neural Engine (FP16) | 62.78% | -0.51 | 46.53% | 11.53 | 15.16 | 162.2 | ~173 | [v-75b](https://edgefirst.studio/public/validation/v-75b/details?mode=charts) |
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| 142 |
+
| Medium | Apple M2 Max β CoreML Metal GPU (FP16) | 62.80% | -0.49 | 46.52% | 33.27 | 37.50 | 87.8 | ~90 | [v-765](https://edgefirst.studio/public/validation/v-765/details?mode=charts) |
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| 143 |
+
| Medium | Apple M2 Max β CoreML CPU (FP16) | 62.75% | -0.54 | 46.46% | 56.58 | 60.68 | 34.6 | ~35 | [v-9dc](https://edgefirst.studio/public/validation/v-9dc/details?mode=charts) |
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| 144 |
+
| Medium | NXP i.MX 8M Plus + VeriSilicon NPU (FRDM) | 62.79% | -0.50 | 46.34% | 206.67 | 258.59 | 4.6 | ~5 | [v-97b](https://edgefirst.studio/public/validation/v-97b/details?mode=charts) |
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| 145 |
+
| Medium | NXP i.MX 95 + eIQ Neutron NPU β throughput | 61.95% | -1.34 | 45.73% | 301.77 | 325.55 | 13.2 | ~13 | [v-75f](https://edgefirst.studio/public/validation/v-75f/details?mode=charts) |
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| 146 |
+
| Medium | NXP i.MX 95 + eIQ Neutron NPU (FRDM) β latency | 62.77% | -0.52 | 46.30% | 78.06 | 110.95 | 12.3 | ~13 | [v-96b](https://edgefirst.studio/public/validation/v-96b/details?mode=charts) |
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| 147 |
+
| Medium | NXP i.MX 95 + eIQ Neutron NPU (FRDM) β throughput | 62.77% | -0.52 | 46.30% | 301.76 | 335.74 | 13.1 | ~13 | [v-96c](https://edgefirst.studio/public/validation/v-96c/details?mode=charts) |
|
| 148 |
+
| Medium | NXP i.MX 95 + eIQ Neutron NPU (Phytec) β throughput | 62.77% | -0.52 | 46.30% | 297.44 | 329.30 | 13.2 | ~13 | [v-94b](https://edgefirst.studio/public/validation/v-94b/details?mode=charts) |
|
| 149 |
+
| Medium | NXP Ara240 β throughput | 60.70% | -2.59 | 43.54% | 24.48 | 41.38 | 47.1 | ~327 | [v-796](https://edgefirst.studio/public/validation/v-796/details?mode=charts) |
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| 150 |
+
| Medium | NXP Ara240 (FRDM) β latency | 60.70% | -2.59 | 43.54% | 24.34 | 37.15 | 47.0 | ~47 | [v-907](https://edgefirst.studio/public/validation/v-907/details?mode=charts) |
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| 151 |
+
| Medium | Raspberry Pi 5 + Hailo-8L NPU | 62.40% | -0.89 | 46.17% | 57.38 | 72.71 | 16.2 | ~35 | [v-906](https://edgefirst.studio/public/validation/v-906/details?mode=charts) |
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| 152 |
+
| Medium | NVIDIA Jetson Orin Nano (TensorRT FP16) | 63.31% | +0.02 | 46.96% | 44.49 | 56.80 | 88.2 | ~90 | [v-92a](https://edgefirst.studio/public/validation/v-92a/details?mode=charts) |
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| 163 |
2. **EdgeFirst Validator** consumes the predictions and trace, computes `pycocotools` accuracy metrics and per-stage timing summaries, and publishes the results to the Studio validation session.
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| 164 |
3. **EdgeFirst HAL** ([open source](https://github.com/EdgeFirstAI/hal)) provides the hardware-accelerated preprocessing and post-decoding primitives used at both validation and deployment time, so the timings measured here reflect the same accelerated paths a production runtime would take.
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+
Inference latency is reported as the on-accelerator inference time. End-to-end latency is the sequential per-image latency across the compute pipeline β preprocessing, inference, and postprocessing; image acquisition (file or camera load and JPEG decode) overlaps these stages and is excluded from this figure.
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+
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| 168 |
+
Two throughput figures are reported. **Realized FPS** is the *measured* steady-state rate at which final results are emitted, computed from the Perfetto trace as `(N-1) / (t_last - t_first)` over the warmup-trimmed steady-state region; it is the true, priority number and generally exceeds `1000 / end-to-end` because the runtime overlaps stages across frames. **Theoretical FPS** is the per-stage accelerator ceiling (`min_s p_s / t_s` β the slowest stage's sustained rate), i.e. the throughput if the accelerator were the *only* bottleneck. It is a possibly-achievable ceiling, not a measured result: reaching it depends on the deployment pipeline. A validation run decodes a JPEG per image and evaluates at a `0.001` confidence threshold (to capture every detection for mAP), both of which load the host and postprocess stages; a production camera pipeline (no JPEG decode) at a deployment threshold of `0.25β0.75` (far fewer candidate boxes through NMS) moves realized throughput toward the theoretical ceiling.
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See [EdgeFirst Studio](https://edgefirst.studio) for the full validation pipeline.
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| 176 |
Artifacts are organized by deployment target. Each model file embeds the EdgeFirst `edgefirst.json` metadata (training session, dataset version, calibration artifact, converter chain) so a single file is sufficient for deployment β no sidecar configuration required.
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| 177 |
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| 178 |
+
Browse and download every artifact from the **[repository file tree](https://huggingface.co/EdgeFirst/yolov5-det/tree/main)**. Files are organized into per-target folders and follow the naming convention `yolov5{size}-det-{precision}[-smart]{extension}`:
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| 179 |
+
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| 180 |
+
| Target | Folder | Format |
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| 181 |
+
|--------|--------|--------|
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| 182 |
+
| ONNX FP32 | `onnx/` | `.onnx` |
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| 183 |
+
| TFLite INT8 | `tflite/` | `.tflite` |
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| 184 |
+
| NXP i.MX 95 (eIQ Neutron) | `imx95/` | `.imx95.tflite` |
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| 185 |
+
| NXP Ara240 | `ara240/` | `.dvm` |
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| 186 |
+
| RPi5 + Hailo-8L (13 TOPS) | `hailo/` | `.hailo8l.hef` |
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| 187 |
+
| NVIDIA Jetson (TensorRT) | `jetson/` | `.engine` |
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| 188 |
+
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| 189 |
+
Each file embeds its `edgefirst.json` metadata (training session, dataset version, calibration artifact, converter chain), so a single download is sufficient for deployment β no sidecar configuration required.
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| 191 |
---
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| 192 |
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| 208 |
```
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| 210 |
[EdgeFirst HAL](https://github.com/EdgeFirstAI/hal) β Hardware abstraction layer with accelerated inference delegates.
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| 211 |
---
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| 212 |
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| 213 |
## Traceability
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| 259 |
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| 260 |
1. **ONNX export** β standard Ultralytics export with `simplify=True`
|
| 261 |
2. **TF-wrapped ONNX** β box coordinates normalized to `[0, 1]` inside DFL decode
|
| 262 |
+
3. **Split decoder** β boxes and scores split into separate output tensors so each receives an independent INT8 quantization scale
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| 263 |
4. **Smart calibration** β calibration samples selected via greedy coverage maximization; the artifact is content-addressed by parameter hash and cached in Studio for deterministic reuse
|
| 264 |
5. **Full integer INT8** β `uint8` input, `int8` output, MLIR quantizer
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| 265 |
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| 284 |
## Limitations
|
| 285 |
|
| 286 |
- **COCO bias** β models trained on COCO (80 classes) inherit the dataset's biases (Western-centric scenes, particular object distributions, limited weather/lighting diversity).
|
| 287 |
+
- **Quantization loss** β integer quantization introduces accuracy loss relative to FP32: INT8 on the NXP i.MX 8M Plus / i.MX 95 Neutron and Hailo NPUs, and a mixed INT8/INT16 scheme on the NXP Ara240 (the box-regression path is promoted to INT16 for localization accuracy). The magnitude per platform is shown in the *Ξ vs FP32* column above.
|
| 288 |
+
- **Configurations under active investigation** β a subset of INT8 results measure below expectations and are marked β above; these are tracked for resolution, not accepted as final. The main cases are YOLO11 / YOLO26 on the NXP i.MX 8M Plus VeriSilicon NPU (the most constrained accelerator, where the newer architectures quantize poorly) and some NXP Ara240 segmentation runs. YOLO11 / YOLO26 on the NXP i.MX 95 eIQ Neutron NPU are not yet supported (a delegate limitation) and render without numbers. Each next card snapshot reflects any recovered accuracy.
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| 289 |
- **Input resolution** β all models expect 640Γ640 input; other resolutions require letterboxing.
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| 290 |
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| 291 |
---
|