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loras/verilog/README.md

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+# verilog
+**Rank**: 100 | **Loss**: 4.2692
+
+Verilog/SystemVerilog expert. RTL design, testbenches, synthesis, timing analysis, FPGA.

loras/verilog/adapter.pt

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+version https://git-lfs.github.com/spec/v1
+oid sha256:4869571615321e6bde6c695ba338d6e8fd81d2ea36a9dcfcb15f8b0f736eddc0
+size 697177068

loras/verilog/config.json

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+{"name": "verilog", "system": "Verilog/SystemVerilog expert. RTL design, testbenches, synthesis, timing analysis, FPGA.", "rank": 100, "alpha": 200, "scaling": 2.0, "best_loss": 4.269170761108398, "train_time": 69.85775971412659, "samples": 3000, "type": "coding", "gpu": "H100 (Modal)", "by": "NiftyOracle codesymb.com"}