Artem Plastinkin commited on
Commit ·
41edfa0
1
Parent(s): aeea7fa
Add model
Browse files
README.md
CHANGED
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@@ -15,8 +15,6 @@ tags:
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# DeepLabV3Plus-R50 (ONNX) – Renesas X5H
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> ⏳ **Model file not yet uploaded.** Benchmark results on this page were published ahead of the model weights — see **Provided Artifacts** below. Download/deployment steps will not work until the file is added to this repository.
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> **⚠️ Partial-model caveat.** The source checkpoint name ends in
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> `custom_seg_split_4_split_2` — this artifact is **one segment of a 4-way split network**, not
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> the full end-to-end DeepLabV3+ model. The latency below reflects only that segment; do not
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separate quantization step is required.
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```
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-
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│
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└─▶ MWMX Runtime ──▶ INT8 auto-cast ──▶ NPX6 NPU
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```
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| Artifact | Status | Notes |
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|----------|--------|-------|
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| **FP32 (ONNX)** |
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## Performance
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|---------|-----------|--------|---------------|------|
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| MWMX Runtime | INT8 (auto) | X5H · 1× NPU · 12 Cores · 850 MHz | 38.104 | Measured |
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### Accuracy (mIoU)
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TBD — not yet measured/published for this repo.
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1. **Renesas R-Car X5H board** with NPX6 NPU
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2. **Renesas MWMX Runtime**
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3. **Hugging Face CLI** to download the model
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## Download
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---
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# DeepLabV3Plus-R50 (ONNX) – Renesas X5H
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> **⚠️ Partial-model caveat.** The source checkpoint name ends in
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> `custom_seg_split_4_split_2` — this artifact is **one segment of a 4-way split network**, not
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> the full end-to-end DeepLabV3+ model. The latency below reflects only that segment; do not
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separate quantization step is required.
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```
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+
deeplabv3plus_r50_oss_sim_inf.onnx (FP32, split_2 segment)
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│
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└─▶ MWMX Runtime ──▶ INT8 auto-cast ──▶ NPX6 NPU
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```
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| Artifact | Status | Notes |
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|----------|--------|-------|
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| **FP32 (ONNX)** | ✅ Published | `fp32/deeplabv3plus_r50_oss_sim_inf.onnx` — segment `split_2` of 4; auto-cast to INT8 by the MWMX toolchain at compile time (see Deployment Flow above); no separate INT8 file is shipped |
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## Performance
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|---------|-----------|--------|---------------|------|
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| MWMX Runtime | INT8 (auto) | X5H · 1× NPU · 12 Cores · 850 MHz | 38.104 | Measured |
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> Reconfirmed: 1-core compile still fails as of the 2026-09-16 benchmark run.
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### Accuracy (mIoU)
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TBD — not yet measured/published for this repo.
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1. **Renesas R-Car X5H board** with NPX6 NPU
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2. **Renesas MWMX Runtime**
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+
3. **Hugging Face CLI** to download the model
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## Download
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```bash
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hf download Renesas/DeepLabV3Plus-R50-ONNX --repo-type=model --include "fp32/*"
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```
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---
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compile_config/l2_seg_48k_add_split_4_split_2.json
ADDED
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+
{
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"segments": [
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{
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"name": "Segment",
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"inputs": [
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"input"
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],
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"outputs": [
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"/backbone/maxpool/MaxPool_output_0"
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],
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+
"n_buffer": 2
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+
},
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+
{
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"name": "Segment_0",
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+
"inputs": [
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"/backbone/maxpool/MaxPool_output_0"
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],
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"outputs": [
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+
"/backbone/layer1/layer1.2/relu_2/Relu_output_0"
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],
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"n_buffer": 2
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},
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{
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"name": "Segment_layer2.{0,1,2,3}",
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"inputs": [
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"/backbone/layer1/layer1.2/relu_2/Relu_output_0"
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],
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"outputs": [
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+
"/backbone/layer2/layer2.3/relu_2/Relu_output_0"
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],
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"n_buffer": 2
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},
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{
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"name": "Segment_layer3.{0,1,2}",
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"inputs": [
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"/backbone/layer2/layer2.3/relu_2/Relu_output_0"
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],
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"outputs": [
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"/backbone/layer3/layer3.2/relu_2/Relu_output_0"
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],
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"n_buffer": 2
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},
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{
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"name": "Segment_layer3.{3,4,5}",
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"inputs": [
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"/backbone/layer3/layer3.2/relu_2/Relu_output_0"
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],
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"outputs": [
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+
"/backbone/layer3/layer3.5/relu_2/Relu_output_0"
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],
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"n_buffer": 2
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+
},
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+
{
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"name": "Segment_layer4.0",
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+
"inputs": [
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+
"/backbone/layer3/layer3.5/relu_2/Relu_output_0"
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+
],
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+
"outputs": [
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+
"/backbone/layer4/layer4.0/relu_2/Relu_output_0"
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],
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"n_buffer": 2
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+
},
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+
{
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"name": "Segment_aspp_modules.1",
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"inputs": [
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+
"/backbone/layer4/layer4.2/relu_2/Relu_output_0"
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],
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"outputs": [
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+
"/aspp_modules/aspp_modules.1/depthwise_conv/activate/Relu_output_0"
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],
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+
"n_buffer": 1
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},
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+
{
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"name": "Segment_aspp_modules.2",
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"inputs": [
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"/backbone/layer4/layer4.2/relu_2/Relu_output_0"
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],
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"outputs": [
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+
"/aspp_modules/aspp_modules.2/depthwise_conv/activate/Relu_output_0"
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],
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"n_buffer": 1
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},
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+
{
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"name": "Segment_bottleneck_0",
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"inputs": [
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"/Concat_1_output_0_2",
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"/bottleneck/conv/Conv_output_0_1"
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],
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+
"outputs": [
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+
"/bottleneck/activate/Relu_output_0"
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+
],
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"n_buffer": 1
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+
},
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+
{
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"name": "Segment_bottleneck_1",
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"inputs": [
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"/Concat_1_output_0_1"
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],
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"outputs": [
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+
"/bottleneck/conv/Conv_output_0_1"
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],
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"n_buffer": 1
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+
},
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{
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"name": "Segment_output",
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"inputs": [
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"/Concat_3_output_0"
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],
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"outputs": [
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"/conv_seg/Conv_output_0"
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],
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"n_buffer": 2
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+
},
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+
{
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"name": "seg_11",
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"inputs": [
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+
"/backbone/layer1/layer1.2/relu_2/Relu_output_0"
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+
],
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+
"outputs": [
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+
"/c1_bottleneck/activate/Relu_output_0"
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+
],
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+
"n_buffer": 1
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+
},
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+
{
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+
"name": "seg_12",
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+
"inputs": [
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+
"/backbone/layer4/layer4.0/relu_2/Relu_output_0"
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+
],
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| 129 |
+
"outputs": [
|
| 130 |
+
"/backbone/layer4/layer4.2/relu_2/Relu_output_0"
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| 131 |
+
],
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| 132 |
+
"n_buffer": 1
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| 133 |
+
},
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| 134 |
+
{
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| 135 |
+
"name": "seg_14",
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| 136 |
+
"inputs": [
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+
"/image_pool/image_pool.0/GlobalAveragePool_output_0"
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| 138 |
+
],
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| 139 |
+
"outputs": [
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+
"/image_pool/image_pool.1/activate/Relu_output_0"
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+
],
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+
"n_buffer": 1
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+
},
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+
{
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+
"name": "seg_16",
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+
"inputs": [
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+
"/backbone/layer4/layer4.2/relu_2/Relu_output_0"
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+
],
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| 149 |
+
"outputs": [
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+
"/aspp_modules/aspp_modules.0/activate/Relu_output_0"
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+
],
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+
"n_buffer": 1
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+
},
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+
{
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+
"name": "seg_17",
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+
"inputs": [
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+
"/aspp_modules/aspp_modules.1/depthwise_conv/activate/Relu_output_0"
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+
],
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+
"outputs": [
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+
"/aspp_modules/aspp_modules.1/pointwise_conv/activate/Relu_output_0"
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+
],
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+
"n_buffer": 1
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+
},
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+
{
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+
"name": "seg_19",
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+
"inputs": [
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+
"/aspp_modules/aspp_modules.2/depthwise_conv/activate/Relu_output_0"
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+
],
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+
"outputs": [
|
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+
"/aspp_modules/aspp_modules.2/pointwise_conv/activate/Relu_output_0"
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+
],
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+
"n_buffer": 2
|
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+
},
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+
{
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+
"name": "seg_18",
|
| 176 |
+
"inputs": [
|
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+
"/aspp_modules/aspp_modules.3/depthwise_conv/activate/Relu_output_0"
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| 178 |
+
],
|
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+
"outputs": [
|
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+
"/aspp_modules/aspp_modules.3/pointwise_conv/activate/Relu_output_0"
|
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+
],
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+
"n_buffer": 2
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+
},
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+
{
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+
"name": "Segment_27",
|
| 186 |
+
"inputs": [
|
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+
"/backbone/layer4/layer4.2/relu_2/Relu_output_0_slice_1"
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+
],
|
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+
"outputs": [
|
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+
"/aspp_modules/aspp_modules.3/depthwise_conv/activate/Relu_1_out"
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+
],
|
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+
"n_buffer": 1
|
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+
},
|
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+
{
|
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+
"name": "Segment_29",
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+
"inputs": [
|
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+
"/backbone/layer4/layer4.2/relu_2/Relu_output_0_slice_2"
|
| 198 |
+
],
|
| 199 |
+
"outputs": [
|
| 200 |
+
"/aspp_modules/aspp_modules.3/depthwise_conv/activate/Relu_2_out"
|
| 201 |
+
],
|
| 202 |
+
"n_buffer": 1
|
| 203 |
+
},
|
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+
{
|
| 205 |
+
"name": "Segment_31",
|
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+
"inputs": [
|
| 207 |
+
"/backbone/layer4/layer4.2/relu_2/Relu_output_0_slice_3"
|
| 208 |
+
],
|
| 209 |
+
"outputs": [
|
| 210 |
+
"/aspp_modules/aspp_modules.3/depthwise_conv/activate/Relu_3_out"
|
| 211 |
+
],
|
| 212 |
+
"n_buffer": 1
|
| 213 |
+
},
|
| 214 |
+
{
|
| 215 |
+
"name": "Segment_33",
|
| 216 |
+
"inputs": [
|
| 217 |
+
"/backbone/layer4/layer4.2/relu_2/Relu_output_0_slice_4"
|
| 218 |
+
],
|
| 219 |
+
"outputs": [
|
| 220 |
+
"/aspp_modules/aspp_modules.3/depthwise_conv/activate/Relu_4_out"
|
| 221 |
+
],
|
| 222 |
+
"n_buffer": 1
|
| 223 |
+
}
|
| 224 |
+
],
|
| 225 |
+
"tiling_info": {
|
| 226 |
+
"/Resize_1_output_0": {
|
| 227 |
+
"l1_tile_shape" : [1,16,64,128]
|
| 228 |
+
},
|
| 229 |
+
"/Resize_2_output_0": {
|
| 230 |
+
"l1_tile_shape" : [1,32,172,19]
|
| 231 |
+
}
|
| 232 |
+
}
|
| 233 |
+
}
|
fp32/.metadata.yaml
ADDED
|
@@ -0,0 +1,5 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
variant:
|
| 2 |
+
id: onnx_fp32
|
| 3 |
+
format: onnx
|
| 4 |
+
precision: fp32
|
| 5 |
+
method: onnx_export # exported from the OpenMMLab checkpoint, no quantization
|
fp32/deeplabv3plus_r50_oss_sim_inf.onnx
ADDED
|
@@ -0,0 +1,3 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
version https://git-lfs.github.com/spec/v1
|
| 2 |
+
oid sha256:bc33270e904d85a8ddcd85d8c4603f577f68255d272a1b8635a0e783c4499f81
|
| 3 |
+
size 165154945
|
int8/benchmarks/x5h_mwmx_npu_apm80_12core.yaml
CHANGED
|
@@ -42,3 +42,46 @@ memory:
|
|
| 42 |
|
| 43 |
power:
|
| 44 |
avg_w: null
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 42 |
|
| 43 |
power:
|
| 44 |
avg_w: null
|
| 45 |
+
|
| 46 |
+
# Exact commands verified against the NNAC "Getting Started" chapter. Rendered
|
| 47 |
+
# by the AI-Dashboard in place of the generic placeholder flow — see
|
| 48 |
+
# downloadRunHTML() / parse_reproduce() in AI-Dashboard/app.js.
|
| 49 |
+
# CAVEAT: this artifact is segment "split_2" of a 4-way split network (see
|
| 50 |
+
# README) — these steps reproduce only this segment's latency, not an
|
| 51 |
+
# end-to-end DeepLabV3+ result. The 1-AI-core config also fails to compile
|
| 52 |
+
# for this artifact, so no 1-core reproduce block exists.
|
| 53 |
+
reproduce:
|
| 54 |
+
steps:
|
| 55 |
+
- title: Download the ONNX model and compile config
|
| 56 |
+
command: hf download Renesas/DeepLabV3Plus-R50-ONNX --repo-type=model --include "fp32/*" --include "compile_config/*"
|
| 57 |
+
- title: Configure the network for the 12-core build (required — this model has no working 1-core config)
|
| 58 |
+
command: |
|
| 59 |
+
cat >> ${WORKDIR}/nnac_config/config.yaml << 'EOF'
|
| 60 |
+
network_configuration:
|
| 61 |
+
deeplabv3plus_r50_oss_sim_inf:
|
| 62 |
+
optimization_options:
|
| 63 |
+
- -segmentation_json ./compile_config/l2_seg_48k_add_split_4_split_2.json
|
| 64 |
+
- -enable_dma_fusion
|
| 65 |
+
- -enable_stu_multi_channel
|
| 66 |
+
- -stu_multi_channel_config 0x15212420
|
| 67 |
+
- -stu_weight
|
| 68 |
+
- -distributed_coef_stu
|
| 69 |
+
EOF
|
| 70 |
+
# If config.yaml already has a network_configuration: key (e.g. from a
|
| 71 |
+
# previous model), merge this block into it instead of appending a duplicate key.
|
| 72 |
+
- title: Compile with the NNAC toolchain (INT8 auto-cast from the FP32 graph)
|
| 73 |
+
command: |
|
| 74 |
+
python3 nnac_frontend/legalize.py -d binary/nnx ./fp32/deeplabv3plus_r50_oss_sim_inf.onnx
|
| 75 |
+
- title: Set up the R-Car X5H board
|
| 76 |
+
command: Configure the board per the AI Compiler (NNAC) "Getting Started" guide, section 3.4 (host TFTP/NFS setup, bootloader flashing, U-Boot, Linux boot, login) -- exact steps depend on your board/network setup.
|
| 77 |
+
- title: Copy the compiled artifact to the board
|
| 78 |
+
command: Copy ${WORKDIR}/binary/nnx to the board -- method may vary (NFS mount, scp, USB, etc.).
|
| 79 |
+
- title: Run on R-Car X5H (single NPU cluster, 12 AI cores)
|
| 80 |
+
command: |
|
| 81 |
+
cd binary
|
| 82 |
+
./host_app ./arc_prog_npus ./nnx/deeplabv3plus_r50_oss_sim_inf
|
| 83 |
+
notes: >-
|
| 84 |
+
hash[n] = 0x...(OK) means the run's output matches the reference hash in
|
| 85 |
+
hash.txt; latency is the NPX execution time reported in cycles and ms.
|
| 86 |
+
This is one segment (split_2 of 4) of the full segmentation pipeline —
|
| 87 |
+
not whole-model latency.
|