VBoussot commited on
Commit
41d7603
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1 Parent(s): e340746

Drop the 2077-line UNetpp.yml (replaced by block-level UNetPlusPlus.yml)

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  1. Finetune/UNetpp.yml +0 -2077
Finetune/UNetpp.yml DELETED
@@ -1,2077 +0,0 @@
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- # Declarative KonfAI graph reproducing the ImpactSynth app model:
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- # smp.UnetPlusPlus(encoder_name='resnet34', encoder_weights=None, in_channels=5,
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- # classes=1, activation=None) + Tanh head.
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- # Built ONLY from curated model-builder registry types, in smp forward-execution order
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- # so execution-order weight transfer pairs all 117 weighted leaves one-to-one.
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- # Generated by generate_unetpp_yaml.py -- do not edit by hand.
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- name: UNetpp
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- network:
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- in_channels: 5
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- dim: 2
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- modules:
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- - name: enc_conv1
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- type: Conv
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- out_branch:
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- - e_c1
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- args:
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- dim: 2
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- in_channels: 5
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- out_channels: 64
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- kernel_size: 7
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- stride: 2
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- padding: 3
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- bias: false
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- - name: enc_bn1
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- type: BatchNorm
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- in_branch:
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- - e_c1
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- out_branch:
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- - e_c1
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- args:
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- dim: 2
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- num_features: 64
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- - name: enc_relu
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- type: ReLU
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- in_branch:
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- - e_c1
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- out_branch:
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- - e_c1
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- args: {}
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- - name: enc_maxpool
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- type: MaxPool
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- in_branch:
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- - e_c1
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- out_branch:
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- - mp
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- args:
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- dim: 2
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- kernel_size: 3
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- stride: 2
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- padding: 1
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- - name: l1_b0_conv1
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- type: Conv
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- in_branch:
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- - mp
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- out_branch:
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- - l1_b0_m
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- args:
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- dim: 2
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- in_channels: 64
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- out_channels: 64
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- kernel_size: 3
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- stride: 1
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- padding: 1
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- bias: false
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- - name: l1_b0_bn1
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- type: BatchNorm
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- in_branch:
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- - l1_b0_m
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- out_branch:
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- - l1_b0_m
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- args:
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- dim: 2
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- num_features: 64
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- - name: l1_b0_relu1
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- type: ReLU
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- in_branch:
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- - l1_b0_m
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- out_branch:
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- - l1_b0_m
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- args: {}
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- - name: l1_b0_conv2
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- type: Conv
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- in_branch:
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- - l1_b0_m
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- out_branch:
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- - l1_b0_m
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- args:
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- dim: 2
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- in_channels: 64
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- out_channels: 64
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- kernel_size: 3
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- stride: 1
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- padding: 1
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- bias: false
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- - name: l1_b0_bn2
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- type: BatchNorm
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- in_branch:
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- - l1_b0_m
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- out_branch:
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- - l1_b0_m
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- args:
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- dim: 2
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- num_features: 64
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- - name: l1_b0_add
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- type: Add
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- in_branch:
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- - l1_b0_m
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- - mp
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- out_branch:
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- - l1_b0_m
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- args: {}
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- - name: l1_b0_relu2
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- type: ReLU
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- in_branch:
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- - l1_b0_m
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- out_branch:
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- - l1_0
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- args: {}
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- - name: l1_b1_conv1
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- type: Conv
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- in_branch:
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- - l1_0
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- out_branch:
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- - l1_b1_m
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- args:
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- dim: 2
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- in_channels: 64
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- out_channels: 64
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- kernel_size: 3
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- stride: 1
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- padding: 1
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- bias: false
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- - name: l1_b1_bn1
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- type: BatchNorm
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- in_branch:
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- - l1_b1_m
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- out_branch:
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- - l1_b1_m
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- args:
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- dim: 2
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- num_features: 64
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- - name: l1_b1_relu1
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- type: ReLU
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- in_branch:
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- - l1_b1_m
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- out_branch:
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- - l1_b1_m
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- args: {}
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- - name: l1_b1_conv2
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- type: Conv
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- in_branch:
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- - l1_b1_m
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- out_branch:
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- - l1_b1_m
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- args:
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- dim: 2
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- in_channels: 64
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- out_channels: 64
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- kernel_size: 3
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- stride: 1
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- padding: 1
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- bias: false
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- - name: l1_b1_bn2
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- type: BatchNorm
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- in_branch:
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- - l1_b1_m
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- out_branch:
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- - l1_b1_m
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- args:
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- dim: 2
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- num_features: 64
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- - name: l1_b1_add
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- type: Add
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- in_branch:
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- - l1_b1_m
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- - l1_0
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- out_branch:
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- - l1_b1_m
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- args: {}
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- - name: l1_b1_relu2
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- type: ReLU
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- in_branch:
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- - l1_b1_m
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- out_branch:
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- - l1_1
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- args: {}
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- - name: l1_b2_conv1
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- type: Conv
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- in_branch:
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- - l1_1
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- out_branch:
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- - l1_b2_m
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- args:
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- dim: 2
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- in_channels: 64
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- out_channels: 64
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- kernel_size: 3
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- stride: 1
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- padding: 1
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- bias: false
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- - name: l1_b2_bn1
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- type: BatchNorm
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- in_branch:
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- - l1_b2_m
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- out_branch:
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- - l1_b2_m
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- args:
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- dim: 2
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- num_features: 64
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- - name: l1_b2_relu1
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- type: ReLU
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- in_branch:
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- - l1_b2_m
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- out_branch:
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- - l1_b2_m
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- args: {}
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- - name: l1_b2_conv2
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- type: Conv
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- in_branch:
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- - l1_b2_m
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- out_branch:
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- - l1_b2_m
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- args:
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- dim: 2
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- in_channels: 64
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- out_channels: 64
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- kernel_size: 3
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- stride: 1
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- padding: 1
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- bias: false
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- - name: l1_b2_bn2
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- type: BatchNorm
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- in_branch:
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- - l1_b2_m
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- out_branch:
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- - l1_b2_m
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- args:
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- dim: 2
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- num_features: 64
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- - name: l1_b2_add
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- type: Add
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- in_branch:
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- - l1_b2_m
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- - l1_1
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- out_branch:
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- - l1_b2_m
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- args: {}
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- - name: l1_b2_relu2
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- type: ReLU
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- in_branch:
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- - l1_b2_m
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- out_branch:
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- - e_l1
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- args: {}
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- - name: l2_b0_conv1
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- type: Conv
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- in_branch:
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- - e_l1
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- out_branch:
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- - l2_b0_m
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- args:
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- dim: 2
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- in_channels: 64
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- out_channels: 128
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- kernel_size: 3
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- stride: 2
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- padding: 1
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- bias: false
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- - name: l2_b0_bn1
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- type: BatchNorm
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- in_branch:
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- - l2_b0_m
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- out_branch:
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- - l2_b0_m
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- args:
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- dim: 2
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- num_features: 128
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- - name: l2_b0_relu1
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- type: ReLU
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- in_branch:
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- - l2_b0_m
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- out_branch:
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- - l2_b0_m
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- args: {}
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- - name: l2_b0_conv2
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- type: Conv
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- in_branch:
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- - l2_b0_m
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- out_branch:
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- - l2_b0_m
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- args:
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- dim: 2
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- in_channels: 128
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- out_channels: 128
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- kernel_size: 3
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- stride: 1
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- padding: 1
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- bias: false
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- - name: l2_b0_bn2
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- type: BatchNorm
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- in_branch:
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- - l2_b0_m
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- out_branch:
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- - l2_b0_m
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- args:
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- dim: 2
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- num_features: 128
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- - name: l2_b0_dsconv
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- type: Conv
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- in_branch:
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- - e_l1
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- out_branch:
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- - l2_b0_s
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- args:
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- dim: 2
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- in_channels: 64
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- out_channels: 128
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- kernel_size: 1
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- stride: 2
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- padding: 0
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- bias: false
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- - name: l2_b0_dsbn
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- type: BatchNorm
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- in_branch:
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- - l2_b0_s
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- out_branch:
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- - l2_b0_s
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- args:
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- dim: 2
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- num_features: 128
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- - name: l2_b0_add
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- type: Add
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- in_branch:
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- - l2_b0_m
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- - l2_b0_s
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- out_branch:
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- - l2_b0_m
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- args: {}
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- - name: l2_b0_relu2
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- type: ReLU
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- in_branch:
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- - l2_b0_m
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- out_branch:
344
- - l2_0
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- args: {}
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- - name: l2_b1_conv1
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- type: Conv
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- in_branch:
349
- - l2_0
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- out_branch:
351
- - l2_b1_m
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- args:
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- dim: 2
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- in_channels: 128
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- out_channels: 128
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- kernel_size: 3
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- stride: 1
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- padding: 1
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- bias: false
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- - name: l2_b1_bn1
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- type: BatchNorm
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- in_branch:
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- - l2_b1_m
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- out_branch:
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- - l2_b1_m
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- args:
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- dim: 2
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- num_features: 128
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- - name: l2_b1_relu1
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- type: ReLU
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- in_branch:
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- - l2_b1_m
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- out_branch:
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- - l2_b1_m
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- args: {}
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- - name: l2_b1_conv2
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- type: Conv
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- in_branch:
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- - l2_b1_m
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- out_branch:
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- - l2_b1_m
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- args:
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- dim: 2
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- in_channels: 128
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- out_channels: 128
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- kernel_size: 3
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- stride: 1
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- padding: 1
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- bias: false
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- - name: l2_b1_bn2
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- type: BatchNorm
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- in_branch:
393
- - l2_b1_m
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- out_branch:
395
- - l2_b1_m
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- args:
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- dim: 2
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- num_features: 128
399
- - name: l2_b1_add
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- type: Add
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- in_branch:
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- - l2_b1_m
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- - l2_0
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- out_branch:
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- - l2_b1_m
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- args: {}
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- - name: l2_b1_relu2
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- type: ReLU
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- in_branch:
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- - l2_b1_m
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- out_branch:
412
- - l2_1
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- args: {}
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- - name: l2_b2_conv1
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- type: Conv
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- in_branch:
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- - l2_1
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- out_branch:
419
- - l2_b2_m
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- args:
421
- dim: 2
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- in_channels: 128
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- out_channels: 128
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- kernel_size: 3
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- stride: 1
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- padding: 1
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- bias: false
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- - name: l2_b2_bn1
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- type: BatchNorm
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- in_branch:
431
- - l2_b2_m
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- out_branch:
433
- - l2_b2_m
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- args:
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- dim: 2
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- num_features: 128
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- - name: l2_b2_relu1
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- type: ReLU
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- in_branch:
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- - l2_b2_m
441
- out_branch:
442
- - l2_b2_m
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- args: {}
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- - name: l2_b2_conv2
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- type: Conv
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- in_branch:
447
- - l2_b2_m
448
- out_branch:
449
- - l2_b2_m
450
- args:
451
- dim: 2
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- in_channels: 128
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- out_channels: 128
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- kernel_size: 3
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- stride: 1
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- padding: 1
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- bias: false
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- - name: l2_b2_bn2
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- type: BatchNorm
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- in_branch:
461
- - l2_b2_m
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- out_branch:
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- - l2_b2_m
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- args:
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- dim: 2
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- num_features: 128
467
- - name: l2_b2_add
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- type: Add
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- in_branch:
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- - l2_b2_m
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- - l2_1
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- out_branch:
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- - l2_b2_m
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- args: {}
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- - name: l2_b2_relu2
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- type: ReLU
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- in_branch:
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- - l2_b2_m
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- out_branch:
480
- - l2_2
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- args: {}
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- - name: l2_b3_conv1
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- type: Conv
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- in_branch:
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- - l2_2
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- out_branch:
487
- - l2_b3_m
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- args:
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- dim: 2
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- in_channels: 128
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- out_channels: 128
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- kernel_size: 3
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- stride: 1
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- padding: 1
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- bias: false
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- - name: l2_b3_bn1
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- type: BatchNorm
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- in_branch:
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- - l2_b3_m
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- out_branch:
501
- - l2_b3_m
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- args:
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- dim: 2
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- num_features: 128
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- - name: l2_b3_relu1
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- type: ReLU
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- in_branch:
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- - l2_b3_m
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- out_branch:
510
- - l2_b3_m
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- args: {}
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- - name: l2_b3_conv2
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- type: Conv
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- in_branch:
515
- - l2_b3_m
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- out_branch:
517
- - l2_b3_m
518
- args:
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- dim: 2
520
- in_channels: 128
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- out_channels: 128
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- kernel_size: 3
523
- stride: 1
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- padding: 1
525
- bias: false
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- - name: l2_b3_bn2
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- type: BatchNorm
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- in_branch:
529
- - l2_b3_m
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- out_branch:
531
- - l2_b3_m
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- args:
533
- dim: 2
534
- num_features: 128
535
- - name: l2_b3_add
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- type: Add
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- in_branch:
538
- - l2_b3_m
539
- - l2_2
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- out_branch:
541
- - l2_b3_m
542
- args: {}
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- - name: l2_b3_relu2
544
- type: ReLU
545
- in_branch:
546
- - l2_b3_m
547
- out_branch:
548
- - e_l2
549
- args: {}
550
- - name: l3_b0_conv1
551
- type: Conv
552
- in_branch:
553
- - e_l2
554
- out_branch:
555
- - l3_b0_m
556
- args:
557
- dim: 2
558
- in_channels: 128
559
- out_channels: 256
560
- kernel_size: 3
561
- stride: 2
562
- padding: 1
563
- bias: false
564
- - name: l3_b0_bn1
565
- type: BatchNorm
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- in_branch:
567
- - l3_b0_m
568
- out_branch:
569
- - l3_b0_m
570
- args:
571
- dim: 2
572
- num_features: 256
573
- - name: l3_b0_relu1
574
- type: ReLU
575
- in_branch:
576
- - l3_b0_m
577
- out_branch:
578
- - l3_b0_m
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- args: {}
580
- - name: l3_b0_conv2
581
- type: Conv
582
- in_branch:
583
- - l3_b0_m
584
- out_branch:
585
- - l3_b0_m
586
- args:
587
- dim: 2
588
- in_channels: 256
589
- out_channels: 256
590
- kernel_size: 3
591
- stride: 1
592
- padding: 1
593
- bias: false
594
- - name: l3_b0_bn2
595
- type: BatchNorm
596
- in_branch:
597
- - l3_b0_m
598
- out_branch:
599
- - l3_b0_m
600
- args:
601
- dim: 2
602
- num_features: 256
603
- - name: l3_b0_dsconv
604
- type: Conv
605
- in_branch:
606
- - e_l2
607
- out_branch:
608
- - l3_b0_s
609
- args:
610
- dim: 2
611
- in_channels: 128
612
- out_channels: 256
613
- kernel_size: 1
614
- stride: 2
615
- padding: 0
616
- bias: false
617
- - name: l3_b0_dsbn
618
- type: BatchNorm
619
- in_branch:
620
- - l3_b0_s
621
- out_branch:
622
- - l3_b0_s
623
- args:
624
- dim: 2
625
- num_features: 256
626
- - name: l3_b0_add
627
- type: Add
628
- in_branch:
629
- - l3_b0_m
630
- - l3_b0_s
631
- out_branch:
632
- - l3_b0_m
633
- args: {}
634
- - name: l3_b0_relu2
635
- type: ReLU
636
- in_branch:
637
- - l3_b0_m
638
- out_branch:
639
- - l3_0
640
- args: {}
641
- - name: l3_b1_conv1
642
- type: Conv
643
- in_branch:
644
- - l3_0
645
- out_branch:
646
- - l3_b1_m
647
- args:
648
- dim: 2
649
- in_channels: 256
650
- out_channels: 256
651
- kernel_size: 3
652
- stride: 1
653
- padding: 1
654
- bias: false
655
- - name: l3_b1_bn1
656
- type: BatchNorm
657
- in_branch:
658
- - l3_b1_m
659
- out_branch:
660
- - l3_b1_m
661
- args:
662
- dim: 2
663
- num_features: 256
664
- - name: l3_b1_relu1
665
- type: ReLU
666
- in_branch:
667
- - l3_b1_m
668
- out_branch:
669
- - l3_b1_m
670
- args: {}
671
- - name: l3_b1_conv2
672
- type: Conv
673
- in_branch:
674
- - l3_b1_m
675
- out_branch:
676
- - l3_b1_m
677
- args:
678
- dim: 2
679
- in_channels: 256
680
- out_channels: 256
681
- kernel_size: 3
682
- stride: 1
683
- padding: 1
684
- bias: false
685
- - name: l3_b1_bn2
686
- type: BatchNorm
687
- in_branch:
688
- - l3_b1_m
689
- out_branch:
690
- - l3_b1_m
691
- args:
692
- dim: 2
693
- num_features: 256
694
- - name: l3_b1_add
695
- type: Add
696
- in_branch:
697
- - l3_b1_m
698
- - l3_0
699
- out_branch:
700
- - l3_b1_m
701
- args: {}
702
- - name: l3_b1_relu2
703
- type: ReLU
704
- in_branch:
705
- - l3_b1_m
706
- out_branch:
707
- - l3_1
708
- args: {}
709
- - name: l3_b2_conv1
710
- type: Conv
711
- in_branch:
712
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