File size: 1,659 Bytes
caddd62 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 | # Copyright (c) 2026 ETH Zurich and University of Bologna.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
#
# Authors:
# - Philippe Sauter <phsauter@iis.ee.ethz.ch>
#
# Verible lint rules configuration.
# Reference: https://chipsalliance.github.io/verible/verilog_lint.html
#
# Syntax:
# +rule-name enable rule
# -rule-name disable rule
# rule-name=p:v set parameter p to value v (enables rule implicitly)
###########################
# Arrays and Types
###########################
# Unpacked dimensions should be allowed to have explicit ordering given
-unpacked-dimensions-range-ordering
###########################
# Case statements
###########################
# Every case statement must have a default branch (unless unique/priority)
+case-missing-default
###########################
# Naming conventions
###########################
# Relax interface naming scheme since we use _if and _intf
-interface-name-style
###########################
# File structure
###########################
# One module definition per file (packages/interfaces may coexist)
-one-module-per-file
# Module name may not match the filename
# eg for files implementing various options and managed via bender
-module-filename
###########################
# Whitespace / Formatting
###########################
# No hard tabs — use spaces
+no-tabs
# No trailing whitespace
+no-trailing-spaces
# File must end with a newline (POSIX)
+posix-eof
# Maximum line length; 140 chars is a reasonable limit for HDL
line-length=length:140
# Allow line continuation
-forbid-line-continuations
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