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Below are the micro-instruction and sequence word formats. As I am still
studying their meanings, I will not provide a detailed explanation of each
field here. For comprehensive information, please refer to the foundational
documentation in uCodeDisasm[25] and lib-micro[27].
4746 45 44 43 32 31 24 23 22 18 17 12 11 6 5 0
+---+--+--+-------------+--------+--+-----+-------+-------+-------+
|CRC|m2|m1| opcode | imm0 |m0| imm1| dst | src1 | src0 |
+---+--+--+-------------+--------+--+-----+-------+-------+-------+
2 1 1 12 8 1 5 6 6 6
2928 27 25 2423 22 8 7 6 5 2 1 0
+---+-----+---+--------------------+---+-------+---+
|CRC|sync |up2| uaddr |up1| eflow |up0|
+---+-----+---+--------------------+---+-------+---+
2 3 2 15 2 4 2
The code appears relatively simple at first glance. It continuously loads
data from memory locations pointed to by RSI and RDI, compares them, and
increments the memory addresses in these registers while decrementing the
counter value in RCX.
Let's clarify the following abbreviations:
ZX (Zero eXtended): Indicates zero-extension of a value.
DSZ (Data Size): Specifies the size of a data operand.
ASZ (Address Size): Denotes the size of an address operand.
SC (Scale): Represents the scaling factor in addressing calculations.
And the terms TAKEN and NOTTAKEN serve as branch hints for the Microcode
Sequencer.
For example:
U3cc8: 1c0000231027 tmp1:= LDZX_DSZN_ASZ32_SC1(rdi, mode=0x08)
This is a load instruction. While uCodeDisasm displays it with DSZN, the
actual data size for this instruction is 32 bits. The opcode is 12 bits in
length, with the data size encoded in bits [7:6] as follows:
00: DSZ32
01: DSZ64
10: DSZ16
11: DSZ8
The instruction specifies both address and data sizes as 32-bit. This
initially caused confusion since the test CPU (Intel Pentium N4200,
Goldmont microarchitecture) is a 64-bit processor. I would expect the
microcode to operate in 64-bit mode by default. I considered this might be
a 32-bit version of the CMPS instruction. However, after thorough searching
of the MSROM, I was unable to locate any corresponding 64-bit CMPS
microcode routine.
Testing the 64-bit "REPE CMPSQ" instruction on an x86-64 Ubuntu system
confirmed that microcode routine U08b0 handles the 64-bit CMPS operation.
During my analysis, I observed that while most micro-instructions in the
MSROM use DSZ32/ASZ32, some explicitly specify ASZ64 and DSZ64. Also, the
opcode for CMPSD is "A7", while CMPSQ uses "REX.W + A7" - the same opcode
with a prefix modifier. This leads me to hypothesize that the 32-bit and
64-bit CMPS operations might share the same microcode routine, with the
REX.W prefix potentially generating a control signal that directs the
execution unit to perform either 32-bit or 64-bit comparisons as
appropriate.
It is noticeable that MOD1 (bit 44) is often set on DSZ32 and ASZ32
micro-instructions, whereas those specifying DSZ64 or ASZ64 usually do not
have MOD1 set, though exceptions exist, such as in the case of "U3d4a:
104900035924 tmp5:= MOVE_DSZ64(rsp, rsp)".
After some testing, the hypothesis seems to be correct. For example,
"SUB_DSZ32_DRR(TMP10, TMP1, TMP0) | MOD1" performs 64-bit comparisons
during "REPE CMPSQ" operations but switches to 32-bit comparisons for "REPE
CMPSD". In contrast, SUB_DSZ64_DRR(TMP10, TMP1, TMP0) maintains exclusively
64-bit comparisons, even when the upper layer operating system operates in
32-bit mode.
TMP0-TMP15 are 64-bit microarchitectural registers that can be used as
scratch registers within microcode routines. Unlike architectural registers
(such as RAX, RBX, etc.), which share a single RFLAGS register, each
microarchitectural register has its own dedicated set of arithmetic flags.
These flags are updated whenever the register is used as the destination of
an arithmetic micro-instruction.
For instance, consider the micro-operation at: "U3cce: 10050003ac31
SUB_DSZ32_DRR(TMP10, TMP1, TMP0) | MOD1". This instruction sets TMP10's Z
flag if TMP1 equals TMP0. The subsequent micro-operation: "U3cd0:
015f6410023a UJMPCC_DIRECT_TAKEN_CONDZ(tmp10, U0464)" then performs a
conditional jump based on TMP10's Z flag state.
This microcode routine is essentially what one would expect for a
comparison instruction within a loop, except that instead of using CMP, the
actual compare operation is performed by SUB, as is the case in the
OpenSPARC CPU. Yet, despite the brevity of this code segment, several
unresolved mysteries remain.
For instance, what is the purpose of SIGEVENT(0x0000003b)? Why would the
code send a signal immediately after checking the RCX register, before