Datasets:
Devilishcode
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hacking

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1.99k
08: 1 0x2078 0x7cf6
09: 1 0x263a 0x7cfe
10: 1 0x18c4 0x7cfa
11: 1 0x78d6 0x7d02
12: 1 0x2018 0x7c04
13: 1 0x5b94 0x7c14
14: 1 0x5ce2 0x7c88
15: 1 0x6908 0x7c6c
16: 1 0x3b52 0x7c4a
17: 1 0x4e76 0x7db8
18: 1 0x01ce 0x7ce6
19: 1 0x2ec8 0x7d6e
20: 1 0x6ff6 0x7d26
21: 1 0x13da 0x7d94
22: 1 0x667c 0x7cea
23: 1 0x0cd2 0x7d0a
24: 1 0x0e66 0x7d7a
25: 1 0x4c5a 0x7dd6
26: 1 0x24bc 0x7d12
27: 1 0x31a4 0x7d36
28: 1 0x758e 0x7df6
29: 0 0x0000 0x0000
30: 0 0x0000 0x0000
31: 0 0x0000 0x0000
Match/patch table is implemented as one of Microcode Sequencer
Arrays (array 3), with the following structure:
30 16 15 0
+------------------------+------------------------+-+
| dst | src |p|
+------------------------+------------------------+-+
15 15 1
p : Indicates whether the entry is active
src: 15-bit source address (calculated as uaddr/2) representing the hook
location
dst: 15-bit destination address (calculated as uaddr/2) for the jump
target
This component plays a critical role in the microcode update system. During
microcode execution, when the processor encounters an instruction at the
src address, the control flow is redirected to the corresponding dst
address, enabling runtime modification of the execution path. The table
contains 32 entries, with the first entry typically reserved/unused.
The MSRAM is completely filled up to 0x7df6 (as shown in slot 28), and the
whole space stops at 0x7dff in case I didn't mention that before. It
leaves no space to insert more microcode. At first, I assumed microcode
patches were incrementally applied with each update. To test this, I
disabled microcode updates in the Linux kernel and even removed the
microcode blob from coreboot. Surprisingly, the microcode RAM became even
more saturated, and one more match/patch register was occupied.
This means that if you are using stepping 9 (or an even earlier revision,
if one exists) this experiment may not be feasible. To free up space, I
attempted to erase certain match/patch registers, assuming that
security-related patches would have minimal impact. However, the system
became unstable. Shows these microcode patches are more serious than I
thought.
According to Coreboot doc, "When a CPU core comes out of reset, it uses
microcode from an internal ROM. This "default" microcode often contains
bugs, so it needs to be updated as soon as possible. For example, Core 2
CPUs can boot without microcode updates, but have stability problems. On
newer platforms, it is nearly impossible to boot without having updated the
microcode. On some platforms, an updated microcode is required in order to
enable Cache-As-RAM or to be able to successfully initialize the DRAM.
Plus, microcode needs to be loaded multiple times. Intel Document 504790
explains that this is because of so-called enhanced microcode updates,
which are large updates with errata workarounds for both core and uncore.
In order to correctly apply enhanced microcode updates, the MP-Init
algorithm must be decomposed into multiple initialization phases.
...
Beginning with 4th generation Intel Core processors, it is possible for
microcode to be updated before the CPU is taken out of reset. This is
accomplished by means of FIT, a data structure which contains pointers to
various firmware ingredients in the BIOS flash."
Microcode updates are not optional especially those FIT ones in BIOS,
because modern CPUs need them to even work right. To mess up a CPU with
heavy microcode patches, maybe the only way is to analysis it, find gaps
and squeeze code pieces in there like old-school infection virus.
For this project, it would be much easier to start with a CPU that is
stepping 10, there should be enough space to implant the backdoor
microcode. Below is the current match/patch status for stepping 10 under
microcode revision 0x28.
idx p src dst
00: 0 0x0000 0x0000
01: 1 0x4dc0 0x7c4c
02: 1 0x2078 0x7c0e
03: 1 0x682a 0x7c86
04: 1 0x1c3c 0x7c30
05: 1 0x6a10 0x7c44
06: 1 0x3c7a 0x7c22
07: 1 0x4f52 0x7cca