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platform/aiml/models/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/fs/cfskh2mdyfj22dss4y4cpndimbeaqmdvmfwc2kbeeopatr66npkt.py

@@ -0,0 +1,65 @@
+
+import triton
+import triton.language as tl
+
+from torch._inductor.runtime import triton_helpers, triton_heuristics
+from torch._inductor.runtime.triton_helpers import libdevice, math as tl_math
+from torch._inductor.runtime.hints import AutotuneHint, ReductionHint, TileHint, DeviceProperties
+triton_helpers.set_driver_to_gpu()
+
+@triton_heuristics.pointwise(
+    size_hints={'x': 4194304}, 
+    filename=__file__,
+    triton_meta={'signature': {'in_ptr0': '*bf16', 'in_ptr1': '*i64', 'in_ptr2': '*bf16', 'out_ptr0': '*bf16', 'xnumel': 'i32', 'XBLOCK': 'constexpr'}, 'device': DeviceProperties(type='cuda', index=0, multi_processor_count=132, cc=90, major=9, regs_per_multiprocessor=65536, max_threads_per_multi_processor=2048, warp_size=32), 'constants': {}, 'configs': [{(0,): [['tt.divisibility', 16]], (1,): [['tt.divisibility', 16]], (2,): [['tt.divisibility', 16]], (3,): [['tt.divisibility', 16]], (4,): [['tt.divisibility', 16]]}]},
+    inductor_meta={'grid_type': 'Grid1D', 'autotune_hints': set(), 'kernel_name': 'triton_poi_fused_cat_4', 'mutated_arg_names': [], 'optimize_mem': True, 'no_x_dim': False, 'num_load': 6, 'num_reduction': 0, 'backend_hash': 'F43D6982A315236AF8E29EA38FBEB3BFF1A29D8B91A2D6952242D4C92EF73270', 'are_deterministic_algorithms_enabled': False, 'assert_indirect_indexing': True, 'autotune_local_cache': True, 'autotune_pointwise': True, 'autotune_remote_cache': None, 'force_disable_caches': False, 'dynamic_scale_rblock': True, 'max_autotune': False, 'max_autotune_pointwise': False, 'min_split_scan_rblock': 256, 'spill_threshold': 16, 'store_cubin': False},
+    min_elem_per_thread=0
+)
+@triton.jit
+def triton_poi_fused_cat_4(in_ptr0, in_ptr1, in_ptr2, out_ptr0, xnumel, XBLOCK : tl.constexpr):
+    xoffset = tl.program_id(0) * XBLOCK
+    xindex = xoffset + tl.arange(0, XBLOCK)[:]
+    xmask = xindex < xnumel
+    x0 = (xindex % 128)
+    x1 = ((xindex // 128) % 4)
+    x2 = xindex // 512
+    x4 = xindex
+    tmp0 = x0
+    tmp1 = tl.full([1], 0, tl.int64)
+    tmp2 = tmp0 >= tmp1
+    tmp3 = tl.full([1], 64, tl.int64)
+    tmp4 = tmp0 < tmp3
+    tmp5 = tl.load(in_ptr0 + (3584 + 128*x1 + 4608*x2 + (x0)), xmask & tmp4, eviction_policy='evict_last', other=0.0).to(tl.float32)
+    tmp6 = tl.load(in_ptr1 + (x2), xmask & tmp4, eviction_policy='evict_last', other=0.0)
+    tmp7 = tl.full([XBLOCK], 131072, tl.int32)
+    tmp8 = tmp6 + tmp7
+    tmp9 = tmp6 < 0
+    tmp10 = tl.where(tmp9, tmp8, tmp6)
+    tl.device_assert(((0 <= tl.broadcast_to(tmp10, [XBLOCK])) & (tl.broadcast_to(tmp10, [XBLOCK]) < 131072)) | ~(xmask & tmp4), "index out of bounds: 0 <= tl.broadcast_to(tmp10, [XBLOCK]) < 131072")
+    tmp12 = tl.load(in_ptr2 + (128*tmp10 + (x0)), xmask & tmp4, eviction_policy='evict_last', other=0.0).to(tl.float32)
+    tmp13 = tmp5 * tmp12
+    tmp14 = tl.load(in_ptr0 + (3648 + 128*x1 + 4608*x2 + (x0)), xmask & tmp4, eviction_policy='evict_last', other=0.0).to(tl.float32)
+    tmp15 = tl.load(in_ptr2 + (64 + 128*tmp10 + (x0)), xmask & tmp4, eviction_policy='evict_last', other=0.0).to(tl.float32)
+    tmp16 = tmp14 * tmp15
+    tmp17 = tmp13 - tmp16
+    tmp18 = tl.full(tmp17.shape, 0.0, tmp17.dtype)
+    tmp19 = tl.where(tmp4, tmp17, tmp18)
+    tmp20 = tmp0 >= tmp3
+    tmp21 = tl.full([1], 128, tl.int64)
+    tmp22 = tmp0 < tmp21
+    tmp23 = tl.load(in_ptr0 + (3648 + 128*x1 + 4608*x2 + ((-64) + x0)), xmask & tmp20, eviction_policy='evict_last', other=0.0).to(tl.float32)
+    tmp24 = tl.load(in_ptr1 + (x2), xmask & tmp20, eviction_policy='evict_last', other=0.0)
+    tmp25 = tl.full([XBLOCK], 131072, tl.int32)
+    tmp26 = tmp24 + tmp25
+    tmp27 = tmp24 < 0
+    tmp28 = tl.where(tmp27, tmp26, tmp24)
+    tl.device_assert(((0 <= tl.broadcast_to(tmp28, [XBLOCK])) & (tl.broadcast_to(tmp28, [XBLOCK]) < 131072)) | ~(xmask & tmp20), "index out of bounds: 0 <= tl.broadcast_to(tmp28, [XBLOCK]) < 131072")
+    tmp30 = tl.load(in_ptr2 + (128*tmp28 + ((-64) + x0)), xmask & tmp20, eviction_policy='evict_last', other=0.0).to(tl.float32)
+    tmp31 = tmp23 * tmp30
+    tmp32 = tl.load(in_ptr0 + (3584 + 128*x1 + 4608*x2 + ((-64) + x0)), xmask & tmp20, eviction_policy='evict_last', other=0.0).to(tl.float32)
+    tmp33 = tl.load(in_ptr2 + (64 + 128*tmp28 + ((-64) + x0)), xmask & tmp20, eviction_policy='evict_last', other=0.0).to(tl.float32)
+    tmp34 = tmp32 * tmp33
+    tmp35 = tmp31 + tmp34
+    tmp36 = tl.full(tmp35.shape, 0.0, tmp35.dtype)
+    tmp37 = tl.where(tmp20, tmp35, tmp36)
+    tmp38 = tl.where(tmp4, tmp19, tmp37)
+    tl.store(out_ptr0 + (x4), tmp38, xmask)

platform/aiml/models/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/fs/e6992cd62d821ebcd5127e9b808957313ca6438ffabca12f64e17a0a6e7f19a3.best_config

@@ -0,0 +1 @@
+{"XBLOCK": 1024, "num_warps": 4, "num_stages": 1, "configs_hash": "3ca5c3e34d35093f3c9ab2829a9faeebad5e61c4ca13d5ed6053d7b71ce60d5a", "found_by_coordesc": false, "time_taken_ms": 12}

platform/aiml/models/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/jc/9951aeebb36ea3d940675958440fd5e1aef95db7493ee16b18874b4b25e8836d.best_config

@@ -0,0 +1 @@
+{"XBLOCK": 1024, "num_warps": 4, "num_stages": 1, "configs_hash": "3ca5c3e34d35093f3c9ab2829a9faeebad5e61c4ca13d5ed6053d7b71ce60d5a", "found_by_coordesc": false, "time_taken_ms": 12}

platform/aiml/models/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/jc/cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py

@@ -0,0 +1,65 @@
+
+import triton
+import triton.language as tl
+
+from torch._inductor.runtime import triton_helpers, triton_heuristics
+from torch._inductor.runtime.triton_helpers import libdevice, math as tl_math
+from torch._inductor.runtime.hints import AutotuneHint, ReductionHint, TileHint, DeviceProperties
+triton_helpers.set_driver_to_gpu()
+
+@triton_heuristics.pointwise(
+    size_hints={'x': 4194304}, 
+    filename=__file__,
+    triton_meta={'signature': {'in_ptr0': '*bf16', 'in_ptr1': '*i64', 'in_ptr2': '*bf16', 'out_ptr0': '*bf16', 'xnumel': 'i32', 'XBLOCK': 'constexpr'}, 'device': DeviceProperties(type='cuda', index=0, multi_processor_count=132, cc=90, major=9, regs_per_multiprocessor=65536, max_threads_per_multi_processor=2048, warp_size=32), 'constants': {}, 'configs': [{(0,): [['tt.divisibility', 16]], (1,): [['tt.divisibility', 16]], (2,): [['tt.divisibility', 16]], (3,): [['tt.divisibility', 16]], (4,): [['tt.divisibility', 16]]}]},
+    inductor_meta={'grid_type': 'Grid1D', 'autotune_hints': set(), 'kernel_name': 'triton_poi_fused_cat_2', 'mutated_arg_names': [], 'optimize_mem': True, 'no_x_dim': False, 'num_load': 6, 'num_reduction': 0, 'backend_hash': 'F43D6982A315236AF8E29EA38FBEB3BFF1A29D8B91A2D6952242D4C92EF73270', 'are_deterministic_algorithms_enabled': False, 'assert_indirect_indexing': True, 'autotune_local_cache': True, 'autotune_pointwise': True, 'autotune_remote_cache': None, 'force_disable_caches': False, 'dynamic_scale_rblock': True, 'max_autotune': False, 'max_autotune_pointwise': False, 'min_split_scan_rblock': 256, 'spill_threshold': 16, 'store_cubin': False},
+    min_elem_per_thread=0
+)
+@triton.jit
+def triton_poi_fused_cat_2(in_ptr0, in_ptr1, in_ptr2, out_ptr0, xnumel, XBLOCK : tl.constexpr):
+    xoffset = tl.program_id(0) * XBLOCK
+    xindex = xoffset + tl.arange(0, XBLOCK)[:]
+    xmask = xindex < xnumel
+    x0 = (xindex % 128)
+    x1 = ((xindex // 128) % 4)
+    x2 = xindex // 512
+    x4 = xindex
+    tmp0 = x0
+    tmp1 = tl.full([1], 0, tl.int64)
+    tmp2 = tmp0 >= tmp1
+    tmp3 = tl.full([1], 64, tl.int64)
+    tmp4 = tmp0 < tmp3
+    tmp5 = tl.load(in_ptr0 + (3584 + 128*x1 + 4608*x2 + (x0)), xmask & tmp4, eviction_policy='evict_last', other=0.0).to(tl.float32)
+    tmp6 = tl.load(in_ptr1 + (x2), xmask & tmp4, eviction_policy='evict_last', other=0.0)
+    tmp7 = tl.full([XBLOCK], 131072, tl.int32)
+    tmp8 = tmp6 + tmp7
+    tmp9 = tmp6 < 0
+    tmp10 = tl.where(tmp9, tmp8, tmp6)
+    tl.device_assert(((0 <= tl.broadcast_to(tmp10, [XBLOCK])) & (tl.broadcast_to(tmp10, [XBLOCK]) < 131072)) | ~(xmask & tmp4), "index out of bounds: 0 <= tl.broadcast_to(tmp10, [XBLOCK]) < 131072")
+    tmp12 = tl.load(in_ptr2 + (128*tmp10 + (x0)), xmask & tmp4, eviction_policy='evict_last', other=0.0).to(tl.float32)
+    tmp13 = tmp5 * tmp12
+    tmp14 = tl.load(in_ptr0 + (3648 + 128*x1 + 4608*x2 + (x0)), xmask & tmp4, eviction_policy='evict_last', other=0.0).to(tl.float32)
+    tmp15 = tl.load(in_ptr2 + (64 + 128*tmp10 + (x0)), xmask & tmp4, eviction_policy='evict_last', other=0.0).to(tl.float32)
+    tmp16 = tmp14 * tmp15
+    tmp17 = tmp13 - tmp16
+    tmp18 = tl.full(tmp17.shape, 0.0, tmp17.dtype)
+    tmp19 = tl.where(tmp4, tmp17, tmp18)
+    tmp20 = tmp0 >= tmp3
+    tmp21 = tl.full([1], 128, tl.int64)
+    tmp22 = tmp0 < tmp21
+    tmp23 = tl.load(in_ptr0 + (3648 + 128*x1 + 4608*x2 + ((-64) + x0)), xmask & tmp20, eviction_policy='evict_last', other=0.0).to(tl.float32)
+    tmp24 = tl.load(in_ptr1 + (x2), xmask & tmp20, eviction_policy='evict_last', other=0.0)
+    tmp25 = tl.full([XBLOCK], 131072, tl.int32)
+    tmp26 = tmp24 + tmp25
+    tmp27 = tmp24 < 0
+    tmp28 = tl.where(tmp27, tmp26, tmp24)
+    tl.device_assert(((0 <= tl.broadcast_to(tmp28, [XBLOCK])) & (tl.broadcast_to(tmp28, [XBLOCK]) < 131072)) | ~(xmask & tmp20), "index out of bounds: 0 <= tl.broadcast_to(tmp28, [XBLOCK]) < 131072")
+    tmp30 = tl.load(in_ptr2 + (128*tmp28 + ((-64) + x0)), xmask & tmp20, eviction_policy='evict_last', other=0.0).to(tl.float32)
+    tmp31 = tmp23 * tmp30
+    tmp32 = tl.load(in_ptr0 + (3584 + 128*x1 + 4608*x2 + ((-64) + x0)), xmask & tmp20, eviction_policy='evict_last', other=0.0).to(tl.float32)
+    tmp33 = tl.load(in_ptr2 + (64 + 128*tmp28 + ((-64) + x0)), xmask & tmp20, eviction_policy='evict_last', other=0.0).to(tl.float32)
+    tmp34 = tmp32 * tmp33
+    tmp35 = tmp31 + tmp34
+    tmp36 = tl.full(tmp35.shape, 0.0, tmp35.dtype)
+    tmp37 = tl.where(tmp20, tmp35, tmp36)
+    tmp38 = tl.where(tmp4, tmp19, tmp37)
+    tl.store(out_ptr0 + (x4), tmp38, xmask)

platform/aiml/models/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/kx/ckxvdfgxhb3qwf2i5askplyvuxh257jqaiodjraqxsprweahmslo.py

@@ -0,0 +1,377 @@
+# AOT ID: ['0_inference']
+from ctypes import c_void_p, c_long, c_int
+import torch
+import math
+import random
+import os
+import tempfile
+from math import inf, nan
+from cmath import nanj
+from torch._inductor.hooks import run_intermediate_hooks
+from torch._inductor.utils import maybe_profile
+from torch._inductor.codegen.memory_planning import _align as align
+from torch import device, empty_strided
+from torch._inductor.async_compile import AsyncCompile
+from torch._inductor.select_algorithm import extern_kernels
+from torch._inductor.codegen.multi_kernel import MultiKernelCall
+import triton
+import triton.language as tl
+from torch._inductor.runtime.triton_heuristics import start_graph, end_graph
+from torch._C import _cuda_getCurrentRawStream as get_raw_stream
+from torch._C import _cuda_getCurrentRawStream as get_raw_stream
+
+aten = torch.ops.aten
+inductor_ops = torch.ops.inductor
+_quantized = torch.ops._quantized
+assert_size_stride = torch._C._dynamo.guards.assert_size_stride
+empty_strided_cpu = torch._C._dynamo.guards._empty_strided_cpu
+empty_strided_cuda = torch._C._dynamo.guards._empty_strided_cuda
+empty_strided_xpu = torch._C._dynamo.guards._empty_strided_xpu
+reinterpret_tensor = torch._C._dynamo.guards._reinterpret_tensor
+alloc_from_pool = torch.ops.inductor._alloc_from_pool
+async_compile = AsyncCompile()
+empty_strided_p2p = torch._C._distributed_c10d._SymmetricMemory.empty_strided_p2p
+
+
+# kernel path: /home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py
+# Topologically Sorted Source Nodes: [long, embedding, to, pow_1, mean, add, rsqrt, mul, to_1, mul_1], Original ATen: [aten._to_copy, aten.embedding, aten.pow, aten.mean, aten.add, aten.rsqrt, aten.mul]
+# Source node to ATen node mapping:
+#   add => add_14
+#   embedding => embedding
+#   long => convert_element_type
+#   mean => mean
+#   mul => mul_10
+#   mul_1 => mul_15
+#   pow_1 => pow_1
+#   rsqrt => rsqrt
+#   to => convert_element_type_1
+#   to_1 => convert_element_type_2
+# Graph fragment:
+#   %convert_element_type : [num_users=1] = call_function[target=torch.ops.prims.convert_element_type.default](args = (%arg0_1, torch.int64), kwargs = {})
+#   %embedding : [num_users=2] = call_function[target=torch.ops.aten.embedding.default](args = (%arg2_1, %convert_element_type), kwargs = {})
+#   %convert_element_type_1 : [num_users=2] = call_function[target=torch.ops.prims.convert_element_type.default](args = (%embedding, torch.float32), kwargs = {})
+#   %pow_1 : [num_users=1] = call_function[target=torch.ops.aten.pow.Tensor_Scalar](args = (%convert_element_type_1, 2), kwargs = {})
+#   %mean : [num_users=1] = call_function[target=torch.ops.aten.mean.dim](args = (%pow_1, [-1], True), kwargs = {})
+#   %add_14 : [num_users=1] = call_function[target=torch.ops.aten.add.Tensor](args = (%mean, 1e-06), kwargs = {})
+#   %rsqrt : [num_users=1] = call_function[target=torch.ops.aten.rsqrt.default](args = (%add_14,), kwargs = {})
+#   %mul_10 : [num_users=1] = call_function[target=torch.ops.aten.mul.Tensor](args = (%convert_element_type_1, %rsqrt), kwargs = {})
+#   %convert_element_type_2 : [num_users=1] = call_function[target=torch.ops.prims.convert_element_type.default](args = (%mul_10, torch.bfloat16), kwargs = {})
+#   %mul_15 : [num_users=1] = call_function[target=torch.ops.aten.mul.Tensor](args = (%convert_element_type_2, %arg3_1), kwargs = {})
+triton_red_fused__to_copy_add_embedding_mean_mul_pow_rsqrt_0 = async_compile.triton('triton_red_fused__to_copy_add_embedding_mean_mul_pow_rsqrt_0', '''
+import triton
+import triton.language as tl
+
+from torch._inductor.runtime import triton_helpers, triton_heuristics
+from torch._inductor.runtime.triton_helpers import libdevice, math as tl_math
+from torch._inductor.runtime.hints import AutotuneHint, ReductionHint, TileHint, DeviceProperties
+triton_helpers.set_driver_to_gpu()
+
+@triton_heuristics.reduction(
+    size_hints={'x': 8192, 'r0_': 4096},
+    reduction_hint=ReductionHint.INNER,
+    filename=__file__,
+    triton_meta={'signature': {'in_ptr0': '*i32', 'in_ptr1': '*bf16', 'in_ptr2': '*bf16', 'out_ptr0': '*bf16', 'out_ptr2': '*bf16', 'xnumel': 'i32', 'r0_numel': 'i32', 'XBLOCK': 'constexpr', 'R0_BLOCK': 'constexpr'}, 'device': DeviceProperties(type='cuda', index=0, multi_processor_count=132, cc=90, major=9, regs_per_multiprocessor=65536, max_threads_per_multi_processor=2048, warp_size=32), 'constants': {}, 'configs': [{(0,): [['tt.divisibility', 16]], (1,): [['tt.divisibility', 16]], (2,): [['tt.divisibility', 16]], (3,): [['tt.divisibility', 16]], (4,): [['tt.divisibility', 16]], (6,): [['tt.divisibility', 16]]}]},
+    inductor_meta={'grid_type': 'Grid1D', 'autotune_hints': set(), 'kernel_name': 'triton_red_fused__to_copy_add_embedding_mean_mul_pow_rsqrt_0', 'mutated_arg_names': [], 'optimize_mem': True, 'no_x_dim': False, 'num_load': 3, 'num_reduction': 1, 'backend_hash': 'F43D6982A315236AF8E29EA38FBEB3BFF1A29D8B91A2D6952242D4C92EF73270', 'are_deterministic_algorithms_enabled': False, 'assert_indirect_indexing': True, 'autotune_local_cache': True, 'autotune_pointwise': True, 'autotune_remote_cache': None, 'force_disable_caches': False, 'dynamic_scale_rblock': True, 'max_autotune': False, 'max_autotune_pointwise': False, 'min_split_scan_rblock': 256, 'spill_threshold': 16, 'store_cubin': False}
+)
+@triton.jit
+def triton_red_fused__to_copy_add_embedding_mean_mul_pow_rsqrt_0(in_ptr0, in_ptr1, in_ptr2, out_ptr0, out_ptr2, xnumel, r0_numel, XBLOCK : tl.constexpr, R0_BLOCK : tl.constexpr):
+    r0_numel = 3584
+    rnumel = r0_numel
+    RBLOCK: tl.constexpr = R0_BLOCK
+    xoffset = tl.program_id(0) * XBLOCK
+    xindex = xoffset + tl.arange(0, XBLOCK)[:, None]
+    xmask = xindex < xnumel
+    r0_base = tl.arange(0, R0_BLOCK)[None, :]
+    rbase = r0_base
+    x0 = xindex
+    tmp0 = tl.load(in_ptr0 + (x0), xmask, eviction_policy='evict_last')
+    _tmp11 = tl.full([XBLOCK, R0_BLOCK], 0, tl.float32)
+    for r0_offset in range(0, r0_numel, R0_BLOCK):
+        r0_index = r0_offset + r0_base
+        r0_mask = r0_index < r0_numel
+        roffset = r0_offset
+        rindex = r0_index
+        r0_1 = r0_index
+        tmp1 = tmp0.to(tl.int64)
+        tmp2 = tl.full([XBLOCK, R0_BLOCK], 152064, tl.int32)
+        tmp3 = tmp1 + tmp2
+        tmp4 = tmp1 < 0
+        tmp5 = tl.where(tmp4, tmp3, tmp1)
+        tl.device_assert(((0 <= tmp5) & (tmp5 < 152064)) | ~(xmask), "index out of bounds: 0 <= tmp5 < 152064")
+        tmp7 = tl.load(in_ptr1 + (r0_1 + 3584*tmp5), xmask & r0_mask, eviction_policy='evict_first', other=0.0).to(tl.float32)
+        tmp8 = tmp7.to(tl.float32)
+        tmp9 = tmp8 * tmp8
+        tmp10 = tl.broadcast_to(tmp9, [XBLOCK, R0_BLOCK])
+        tmp12 = _tmp11 + tmp10
+        _tmp11 = tl.where(r0_mask & xmask, tmp12, _tmp11)
+        tl.store(out_ptr0 + (r0_1 + 3584*x0), tmp7, r0_mask & xmask)
+    tmp11 = tl.sum(_tmp11, 1)[:, None]
+    for r0_offset in range(0, r0_numel, R0_BLOCK):
+        r0_index = r0_offset + r0_base
+        r0_mask = r0_index < r0_numel
+        roffset = r0_offset
+        rindex = r0_index
+        r0_1 = r0_index
+        tmp13 = tl.load(out_ptr0 + (r0_1 + 3584*x0), r0_mask & xmask, eviction_policy='evict_first', other=0.0).to(tl.float32)
+        tmp22 = tl.load(in_ptr2 + (r0_1), r0_mask, eviction_policy='evict_last', other=0.0).to(tl.float32)
+        tmp14 = tmp13.to(tl.float32)
+        tmp15 = 3584.0
+        tmp16 = (tmp11 / tmp15)
+        tmp17 = 1e-06
+        tmp18 = tmp16 + tmp17
+        tmp19 = libdevice.rsqrt(tmp18)
+        tmp20 = tmp14 * tmp19
+        tmp21 = tmp20.to(tl.float32)
+        tmp23 = tmp21 * tmp22
+        tl.store(out_ptr2 + (r0_1 + 3584*x0), tmp23, r0_mask & xmask)
+''', device_str='cuda')
+
+
+# kernel path: /home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py
+# Topologically Sorted Source Nodes: [cat], Original ATen: [aten.cat]
+# Source node to ATen node mapping:
+#   cat => cat
+# Graph fragment:
+#   %cat : [num_users=1] = call_function[target=torch.ops.aten.cat.default](args = ([%sub_26, %add_97], -1), kwargs = {})
+triton_poi_fused_cat_1 = async_compile.triton('triton_poi_fused_cat_1', '''
+import triton
+import triton.language as tl
+
+from torch._inductor.runtime import triton_helpers, triton_heuristics
+from torch._inductor.runtime.triton_helpers import libdevice, math as tl_math
+from torch._inductor.runtime.hints import AutotuneHint, ReductionHint, TileHint, DeviceProperties
+triton_helpers.set_driver_to_gpu()
+
+@triton_heuristics.pointwise(
+    size_hints={'x': 33554432}, 
+    filename=__file__,
+    triton_meta={'signature': {'in_ptr0': '*bf16', 'in_ptr1': '*i64', 'in_ptr2': '*bf16', 'out_ptr0': '*bf16', 'xnumel': 'i32', 'XBLOCK': 'constexpr'}, 'device': DeviceProperties(type='cuda', index=0, multi_processor_count=132, cc=90, major=9, regs_per_multiprocessor=65536, max_threads_per_multi_processor=2048, warp_size=32), 'constants': {}, 'configs': [{(0,): [['tt.divisibility', 16]], (1,): [['tt.divisibility', 16]], (2,): [['tt.divisibility', 16]], (3,): [['tt.divisibility', 16]], (4,): [['tt.divisibility', 16]]}]},
+    inductor_meta={'grid_type': 'Grid1D', 'autotune_hints': set(), 'kernel_name': 'triton_poi_fused_cat_1', 'mutated_arg_names': [], 'optimize_mem': True, 'no_x_dim': False, 'num_load': 6, 'num_reduction': 0, 'backend_hash': 'F43D6982A315236AF8E29EA38FBEB3BFF1A29D8B91A2D6952242D4C92EF73270', 'are_deterministic_algorithms_enabled': False, 'assert_indirect_indexing': True, 'autotune_local_cache': True, 'autotune_pointwise': True, 'autotune_remote_cache': None, 'force_disable_caches': False, 'dynamic_scale_rblock': True, 'max_autotune': False, 'max_autotune_pointwise': False, 'min_split_scan_rblock': 256, 'spill_threshold': 16, 'store_cubin': False},
+    min_elem_per_thread=0
+)
+@triton.jit
+def triton_poi_fused_cat_1(in_ptr0, in_ptr1, in_ptr2, out_ptr0, xnumel, XBLOCK : tl.constexpr):
+    xoffset = tl.program_id(0) * XBLOCK
+    xindex = xoffset + tl.arange(0, XBLOCK)[:]
+    xmask = xindex < xnumel
+    x0 = (xindex % 128)
+    x1 = ((xindex // 128) % 28)
+    x2 = xindex // 3584
+    x4 = xindex
+    tmp0 = x0
+    tmp1 = tl.full([1], 0, tl.int64)
+    tmp2 = tmp0 >= tmp1
+    tmp3 = tl.full([1], 64, tl.int64)
+    tmp4 = tmp0 < tmp3
+    tmp5 = tl.load(in_ptr0 + (128*x1 + 4608*x2 + (x0)), xmask & tmp4, eviction_policy='evict_last', other=0.0).to(tl.float32)
+    tmp6 = tl.load(in_ptr1 + (x2), xmask & tmp4, eviction_policy='evict_last', other=0.0)
+    tmp7 = tl.full([XBLOCK], 131072, tl.int32)
+    tmp8 = tmp6 + tmp7
+    tmp9 = tmp6 < 0
+    tmp10 = tl.where(tmp9, tmp8, tmp6)
+    tl.device_assert(((0 <= tl.broadcast_to(tmp10, [XBLOCK])) & (tl.broadcast_to(tmp10, [XBLOCK]) < 131072)) | ~(xmask & tmp4), "index out of bounds: 0 <= tl.broadcast_to(tmp10, [XBLOCK]) < 131072")
+    tmp12 = tl.load(in_ptr2 + (128*tmp10 + (x0)), xmask & tmp4, eviction_policy='evict_last', other=0.0).to(tl.float32)
+    tmp13 = tmp5 * tmp12
+    tmp14 = tl.load(in_ptr0 + (64 + 128*x1 + 4608*x2 + (x0)), xmask & tmp4, eviction_policy='evict_last', other=0.0).to(tl.float32)
+    tmp15 = tl.load(in_ptr2 + (64 + 128*tmp10 + (x0)), xmask & tmp4, eviction_policy='evict_last', other=0.0).to(tl.float32)
+    tmp16 = tmp14 * tmp15
+    tmp17 = tmp13 - tmp16
+    tmp18 = tl.full(tmp17.shape, 0.0, tmp17.dtype)
+    tmp19 = tl.where(tmp4, tmp17, tmp18)
+    tmp20 = tmp0 >= tmp3
+    tmp21 = tl.full([1], 128, tl.int64)
+    tmp22 = tmp0 < tmp21
+    tmp23 = tl.load(in_ptr0 + (64 + 128*x1 + 4608*x2 + ((-64) + x0)), xmask & tmp20, eviction_policy='evict_last', other=0.0).to(tl.float32)
+    tmp24 = tl.load(in_ptr1 + (x2), xmask & tmp20, eviction_policy='evict_last', other=0.0)
+    tmp25 = tl.full([XBLOCK], 131072, tl.int32)
+    tmp26 = tmp24 + tmp25
+    tmp27 = tmp24 < 0
+    tmp28 = tl.where(tmp27, tmp26, tmp24)
+    tl.device_assert(((0 <= tl.broadcast_to(tmp28, [XBLOCK])) & (tl.broadcast_to(tmp28, [XBLOCK]) < 131072)) | ~(xmask & tmp20), "index out of bounds: 0 <= tl.broadcast_to(tmp28, [XBLOCK]) < 131072")
+    tmp30 = tl.load(in_ptr2 + (128*tmp28 + ((-64) + x0)), xmask & tmp20, eviction_policy='evict_last', other=0.0).to(tl.float32)
+    tmp31 = tmp23 * tmp30
+    tmp32 = tl.load(in_ptr0 + (128*x1 + 4608*x2 + ((-64) + x0)), xmask & tmp20, eviction_policy='evict_last', other=0.0).to(tl.float32)
+    tmp33 = tl.load(in_ptr2 + (64 + 128*tmp28 + ((-64) + x0)), xmask & tmp20, eviction_policy='evict_last', other=0.0).to(tl.float32)
+    tmp34 = tmp32 * tmp33
+    tmp35 = tmp31 + tmp34
+    tmp36 = tl.full(tmp35.shape, 0.0, tmp35.dtype)
+    tmp37 = tl.where(tmp20, tmp35, tmp36)
+    tmp38 = tl.where(tmp4, tmp19, tmp37)
+    tl.store(out_ptr0 + (x4), tmp38, xmask)
+''', device_str='cuda')
+
+
+# kernel path: /home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/jc/cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py
+# Topologically Sorted Source Nodes: [cat_2], Original ATen: [aten.cat]
+# Source node to ATen node mapping:
+#   cat_2 => cat_1
+# Graph fragment:
+#   %cat_1 : [num_users=1] = call_function[target=torch.ops.aten.cat.default](args = ([%sub_43, %add_159], -1), kwargs = {})
+triton_poi_fused_cat_2 = async_compile.triton('triton_poi_fused_cat_2', '''
+import triton
+import triton.language as tl
+
+from torch._inductor.runtime import triton_helpers, triton_heuristics
+from torch._inductor.runtime.triton_helpers import libdevice, math as tl_math
+from torch._inductor.runtime.hints import AutotuneHint, ReductionHint, TileHint, DeviceProperties
+triton_helpers.set_driver_to_gpu()
+
+@triton_heuristics.pointwise(
+    size_hints={'x': 4194304}, 
+    filename=__file__,
+    triton_meta={'signature': {'in_ptr0': '*bf16', 'in_ptr1': '*i64', 'in_ptr2': '*bf16', 'out_ptr0': '*bf16', 'xnumel': 'i32', 'XBLOCK': 'constexpr'}, 'device': DeviceProperties(type='cuda', index=0, multi_processor_count=132, cc=90, major=9, regs_per_multiprocessor=65536, max_threads_per_multi_processor=2048, warp_size=32), 'constants': {}, 'configs': [{(0,): [['tt.divisibility', 16]], (1,): [['tt.divisibility', 16]], (2,): [['tt.divisibility', 16]], (3,): [['tt.divisibility', 16]], (4,): [['tt.divisibility', 16]]}]},
+    inductor_meta={'grid_type': 'Grid1D', 'autotune_hints': set(), 'kernel_name': 'triton_poi_fused_cat_2', 'mutated_arg_names': [], 'optimize_mem': True, 'no_x_dim': False, 'num_load': 6, 'num_reduction': 0, 'backend_hash': 'F43D6982A315236AF8E29EA38FBEB3BFF1A29D8B91A2D6952242D4C92EF73270', 'are_deterministic_algorithms_enabled': False, 'assert_indirect_indexing': True, 'autotune_local_cache': True, 'autotune_pointwise': True, 'autotune_remote_cache': None, 'force_disable_caches': False, 'dynamic_scale_rblock': True, 'max_autotune': False, 'max_autotune_pointwise': False, 'min_split_scan_rblock': 256, 'spill_threshold': 16, 'store_cubin': False},
+    min_elem_per_thread=0
+)
+@triton.jit
+def triton_poi_fused_cat_2(in_ptr0, in_ptr1, in_ptr2, out_ptr0, xnumel, XBLOCK : tl.constexpr):
+    xoffset = tl.program_id(0) * XBLOCK
+    xindex = xoffset + tl.arange(0, XBLOCK)[:]
+    xmask = xindex < xnumel
+    x0 = (xindex % 128)
+    x1 = ((xindex // 128) % 4)
+    x2 = xindex // 512
+    x4 = xindex
+    tmp0 = x0
+    tmp1 = tl.full([1], 0, tl.int64)
+    tmp2 = tmp0 >= tmp1
+    tmp3 = tl.full([1], 64, tl.int64)
+    tmp4 = tmp0 < tmp3
+    tmp5 = tl.load(in_ptr0 + (3584 + 128*x1 + 4608*x2 + (x0)), xmask & tmp4, eviction_policy='evict_last', other=0.0).to(tl.float32)
+    tmp6 = tl.load(in_ptr1 + (x2), xmask & tmp4, eviction_policy='evict_last', other=0.0)
+    tmp7 = tl.full([XBLOCK], 131072, tl.int32)
+    tmp8 = tmp6 + tmp7
+    tmp9 = tmp6 < 0
+    tmp10 = tl.where(tmp9, tmp8, tmp6)
+    tl.device_assert(((0 <= tl.broadcast_to(tmp10, [XBLOCK])) & (tl.broadcast_to(tmp10, [XBLOCK]) < 131072)) | ~(xmask & tmp4), "index out of bounds: 0 <= tl.broadcast_to(tmp10, [XBLOCK]) < 131072")
+    tmp12 = tl.load(in_ptr2 + (128*tmp10 + (x0)), xmask & tmp4, eviction_policy='evict_last', other=0.0).to(tl.float32)
+    tmp13 = tmp5 * tmp12
+    tmp14 = tl.load(in_ptr0 + (3648 + 128*x1 + 4608*x2 + (x0)), xmask & tmp4, eviction_policy='evict_last', other=0.0).to(tl.float32)
+    tmp15 = tl.load(in_ptr2 + (64 + 128*tmp10 + (x0)), xmask & tmp4, eviction_policy='evict_last', other=0.0).to(tl.float32)
+    tmp16 = tmp14 * tmp15
+    tmp17 = tmp13 - tmp16
+    tmp18 = tl.full(tmp17.shape, 0.0, tmp17.dtype)
+    tmp19 = tl.where(tmp4, tmp17, tmp18)
+    tmp20 = tmp0 >= tmp3
+    tmp21 = tl.full([1], 128, tl.int64)
+    tmp22 = tmp0 < tmp21
+    tmp23 = tl.load(in_ptr0 + (3648 + 128*x1 + 4608*x2 + ((-64) + x0)), xmask & tmp20, eviction_policy='evict_last', other=0.0).to(tl.float32)
+    tmp24 = tl.load(in_ptr1 + (x2), xmask & tmp20, eviction_policy='evict_last', other=0.0)
+    tmp25 = tl.full([XBLOCK], 131072, tl.int32)
+    tmp26 = tmp24 + tmp25
+    tmp27 = tmp24 < 0
+    tmp28 = tl.where(tmp27, tmp26, tmp24)
+    tl.device_assert(((0 <= tl.broadcast_to(tmp28, [XBLOCK])) & (tl.broadcast_to(tmp28, [XBLOCK]) < 131072)) | ~(xmask & tmp20), "index out of bounds: 0 <= tl.broadcast_to(tmp28, [XBLOCK]) < 131072")
+    tmp30 = tl.load(in_ptr2 + (128*tmp28 + ((-64) + x0)), xmask & tmp20, eviction_policy='evict_last', other=0.0).to(tl.float32)
+    tmp31 = tmp23 * tmp30
+    tmp32 = tl.load(in_ptr0 + (3584 + 128*x1 + 4608*x2 + ((-64) + x0)), xmask & tmp20, eviction_policy='evict_last', other=0.0).to(tl.float32)
+    tmp33 = tl.load(in_ptr2 + (64 + 128*tmp28 + ((-64) + x0)), xmask & tmp20, eviction_policy='evict_last', other=0.0).to(tl.float32)
+    tmp34 = tmp32 * tmp33
+    tmp35 = tmp31 + tmp34
+    tmp36 = tl.full(tmp35.shape, 0.0, tmp35.dtype)
+    tmp37 = tl.where(tmp20, tmp35, tmp36)
+    tmp38 = tl.where(tmp4, tmp19, tmp37)
+    tl.store(out_ptr0 + (x4), tmp38, xmask)
+''', device_str='cuda')
+
+
+# kernel path: /home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/vl/cvldluh6ekwrc6dg3fhtk6itaod5famu6kcfiasoqowee4rnccf2.py
+# Topologically Sorted Source Nodes: [view_3], Original ATen: [aten.view]
+# Source node to ATen node mapping:
+#   view_3 => full_default
+# Graph fragment:
+#   %full_default : [num_users=1] = call_function[target=torch.ops.aten.full.default](args = ([%arg1_1, 28, 128], 0.0), kwargs = {dtype: torch.bfloat16, layout: torch.strided, device: cuda:0, pin_memory: False})
+triton_poi_fused_view_3 = async_compile.triton('triton_poi_fused_view_3', '''
+import triton
+import triton.language as tl
+
+from torch._inductor.runtime import triton_helpers, triton_heuristics
+from torch._inductor.runtime.triton_helpers import libdevice, math as tl_math
+from torch._inductor.runtime.hints import AutotuneHint, ReductionHint, TileHint, DeviceProperties
+triton_helpers.set_driver_to_gpu()
+
+@triton_heuristics.pointwise(
+    size_hints={'x': 33554432}, 
+    filename=__file__,
+    triton_meta={'signature': {'out_ptr0': '*bf16', 'xnumel': 'i32', 'XBLOCK': 'constexpr'}, 'device': DeviceProperties(type='cuda', index=0, multi_processor_count=132, cc=90, major=9, regs_per_multiprocessor=65536, max_threads_per_multi_processor=2048, warp_size=32), 'constants': {}, 'configs': [{(0,): [['tt.divisibility', 16]], (1,): [['tt.divisibility', 16]]}]},
+    inductor_meta={'grid_type': 'Grid1D', 'autotune_hints': set(), 'kernel_name': 'triton_poi_fused_view_3', 'mutated_arg_names': [], 'optimize_mem': True, 'no_x_dim': False, 'num_load': 0, 'num_reduction': 0, 'backend_hash': 'F43D6982A315236AF8E29EA38FBEB3BFF1A29D8B91A2D6952242D4C92EF73270', 'are_deterministic_algorithms_enabled': False, 'assert_indirect_indexing': True, 'autotune_local_cache': True, 'autotune_pointwise': True, 'autotune_remote_cache': None, 'force_disable_caches': False, 'dynamic_scale_rblock': True, 'max_autotune': False, 'max_autotune_pointwise': False, 'min_split_scan_rblock': 256, 'spill_threshold': 16, 'store_cubin': False},
+    min_elem_per_thread=0
+)
+@triton.jit
+def triton_poi_fused_view_3(out_ptr0, xnumel, XBLOCK : tl.constexpr):
+    xoffset = tl.program_id(0) * XBLOCK
+    xindex = xoffset + tl.arange(0, XBLOCK)[:]
+    xmask = xindex < xnumel
+    x0 = xindex
+    tmp0 = 0.0
+    tl.store(out_ptr0 + (x0), tmp0, xmask)
+''', device_str='cuda')
+
+
+async_compile.wait(globals())
+del async_compile
+
+def call(args):
+    arg0_1, arg1_1, arg2_1, arg3_1, arg4_1, arg5_1, arg6_1, arg7_1 = args
+    args.clear()
+    s0 = arg1_1
+    assert_size_stride(arg0_1, (s0, ), (1, ))
+    assert_size_stride(arg2_1, (152064, 3584), (3584, 1))
+    assert_size_stride(arg3_1, (3584, ), (1, ))
+    assert_size_stride(arg4_1, (4608, 3584), (3584, 1))
+    assert_size_stride(arg5_1, (4608, ), (1, ))
+    assert_size_stride(arg6_1, (s0, ), (1, ))
+    assert_size_stride(arg7_1, (131072, 128), (128, 1))
+    with torch.cuda._DeviceGuard(0):
+        torch.cuda.set_device(0)
+        buf0 = empty_strided_cuda((s0, 3584), (3584, 1), torch.bfloat16)
+        buf2 = empty_strided_cuda((s0, 3584), (3584, 1), torch.bfloat16)
+        # Topologically Sorted Source Nodes: [long, embedding, to, pow_1, mean, add, rsqrt, mul, to_1, mul_1], Original ATen: [aten._to_copy, aten.embedding, aten.pow, aten.mean, aten.add, aten.rsqrt, aten.mul]
+        stream0 = get_raw_stream(0)
+        triton_red_fused__to_copy_add_embedding_mean_mul_pow_rsqrt_0.run(arg0_1, arg2_1, arg3_1, buf0, buf2, s0, 3584, stream=stream0)
+        del arg0_1
+        del arg2_1
+        del arg3_1
+        buf3 = empty_strided_cuda((s0, 4608), (4608, 1), torch.bfloat16)
+        # Topologically Sorted Source Nodes: [to, pow_1, mean, add, rsqrt, mul, to_1, mul_1, linear], Original ATen: [aten._to_copy, aten.pow, aten.mean, aten.add, aten.rsqrt, aten.mul, aten.addmm]
+        extern_kernels.addmm(arg5_1, buf2, reinterpret_tensor(arg4_1, (3584, 4608), (1, 3584), 0), alpha=1, beta=1, out=buf3)
+        del arg4_1
+        del arg5_1
+        buf4 = reinterpret_tensor(buf2, (s0, 28, 128), (3584, 128, 1), 0); del buf2  # reuse
+        # Topologically Sorted Source Nodes: [cat], Original ATen: [aten.cat]
+        triton_poi_fused_cat_1_xnumel = 3584*s0
+        stream0 = get_raw_stream(0)
+        triton_poi_fused_cat_1.run(buf3, arg6_1, arg7_1, buf4, triton_poi_fused_cat_1_xnumel, stream=stream0)
+        buf5 = empty_strided_cuda((s0, 4, 128), (512, 128, 1), torch.bfloat16)
+        # Topologically Sorted Source Nodes: [cat_2], Original ATen: [aten.cat]
+        triton_poi_fused_cat_2_xnumel = 512*s0
+        stream0 = get_raw_stream(0)
+        triton_poi_fused_cat_2.run(buf3, arg6_1, arg7_1, buf5, triton_poi_fused_cat_2_xnumel, stream=stream0)
+        del arg6_1
+        del arg7_1
+        buf6 = empty_strided_cuda((s0, 28, 128), (3584, 128, 1), torch.bfloat16)
+        # Topologically Sorted Source Nodes: [view_3], Original ATen: [aten.view]
+        triton_poi_fused_view_3_xnumel = 3584*s0
+        stream0 = get_raw_stream(0)
+        triton_poi_fused_view_3.run(buf6, triton_poi_fused_view_3_xnumel, stream=stream0)
+    return (buf4, buf5, reinterpret_tensor(buf3, (s0, 4, 128), (4608, 128, 1), 4096), buf6, buf0, )
+
+
+def benchmark_compiled_module(times=10, repeat=10):
+    from torch._dynamo.testing import rand_strided
+    from torch._inductor.utils import print_performance
+    arg0_1 = rand_strided((8192, ), (1, ), device='cuda:0', dtype=torch.int32)
+    arg1_1 = 8192
+    arg2_1 = rand_strided((152064, 3584), (3584, 1), device='cuda:0', dtype=torch.bfloat16)
+    arg3_1 = rand_strided((3584, ), (1, ), device='cuda:0', dtype=torch.bfloat16)
+    arg4_1 = rand_strided((4608, 3584), (3584, 1), device='cuda:0', dtype=torch.bfloat16)
+    arg5_1 = rand_strided((4608, ), (1, ), device='cuda:0', dtype=torch.bfloat16)
+    arg6_1 = rand_strided((8192, ), (1, ), device='cuda:0', dtype=torch.int64)
+    arg7_1 = rand_strided((131072, 128), (128, 1), device='cuda:0', dtype=torch.bfloat16)
+    fn = lambda: call([arg0_1, arg1_1, arg2_1, arg3_1, arg4_1, arg5_1, arg6_1, arg7_1])
+    return print_performance(fn, times=times, repeat=repeat)
+
+
+if __name__ == "__main__":
+    from torch._inductor.wrapper_benchmark import compiled_module_main
+    compiled_module_main('None', benchmark_compiled_module)

platform/aiml/models/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py

@@ -0,0 +1,65 @@
+
+import triton
+import triton.language as tl
+
+from torch._inductor.runtime import triton_helpers, triton_heuristics
+from torch._inductor.runtime.triton_helpers import libdevice, math as tl_math
+from torch._inductor.runtime.hints import AutotuneHint, ReductionHint, TileHint, DeviceProperties
+triton_helpers.set_driver_to_gpu()
+
+@triton_heuristics.reduction(
+    size_hints={'x': 8192, 'r0_': 4096},
+    reduction_hint=ReductionHint.INNER,
+    filename=__file__,
+    triton_meta={'signature': {'in_ptr0': '*bf16', 'in_ptr1': '*bf16', 'in_ptr2': '*bf16', 'out_ptr1': '*bf16', 'xnumel': 'i32', 'r0_numel': 'i32', 'XBLOCK': 'constexpr', 'R0_BLOCK': 'constexpr'}, 'device': DeviceProperties(type='cuda', index=0, multi_processor_count=132, cc=90, major=9, regs_per_multiprocessor=65536, max_threads_per_multi_processor=2048, warp_size=32), 'constants': {}, 'configs': [{(0,): [['tt.divisibility', 16]], (1,): [['tt.divisibility', 16]], (2,): [['tt.divisibility', 16]], (3,): [['tt.divisibility', 16]], (5,): [['tt.divisibility', 16]]}]},
+    inductor_meta={'grid_type': 'Grid1D', 'autotune_hints': set(), 'kernel_name': 'triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_0', 'mutated_arg_names': [], 'optimize_mem': True, 'no_x_dim': False, 'num_load': 5, 'num_reduction': 1, 'backend_hash': 'F43D6982A315236AF8E29EA38FBEB3BFF1A29D8B91A2D6952242D4C92EF73270', 'are_deterministic_algorithms_enabled': False, 'assert_indirect_indexing': True, 'autotune_local_cache': True, 'autotune_pointwise': True, 'autotune_remote_cache': None, 'force_disable_caches': False, 'dynamic_scale_rblock': True, 'max_autotune': False, 'max_autotune_pointwise': False, 'min_split_scan_rblock': 256, 'spill_threshold': 16, 'store_cubin': False}
+)
+@triton.jit
+def triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_0(in_ptr0, in_ptr1, in_ptr2, out_ptr1, xnumel, r0_numel, XBLOCK : tl.constexpr, R0_BLOCK : tl.constexpr):
+    r0_numel = 3584
+    rnumel = r0_numel
+    RBLOCK: tl.constexpr = R0_BLOCK
+    xoffset = tl.program_id(0) * XBLOCK
+    xindex = xoffset + tl.arange(0, XBLOCK)[:, None]
+    xmask = xindex < xnumel
+    r0_base = tl.arange(0, R0_BLOCK)[None, :]
+    rbase = r0_base
+    x0 = xindex
+    _tmp7 = tl.full([XBLOCK, R0_BLOCK], 0, tl.float32)
+    for r0_offset in range(0, r0_numel, R0_BLOCK):
+        r0_index = r0_offset + r0_base
+        r0_mask = r0_index < r0_numel
+        roffset = r0_offset
+        rindex = r0_index
+        r0_1 = r0_index
+        tmp0 = tl.load(in_ptr0 + (r0_1 + 3584*x0), r0_mask & xmask, eviction_policy='evict_last', other=0.0).to(tl.float32)
+        tmp2 = tl.load(in_ptr1 + (r0_1 + 3584*x0), r0_mask & xmask, eviction_policy='evict_last', other=0.0).to(tl.float32)
+        tmp1 = tmp0.to(tl.float32)
+        tmp3 = tmp2.to(tl.float32)
+        tmp4 = tmp1 + tmp3
+        tmp5 = tmp4 * tmp4
+        tmp6 = tl.broadcast_to(tmp5, [XBLOCK, R0_BLOCK])
+        tmp8 = _tmp7 + tmp6
+        _tmp7 = tl.where(r0_mask & xmask, tmp8, _tmp7)
+    tmp7 = tl.sum(_tmp7, 1)[:, None]
+    for r0_offset in range(0, r0_numel, R0_BLOCK):
+        r0_index = r0_offset + r0_base
+        r0_mask = r0_index < r0_numel
+        roffset = r0_offset
+        rindex = r0_index
+        r0_1 = r0_index
+        tmp9 = tl.load(in_ptr0 + (r0_1 + 3584*x0), r0_mask & xmask, eviction_policy='evict_first', other=0.0).to(tl.float32)
+        tmp11 = tl.load(in_ptr1 + (r0_1 + 3584*x0), r0_mask & xmask, eviction_policy='evict_first', other=0.0).to(tl.float32)
+        tmp21 = tl.load(in_ptr2 + (r0_1), r0_mask, eviction_policy='evict_last', other=0.0).to(tl.float32)
+        tmp10 = tmp9.to(tl.float32)
+        tmp12 = tmp11.to(tl.float32)
+        tmp13 = tmp10 + tmp12
+        tmp14 = 3584.0
+        tmp15 = (tmp7 / tmp14)
+        tmp16 = 1e-06
+        tmp17 = tmp15 + tmp16
+        tmp18 = libdevice.rsqrt(tmp17)
+        tmp19 = tmp13 * tmp18
+        tmp20 = tmp19.to(tl.float32)
+        tmp22 = tmp20 * tmp21
+        tl.store(out_ptr1 + (r0_1 + 3584*x0), tmp22, r0_mask & xmask)

platform/aiml/models/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/rl/crlfh6vfyrefv57vpikmf3lb2kgqzyaqhnhdzoizj44yuurmo5ql.py

@@ -0,0 +1,73 @@
+
+import triton
+import triton.language as tl
+
+from torch._inductor.runtime import triton_helpers, triton_heuristics
+from torch._inductor.runtime.triton_helpers import libdevice, math as tl_math
+from torch._inductor.runtime.hints import AutotuneHint, ReductionHint, TileHint, DeviceProperties
+triton_helpers.set_driver_to_gpu()
+
+@triton_heuristics.reduction(
+    size_hints={'x': 8192, 'r0_': 4096},
+    reduction_hint=ReductionHint.INNER,
+    filename=__file__,
+    triton_meta={'signature': {'in_ptr0': '*bf16', 'in_ptr1': '*bf16', 'in_ptr2': '*bf16', 'in_ptr3': '*bf16', 'out_ptr1': '*bf16', 'out_ptr2': '*bf16', 'xnumel': 'i32', 'r0_numel': 'i32', 'XBLOCK': 'constexpr', 'R0_BLOCK': 'constexpr'}, 'device': DeviceProperties(type='cuda', index=0, multi_processor_count=132, cc=90, major=9, regs_per_multiprocessor=65536, max_threads_per_multi_processor=2048, warp_size=32), 'constants': {}, 'configs': [{(0,): [['tt.divisibility', 16]], (1,): [['tt.divisibility', 16]], (2,): [['tt.divisibility', 16]], (3,): [['tt.divisibility', 16]], (4,): [['tt.divisibility', 16]], (5,): [['tt.divisibility', 16]], (7,): [['tt.divisibility', 16]]}]},
+    inductor_meta={'grid_type': 'Grid1D', 'autotune_hints': set(), 'kernel_name': 'triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2', 'mutated_arg_names': [], 'optimize_mem': True, 'no_x_dim': False, 'num_load': 7, 'num_reduction': 1, 'backend_hash': 'F43D6982A315236AF8E29EA38FBEB3BFF1A29D8B91A2D6952242D4C92EF73270', 'are_deterministic_algorithms_enabled': False, 'assert_indirect_indexing': True, 'autotune_local_cache': True, 'autotune_pointwise': True, 'autotune_remote_cache': None, 'force_disable_caches': False, 'dynamic_scale_rblock': True, 'max_autotune': False, 'max_autotune_pointwise': False, 'min_split_scan_rblock': 256, 'spill_threshold': 16, 'store_cubin': False}
+)
+@triton.jit
+def triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2(in_ptr0, in_ptr1, in_ptr2, in_ptr3, out_ptr1, out_ptr2, xnumel, r0_numel, XBLOCK : tl.constexpr, R0_BLOCK : tl.constexpr):
+    r0_numel = 3584
+    rnumel = r0_numel
+    RBLOCK: tl.constexpr = R0_BLOCK
+    xoffset = tl.program_id(0) * XBLOCK
+    xindex = xoffset + tl.arange(0, XBLOCK)[:, None]
+    xmask = xindex < xnumel
+    r0_base = tl.arange(0, R0_BLOCK)[None, :]
+    rbase = r0_base
+    x0 = xindex
+    _tmp10 = tl.full([XBLOCK, R0_BLOCK], 0, tl.float32)
+    for r0_offset in range(0, r0_numel, R0_BLOCK):
+        r0_index = r0_offset + r0_base
+        r0_mask = r0_index < r0_numel
+        roffset = r0_offset
+        rindex = r0_index
+        r0_1 = r0_index
+        tmp0 = tl.load(in_ptr0 + (r0_1 + 3584*x0), r0_mask & xmask, eviction_policy='evict_last', other=0.0).to(tl.float32)
+        tmp2 = tl.load(in_ptr1 + (r0_1 + 3584*x0), r0_mask & xmask, eviction_policy='evict_last', other=0.0).to(tl.float32)
+        tmp4 = tl.load(in_ptr2 + (r0_1 + 3584*x0), r0_mask & xmask, eviction_policy='evict_last', other=0.0).to(tl.float32)
+        tmp1 = tmp0.to(tl.float32)
+        tmp3 = tmp2.to(tl.float32)
+        tmp5 = tmp4.to(tl.float32)
+        tmp6 = tmp3 + tmp5
+        tmp7 = tmp1 + tmp6
+        tmp8 = tmp7 * tmp7
+        tmp9 = tl.broadcast_to(tmp8, [XBLOCK, R0_BLOCK])
+        tmp11 = _tmp10 + tmp9
+        _tmp10 = tl.where(r0_mask & xmask, tmp11, _tmp10)
+    tmp10 = tl.sum(_tmp10, 1)[:, None]
+    for r0_offset in range(0, r0_numel, R0_BLOCK):
+        r0_index = r0_offset + r0_base
+        r0_mask = r0_index < r0_numel
+        roffset = r0_offset
+        rindex = r0_index
+        r0_1 = r0_index
+        tmp12 = tl.load(in_ptr0 + (r0_1 + 3584*x0), r0_mask & xmask, eviction_policy='evict_first', other=0.0).to(tl.float32)
+        tmp14 = tl.load(in_ptr1 + (r0_1 + 3584*x0), r0_mask & xmask, eviction_policy='evict_first', other=0.0).to(tl.float32)
+        tmp16 = tl.load(in_ptr2 + (r0_1 + 3584*x0), r0_mask & xmask, eviction_policy='evict_first', other=0.0).to(tl.float32)
+        tmp27 = tl.load(in_ptr3 + (r0_1), r0_mask, eviction_policy='evict_last', other=0.0).to(tl.float32)
+        tmp13 = tmp12.to(tl.float32)
+        tmp15 = tmp14.to(tl.float32)
+        tmp17 = tmp16.to(tl.float32)
+        tmp18 = tmp15 + tmp17
+        tmp19 = tmp13 + tmp18
+        tmp20 = 3584.0
+        tmp21 = (tmp10 / tmp20)
+        tmp22 = 1e-06
+        tmp23 = tmp21 + tmp22
+        tmp24 = libdevice.rsqrt(tmp23)
+        tmp25 = tmp19 * tmp24
+        tmp26 = tmp25.to(tl.float32)
+        tmp28 = tmp26 * tmp27
+        tmp29 = tmp19.to(tl.float32)
+        tl.store(out_ptr1 + (r0_1 + 3584*x0), tmp28, r0_mask & xmask)
+        tl.store(out_ptr2 + (r0_1 + 3584*x0), tmp29, r0_mask & xmask)

platform/aiml/models/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/vl/e9fe9833e650e31ed083cf1b1d3b94e571fa8ac83d3dcbe46f0bb262ae60cb1a.best_config

@@ -0,0 +1 @@
+{"XBLOCK": 1024, "num_warps": 4, "num_stages": 1, "configs_hash": "3ca5c3e34d35093f3c9ab2829a9faeebad5e61c4ca13d5ed6053d7b71ce60d5a", "found_by_coordesc": false, "time_taken_ms": 16}

platform/aiml/models/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/triton_cache/56GRXI34W4GACMMG3DGUF6QSRGNYNUEAXKCSMJ7BXVXUVGHL27YA/triton_poi_fused_cat_2.json

@@ -0,0 +1 @@
+{"hash": "ef8d1ba37cb70c013186d8cd42fa12899b86d080ba852627e1bd6f4a98ebd7f0", "target": {"backend": "cuda", "arch": 90, "warp_size": 32}, "num_warps": 4, "num_ctas": 1, "num_stages": 1, "num_buffers_warp_spec": 0, "num_consumer_groups": 0, "reg_dec_producer": 0, "reg_inc_consumer": 0, "maxnreg": null, "cluster_dims": [1, 1, 1], "ptx_version": null, "enable_fp_fusion": true, "launch_cooperative_grid": false, "supported_fp8_dtypes": ["fp8e4b15", "fp8e4nv", "fp8e5"], "deprecated_fp8_dtypes": ["fp8e4b15"], "default_dot_input_precision": "tf32", "allowed_dot_input_precisions": ["tf32", "tf32x3", "ieee"], "max_num_imprecise_acc_default": 1073741824, "extern_libs": [["libdevice", "/home/x/.local/lib/python3.12/site-packages/triton/backends/nvidia/lib/libdevice.10.bc"]], "debug": true, "backend_name": "cuda", "sanitize_overflow": false, "arch": "sm90", "triton_version": "3.3.1", "shared": 0, "tmem_size": 0, "global_scratch_size": 0, "global_scratch_align": 1, "name": "triton_poi_fused_cat_2"}

platform/aiml/models/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/triton_cache/5VJWGVMJ4PCN72YPQKLCBR2EFNJZVDLX75I2N2L5E2N6PXCORMPA/triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_0.ttir

@@ -0,0 +1,138 @@
+#loc = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":18:0)
+#loc1 = loc(unknown)
+#loc24 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":44:25)
+#loc54 = loc(callsite(#loc1 at #loc24))
+module {
+  tt.func public @triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_0(%arg0: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":18:0), %arg1: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":18:0), %arg2: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":18:0), %arg3: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":18:0), %arg4: i32 loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":18:0), %arg5: i32 {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":18:0)) attributes {noinline = false} {
+    %cst = arith.constant dense<0.000000e+00> : tensor<1x2048xbf16> loc(#loc1)
+    %c2048_i32 = arith.constant 2048 : i32 loc(#loc1)
+    %c3584_i32 = arith.constant 3584 : i32 loc(#loc1)
+    %c0_i32 = arith.constant 0 : i32 loc(#loc1)
+    %cst_0 = arith.constant dense<9.99999997E-7> : tensor<1x1xf32> loc(#loc1)
+    %cst_1 = arith.constant dense<3.584000e+03> : tensor<1x1xf32> loc(#loc1)
+    %cst_2 = arith.constant dense<3584> : tensor<1x2048xi32> loc(#loc1)
+    %cst_3 = arith.constant dense<0.000000e+00> : tensor<1x2048xf32> loc(#loc1)
+    %0 = tt.get_program_id x : i32 loc(#loc2)
+    %1 = arith.cmpi slt, %0, %arg4 : i32 loc(#loc3)
+    %2 = tt.make_range {end = 2048 : i32, start = 0 : i32} : tensor<2048xi32> loc(#loc4)
+    %3 = tt.expand_dims %2 {axis = 0 : i32} : tensor<2048xi32> -> tensor<1x2048xi32> loc(#loc5)
+    %4 = scf.for %arg6 = %c0_i32 to %c3584_i32 step %c2048_i32 iter_args(%arg7 = %cst_3) -> (tensor<1x2048xf32>)  : i32 {
+      %7 = tt.splat %arg6 : i32 -> tensor<1x2048xi32> loc(#loc7)
+      %8 = arith.addi %7, %3 : tensor<1x2048xi32> loc(#loc7)
+      %9 = arith.cmpi slt, %8, %cst_2 : tensor<1x2048xi32> loc(#loc8)
+      %10 = arith.muli %0, %c3584_i32 : i32 loc(#loc9)
+      %11 = tt.splat %10 : i32 -> tensor<1x2048xi32> loc(#loc51)
+      %12 = arith.addi %8, %11 : tensor<1x2048xi32> loc(#loc10)
+      %13 = tt.splat %arg0 : !tt.ptr<bf16> -> tensor<1x2048x!tt.ptr<bf16>> loc(#loc11)
+      %14 = tt.addptr %13, %12 : tensor<1x2048x!tt.ptr<bf16>>, tensor<1x2048xi32> loc(#loc11)
+      %15 = tt.splat %1 : i1 -> tensor<1x2048xi1> loc(#loc52)
+      %16 = arith.andi %9, %15 : tensor<1x2048xi1> loc(#loc12)
+      %17 = tt.load %14, %16, %cst evictionPolicy = evict_last : tensor<1x2048x!tt.ptr<bf16>> loc(#loc13)
+      %18 = arith.extf %17 : tensor<1x2048xbf16> to tensor<1x2048xf32> loc(#loc14)
+      %19 = tt.splat %arg1 : !tt.ptr<bf16> -> tensor<1x2048x!tt.ptr<bf16>> loc(#loc15)
+      %20 = tt.addptr %19, %12 : tensor<1x2048x!tt.ptr<bf16>>, tensor<1x2048xi32> loc(#loc15)
+      %21 = tt.load %20, %16, %cst evictionPolicy = evict_last : tensor<1x2048x!tt.ptr<bf16>> loc(#loc16)
+      %22 = arith.extf %21 : tensor<1x2048xbf16> to tensor<1x2048xf32> loc(#loc17)
+      %23 = arith.addf %18, %22 : tensor<1x2048xf32> loc(#loc18)
+      %24 = arith.mulf %23, %23 : tensor<1x2048xf32> loc(#loc19)
+      %25 = arith.addf %arg7, %24 : tensor<1x2048xf32> loc(#loc20)
+      %26 = arith.select %16, %25, %arg7 : tensor<1x2048xi1>, tensor<1x2048xf32> loc(#loc21)
+      scf.yield %26 : tensor<1x2048xf32> loc(#loc22)
+    } loc(#loc6)
+    %5 = "tt.reduce"(%4) <{axis = 1 : i32}> ({
+    ^bb0(%arg6: f32 loc(callsite(#loc1 at #loc24)), %arg7: f32 loc(callsite(#loc1 at #loc24))):
+      %7 = arith.addf %arg6, %arg7 : f32 loc(#loc58)
+      tt.reduce.return %7 : f32 loc(#loc53)
+    }) : (tensor<1x2048xf32>) -> tensor<1xf32> loc(#loc53)
+    %6 = tt.expand_dims %5 {axis = 1 : i32} : tensor<1xf32> -> tensor<1x1xf32> loc(#loc26)
+    scf.for %arg6 = %c0_i32 to %c3584_i32 step %c2048_i32  : i32 {
+      %7 = tt.splat %arg6 : i32 -> tensor<1x2048xi32> loc(#loc28)
+      %8 = arith.addi %7, %3 : tensor<1x2048xi32> loc(#loc28)
+      %9 = arith.cmpi slt, %8, %cst_2 : tensor<1x2048xi32> loc(#loc29)
+      %10 = arith.muli %0, %c3584_i32 : i32 loc(#loc30)
+      %11 = tt.splat %10 : i32 -> tensor<1x2048xi32> loc(#loc56)
+      %12 = arith.addi %8, %11 : tensor<1x2048xi32> loc(#loc31)
+      %13 = tt.splat %arg0 : !tt.ptr<bf16> -> tensor<1x2048x!tt.ptr<bf16>> loc(#loc32)
+      %14 = tt.addptr %13, %12 : tensor<1x2048x!tt.ptr<bf16>>, tensor<1x2048xi32> loc(#loc32)
+      %15 = tt.splat %1 : i1 -> tensor<1x2048xi1> loc(#loc57)
+      %16 = arith.andi %9, %15 : tensor<1x2048xi1> loc(#loc33)
+      %17 = tt.load %14, %16, %cst evictionPolicy = evict_first : tensor<1x2048x!tt.ptr<bf16>> loc(#loc34)
+      %18 = arith.extf %17 : tensor<1x2048xbf16> to tensor<1x2048xf32> loc(#loc35)
+      %19 = tt.splat %arg1 : !tt.ptr<bf16> -> tensor<1x2048x!tt.ptr<bf16>> loc(#loc36)
+      %20 = tt.addptr %19, %12 : tensor<1x2048x!tt.ptr<bf16>>, tensor<1x2048xi32> loc(#loc36)
+      %21 = tt.load %20, %16, %cst evictionPolicy = evict_first : tensor<1x2048x!tt.ptr<bf16>> loc(#loc37)
+      %22 = arith.extf %21 : tensor<1x2048xbf16> to tensor<1x2048xf32> loc(#loc38)
+      %23 = tt.splat %arg2 : !tt.ptr<bf16> -> tensor<1x2048x!tt.ptr<bf16>> loc(#loc39)
+      %24 = tt.addptr %23, %8 : tensor<1x2048x!tt.ptr<bf16>>, tensor<1x2048xi32> loc(#loc39)
+      %25 = tt.load %24, %9, %cst evictionPolicy = evict_last : tensor<1x2048x!tt.ptr<bf16>> loc(#loc40)
+      %26 = arith.extf %25 : tensor<1x2048xbf16> to tensor<1x2048xf32> loc(#loc41)
+      %27 = arith.addf %18, %22 : tensor<1x2048xf32> loc(#loc42)
+      %28 = arith.divf %6, %cst_1 : tensor<1x1xf32> loc(#loc43)
+      %29 = arith.addf %28, %cst_0 : tensor<1x1xf32> loc(#loc44)
+      %30 = tt.extern_elementwise %29 {libname = "", libpath = "", pure = true, symbol = "__nv_rsqrtf"} : (tensor<1x1xf32>) -> tensor<1x1xf32> loc(#loc45)
+      %31 = tt.broadcast %30 : tensor<1x1xf32> -> tensor<1x2048xf32> loc(#loc46)
+      %32 = arith.mulf %27, %31 : tensor<1x2048xf32> loc(#loc46)
+      %33 = arith.mulf %32, %26 : tensor<1x2048xf32> loc(#loc47)
+      %34 = tt.splat %arg3 : !tt.ptr<bf16> -> tensor<1x2048x!tt.ptr<bf16>> loc(#loc48)
+      %35 = tt.addptr %34, %12 : tensor<1x2048x!tt.ptr<bf16>>, tensor<1x2048xi32> loc(#loc48)
+      %36 = arith.truncf %33 : tensor<1x2048xf32> to tensor<1x2048xbf16> loc(#loc49)
+      tt.store %35, %36, %16 : tensor<1x2048x!tt.ptr<bf16>> loc(#loc49)
+    } loc(#loc27)
+    tt.return loc(#loc50)
+  } loc(#loc)
+} loc(#loc)
+#loc2 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":22:28)
+#loc3 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":24:21)
+#loc4 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":25:27)
+#loc5 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":25:37)
+#loc6 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":29:40)
+#loc7 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":30:31)
+#loc8 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":31:29)
+#loc9 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":35:46)
+#loc10 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":35:41)
+#loc11 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":35:34)
+#loc12 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":35:61)
+#loc13 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":35:51)
+#loc14 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":35:112)
+#loc15 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":36:34)
+#loc16 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":36:51)
+#loc17 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":36:112)
+#loc18 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":39:22)
+#loc19 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":40:22)
+#loc20 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":42:23)
+#loc21 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":43:48)
+#loc22 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":43:8)
+#loc23 = loc("/home/x/.local/lib/python3.12/site-packages/triton/language/standard.py":286:36)
+#loc25 = loc("/home/x/.local/lib/python3.12/site-packages/triton/language/standard.py":256:15)
+#loc26 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":44:28)
+#loc27 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":45:40)
+#loc28 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":46:31)
+#loc29 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":47:29)
+#loc30 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":51:46)
+#loc31 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":51:41)
+#loc32 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":51:34)
+#loc33 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":51:61)
+#loc34 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":51:51)
+#loc35 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":51:113)
+#loc36 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":52:35)
+#loc37 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":52:52)
+#loc38 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":52:114)
+#loc39 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":53:35)
+#loc40 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":53:42)
+#loc41 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":53:95)
+#loc42 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":56:24)
+#loc43 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":58:24)
+#loc44 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":60:24)
+#loc45 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":61:32)
+#loc46 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":62:24)
+#loc47 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":64:24)
+#loc48 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":65:29)
+#loc49 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":65:53)
+#loc50 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/pw/cpwpvywcxi3pfee3hihkhgruiudxch5x5fjmrfni32pbrohqnjnc.py":45:4)
+#loc51 = loc(fused[#loc10, #loc9])
+#loc52 = loc(fused[#loc12, #loc3])
+#loc53 = loc(callsite(#loc23 at #loc24))
+#loc55 = loc(callsite(#loc25 at #loc23))
+#loc56 = loc(fused[#loc31, #loc30])
+#loc57 = loc(fused[#loc33, #loc3])
+#loc58 = loc(callsite(#loc55 at #loc24))

platform/aiml/models/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/triton_cache/BYJOQAU3AABYVRHMFUFDBINMWKEVL4QD43PIQ4TTQIYQCLHUG7GQ/__grp__triton_poi_fused_cat_1.json

@@ -0,0 +1 @@
+{"child_paths": {"triton_poi_fused_cat_1.ttir": "/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/triton_cache/BYJOQAU3AABYVRHMFUFDBINMWKEVL4QD43PIQ4TTQIYQCLHUG7GQ/triton_poi_fused_cat_1.ttir", "triton_poi_fused_cat_1.ttgir": "/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/triton_cache/BYJOQAU3AABYVRHMFUFDBINMWKEVL4QD43PIQ4TTQIYQCLHUG7GQ/triton_poi_fused_cat_1.ttgir", "triton_poi_fused_cat_1.llir": "/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/triton_cache/BYJOQAU3AABYVRHMFUFDBINMWKEVL4QD43PIQ4TTQIYQCLHUG7GQ/triton_poi_fused_cat_1.llir", "triton_poi_fused_cat_1.ptx": "/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/triton_cache/BYJOQAU3AABYVRHMFUFDBINMWKEVL4QD43PIQ4TTQIYQCLHUG7GQ/triton_poi_fused_cat_1.ptx", "triton_poi_fused_cat_1.cubin": "/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/triton_cache/BYJOQAU3AABYVRHMFUFDBINMWKEVL4QD43PIQ4TTQIYQCLHUG7GQ/triton_poi_fused_cat_1.cubin", "triton_poi_fused_cat_1.json": "/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/triton_cache/BYJOQAU3AABYVRHMFUFDBINMWKEVL4QD43PIQ4TTQIYQCLHUG7GQ/triton_poi_fused_cat_1.json"}}

platform/aiml/models/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/triton_cache/BYJOQAU3AABYVRHMFUFDBINMWKEVL4QD43PIQ4TTQIYQCLHUG7GQ/triton_poi_fused_cat_1.llir

@@ -0,0 +1,356 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+target datalayout = "e-p3:32:32-p4:32:32-p5:32:32-p6:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64"
+
+@assertFunc_1 = internal constant [8 x i8] c"unknown\00"
+@assertFile_1 = internal constant [134 x i8] c"/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py\00"
+@assertMessage_1 = internal constant [68 x i8] c"index out of bounds: 0 <= tl.broadcast_to(tmp28, [XBLOCK]) < 131072\00"
+@assertFunc_0 = internal constant [8 x i8] c"unknown\00"
+@assertFile_0 = internal constant [134 x i8] c"/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py\00"
+@assertMessage_0 = internal constant [68 x i8] c"index out of bounds: 0 <= tl.broadcast_to(tmp10, [XBLOCK]) < 131072\00"
+
+; Function Attrs: noreturn
+declare !dbg !6 void @__assertfail(ptr, ptr, i32, ptr, i64) local_unnamed_addr #0
+
+define ptx_kernel void @triton_poi_fused_cat_1(ptr addrspace(1) %0, ptr addrspace(1) %1, ptr addrspace(1) %2, ptr addrspace(1) %3, i32 %4, ptr addrspace(1) readnone captures(none) %5) local_unnamed_addr !dbg !10 {
+  %7 = tail call i32 @llvm.nvvm.read.ptx.sreg.ctaid.x(), !dbg !11
+  %8 = shl i32 %7, 10, !dbg !12
+  %9 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !13
+  %10 = shl i32 %9, 3, !dbg !13
+  %11 = and i32 %10, 1016, !dbg !13
+  %12 = or disjoint i32 %11, %8, !dbg !14
+  %13 = icmp slt i32 %12, %4, !dbg !15
+  %14 = sdiv i32 %12, 128, !dbg !16
+  %15 = mul i32 %14, 128, !dbg !17
+  %.decomposed = sub i32 %12, %15, !dbg !17
+  %16 = srem i32 %14, 28, !dbg !18
+  %17 = sdiv i32 %12, 3584, !dbg !19
+  %18 = icmp slt i32 %.decomposed, 64, !dbg !20
+  %19 = shl nsw i32 %16, 7, !dbg !21
+  %20 = mul i32 %17, 4608, !dbg !22
+  %21 = add i32 %19, %20, !dbg !23
+  %22 = add i32 %21, %.decomposed, !dbg !24
+  %23 = sext i32 %22 to i64, !dbg !25
+  %24 = getelementptr bfloat, ptr addrspace(1) %0, i64 %23, !dbg !25
+  %25 = and i1 %18, %13, !dbg !26
+  %26 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, $4;\0A\09mov.u32 $1, $5;\0A\09mov.u32 $2, $6;\0A\09mov.u32 $3, $7;\0A\09@$9 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $8 + 0 ];", "=r,=r,=r,=r,r,r,r,r,l,b"(i32 0, i32 0, i32 0, i32 0, ptr addrspace(1) %24, i1 %25) #3, !dbg !27
+  %27 = sext i32 %17 to i64, !dbg !28
+  %28 = getelementptr i64, ptr addrspace(1) %1, i64 %27, !dbg !28
+  %29 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %28, i1 %25) #3, !dbg !29
+  %30 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %28, i1 %25) #3, !dbg !29
+  %31 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %28, i1 %25) #3, !dbg !29
+  %32 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %28, i1 %25) #3, !dbg !29
+  %33 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %28, i1 %25) #3, !dbg !29
+  %34 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %28, i1 %25) #3, !dbg !29
+  %35 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %28, i1 %25) #3, !dbg !29
+  %36 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %28, i1 %25) #3, !dbg !29
+  %37 = lshr i64 %29, 46, !dbg !30
+  %38 = and i64 %37, 131072, !dbg !30
+  %39 = add i64 %38, %29, !dbg !30
+  %40 = icmp ugt i64 %39, 131071, !dbg !31
+  %.not1 = and i1 %25, %40, !dbg !32
+  br i1 %.not1, label %41, label %42, !dbg !32
+
+41:                                               ; preds = %6
+  tail call void @__assertfail(ptr nonnull @assertMessage_0, ptr nonnull @assertFile_0, i32 37, ptr nonnull @assertFunc_0, i64 1), !dbg !32
+  unreachable, !dbg !32
+
+42:                                               ; preds = %6
+  %43 = sext i32 %.decomposed to i64, !dbg !20
+  tail call void @llvm.nvvm.barrier0(), !dbg !32
+  %44 = shl i64 %39, 7, !dbg !33
+  %45 = getelementptr bfloat, ptr addrspace(1) %2, i64 %44, !dbg !34
+  %46 = getelementptr bfloat, ptr addrspace(1) %45, i64 %43, !dbg !34
+  %47 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, $4;\0A\09mov.u32 $1, $5;\0A\09mov.u32 $2, $6;\0A\09mov.u32 $3, $7;\0A\09@$9 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $8 + 0 ];", "=r,=r,=r,=r,r,r,r,r,l,b"(i32 0, i32 0, i32 0, i32 0, ptr addrspace(1) %46, i1 %25) #3, !dbg !35
+  %48 = or disjoint i32 %19, 64, !dbg !36
+  %49 = add i32 %48, %20, !dbg !37
+  %50 = add i32 %49, %.decomposed, !dbg !38
+  %51 = sext i32 %50 to i64, !dbg !39
+  %52 = getelementptr bfloat, ptr addrspace(1) %0, i64 %51, !dbg !39
+  %53 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, $4;\0A\09mov.u32 $1, $5;\0A\09mov.u32 $2, $6;\0A\09mov.u32 $3, $7;\0A\09@$9 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $8 + 0 ];", "=r,=r,=r,=r,r,r,r,r,l,b"(i32 0, i32 0, i32 0, i32 0, ptr addrspace(1) %52, i1 %25) #3, !dbg !40
+  %54 = or disjoint i64 %44, 64, !dbg !41
+  %55 = getelementptr bfloat, ptr addrspace(1) %2, i64 %54, !dbg !42
+  %56 = getelementptr bfloat, ptr addrspace(1) %55, i64 %43, !dbg !42
+  %57 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, $4;\0A\09mov.u32 $1, $5;\0A\09mov.u32 $2, $6;\0A\09mov.u32 $3, $7;\0A\09@$9 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $8 + 0 ];", "=r,=r,=r,=r,r,r,r,r,l,b"(i32 0, i32 0, i32 0, i32 0, ptr addrspace(1) %56, i1 %25) #3, !dbg !43
+  %58 = icmp sgt i32 %.decomposed, 63, !dbg !44
+  %59 = add nsw i32 %.decomposed, -64, !dbg !45
+  %60 = add i32 %49, %59, !dbg !46
+  %61 = sext i32 %60 to i64, !dbg !47
+  %62 = getelementptr bfloat, ptr addrspace(1) %0, i64 %61, !dbg !47
+  %63 = and i1 %58, %13, !dbg !48
+  %64 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, $4;\0A\09mov.u32 $1, $5;\0A\09mov.u32 $2, $6;\0A\09mov.u32 $3, $7;\0A\09@$9 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $8 + 0 ];", "=r,=r,=r,=r,r,r,r,r,l,b"(i32 0, i32 0, i32 0, i32 0, ptr addrspace(1) %62, i1 %63) #3, !dbg !49
+  %65 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %28, i1 %63) #3, !dbg !50
+  %66 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %28, i1 %63) #3, !dbg !50
+  %67 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %28, i1 %63) #3, !dbg !50
+  %68 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %28, i1 %63) #3, !dbg !50
+  %69 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %28, i1 %63) #3, !dbg !50
+  %70 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %28, i1 %63) #3, !dbg !50
+  %71 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %28, i1 %63) #3, !dbg !50
+  %72 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %28, i1 %63) #3, !dbg !50
+  %73 = lshr i64 %65, 46, !dbg !51
+  %74 = and i64 %73, 131072, !dbg !51
+  %75 = add i64 %74, %65, !dbg !51
+  %76 = icmp ugt i64 %75, 131071, !dbg !52
+  %.not2 = and i1 %63, %76, !dbg !53
+  br i1 %.not2, label %77, label %78, !dbg !53
+
+77:                                               ; preds = %42
+  tail call void @__assertfail(ptr nonnull @assertMessage_1, ptr nonnull @assertFile_1, i32 55, ptr nonnull @assertFunc_1, i64 1), !dbg !53
+  unreachable, !dbg !53
+
+78:                                               ; preds = %42
+  %79 = extractvalue { i32, i32, i32, i32 } %64, 3, !dbg !49
+  %80 = bitcast i32 %79 to <2 x bfloat>, !dbg !49
+  %81 = extractvalue { i32, i32, i32, i32 } %64, 2, !dbg !49
+  %82 = bitcast i32 %81 to <2 x bfloat>, !dbg !49
+  %83 = extractvalue { i32, i32, i32, i32 } %64, 1, !dbg !49
+  %84 = bitcast i32 %83 to <2 x bfloat>, !dbg !49
+  %85 = extractvalue { i32, i32, i32, i32 } %64, 0, !dbg !49
+  %86 = bitcast i32 %85 to <2 x bfloat>, !dbg !49
+  %87 = extractvalue { i32, i32, i32, i32 } %26, 3, !dbg !27
+  %88 = bitcast i32 %87 to <2 x bfloat>, !dbg !27
+  %89 = extractvalue { i32, i32, i32, i32 } %47, 3, !dbg !35
+  %90 = bitcast i32 %89 to <2 x bfloat>, !dbg !35
+  %91 = extractvalue { i32, i32, i32, i32 } %53, 3, !dbg !40
+  %92 = bitcast i32 %91 to <2 x bfloat>, !dbg !40
+  %93 = extractvalue { i32, i32, i32, i32 } %57, 3, !dbg !43
+  %94 = bitcast i32 %93 to <2 x bfloat>, !dbg !43
+  %95 = extractvalue { i32, i32, i32, i32 } %26, 2, !dbg !27
+  %96 = bitcast i32 %95 to <2 x bfloat>, !dbg !27
+  %97 = extractvalue { i32, i32, i32, i32 } %47, 2, !dbg !35
+  %98 = bitcast i32 %97 to <2 x bfloat>, !dbg !35
+  %99 = extractvalue { i32, i32, i32, i32 } %53, 2, !dbg !40
+  %100 = bitcast i32 %99 to <2 x bfloat>, !dbg !40
+  %101 = extractvalue { i32, i32, i32, i32 } %57, 2, !dbg !43
+  %102 = bitcast i32 %101 to <2 x bfloat>, !dbg !43
+  %103 = extractvalue { i32, i32, i32, i32 } %26, 1, !dbg !27
+  %104 = bitcast i32 %103 to <2 x bfloat>, !dbg !27
+  %105 = extractvalue { i32, i32, i32, i32 } %47, 1, !dbg !35
+  %106 = bitcast i32 %105 to <2 x bfloat>, !dbg !35
+  %107 = extractvalue { i32, i32, i32, i32 } %53, 1, !dbg !40
+  %108 = bitcast i32 %107 to <2 x bfloat>, !dbg !40
+  %109 = extractvalue { i32, i32, i32, i32 } %57, 1, !dbg !43
+  %110 = bitcast i32 %109 to <2 x bfloat>, !dbg !43
+  %111 = extractvalue { i32, i32, i32, i32 } %26, 0, !dbg !27
+  %112 = bitcast i32 %111 to <2 x bfloat>, !dbg !27
+  %113 = extractvalue { i32, i32, i32, i32 } %47, 0, !dbg !35
+  %114 = bitcast i32 %113 to <2 x bfloat>, !dbg !35
+  %115 = extractvalue { i32, i32, i32, i32 } %53, 0, !dbg !40
+  %116 = bitcast i32 %115 to <2 x bfloat>, !dbg !40
+  %117 = extractvalue { i32, i32, i32, i32 } %57, 0, !dbg !43
+  %118 = bitcast i32 %117 to <2 x bfloat>, !dbg !43
+  tail call void @llvm.nvvm.barrier0(), !dbg !53
+  %119 = shl i64 %75, 7, !dbg !54
+  %120 = sext i32 %59 to i64, !dbg !55
+  %121 = getelementptr bfloat, ptr addrspace(1) %2, i64 %119, !dbg !56
+  %122 = getelementptr bfloat, ptr addrspace(1) %121, i64 %120, !dbg !56
+  %123 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, $4;\0A\09mov.u32 $1, $5;\0A\09mov.u32 $2, $6;\0A\09mov.u32 $3, $7;\0A\09@$9 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $8 + 0 ];", "=r,=r,=r,=r,r,r,r,r,l,b"(i32 0, i32 0, i32 0, i32 0, ptr addrspace(1) %122, i1 %63) #3, !dbg !57
+  %124 = extractvalue { i32, i32, i32, i32 } %123, 0, !dbg !57
+  %125 = bitcast i32 %124 to <2 x bfloat>, !dbg !57
+  %126 = extractvalue { i32, i32, i32, i32 } %123, 1, !dbg !57
+  %127 = bitcast i32 %126 to <2 x bfloat>, !dbg !57
+  %128 = extractvalue { i32, i32, i32, i32 } %123, 2, !dbg !57
+  %129 = bitcast i32 %128 to <2 x bfloat>, !dbg !57
+  %130 = extractvalue { i32, i32, i32, i32 } %123, 3, !dbg !57
+  %131 = bitcast i32 %130 to <2 x bfloat>, !dbg !57
+  %132 = add i32 %21, %59, !dbg !58
+  %133 = sext i32 %132 to i64, !dbg !59
+  %134 = getelementptr bfloat, ptr addrspace(1) %0, i64 %133, !dbg !59
+  %135 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, $4;\0A\09mov.u32 $1, $5;\0A\09mov.u32 $2, $6;\0A\09mov.u32 $3, $7;\0A\09@$9 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $8 + 0 ];", "=r,=r,=r,=r,r,r,r,r,l,b"(i32 0, i32 0, i32 0, i32 0, ptr addrspace(1) %134, i1 %63) #3, !dbg !60
+  %136 = extractvalue { i32, i32, i32, i32 } %135, 0, !dbg !60
+  %137 = bitcast i32 %136 to <2 x bfloat>, !dbg !60
+  %138 = extractvalue { i32, i32, i32, i32 } %135, 1, !dbg !60
+  %139 = bitcast i32 %138 to <2 x bfloat>, !dbg !60
+  %140 = extractvalue { i32, i32, i32, i32 } %135, 2, !dbg !60
+  %141 = bitcast i32 %140 to <2 x bfloat>, !dbg !60
+  %142 = extractvalue { i32, i32, i32, i32 } %135, 3, !dbg !60
+  %143 = bitcast i32 %142 to <2 x bfloat>, !dbg !60
+  %144 = or disjoint i64 %119, 64, !dbg !61
+  %145 = getelementptr bfloat, ptr addrspace(1) %2, i64 %144, !dbg !62
+  %146 = getelementptr bfloat, ptr addrspace(1) %145, i64 %120, !dbg !62
+  %147 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, $4;\0A\09mov.u32 $1, $5;\0A\09mov.u32 $2, $6;\0A\09mov.u32 $3, $7;\0A\09@$9 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $8 + 0 ];", "=r,=r,=r,=r,r,r,r,r,l,b"(i32 0, i32 0, i32 0, i32 0, ptr addrspace(1) %146, i1 %63) #3, !dbg !63
+  %148 = extractvalue { i32, i32, i32, i32 } %147, 0, !dbg !63
+  %149 = bitcast i32 %148 to <2 x bfloat>, !dbg !63
+  %150 = extractvalue { i32, i32, i32, i32 } %147, 1, !dbg !63
+  %151 = bitcast i32 %150 to <2 x bfloat>, !dbg !63
+  %152 = extractvalue { i32, i32, i32, i32 } %147, 2, !dbg !63
+  %153 = bitcast i32 %152 to <2 x bfloat>, !dbg !63
+  %154 = extractvalue { i32, i32, i32, i32 } %147, 3, !dbg !63
+  %155 = bitcast i32 %154 to <2 x bfloat>, !dbg !63
+  %156 = sext i32 %12 to i64, !dbg !64
+  %157 = getelementptr bfloat, ptr addrspace(1) %3, i64 %156, !dbg !64
+  %158 = fpext <2 x bfloat> %86 to <2 x float>, !dbg !65
+  %159 = fpext <2 x bfloat> %112 to <2 x float>, !dbg !66
+  %160 = fpext <2 x bfloat> %114 to <2 x float>, !dbg !67
+  %161 = fmul <2 x float> %159, %160, !dbg !68
+  %162 = fpext <2 x bfloat> %116 to <2 x float>, !dbg !69
+  %163 = fpext <2 x bfloat> %118 to <2 x float>, !dbg !70
+  %164 = fmul <2 x float> %162, %163, !dbg !71
+  %165 = fsub <2 x float> %161, %164, !dbg !72
+  %166 = fpext <2 x bfloat> %125 to <2 x float>, !dbg !73
+  %167 = fmul <2 x float> %158, %166, !dbg !74
+  %168 = fpext <2 x bfloat> %137 to <2 x float>, !dbg !75
+  %169 = fpext <2 x bfloat> %149 to <2 x float>, !dbg !76
+  %170 = fmul <2 x float> %168, %169, !dbg !77
+  %171 = fadd <2 x float> %167, %170, !dbg !78
+  %172 = insertelement <2 x i1> poison, i1 %18, i64 0, !dbg !79
+  %173 = shufflevector <2 x i1> %172, <2 x i1> poison, <2 x i32> zeroinitializer, !dbg !79
+  %174 = select <2 x i1> %173, <2 x float> %165, <2 x float> %171, !dbg !79
+  %175 = fptrunc <2 x float> %174 to <2 x bfloat>, !dbg !80
+  %176 = fpext <2 x bfloat> %84 to <2 x float>, !dbg !65
+  %177 = fpext <2 x bfloat> %104 to <2 x float>, !dbg !66
+  %178 = fpext <2 x bfloat> %106 to <2 x float>, !dbg !67
+  %179 = fmul <2 x float> %177, %178, !dbg !68
+  %180 = fpext <2 x bfloat> %108 to <2 x float>, !dbg !69
+  %181 = fpext <2 x bfloat> %110 to <2 x float>, !dbg !70
+  %182 = fmul <2 x float> %180, %181, !dbg !71
+  %183 = fsub <2 x float> %179, %182, !dbg !72
+  %184 = fpext <2 x bfloat> %127 to <2 x float>, !dbg !73
+  %185 = fmul <2 x float> %176, %184, !dbg !74
+  %186 = fpext <2 x bfloat> %139 to <2 x float>, !dbg !75
+  %187 = fpext <2 x bfloat> %151 to <2 x float>, !dbg !76
+  %188 = fmul <2 x float> %186, %187, !dbg !77
+  %189 = fadd <2 x float> %185, %188, !dbg !78
+  %190 = select <2 x i1> %173, <2 x float> %183, <2 x float> %189, !dbg !79
+  %191 = fptrunc <2 x float> %190 to <2 x bfloat>, !dbg !80
+  %192 = fpext <2 x bfloat> %82 to <2 x float>, !dbg !65
+  %193 = fpext <2 x bfloat> %96 to <2 x float>, !dbg !66
+  %194 = fpext <2 x bfloat> %98 to <2 x float>, !dbg !67
+  %195 = fmul <2 x float> %193, %194, !dbg !68
+  %196 = fpext <2 x bfloat> %100 to <2 x float>, !dbg !69
+  %197 = fpext <2 x bfloat> %102 to <2 x float>, !dbg !70
+  %198 = fmul <2 x float> %196, %197, !dbg !71
+  %199 = fsub <2 x float> %195, %198, !dbg !72
+  %200 = fpext <2 x bfloat> %129 to <2 x float>, !dbg !73
+  %201 = fmul <2 x float> %192, %200, !dbg !74
+  %202 = fpext <2 x bfloat> %141 to <2 x float>, !dbg !75
+  %203 = fpext <2 x bfloat> %153 to <2 x float>, !dbg !76
+  %204 = fmul <2 x float> %202, %203, !dbg !77
+  %205 = fadd <2 x float> %201, %204, !dbg !78
+  %206 = select <2 x i1> %173, <2 x float> %199, <2 x float> %205, !dbg !79
+  %207 = fptrunc <2 x float> %206 to <2 x bfloat>, !dbg !80
+  %208 = fpext <2 x bfloat> %80 to <2 x float>, !dbg !65
+  %209 = fpext <2 x bfloat> %88 to <2 x float>, !dbg !66
+  %210 = fpext <2 x bfloat> %90 to <2 x float>, !dbg !67
+  %211 = fmul <2 x float> %209, %210, !dbg !68
+  %212 = fpext <2 x bfloat> %92 to <2 x float>, !dbg !69
+  %213 = fpext <2 x bfloat> %94 to <2 x float>, !dbg !70
+  %214 = fmul <2 x float> %212, %213, !dbg !71
+  %215 = fsub <2 x float> %211, %214, !dbg !72
+  %216 = fpext <2 x bfloat> %131 to <2 x float>, !dbg !73
+  %217 = fmul <2 x float> %208, %216, !dbg !74
+  %218 = fpext <2 x bfloat> %143 to <2 x float>, !dbg !75
+  %219 = fpext <2 x bfloat> %155 to <2 x float>, !dbg !76
+  %220 = fmul <2 x float> %218, %219, !dbg !77
+  %221 = fadd <2 x float> %217, %220, !dbg !78
+  %222 = select <2 x i1> %173, <2 x float> %215, <2 x float> %221, !dbg !79
+  %223 = fptrunc <2 x float> %222 to <2 x bfloat>, !dbg !80
+  %224 = bitcast <2 x bfloat> %175 to i32, !dbg !80
+  %225 = bitcast <2 x bfloat> %191 to i32, !dbg !80
+  %226 = bitcast <2 x bfloat> %207 to i32, !dbg !80
+  %227 = bitcast <2 x bfloat> %223 to i32, !dbg !80
+  tail call void asm sideeffect "@$5 st.global.v4.b32 [ $4 + 0 ], { $0, $1, $2, $3 };", "r,r,r,r,l,b"(i32 %224, i32 %225, i32 %226, i32 %227, ptr addrspace(1) %157, i1 %13) #3, !dbg !80
+  ret void, !dbg !81
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.ctaid.x() #1
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.x() #1
+
+; Function Attrs: convergent nocallback nounwind
+declare void @llvm.nvvm.barrier0() #2
+
+attributes #0 = { noreturn }
+attributes #1 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #2 = { convergent nocallback nounwind }
+attributes #3 = { nounwind }
+
+!llvm.module.flags = !{!0, !1}
+!llvm.dbg.cu = !{!2}
+!nvvm.annotations = !{!4}
+!llvm.ident = !{!5}
+
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = !{i32 4, !"nvvm-reflect-ftz", i32 1}
+!2 = distinct !DICompileUnit(language: DW_LANG_C, file: !3, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: LineTablesOnly)
+!3 = !DIFile(filename: "czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py", directory: "/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm")
+!4 = !{ptr @triton_poi_fused_cat_1, !"reqntidx", i32 128}
+!5 = !{!"clang version 3.8.0 (tags/RELEASE_380/final)"}
+!6 = !DISubprogram(name: "__assertfail", linkageName: "__assertfail", scope: !7, file: !7, type: !8, spFlags: DISPFlagOptimized)
+!7 = !DIFile(filename: "<unknown>", directory: "")
+!8 = !DISubroutineType(cc: DW_CC_normal, types: !9)
+!9 = !{}
+!10 = distinct !DISubprogram(name: "triton_poi_fused_cat_1", linkageName: "triton_poi_fused_cat_1", scope: !3, file: !3, line: 18, type: !8, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !2)
+!11 = !DILocation(line: 19, column: 28, scope: !10)
+!12 = !DILocation(line: 19, column: 33, scope: !10)
+!13 = !DILocation(line: 20, column: 36, scope: !10)
+!14 = !DILocation(line: 20, column: 23, scope: !10)
+!15 = !DILocation(line: 21, column: 21, scope: !10)
+!16 = !DILocation(line: 23, column: 21, scope: !10)
+!17 = !DILocation(line: 22, column: 19, scope: !10)
+!18 = !DILocation(line: 23, column: 28, scope: !10)
+!19 = !DILocation(line: 24, column: 19, scope: !10)
+!20 = !DILocation(line: 30, column: 18, scope: !10)
+!21 = !DILocation(line: 31, column: 34, scope: !10)
+!22 = !DILocation(line: 31, column: 44, scope: !10)
+!23 = !DILocation(line: 31, column: 39, scope: !10)
+!24 = !DILocation(line: 31, column: 50, scope: !10)
+!25 = !DILocation(line: 31, column: 30, scope: !10)
+!26 = !DILocation(line: 31, column: 64, scope: !10)
+!27 = !DILocation(line: 31, column: 56, scope: !10)
+!28 = !DILocation(line: 32, column: 30, scope: !10)
+!29 = !DILocation(line: 32, column: 35, scope: !10)
+!30 = !DILocation(line: 36, column: 33, scope: !10)
+!31 = !DILocation(line: 37, column: 65, scope: !10)
+!32 = !DILocation(line: 37, column: 128, scope: !10)
+!33 = !DILocation(line: 38, column: 35, scope: !10)
+!34 = !DILocation(line: 38, column: 31, scope: !10)
+!35 = !DILocation(line: 38, column: 50, scope: !10)
+!36 = !DILocation(line: 40, column: 36, scope: !10)
+!37 = !DILocation(line: 40, column: 45, scope: !10)
+!38 = !DILocation(line: 40, column: 56, scope: !10)
+!39 = !DILocation(line: 40, column: 31, scope: !10)
+!40 = !DILocation(line: 40, column: 62, scope: !10)
+!41 = !DILocation(line: 41, column: 36, scope: !10)
+!42 = !DILocation(line: 41, column: 31, scope: !10)
+!43 = !DILocation(line: 41, column: 55, scope: !10)
+!44 = !DILocation(line: 46, column: 20, scope: !10)
+!45 = !DILocation(line: 49, column: 64, scope: !10)
+!46 = !DILocation(line: 49, column: 56, scope: !10)
+!47 = !DILocation(line: 49, column: 31, scope: !10)
+!48 = !DILocation(line: 49, column: 78, scope: !10)
+!49 = !DILocation(line: 49, column: 70, scope: !10)
+!50 = !DILocation(line: 50, column: 36, scope: !10)
+!51 = !DILocation(line: 54, column: 35, scope: !10)
+!52 = !DILocation(line: 55, column: 65, scope: !10)
+!53 = !DILocation(line: 55, column: 129, scope: !10)
+!54 = !DILocation(line: 56, column: 35, scope: !10)
+!55 = !DILocation(line: 56, column: 44, scope: !10)
+!56 = !DILocation(line: 56, column: 31, scope: !10)
+!57 = !DILocation(line: 56, column: 58, scope: !10)
+!58 = !DILocation(line: 58, column: 51, scope: !10)
+!59 = !DILocation(line: 58, column: 31, scope: !10)
+!60 = !DILocation(line: 58, column: 65, scope: !10)
+!61 = !DILocation(line: 59, column: 36, scope: !10)
+!62 = !DILocation(line: 59, column: 31, scope: !10)
+!63 = !DILocation(line: 59, column: 63, scope: !10)
+!64 = !DILocation(line: 65, column: 25, scope: !10)
+!65 = !DILocation(line: 49, column: 129, scope: !10)
+!66 = !DILocation(line: 31, column: 114, scope: !10)
+!67 = !DILocation(line: 38, column: 108, scope: !10)
+!68 = !DILocation(line: 39, column: 19, scope: !10)
+!69 = !DILocation(line: 40, column: 120, scope: !10)
+!70 = !DILocation(line: 41, column: 113, scope: !10)
+!71 = !DILocation(line: 42, column: 20, scope: !10)
+!72 = !DILocation(line: 43, column: 20, scope: !10)
+!73 = !DILocation(line: 56, column: 117, scope: !10)
+!74 = !DILocation(line: 57, column: 20, scope: !10)
+!75 = !DILocation(line: 58, column: 124, scope: !10)
+!76 = !DILocation(line: 59, column: 122, scope: !10)
+!77 = !DILocation(line: 60, column: 20, scope: !10)
+!78 = !DILocation(line: 61, column: 20, scope: !10)
+!79 = !DILocation(line: 0, scope: !10)
+!80 = !DILocation(line: 65, column: 37, scope: !10)
+!81 = !DILocation(line: 65, column: 4, scope: !10)

platform/aiml/models/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/triton_cache/BYJOQAU3AABYVRHMFUFDBINMWKEVL4QD43PIQ4TTQIYQCLHUG7GQ/triton_poi_fused_cat_1.ttgir

@@ -0,0 +1,206 @@
+#blocked = #ttg.blocked<{sizePerThread = [8], threadsPerWarp = [32], warpsPerCTA = [4], order = [0]}>
+#loc = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":18:0)
+module attributes {"ttg.num-ctas" = 1 : i32, "ttg.num-warps" = 4 : i32, ttg.target = "cuda:90", "ttg.threads-per-warp" = 32 : i32} {
+  tt.func public @triton_poi_fused_cat_1(%arg0: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":18:0), %arg1: !tt.ptr<i64> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":18:0), %arg2: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":18:0), %arg3: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":18:0), %arg4: i32 {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":18:0)) attributes {noinline = false} {
+    %cst = arith.constant dense<64> : tensor<1024xi64, #blocked> loc(#loc1)
+    %cst_0 = arith.constant dense<0.000000e+00> : tensor<1024xf32, #blocked> loc(#loc1)
+    %cst_1 = arith.constant dense<128> : tensor<1024xi64, #blocked> loc(#loc1)
+    %cst_2 = arith.constant dense<0> : tensor<1024xi64, #blocked> loc(#loc1)
+    %cst_3 = arith.constant dense<131072> : tensor<1024xi64, #blocked> loc(#loc1)
+    %cst_4 = arith.constant dense<0.000000e+00> : tensor<1024xbf16, #blocked> loc(#loc1)
+    %c1024_i32 = arith.constant 1024 : i32 loc(#loc1)
+    %cst_5 = arith.constant dense<128> : tensor<1024xi32, #blocked> loc(#loc1)
+    %cst_6 = arith.constant dense<28> : tensor<1024xi32, #blocked> loc(#loc1)
+    %cst_7 = arith.constant dense<3584> : tensor<1024xi32, #blocked> loc(#loc1)
+    %cst_8 = arith.constant dense<4608> : tensor<1024xi32, #blocked> loc(#loc1)
+    %cst_9 = arith.constant dense<true> : tensor<1024xi1, #blocked> loc(#loc1)
+    %cst_10 = arith.constant dense<64> : tensor<1024xi32, #blocked> loc(#loc1)
+    %cst_11 = arith.constant dense<-64> : tensor<1024xi32, #blocked> loc(#loc1)
+    %0 = tt.get_program_id x : i32 loc(#loc2)
+    %1 = arith.muli %0, %c1024_i32 : i32 loc(#loc3)
+    %2 = tt.make_range {end = 1024 : i32, start = 0 : i32} : tensor<1024xi32, #blocked> loc(#loc4)
+    %3 = tt.splat %1 : i32 -> tensor<1024xi32, #blocked> loc(#loc5)
+    %4 = arith.addi %3, %2 : tensor<1024xi32, #blocked> loc(#loc5)
+    %5 = tt.splat %arg4 : i32 -> tensor<1024xi32, #blocked> loc(#loc6)
+    %6 = arith.cmpi slt, %4, %5 : tensor<1024xi32, #blocked> loc(#loc6)
+    %7 = arith.remsi %4, %cst_5 : tensor<1024xi32, #blocked> loc(#loc7)
+    %8 = arith.divsi %4, %cst_5 : tensor<1024xi32, #blocked> loc(#loc8)
+    %9 = arith.remsi %8, %cst_6 : tensor<1024xi32, #blocked> loc(#loc9)
+    %10 = arith.divsi %4, %cst_7 : tensor<1024xi32, #blocked> loc(#loc10)
+    %11 = arith.extsi %7 : tensor<1024xi32, #blocked> to tensor<1024xi64, #blocked> loc(#loc11)
+    %12 = arith.cmpi slt, %11, %cst : tensor<1024xi64, #blocked> loc(#loc11)
+    %13 = arith.muli %9, %cst_5 : tensor<1024xi32, #blocked> loc(#loc12)
+    %14 = arith.muli %10, %cst_8 : tensor<1024xi32, #blocked> loc(#loc13)
+    %15 = arith.addi %13, %14 : tensor<1024xi32, #blocked> loc(#loc14)
+    %16 = arith.addi %15, %7 : tensor<1024xi32, #blocked> loc(#loc15)
+    %17 = tt.splat %arg0 : !tt.ptr<bf16> -> tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc16)
+    %18 = tt.addptr %17, %16 : tensor<1024x!tt.ptr<bf16>, #blocked>, tensor<1024xi32, #blocked> loc(#loc16)
+    %19 = arith.andi %6, %12 : tensor<1024xi1, #blocked> loc(#loc17)
+    %20 = tt.load %18, %19, %cst_4 evictionPolicy = evict_last : tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc18)
+    %21 = arith.extf %20 : tensor<1024xbf16, #blocked> to tensor<1024xf32, #blocked> loc(#loc19)
+    %22 = tt.splat %arg1 : !tt.ptr<i64> -> tensor<1024x!tt.ptr<i64>, #blocked> loc(#loc20)
+    %23 = tt.addptr %22, %10 : tensor<1024x!tt.ptr<i64>, #blocked>, tensor<1024xi32, #blocked> loc(#loc20)
+    %24 = tt.load %23, %19, %cst_2 evictionPolicy = evict_last : tensor<1024x!tt.ptr<i64>, #blocked> loc(#loc21)
+    %25 = arith.addi %24, %cst_3 : tensor<1024xi64, #blocked> loc(#loc22)
+    %26 = arith.cmpi slt, %24, %cst_2 : tensor<1024xi64, #blocked> loc(#loc23)
+    %27 = arith.select %26, %25, %24 : tensor<1024xi1, #blocked>, tensor<1024xi64, #blocked> loc(#loc24)
+    %28 = arith.cmpi sge, %27, %cst_2 : tensor<1024xi64, #blocked> loc(#loc25)
+    %29 = arith.cmpi slt, %27, %cst_3 : tensor<1024xi64, #blocked> loc(#loc26)
+    %30 = arith.andi %28, %29 : tensor<1024xi1, #blocked> loc(#loc27)
+    %31 = arith.xori %19, %cst_9 : tensor<1024xi1, #blocked> loc(#loc28)
+    %32 = arith.ori %30, %31 : tensor<1024xi1, #blocked> loc(#loc29)
+    tt.assert %32, "index out of bounds: 0 <= tl.broadcast_to(tmp10, [XBLOCK]) < 131072" : tensor<1024xi1, #blocked> loc(#loc30)
+    %33 = arith.muli %27, %cst_1 : tensor<1024xi64, #blocked> loc(#loc31)
+    %34 = arith.addi %33, %11 : tensor<1024xi64, #blocked> loc(#loc32)
+    %35 = tt.splat %arg2 : !tt.ptr<bf16> -> tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc33)
+    %36 = tt.addptr %35, %34 : tensor<1024x!tt.ptr<bf16>, #blocked>, tensor<1024xi64, #blocked> loc(#loc33)
+    %37 = tt.load %36, %19, %cst_4 evictionPolicy = evict_last : tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc34)
+    %38 = arith.extf %37 : tensor<1024xbf16, #blocked> to tensor<1024xf32, #blocked> loc(#loc35)
+    %39 = arith.mulf %21, %38 : tensor<1024xf32, #blocked> loc(#loc36)
+    %40 = arith.addi %13, %cst_10 : tensor<1024xi32, #blocked> loc(#loc37)
+    %41 = arith.addi %40, %14 : tensor<1024xi32, #blocked> loc(#loc38)
+    %42 = arith.addi %41, %7 : tensor<1024xi32, #blocked> loc(#loc39)
+    %43 = tt.addptr %17, %42 : tensor<1024x!tt.ptr<bf16>, #blocked>, tensor<1024xi32, #blocked> loc(#loc40)
+    %44 = tt.load %43, %19, %cst_4 evictionPolicy = evict_last : tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc41)
+    %45 = arith.extf %44 : tensor<1024xbf16, #blocked> to tensor<1024xf32, #blocked> loc(#loc42)
+    %46 = arith.addi %33, %cst : tensor<1024xi64, #blocked> loc(#loc43)
+    %47 = arith.addi %46, %11 : tensor<1024xi64, #blocked> loc(#loc44)
+    %48 = tt.addptr %35, %47 : tensor<1024x!tt.ptr<bf16>, #blocked>, tensor<1024xi64, #blocked> loc(#loc45)
+    %49 = tt.load %48, %19, %cst_4 evictionPolicy = evict_last : tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc46)
+    %50 = arith.extf %49 : tensor<1024xbf16, #blocked> to tensor<1024xf32, #blocked> loc(#loc47)
+    %51 = arith.mulf %45, %50 : tensor<1024xf32, #blocked> loc(#loc48)
+    %52 = arith.subf %39, %51 : tensor<1024xf32, #blocked> loc(#loc49)
+    %53 = arith.cmpi sge, %11, %cst : tensor<1024xi64, #blocked> loc(#loc50)
+    %54 = arith.addi %7, %cst_11 : tensor<1024xi32, #blocked> loc(#loc51)
+    %55 = arith.addi %41, %54 : tensor<1024xi32, #blocked> loc(#loc52)
+    %56 = tt.addptr %17, %55 : tensor<1024x!tt.ptr<bf16>, #blocked>, tensor<1024xi32, #blocked> loc(#loc53)
+    %57 = arith.andi %6, %53 : tensor<1024xi1, #blocked> loc(#loc54)
+    %58 = tt.load %56, %57, %cst_4 evictionPolicy = evict_last : tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc55)
+    %59 = arith.extf %58 : tensor<1024xbf16, #blocked> to tensor<1024xf32, #blocked> loc(#loc56)
+    %60 = tt.load %23, %57, %cst_2 evictionPolicy = evict_last : tensor<1024x!tt.ptr<i64>, #blocked> loc(#loc57)
+    %61 = arith.addi %60, %cst_3 : tensor<1024xi64, #blocked> loc(#loc58)
+    %62 = arith.cmpi slt, %60, %cst_2 : tensor<1024xi64, #blocked> loc(#loc59)
+    %63 = arith.select %62, %61, %60 : tensor<1024xi1, #blocked>, tensor<1024xi64, #blocked> loc(#loc60)
+    %64 = arith.cmpi sge, %63, %cst_2 : tensor<1024xi64, #blocked> loc(#loc61)
+    %65 = arith.cmpi slt, %63, %cst_3 : tensor<1024xi64, #blocked> loc(#loc62)
+    %66 = arith.andi %64, %65 : tensor<1024xi1, #blocked> loc(#loc63)
+    %67 = arith.xori %57, %cst_9 : tensor<1024xi1, #blocked> loc(#loc64)
+    %68 = arith.ori %66, %67 : tensor<1024xi1, #blocked> loc(#loc65)
+    tt.assert %68, "index out of bounds: 0 <= tl.broadcast_to(tmp28, [XBLOCK]) < 131072" : tensor<1024xi1, #blocked> loc(#loc66)
+    %69 = arith.muli %63, %cst_1 : tensor<1024xi64, #blocked> loc(#loc67)
+    %70 = arith.extsi %54 : tensor<1024xi32, #blocked> to tensor<1024xi64, #blocked> loc(#loc68)
+    %71 = arith.addi %69, %70 : tensor<1024xi64, #blocked> loc(#loc68)
+    %72 = tt.addptr %35, %71 : tensor<1024x!tt.ptr<bf16>, #blocked>, tensor<1024xi64, #blocked> loc(#loc69)
+    %73 = tt.load %72, %57, %cst_4 evictionPolicy = evict_last : tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc70)
+    %74 = arith.extf %73 : tensor<1024xbf16, #blocked> to tensor<1024xf32, #blocked> loc(#loc71)
+    %75 = arith.mulf %59, %74 : tensor<1024xf32, #blocked> loc(#loc72)
+    %76 = arith.addi %15, %54 : tensor<1024xi32, #blocked> loc(#loc73)
+    %77 = tt.addptr %17, %76 : tensor<1024x!tt.ptr<bf16>, #blocked>, tensor<1024xi32, #blocked> loc(#loc74)
+    %78 = tt.load %77, %57, %cst_4 evictionPolicy = evict_last : tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc75)
+    %79 = arith.extf %78 : tensor<1024xbf16, #blocked> to tensor<1024xf32, #blocked> loc(#loc76)
+    %80 = arith.addi %69, %cst : tensor<1024xi64, #blocked> loc(#loc77)
+    %81 = arith.addi %80, %70 : tensor<1024xi64, #blocked> loc(#loc78)
+    %82 = tt.addptr %35, %81 : tensor<1024x!tt.ptr<bf16>, #blocked>, tensor<1024xi64, #blocked> loc(#loc79)
+    %83 = tt.load %82, %57, %cst_4 evictionPolicy = evict_last : tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc80)
+    %84 = arith.extf %83 : tensor<1024xbf16, #blocked> to tensor<1024xf32, #blocked> loc(#loc81)
+    %85 = arith.mulf %79, %84 : tensor<1024xf32, #blocked> loc(#loc82)
+    %86 = arith.addf %75, %85 : tensor<1024xf32, #blocked> loc(#loc83)
+    %87 = arith.select %53, %86, %cst_0 : tensor<1024xi1, #blocked>, tensor<1024xf32, #blocked> loc(#loc84)
+    %88 = arith.select %12, %52, %87 : tensor<1024xi1, #blocked>, tensor<1024xf32, #blocked> loc(#loc90)
+    %89 = tt.splat %arg3 : !tt.ptr<bf16> -> tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc87)
+    %90 = tt.addptr %89, %4 : tensor<1024x!tt.ptr<bf16>, #blocked>, tensor<1024xi32, #blocked> loc(#loc87)
+    %91 = arith.truncf %88 : tensor<1024xf32, #blocked> to tensor<1024xbf16, #blocked> loc(#loc88)
+    tt.store %90, %91, %6 : tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc88)
+    tt.return loc(#loc89)
+  } loc(#loc)
+} loc(#loc)
+#loc1 = loc(unknown)
+#loc2 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":19:28)
+#loc3 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":19:33)
+#loc4 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":20:36)
+#loc5 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":20:23)
+#loc6 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":21:21)
+#loc7 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":22:19)
+#loc8 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":23:21)
+#loc9 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":23:28)
+#loc10 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":24:19)
+#loc11 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":30:18)
+#loc12 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":31:34)
+#loc13 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":31:44)
+#loc14 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":31:39)
+#loc15 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":31:50)
+#loc16 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":31:30)
+#loc17 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":31:64)
+#loc18 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":31:56)
+#loc19 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":31:114)
+#loc20 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":32:30)
+#loc21 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":32:35)
+#loc22 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":34:18)
+#loc23 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":35:18)
+#loc24 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":36:33)
+#loc25 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":37:28)
+#loc26 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":37:100)
+#loc27 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":37:65)
+#loc28 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":37:113)
+#loc29 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":37:111)
+#loc30 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":37:128)
+#loc31 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":38:35)
+#loc32 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":38:44)
+#loc33 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":38:31)
+#loc34 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":38:50)
+#loc35 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":38:108)
+#loc36 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":39:19)
+#loc37 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":40:36)
+#loc38 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":40:45)
+#loc39 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":40:56)
+#loc40 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":40:31)
+#loc41 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":40:62)
+#loc42 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":40:120)
+#loc43 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":41:36)
+#loc44 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":41:49)
+#loc45 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":41:31)
+#loc46 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":41:55)
+#loc47 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":41:113)
+#loc48 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":42:20)
+#loc49 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":43:20)
+#loc50 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":46:20)
+#loc51 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":49:64)
+#loc52 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":49:56)
+#loc53 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":49:31)
+#loc54 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":49:78)
+#loc55 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":49:70)
+#loc56 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":49:129)
+#loc57 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":50:36)
+#loc58 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":52:20)
+#loc59 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":53:20)
+#loc60 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":54:35)
+#loc61 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":55:28)
+#loc62 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":55:100)
+#loc63 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":55:65)
+#loc64 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":55:113)
+#loc65 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":55:111)
+#loc66 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":55:129)
+#loc67 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":56:35)
+#loc68 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":56:44)
+#loc69 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":56:31)
+#loc70 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":56:58)
+#loc71 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":56:117)
+#loc72 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":57:20)
+#loc73 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":58:51)
+#loc74 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":58:31)
+#loc75 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":58:65)
+#loc76 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":58:124)
+#loc77 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":59:36)
+#loc78 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":59:49)
+#loc79 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":59:31)
+#loc80 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":59:63)
+#loc81 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":59:122)
+#loc82 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":60:20)
+#loc83 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":61:20)
+#loc84 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":63:35)
+#loc85 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":64:34)
+#loc86 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":45:34)
+#loc87 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":65:25)
+#loc88 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":65:37)
+#loc89 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":65:4)
+#loc90 = loc(fused[#loc85, #loc86])

platform/aiml/models/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/triton_cache/H7DURMMQ2HZPVNXDZQV7XUMBZAAA7SUNIOX3MKWQ7JZH2F7ESYMQ/__grp__triton_poi_fused_cat_2.json

@@ -0,0 +1 @@
+{"child_paths": {"triton_poi_fused_cat_2.ttir": "/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/triton_cache/H7DURMMQ2HZPVNXDZQV7XUMBZAAA7SUNIOX3MKWQ7JZH2F7ESYMQ/triton_poi_fused_cat_2.ttir", "triton_poi_fused_cat_2.ttgir": "/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/triton_cache/H7DURMMQ2HZPVNXDZQV7XUMBZAAA7SUNIOX3MKWQ7JZH2F7ESYMQ/triton_poi_fused_cat_2.ttgir", "triton_poi_fused_cat_2.llir": "/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/triton_cache/H7DURMMQ2HZPVNXDZQV7XUMBZAAA7SUNIOX3MKWQ7JZH2F7ESYMQ/triton_poi_fused_cat_2.llir", "triton_poi_fused_cat_2.ptx": "/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/triton_cache/H7DURMMQ2HZPVNXDZQV7XUMBZAAA7SUNIOX3MKWQ7JZH2F7ESYMQ/triton_poi_fused_cat_2.ptx", "triton_poi_fused_cat_2.cubin": "/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/triton_cache/H7DURMMQ2HZPVNXDZQV7XUMBZAAA7SUNIOX3MKWQ7JZH2F7ESYMQ/triton_poi_fused_cat_2.cubin", "triton_poi_fused_cat_2.json": "/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/triton_cache/H7DURMMQ2HZPVNXDZQV7XUMBZAAA7SUNIOX3MKWQ7JZH2F7ESYMQ/triton_poi_fused_cat_2.json"}}

platform/aiml/models/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/triton_cache/H7DURMMQ2HZPVNXDZQV7XUMBZAAA7SUNIOX3MKWQ7JZH2F7ESYMQ/triton_poi_fused_cat_2.ptx

@@ -0,0 +1,522 @@
+//
+// Generated by LLVM NVPTX Back-End
+//
+
+.version 8.4
+.target sm_90a
+.address_size 64
+
+	// .globl	triton_poi_fused_cat_2  // -- Begin function triton_poi_fused_cat_2
+.extern .func __assertfail
+(
+	.param .b64 __assertfail_param_0,
+	.param .b64 __assertfail_param_1,
+	.param .b32 __assertfail_param_2,
+	.param .b64 __assertfail_param_3,
+	.param .b64 __assertfail_param_4
+)
+.noreturn;
+.global .align 1 .b8 assertFunc_1[8] = {117, 110, 107, 110, 111, 119, 110};
+.global .align 1 .b8 assertFile_1[134] = {47, 104, 111, 109, 101, 47, 120, 47, 46, 99, 97, 99, 104, 101, 47, 118, 108, 108, 109, 47, 116, 111, 114, 99, 104, 95, 99, 111, 109, 112, 105, 108, 101, 95, 99, 97, 99, 104, 101, 47, 48, 54, 57, 99, 101, 51, 101, 97, 50, 98, 47, 114, 97, 110, 107, 95, 48, 95, 48, 47, 105, 110, 100, 117, 99, 116, 111, 114, 95, 99, 97, 99, 104, 101, 47, 106, 99, 47, 99, 106, 99, 103, 120, 105, 101, 105, 98, 113, 98, 105, 108, 104, 52, 107, 110, 54, 50, 118, 107, 113, 119, 103, 113, 50, 53, 97, 54, 120, 122, 52, 117, 103, 107, 122, 120, 109, 105, 119, 53, 104, 109, 122, 109, 102, 50, 113, 105, 106, 117, 115, 46, 112, 121};
+.global .align 1 .b8 assertMessage_1[68] = {105, 110, 100, 101, 120, 32, 111, 117, 116, 32, 111, 102, 32, 98, 111, 117, 110, 100, 115, 58, 32, 48, 32, 60, 61, 32, 116, 108, 46, 98, 114, 111, 97, 100, 99, 97, 115, 116, 95, 116, 111, 40, 116, 109, 112, 50, 56, 44, 32, 91, 88, 66, 76, 79, 67, 75, 93, 41, 32, 60, 32, 49, 51, 49, 48, 55, 50};
+.global .align 1 .b8 assertFunc_0[8] = {117, 110, 107, 110, 111, 119, 110};
+.global .align 1 .b8 assertFile_0[134] = {47, 104, 111, 109, 101, 47, 120, 47, 46, 99, 97, 99, 104, 101, 47, 118, 108, 108, 109, 47, 116, 111, 114, 99, 104, 95, 99, 111, 109, 112, 105, 108, 101, 95, 99, 97, 99, 104, 101, 47, 48, 54, 57, 99, 101, 51, 101, 97, 50, 98, 47, 114, 97, 110, 107, 95, 48, 95, 48, 47, 105, 110, 100, 117, 99, 116, 111, 114, 95, 99, 97, 99, 104, 101, 47, 106, 99, 47, 99, 106, 99, 103, 120, 105, 101, 105, 98, 113, 98, 105, 108, 104, 52, 107, 110, 54, 50, 118, 107, 113, 119, 103, 113, 50, 53, 97, 54, 120, 122, 52, 117, 103, 107, 122, 120, 109, 105, 119, 53, 104, 109, 122, 109, 102, 50, 113, 105, 106, 117, 115, 46, 112, 121};
+.global .align 1 .b8 assertMessage_0[68] = {105, 110, 100, 101, 120, 32, 111, 117, 116, 32, 111, 102, 32, 98, 111, 117, 110, 100, 115, 58, 32, 48, 32, 60, 61, 32, 116, 108, 46, 98, 114, 111, 97, 100, 99, 97, 115, 116, 95, 116, 111, 40, 116, 109, 112, 49, 48, 44, 32, 91, 88, 66, 76, 79, 67, 75, 93, 41, 32, 60, 32, 49, 51, 49, 48, 55, 50};
+                                        // @triton_poi_fused_cat_2
+.visible .entry triton_poi_fused_cat_2(
+	.param .u64 .ptr .global .align 1 triton_poi_fused_cat_2_param_0,
+	.param .u64 .ptr .global .align 1 triton_poi_fused_cat_2_param_1,
+	.param .u64 .ptr .global .align 1 triton_poi_fused_cat_2_param_2,
+	.param .u64 .ptr .global .align 1 triton_poi_fused_cat_2_param_3,
+	.param .u32 triton_poi_fused_cat_2_param_4,
+	.param .u64 .ptr .global .align 1 triton_poi_fused_cat_2_param_5
+)
+.reqntid 256, 1, 1
+{
+	.reg .pred 	%p<27>;
+	.reg .b16 	%rs<17>;
+	.reg .b32 	%r<52>;
+	.reg .f32 	%f<29>;
+	.reg .b64 	%rd<54>;
+	.loc	1 18 0                          // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:18:0
+$L__func_begin0:
+	.loc	1 18 0                          // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:18:0
+
+// %bb.0:
+	ld.param.u32 	%r11, [triton_poi_fused_cat_2_param_4];
+	ld.param.u64 	%rd5, [triton_poi_fused_cat_2_param_0];
+	ld.param.u64 	%rd13, [triton_poi_fused_cat_2_param_1];
+$L__tmp0:
+	.loc	1 19 28                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:19:28
+	mov.u32 	%r14, %ctaid.x;
+	.loc	1 19 33                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:19:33
+	shl.b32 	%r15, %r14, 9;
+	.loc	1 20 36                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:20:36
+	mov.u32 	%r16, %tid.x;
+	shl.b32 	%r17, %r16, 1;
+	and.b32  	%r18, %r17, 510;
+	.loc	1 20 23                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:20:23
+	or.b32  	%r1, %r18, %r15;
+	.loc	1 21 21                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:21:21
+	setp.lt.s32 	%p6, %r1, %r11;
+	.loc	1 23 21                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:23:21
+	bfe.s32 	%r19, %r14, 22, 1;
+	shr.u32 	%r20, %r19, 25;
+	add.s32 	%r21, %r1, %r20;
+	shr.s32 	%r22, %r21, 7;
+	.loc	1 22 19                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:22:19
+	and.b32  	%r23, %r21, -128;
+	sub.s32 	%r2, %r1, %r23;
+	.loc	1 23 28                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:23:28
+	shr.u32 	%r24, %r22, 30;
+	add.s32 	%r25, %r22, %r24;
+	and.b32  	%r26, %r25, 33554428;
+	sub.s32 	%r27, %r22, %r26;
+	.loc	1 24 19                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:24:19
+	shr.u32 	%r28, %r19, 23;
+	add.s32 	%r29, %r1, %r28;
+	shr.s32 	%r30, %r29, 9;
+	.loc	1 30 18                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:30:18
+	setp.lt.s32 	%p7, %r2, 64;
+	.loc	1 31 41                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:31:41
+	shl.b32 	%r31, %r27, 7;
+	.loc	1 31 37                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:31:37
+	mad.lo.s32 	%r3, %r30, 4608, %r31;
+	.loc	1 31 46                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:31:46
+	add.s32 	%r4, %r3, 3584;
+	.loc	1 31 57                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:31:57
+	add.s32 	%r32, %r4, %r2;
+	.loc	1 31 30                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:31:30
+	mul.wide.s32 	%rd14, %r32, 2;
+	add.s64 	%rd8, %rd5, %rd14;
+	.loc	1 31 71                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:31:71
+	and.pred  	%p5, %p7, %p6;
+	not.pred 	%p8, %p5;
+	mov.b32 	%r13, 0;
+	.loc	1 31 63                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:31:63
+	// begin inline asm
+	mov.u32 %r12, %r13;
+	@%p5 ld.global.L1::evict_last.b32 { %r12 }, [ %rd8 + 0 ];
+	// end inline asm
+	.loc	1 32 30                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:32:30
+	mul.wide.s32 	%rd15, %r30, 8;
+	add.s64 	%rd12, %rd13, %rd15;
+	.loc	1 32 35                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:32:35
+	// begin inline asm
+	mov.u64 %rd9, 0x0;
+	@%p5 ld.global.L1::evict_last.b64 { %rd9 }, [ %rd12 + 0 ];
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd11, 0x0;
+	@%p5 ld.global.L1::evict_last.b64 { %rd11 }, [ %rd12 + 0 ];
+	// end inline asm
+	.loc	1 36 33                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:36:33
+	shr.u64 	%rd16, %rd9, 46;
+	and.b64  	%rd17, %rd16, 131072;
+	add.s64 	%rd2, %rd17, %rd9;
+	.loc	1 37 65                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:37:65
+	setp.lt.u64 	%p9, %rd2, 131072;
+	.loc	1 37 128                        // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:37:128
+	or.pred  	%p10, %p8, %p9;
+	@%p10 bra 	$L__BB0_2;
+	bra.uni 	$L__BB0_1;
+$L__BB0_2:
+	.loc	1 0 128                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:0:128
+	ld.param.u64 	%rd6, [triton_poi_fused_cat_2_param_2];
+	.loc	1 37 128                        // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:37:128
+	bar.sync 	0;
+	.loc	1 38 31                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:38:31
+	shl.b64 	%rd26, %rd2, 8;
+	add.s64 	%rd27, %rd6, %rd26;
+	mul.wide.s32 	%rd28, %r2, 2;
+	add.s64 	%rd18, %rd27, %rd28;
+	.loc	1 38 50                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:38:50
+	// begin inline asm
+	mov.u32 %r33, %r13;
+	@%p5 ld.global.L1::evict_last.b32 { %r33 }, [ %rd18 + 0 ];
+	// end inline asm
+	.loc	1 40 47                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:40:47
+	add.s32 	%r41, %r3, 3648;
+	.loc	1 40 58                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:40:58
+	add.s32 	%r42, %r41, %r2;
+	.loc	1 40 31                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:40:31
+	mul.wide.s32 	%rd29, %r42, 2;
+	add.s64 	%rd19, %rd5, %rd29;
+	.loc	1 40 64                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:40:64
+	// begin inline asm
+	mov.u32 %r35, %r13;
+	@%p5 ld.global.L1::evict_last.b32 { %r35 }, [ %rd19 + 0 ];
+	// end inline asm
+	.loc	1 41 31                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:41:31
+	add.s64 	%rd20, %rd18, 128;
+	.loc	1 41 55                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:41:55
+	// begin inline asm
+	mov.u32 %r37, %r13;
+	@%p5 ld.global.L1::evict_last.b32 { %r37 }, [ %rd20 + 0 ];
+	// end inline asm
+	.loc	1 46 20                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:46:20
+	setp.gt.s32 	%p18, %r2, 63;
+	.loc	1 49 66                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:49:66
+	add.s32 	%r9, %r2, -64;
+	.loc	1 49 58                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:49:58
+	add.s32 	%r43, %r41, %r9;
+	.loc	1 49 31                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:49:31
+	mul.wide.s32 	%rd30, %r43, 2;
+	add.s64 	%rd21, %rd5, %rd30;
+	.loc	1 49 80                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:49:80
+	and.pred  	%p16, %p18, %p6;
+	not.pred 	%p19, %p16;
+	.loc	1 49 72                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:49:72
+	// begin inline asm
+	mov.u32 %r39, %r13;
+	@%p16 ld.global.L1::evict_last.b32 { %r39 }, [ %rd21 + 0 ];
+	// end inline asm
+	.loc	1 50 36                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:50:36
+	// begin inline asm
+	mov.u64 %rd22, 0x0;
+	@%p16 ld.global.L1::evict_last.b64 { %rd22 }, [ %rd12 + 0 ];
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd24, 0x0;
+	@%p16 ld.global.L1::evict_last.b64 { %rd24 }, [ %rd12 + 0 ];
+	// end inline asm
+	.loc	1 54 35                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:54:35
+	shr.u64 	%rd31, %rd22, 46;
+	and.b64  	%rd32, %rd31, 131072;
+	add.s64 	%rd4, %rd32, %rd22;
+	.loc	1 55 65                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:55:65
+	setp.lt.u64 	%p20, %rd4, 131072;
+	.loc	1 55 129                        // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:55:129
+	or.pred  	%p21, %p19, %p20;
+	@%p21 bra 	$L__BB0_4;
+	bra.uni 	$L__BB0_3;
+$L__BB0_4:
+	.loc	1 0 129                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:0:129
+	ld.param.u64 	%rd7, [triton_poi_fused_cat_2_param_3];
+	cvt.s64.s32 	%rd3, %r2;
+	.loc	1 55 129                        // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:55:129
+	bar.sync 	0;
+	.loc	1 56 31                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:56:31
+	shl.b64 	%rd37, %rd4, 8;
+	add.s64 	%rd38, %rd6, %rd37;
+	shl.b64 	%rd39, %rd3, 1;
+	add.s64 	%rd35, %rd38, %rd39;
+	add.s64 	%rd33, %rd35, -128;
+	mov.b32 	%r45, 0;
+	.loc	1 56 58                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:56:58
+	// begin inline asm
+	mov.u32 %r44, %r45;
+	@%p16 ld.global.L1::evict_last.b32 { %r44 }, [ %rd33 + 0 ];
+	// end inline asm
+	.loc	1 58 58                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:58:58
+	add.s32 	%r51, %r4, %r9;
+	.loc	1 58 31                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:58:31
+	mul.wide.s32 	%rd40, %r51, 2;
+	add.s64 	%rd34, %rd5, %rd40;
+	.loc	1 58 72                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:58:72
+	// begin inline asm
+	mov.u32 %r46, %r45;
+	@%p16 ld.global.L1::evict_last.b32 { %r46 }, [ %rd34 + 0 ];
+	// end inline asm
+	.loc	1 59 63                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:59:63
+	// begin inline asm
+	mov.u32 %r48, %r45;
+	@%p16 ld.global.L1::evict_last.b32 { %r48 }, [ %rd35 + 0 ];
+	// end inline asm
+	.loc	1 65 25                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:65:25
+	mul.wide.s32 	%rd41, %r1, 2;
+	add.s64 	%rd36, %rd7, %rd41;
+	.loc	1 49 131                        // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:49:131
+	mov.b32 	{%rs1, %rs2}, %r39;
+	cvt.f32.bf16 	%f1, %rs1;
+	cvt.f32.bf16 	%f2, %rs2;
+	.loc	1 31 121                        // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:31:121
+	mov.b32 	{%rs3, %rs4}, %r12;
+	cvt.f32.bf16 	%f3, %rs3;
+	cvt.f32.bf16 	%f4, %rs4;
+	.loc	1 38 108                        // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:38:108
+	mov.b32 	{%rs5, %rs6}, %r33;
+	cvt.f32.bf16 	%f5, %rs5;
+	cvt.f32.bf16 	%f6, %rs6;
+	.loc	1 40 122                        // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:40:122
+	mov.b32 	{%rs7, %rs8}, %r35;
+	cvt.f32.bf16 	%f7, %rs8;
+	cvt.f32.bf16 	%f8, %rs7;
+	.loc	1 41 113                        // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:41:113
+	mov.b32 	{%rs9, %rs10}, %r37;
+	cvt.f32.bf16 	%f9, %rs10;
+	cvt.f32.bf16 	%f10, %rs9;
+	.loc	1 42 20                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:42:20
+	mul.f32 	%f11, %f8, %f10;
+	mul.f32 	%f12, %f7, %f9;
+	.loc	1 43 20                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:43:20
+	neg.f32 	%f13, %f12;
+	fma.rn.f32 	%f14, %f4, %f6, %f13;
+	neg.f32 	%f15, %f11;
+	fma.rn.f32 	%f16, %f3, %f5, %f15;
+	.loc	1 56 117                        // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:56:117
+	mov.b32 	{%rs11, %rs12}, %r44;
+	cvt.f32.bf16 	%f17, %rs11;
+	cvt.f32.bf16 	%f18, %rs12;
+	.loc	1 58 131                        // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:58:131
+	mov.b32 	{%rs13, %rs14}, %r46;
+	cvt.f32.bf16 	%f19, %rs14;
+	cvt.f32.bf16 	%f20, %rs13;
+	.loc	1 59 122                        // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:59:122
+	mov.b32 	{%rs15, %rs16}, %r48;
+	cvt.f32.bf16 	%f21, %rs16;
+	cvt.f32.bf16 	%f22, %rs15;
+	.loc	1 60 20                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:60:20
+	mul.f32 	%f23, %f20, %f22;
+	mul.f32 	%f24, %f19, %f21;
+	.loc	1 61 20                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:61:20
+	fma.rn.f32 	%f25, %f2, %f18, %f24;
+	fma.rn.f32 	%f26, %f1, %f17, %f23;
+	.loc	1 0 0                           // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:0:0
+	selp.f32 	%f27, %f16, %f26, %p7;
+	selp.f32 	%f28, %f14, %f25, %p7;
+	.loc	1 65 37                         // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:65:37
+	cvt.rn.bf16x2.f32 	%r50, %f28, %f27;
+	// begin inline asm
+	@%p6 st.global.b32 [ %rd36 + 0 ], { %r50 };
+	// end inline asm
+	.loc	1 65 4                          // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:65:4
+	ret;
+$L__BB0_1:
+	.loc	1 37 128                        // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:37:128
+	mov.u64 	%rd48, assertMessage_0;
+	cvta.global.u64 	%rd49, %rd48;
+	mov.u64 	%rd50, assertFile_0;
+	cvta.global.u64 	%rd51, %rd50;
+	mov.u64 	%rd52, assertFunc_0;
+	cvta.global.u64 	%rd53, %rd52;
+	{ // callseq 8, 0
+	.param .b64 param0;
+	st.param.b64 	[param0], %rd49;
+	.param .b64 param1;
+	st.param.b64 	[param1], %rd51;
+	.param .b32 param2;
+	st.param.b32 	[param2], 37;
+	.param .b64 param3;
+	st.param.b64 	[param3], %rd53;
+	.param .b64 param4;
+	st.param.b64 	[param4], 1;
+	call.uni 
+	__assertfail, 
+	(
+	param0, 
+	param1, 
+	param2, 
+	param3, 
+	param4
+	);
+	} // callseq 8
+	trap;
+$L__BB0_3:
+	.loc	1 55 129                        // cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py:55:129
+	mov.u64 	%rd42, assertMessage_1;
+	cvta.global.u64 	%rd43, %rd42;
+	mov.u64 	%rd44, assertFile_1;
+	cvta.global.u64 	%rd45, %rd44;
+	mov.u64 	%rd46, assertFunc_1;
+	cvta.global.u64 	%rd47, %rd46;
+	{ // callseq 7, 0
+	.param .b64 param0;
+	st.param.b64 	[param0], %rd43;
+	.param .b64 param1;
+	st.param.b64 	[param1], %rd45;
+	.param .b32 param2;
+	st.param.b32 	[param2], 55;
+	.param .b64 param3;
+	st.param.b64 	[param3], %rd47;
+	.param .b64 param4;
+	st.param.b64 	[param4], 1;
+	call.uni 
+	__assertfail, 
+	(
+	param0, 
+	param1, 
+	param2, 
+	param3, 
+	param4
+	);
+	} // callseq 7
+	trap;
+$L__tmp1:
+$L__func_end0:
+                                        // -- End function
+}
+	.file	1 "/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/jc/cjcgxieibqbilh4kn62vkqwgq25a6xz4ugkzxmiw5hmzmf2qijus.py"
+	.section	.debug_abbrev
+	{
+.b8 1                                   // Abbreviation Code
+.b8 17                                  // DW_TAG_compile_unit
+.b8 0                                   // DW_CHILDREN_no
+.b8 37                                  // DW_AT_producer
+.b8 8                                   // DW_FORM_string
+.b8 19                                  // DW_AT_language
+.b8 5                                   // DW_FORM_data2
+.b8 3                                   // DW_AT_name
+.b8 8                                   // DW_FORM_string
+.b8 16                                  // DW_AT_stmt_list
+.b8 6                                   // DW_FORM_data4
+.b8 27                                  // DW_AT_comp_dir
+.b8 8                                   // DW_FORM_string
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 0                                   // EOM(3)
+	}
+	.section	.debug_info
+	{
+.b32 155                                // Length of Unit
+.b8 2                                   // DWARF version number
+.b8 0
+.b32 .debug_abbrev                      // Offset Into Abbrev. Section
+.b8 8                                   // Address Size (in bytes)
+.b8 1                                   // Abbrev [1] 0xb:0x94 DW_TAG_compile_unit
+.b8 116                                 // DW_AT_producer
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 0
+.b8 2                                   // DW_AT_language
+.b8 0
+.b8 99                                  // DW_AT_name
+.b8 106
+.b8 99
+.b8 103
+.b8 120
+.b8 105
+.b8 101
+.b8 105
+.b8 98
+.b8 113
+.b8 98
+.b8 105
+.b8 108
+.b8 104
+.b8 52
+.b8 107
+.b8 110
+.b8 54
+.b8 50
+.b8 118
+.b8 107
+.b8 113
+.b8 119
+.b8 103
+.b8 113
+.b8 50
+.b8 53
+.b8 97
+.b8 54
+.b8 120
+.b8 122
+.b8 52
+.b8 117
+.b8 103
+.b8 107
+.b8 122
+.b8 120
+.b8 109
+.b8 105
+.b8 119
+.b8 53
+.b8 104
+.b8 109
+.b8 122
+.b8 109
+.b8 102
+.b8 50
+.b8 113
+.b8 105
+.b8 106
+.b8 117
+.b8 115
+.b8 46
+.b8 112
+.b8 121
+.b8 0
+.b32 .debug_line                        // DW_AT_stmt_list
+.b8 47                                  // DW_AT_comp_dir
+.b8 104
+.b8 111
+.b8 109
+.b8 101
+.b8 47
+.b8 120
+.b8 47
+.b8 46
+.b8 99
+.b8 97
+.b8 99
+.b8 104
+.b8 101
+.b8 47
+.b8 118
+.b8 108
+.b8 108
+.b8 109
+.b8 47
+.b8 116
+.b8 111
+.b8 114
+.b8 99
+.b8 104
+.b8 95
+.b8 99
+.b8 111
+.b8 109
+.b8 112
+.b8 105
+.b8 108
+.b8 101
+.b8 95
+.b8 99
+.b8 97
+.b8 99
+.b8 104
+.b8 101
+.b8 47
+.b8 48
+.b8 54
+.b8 57
+.b8 99
+.b8 101
+.b8 51
+.b8 101
+.b8 97
+.b8 50
+.b8 98
+.b8 47
+.b8 114
+.b8 97
+.b8 110
+.b8 107
+.b8 95
+.b8 48
+.b8 95
+.b8 48
+.b8 47
+.b8 105
+.b8 110
+.b8 100
+.b8 117
+.b8 99
+.b8 116
+.b8 111
+.b8 114
+.b8 95
+.b8 99
+.b8 97
+.b8 99
+.b8 104
+.b8 101
+.b8 47
+.b8 106
+.b8 99
+.b8 0
+	}
+	.section	.debug_macinfo	{	}

platform/aiml/models/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/triton_cache/JGBJTSHFQO5ZMSSDR5JQ4N6IDDC3AKTV33H2WXFG26XWQP3IZ4ZA/triton_poi_fused_cat_1.ttir

@@ -0,0 +1,205 @@
+#loc = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":18:0)
+module {
+  tt.func public @triton_poi_fused_cat_1(%arg0: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":18:0), %arg1: !tt.ptr<i64> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":18:0), %arg2: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":18:0), %arg3: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":18:0), %arg4: i32 {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":18:0)) attributes {noinline = false} {
+    %cst = arith.constant dense<131072> : tensor<512xi64> loc(#loc1)
+    %cst_0 = arith.constant dense<0> : tensor<512xi64> loc(#loc1)
+    %cst_1 = arith.constant dense<0.000000e+00> : tensor<512xbf16> loc(#loc1)
+    %cst_2 = arith.constant dense<-64> : tensor<512xi32> loc(#loc1)
+    %cst_3 = arith.constant dense<64> : tensor<512xi32> loc(#loc1)
+    %cst_4 = arith.constant dense<128> : tensor<512xi64> loc(#loc1)
+    %cst_5 = arith.constant dense<true> : tensor<512xi1> loc(#loc1)
+    %cst_6 = arith.constant dense<0.000000e+00> : tensor<512xf32> loc(#loc1)
+    %cst_7 = arith.constant dense<4608> : tensor<512xi32> loc(#loc1)
+    %cst_8 = arith.constant dense<64> : tensor<512xi64> loc(#loc1)
+    %cst_9 = arith.constant dense<3584> : tensor<512xi32> loc(#loc1)
+    %cst_10 = arith.constant dense<28> : tensor<512xi32> loc(#loc1)
+    %cst_11 = arith.constant dense<128> : tensor<512xi32> loc(#loc1)
+    %c512_i32 = arith.constant 512 : i32 loc(#loc1)
+    %0 = tt.get_program_id x : i32 loc(#loc2)
+    %1 = arith.muli %0, %c512_i32 : i32 loc(#loc3)
+    %2 = tt.make_range {end = 512 : i32, start = 0 : i32} : tensor<512xi32> loc(#loc4)
+    %3 = tt.splat %1 : i32 -> tensor<512xi32> loc(#loc5)
+    %4 = arith.addi %3, %2 : tensor<512xi32> loc(#loc5)
+    %5 = tt.splat %arg4 : i32 -> tensor<512xi32> loc(#loc6)
+    %6 = arith.cmpi slt, %4, %5 : tensor<512xi32> loc(#loc6)
+    %7 = arith.remsi %4, %cst_11 : tensor<512xi32> loc(#loc7)
+    %8 = arith.divsi %4, %cst_11 : tensor<512xi32> loc(#loc8)
+    %9 = arith.remsi %8, %cst_10 : tensor<512xi32> loc(#loc9)
+    %10 = arith.divsi %4, %cst_9 : tensor<512xi32> loc(#loc10)
+    %11 = arith.extsi %7 : tensor<512xi32> to tensor<512xi64> loc(#loc11)
+    %12 = arith.cmpi slt, %11, %cst_8 : tensor<512xi64> loc(#loc11)
+    %13 = arith.muli %9, %cst_11 : tensor<512xi32> loc(#loc12)
+    %14 = arith.muli %10, %cst_7 : tensor<512xi32> loc(#loc13)
+    %15 = arith.addi %13, %14 : tensor<512xi32> loc(#loc14)
+    %16 = arith.addi %15, %7 : tensor<512xi32> loc(#loc15)
+    %17 = tt.splat %arg0 : !tt.ptr<bf16> -> tensor<512x!tt.ptr<bf16>> loc(#loc16)
+    %18 = tt.addptr %17, %16 : tensor<512x!tt.ptr<bf16>>, tensor<512xi32> loc(#loc16)
+    %19 = arith.andi %6, %12 : tensor<512xi1> loc(#loc17)
+    %20 = tt.load %18, %19, %cst_1 evictionPolicy = evict_last : tensor<512x!tt.ptr<bf16>> loc(#loc18)
+    %21 = arith.extf %20 : tensor<512xbf16> to tensor<512xf32> loc(#loc19)
+    %22 = tt.splat %arg1 : !tt.ptr<i64> -> tensor<512x!tt.ptr<i64>> loc(#loc20)
+    %23 = tt.addptr %22, %10 : tensor<512x!tt.ptr<i64>>, tensor<512xi32> loc(#loc20)
+    %24 = tt.load %23, %19, %cst_0 evictionPolicy = evict_last : tensor<512x!tt.ptr<i64>> loc(#loc21)
+    %25 = arith.addi %24, %cst : tensor<512xi64> loc(#loc22)
+    %26 = arith.cmpi slt, %24, %cst_0 : tensor<512xi64> loc(#loc23)
+    %27 = arith.select %26, %25, %24 : tensor<512xi1>, tensor<512xi64> loc(#loc24)
+    %28 = arith.cmpi sge, %27, %cst_0 : tensor<512xi64> loc(#loc25)
+    %29 = arith.cmpi slt, %27, %cst : tensor<512xi64> loc(#loc26)
+    %30 = arith.andi %28, %29 : tensor<512xi1> loc(#loc27)
+    %31 = arith.xori %19, %cst_5 : tensor<512xi1> loc(#loc28)
+    %32 = arith.ori %30, %31 : tensor<512xi1> loc(#loc29)
+    tt.assert %32, "index out of bounds: 0 <= tl.broadcast_to(tmp10, [XBLOCK]) < 131072" : tensor<512xi1> loc(#loc30)
+    %33 = arith.muli %27, %cst_4 : tensor<512xi64> loc(#loc31)
+    %34 = arith.addi %33, %11 : tensor<512xi64> loc(#loc32)
+    %35 = tt.splat %arg2 : !tt.ptr<bf16> -> tensor<512x!tt.ptr<bf16>> loc(#loc33)
+    %36 = tt.addptr %35, %34 : tensor<512x!tt.ptr<bf16>>, tensor<512xi64> loc(#loc33)
+    %37 = tt.load %36, %19, %cst_1 evictionPolicy = evict_last : tensor<512x!tt.ptr<bf16>> loc(#loc34)
+    %38 = arith.extf %37 : tensor<512xbf16> to tensor<512xf32> loc(#loc35)
+    %39 = arith.mulf %21, %38 : tensor<512xf32> loc(#loc36)
+    %40 = arith.addi %13, %cst_3 : tensor<512xi32> loc(#loc37)
+    %41 = arith.addi %40, %14 : tensor<512xi32> loc(#loc38)
+    %42 = arith.addi %41, %7 : tensor<512xi32> loc(#loc39)
+    %43 = tt.addptr %17, %42 : tensor<512x!tt.ptr<bf16>>, tensor<512xi32> loc(#loc40)
+    %44 = tt.load %43, %19, %cst_1 evictionPolicy = evict_last : tensor<512x!tt.ptr<bf16>> loc(#loc41)
+    %45 = arith.extf %44 : tensor<512xbf16> to tensor<512xf32> loc(#loc42)
+    %46 = arith.addi %33, %cst_8 : tensor<512xi64> loc(#loc43)
+    %47 = arith.addi %46, %11 : tensor<512xi64> loc(#loc44)
+    %48 = tt.addptr %35, %47 : tensor<512x!tt.ptr<bf16>>, tensor<512xi64> loc(#loc45)
+    %49 = tt.load %48, %19, %cst_1 evictionPolicy = evict_last : tensor<512x!tt.ptr<bf16>> loc(#loc46)
+    %50 = arith.extf %49 : tensor<512xbf16> to tensor<512xf32> loc(#loc47)
+    %51 = arith.mulf %45, %50 : tensor<512xf32> loc(#loc48)
+    %52 = arith.subf %39, %51 : tensor<512xf32> loc(#loc49)
+    %53 = arith.cmpi sge, %11, %cst_8 : tensor<512xi64> loc(#loc50)
+    %54 = arith.addi %7, %cst_2 : tensor<512xi32> loc(#loc51)
+    %55 = arith.addi %41, %54 : tensor<512xi32> loc(#loc52)
+    %56 = tt.addptr %17, %55 : tensor<512x!tt.ptr<bf16>>, tensor<512xi32> loc(#loc53)
+    %57 = arith.andi %6, %53 : tensor<512xi1> loc(#loc54)
+    %58 = tt.load %56, %57, %cst_1 evictionPolicy = evict_last : tensor<512x!tt.ptr<bf16>> loc(#loc55)
+    %59 = arith.extf %58 : tensor<512xbf16> to tensor<512xf32> loc(#loc56)
+    %60 = tt.load %23, %57, %cst_0 evictionPolicy = evict_last : tensor<512x!tt.ptr<i64>> loc(#loc57)
+    %61 = arith.addi %60, %cst : tensor<512xi64> loc(#loc58)
+    %62 = arith.cmpi slt, %60, %cst_0 : tensor<512xi64> loc(#loc59)
+    %63 = arith.select %62, %61, %60 : tensor<512xi1>, tensor<512xi64> loc(#loc60)
+    %64 = arith.cmpi sge, %63, %cst_0 : tensor<512xi64> loc(#loc61)
+    %65 = arith.cmpi slt, %63, %cst : tensor<512xi64> loc(#loc62)
+    %66 = arith.andi %64, %65 : tensor<512xi1> loc(#loc63)
+    %67 = arith.xori %57, %cst_5 : tensor<512xi1> loc(#loc64)
+    %68 = arith.ori %66, %67 : tensor<512xi1> loc(#loc65)
+    tt.assert %68, "index out of bounds: 0 <= tl.broadcast_to(tmp28, [XBLOCK]) < 131072" : tensor<512xi1> loc(#loc66)
+    %69 = arith.muli %63, %cst_4 : tensor<512xi64> loc(#loc67)
+    %70 = arith.extsi %54 : tensor<512xi32> to tensor<512xi64> loc(#loc68)
+    %71 = arith.addi %69, %70 : tensor<512xi64> loc(#loc68)
+    %72 = tt.addptr %35, %71 : tensor<512x!tt.ptr<bf16>>, tensor<512xi64> loc(#loc69)
+    %73 = tt.load %72, %57, %cst_1 evictionPolicy = evict_last : tensor<512x!tt.ptr<bf16>> loc(#loc70)
+    %74 = arith.extf %73 : tensor<512xbf16> to tensor<512xf32> loc(#loc71)
+    %75 = arith.mulf %59, %74 : tensor<512xf32> loc(#loc72)
+    %76 = arith.addi %15, %54 : tensor<512xi32> loc(#loc73)
+    %77 = tt.addptr %17, %76 : tensor<512x!tt.ptr<bf16>>, tensor<512xi32> loc(#loc74)
+    %78 = tt.load %77, %57, %cst_1 evictionPolicy = evict_last : tensor<512x!tt.ptr<bf16>> loc(#loc75)
+    %79 = arith.extf %78 : tensor<512xbf16> to tensor<512xf32> loc(#loc76)
+    %80 = arith.addi %69, %cst_8 : tensor<512xi64> loc(#loc77)
+    %81 = arith.addi %80, %70 : tensor<512xi64> loc(#loc78)
+    %82 = tt.addptr %35, %81 : tensor<512x!tt.ptr<bf16>>, tensor<512xi64> loc(#loc79)
+    %83 = tt.load %82, %57, %cst_1 evictionPolicy = evict_last : tensor<512x!tt.ptr<bf16>> loc(#loc80)
+    %84 = arith.extf %83 : tensor<512xbf16> to tensor<512xf32> loc(#loc81)
+    %85 = arith.mulf %79, %84 : tensor<512xf32> loc(#loc82)
+    %86 = arith.addf %75, %85 : tensor<512xf32> loc(#loc83)
+    %87 = arith.select %53, %86, %cst_6 : tensor<512xi1>, tensor<512xf32> loc(#loc84)
+    %88 = arith.select %12, %52, %87 : tensor<512xi1>, tensor<512xf32> loc(#loc90)
+    %89 = tt.splat %arg3 : !tt.ptr<bf16> -> tensor<512x!tt.ptr<bf16>> loc(#loc87)
+    %90 = tt.addptr %89, %4 : tensor<512x!tt.ptr<bf16>>, tensor<512xi32> loc(#loc87)
+    %91 = arith.truncf %88 : tensor<512xf32> to tensor<512xbf16> loc(#loc88)
+    tt.store %90, %91, %6 : tensor<512x!tt.ptr<bf16>> loc(#loc88)
+    tt.return loc(#loc89)
+  } loc(#loc)
+} loc(#loc)
+#loc1 = loc(unknown)
+#loc2 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":19:28)
+#loc3 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":19:33)
+#loc4 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":20:36)
+#loc5 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":20:23)
+#loc6 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":21:21)
+#loc7 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":22:19)
+#loc8 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":23:21)
+#loc9 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":23:28)
+#loc10 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":24:19)
+#loc11 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":30:18)
+#loc12 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":31:34)
+#loc13 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":31:44)
+#loc14 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":31:39)
+#loc15 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":31:50)
+#loc16 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":31:30)
+#loc17 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":31:64)
+#loc18 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":31:56)
+#loc19 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":31:114)
+#loc20 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":32:30)
+#loc21 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":32:35)
+#loc22 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":34:18)
+#loc23 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":35:18)
+#loc24 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":36:33)
+#loc25 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":37:28)
+#loc26 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":37:100)
+#loc27 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":37:65)
+#loc28 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":37:113)
+#loc29 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":37:111)
+#loc30 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":37:128)
+#loc31 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":38:35)
+#loc32 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":38:44)
+#loc33 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":38:31)
+#loc34 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":38:50)
+#loc35 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":38:108)
+#loc36 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":39:19)
+#loc37 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":40:36)
+#loc38 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":40:45)
+#loc39 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":40:56)
+#loc40 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":40:31)
+#loc41 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":40:62)
+#loc42 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":40:120)
+#loc43 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":41:36)
+#loc44 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":41:49)
+#loc45 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":41:31)
+#loc46 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":41:55)
+#loc47 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":41:113)
+#loc48 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":42:20)
+#loc49 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":43:20)
+#loc50 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":46:20)
+#loc51 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":49:64)
+#loc52 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":49:56)
+#loc53 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":49:31)
+#loc54 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":49:78)
+#loc55 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":49:70)
+#loc56 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":49:129)
+#loc57 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":50:36)
+#loc58 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":52:20)
+#loc59 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":53:20)
+#loc60 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":54:35)
+#loc61 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":55:28)
+#loc62 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":55:100)
+#loc63 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":55:65)
+#loc64 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":55:113)
+#loc65 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":55:111)
+#loc66 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":55:129)
+#loc67 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":56:35)
+#loc68 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":56:44)
+#loc69 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":56:31)
+#loc70 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":56:58)
+#loc71 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":56:117)
+#loc72 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":57:20)
+#loc73 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":58:51)
+#loc74 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":58:31)
+#loc75 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":58:65)
+#loc76 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":58:124)
+#loc77 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":59:36)
+#loc78 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":59:49)
+#loc79 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":59:31)
+#loc80 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":59:63)
+#loc81 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":59:122)
+#loc82 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":60:20)
+#loc83 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":61:20)
+#loc84 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":63:35)
+#loc85 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":64:34)
+#loc86 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":45:34)
+#loc87 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":65:25)
+#loc88 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":65:37)
+#loc89 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/zm/czmwqln3pmd5itf5nbvnjurfzsxg24x3rxugagktrk6mefwreaah.py":65:4)
+#loc90 = loc(fused[#loc85, #loc86])

platform/aiml/models/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/triton_cache/NZ4RRAGQZEUI36VICEM2HXVDV76GVUUMDMXZI67YY57ZOH6LFYLQ/triton_red_fused__to_copy_add_embedding_mean_mul_pow_rsqrt_0.llir

@@ -0,0 +1,329 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+target datalayout = "e-p6:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64"
+
+@assertFunc_0 = internal constant [8 x i8] c"unknown\00"
+@assertFile_0 = internal constant [134 x i8] c"/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py\00"
+@assertMessage_0 = internal constant [40 x i8] c"index out of bounds: 0 <= tmp5 < 152064\00"
+@global_smem = external addrspace(3) global [0 x i8], align 16
+@.str = private unnamed_addr constant [11 x i8] c"__CUDA_FTZ\00", align 1
+
+; Function Attrs: noreturn
+declare !dbg !6 void @__assertfail(ptr, ptr, i32, ptr, i64) local_unnamed_addr #0
+
+define ptx_kernel void @triton_red_fused__to_copy_add_embedding_mean_mul_pow_rsqrt_0(ptr addrspace(1) %0, ptr addrspace(1) %1, ptr addrspace(1) %2, ptr addrspace(1) %3, ptr addrspace(1) %4, i32 %5, i32 %6, ptr addrspace(1) readnone captures(none) %7) local_unnamed_addr !dbg !10 {
+  %9 = tail call i32 @llvm.nvvm.read.ptx.sreg.ctaid.x(), !dbg !11
+  %10 = icmp slt i32 %9, %5, !dbg !12
+  %11 = sext i32 %9 to i64, !dbg !13
+  %12 = getelementptr i32, ptr addrspace(1) %0, i64 %11, !dbg !13
+  %13 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %12, i1 %10) #6, !dbg !14
+  %14 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %12, i1 %10) #6, !dbg !14
+  %15 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %12, i1 %10) #6, !dbg !14
+  %16 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %12, i1 %10) #6, !dbg !14
+  %17 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %12, i1 %10) #6, !dbg !14
+  %18 = sext i32 %17 to i64, !dbg !15
+  %19 = add nsw i64 %18, 152064, !dbg !16
+  %20 = icmp slt i32 %17, 0, !dbg !17
+  %21 = select i1 %20, i64 %19, i64 %18, !dbg !18
+  %22 = icmp ugt i64 %21, 152063, !dbg !19
+  %.not3 = and i1 %10, %22, !dbg !20
+  br i1 %.not3, label %146, label %.split.preheader, !dbg !21
+
+.split.preheader:                                 ; preds = %8
+  %23 = icmp slt i32 %16, 0, !dbg !17
+  %24 = sext i32 %16 to i64, !dbg !15
+  %25 = add nsw i64 %24, 152064, !dbg !16
+  %26 = select i1 %23, i64 %25, i64 %24, !dbg !18
+  %.idx = mul nsw i64 %26, 7168
+  %27 = getelementptr i8, ptr addrspace(1) %1, i64 %.idx
+  %28 = mul i32 %9, 3584, !dbg !22
+  %29 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !23
+  %30 = shl i32 %29, 2, !dbg !23
+  %31 = and i32 %30, 2044, !dbg !23
+  %32 = lshr i32 %29, 5, !dbg !23
+  %33 = and i32 %29, 31, !dbg !23
+  %34 = zext nneg i32 %31 to i64, !dbg !24
+  tail call void @llvm.nvvm.barrier0(), !dbg !21
+  %35 = getelementptr bfloat, ptr addrspace(1) %27, i64 %34, !dbg !25
+  %36 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, $2;\0A\09mov.u32 $1, $3;\0A\09@$5 ld.global.L1::evict_first.v2.b32 { $0, $1 }, [ $4 + 0 ];", "=r,=r,r,r,l,b"(i32 0, i32 0, ptr addrspace(1) %35, i1 %10) #6, !dbg !26
+  %37 = extractvalue { i32, i32 } %36, 0, !dbg !26
+  %38 = bitcast i32 %37 to <2 x bfloat>, !dbg !26
+  %39 = extractvalue { i32, i32 } %36, 1, !dbg !26
+  %40 = bitcast i32 %39 to <2 x bfloat>, !dbg !26
+  %41 = extractelement <2 x bfloat> %40, i64 0, !dbg !26
+  %42 = extractelement <2 x bfloat> %40, i64 1, !dbg !26
+  %43 = fpext bfloat %41 to float, !dbg !27
+  %44 = fpext bfloat %42 to float, !dbg !27
+  %45 = fmul float %43, %43, !dbg !28
+  %46 = fmul float %44, %44, !dbg !28
+  %47 = select i1 %10, float %45, float 0.000000e+00, !dbg !29
+  %48 = select i1 %10, float %46, float 0.000000e+00, !dbg !29
+  %49 = add i32 %31, %28, !dbg !30
+  %50 = sext i32 %49 to i64, !dbg !31
+  %51 = getelementptr bfloat, ptr addrspace(1) %3, i64 %50, !dbg !31
+  tail call void asm sideeffect "@$3 st.global.v2.b32 [ $2 + 0 ], { $0, $1 };", "r,r,l,b"(i32 %37, i32 %39, ptr addrspace(1) %51, i1 %10) #6, !dbg !32
+  %52 = or disjoint i64 %34, 2048, !dbg !33
+  %53 = icmp samesign ult i64 %52, 3584, !dbg !34
+  tail call void @llvm.nvvm.barrier0(), !dbg !21
+  %54 = getelementptr bfloat, ptr addrspace(1) %27, i64 %52, !dbg !25
+  %55 = and i1 %10, %53, !dbg !35
+  %56 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, $2;\0A\09mov.u32 $1, $3;\0A\09@$5 ld.global.L1::evict_first.v2.b32 { $0, $1 }, [ $4 + 0 ];", "=r,=r,r,r,l,b"(i32 0, i32 0, ptr addrspace(1) %54, i1 %55) #6, !dbg !26
+  %57 = extractvalue { i32, i32 } %56, 0, !dbg !26
+  %58 = bitcast i32 %57 to <2 x bfloat>, !dbg !26
+  %59 = extractvalue { i32, i32 } %56, 1, !dbg !26
+  %60 = bitcast i32 %59 to <2 x bfloat>, !dbg !26
+  %61 = extractelement <2 x bfloat> %60, i64 0, !dbg !26
+  %62 = extractelement <2 x bfloat> %60, i64 1, !dbg !26
+  %63 = fpext bfloat %61 to float, !dbg !27
+  %64 = fpext bfloat %62 to float, !dbg !27
+  %65 = fmul float %63, %63, !dbg !28
+  %66 = fmul float %64, %64, !dbg !28
+  %67 = fadd float %47, %65, !dbg !36
+  %68 = fadd float %48, %66, !dbg !36
+  %69 = fpext <2 x bfloat> %38 to <2 x float>, !dbg !27
+  %70 = fmul <2 x float> %69, %69, !dbg !28
+  %71 = insertelement <2 x i1> poison, i1 %10, i64 0, !dbg !29
+  %72 = shufflevector <2 x i1> %71, <2 x i1> poison, <2 x i32> zeroinitializer, !dbg !29
+  %73 = select <2 x i1> %72, <2 x float> %70, <2 x float> zeroinitializer, !dbg !29
+  %74 = fpext <2 x bfloat> %58 to <2 x float>, !dbg !27
+  %75 = fmul <2 x float> %74, %74, !dbg !28
+  %76 = fadd <2 x float> %73, %75, !dbg !36
+  %77 = insertelement <2 x i1> poison, i1 %55, i64 0, !dbg !29
+  %78 = shufflevector <2 x i1> %77, <2 x i1> poison, <2 x i32> zeroinitializer, !dbg !29
+  %79 = select <2 x i1> %78, <2 x float> %76, <2 x float> %73, !dbg !29
+  %80 = select i1 %55, float %67, float %47, !dbg !29
+  %81 = select i1 %55, float %68, float %48, !dbg !29
+  %82 = trunc nuw nsw i64 %52 to i32, !dbg !30
+  %83 = add i32 %28, %82, !dbg !30
+  %84 = sext i32 %83 to i64, !dbg !31
+  %85 = getelementptr bfloat, ptr addrspace(1) %3, i64 %84, !dbg !31
+  tail call void asm sideeffect "@$3 st.global.v2.b32 [ $2 + 0 ], { $0, $1 };", "r,r,l,b"(i32 %57, i32 %59, ptr addrspace(1) %85, i1 %55) #6, !dbg !32
+  %shift = shufflevector <2 x float> %79, <2 x float> poison, <2 x i32> <i32 1, i32 poison>, !dbg !37
+  %86 = fadd <2 x float> %79, %shift, !dbg !37
+  %87 = extractelement <2 x float> %86, i64 0, !dbg !37
+  %88 = fadd float %80, %87, !dbg !37
+  %89 = fadd float %81, %88, !dbg !37
+  %90 = bitcast float %89 to i32, !dbg !42
+  %91 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %90, i32 16, i32 31), !dbg !42
+  %92 = bitcast i32 %91 to float, !dbg !42
+  %93 = fadd float %89, %92, !dbg !37
+  %94 = bitcast float %93 to i32, !dbg !42
+  %95 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %94, i32 8, i32 31), !dbg !42
+  %96 = bitcast i32 %95 to float, !dbg !42
+  %97 = fadd float %93, %96, !dbg !37
+  %98 = bitcast float %97 to i32, !dbg !42
+  %99 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %98, i32 4, i32 31), !dbg !42
+  %100 = bitcast i32 %99 to float, !dbg !42
+  %101 = fadd float %97, %100, !dbg !37
+  %102 = bitcast float %101 to i32, !dbg !42
+  %103 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %102, i32 2, i32 31), !dbg !42
+  %104 = bitcast i32 %103 to float, !dbg !42
+  %105 = fadd float %101, %104, !dbg !37
+  %106 = bitcast float %105 to i32, !dbg !42
+  %107 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %106, i32 1, i32 31), !dbg !42
+  %108 = bitcast i32 %107 to float, !dbg !42
+  %109 = fadd float %105, %108, !dbg !37
+  %110 = and i32 %32, 15, !dbg !42
+  %111 = icmp eq i32 %33, 0, !dbg !42
+  %112 = zext nneg i32 %110 to i64, !dbg !42
+  %113 = getelementptr float, ptr addrspace(3) @global_smem, i64 %112, !dbg !42
+  %114 = bitcast float %109 to <1 x i32>, !dbg !42
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %113, <1 x i32> %114, i1 %111) #6, !dbg !42
+  tail call void @llvm.nvvm.barrier0(), !dbg !42
+  %115 = icmp slt i32 %29, 16, !dbg !42
+  %116 = sext i32 %29 to i64, !dbg !42
+  %117 = getelementptr float, ptr addrspace(3) @global_smem, i64 %116, !dbg !42
+  %118 = tail call i32 asm sideeffect "@$2 ld.shared.b32 $0, [ $1 + 0 ];", "=r,r,b"(ptr addrspace(3) %117, i1 %115) #6, !dbg !42
+  %119 = bitcast i32 %118 to float, !dbg !42
+  %120 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %118, i32 8, i32 31), !dbg !42
+  %121 = bitcast i32 %120 to float, !dbg !42
+  %122 = fadd float %119, %121, !dbg !37
+  %123 = bitcast float %122 to i32, !dbg !42
+  %124 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %123, i32 4, i32 31), !dbg !42
+  %125 = bitcast i32 %124 to float, !dbg !42
+  %126 = fadd float %122, %125, !dbg !37
+  %127 = bitcast float %126 to i32, !dbg !42
+  %128 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %127, i32 2, i32 31), !dbg !42
+  %129 = bitcast i32 %128 to float, !dbg !42
+  %130 = fadd float %126, %129, !dbg !37
+  %131 = bitcast float %130 to i32, !dbg !42
+  %132 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %131, i32 1, i32 31), !dbg !42
+  %133 = bitcast i32 %132 to float, !dbg !42
+  %134 = fadd float %130, %133, !dbg !37
+  %135 = and i32 %29, 15, !dbg !42
+  %136 = icmp eq i32 %135, 0, !dbg !42
+  %137 = and i1 %115, %136, !dbg !42
+  %138 = bitcast float %134 to <1 x i32>, !dbg !42
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %117, <1 x i32> %138, i1 %137) #6, !dbg !42
+  tail call void @llvm.nvvm.barrier0(), !dbg !42
+  %139 = load float, ptr addrspace(3) @global_smem, align 16, !dbg !42
+  %140 = tail call float @llvm.nvvm.div.full(float %139, float 3.584000e+03), !dbg !43
+  %141 = fadd float %140, 0x3EB0C6F7A0000000, !dbg !44
+  %142 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6, !dbg !45
+  %143 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6, !dbg !45
+  %144 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6, !dbg !45
+  %145 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #6, !dbg !45
+  %.not.i10 = icmp eq i32 %145, 0, !dbg !45
+  br i1 %.not.i10, label %149, label %147, !dbg !45
+
+146:                                              ; preds = %8
+  tail call void @__assertfail(ptr nonnull @assertMessage_0, ptr nonnull @assertFile_0, i32 41, ptr nonnull @assertFunc_0, i64 1), !dbg !21
+  unreachable, !dbg !21
+
+147:                                              ; preds = %.split.preheader
+  %148 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %141), !dbg !45
+  br label %__nv_rsqrtf.exit12, !dbg !45
+
+149:                                              ; preds = %.split.preheader
+  %150 = tail call float @llvm.nvvm.rsqrt.approx.f(float %141), !dbg !45
+  br label %__nv_rsqrtf.exit12, !dbg !45
+
+__nv_rsqrtf.exit12:                               ; preds = %147, %149
+  %.0.i11 = phi float [ %148, %147 ], [ %150, %149 ], !dbg !45
+  %151 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, $2;\0A\09mov.u32 $1, $3;\0A\09@$5 ld.global.L1::evict_first.v2.b32 { $0, $1 }, [ $4 + 0 ];", "=r,=r,r,r,l,b"(i32 0, i32 0, ptr addrspace(1) %51, i1 %10) #6, !dbg !46
+  %152 = extractvalue { i32, i32 } %151, 0, !dbg !46
+  %153 = bitcast i32 %152 to <2 x bfloat>, !dbg !46
+  %154 = extractvalue { i32, i32 } %151, 1, !dbg !46
+  %155 = bitcast i32 %154 to <2 x bfloat>, !dbg !46
+  %156 = getelementptr bfloat, ptr addrspace(1) %2, i64 %34, !dbg !47
+  %157 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, $2;\0A\09mov.u32 $1, $3;\0A\09@$5 ld.global.L1::evict_last.v2.b32 { $0, $1 }, [ $4 + 0 ];", "=r,=r,r,r,l,b"(i32 0, i32 0, ptr addrspace(1) %156, i1 true) #6, !dbg !48
+  %158 = extractvalue { i32, i32 } %157, 0, !dbg !48
+  %159 = bitcast i32 %158 to <2 x bfloat>, !dbg !48
+  %160 = extractvalue { i32, i32 } %157, 1, !dbg !48
+  %161 = bitcast i32 %160 to <2 x bfloat>, !dbg !48
+  %162 = getelementptr bfloat, ptr addrspace(1) %4, i64 %50, !dbg !49
+  %163 = fpext <2 x bfloat> %153 to <2 x float>, !dbg !50
+  %164 = fpext <2 x bfloat> %159 to <2 x float>, !dbg !51
+  %165 = insertelement <2 x float> poison, float %.0.i11, i64 0, !dbg !52
+  %166 = shufflevector <2 x float> %165, <2 x float> poison, <2 x i32> zeroinitializer, !dbg !52
+  %167 = fmul <2 x float> %166, %163, !dbg !52
+  %168 = fmul <2 x float> %167, %164, !dbg !53
+  %169 = fptrunc <2 x float> %168 to <2 x bfloat>, !dbg !54
+  %170 = fpext <2 x bfloat> %155 to <2 x float>, !dbg !50
+  %171 = fpext <2 x bfloat> %161 to <2 x float>, !dbg !51
+  %172 = fmul <2 x float> %166, %170, !dbg !52
+  %173 = fmul <2 x float> %172, %171, !dbg !53
+  %174 = fptrunc <2 x float> %173 to <2 x bfloat>, !dbg !54
+  %175 = bitcast <2 x bfloat> %169 to i32, !dbg !54
+  %176 = bitcast <2 x bfloat> %174 to i32, !dbg !54
+  tail call void asm sideeffect "@$3 st.global.v2.b32 [ $2 + 0 ], { $0, $1 };", "r,r,l,b"(i32 %175, i32 %176, ptr addrspace(1) %162, i1 %10) #6, !dbg !54
+  %177 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, $2;\0A\09mov.u32 $1, $3;\0A\09@$5 ld.global.L1::evict_first.v2.b32 { $0, $1 }, [ $4 + 0 ];", "=r,=r,r,r,l,b"(i32 0, i32 0, ptr addrspace(1) %85, i1 %55) #6, !dbg !46
+  %178 = extractvalue { i32, i32 } %177, 0, !dbg !46
+  %179 = bitcast i32 %178 to <2 x bfloat>, !dbg !46
+  %180 = extractvalue { i32, i32 } %177, 1, !dbg !46
+  %181 = bitcast i32 %180 to <2 x bfloat>, !dbg !46
+  %182 = getelementptr bfloat, ptr addrspace(1) %2, i64 %52, !dbg !47
+  %183 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, $2;\0A\09mov.u32 $1, $3;\0A\09@$5 ld.global.L1::evict_last.v2.b32 { $0, $1 }, [ $4 + 0 ];", "=r,=r,r,r,l,b"(i32 0, i32 0, ptr addrspace(1) %182, i1 %53) #6, !dbg !48
+  %184 = extractvalue { i32, i32 } %183, 0, !dbg !48
+  %185 = bitcast i32 %184 to <2 x bfloat>, !dbg !48
+  %186 = extractvalue { i32, i32 } %183, 1, !dbg !48
+  %187 = bitcast i32 %186 to <2 x bfloat>, !dbg !48
+  %188 = getelementptr bfloat, ptr addrspace(1) %4, i64 %84, !dbg !49
+  %189 = fpext <2 x bfloat> %179 to <2 x float>, !dbg !50
+  %190 = fpext <2 x bfloat> %185 to <2 x float>, !dbg !51
+  %191 = fmul <2 x float> %166, %189, !dbg !52
+  %192 = fmul <2 x float> %191, %190, !dbg !53
+  %193 = fptrunc <2 x float> %192 to <2 x bfloat>, !dbg !54
+  %194 = fpext <2 x bfloat> %181 to <2 x float>, !dbg !50
+  %195 = fpext <2 x bfloat> %187 to <2 x float>, !dbg !51
+  %196 = fmul <2 x float> %166, %194, !dbg !52
+  %197 = fmul <2 x float> %196, %195, !dbg !53
+  %198 = fptrunc <2 x float> %197 to <2 x bfloat>, !dbg !54
+  %199 = bitcast <2 x bfloat> %193 to i32, !dbg !54
+  %200 = bitcast <2 x bfloat> %198 to i32, !dbg !54
+  tail call void asm sideeffect "@$3 st.global.v2.b32 [ $2 + 0 ], { $0, $1 };", "r,r,l,b"(i32 %199, i32 %200, ptr addrspace(1) %188, i1 %55) #6, !dbg !54
+  ret void, !dbg !55
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.ctaid.x() #1
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.x() #1
+
+; Function Attrs: convergent nocallback nounwind memory(inaccessiblemem: readwrite)
+declare i32 @llvm.nvvm.shfl.sync.bfly.i32(i32, i32, i32, i32) #2
+
+; Function Attrs: convergent nocallback nounwind
+declare void @llvm.nvvm.barrier0() #3
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
+declare float @llvm.nvvm.div.full(float, float) #4
+
+declare i32 @__nvvm_reflect(ptr) local_unnamed_addr #5
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
+declare float @llvm.nvvm.rsqrt.approx.ftz.f(float) #4
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
+declare float @llvm.nvvm.rsqrt.approx.f(float) #4
+
+attributes #0 = { noreturn }
+attributes #1 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #2 = { convergent nocallback nounwind memory(inaccessiblemem: readwrite) }
+attributes #3 = { convergent nocallback nounwind }
+attributes #4 = { mustprogress nocallback nofree nosync nounwind willreturn memory(none) }
+attributes #5 = { "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #6 = { nounwind }
+
+!llvm.module.flags = !{!0, !1}
+!llvm.dbg.cu = !{!2}
+!nvvm.annotations = !{!4}
+!llvm.ident = !{!5}
+
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = !{i32 4, !"nvvm-reflect-ftz", i32 1}
+!2 = distinct !DICompileUnit(language: DW_LANG_C, file: !3, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: LineTablesOnly)
+!3 = !DIFile(filename: "clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py", directory: "/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo")
+!4 = !{ptr @triton_red_fused__to_copy_add_embedding_mean_mul_pow_rsqrt_0, !"reqntidx", i32 512}
+!5 = !{!"clang version 3.8.0 (tags/RELEASE_380/final)"}
+!6 = !DISubprogram(name: "__assertfail", linkageName: "__assertfail", scope: !7, file: !7, type: !8, spFlags: DISPFlagOptimized)
+!7 = !DIFile(filename: "<unknown>", directory: "")
+!8 = !DISubroutineType(cc: DW_CC_normal, types: !9)
+!9 = !{}
+!10 = distinct !DISubprogram(name: "triton_red_fused__to_copy_add_embedding_mean_mul_pow_rsqrt_0", linkageName: "triton_red_fused__to_copy_add_embedding_mean_mul_pow_rsqrt_0", scope: !3, file: !3, line: 18, type: !8, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !2)
+!11 = !DILocation(line: 22, column: 28, scope: !10)
+!12 = !DILocation(line: 24, column: 21, scope: !10)
+!13 = !DILocation(line: 28, column: 30, scope: !10)
+!14 = !DILocation(line: 28, column: 35, scope: !10)
+!15 = !DILocation(line: 36, column: 23, scope: !10)
+!16 = !DILocation(line: 38, column: 22, scope: !10)
+!17 = !DILocation(line: 39, column: 22, scope: !10)
+!18 = !DILocation(line: 40, column: 36, scope: !10)
+!19 = !DILocation(line: 41, column: 41, scope: !10)
+!20 = !DILocation(line: 42, column: 46, scope: !10)
+!21 = !DILocation(line: 41, column: 69, scope: !10)
+!22 = !DILocation(line: 48, column: 41, scope: !10)
+!23 = !DILocation(line: 25, column: 37, scope: !10)
+!24 = !DILocation(line: 30, column: 40, scope: !10)
+!25 = !DILocation(line: 42, column: 34, scope: !10)
+!26 = !DILocation(line: 42, column: 53, scope: !10)
+!27 = !DILocation(line: 42, column: 115, scope: !10)
+!28 = !DILocation(line: 44, column: 22, scope: !10)
+!29 = !DILocation(line: 47, column: 50, scope: !10)
+!30 = !DILocation(line: 48, column: 36, scope: !10)
+!31 = !DILocation(line: 48, column: 29, scope: !10)
+!32 = !DILocation(line: 48, column: 52, scope: !10)
+!33 = !DILocation(line: 31, column: 31, scope: !10)
+!34 = !DILocation(line: 32, column: 29, scope: !10)
+!35 = !DILocation(line: 42, column: 61, scope: !10)
+!36 = !DILocation(line: 46, column: 25, scope: !10)
+!37 = !DILocation(line: 256, column: 15, scope: !38, inlinedAt: !41)
+!38 = distinct !DILexicalBlockFile(scope: !40, file: !39, discriminator: 0)
+!39 = !DIFile(filename: "standard.py", directory: "/home/x/.local/lib/python3.12/site-packages/triton/language")
+!40 = distinct !DILexicalBlockFile(scope: !10, file: !39, discriminator: 0)
+!41 = !DILocation(line: 49, column: 27, scope: !10)
+!42 = !DILocation(line: 286, column: 36, scope: !40, inlinedAt: !41)
+!43 = !DILocation(line: 60, column: 25, scope: !10)
+!44 = !DILocation(line: 62, column: 24, scope: !10)
+!45 = !DILocation(line: 63, column: 32, scope: !10)
+!46 = !DILocation(line: 56, column: 53, scope: !10)
+!47 = !DILocation(line: 57, column: 35, scope: !10)
+!48 = !DILocation(line: 57, column: 42, scope: !10)
+!49 = !DILocation(line: 67, column: 29, scope: !10)
+!50 = !DILocation(line: 56, column: 115, scope: !10)
+!51 = !DILocation(line: 57, column: 95, scope: !10)
+!52 = !DILocation(line: 64, column: 24, scope: !10)
+!53 = !DILocation(line: 66, column: 24, scope: !10)
+!54 = !DILocation(line: 67, column: 53, scope: !10)
+!55 = !DILocation(line: 50, column: 4, scope: !10)

platform/aiml/models/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/triton_cache/NZ4RRAGQZEUI36VICEM2HXVDV76GVUUMDMXZI67YY57ZOH6LFYLQ/triton_red_fused__to_copy_add_embedding_mean_mul_pow_rsqrt_0.ttir

@@ -0,0 +1,164 @@
+#loc = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":18:0)
+#loc1 = loc(unknown)
+#loc36 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":49:27)
+#loc62 = loc(callsite(#loc1 at #loc36))
+module {
+  tt.func public @triton_red_fused__to_copy_add_embedding_mean_mul_pow_rsqrt_0(%arg0: !tt.ptr<i32> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":18:0), %arg1: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":18:0), %arg2: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":18:0), %arg3: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":18:0), %arg4: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":18:0), %arg5: i32 loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":18:0), %arg6: i32 {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":18:0)) attributes {noinline = false} {
+    %cst = arith.constant dense<3584> : tensor<1x1xi64> loc(#loc1)
+    %true = arith.constant true loc(#loc1)
+    %cst_0 = arith.constant dense<152064> : tensor<1x1xi64> loc(#loc1)
+    %cst_1 = arith.constant dense<0.000000e+00> : tensor<1x2048xbf16> loc(#loc1)
+    %cst_2 = arith.constant dense<0> : tensor<1x1xi64> loc(#loc1)
+    %c2048_i32 = arith.constant 2048 : i32 loc(#loc1)
+    %c3584_i32 = arith.constant 3584 : i32 loc(#loc1)
+    %c0_i32 = arith.constant 0 : i32 loc(#loc1)
+    %cst_3 = arith.constant dense<9.99999997E-7> : tensor<1x1xf32> loc(#loc1)
+    %cst_4 = arith.constant dense<3.584000e+03> : tensor<1x1xf32> loc(#loc1)
+    %cst_5 = arith.constant dense<3584> : tensor<1x2048xi32> loc(#loc1)
+    %cst_6 = arith.constant dense<0.000000e+00> : tensor<1x2048xf32> loc(#loc1)
+    %0 = tt.get_program_id x : i32 loc(#loc2)
+    %1 = arith.cmpi slt, %0, %arg5 : i32 loc(#loc3)
+    %2 = tt.splat %1 : i1 -> tensor<1x1xi1> loc(#loc3)
+    %3 = tt.make_range {end = 2048 : i32, start = 0 : i32} : tensor<2048xi32> loc(#loc4)
+    %4 = tt.expand_dims %3 {axis = 0 : i32} : tensor<2048xi32> -> tensor<1x2048xi32> loc(#loc5)
+    %5 = tt.addptr %arg0, %0 : !tt.ptr<i32>, i32 loc(#loc6)
+    %6 = tt.splat %5 : !tt.ptr<i32> -> tensor<1x1x!tt.ptr<i32>> loc(#loc6)
+    %7 = tt.load %6, %2 evictionPolicy = evict_last : tensor<1x1x!tt.ptr<i32>> loc(#loc7)
+    %8 = scf.for %arg7 = %c0_i32 to %c3584_i32 step %c2048_i32 iter_args(%arg8 = %cst_6) -> (tensor<1x2048xf32>)  : i32 {
+      %11 = tt.splat %arg7 : i32 -> tensor<1x2048xi32> loc(#loc9)
+      %12 = arith.addi %11, %4 : tensor<1x2048xi32> loc(#loc9)
+      %13 = arith.cmpi slt, %12, %cst_5 : tensor<1x2048xi32> loc(#loc10)
+      %14 = arith.extsi %7 : tensor<1x1xi32> to tensor<1x1xi64> loc(#loc11)
+      %15 = arith.addi %14, %cst_0 : tensor<1x1xi64> loc(#loc12)
+      %16 = arith.cmpi slt, %14, %cst_2 : tensor<1x1xi64> loc(#loc13)
+      %17 = arith.select %16, %15, %14 : tensor<1x1xi1>, tensor<1x1xi64> loc(#loc14)
+      %18 = arith.cmpi sge, %17, %cst_2 : tensor<1x1xi64> loc(#loc15)
+      %19 = arith.cmpi slt, %17, %cst_0 : tensor<1x1xi64> loc(#loc16)
+      %20 = arith.andi %18, %19 : tensor<1x1xi1> loc(#loc17)
+      %21 = arith.xori %1, %true : i1 loc(#loc18)
+      %22 = tt.splat %21 : i1 -> tensor<1x1xi1> loc(#loc18)
+      %23 = arith.ori %20, %22 : tensor<1x1xi1> loc(#loc19)
+      %24 = tt.broadcast %23 : tensor<1x1xi1> -> tensor<1x2048xi1> loc(#loc19)
+      tt.assert %24, "index out of bounds: 0 <= tmp5 < 152064" : tensor<1x2048xi1> loc(#loc20)
+      %25 = arith.muli %17, %cst : tensor<1x1xi64> loc(#loc21)
+      %26 = tt.broadcast %25 : tensor<1x1xi64> -> tensor<1x2048xi64> loc(#loc21)
+      %27 = arith.extsi %12 : tensor<1x2048xi32> to tensor<1x2048xi64> loc(#loc22)
+      %28 = arith.addi %27, %26 : tensor<1x2048xi64> loc(#loc22)
+      %29 = tt.splat %arg1 : !tt.ptr<bf16> -> tensor<1x2048x!tt.ptr<bf16>> loc(#loc23)
+      %30 = tt.addptr %29, %28 : tensor<1x2048x!tt.ptr<bf16>>, tensor<1x2048xi64> loc(#loc23)
+      %31 = tt.splat %1 : i1 -> tensor<1x2048xi1> loc(#loc59)
+      %32 = arith.andi %31, %13 : tensor<1x2048xi1> loc(#loc24)
+      %33 = tt.load %30, %32, %cst_1 evictionPolicy = evict_first : tensor<1x2048x!tt.ptr<bf16>> loc(#loc25)
+      %34 = arith.extf %33 : tensor<1x2048xbf16> to tensor<1x2048xf32> loc(#loc26)
+      %35 = arith.mulf %34, %34 : tensor<1x2048xf32> loc(#loc27)
+      %36 = arith.addf %arg8, %35 : tensor<1x2048xf32> loc(#loc28)
+      %37 = arith.select %32, %36, %arg8 : tensor<1x2048xi1>, tensor<1x2048xf32> loc(#loc29)
+      %38 = arith.muli %0, %c3584_i32 : i32 loc(#loc30)
+      %39 = tt.splat %38 : i32 -> tensor<1x2048xi32> loc(#loc60)
+      %40 = arith.addi %12, %39 : tensor<1x2048xi32> loc(#loc31)
+      %41 = tt.splat %arg3 : !tt.ptr<bf16> -> tensor<1x2048x!tt.ptr<bf16>> loc(#loc32)
+      %42 = tt.addptr %41, %40 : tensor<1x2048x!tt.ptr<bf16>>, tensor<1x2048xi32> loc(#loc32)
+      %43 = arith.truncf %34 : tensor<1x2048xf32> to tensor<1x2048xbf16> loc(#loc33)
+      tt.store %42, %43, %32 : tensor<1x2048x!tt.ptr<bf16>> loc(#loc33)
+      scf.yield %37 : tensor<1x2048xf32> loc(#loc34)
+    } loc(#loc8)
+    %9 = "tt.reduce"(%8) <{axis = 1 : i32}> ({
+    ^bb0(%arg7: f32 loc(callsite(#loc1 at #loc36)), %arg8: f32 loc(callsite(#loc1 at #loc36))):
+      %11 = arith.addf %arg7, %arg8 : f32 loc(#loc66)
+      tt.reduce.return %11 : f32 loc(#loc61)
+    }) : (tensor<1x2048xf32>) -> tensor<1xf32> loc(#loc61)
+    %10 = tt.expand_dims %9 {axis = 1 : i32} : tensor<1xf32> -> tensor<1x1xf32> loc(#loc38)
+    scf.for %arg7 = %c0_i32 to %c3584_i32 step %c2048_i32  : i32 {
+      %11 = tt.splat %arg7 : i32 -> tensor<1x2048xi32> loc(#loc40)
+      %12 = arith.addi %11, %4 : tensor<1x2048xi32> loc(#loc40)
+      %13 = arith.cmpi slt, %12, %cst_5 : tensor<1x2048xi32> loc(#loc41)
+      %14 = arith.muli %0, %c3584_i32 : i32 loc(#loc42)
+      %15 = tt.splat %14 : i32 -> tensor<1x2048xi32> loc(#loc64)
+      %16 = arith.addi %12, %15 : tensor<1x2048xi32> loc(#loc43)
+      %17 = tt.splat %arg3 : !tt.ptr<bf16> -> tensor<1x2048x!tt.ptr<bf16>> loc(#loc44)
+      %18 = tt.addptr %17, %16 : tensor<1x2048x!tt.ptr<bf16>>, tensor<1x2048xi32> loc(#loc44)
+      %19 = tt.splat %1 : i1 -> tensor<1x2048xi1> loc(#loc65)
+      %20 = arith.andi %13, %19 : tensor<1x2048xi1> loc(#loc45)
+      %21 = tt.load %18, %20, %cst_1 evictionPolicy = evict_first : tensor<1x2048x!tt.ptr<bf16>> loc(#loc46)
+      %22 = arith.extf %21 : tensor<1x2048xbf16> to tensor<1x2048xf32> loc(#loc47)
+      %23 = tt.splat %arg2 : !tt.ptr<bf16> -> tensor<1x2048x!tt.ptr<bf16>> loc(#loc48)
+      %24 = tt.addptr %23, %12 : tensor<1x2048x!tt.ptr<bf16>>, tensor<1x2048xi32> loc(#loc48)
+      %25 = tt.load %24, %13, %cst_1 evictionPolicy = evict_last : tensor<1x2048x!tt.ptr<bf16>> loc(#loc49)
+      %26 = arith.extf %25 : tensor<1x2048xbf16> to tensor<1x2048xf32> loc(#loc50)
+      %27 = arith.divf %10, %cst_4 : tensor<1x1xf32> loc(#loc51)
+      %28 = arith.addf %27, %cst_3 : tensor<1x1xf32> loc(#loc52)
+      %29 = tt.extern_elementwise %28 {libname = "", libpath = "", pure = true, symbol = "__nv_rsqrtf"} : (tensor<1x1xf32>) -> tensor<1x1xf32> loc(#loc53)
+      %30 = tt.broadcast %29 : tensor<1x1xf32> -> tensor<1x2048xf32> loc(#loc54)
+      %31 = arith.mulf %22, %30 : tensor<1x2048xf32> loc(#loc54)
+      %32 = arith.mulf %31, %26 : tensor<1x2048xf32> loc(#loc55)
+      %33 = tt.splat %arg4 : !tt.ptr<bf16> -> tensor<1x2048x!tt.ptr<bf16>> loc(#loc56)
+      %34 = tt.addptr %33, %16 : tensor<1x2048x!tt.ptr<bf16>>, tensor<1x2048xi32> loc(#loc56)
+      %35 = arith.truncf %32 : tensor<1x2048xf32> to tensor<1x2048xbf16> loc(#loc57)
+      tt.store %34, %35, %20 : tensor<1x2048x!tt.ptr<bf16>> loc(#loc57)
+    } loc(#loc39)
+    tt.return loc(#loc58)
+  } loc(#loc)
+} loc(#loc)
+#loc2 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":22:28)
+#loc3 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":24:21)
+#loc4 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":25:27)
+#loc5 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":25:37)
+#loc6 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":28:30)
+#loc7 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":28:35)
+#loc8 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":30:40)
+#loc9 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":31:31)
+#loc10 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":32:29)
+#loc11 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":36:23)
+#loc12 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":38:22)
+#loc13 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":39:22)
+#loc14 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":40:36)
+#loc15 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":41:32)
+#loc16 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":41:48)
+#loc17 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":41:41)
+#loc18 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":41:61)
+#loc19 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":41:59)
+#loc20 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":41:69)
+#loc21 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":42:46)
+#loc22 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":42:41)
+#loc23 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":42:34)
+#loc24 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":42:61)
+#loc25 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":42:53)
+#loc26 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":42:115)
+#loc27 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":44:22)
+#loc28 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":46:25)
+#loc29 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":47:50)
+#loc30 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":48:41)
+#loc31 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":48:36)
+#loc32 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":48:29)
+#loc33 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":48:52)
+#loc34 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":48:8)
+#loc35 = loc("/home/x/.local/lib/python3.12/site-packages/triton/language/standard.py":286:36)
+#loc37 = loc("/home/x/.local/lib/python3.12/site-packages/triton/language/standard.py":256:15)
+#loc38 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":49:30)
+#loc39 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":50:40)
+#loc40 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":51:31)
+#loc41 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":52:29)
+#loc42 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":56:48)
+#loc43 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":56:43)
+#loc44 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":56:36)
+#loc45 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":56:63)
+#loc46 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":56:53)
+#loc47 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":56:115)
+#loc48 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":57:35)
+#loc49 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":57:42)
+#loc50 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":57:95)
+#loc51 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":60:25)
+#loc52 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":62:24)
+#loc53 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":63:32)
+#loc54 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":64:24)
+#loc55 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":66:24)
+#loc56 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":67:29)
+#loc57 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":67:53)
+#loc58 = loc("/home/x/.cache/vllm/torch_compile_cache/069ce3ea2b/rank_0_0/inductor_cache/lo/clovpxsk3xeovrpue7dyfqa3cpqyo2mprscekt4hx7gmplpafuyn.py":50:4)
+#loc59 = loc(fused[#loc24, #loc3])
+#loc60 = loc(fused[#loc31, #loc30])
+#loc61 = loc(callsite(#loc35 at #loc36))
+#loc63 = loc(callsite(#loc37 at #loc35))
+#loc64 = loc(fused[#loc43, #loc42])
+#loc65 = loc(fused[#loc45, #loc3])
+#loc66 = loc(callsite(#loc63 at #loc36))

platform/aiml/models/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/2GRAEIQ7XVOGHZYKSSUSTY5FB5QDTTCHSNTG7532JOJYAR57HZGA/triton_red_fused__to_copy_mean_pow_3.json

@@ -0,0 +1 @@
+{"hash": "d1a202221fbd5c63e70a94a929e3a50f6039cc4793666ff77a4b938047bf3e4c", "target": {"backend": "cuda", "arch": 90, "warp_size": 32}, "num_warps": 8, "num_ctas": 1, "num_stages": 1, "num_buffers_warp_spec": 0, "num_consumer_groups": 0, "reg_dec_producer": 0, "reg_inc_consumer": 0, "maxnreg": null, "cluster_dims": [1, 1, 1], "ptx_version": null, "enable_fp_fusion": true, "launch_cooperative_grid": false, "supported_fp8_dtypes": ["fp8e4b15", "fp8e4nv", "fp8e5"], "deprecated_fp8_dtypes": ["fp8e4b15"], "default_dot_input_precision": "tf32", "allowed_dot_input_precisions": ["tf32", "tf32x3", "ieee"], "max_num_imprecise_acc_default": 1073741824, "extern_libs": [["libdevice", "/home/x/hfenv/lib/python3.12/site-packages/triton/backends/nvidia/lib/libdevice.10.bc"]], "debug": true, "backend_name": "cuda", "sanitize_overflow": false, "arch": "sm90", "triton_version": "3.3.1", "shared": 32, "tmem_size": 0, "global_scratch_size": 0, "global_scratch_align": 1, "name": "triton_red_fused__to_copy_mean_pow_3"}

platform/aiml/models/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/2GRAEIQ7XVOGHZYKSSUSTY5FB5QDTTCHSNTG7532JOJYAR57HZGA/triton_red_fused__to_copy_mean_pow_3.ttir

@@ -0,0 +1,86 @@
+#loc = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/q6/cq6mzwfpigp5chrryoby5ai6qeaqai4pkb6ivf4fa27c2pdxyi6a.py":18:0)
+#loc1 = loc(unknown)
+#loc25 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/q6/cq6mzwfpigp5chrryoby5ai6qeaqai4pkb6ivf4fa27c2pdxyi6a.py":43:25)
+#loc32 = loc(callsite(#loc1 at #loc25))
+module {
+  tt.func public @triton_red_fused__to_copy_mean_pow_3(%arg0: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/q6/cq6mzwfpigp5chrryoby5ai6qeaqai4pkb6ivf4fa27c2pdxyi6a.py":18:0), %arg1: !tt.ptr<f32> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/q6/cq6mzwfpigp5chrryoby5ai6qeaqai4pkb6ivf4fa27c2pdxyi6a.py":18:0), %arg2: i32 loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/q6/cq6mzwfpigp5chrryoby5ai6qeaqai4pkb6ivf4fa27c2pdxyi6a.py":18:0), %arg3: i32 {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/q6/cq6mzwfpigp5chrryoby5ai6qeaqai4pkb6ivf4fa27c2pdxyi6a.py":18:0)) attributes {noinline = false} {
+    %cst = arith.constant dense<0.000000e+00> : tensor<8x128xbf16> loc(#loc1)
+    %cst_0 = arith.constant dense<7168> : tensor<8x1xi32> loc(#loc1)
+    %cst_1 = arith.constant dense<128> : tensor<8x1xi32> loc(#loc1)
+    %cst_2 = arith.constant dense<128> : tensor<1x128xi32> loc(#loc1)
+    %cst_3 = arith.constant dense<0.000000e+00> : tensor<8x128xf32> loc(#loc1)
+    %cst_4 = arith.constant dense<40> : tensor<8x1xi32> loc(#loc1)
+    %c8_i32 = arith.constant 8 : i32 loc(#loc1)
+    %0 = tt.get_program_id x : i32 loc(#loc2)
+    %1 = arith.muli %0, %c8_i32 : i32 loc(#loc3)
+    %2 = tt.make_range {end = 8 : i32, start = 0 : i32} : tensor<8xi32> loc(#loc4)
+    %3 = tt.expand_dims %2 {axis = 1 : i32} : tensor<8xi32> -> tensor<8x1xi32> loc(#loc5)
+    %4 = tt.splat %1 : i32 -> tensor<8x1xi32> loc(#loc6)
+    %5 = arith.addi %4, %3 : tensor<8x1xi32> loc(#loc6)
+    %6 = tt.splat %arg2 : i32 -> tensor<8x1xi32> loc(#loc7)
+    %7 = arith.cmpi slt, %5, %6 : tensor<8x1xi32> loc(#loc7)
+    %8 = tt.make_range {end = 128 : i32, start = 0 : i32} : tensor<128xi32> loc(#loc8)
+    %9 = tt.expand_dims %8 {axis = 0 : i32} : tensor<128xi32> -> tensor<1x128xi32> loc(#loc9)
+    %10 = arith.remsi %5, %cst_4 : tensor<8x1xi32> loc(#loc10)
+    %11 = arith.divsi %5, %cst_4 : tensor<8x1xi32> loc(#loc11)
+    %12 = arith.cmpi slt, %9, %cst_2 : tensor<1x128xi32> loc(#loc12)
+    %13 = arith.muli %10, %cst_1 : tensor<8x1xi32> loc(#loc13)
+    %14 = tt.broadcast %9 : tensor<1x128xi32> -> tensor<8x128xi32> loc(#loc14)
+    %15 = tt.broadcast %13 : tensor<8x1xi32> -> tensor<8x128xi32> loc(#loc14)
+    %16 = arith.addi %14, %15 : tensor<8x128xi32> loc(#loc14)
+    %17 = arith.muli %11, %cst_0 : tensor<8x1xi32> loc(#loc15)
+    %18 = tt.broadcast %17 : tensor<8x1xi32> -> tensor<8x128xi32> loc(#loc16)
+    %19 = arith.addi %16, %18 : tensor<8x128xi32> loc(#loc16)
+    %20 = tt.splat %arg0 : !tt.ptr<bf16> -> tensor<8x128x!tt.ptr<bf16>> loc(#loc17)
+    %21 = tt.addptr %20, %19 : tensor<8x128x!tt.ptr<bf16>>, tensor<8x128xi32> loc(#loc17)
+    %22 = tt.broadcast %7 : tensor<8x1xi1> -> tensor<8x128xi1> loc(#loc18)
+    %23 = tt.broadcast %12 : tensor<1x128xi1> -> tensor<8x128xi1> loc(#loc18)
+    %24 = arith.andi %22, %23 : tensor<8x128xi1> loc(#loc18)
+    %25 = tt.load %21, %24, %cst evictionPolicy = evict_first : tensor<8x128x!tt.ptr<bf16>> loc(#loc19)
+    %26 = arith.extf %25 : tensor<8x128xbf16> to tensor<8x128xf32> loc(#loc20)
+    %27 = arith.mulf %26, %26 : tensor<8x128xf32> loc(#loc21)
+    %28 = arith.addf %27, %cst_3 : tensor<8x128xf32> loc(#loc22)
+    %29 = arith.select %24, %28, %cst_3 : tensor<8x128xi1>, tensor<8x128xf32> loc(#loc23)
+    %30 = "tt.reduce"(%29) <{axis = 1 : i32}> ({
+    ^bb0(%arg4: f32 loc(callsite(#loc1 at #loc25)), %arg5: f32 loc(callsite(#loc1 at #loc25))):
+      %34 = arith.addf %arg4, %arg5 : f32 loc(#loc34)
+      tt.reduce.return %34 : f32 loc(#loc31)
+    }) : (tensor<8x128xf32>) -> tensor<8xf32> loc(#loc31)
+    %31 = tt.expand_dims %30 {axis = 1 : i32} : tensor<8xf32> -> tensor<8x1xf32> loc(#loc27)
+    %32 = tt.splat %arg1 : !tt.ptr<f32> -> tensor<8x1x!tt.ptr<f32>> loc(#loc28)
+    %33 = tt.addptr %32, %5 : tensor<8x1x!tt.ptr<f32>>, tensor<8x1xi32> loc(#loc28)
+    tt.store %33, %31, %7 : tensor<8x1x!tt.ptr<f32>> loc(#loc29)
+    tt.return loc(#loc30)
+  } loc(#loc)
+} loc(#loc)
+#loc2 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/q6/cq6mzwfpigp5chrryoby5ai6qeaqai4pkb6ivf4fa27c2pdxyi6a.py":22:28)
+#loc3 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/q6/cq6mzwfpigp5chrryoby5ai6qeaqai4pkb6ivf4fa27c2pdxyi6a.py":22:33)
+#loc4 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/q6/cq6mzwfpigp5chrryoby5ai6qeaqai4pkb6ivf4fa27c2pdxyi6a.py":23:36)
+#loc5 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/q6/cq6mzwfpigp5chrryoby5ai6qeaqai4pkb6ivf4fa27c2pdxyi6a.py":23:44)
+#loc6 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/q6/cq6mzwfpigp5chrryoby5ai6qeaqai4pkb6ivf4fa27c2pdxyi6a.py":23:23)
+#loc7 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/q6/cq6mzwfpigp5chrryoby5ai6qeaqai4pkb6ivf4fa27c2pdxyi6a.py":24:21)
+#loc8 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/q6/cq6mzwfpigp5chrryoby5ai6qeaqai4pkb6ivf4fa27c2pdxyi6a.py":25:27)
+#loc9 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/q6/cq6mzwfpigp5chrryoby5ai6qeaqai4pkb6ivf4fa27c2pdxyi6a.py":25:37)
+#loc10 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/q6/cq6mzwfpigp5chrryoby5ai6qeaqai4pkb6ivf4fa27c2pdxyi6a.py":27:19)
+#loc11 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/q6/cq6mzwfpigp5chrryoby5ai6qeaqai4pkb6ivf4fa27c2pdxyi6a.py":28:19)
+#loc12 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/q6/cq6mzwfpigp5chrryoby5ai6qeaqai4pkb6ivf4fa27c2pdxyi6a.py":33:29)
+#loc13 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/q6/cq6mzwfpigp5chrryoby5ai6qeaqai4pkb6ivf4fa27c2pdxyi6a.py":37:45)
+#loc14 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/q6/cq6mzwfpigp5chrryoby5ai6qeaqai4pkb6ivf4fa27c2pdxyi6a.py":37:41)
+#loc15 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/q6/cq6mzwfpigp5chrryoby5ai6qeaqai4pkb6ivf4fa27c2pdxyi6a.py":37:55)
+#loc16 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/q6/cq6mzwfpigp5chrryoby5ai6qeaqai4pkb6ivf4fa27c2pdxyi6a.py":37:50)
+#loc17 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/q6/cq6mzwfpigp5chrryoby5ai6qeaqai4pkb6ivf4fa27c2pdxyi6a.py":37:34)
+#loc18 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/q6/cq6mzwfpigp5chrryoby5ai6qeaqai4pkb6ivf4fa27c2pdxyi6a.py":37:68)
+#loc19 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/q6/cq6mzwfpigp5chrryoby5ai6qeaqai4pkb6ivf4fa27c2pdxyi6a.py":37:60)
+#loc20 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/q6/cq6mzwfpigp5chrryoby5ai6qeaqai4pkb6ivf4fa27c2pdxyi6a.py":37:122)
+#loc21 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/q6/cq6mzwfpigp5chrryoby5ai6qeaqai4pkb6ivf4fa27c2pdxyi6a.py":39:22)
+#loc22 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/q6/cq6mzwfpigp5chrryoby5ai6qeaqai4pkb6ivf4fa27c2pdxyi6a.py":41:23)
+#loc23 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/q6/cq6mzwfpigp5chrryoby5ai6qeaqai4pkb6ivf4fa27c2pdxyi6a.py":42:48)
+#loc24 = loc("/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py":286:36)
+#loc26 = loc("/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py":256:15)
+#loc27 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/q6/cq6mzwfpigp5chrryoby5ai6qeaqai4pkb6ivf4fa27c2pdxyi6a.py":43:28)
+#loc28 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/q6/cq6mzwfpigp5chrryoby5ai6qeaqai4pkb6ivf4fa27c2pdxyi6a.py":44:25)
+#loc29 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/q6/cq6mzwfpigp5chrryoby5ai6qeaqai4pkb6ivf4fa27c2pdxyi6a.py":44:36)
+#loc30 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/q6/cq6mzwfpigp5chrryoby5ai6qeaqai4pkb6ivf4fa27c2pdxyi6a.py":44:4)
+#loc31 = loc(callsite(#loc24 at #loc25))
+#loc33 = loc(callsite(#loc26 at #loc24))
+#loc34 = loc(callsite(#loc33 at #loc25))

platform/aiml/models/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/45LDULZ442N5JFUIVYNUNADONVNIWAD3NTIV4IAI7XAWL753KBVQ/triton_poi_fused_add_mul_sub_5.json

@@ -0,0 +1 @@
+{"hash": "e7563a2f3ce69bd49688ae1b46806e6d5a8b007b6cd15e2008fdc165ffbb506b", "target": {"backend": "cuda", "arch": 90, "warp_size": 32}, "num_warps": 8, "num_ctas": 1, "num_stages": 1, "num_buffers_warp_spec": 0, "num_consumer_groups": 0, "reg_dec_producer": 0, "reg_inc_consumer": 0, "maxnreg": null, "cluster_dims": [1, 1, 1], "ptx_version": null, "enable_fp_fusion": true, "launch_cooperative_grid": false, "supported_fp8_dtypes": ["fp8e4b15", "fp8e4nv", "fp8e5"], "deprecated_fp8_dtypes": ["fp8e4b15"], "default_dot_input_precision": "tf32", "allowed_dot_input_precisions": ["tf32", "tf32x3", "ieee"], "max_num_imprecise_acc_default": 1073741824, "extern_libs": [["libdevice", "/home/x/hfenv/lib/python3.12/site-packages/triton/backends/nvidia/lib/libdevice.10.bc"]], "debug": true, "backend_name": "cuda", "sanitize_overflow": false, "arch": "sm90", "triton_version": "3.3.1", "shared": 0, "tmem_size": 0, "global_scratch_size": 0, "global_scratch_align": 1, "name": "triton_poi_fused_add_mul_sub_5"}

platform/aiml/models/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/45LDULZ442N5JFUIVYNUNADONVNIWAD3NTIV4IAI7XAWL753KBVQ/triton_poi_fused_add_mul_sub_5.llir

@@ -0,0 +1,297 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+target datalayout = "e-p3:32:32-p4:32:32-p5:32:32-p6:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64"
+
+@assertFunc_0 = internal constant [8 x i8] c"unknown\00"
+@assertFile_0 = internal constant [134 x i8] c"/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py\00"
+@assertMessage_0 = internal constant [41 x i8] c"index out of bounds: 0 <= tmp16 < 131072\00"
+@.str = private unnamed_addr constant [11 x i8] c"__CUDA_FTZ\00", align 1
+
+; Function Attrs: noreturn
+declare !dbg !6 void @__assertfail(ptr, ptr, i32, ptr, i64) local_unnamed_addr #0
+
+define ptx_kernel void @triton_poi_fused_add_mul_sub_5(ptr addrspace(1) %0, ptr addrspace(1) %1, ptr addrspace(1) %2, ptr addrspace(1) %3, ptr addrspace(1) %4, ptr addrspace(1) %5, ptr addrspace(1) %6, i32 %7, ptr addrspace(1) readnone captures(none) %8) local_unnamed_addr !dbg !10 {
+  %10 = tail call i32 @llvm.nvvm.read.ptx.sreg.ctaid.x(), !dbg !11
+  %11 = shl i32 %10, 9, !dbg !12
+  %12 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !13
+  %13 = shl i32 %12, 1, !dbg !13
+  %14 = and i32 %13, 510, !dbg !13
+  %15 = or disjoint i32 %14, %11, !dbg !14
+  %16 = or disjoint i32 %15, 1, !dbg !14
+  %17 = icmp slt i32 %15, %7, !dbg !15
+  %18 = sdiv i32 %15, 64, !dbg !16
+  %19 = mul i32 %18, 64, !dbg !17
+  %.decomposed = sub i32 %15, %19, !dbg !17
+  %20 = srem i32 %16, 64, !dbg !17
+  %21 = srem i32 %18, 40, !dbg !18
+  %22 = sdiv i32 %15, 2560, !dbg !19
+  %23 = shl nsw i32 %21, 7, !dbg !20
+  %24 = mul i32 %22, 7168, !dbg !21
+  %25 = add i32 %23, %24, !dbg !22
+  %26 = add i32 %25, %.decomposed, !dbg !23
+  %27 = sext i32 %26 to i64, !dbg !24
+  %28 = getelementptr bfloat, ptr addrspace(1) %0, i64 %27, !dbg !24
+  %29 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %28, i1 %17) #5, !dbg !25
+  %30 = sext i32 %18 to i64, !dbg !26
+  %31 = getelementptr float, ptr addrspace(1) %1, i64 %30, !dbg !26
+  %32 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %31, i1 %17) #5, !dbg !27
+  %33 = bitcast i32 %32 to float, !dbg !27
+  %34 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %31, i1 %17) #5, !dbg !27
+  %35 = bitcast i32 %34 to float, !dbg !27
+  %36 = sext i32 %.decomposed to i64, !dbg !28
+  %37 = getelementptr bfloat, ptr addrspace(1) %2, i64 %36, !dbg !28
+  %38 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %37, i1 %17) #5, !dbg !29
+  %39 = sext i32 %22 to i64, !dbg !30
+  %40 = getelementptr i64, ptr addrspace(1) %3, i64 %39, !dbg !30
+  %41 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %40, i1 %17) #5, !dbg !31
+  %42 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %40, i1 %17) #5, !dbg !31
+  %43 = add nsw i32 %.decomposed, 64, !dbg !32
+  %44 = add i32 %25, %43, !dbg !33
+  %45 = or disjoint i32 %25, 64, !dbg !34
+  %46 = add nsw i32 %45, %20, !dbg !33
+  %47 = sext i32 %44 to i64, !dbg !35
+  %48 = getelementptr bfloat, ptr addrspace(1) %0, i64 %47, !dbg !35
+  %49 = sext i32 %46 to i64, !dbg !35
+  %50 = getelementptr bfloat, ptr addrspace(1) %0, i64 %49, !dbg !35
+  %51 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.b16 { $0 }, [ $1 + 0 ];", "=c,l,b"(ptr addrspace(1) %48, i1 %17) #5, !dbg !36
+  %52 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.b16 { $0 }, [ $1 + 0 ];", "=c,l,b"(ptr addrspace(1) %50, i1 %17) #5, !dbg !36
+  %53 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %31, i1 %17) #5, !dbg !37
+  %54 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %31, i1 %17) #5, !dbg !37
+  %55 = zext nneg i32 %43 to i64, !dbg !38
+  %56 = getelementptr bfloat, ptr addrspace(1) %2, i64 %55, !dbg !38
+  %57 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %56, i1 %17) #5, !dbg !39
+  %58 = tail call float @llvm.nvvm.div.full(float %33, float 1.280000e+02), !dbg !40
+  %59 = tail call float @llvm.nvvm.div.full(float %35, float 1.280000e+02), !dbg !40
+  %60 = fadd float %58, 0x3EB0C6F7A0000000, !dbg !41
+  %61 = fadd float %59, 0x3EB0C6F7A0000000, !dbg !41
+  %62 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5, !dbg !42
+  %.not.i = icmp eq i32 %62, 0, !dbg !42
+  br i1 %.not.i, label %65, label %63, !dbg !42
+
+63:                                               ; preds = %9
+  %64 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %60), !dbg !42
+  br label %__nv_rsqrtf.exit, !dbg !42
+
+65:                                               ; preds = %9
+  %66 = tail call float @llvm.nvvm.rsqrt.approx.f(float %60), !dbg !42
+  br label %__nv_rsqrtf.exit, !dbg !42
+
+__nv_rsqrtf.exit:                                 ; preds = %63, %65
+  %.0.i = phi float [ %64, %63 ], [ %66, %65 ], !dbg !42
+  %67 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5, !dbg !42
+  %.not.i2 = icmp eq i32 %67, 0, !dbg !42
+  br i1 %.not.i2, label %70, label %68, !dbg !42
+
+68:                                               ; preds = %__nv_rsqrtf.exit
+  %69 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %61), !dbg !42
+  br label %__nv_rsqrtf.exit4, !dbg !42
+
+70:                                               ; preds = %__nv_rsqrtf.exit
+  %71 = tail call float @llvm.nvvm.rsqrt.approx.f(float %61), !dbg !42
+  br label %__nv_rsqrtf.exit4, !dbg !42
+
+__nv_rsqrtf.exit4:                                ; preds = %68, %70
+  %.0.i3 = phi float [ %69, %68 ], [ %71, %70 ], !dbg !42
+  %72 = lshr i64 %41, 46, !dbg !43
+  %73 = and i64 %72, 131072, !dbg !43
+  %74 = add i64 %73, %41, !dbg !43
+  %75 = icmp ugt i64 %74, 131071, !dbg !44
+  %.not1 = and i1 %17, %75, !dbg !45
+  br i1 %.not1, label %76, label %77, !dbg !45
+
+76:                                               ; preds = %__nv_rsqrtf.exit4
+  tail call void @__assertfail(ptr nonnull @assertMessage_0, ptr nonnull @assertFile_0, i32 46, ptr nonnull @assertFunc_0, i64 1), !dbg !45
+  unreachable, !dbg !45
+
+77:                                               ; preds = %__nv_rsqrtf.exit4
+  %78 = bitcast i32 %54 to float, !dbg !37
+  %79 = bitcast i32 %53 to float, !dbg !37
+  tail call void @llvm.nvvm.barrier0(), !dbg !45
+  %.idx = shl i64 %74, 8, !dbg !46
+  %80 = getelementptr i8, ptr addrspace(1) %4, i64 %.idx, !dbg !46
+  %81 = getelementptr bfloat, ptr addrspace(1) %80, i64 %36, !dbg !46
+  %82 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %81, i1 %17) #5, !dbg !47
+  %83 = tail call float @llvm.nvvm.div.full(float %79, float 1.280000e+02), !dbg !48
+  %84 = tail call float @llvm.nvvm.div.full(float %78, float 1.280000e+02), !dbg !48
+  %85 = fadd float %83, 0x3EB0C6F7A0000000, !dbg !49
+  %86 = fadd float %84, 0x3EB0C6F7A0000000, !dbg !49
+  %87 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5, !dbg !50
+  %.not.i5 = icmp eq i32 %87, 0, !dbg !50
+  br i1 %.not.i5, label %90, label %88, !dbg !50
+
+88:                                               ; preds = %77
+  %89 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %85), !dbg !50
+  br label %__nv_rsqrtf.exit7, !dbg !50
+
+90:                                               ; preds = %77
+  %91 = tail call float @llvm.nvvm.rsqrt.approx.f(float %85), !dbg !50
+  br label %__nv_rsqrtf.exit7, !dbg !50
+
+__nv_rsqrtf.exit7:                                ; preds = %88, %90
+  %.0.i6 = phi float [ %89, %88 ], [ %91, %90 ], !dbg !50
+  %92 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5, !dbg !50
+  %.not.i8 = icmp eq i32 %92, 0, !dbg !50
+  br i1 %.not.i8, label %95, label %93, !dbg !50
+
+93:                                               ; preds = %__nv_rsqrtf.exit7
+  %94 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %86), !dbg !50
+  br label %__nv_rsqrtf.exit10, !dbg !50
+
+95:                                               ; preds = %__nv_rsqrtf.exit7
+  %96 = tail call float @llvm.nvvm.rsqrt.approx.f(float %86), !dbg !50
+  br label %__nv_rsqrtf.exit10, !dbg !50
+
+__nv_rsqrtf.exit10:                               ; preds = %93, %95
+  %.0.i9 = phi float [ %94, %93 ], [ %96, %95 ], !dbg !50
+  %97 = bitcast i32 %29 to <2 x bfloat>, !dbg !25
+  %98 = bitcast i32 %38 to <2 x bfloat>, !dbg !29
+  %99 = bitcast i32 %82 to <2 x bfloat>, !dbg !47
+  %100 = insertelement <2 x i16> poison, i16 %51, i64 0, !dbg !36
+  %101 = insertelement <2 x i16> %100, i16 %52, i64 1, !dbg !36
+  %102 = bitcast <2 x i16> %101 to <2 x bfloat>, !dbg !36
+  %103 = bitcast i32 %57 to <2 x bfloat>, !dbg !39
+  %104 = getelementptr bfloat, ptr addrspace(1) %80, i64 %55, !dbg !51
+  %105 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %104, i1 %17) #5, !dbg !52
+  %106 = bitcast i32 %105 to <2 x bfloat>, !dbg !52
+  %107 = shl i32 %18, 7, !dbg !53
+  %108 = add i32 %107, %.decomposed, !dbg !54
+  %109 = sext i32 %108 to i64, !dbg !55
+  %110 = getelementptr bfloat, ptr addrspace(1) %5, i64 %109, !dbg !55
+  %111 = fpext <2 x bfloat> %97 to <2 x float>, !dbg !56
+  %112 = insertelement <2 x float> poison, float %.0.i, i64 0, !dbg !57
+  %113 = insertelement <2 x float> %112, float %.0.i3, i64 1, !dbg !57
+  %114 = fmul <2 x float> %113, %111, !dbg !57
+  %115 = fpext <2 x bfloat> %98 to <2 x float>, !dbg !58
+  %116 = fmul <2 x float> %114, %115, !dbg !59
+  %117 = fpext <2 x bfloat> %99 to <2 x float>, !dbg !60
+  %118 = fmul <2 x float> %116, %117, !dbg !61
+  %119 = fpext <2 x bfloat> %102 to <2 x float>, !dbg !62
+  %120 = fpext <2 x bfloat> %103 to <2 x float>, !dbg !63
+  %121 = insertelement <2 x float> poison, float %.0.i6, i64 0, !dbg !64
+  %122 = insertelement <2 x float> %121, float %.0.i9, i64 1, !dbg !64
+  %123 = fmul <2 x float> %122, %119, !dbg !64
+  %124 = fmul <2 x float> %123, %120, !dbg !65
+  %125 = fpext <2 x bfloat> %106 to <2 x float>, !dbg !66
+  %126 = fmul <2 x float> %124, %125, !dbg !67
+  %127 = fsub <2 x float> %118, %126, !dbg !68
+  %128 = fptrunc <2 x float> %127 to <2 x bfloat>, !dbg !69
+  %129 = bitcast <2 x bfloat> %128 to i32, !dbg !69
+  tail call void asm sideeffect "@$2 st.global.b32 [ $1 + 0 ], { $0 };", "r,l,b"(i32 %129, ptr addrspace(1) %110, i1 %17) #5, !dbg !69
+  %130 = getelementptr bfloat, ptr addrspace(1) %6, i64 %109, !dbg !70
+  %131 = fmul <2 x float> %124, %117, !dbg !71
+  %132 = fmul <2 x float> %116, %125, !dbg !72
+  %133 = fadd <2 x float> %131, %132, !dbg !73
+  %134 = fptrunc <2 x float> %133 to <2 x bfloat>, !dbg !74
+  %135 = bitcast <2 x bfloat> %134 to i32, !dbg !74
+  tail call void asm sideeffect "@$2 st.global.b32 [ $1 + 0 ], { $0 };", "r,l,b"(i32 %135, ptr addrspace(1) %130, i1 %17) #5, !dbg !74
+  ret void, !dbg !75
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.ctaid.x() #1
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.x() #1
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
+declare float @llvm.nvvm.div.full(float, float) #2
+
+; Function Attrs: convergent nocallback nounwind
+declare void @llvm.nvvm.barrier0() #3
+
+declare i32 @__nvvm_reflect(ptr) local_unnamed_addr #4
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
+declare float @llvm.nvvm.rsqrt.approx.ftz.f(float) #2
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
+declare float @llvm.nvvm.rsqrt.approx.f(float) #2
+
+attributes #0 = { noreturn }
+attributes #1 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #2 = { mustprogress nocallback nofree nosync nounwind willreturn memory(none) }
+attributes #3 = { convergent nocallback nounwind }
+attributes #4 = { "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #5 = { nounwind }
+
+!llvm.module.flags = !{!0, !1}
+!llvm.dbg.cu = !{!2}
+!nvvm.annotations = !{!4}
+!llvm.ident = !{!5}
+
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = !{i32 4, !"nvvm-reflect-ftz", i32 1}
+!2 = distinct !DICompileUnit(language: DW_LANG_C, file: !3, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: LineTablesOnly)
+!3 = !DIFile(filename: "cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py", directory: "/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa")
+!4 = !{ptr @triton_poi_fused_add_mul_sub_5, !"reqntidx", i32 256}
+!5 = !{!"clang version 3.8.0 (tags/RELEASE_380/final)"}
+!6 = !DISubprogram(name: "__assertfail", linkageName: "__assertfail", scope: !7, file: !7, type: !8, spFlags: DISPFlagOptimized)
+!7 = !DIFile(filename: "<unknown>", directory: "")
+!8 = !DISubroutineType(cc: DW_CC_normal, types: !9)
+!9 = !{}
+!10 = distinct !DISubprogram(name: "triton_poi_fused_add_mul_sub_5", linkageName: "triton_poi_fused_add_mul_sub_5", scope: !3, file: !3, line: 18, type: !8, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !2)
+!11 = !DILocation(line: 19, column: 28, scope: !10)
+!12 = !DILocation(line: 19, column: 33, scope: !10)
+!13 = !DILocation(line: 20, column: 36, scope: !10)
+!14 = !DILocation(line: 20, column: 23, scope: !10)
+!15 = !DILocation(line: 21, column: 21, scope: !10)
+!16 = !DILocation(line: 23, column: 21, scope: !10)
+!17 = !DILocation(line: 22, column: 19, scope: !10)
+!18 = !DILocation(line: 23, column: 27, scope: !10)
+!19 = !DILocation(line: 24, column: 19, scope: !10)
+!20 = !DILocation(line: 26, column: 39, scope: !10)
+!21 = !DILocation(line: 26, column: 49, scope: !10)
+!22 = !DILocation(line: 26, column: 35, scope: !10)
+!23 = !DILocation(line: 26, column: 44, scope: !10)
+!24 = !DILocation(line: 26, column: 30, scope: !10)
+!25 = !DILocation(line: 26, column: 54, scope: !10)
+!26 = !DILocation(line: 27, column: 30, scope: !10)
+!27 = !DILocation(line: 27, column: 35, scope: !10)
+!28 = !DILocation(line: 28, column: 31, scope: !10)
+!29 = !DILocation(line: 28, column: 36, scope: !10)
+!30 = !DILocation(line: 29, column: 31, scope: !10)
+!31 = !DILocation(line: 29, column: 36, scope: !10)
+!32 = !DILocation(line: 30, column: 36, scope: !10)
+!33 = !DILocation(line: 30, column: 75, scope: !10)
+!34 = !DILocation(line: 30, column: 41, scope: !10)
+!35 = !DILocation(line: 30, column: 31, scope: !10)
+!36 = !DILocation(line: 30, column: 85, scope: !10)
+!37 = !DILocation(line: 31, column: 57, scope: !10)
+!38 = !DILocation(line: 32, column: 31, scope: !10)
+!39 = !DILocation(line: 32, column: 41, scope: !10)
+!40 = !DILocation(line: 35, column: 19, scope: !10)
+!41 = !DILocation(line: 37, column: 18, scope: !10)
+!42 = !DILocation(line: 38, column: 27, scope: !10)
+!43 = !DILocation(line: 45, column: 35, scope: !10)
+!44 = !DILocation(line: 46, column: 38, scope: !10)
+!45 = !DILocation(line: 46, column: 67, scope: !10)
+!46 = !DILocation(line: 47, column: 31, scope: !10)
+!47 = !DILocation(line: 47, column: 48, scope: !10)
+!48 = !DILocation(line: 50, column: 21, scope: !10)
+!49 = !DILocation(line: 51, column: 20, scope: !10)
+!50 = !DILocation(line: 52, column: 28, scope: !10)
+!51 = !DILocation(line: 56, column: 31, scope: !10)
+!52 = !DILocation(line: 56, column: 53, scope: !10)
+!53 = !DILocation(line: 62, column: 34, scope: !10)
+!54 = !DILocation(line: 62, column: 30, scope: !10)
+!55 = !DILocation(line: 62, column: 25, scope: !10)
+!56 = !DILocation(line: 26, column: 64, scope: !10)
+!57 = !DILocation(line: 39, column: 18, scope: !10)
+!58 = !DILocation(line: 28, column: 76, scope: !10)
+!59 = !DILocation(line: 41, column: 19, scope: !10)
+!60 = !DILocation(line: 47, column: 58, scope: !10)
+!61 = !DILocation(line: 48, column: 20, scope: !10)
+!62 = !DILocation(line: 30, column: 95, scope: !10)
+!63 = !DILocation(line: 32, column: 81, scope: !10)
+!64 = !DILocation(line: 53, column: 20, scope: !10)
+!65 = !DILocation(line: 55, column: 20, scope: !10)
+!66 = !DILocation(line: 56, column: 63, scope: !10)
+!67 = !DILocation(line: 57, column: 20, scope: !10)
+!68 = !DILocation(line: 58, column: 20, scope: !10)
+!69 = !DILocation(line: 62, column: 46, scope: !10)
+!70 = !DILocation(line: 63, column: 25, scope: !10)
+!71 = !DILocation(line: 59, column: 20, scope: !10)
+!72 = !DILocation(line: 60, column: 20, scope: !10)
+!73 = !DILocation(line: 61, column: 20, scope: !10)
+!74 = !DILocation(line: 63, column: 46, scope: !10)
+!75 = !DILocation(line: 63, column: 4, scope: !10)

platform/aiml/models/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/45LDULZ442N5JFUIVYNUNADONVNIWAD3NTIV4IAI7XAWL753KBVQ/triton_poi_fused_add_mul_sub_5.ttgir

@@ -0,0 +1,190 @@
+#blocked = #ttg.blocked<{sizePerThread = [2], threadsPerWarp = [32], warpsPerCTA = [8], order = [0]}>
+#loc = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":18:0)
+module attributes {"ttg.num-ctas" = 1 : i32, "ttg.num-warps" = 8 : i32, ttg.target = "cuda:90", "ttg.threads-per-warp" = 32 : i32} {
+  tt.func public @triton_poi_fused_add_mul_sub_5(%arg0: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":18:0), %arg1: !tt.ptr<f32> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":18:0), %arg2: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":18:0), %arg3: !tt.ptr<i64> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":18:0), %arg4: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":18:0), %arg5: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":18:0), %arg6: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":18:0), %arg7: i32 {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":18:0)) attributes {noinline = false} {
+    %cst = arith.constant dense<1.280000e+02> : tensor<512xf32, #blocked> loc(#loc1)
+    %cst_0 = arith.constant dense<9.99999997E-7> : tensor<512xf32, #blocked> loc(#loc1)
+    %cst_1 = arith.constant dense<128> : tensor<512xi64, #blocked> loc(#loc1)
+    %cst_2 = arith.constant dense<131072> : tensor<512xi64, #blocked> loc(#loc1)
+    %cst_3 = arith.constant dense<0> : tensor<512xi64, #blocked> loc(#loc1)
+    %c512_i32 = arith.constant 512 : i32 loc(#loc1)
+    %cst_4 = arith.constant dense<64> : tensor<512xi32, #blocked> loc(#loc1)
+    %cst_5 = arith.constant dense<40> : tensor<512xi32, #blocked> loc(#loc1)
+    %cst_6 = arith.constant dense<2560> : tensor<512xi32, #blocked> loc(#loc1)
+    %cst_7 = arith.constant dense<128> : tensor<512xi32, #blocked> loc(#loc1)
+    %cst_8 = arith.constant dense<7168> : tensor<512xi32, #blocked> loc(#loc1)
+    %cst_9 = arith.constant dense<true> : tensor<512xi1, #blocked> loc(#loc1)
+    %0 = tt.get_program_id x : i32 loc(#loc2)
+    %1 = arith.muli %0, %c512_i32 : i32 loc(#loc3)
+    %2 = tt.make_range {end = 512 : i32, start = 0 : i32} : tensor<512xi32, #blocked> loc(#loc4)
+    %3 = tt.splat %1 : i32 -> tensor<512xi32, #blocked> loc(#loc5)
+    %4 = arith.addi %3, %2 : tensor<512xi32, #blocked> loc(#loc5)
+    %5 = tt.splat %arg7 : i32 -> tensor<512xi32, #blocked> loc(#loc6)
+    %6 = arith.cmpi slt, %4, %5 : tensor<512xi32, #blocked> loc(#loc6)
+    %7 = arith.remsi %4, %cst_4 : tensor<512xi32, #blocked> loc(#loc7)
+    %8 = arith.divsi %4, %cst_4 : tensor<512xi32, #blocked> loc(#loc8)
+    %9 = arith.remsi %8, %cst_5 : tensor<512xi32, #blocked> loc(#loc9)
+    %10 = arith.divsi %4, %cst_6 : tensor<512xi32, #blocked> loc(#loc10)
+    %11 = arith.muli %9, %cst_7 : tensor<512xi32, #blocked> loc(#loc11)
+    %12 = arith.addi %7, %11 : tensor<512xi32, #blocked> loc(#loc12)
+    %13 = arith.muli %10, %cst_8 : tensor<512xi32, #blocked> loc(#loc13)
+    %14 = arith.addi %12, %13 : tensor<512xi32, #blocked> loc(#loc14)
+    %15 = tt.splat %arg0 : !tt.ptr<bf16> -> tensor<512x!tt.ptr<bf16>, #blocked> loc(#loc15)
+    %16 = tt.addptr %15, %14 : tensor<512x!tt.ptr<bf16>, #blocked>, tensor<512xi32, #blocked> loc(#loc15)
+    %17 = tt.load %16, %6 : tensor<512x!tt.ptr<bf16>, #blocked> loc(#loc16)
+    %18 = arith.extf %17 : tensor<512xbf16, #blocked> to tensor<512xf32, #blocked> loc(#loc17)
+    %19 = tt.splat %arg1 : !tt.ptr<f32> -> tensor<512x!tt.ptr<f32>, #blocked> loc(#loc18)
+    %20 = tt.addptr %19, %8 : tensor<512x!tt.ptr<f32>, #blocked>, tensor<512xi32, #blocked> loc(#loc18)
+    %21 = tt.load %20, %6 evictionPolicy = evict_last : tensor<512x!tt.ptr<f32>, #blocked> loc(#loc19)
+    %22 = tt.splat %arg2 : !tt.ptr<bf16> -> tensor<512x!tt.ptr<bf16>, #blocked> loc(#loc20)
+    %23 = tt.addptr %22, %7 : tensor<512x!tt.ptr<bf16>, #blocked>, tensor<512xi32, #blocked> loc(#loc20)
+    %24 = tt.load %23, %6 evictionPolicy = evict_last : tensor<512x!tt.ptr<bf16>, #blocked> loc(#loc21)
+    %25 = arith.extf %24 : tensor<512xbf16, #blocked> to tensor<512xf32, #blocked> loc(#loc22)
+    %26 = tt.splat %arg3 : !tt.ptr<i64> -> tensor<512x!tt.ptr<i64>, #blocked> loc(#loc23)
+    %27 = tt.addptr %26, %10 : tensor<512x!tt.ptr<i64>, #blocked>, tensor<512xi32, #blocked> loc(#loc23)
+    %28 = tt.load %27, %6 evictionPolicy = evict_last : tensor<512x!tt.ptr<i64>, #blocked> loc(#loc24)
+    %29 = arith.addi %7, %cst_4 : tensor<512xi32, #blocked> loc(#loc25)
+    %30 = arith.addi %29, %11 : tensor<512xi32, #blocked> loc(#loc26)
+    %31 = arith.divsi %29, %cst_7 : tensor<512xi32, #blocked> loc(#loc27)
+    %32 = arith.muli %31, %cst_7 : tensor<512xi32, #blocked> loc(#loc28)
+    %33 = arith.addi %30, %32 : tensor<512xi32, #blocked> loc(#loc29)
+    %34 = arith.addi %33, %13 : tensor<512xi32, #blocked> loc(#loc30)
+    %35 = tt.addptr %15, %34 : tensor<512x!tt.ptr<bf16>, #blocked>, tensor<512xi32, #blocked> loc(#loc31)
+    %36 = tt.load %35, %6 : tensor<512x!tt.ptr<bf16>, #blocked> loc(#loc32)
+    %37 = arith.extf %36 : tensor<512xbf16, #blocked> to tensor<512xf32, #blocked> loc(#loc33)
+    %38 = arith.addi %8, %31 : tensor<512xi32, #blocked> loc(#loc34)
+    %39 = tt.addptr %19, %38 : tensor<512x!tt.ptr<f32>, #blocked>, tensor<512xi32, #blocked> loc(#loc35)
+    %40 = tt.load %39, %6 evictionPolicy = evict_last : tensor<512x!tt.ptr<f32>, #blocked> loc(#loc36)
+    %41 = tt.addptr %22, %29 : tensor<512x!tt.ptr<bf16>, #blocked>, tensor<512xi32, #blocked> loc(#loc37)
+    %42 = tt.load %41, %6 evictionPolicy = evict_last : tensor<512x!tt.ptr<bf16>, #blocked> loc(#loc38)
+    %43 = arith.extf %42 : tensor<512xbf16, #blocked> to tensor<512xf32, #blocked> loc(#loc39)
+    %44 = arith.divf %21, %cst : tensor<512xf32, #blocked> loc(#loc40)
+    %45 = arith.addf %44, %cst_0 : tensor<512xf32, #blocked> loc(#loc41)
+    %46 = tt.extern_elementwise %45 {libname = "", libpath = "", pure = true, symbol = "__nv_rsqrtf"} : (tensor<512xf32, #blocked>) -> tensor<512xf32, #blocked> loc(#loc42)
+    %47 = arith.mulf %18, %46 : tensor<512xf32, #blocked> loc(#loc43)
+    %48 = arith.mulf %47, %25 : tensor<512xf32, #blocked> loc(#loc44)
+    %49 = arith.addi %28, %cst_2 : tensor<512xi64, #blocked> loc(#loc45)
+    %50 = arith.cmpi slt, %28, %cst_3 : tensor<512xi64, #blocked> loc(#loc46)
+    %51 = arith.select %50, %49, %28 : tensor<512xi1, #blocked>, tensor<512xi64, #blocked> loc(#loc47)
+    %52 = arith.cmpi sge, %51, %cst_3 : tensor<512xi64, #blocked> loc(#loc48)
+    %53 = arith.cmpi slt, %51, %cst_2 : tensor<512xi64, #blocked> loc(#loc49)
+    %54 = arith.andi %52, %53 : tensor<512xi1, #blocked> loc(#loc50)
+    %55 = arith.xori %6, %cst_9 : tensor<512xi1, #blocked> loc(#loc51)
+    %56 = arith.ori %54, %55 : tensor<512xi1, #blocked> loc(#loc52)
+    tt.assert %56, "index out of bounds: 0 <= tmp16 < 131072" : tensor<512xi1, #blocked> loc(#loc53)
+    %57 = arith.muli %51, %cst_1 : tensor<512xi64, #blocked> loc(#loc54)
+    %58 = arith.extsi %7 : tensor<512xi32, #blocked> to tensor<512xi64, #blocked> loc(#loc55)
+    %59 = arith.addi %58, %57 : tensor<512xi64, #blocked> loc(#loc55)
+    %60 = tt.splat %arg4 : !tt.ptr<bf16> -> tensor<512x!tt.ptr<bf16>, #blocked> loc(#loc56)
+    %61 = tt.addptr %60, %59 : tensor<512x!tt.ptr<bf16>, #blocked>, tensor<512xi64, #blocked> loc(#loc56)
+    %62 = tt.load %61, %6 : tensor<512x!tt.ptr<bf16>, #blocked> loc(#loc57)
+    %63 = arith.extf %62 : tensor<512xbf16, #blocked> to tensor<512xf32, #blocked> loc(#loc58)
+    %64 = arith.mulf %48, %63 : tensor<512xf32, #blocked> loc(#loc59)
+    %65 = arith.divf %40, %cst : tensor<512xf32, #blocked> loc(#loc60)
+    %66 = arith.addf %65, %cst_0 : tensor<512xf32, #blocked> loc(#loc61)
+    %67 = tt.extern_elementwise %66 {libname = "", libpath = "", pure = true, symbol = "__nv_rsqrtf"} : (tensor<512xf32, #blocked>) -> tensor<512xf32, #blocked> loc(#loc62)
+    %68 = arith.mulf %37, %67 : tensor<512xf32, #blocked> loc(#loc63)
+    %69 = arith.mulf %68, %43 : tensor<512xf32, #blocked> loc(#loc64)
+    %70 = arith.extsi %29 : tensor<512xi32, #blocked> to tensor<512xi64, #blocked> loc(#loc65)
+    %71 = arith.addi %70, %57 : tensor<512xi64, #blocked> loc(#loc65)
+    %72 = tt.addptr %60, %71 : tensor<512x!tt.ptr<bf16>, #blocked>, tensor<512xi64, #blocked> loc(#loc66)
+    %73 = tt.load %72, %6 : tensor<512x!tt.ptr<bf16>, #blocked> loc(#loc67)
+    %74 = arith.extf %73 : tensor<512xbf16, #blocked> to tensor<512xf32, #blocked> loc(#loc68)
+    %75 = arith.mulf %69, %74 : tensor<512xf32, #blocked> loc(#loc69)
+    %76 = arith.subf %64, %75 : tensor<512xf32, #blocked> loc(#loc70)
+    %77 = arith.mulf %69, %63 : tensor<512xf32, #blocked> loc(#loc71)
+    %78 = arith.mulf %48, %74 : tensor<512xf32, #blocked> loc(#loc72)
+    %79 = arith.addf %77, %78 : tensor<512xf32, #blocked> loc(#loc73)
+    %80 = arith.muli %8, %cst_7 : tensor<512xi32, #blocked> loc(#loc74)
+    %81 = arith.addi %7, %80 : tensor<512xi32, #blocked> loc(#loc75)
+    %82 = tt.splat %arg5 : !tt.ptr<bf16> -> tensor<512x!tt.ptr<bf16>, #blocked> loc(#loc76)
+    %83 = tt.addptr %82, %81 : tensor<512x!tt.ptr<bf16>, #blocked>, tensor<512xi32, #blocked> loc(#loc76)
+    %84 = arith.truncf %76 : tensor<512xf32, #blocked> to tensor<512xbf16, #blocked> loc(#loc77)
+    tt.store %83, %84, %6 : tensor<512x!tt.ptr<bf16>, #blocked> loc(#loc77)
+    %85 = tt.splat %arg6 : !tt.ptr<bf16> -> tensor<512x!tt.ptr<bf16>, #blocked> loc(#loc78)
+    %86 = tt.addptr %85, %81 : tensor<512x!tt.ptr<bf16>, #blocked>, tensor<512xi32, #blocked> loc(#loc78)
+    %87 = arith.truncf %79 : tensor<512xf32, #blocked> to tensor<512xbf16, #blocked> loc(#loc79)
+    tt.store %86, %87, %6 : tensor<512x!tt.ptr<bf16>, #blocked> loc(#loc79)
+    tt.return loc(#loc80)
+  } loc(#loc)
+} loc(#loc)
+#loc1 = loc(unknown)
+#loc2 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":19:28)
+#loc3 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":19:33)
+#loc4 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":20:36)
+#loc5 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":20:23)
+#loc6 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":21:21)
+#loc7 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":22:19)
+#loc8 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":23:21)
+#loc9 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":23:27)
+#loc10 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":24:19)
+#loc11 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":26:39)
+#loc12 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":26:35)
+#loc13 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":26:49)
+#loc14 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":26:44)
+#loc15 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":26:30)
+#loc16 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":26:54)
+#loc17 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":26:64)
+#loc18 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":27:30)
+#loc19 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":27:35)
+#loc20 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":28:31)
+#loc21 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":28:36)
+#loc22 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":28:76)
+#loc23 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":29:31)
+#loc24 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":29:36)
+#loc25 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":30:36)
+#loc26 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":30:41)
+#loc27 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":30:68)
+#loc28 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":30:55)
+#loc29 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":30:50)
+#loc30 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":30:75)
+#loc31 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":30:31)
+#loc32 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":30:85)
+#loc33 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":30:95)
+#loc34 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":31:37)
+#loc35 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":31:31)
+#loc36 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":31:57)
+#loc37 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":32:31)
+#loc38 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":32:41)
+#loc39 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":32:81)
+#loc40 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":35:19)
+#loc41 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":37:18)
+#loc42 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":38:27)
+#loc43 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":39:18)
+#loc44 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":41:19)
+#loc45 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":43:20)
+#loc46 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":44:20)
+#loc47 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":45:35)
+#loc48 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":46:28)
+#loc49 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":46:46)
+#loc50 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":46:38)
+#loc51 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":46:59)
+#loc52 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":46:57)
+#loc53 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":46:67)
+#loc54 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":47:40)
+#loc55 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":47:36)
+#loc56 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":47:31)
+#loc57 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":47:48)
+#loc58 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":47:58)
+#loc59 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":48:20)
+#loc60 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":50:21)
+#loc61 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":51:20)
+#loc62 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":52:28)
+#loc63 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":53:20)
+#loc64 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":55:20)
+#loc65 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":56:41)
+#loc66 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":56:31)
+#loc67 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":56:53)
+#loc68 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":56:63)
+#loc69 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":57:20)
+#loc70 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":58:20)
+#loc71 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":59:20)
+#loc72 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":60:20)
+#loc73 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":61:20)
+#loc74 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":62:34)
+#loc75 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":62:30)
+#loc76 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":62:25)
+#loc77 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":62:46)
+#loc78 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":63:25)
+#loc79 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":63:46)
+#loc80 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":63:4)

platform/aiml/models/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/45LDULZ442N5JFUIVYNUNADONVNIWAD3NTIV4IAI7XAWL753KBVQ/triton_poi_fused_add_mul_sub_5.ttir

@@ -0,0 +1,189 @@
+#loc = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":18:0)
+module {
+  tt.func public @triton_poi_fused_add_mul_sub_5(%arg0: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":18:0), %arg1: !tt.ptr<f32> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":18:0), %arg2: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":18:0), %arg3: !tt.ptr<i64> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":18:0), %arg4: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":18:0), %arg5: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":18:0), %arg6: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":18:0), %arg7: i32 {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":18:0)) attributes {noinline = false} {
+    %cst = arith.constant dense<0> : tensor<512xi64> loc(#loc1)
+    %cst_0 = arith.constant dense<131072> : tensor<512xi64> loc(#loc1)
+    %cst_1 = arith.constant dense<128> : tensor<512xi64> loc(#loc1)
+    %cst_2 = arith.constant dense<true> : tensor<512xi1> loc(#loc1)
+    %cst_3 = arith.constant dense<9.99999997E-7> : tensor<512xf32> loc(#loc1)
+    %cst_4 = arith.constant dense<1.280000e+02> : tensor<512xf32> loc(#loc1)
+    %cst_5 = arith.constant dense<7168> : tensor<512xi32> loc(#loc1)
+    %cst_6 = arith.constant dense<128> : tensor<512xi32> loc(#loc1)
+    %cst_7 = arith.constant dense<2560> : tensor<512xi32> loc(#loc1)
+    %cst_8 = arith.constant dense<40> : tensor<512xi32> loc(#loc1)
+    %cst_9 = arith.constant dense<64> : tensor<512xi32> loc(#loc1)
+    %c512_i32 = arith.constant 512 : i32 loc(#loc1)
+    %0 = tt.get_program_id x : i32 loc(#loc2)
+    %1 = arith.muli %0, %c512_i32 : i32 loc(#loc3)
+    %2 = tt.make_range {end = 512 : i32, start = 0 : i32} : tensor<512xi32> loc(#loc4)
+    %3 = tt.splat %1 : i32 -> tensor<512xi32> loc(#loc5)
+    %4 = arith.addi %3, %2 : tensor<512xi32> loc(#loc5)
+    %5 = tt.splat %arg7 : i32 -> tensor<512xi32> loc(#loc6)
+    %6 = arith.cmpi slt, %4, %5 : tensor<512xi32> loc(#loc6)
+    %7 = arith.remsi %4, %cst_9 : tensor<512xi32> loc(#loc7)
+    %8 = arith.divsi %4, %cst_9 : tensor<512xi32> loc(#loc8)
+    %9 = arith.remsi %8, %cst_8 : tensor<512xi32> loc(#loc9)
+    %10 = arith.divsi %4, %cst_7 : tensor<512xi32> loc(#loc10)
+    %11 = arith.muli %9, %cst_6 : tensor<512xi32> loc(#loc11)
+    %12 = arith.addi %7, %11 : tensor<512xi32> loc(#loc12)
+    %13 = arith.muli %10, %cst_5 : tensor<512xi32> loc(#loc13)
+    %14 = arith.addi %12, %13 : tensor<512xi32> loc(#loc14)
+    %15 = tt.splat %arg0 : !tt.ptr<bf16> -> tensor<512x!tt.ptr<bf16>> loc(#loc15)
+    %16 = tt.addptr %15, %14 : tensor<512x!tt.ptr<bf16>>, tensor<512xi32> loc(#loc15)
+    %17 = tt.load %16, %6 : tensor<512x!tt.ptr<bf16>> loc(#loc16)
+    %18 = arith.extf %17 : tensor<512xbf16> to tensor<512xf32> loc(#loc17)
+    %19 = tt.splat %arg1 : !tt.ptr<f32> -> tensor<512x!tt.ptr<f32>> loc(#loc18)
+    %20 = tt.addptr %19, %8 : tensor<512x!tt.ptr<f32>>, tensor<512xi32> loc(#loc18)
+    %21 = tt.load %20, %6 evictionPolicy = evict_last : tensor<512x!tt.ptr<f32>> loc(#loc19)
+    %22 = tt.splat %arg2 : !tt.ptr<bf16> -> tensor<512x!tt.ptr<bf16>> loc(#loc20)
+    %23 = tt.addptr %22, %7 : tensor<512x!tt.ptr<bf16>>, tensor<512xi32> loc(#loc20)
+    %24 = tt.load %23, %6 evictionPolicy = evict_last : tensor<512x!tt.ptr<bf16>> loc(#loc21)
+    %25 = arith.extf %24 : tensor<512xbf16> to tensor<512xf32> loc(#loc22)
+    %26 = tt.splat %arg3 : !tt.ptr<i64> -> tensor<512x!tt.ptr<i64>> loc(#loc23)
+    %27 = tt.addptr %26, %10 : tensor<512x!tt.ptr<i64>>, tensor<512xi32> loc(#loc23)
+    %28 = tt.load %27, %6 evictionPolicy = evict_last : tensor<512x!tt.ptr<i64>> loc(#loc24)
+    %29 = arith.addi %7, %cst_9 : tensor<512xi32> loc(#loc25)
+    %30 = arith.addi %29, %11 : tensor<512xi32> loc(#loc26)
+    %31 = arith.divsi %29, %cst_6 : tensor<512xi32> loc(#loc27)
+    %32 = arith.muli %31, %cst_6 : tensor<512xi32> loc(#loc28)
+    %33 = arith.addi %30, %32 : tensor<512xi32> loc(#loc29)
+    %34 = arith.addi %33, %13 : tensor<512xi32> loc(#loc30)
+    %35 = tt.addptr %15, %34 : tensor<512x!tt.ptr<bf16>>, tensor<512xi32> loc(#loc31)
+    %36 = tt.load %35, %6 : tensor<512x!tt.ptr<bf16>> loc(#loc32)
+    %37 = arith.extf %36 : tensor<512xbf16> to tensor<512xf32> loc(#loc33)
+    %38 = arith.addi %8, %31 : tensor<512xi32> loc(#loc34)
+    %39 = tt.addptr %19, %38 : tensor<512x!tt.ptr<f32>>, tensor<512xi32> loc(#loc35)
+    %40 = tt.load %39, %6 evictionPolicy = evict_last : tensor<512x!tt.ptr<f32>> loc(#loc36)
+    %41 = tt.addptr %22, %29 : tensor<512x!tt.ptr<bf16>>, tensor<512xi32> loc(#loc37)
+    %42 = tt.load %41, %6 evictionPolicy = evict_last : tensor<512x!tt.ptr<bf16>> loc(#loc38)
+    %43 = arith.extf %42 : tensor<512xbf16> to tensor<512xf32> loc(#loc39)
+    %44 = arith.divf %21, %cst_4 : tensor<512xf32> loc(#loc40)
+    %45 = arith.addf %44, %cst_3 : tensor<512xf32> loc(#loc41)
+    %46 = tt.extern_elementwise %45 {libname = "", libpath = "", pure = true, symbol = "__nv_rsqrtf"} : (tensor<512xf32>) -> tensor<512xf32> loc(#loc42)
+    %47 = arith.mulf %18, %46 : tensor<512xf32> loc(#loc43)
+    %48 = arith.mulf %47, %25 : tensor<512xf32> loc(#loc44)
+    %49 = arith.addi %28, %cst_0 : tensor<512xi64> loc(#loc45)
+    %50 = arith.cmpi slt, %28, %cst : tensor<512xi64> loc(#loc46)
+    %51 = arith.select %50, %49, %28 : tensor<512xi1>, tensor<512xi64> loc(#loc47)
+    %52 = arith.cmpi sge, %51, %cst : tensor<512xi64> loc(#loc48)
+    %53 = arith.cmpi slt, %51, %cst_0 : tensor<512xi64> loc(#loc49)
+    %54 = arith.andi %52, %53 : tensor<512xi1> loc(#loc50)
+    %55 = arith.xori %6, %cst_2 : tensor<512xi1> loc(#loc51)
+    %56 = arith.ori %54, %55 : tensor<512xi1> loc(#loc52)
+    tt.assert %56, "index out of bounds: 0 <= tmp16 < 131072" : tensor<512xi1> loc(#loc53)
+    %57 = arith.muli %51, %cst_1 : tensor<512xi64> loc(#loc54)
+    %58 = arith.extsi %7 : tensor<512xi32> to tensor<512xi64> loc(#loc55)
+    %59 = arith.addi %58, %57 : tensor<512xi64> loc(#loc55)
+    %60 = tt.splat %arg4 : !tt.ptr<bf16> -> tensor<512x!tt.ptr<bf16>> loc(#loc56)
+    %61 = tt.addptr %60, %59 : tensor<512x!tt.ptr<bf16>>, tensor<512xi64> loc(#loc56)
+    %62 = tt.load %61, %6 : tensor<512x!tt.ptr<bf16>> loc(#loc57)
+    %63 = arith.extf %62 : tensor<512xbf16> to tensor<512xf32> loc(#loc58)
+    %64 = arith.mulf %48, %63 : tensor<512xf32> loc(#loc59)
+    %65 = arith.divf %40, %cst_4 : tensor<512xf32> loc(#loc60)
+    %66 = arith.addf %65, %cst_3 : tensor<512xf32> loc(#loc61)
+    %67 = tt.extern_elementwise %66 {libname = "", libpath = "", pure = true, symbol = "__nv_rsqrtf"} : (tensor<512xf32>) -> tensor<512xf32> loc(#loc62)
+    %68 = arith.mulf %37, %67 : tensor<512xf32> loc(#loc63)
+    %69 = arith.mulf %68, %43 : tensor<512xf32> loc(#loc64)
+    %70 = arith.extsi %29 : tensor<512xi32> to tensor<512xi64> loc(#loc65)
+    %71 = arith.addi %70, %57 : tensor<512xi64> loc(#loc65)
+    %72 = tt.addptr %60, %71 : tensor<512x!tt.ptr<bf16>>, tensor<512xi64> loc(#loc66)
+    %73 = tt.load %72, %6 : tensor<512x!tt.ptr<bf16>> loc(#loc67)
+    %74 = arith.extf %73 : tensor<512xbf16> to tensor<512xf32> loc(#loc68)
+    %75 = arith.mulf %69, %74 : tensor<512xf32> loc(#loc69)
+    %76 = arith.subf %64, %75 : tensor<512xf32> loc(#loc70)
+    %77 = arith.mulf %69, %63 : tensor<512xf32> loc(#loc71)
+    %78 = arith.mulf %48, %74 : tensor<512xf32> loc(#loc72)
+    %79 = arith.addf %77, %78 : tensor<512xf32> loc(#loc73)
+    %80 = arith.muli %8, %cst_6 : tensor<512xi32> loc(#loc74)
+    %81 = arith.addi %7, %80 : tensor<512xi32> loc(#loc75)
+    %82 = tt.splat %arg5 : !tt.ptr<bf16> -> tensor<512x!tt.ptr<bf16>> loc(#loc76)
+    %83 = tt.addptr %82, %81 : tensor<512x!tt.ptr<bf16>>, tensor<512xi32> loc(#loc76)
+    %84 = arith.truncf %76 : tensor<512xf32> to tensor<512xbf16> loc(#loc77)
+    tt.store %83, %84, %6 : tensor<512x!tt.ptr<bf16>> loc(#loc77)
+    %85 = tt.splat %arg6 : !tt.ptr<bf16> -> tensor<512x!tt.ptr<bf16>> loc(#loc78)
+    %86 = tt.addptr %85, %81 : tensor<512x!tt.ptr<bf16>>, tensor<512xi32> loc(#loc78)
+    %87 = arith.truncf %79 : tensor<512xf32> to tensor<512xbf16> loc(#loc79)
+    tt.store %86, %87, %6 : tensor<512x!tt.ptr<bf16>> loc(#loc79)
+    tt.return loc(#loc80)
+  } loc(#loc)
+} loc(#loc)
+#loc1 = loc(unknown)
+#loc2 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":19:28)
+#loc3 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":19:33)
+#loc4 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":20:36)
+#loc5 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":20:23)
+#loc6 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":21:21)
+#loc7 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":22:19)
+#loc8 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":23:21)
+#loc9 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":23:27)
+#loc10 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":24:19)
+#loc11 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":26:39)
+#loc12 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":26:35)
+#loc13 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":26:49)
+#loc14 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":26:44)
+#loc15 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":26:30)
+#loc16 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":26:54)
+#loc17 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":26:64)
+#loc18 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":27:30)
+#loc19 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":27:35)
+#loc20 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":28:31)
+#loc21 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":28:36)
+#loc22 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":28:76)
+#loc23 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":29:31)
+#loc24 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":29:36)
+#loc25 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":30:36)
+#loc26 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":30:41)
+#loc27 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":30:68)
+#loc28 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":30:55)
+#loc29 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":30:50)
+#loc30 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":30:75)
+#loc31 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":30:31)
+#loc32 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":30:85)
+#loc33 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":30:95)
+#loc34 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":31:37)
+#loc35 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":31:31)
+#loc36 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":31:57)
+#loc37 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":32:31)
+#loc38 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":32:41)
+#loc39 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":32:81)
+#loc40 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":35:19)
+#loc41 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":37:18)
+#loc42 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":38:27)
+#loc43 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":39:18)
+#loc44 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":41:19)
+#loc45 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":43:20)
+#loc46 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":44:20)
+#loc47 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":45:35)
+#loc48 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":46:28)
+#loc49 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":46:46)
+#loc50 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":46:38)
+#loc51 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":46:59)
+#loc52 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":46:57)
+#loc53 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":46:67)
+#loc54 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":47:40)
+#loc55 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":47:36)
+#loc56 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":47:31)
+#loc57 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":47:48)
+#loc58 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":47:58)
+#loc59 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":48:20)
+#loc60 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":50:21)
+#loc61 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":51:20)
+#loc62 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":52:28)
+#loc63 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":53:20)
+#loc64 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":55:20)
+#loc65 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":56:41)
+#loc66 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":56:31)
+#loc67 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":56:53)
+#loc68 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":56:63)
+#loc69 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":57:20)
+#loc70 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":58:20)
+#loc71 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":59:20)
+#loc72 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":60:20)
+#loc73 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":61:20)
+#loc74 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":62:34)
+#loc75 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":62:30)
+#loc76 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":62:25)
+#loc77 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":62:46)
+#loc78 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":63:25)
+#loc79 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":63:46)
+#loc80 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py":63:4)

platform/aiml/models/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/4VKD4PBE7ZFPVR2HT6BRTSPMGIUGA2E7B3L3R5SB4CN4JM7KMHOQ/__grp__triton_poi_fused_add_mul_sub_5.json

@@ -0,0 +1 @@
+{"child_paths": {"triton_poi_fused_add_mul_sub_5.ttir": "/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/4VKD4PBE7ZFPVR2HT6BRTSPMGIUGA2E7B3L3R5SB4CN4JM7KMHOQ/triton_poi_fused_add_mul_sub_5.ttir", "triton_poi_fused_add_mul_sub_5.ttgir": "/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/4VKD4PBE7ZFPVR2HT6BRTSPMGIUGA2E7B3L3R5SB4CN4JM7KMHOQ/triton_poi_fused_add_mul_sub_5.ttgir", "triton_poi_fused_add_mul_sub_5.llir": "/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/4VKD4PBE7ZFPVR2HT6BRTSPMGIUGA2E7B3L3R5SB4CN4JM7KMHOQ/triton_poi_fused_add_mul_sub_5.llir", "triton_poi_fused_add_mul_sub_5.ptx": "/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/4VKD4PBE7ZFPVR2HT6BRTSPMGIUGA2E7B3L3R5SB4CN4JM7KMHOQ/triton_poi_fused_add_mul_sub_5.ptx", "triton_poi_fused_add_mul_sub_5.cubin": "/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/4VKD4PBE7ZFPVR2HT6BRTSPMGIUGA2E7B3L3R5SB4CN4JM7KMHOQ/triton_poi_fused_add_mul_sub_5.cubin", "triton_poi_fused_add_mul_sub_5.json": "/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/4VKD4PBE7ZFPVR2HT6BRTSPMGIUGA2E7B3L3R5SB4CN4JM7KMHOQ/triton_poi_fused_add_mul_sub_5.json"}}

platform/aiml/models/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/4VKD4PBE7ZFPVR2HT6BRTSPMGIUGA2E7B3L3R5SB4CN4JM7KMHOQ/triton_poi_fused_add_mul_sub_5.llir

@@ -0,0 +1,671 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+target datalayout = "e-p3:32:32-p4:32:32-p5:32:32-p6:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64"
+
+@assertFunc_0 = internal constant [8 x i8] c"unknown\00"
+@assertFile_0 = internal constant [134 x i8] c"/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py\00"
+@assertMessage_0 = internal constant [41 x i8] c"index out of bounds: 0 <= tmp16 < 131072\00"
+@.str = private unnamed_addr constant [11 x i8] c"__CUDA_FTZ\00", align 1
+
+; Function Attrs: noreturn
+declare !dbg !6 void @__assertfail(ptr, ptr, i32, ptr, i64) local_unnamed_addr #0
+
+define ptx_kernel void @triton_poi_fused_add_mul_sub_5(ptr addrspace(1) %0, ptr addrspace(1) %1, ptr addrspace(1) %2, ptr addrspace(1) %3, ptr addrspace(1) %4, ptr addrspace(1) %5, ptr addrspace(1) %6, i32 %7, ptr addrspace(1) readnone captures(none) %8) local_unnamed_addr !dbg !10 {
+  %10 = tail call i32 @llvm.nvvm.read.ptx.sreg.ctaid.x(), !dbg !11
+  %11 = shl i32 %10, 10, !dbg !12
+  %12 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !13
+  %13 = shl i32 %12, 3, !dbg !13
+  %14 = and i32 %13, 1016, !dbg !13
+  %15 = or disjoint i32 %14, %11, !dbg !14
+  %16 = or disjoint i32 %15, 1, !dbg !14
+  %17 = or disjoint i32 %15, 2, !dbg !14
+  %18 = or disjoint i32 %15, 3, !dbg !14
+  %19 = or disjoint i32 %15, 4, !dbg !14
+  %20 = or disjoint i32 %15, 5, !dbg !14
+  %21 = or disjoint i32 %15, 6, !dbg !14
+  %22 = or disjoint i32 %15, 7, !dbg !14
+  %23 = icmp slt i32 %15, %7, !dbg !15
+  %24 = sdiv i32 %15, 64, !dbg !16
+  %25 = mul i32 %24, 64, !dbg !17
+  %.decomposed = sub i32 %15, %25, !dbg !17
+  %26 = srem i32 %16, 64, !dbg !17
+  %27 = srem i32 %17, 64, !dbg !17
+  %28 = srem i32 %18, 64, !dbg !17
+  %29 = srem i32 %19, 64, !dbg !17
+  %30 = srem i32 %20, 64, !dbg !17
+  %31 = srem i32 %21, 64, !dbg !17
+  %32 = srem i32 %22, 64, !dbg !17
+  %33 = srem i32 %24, 40, !dbg !18
+  %34 = sdiv i32 %15, 2560, !dbg !19
+  %35 = shl nsw i32 %33, 7, !dbg !20
+  %36 = mul i32 %34, 7168, !dbg !21
+  %37 = add i32 %35, %36, !dbg !22
+  %38 = add i32 %37, %.decomposed, !dbg !23
+  %39 = sext i32 %38 to i64, !dbg !24
+  %40 = getelementptr bfloat, ptr addrspace(1) %0, i64 %39, !dbg !24
+  %41 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];", "=r,=r,=r,=r,l,b"(ptr addrspace(1) %40, i1 %23) #5, !dbg !25
+  %42 = sext i32 %24 to i64, !dbg !26
+  %43 = getelementptr float, ptr addrspace(1) %1, i64 %42, !dbg !26
+  %44 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %43, i1 %23) #5, !dbg !27
+  %45 = bitcast i32 %44 to float, !dbg !27
+  %46 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %43, i1 %23) #5, !dbg !27
+  %47 = bitcast i32 %46 to float, !dbg !27
+  %48 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %43, i1 %23) #5, !dbg !27
+  %49 = bitcast i32 %48 to float, !dbg !27
+  %50 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %43, i1 %23) #5, !dbg !27
+  %51 = bitcast i32 %50 to float, !dbg !27
+  %52 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %43, i1 %23) #5, !dbg !27
+  %53 = bitcast i32 %52 to float, !dbg !27
+  %54 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %43, i1 %23) #5, !dbg !27
+  %55 = bitcast i32 %54 to float, !dbg !27
+  %56 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %43, i1 %23) #5, !dbg !27
+  %57 = bitcast i32 %56 to float, !dbg !27
+  %58 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %43, i1 %23) #5, !dbg !27
+  %59 = bitcast i32 %58 to float, !dbg !27
+  %60 = sext i32 %.decomposed to i64, !dbg !28
+  %61 = getelementptr bfloat, ptr addrspace(1) %2, i64 %60, !dbg !28
+  %62 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];", "=r,=r,=r,=r,l,b"(ptr addrspace(1) %61, i1 %23) #5, !dbg !29
+  %63 = sext i32 %34 to i64, !dbg !30
+  %64 = getelementptr i64, ptr addrspace(1) %3, i64 %63, !dbg !30
+  %65 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %64, i1 %23) #5, !dbg !31
+  %66 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %64, i1 %23) #5, !dbg !31
+  %67 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %64, i1 %23) #5, !dbg !31
+  %68 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %64, i1 %23) #5, !dbg !31
+  %69 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %64, i1 %23) #5, !dbg !31
+  %70 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %64, i1 %23) #5, !dbg !31
+  %71 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %64, i1 %23) #5, !dbg !31
+  %72 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %64, i1 %23) #5, !dbg !31
+  %73 = add nsw i32 %.decomposed, 64, !dbg !32
+  %74 = add i32 %37, %73, !dbg !33
+  %75 = or disjoint i32 %37, 64, !dbg !34
+  %76 = add nsw i32 %75, %26, !dbg !33
+  %77 = add nsw i32 %75, %27, !dbg !33
+  %78 = add nsw i32 %75, %28, !dbg !33
+  %79 = add nsw i32 %75, %29, !dbg !33
+  %80 = add nsw i32 %75, %30, !dbg !33
+  %81 = add nsw i32 %75, %31, !dbg !33
+  %82 = add nsw i32 %75, %32, !dbg !33
+  %83 = sext i32 %74 to i64, !dbg !35
+  %84 = getelementptr bfloat, ptr addrspace(1) %0, i64 %83, !dbg !35
+  %85 = sext i32 %76 to i64, !dbg !35
+  %86 = getelementptr bfloat, ptr addrspace(1) %0, i64 %85, !dbg !35
+  %87 = sext i32 %77 to i64, !dbg !35
+  %88 = getelementptr bfloat, ptr addrspace(1) %0, i64 %87, !dbg !35
+  %89 = sext i32 %78 to i64, !dbg !35
+  %90 = getelementptr bfloat, ptr addrspace(1) %0, i64 %89, !dbg !35
+  %91 = sext i32 %79 to i64, !dbg !35
+  %92 = getelementptr bfloat, ptr addrspace(1) %0, i64 %91, !dbg !35
+  %93 = sext i32 %80 to i64, !dbg !35
+  %94 = getelementptr bfloat, ptr addrspace(1) %0, i64 %93, !dbg !35
+  %95 = sext i32 %81 to i64, !dbg !35
+  %96 = getelementptr bfloat, ptr addrspace(1) %0, i64 %95, !dbg !35
+  %97 = sext i32 %82 to i64, !dbg !35
+  %98 = getelementptr bfloat, ptr addrspace(1) %0, i64 %97, !dbg !35
+  %99 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.b16 { $0 }, [ $1 + 0 ];", "=c,l,b"(ptr addrspace(1) %84, i1 %23) #5, !dbg !36
+  %100 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.b16 { $0 }, [ $1 + 0 ];", "=c,l,b"(ptr addrspace(1) %86, i1 %23) #5, !dbg !36
+  %101 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.b16 { $0 }, [ $1 + 0 ];", "=c,l,b"(ptr addrspace(1) %88, i1 %23) #5, !dbg !36
+  %102 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.b16 { $0 }, [ $1 + 0 ];", "=c,l,b"(ptr addrspace(1) %90, i1 %23) #5, !dbg !36
+  %103 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.b16 { $0 }, [ $1 + 0 ];", "=c,l,b"(ptr addrspace(1) %92, i1 %23) #5, !dbg !36
+  %104 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.b16 { $0 }, [ $1 + 0 ];", "=c,l,b"(ptr addrspace(1) %94, i1 %23) #5, !dbg !36
+  %105 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.b16 { $0 }, [ $1 + 0 ];", "=c,l,b"(ptr addrspace(1) %96, i1 %23) #5, !dbg !36
+  %106 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.b16 { $0 }, [ $1 + 0 ];", "=c,l,b"(ptr addrspace(1) %98, i1 %23) #5, !dbg !36
+  %107 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %43, i1 %23) #5, !dbg !37
+  %108 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %43, i1 %23) #5, !dbg !37
+  %109 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %43, i1 %23) #5, !dbg !37
+  %110 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %43, i1 %23) #5, !dbg !37
+  %111 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %43, i1 %23) #5, !dbg !37
+  %112 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %43, i1 %23) #5, !dbg !37
+  %113 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %43, i1 %23) #5, !dbg !37
+  %114 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %43, i1 %23) #5, !dbg !37
+  %115 = zext nneg i32 %73 to i64, !dbg !38
+  %116 = getelementptr bfloat, ptr addrspace(1) %2, i64 %115, !dbg !38
+  %117 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];", "=r,=r,=r,=r,l,b"(ptr addrspace(1) %116, i1 %23) #5, !dbg !39
+  %118 = tail call float @llvm.nvvm.div.full(float %45, float 1.280000e+02), !dbg !40
+  %119 = tail call float @llvm.nvvm.div.full(float %47, float 1.280000e+02), !dbg !40
+  %120 = tail call float @llvm.nvvm.div.full(float %49, float 1.280000e+02), !dbg !40
+  %121 = tail call float @llvm.nvvm.div.full(float %51, float 1.280000e+02), !dbg !40
+  %122 = tail call float @llvm.nvvm.div.full(float %53, float 1.280000e+02), !dbg !40
+  %123 = tail call float @llvm.nvvm.div.full(float %55, float 1.280000e+02), !dbg !40
+  %124 = tail call float @llvm.nvvm.div.full(float %57, float 1.280000e+02), !dbg !40
+  %125 = tail call float @llvm.nvvm.div.full(float %59, float 1.280000e+02), !dbg !40
+  %126 = fadd float %118, 0x3EB0C6F7A0000000, !dbg !41
+  %127 = fadd float %119, 0x3EB0C6F7A0000000, !dbg !41
+  %128 = fadd float %120, 0x3EB0C6F7A0000000, !dbg !41
+  %129 = fadd float %121, 0x3EB0C6F7A0000000, !dbg !41
+  %130 = fadd float %122, 0x3EB0C6F7A0000000, !dbg !41
+  %131 = fadd float %123, 0x3EB0C6F7A0000000, !dbg !41
+  %132 = fadd float %124, 0x3EB0C6F7A0000000, !dbg !41
+  %133 = fadd float %125, 0x3EB0C6F7A0000000, !dbg !41
+  %134 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5, !dbg !42
+  %.not.i = icmp eq i32 %134, 0, !dbg !42
+  br i1 %.not.i, label %137, label %135, !dbg !42
+
+135:                                              ; preds = %9
+  %136 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %126), !dbg !42
+  br label %__nv_rsqrtf.exit, !dbg !42
+
+137:                                              ; preds = %9
+  %138 = tail call float @llvm.nvvm.rsqrt.approx.f(float %126), !dbg !42
+  br label %__nv_rsqrtf.exit, !dbg !42
+
+__nv_rsqrtf.exit:                                 ; preds = %135, %137
+  %.0.i = phi float [ %136, %135 ], [ %138, %137 ], !dbg !42
+  %139 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5, !dbg !42
+  %.not.i2 = icmp eq i32 %139, 0, !dbg !42
+  br i1 %.not.i2, label %142, label %140, !dbg !42
+
+140:                                              ; preds = %__nv_rsqrtf.exit
+  %141 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %127), !dbg !42
+  br label %__nv_rsqrtf.exit4, !dbg !42
+
+142:                                              ; preds = %__nv_rsqrtf.exit
+  %143 = tail call float @llvm.nvvm.rsqrt.approx.f(float %127), !dbg !42
+  br label %__nv_rsqrtf.exit4, !dbg !42
+
+__nv_rsqrtf.exit4:                                ; preds = %140, %142
+  %.0.i3 = phi float [ %141, %140 ], [ %143, %142 ], !dbg !42
+  %144 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5, !dbg !42
+  %.not.i5 = icmp eq i32 %144, 0, !dbg !42
+  br i1 %.not.i5, label %147, label %145, !dbg !42
+
+145:                                              ; preds = %__nv_rsqrtf.exit4
+  %146 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %128), !dbg !42
+  br label %__nv_rsqrtf.exit7, !dbg !42
+
+147:                                              ; preds = %__nv_rsqrtf.exit4
+  %148 = tail call float @llvm.nvvm.rsqrt.approx.f(float %128), !dbg !42
+  br label %__nv_rsqrtf.exit7, !dbg !42
+
+__nv_rsqrtf.exit7:                                ; preds = %145, %147
+  %.0.i6 = phi float [ %146, %145 ], [ %148, %147 ], !dbg !42
+  %149 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5, !dbg !42
+  %.not.i8 = icmp eq i32 %149, 0, !dbg !42
+  br i1 %.not.i8, label %152, label %150, !dbg !42
+
+150:                                              ; preds = %__nv_rsqrtf.exit7
+  %151 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %129), !dbg !42
+  br label %__nv_rsqrtf.exit10, !dbg !42
+
+152:                                              ; preds = %__nv_rsqrtf.exit7
+  %153 = tail call float @llvm.nvvm.rsqrt.approx.f(float %129), !dbg !42
+  br label %__nv_rsqrtf.exit10, !dbg !42
+
+__nv_rsqrtf.exit10:                               ; preds = %150, %152
+  %.0.i9 = phi float [ %151, %150 ], [ %153, %152 ], !dbg !42
+  %154 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5, !dbg !42
+  %.not.i11 = icmp eq i32 %154, 0, !dbg !42
+  br i1 %.not.i11, label %157, label %155, !dbg !42
+
+155:                                              ; preds = %__nv_rsqrtf.exit10
+  %156 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %130), !dbg !42
+  br label %__nv_rsqrtf.exit13, !dbg !42
+
+157:                                              ; preds = %__nv_rsqrtf.exit10
+  %158 = tail call float @llvm.nvvm.rsqrt.approx.f(float %130), !dbg !42
+  br label %__nv_rsqrtf.exit13, !dbg !42
+
+__nv_rsqrtf.exit13:                               ; preds = %155, %157
+  %.0.i12 = phi float [ %156, %155 ], [ %158, %157 ], !dbg !42
+  %159 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5, !dbg !42
+  %.not.i14 = icmp eq i32 %159, 0, !dbg !42
+  br i1 %.not.i14, label %162, label %160, !dbg !42
+
+160:                                              ; preds = %__nv_rsqrtf.exit13
+  %161 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %131), !dbg !42
+  br label %__nv_rsqrtf.exit16, !dbg !42
+
+162:                                              ; preds = %__nv_rsqrtf.exit13
+  %163 = tail call float @llvm.nvvm.rsqrt.approx.f(float %131), !dbg !42
+  br label %__nv_rsqrtf.exit16, !dbg !42
+
+__nv_rsqrtf.exit16:                               ; preds = %160, %162
+  %.0.i15 = phi float [ %161, %160 ], [ %163, %162 ], !dbg !42
+  %164 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5, !dbg !42
+  %.not.i17 = icmp eq i32 %164, 0, !dbg !42
+  br i1 %.not.i17, label %167, label %165, !dbg !42
+
+165:                                              ; preds = %__nv_rsqrtf.exit16
+  %166 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %132), !dbg !42
+  br label %__nv_rsqrtf.exit19, !dbg !42
+
+167:                                              ; preds = %__nv_rsqrtf.exit16
+  %168 = tail call float @llvm.nvvm.rsqrt.approx.f(float %132), !dbg !42
+  br label %__nv_rsqrtf.exit19, !dbg !42
+
+__nv_rsqrtf.exit19:                               ; preds = %165, %167
+  %.0.i18 = phi float [ %166, %165 ], [ %168, %167 ], !dbg !42
+  %169 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5, !dbg !42
+  %.not.i20 = icmp eq i32 %169, 0, !dbg !42
+  br i1 %.not.i20, label %172, label %170, !dbg !42
+
+170:                                              ; preds = %__nv_rsqrtf.exit19
+  %171 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %133), !dbg !42
+  br label %__nv_rsqrtf.exit22, !dbg !42
+
+172:                                              ; preds = %__nv_rsqrtf.exit19
+  %173 = tail call float @llvm.nvvm.rsqrt.approx.f(float %133), !dbg !42
+  br label %__nv_rsqrtf.exit22, !dbg !42
+
+__nv_rsqrtf.exit22:                               ; preds = %170, %172
+  %.0.i21 = phi float [ %171, %170 ], [ %173, %172 ], !dbg !42
+  %174 = lshr i64 %65, 46, !dbg !43
+  %175 = and i64 %174, 131072, !dbg !43
+  %176 = add i64 %175, %65, !dbg !43
+  %177 = icmp ugt i64 %176, 131071, !dbg !44
+  %.not1 = and i1 %23, %177, !dbg !45
+  br i1 %.not1, label %178, label %179, !dbg !45
+
+178:                                              ; preds = %__nv_rsqrtf.exit22
+  tail call void @__assertfail(ptr nonnull @assertMessage_0, ptr nonnull @assertFile_0, i32 46, ptr nonnull @assertFunc_0, i64 1), !dbg !45
+  unreachable, !dbg !45
+
+179:                                              ; preds = %__nv_rsqrtf.exit22
+  %180 = bitcast i32 %114 to float, !dbg !37
+  %181 = bitcast i32 %113 to float, !dbg !37
+  %182 = bitcast i32 %112 to float, !dbg !37
+  %183 = bitcast i32 %111 to float, !dbg !37
+  %184 = bitcast i32 %110 to float, !dbg !37
+  %185 = bitcast i32 %109 to float, !dbg !37
+  %186 = bitcast i32 %108 to float, !dbg !37
+  %187 = bitcast i32 %107 to float, !dbg !37
+  tail call void @llvm.nvvm.barrier0(), !dbg !45
+  %.idx = shl i64 %176, 8, !dbg !46
+  %188 = getelementptr i8, ptr addrspace(1) %4, i64 %.idx, !dbg !46
+  %189 = getelementptr bfloat, ptr addrspace(1) %188, i64 %60, !dbg !46
+  %190 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];", "=r,=r,=r,=r,l,b"(ptr addrspace(1) %189, i1 %23) #5, !dbg !47
+  %191 = tail call float @llvm.nvvm.div.full(float %187, float 1.280000e+02), !dbg !48
+  %192 = tail call float @llvm.nvvm.div.full(float %186, float 1.280000e+02), !dbg !48
+  %193 = tail call float @llvm.nvvm.div.full(float %185, float 1.280000e+02), !dbg !48
+  %194 = tail call float @llvm.nvvm.div.full(float %184, float 1.280000e+02), !dbg !48
+  %195 = tail call float @llvm.nvvm.div.full(float %183, float 1.280000e+02), !dbg !48
+  %196 = tail call float @llvm.nvvm.div.full(float %182, float 1.280000e+02), !dbg !48
+  %197 = tail call float @llvm.nvvm.div.full(float %181, float 1.280000e+02), !dbg !48
+  %198 = tail call float @llvm.nvvm.div.full(float %180, float 1.280000e+02), !dbg !48
+  %199 = fadd float %191, 0x3EB0C6F7A0000000, !dbg !49
+  %200 = fadd float %192, 0x3EB0C6F7A0000000, !dbg !49
+  %201 = fadd float %193, 0x3EB0C6F7A0000000, !dbg !49
+  %202 = fadd float %194, 0x3EB0C6F7A0000000, !dbg !49
+  %203 = fadd float %195, 0x3EB0C6F7A0000000, !dbg !49
+  %204 = fadd float %196, 0x3EB0C6F7A0000000, !dbg !49
+  %205 = fadd float %197, 0x3EB0C6F7A0000000, !dbg !49
+  %206 = fadd float %198, 0x3EB0C6F7A0000000, !dbg !49
+  %207 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5, !dbg !50
+  %.not.i23 = icmp eq i32 %207, 0, !dbg !50
+  br i1 %.not.i23, label %210, label %208, !dbg !50
+
+208:                                              ; preds = %179
+  %209 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %199), !dbg !50
+  br label %__nv_rsqrtf.exit25, !dbg !50
+
+210:                                              ; preds = %179
+  %211 = tail call float @llvm.nvvm.rsqrt.approx.f(float %199), !dbg !50
+  br label %__nv_rsqrtf.exit25, !dbg !50
+
+__nv_rsqrtf.exit25:                               ; preds = %208, %210
+  %.0.i24 = phi float [ %209, %208 ], [ %211, %210 ], !dbg !50
+  %212 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5, !dbg !50
+  %.not.i26 = icmp eq i32 %212, 0, !dbg !50
+  br i1 %.not.i26, label %215, label %213, !dbg !50
+
+213:                                              ; preds = %__nv_rsqrtf.exit25
+  %214 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %200), !dbg !50
+  br label %__nv_rsqrtf.exit28, !dbg !50
+
+215:                                              ; preds = %__nv_rsqrtf.exit25
+  %216 = tail call float @llvm.nvvm.rsqrt.approx.f(float %200), !dbg !50
+  br label %__nv_rsqrtf.exit28, !dbg !50
+
+__nv_rsqrtf.exit28:                               ; preds = %213, %215
+  %.0.i27 = phi float [ %214, %213 ], [ %216, %215 ], !dbg !50
+  %217 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5, !dbg !50
+  %.not.i29 = icmp eq i32 %217, 0, !dbg !50
+  br i1 %.not.i29, label %220, label %218, !dbg !50
+
+218:                                              ; preds = %__nv_rsqrtf.exit28
+  %219 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %201), !dbg !50
+  br label %__nv_rsqrtf.exit31, !dbg !50
+
+220:                                              ; preds = %__nv_rsqrtf.exit28
+  %221 = tail call float @llvm.nvvm.rsqrt.approx.f(float %201), !dbg !50
+  br label %__nv_rsqrtf.exit31, !dbg !50
+
+__nv_rsqrtf.exit31:                               ; preds = %218, %220
+  %.0.i30 = phi float [ %219, %218 ], [ %221, %220 ], !dbg !50
+  %222 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5, !dbg !50
+  %.not.i32 = icmp eq i32 %222, 0, !dbg !50
+  br i1 %.not.i32, label %225, label %223, !dbg !50
+
+223:                                              ; preds = %__nv_rsqrtf.exit31
+  %224 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %202), !dbg !50
+  br label %__nv_rsqrtf.exit34, !dbg !50
+
+225:                                              ; preds = %__nv_rsqrtf.exit31
+  %226 = tail call float @llvm.nvvm.rsqrt.approx.f(float %202), !dbg !50
+  br label %__nv_rsqrtf.exit34, !dbg !50
+
+__nv_rsqrtf.exit34:                               ; preds = %223, %225
+  %.0.i33 = phi float [ %224, %223 ], [ %226, %225 ], !dbg !50
+  %227 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5, !dbg !50
+  %.not.i35 = icmp eq i32 %227, 0, !dbg !50
+  br i1 %.not.i35, label %230, label %228, !dbg !50
+
+228:                                              ; preds = %__nv_rsqrtf.exit34
+  %229 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %203), !dbg !50
+  br label %__nv_rsqrtf.exit37, !dbg !50
+
+230:                                              ; preds = %__nv_rsqrtf.exit34
+  %231 = tail call float @llvm.nvvm.rsqrt.approx.f(float %203), !dbg !50
+  br label %__nv_rsqrtf.exit37, !dbg !50
+
+__nv_rsqrtf.exit37:                               ; preds = %228, %230
+  %.0.i36 = phi float [ %229, %228 ], [ %231, %230 ], !dbg !50
+  %232 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5, !dbg !50
+  %.not.i38 = icmp eq i32 %232, 0, !dbg !50
+  br i1 %.not.i38, label %235, label %233, !dbg !50
+
+233:                                              ; preds = %__nv_rsqrtf.exit37
+  %234 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %204), !dbg !50
+  br label %__nv_rsqrtf.exit40, !dbg !50
+
+235:                                              ; preds = %__nv_rsqrtf.exit37
+  %236 = tail call float @llvm.nvvm.rsqrt.approx.f(float %204), !dbg !50
+  br label %__nv_rsqrtf.exit40, !dbg !50
+
+__nv_rsqrtf.exit40:                               ; preds = %233, %235
+  %.0.i39 = phi float [ %234, %233 ], [ %236, %235 ], !dbg !50
+  %237 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5, !dbg !50
+  %.not.i41 = icmp eq i32 %237, 0, !dbg !50
+  br i1 %.not.i41, label %240, label %238, !dbg !50
+
+238:                                              ; preds = %__nv_rsqrtf.exit40
+  %239 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %205), !dbg !50
+  br label %__nv_rsqrtf.exit43, !dbg !50
+
+240:                                              ; preds = %__nv_rsqrtf.exit40
+  %241 = tail call float @llvm.nvvm.rsqrt.approx.f(float %205), !dbg !50
+  br label %__nv_rsqrtf.exit43, !dbg !50
+
+__nv_rsqrtf.exit43:                               ; preds = %238, %240
+  %.0.i42 = phi float [ %239, %238 ], [ %241, %240 ], !dbg !50
+  %242 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5, !dbg !50
+  %.not.i44 = icmp eq i32 %242, 0, !dbg !50
+  br i1 %.not.i44, label %245, label %243, !dbg !50
+
+243:                                              ; preds = %__nv_rsqrtf.exit43
+  %244 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %206), !dbg !50
+  br label %__nv_rsqrtf.exit46, !dbg !50
+
+245:                                              ; preds = %__nv_rsqrtf.exit43
+  %246 = tail call float @llvm.nvvm.rsqrt.approx.f(float %206), !dbg !50
+  br label %__nv_rsqrtf.exit46, !dbg !50
+
+__nv_rsqrtf.exit46:                               ; preds = %243, %245
+  %.0.i45 = phi float [ %244, %243 ], [ %246, %245 ], !dbg !50
+  %247 = extractvalue { i32, i32, i32, i32 } %41, 3, !dbg !25
+  %248 = bitcast i32 %247 to <2 x bfloat>, !dbg !25
+  %249 = extractvalue { i32, i32, i32, i32 } %62, 3, !dbg !29
+  %250 = bitcast i32 %249 to <2 x bfloat>, !dbg !29
+  %251 = extractvalue { i32, i32, i32, i32 } %190, 3, !dbg !47
+  %252 = bitcast i32 %251 to <2 x bfloat>, !dbg !47
+  %253 = extractvalue { i32, i32, i32, i32 } %41, 2, !dbg !25
+  %254 = bitcast i32 %253 to <2 x bfloat>, !dbg !25
+  %255 = extractvalue { i32, i32, i32, i32 } %62, 2, !dbg !29
+  %256 = bitcast i32 %255 to <2 x bfloat>, !dbg !29
+  %257 = extractvalue { i32, i32, i32, i32 } %190, 2, !dbg !47
+  %258 = bitcast i32 %257 to <2 x bfloat>, !dbg !47
+  %259 = extractvalue { i32, i32, i32, i32 } %41, 1, !dbg !25
+  %260 = bitcast i32 %259 to <2 x bfloat>, !dbg !25
+  %261 = extractvalue { i32, i32, i32, i32 } %62, 1, !dbg !29
+  %262 = bitcast i32 %261 to <2 x bfloat>, !dbg !29
+  %263 = extractvalue { i32, i32, i32, i32 } %190, 1, !dbg !47
+  %264 = bitcast i32 %263 to <2 x bfloat>, !dbg !47
+  %265 = extractvalue { i32, i32, i32, i32 } %41, 0, !dbg !25
+  %266 = bitcast i32 %265 to <2 x bfloat>, !dbg !25
+  %267 = extractvalue { i32, i32, i32, i32 } %62, 0, !dbg !29
+  %268 = bitcast i32 %267 to <2 x bfloat>, !dbg !29
+  %269 = extractvalue { i32, i32, i32, i32 } %190, 0, !dbg !47
+  %270 = bitcast i32 %269 to <2 x bfloat>, !dbg !47
+  %271 = insertelement <2 x i16> poison, i16 %99, i64 0, !dbg !36
+  %272 = insertelement <2 x i16> %271, i16 %100, i64 1, !dbg !36
+  %273 = bitcast <2 x i16> %272 to <2 x bfloat>, !dbg !36
+  %274 = insertelement <2 x i16> poison, i16 %101, i64 0, !dbg !36
+  %275 = insertelement <2 x i16> %274, i16 %102, i64 1, !dbg !36
+  %276 = bitcast <2 x i16> %275 to <2 x bfloat>, !dbg !36
+  %277 = insertelement <2 x i16> poison, i16 %103, i64 0, !dbg !36
+  %278 = insertelement <2 x i16> %277, i16 %104, i64 1, !dbg !36
+  %279 = bitcast <2 x i16> %278 to <2 x bfloat>, !dbg !36
+  %280 = insertelement <2 x i16> poison, i16 %105, i64 0, !dbg !36
+  %281 = insertelement <2 x i16> %280, i16 %106, i64 1, !dbg !36
+  %282 = bitcast <2 x i16> %281 to <2 x bfloat>, !dbg !36
+  %283 = extractvalue { i32, i32, i32, i32 } %117, 0, !dbg !39
+  %284 = bitcast i32 %283 to <2 x bfloat>, !dbg !39
+  %285 = extractvalue { i32, i32, i32, i32 } %117, 1, !dbg !39
+  %286 = bitcast i32 %285 to <2 x bfloat>, !dbg !39
+  %287 = extractvalue { i32, i32, i32, i32 } %117, 2, !dbg !39
+  %288 = bitcast i32 %287 to <2 x bfloat>, !dbg !39
+  %289 = extractvalue { i32, i32, i32, i32 } %117, 3, !dbg !39
+  %290 = bitcast i32 %289 to <2 x bfloat>, !dbg !39
+  %291 = getelementptr bfloat, ptr addrspace(1) %188, i64 %115, !dbg !51
+  %292 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];", "=r,=r,=r,=r,l,b"(ptr addrspace(1) %291, i1 %23) #5, !dbg !52
+  %293 = extractvalue { i32, i32, i32, i32 } %292, 0, !dbg !52
+  %294 = bitcast i32 %293 to <2 x bfloat>, !dbg !52
+  %295 = extractvalue { i32, i32, i32, i32 } %292, 1, !dbg !52
+  %296 = bitcast i32 %295 to <2 x bfloat>, !dbg !52
+  %297 = extractvalue { i32, i32, i32, i32 } %292, 2, !dbg !52
+  %298 = bitcast i32 %297 to <2 x bfloat>, !dbg !52
+  %299 = extractvalue { i32, i32, i32, i32 } %292, 3, !dbg !52
+  %300 = bitcast i32 %299 to <2 x bfloat>, !dbg !52
+  %301 = shl i32 %24, 7, !dbg !53
+  %302 = add i32 %301, %.decomposed, !dbg !54
+  %303 = sext i32 %302 to i64, !dbg !55
+  %304 = getelementptr bfloat, ptr addrspace(1) %5, i64 %303, !dbg !55
+  %305 = fpext <2 x bfloat> %266 to <2 x float>, !dbg !56
+  %306 = insertelement <2 x float> poison, float %.0.i, i64 0, !dbg !57
+  %307 = insertelement <2 x float> %306, float %.0.i3, i64 1, !dbg !57
+  %308 = fmul <2 x float> %307, %305, !dbg !57
+  %309 = fpext <2 x bfloat> %268 to <2 x float>, !dbg !58
+  %310 = fmul <2 x float> %308, %309, !dbg !59
+  %311 = fpext <2 x bfloat> %270 to <2 x float>, !dbg !60
+  %312 = fmul <2 x float> %310, %311, !dbg !61
+  %313 = fpext <2 x bfloat> %273 to <2 x float>, !dbg !62
+  %314 = fpext <2 x bfloat> %284 to <2 x float>, !dbg !63
+  %315 = insertelement <2 x float> poison, float %.0.i24, i64 0, !dbg !64
+  %316 = insertelement <2 x float> %315, float %.0.i27, i64 1, !dbg !64
+  %317 = fmul <2 x float> %316, %313, !dbg !64
+  %318 = fmul <2 x float> %317, %314, !dbg !65
+  %319 = fpext <2 x bfloat> %294 to <2 x float>, !dbg !66
+  %320 = fmul <2 x float> %318, %319, !dbg !67
+  %321 = fsub <2 x float> %312, %320, !dbg !68
+  %322 = fptrunc <2 x float> %321 to <2 x bfloat>, !dbg !69
+  %323 = fpext <2 x bfloat> %260 to <2 x float>, !dbg !56
+  %324 = insertelement <2 x float> poison, float %.0.i6, i64 0, !dbg !57
+  %325 = insertelement <2 x float> %324, float %.0.i9, i64 1, !dbg !57
+  %326 = fmul <2 x float> %325, %323, !dbg !57
+  %327 = fpext <2 x bfloat> %262 to <2 x float>, !dbg !58
+  %328 = fmul <2 x float> %326, %327, !dbg !59
+  %329 = fpext <2 x bfloat> %264 to <2 x float>, !dbg !60
+  %330 = fmul <2 x float> %328, %329, !dbg !61
+  %331 = fpext <2 x bfloat> %276 to <2 x float>, !dbg !62
+  %332 = fpext <2 x bfloat> %286 to <2 x float>, !dbg !63
+  %333 = insertelement <2 x float> poison, float %.0.i30, i64 0, !dbg !64
+  %334 = insertelement <2 x float> %333, float %.0.i33, i64 1, !dbg !64
+  %335 = fmul <2 x float> %334, %331, !dbg !64
+  %336 = fmul <2 x float> %335, %332, !dbg !65
+  %337 = fpext <2 x bfloat> %296 to <2 x float>, !dbg !66
+  %338 = fmul <2 x float> %336, %337, !dbg !67
+  %339 = fsub <2 x float> %330, %338, !dbg !68
+  %340 = fptrunc <2 x float> %339 to <2 x bfloat>, !dbg !69
+  %341 = fpext <2 x bfloat> %254 to <2 x float>, !dbg !56
+  %342 = insertelement <2 x float> poison, float %.0.i12, i64 0, !dbg !57
+  %343 = insertelement <2 x float> %342, float %.0.i15, i64 1, !dbg !57
+  %344 = fmul <2 x float> %343, %341, !dbg !57
+  %345 = fpext <2 x bfloat> %256 to <2 x float>, !dbg !58
+  %346 = fmul <2 x float> %344, %345, !dbg !59
+  %347 = fpext <2 x bfloat> %258 to <2 x float>, !dbg !60
+  %348 = fmul <2 x float> %346, %347, !dbg !61
+  %349 = fpext <2 x bfloat> %279 to <2 x float>, !dbg !62
+  %350 = fpext <2 x bfloat> %288 to <2 x float>, !dbg !63
+  %351 = insertelement <2 x float> poison, float %.0.i36, i64 0, !dbg !64
+  %352 = insertelement <2 x float> %351, float %.0.i39, i64 1, !dbg !64
+  %353 = fmul <2 x float> %352, %349, !dbg !64
+  %354 = fmul <2 x float> %353, %350, !dbg !65
+  %355 = fpext <2 x bfloat> %298 to <2 x float>, !dbg !66
+  %356 = fmul <2 x float> %354, %355, !dbg !67
+  %357 = fsub <2 x float> %348, %356, !dbg !68
+  %358 = fptrunc <2 x float> %357 to <2 x bfloat>, !dbg !69
+  %359 = fpext <2 x bfloat> %248 to <2 x float>, !dbg !56
+  %360 = insertelement <2 x float> poison, float %.0.i18, i64 0, !dbg !57
+  %361 = insertelement <2 x float> %360, float %.0.i21, i64 1, !dbg !57
+  %362 = fmul <2 x float> %361, %359, !dbg !57
+  %363 = fpext <2 x bfloat> %250 to <2 x float>, !dbg !58
+  %364 = fmul <2 x float> %362, %363, !dbg !59
+  %365 = fpext <2 x bfloat> %252 to <2 x float>, !dbg !60
+  %366 = fmul <2 x float> %364, %365, !dbg !61
+  %367 = fpext <2 x bfloat> %282 to <2 x float>, !dbg !62
+  %368 = fpext <2 x bfloat> %290 to <2 x float>, !dbg !63
+  %369 = insertelement <2 x float> poison, float %.0.i42, i64 0, !dbg !64
+  %370 = insertelement <2 x float> %369, float %.0.i45, i64 1, !dbg !64
+  %371 = fmul <2 x float> %370, %367, !dbg !64
+  %372 = fmul <2 x float> %371, %368, !dbg !65
+  %373 = fpext <2 x bfloat> %300 to <2 x float>, !dbg !66
+  %374 = fmul <2 x float> %372, %373, !dbg !67
+  %375 = fsub <2 x float> %366, %374, !dbg !68
+  %376 = fptrunc <2 x float> %375 to <2 x bfloat>, !dbg !69
+  %377 = bitcast <2 x bfloat> %322 to i32, !dbg !69
+  %378 = bitcast <2 x bfloat> %340 to i32, !dbg !69
+  %379 = bitcast <2 x bfloat> %358 to i32, !dbg !69
+  %380 = bitcast <2 x bfloat> %376 to i32, !dbg !69
+  tail call void asm sideeffect "@$5 st.global.v4.b32 [ $4 + 0 ], { $0, $1, $2, $3 };", "r,r,r,r,l,b"(i32 %377, i32 %378, i32 %379, i32 %380, ptr addrspace(1) %304, i1 %23) #5, !dbg !69
+  %381 = getelementptr bfloat, ptr addrspace(1) %6, i64 %303, !dbg !70
+  %382 = fmul <2 x float> %318, %311, !dbg !71
+  %383 = fmul <2 x float> %310, %319, !dbg !72
+  %384 = fadd <2 x float> %382, %383, !dbg !73
+  %385 = fptrunc <2 x float> %384 to <2 x bfloat>, !dbg !74
+  %386 = fmul <2 x float> %336, %329, !dbg !71
+  %387 = fmul <2 x float> %328, %337, !dbg !72
+  %388 = fadd <2 x float> %386, %387, !dbg !73
+  %389 = fptrunc <2 x float> %388 to <2 x bfloat>, !dbg !74
+  %390 = fmul <2 x float> %354, %347, !dbg !71
+  %391 = fmul <2 x float> %346, %355, !dbg !72
+  %392 = fadd <2 x float> %390, %391, !dbg !73
+  %393 = fptrunc <2 x float> %392 to <2 x bfloat>, !dbg !74
+  %394 = fmul <2 x float> %372, %365, !dbg !71
+  %395 = fmul <2 x float> %364, %373, !dbg !72
+  %396 = fadd <2 x float> %394, %395, !dbg !73
+  %397 = fptrunc <2 x float> %396 to <2 x bfloat>, !dbg !74
+  %398 = bitcast <2 x bfloat> %385 to i32, !dbg !74
+  %399 = bitcast <2 x bfloat> %389 to i32, !dbg !74
+  %400 = bitcast <2 x bfloat> %393 to i32, !dbg !74
+  %401 = bitcast <2 x bfloat> %397 to i32, !dbg !74
+  tail call void asm sideeffect "@$5 st.global.v4.b32 [ $4 + 0 ], { $0, $1, $2, $3 };", "r,r,r,r,l,b"(i32 %398, i32 %399, i32 %400, i32 %401, ptr addrspace(1) %381, i1 %23) #5, !dbg !74
+  ret void, !dbg !75
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.ctaid.x() #1
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.x() #1
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
+declare float @llvm.nvvm.div.full(float, float) #2
+
+; Function Attrs: convergent nocallback nounwind
+declare void @llvm.nvvm.barrier0() #3
+
+declare i32 @__nvvm_reflect(ptr) local_unnamed_addr #4
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
+declare float @llvm.nvvm.rsqrt.approx.ftz.f(float) #2
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
+declare float @llvm.nvvm.rsqrt.approx.f(float) #2
+
+attributes #0 = { noreturn }
+attributes #1 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #2 = { mustprogress nocallback nofree nosync nounwind willreturn memory(none) }
+attributes #3 = { convergent nocallback nounwind }
+attributes #4 = { "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #5 = { nounwind }
+
+!llvm.module.flags = !{!0, !1}
+!llvm.dbg.cu = !{!2}
+!nvvm.annotations = !{!4}
+!llvm.ident = !{!5}
+
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = !{i32 4, !"nvvm-reflect-ftz", i32 1}
+!2 = distinct !DICompileUnit(language: DW_LANG_C, file: !3, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: LineTablesOnly)
+!3 = !DIFile(filename: "cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py", directory: "/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa")
+!4 = !{ptr @triton_poi_fused_add_mul_sub_5, !"reqntidx", i32 128}
+!5 = !{!"clang version 3.8.0 (tags/RELEASE_380/final)"}
+!6 = !DISubprogram(name: "__assertfail", linkageName: "__assertfail", scope: !7, file: !7, type: !8, spFlags: DISPFlagOptimized)
+!7 = !DIFile(filename: "<unknown>", directory: "")
+!8 = !DISubroutineType(cc: DW_CC_normal, types: !9)
+!9 = !{}
+!10 = distinct !DISubprogram(name: "triton_poi_fused_add_mul_sub_5", linkageName: "triton_poi_fused_add_mul_sub_5", scope: !3, file: !3, line: 18, type: !8, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !2)
+!11 = !DILocation(line: 19, column: 28, scope: !10)
+!12 = !DILocation(line: 19, column: 33, scope: !10)
+!13 = !DILocation(line: 20, column: 36, scope: !10)
+!14 = !DILocation(line: 20, column: 23, scope: !10)
+!15 = !DILocation(line: 21, column: 21, scope: !10)
+!16 = !DILocation(line: 23, column: 21, scope: !10)
+!17 = !DILocation(line: 22, column: 19, scope: !10)
+!18 = !DILocation(line: 23, column: 27, scope: !10)
+!19 = !DILocation(line: 24, column: 19, scope: !10)
+!20 = !DILocation(line: 26, column: 39, scope: !10)
+!21 = !DILocation(line: 26, column: 49, scope: !10)
+!22 = !DILocation(line: 26, column: 35, scope: !10)
+!23 = !DILocation(line: 26, column: 44, scope: !10)
+!24 = !DILocation(line: 26, column: 30, scope: !10)
+!25 = !DILocation(line: 26, column: 54, scope: !10)
+!26 = !DILocation(line: 27, column: 30, scope: !10)
+!27 = !DILocation(line: 27, column: 35, scope: !10)
+!28 = !DILocation(line: 28, column: 31, scope: !10)
+!29 = !DILocation(line: 28, column: 36, scope: !10)
+!30 = !DILocation(line: 29, column: 31, scope: !10)
+!31 = !DILocation(line: 29, column: 36, scope: !10)
+!32 = !DILocation(line: 30, column: 36, scope: !10)
+!33 = !DILocation(line: 30, column: 75, scope: !10)
+!34 = !DILocation(line: 30, column: 41, scope: !10)
+!35 = !DILocation(line: 30, column: 31, scope: !10)
+!36 = !DILocation(line: 30, column: 85, scope: !10)
+!37 = !DILocation(line: 31, column: 57, scope: !10)
+!38 = !DILocation(line: 32, column: 31, scope: !10)
+!39 = !DILocation(line: 32, column: 41, scope: !10)
+!40 = !DILocation(line: 35, column: 19, scope: !10)
+!41 = !DILocation(line: 37, column: 18, scope: !10)
+!42 = !DILocation(line: 38, column: 27, scope: !10)
+!43 = !DILocation(line: 45, column: 35, scope: !10)
+!44 = !DILocation(line: 46, column: 38, scope: !10)
+!45 = !DILocation(line: 46, column: 67, scope: !10)
+!46 = !DILocation(line: 47, column: 31, scope: !10)
+!47 = !DILocation(line: 47, column: 48, scope: !10)
+!48 = !DILocation(line: 50, column: 21, scope: !10)
+!49 = !DILocation(line: 51, column: 20, scope: !10)
+!50 = !DILocation(line: 52, column: 28, scope: !10)
+!51 = !DILocation(line: 56, column: 31, scope: !10)
+!52 = !DILocation(line: 56, column: 53, scope: !10)
+!53 = !DILocation(line: 62, column: 34, scope: !10)
+!54 = !DILocation(line: 62, column: 30, scope: !10)
+!55 = !DILocation(line: 62, column: 25, scope: !10)
+!56 = !DILocation(line: 26, column: 64, scope: !10)
+!57 = !DILocation(line: 39, column: 18, scope: !10)
+!58 = !DILocation(line: 28, column: 76, scope: !10)
+!59 = !DILocation(line: 41, column: 19, scope: !10)
+!60 = !DILocation(line: 47, column: 58, scope: !10)
+!61 = !DILocation(line: 48, column: 20, scope: !10)
+!62 = !DILocation(line: 30, column: 95, scope: !10)
+!63 = !DILocation(line: 32, column: 81, scope: !10)
+!64 = !DILocation(line: 53, column: 20, scope: !10)
+!65 = !DILocation(line: 55, column: 20, scope: !10)
+!66 = !DILocation(line: 56, column: 63, scope: !10)
+!67 = !DILocation(line: 57, column: 20, scope: !10)
+!68 = !DILocation(line: 58, column: 20, scope: !10)
+!69 = !DILocation(line: 62, column: 46, scope: !10)
+!70 = !DILocation(line: 63, column: 25, scope: !10)
+!71 = !DILocation(line: 59, column: 20, scope: !10)
+!72 = !DILocation(line: 60, column: 20, scope: !10)
+!73 = !DILocation(line: 61, column: 20, scope: !10)
+!74 = !DILocation(line: 63, column: 46, scope: !10)
+!75 = !DILocation(line: 63, column: 4, scope: !10)

platform/aiml/models/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/4VKD4PBE7ZFPVR2HT6BRTSPMGIUGA2E7B3L3R5SB4CN4JM7KMHOQ/triton_poi_fused_add_mul_sub_5.ptx

@@ -0,0 +1,894 @@
+//
+// Generated by LLVM NVPTX Back-End
+//
+
+.version 8.4
+.target sm_90a
+.address_size 64
+
+	// .globl	triton_poi_fused_add_mul_sub_5 // -- Begin function triton_poi_fused_add_mul_sub_5
+.extern .func __assertfail
+(
+	.param .b64 __assertfail_param_0,
+	.param .b64 __assertfail_param_1,
+	.param .b32 __assertfail_param_2,
+	.param .b64 __assertfail_param_3,
+	.param .b64 __assertfail_param_4
+)
+.noreturn;
+.global .align 1 .b8 assertFunc_0[8] = {117, 110, 107, 110, 111, 119, 110};
+.global .align 1 .b8 assertFile_0[134] = {47, 104, 111, 109, 101, 47, 120, 47, 46, 99, 97, 99, 104, 101, 47, 118, 108, 108, 109, 47, 116, 111, 114, 99, 104, 95, 99, 111, 109, 112, 105, 108, 101, 95, 99, 97, 99, 104, 101, 47, 99, 50, 50, 48, 50, 51, 56, 102, 97, 49, 47, 114, 97, 110, 107, 95, 48, 95, 48, 47, 105, 110, 100, 117, 99, 116, 111, 114, 95, 99, 97, 99, 104, 101, 47, 113, 97, 47, 99, 113, 97, 99, 102, 50, 55, 103, 110, 98, 52, 99, 113, 52, 109, 120, 114, 120, 110, 115, 111, 53, 98, 101, 102, 99, 97, 54, 101, 109, 55, 120, 53, 53, 113, 107, 108, 110, 100, 102, 105, 104, 51, 55, 111, 50, 106, 122, 105, 115, 120, 110, 46, 112, 121};
+.global .align 1 .b8 assertMessage_0[41] = {105, 110, 100, 101, 120, 32, 111, 117, 116, 32, 111, 102, 32, 98, 111, 117, 110, 100, 115, 58, 32, 48, 32, 60, 61, 32, 116, 109, 112, 49, 54, 32, 60, 32, 49, 51, 49, 48, 55, 50};
+.global .align 1 .b8 _$_str[11] = {95, 95, 67, 85, 68, 65, 95, 70, 84, 90};
+                                        // @triton_poi_fused_add_mul_sub_5
+.visible .entry triton_poi_fused_add_mul_sub_5(
+	.param .u64 .ptr .global .align 1 triton_poi_fused_add_mul_sub_5_param_0,
+	.param .u64 .ptr .global .align 1 triton_poi_fused_add_mul_sub_5_param_1,
+	.param .u64 .ptr .global .align 1 triton_poi_fused_add_mul_sub_5_param_2,
+	.param .u64 .ptr .global .align 1 triton_poi_fused_add_mul_sub_5_param_3,
+	.param .u64 .ptr .global .align 1 triton_poi_fused_add_mul_sub_5_param_4,
+	.param .u64 .ptr .global .align 1 triton_poi_fused_add_mul_sub_5_param_5,
+	.param .u64 .ptr .global .align 1 triton_poi_fused_add_mul_sub_5_param_6,
+	.param .u32 triton_poi_fused_add_mul_sub_5_param_7,
+	.param .u64 .ptr .global .align 1 triton_poi_fused_add_mul_sub_5_param_8
+)
+.reqntid 128, 1, 1
+{
+	.reg .pred 	%p<43>;
+	.reg .b16 	%rs<65>;
+	.reg .b32 	%r<128>;
+	.reg .f32 	%f<187>;
+	.reg .b64 	%rd<106>;
+	.loc	1 18 0                          // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:18:0
+$L__func_begin0:
+	.loc	1 18 0                          // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:18:0
+
+// %bb.0:                               // %__nv_rsqrtf.exit
+	ld.param.u32 	%r23, [triton_poi_fused_add_mul_sub_5_param_7];
+	ld.param.u64 	%rd50, [triton_poi_fused_add_mul_sub_5_param_0];
+	ld.param.u64 	%rd51, [triton_poi_fused_add_mul_sub_5_param_1];
+$L__tmp0:
+	.loc	1 19 28                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:19:28
+	mov.u32 	%r52, %ctaid.x;
+	.loc	1 19 33                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:19:33
+	shl.b32 	%r53, %r52, 10;
+	ld.param.u64 	%rd52, [triton_poi_fused_add_mul_sub_5_param_2];
+	ld.param.u64 	%rd53, [triton_poi_fused_add_mul_sub_5_param_3];
+	.loc	1 20 36                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:20:36
+	mov.u32 	%r54, %tid.x;
+	shl.b32 	%r55, %r54, 3;
+	and.b32  	%r56, %r55, 1016;
+	.loc	1 20 23                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:20:23
+	or.b32  	%r1, %r56, %r53;
+	or.b32  	%r57, %r1, 1;
+	or.b32  	%r58, %r1, 2;
+	or.b32  	%r59, %r1, 3;
+	or.b32  	%r60, %r1, 4;
+	or.b32  	%r61, %r1, 5;
+	or.b32  	%r62, %r1, 6;
+	or.b32  	%r63, %r1, 7;
+	.loc	1 21 21                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:21:21
+	setp.ge.s32 	%p36, %r1, %r23;
+	setp.lt.s32 	%p35, %r1, %r23;
+	.loc	1 23 21                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:23:21
+	bfe.s32 	%r64, %r52, 21, 1;
+	.loc	1 22 19                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:22:19
+	shr.u32 	%r65, %r64, 26;
+	.loc	1 23 21                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:23:21
+	add.s32 	%r66, %r1, %r65;
+	shr.s32 	%r2, %r66, 6;
+	.loc	1 22 19                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:22:19
+	and.b32  	%r67, %r66, -64;
+	sub.s32 	%r68, %r1, %r67;
+	add.s32 	%r69, %r57, %r65;
+	and.b32  	%r70, %r69, -64;
+	sub.s32 	%r71, %r57, %r70;
+	add.s32 	%r72, %r58, %r65;
+	and.b32  	%r73, %r72, -64;
+	sub.s32 	%r74, %r58, %r73;
+	add.s32 	%r75, %r59, %r65;
+	and.b32  	%r76, %r75, -64;
+	sub.s32 	%r77, %r59, %r76;
+	add.s32 	%r78, %r60, %r65;
+	and.b32  	%r79, %r78, -64;
+	sub.s32 	%r80, %r60, %r79;
+	add.s32 	%r81, %r61, %r65;
+	and.b32  	%r82, %r81, -64;
+	sub.s32 	%r83, %r61, %r82;
+	add.s32 	%r84, %r62, %r65;
+	and.b32  	%r85, %r84, -64;
+	sub.s32 	%r86, %r62, %r85;
+	add.s32 	%r87, %r63, %r65;
+	and.b32  	%r88, %r87, -64;
+	sub.s32 	%r89, %r63, %r88;
+	.loc	1 23 27                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:23:27
+	mul.hi.s32 	%r90, %r2, 1717986919;
+	shr.u32 	%r91, %r90, 31;
+	shr.u32 	%r92, %r90, 4;
+	add.s32 	%r93, %r92, %r91;
+	mul.lo.s32 	%r94, %r93, 40;
+	sub.s32 	%r95, %r2, %r94;
+	.loc	1 24 19                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:24:19
+	mul.hi.s32 	%r96, %r1, 1717986919;
+	shr.u32 	%r97, %r96, 31;
+	shr.s32 	%r98, %r96, 10;
+	add.s32 	%r99, %r98, %r97;
+	.loc	1 26 39                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:26:39
+	shl.b32 	%r100, %r95, 7;
+	.loc	1 26 35                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:26:35
+	mad.lo.s32 	%r101, %r99, 7168, %r100;
+	.loc	1 26 44                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:26:44
+	add.s32 	%r102, %r101, %r68;
+	.loc	1 26 30                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:26:30
+	mul.wide.s32 	%rd54, %r102, 2;
+	add.s64 	%rd7, %rd50, %rd54;
+	.loc	1 26 54                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:26:54
+	// begin inline asm
+	mov.u32 %r24, 0x0;
+	mov.u32 %r25, 0x0;
+	mov.u32 %r26, 0x0;
+	mov.u32 %r27, 0x0;
+	@%p35 ld.global.v4.b32 { %r24, %r25, %r26, %r27 }, [ %rd7 + 0 ];
+	// end inline asm
+	.loc	1 27 30                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:27:30
+	mul.wide.s32 	%rd55, %r2, 4;
+	add.s64 	%rd8, %rd51, %rd55;
+	.loc	1 27 35                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:27:35
+	// begin inline asm
+	mov.u32 %r28, 0x0;
+	@%p35 ld.global.L1::evict_last.b32 { %r28 }, [ %rd8 + 0 ];
+	// end inline asm
+	// begin inline asm
+	mov.u32 %r29, 0x0;
+	@%p35 ld.global.L1::evict_last.b32 { %r29 }, [ %rd8 + 0 ];
+	// end inline asm
+	// begin inline asm
+	mov.u32 %r30, 0x0;
+	@%p35 ld.global.L1::evict_last.b32 { %r30 }, [ %rd8 + 0 ];
+	// end inline asm
+	// begin inline asm
+	mov.u32 %r31, 0x0;
+	@%p35 ld.global.L1::evict_last.b32 { %r31 }, [ %rd8 + 0 ];
+	// end inline asm
+	// begin inline asm
+	mov.u32 %r32, 0x0;
+	@%p35 ld.global.L1::evict_last.b32 { %r32 }, [ %rd8 + 0 ];
+	// end inline asm
+	// begin inline asm
+	mov.u32 %r33, 0x0;
+	@%p35 ld.global.L1::evict_last.b32 { %r33 }, [ %rd8 + 0 ];
+	// end inline asm
+	// begin inline asm
+	mov.u32 %r34, 0x0;
+	@%p35 ld.global.L1::evict_last.b32 { %r34 }, [ %rd8 + 0 ];
+	// end inline asm
+	// begin inline asm
+	mov.u32 %r35, 0x0;
+	@%p35 ld.global.L1::evict_last.b32 { %r35 }, [ %rd8 + 0 ];
+	// end inline asm
+	.loc	1 28 31                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:28:31
+	mul.wide.s32 	%rd56, %r68, 2;
+	add.s64 	%rd16, %rd52, %rd56;
+	.loc	1 28 36                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:28:36
+	// begin inline asm
+	mov.u32 %r36, 0x0;
+	mov.u32 %r37, 0x0;
+	mov.u32 %r38, 0x0;
+	mov.u32 %r39, 0x0;
+	@%p35 ld.global.L1::evict_last.v4.b32 { %r36, %r37, %r38, %r39 }, [ %rd16 + 0 ];
+	// end inline asm
+	.loc	1 29 31                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:29:31
+	mul.wide.s32 	%rd57, %r99, 8;
+	add.s64 	%rd18, %rd53, %rd57;
+	.loc	1 29 36                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:29:36
+	// begin inline asm
+	mov.u64 %rd17, 0x0;
+	@%p35 ld.global.L1::evict_last.b64 { %rd17 }, [ %rd18 + 0 ];
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd19, 0x0;
+	@%p35 ld.global.L1::evict_last.b64 { %rd19 }, [ %rd18 + 0 ];
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd21, 0x0;
+	@%p35 ld.global.L1::evict_last.b64 { %rd21 }, [ %rd18 + 0 ];
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd23, 0x0;
+	@%p35 ld.global.L1::evict_last.b64 { %rd23 }, [ %rd18 + 0 ];
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd25, 0x0;
+	@%p35 ld.global.L1::evict_last.b64 { %rd25 }, [ %rd18 + 0 ];
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd27, 0x0;
+	@%p35 ld.global.L1::evict_last.b64 { %rd27 }, [ %rd18 + 0 ];
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd29, 0x0;
+	@%p35 ld.global.L1::evict_last.b64 { %rd29 }, [ %rd18 + 0 ];
+	// end inline asm
+	// begin inline asm
+	mov.u64 %rd31, 0x0;
+	@%p35 ld.global.L1::evict_last.b64 { %rd31 }, [ %rd18 + 0 ];
+	// end inline asm
+	.loc	1 30 36                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:30:36
+	add.s32 	%r103, %r68, 64;
+	.loc	1 30 75                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:30:75
+	add.s32 	%r104, %r101, %r103;
+	.loc	1 30 31                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:30:31
+	mul.wide.s32 	%rd58, %r104, 2;
+	add.s64 	%rd33, %rd50, %rd58;
+	cvt.s64.s32 	%rd59, %r71;
+	cvt.s64.s32 	%rd60, %r101;
+	add.s64 	%rd61, %rd60, %rd59;
+	shl.b64 	%rd62, %rd61, 1;
+	add.s64 	%rd63, %rd50, %rd62;
+	add.s64 	%rd34, %rd63, 128;
+	cvt.s64.s32 	%rd64, %r74;
+	add.s64 	%rd65, %rd60, %rd64;
+	shl.b64 	%rd66, %rd65, 1;
+	add.s64 	%rd67, %rd50, %rd66;
+	add.s64 	%rd35, %rd67, 128;
+	cvt.s64.s32 	%rd68, %r77;
+	add.s64 	%rd69, %rd60, %rd68;
+	shl.b64 	%rd70, %rd69, 1;
+	add.s64 	%rd71, %rd50, %rd70;
+	add.s64 	%rd36, %rd71, 128;
+	cvt.s64.s32 	%rd72, %r80;
+	add.s64 	%rd73, %rd60, %rd72;
+	shl.b64 	%rd74, %rd73, 1;
+	add.s64 	%rd75, %rd50, %rd74;
+	add.s64 	%rd37, %rd75, 128;
+	cvt.s64.s32 	%rd76, %r83;
+	add.s64 	%rd77, %rd60, %rd76;
+	shl.b64 	%rd78, %rd77, 1;
+	add.s64 	%rd79, %rd50, %rd78;
+	add.s64 	%rd38, %rd79, 128;
+	cvt.s64.s32 	%rd80, %r86;
+	add.s64 	%rd81, %rd60, %rd80;
+	shl.b64 	%rd82, %rd81, 1;
+	add.s64 	%rd83, %rd50, %rd82;
+	add.s64 	%rd39, %rd83, 128;
+	cvt.s64.s32 	%rd84, %r89;
+	add.s64 	%rd85, %rd60, %rd84;
+	shl.b64 	%rd86, %rd85, 1;
+	add.s64 	%rd87, %rd50, %rd86;
+	add.s64 	%rd40, %rd87, 128;
+	.loc	1 30 85                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:30:85
+	// begin inline asm
+	mov.u16 %rs9, 0x0;
+	@%p35 ld.global.b16 { %rs9 }, [ %rd33 + 0 ];
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs10, 0x0;
+	@%p35 ld.global.b16 { %rs10 }, [ %rd34 + 0 ];
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs11, 0x0;
+	@%p35 ld.global.b16 { %rs11 }, [ %rd35 + 0 ];
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs12, 0x0;
+	@%p35 ld.global.b16 { %rs12 }, [ %rd36 + 0 ];
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs13, 0x0;
+	@%p35 ld.global.b16 { %rs13 }, [ %rd37 + 0 ];
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs14, 0x0;
+	@%p35 ld.global.b16 { %rs14 }, [ %rd38 + 0 ];
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs15, 0x0;
+	@%p35 ld.global.b16 { %rs15 }, [ %rd39 + 0 ];
+	// end inline asm
+	// begin inline asm
+	mov.u16 %rs16, 0x0;
+	@%p35 ld.global.b16 { %rs16 }, [ %rd40 + 0 ];
+	// end inline asm
+	.loc	1 31 57                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:31:57
+	// begin inline asm
+	mov.u32 %r40, 0x0;
+	@%p35 ld.global.L1::evict_last.b32 { %r40 }, [ %rd8 + 0 ];
+	// end inline asm
+	// begin inline asm
+	mov.u32 %r41, 0x0;
+	@%p35 ld.global.L1::evict_last.b32 { %r41 }, [ %rd8 + 0 ];
+	// end inline asm
+	// begin inline asm
+	mov.u32 %r42, 0x0;
+	@%p35 ld.global.L1::evict_last.b32 { %r42 }, [ %rd8 + 0 ];
+	// end inline asm
+	// begin inline asm
+	mov.u32 %r43, 0x0;
+	@%p35 ld.global.L1::evict_last.b32 { %r43 }, [ %rd8 + 0 ];
+	// end inline asm
+	// begin inline asm
+	mov.u32 %r44, 0x0;
+	@%p35 ld.global.L1::evict_last.b32 { %r44 }, [ %rd8 + 0 ];
+	// end inline asm
+	// begin inline asm
+	mov.u32 %r45, 0x0;
+	@%p35 ld.global.L1::evict_last.b32 { %r45 }, [ %rd8 + 0 ];
+	// end inline asm
+	// begin inline asm
+	mov.u32 %r46, 0x0;
+	@%p35 ld.global.L1::evict_last.b32 { %r46 }, [ %rd8 + 0 ];
+	// end inline asm
+	// begin inline asm
+	mov.u32 %r47, 0x0;
+	@%p35 ld.global.L1::evict_last.b32 { %r47 }, [ %rd8 + 0 ];
+	// end inline asm
+	.loc	1 32 31                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:32:31
+	mul.wide.u32 	%rd88, %r103, 2;
+	add.s64 	%rd49, %rd52, %rd88;
+	.loc	1 32 41                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:32:41
+	// begin inline asm
+	mov.u32 %r48, 0x0;
+	mov.u32 %r49, 0x0;
+	mov.u32 %r50, 0x0;
+	mov.u32 %r51, 0x0;
+	@%p35 ld.global.L1::evict_last.v4.b32 { %r48, %r49, %r50, %r51 }, [ %rd49 + 0 ];
+	// end inline asm
+	.loc	1 45 35                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:45:35
+	shr.u64 	%rd89, %rd17, 46;
+	and.b64  	%rd90, %rd89, 131072;
+	add.s64 	%rd3, %rd90, %rd17;
+	.loc	1 46 38                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:46:38
+	setp.lt.u64 	%p37, %rd3, 131072;
+	.loc	1 46 67                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:46:67
+	or.pred  	%p38, %p36, %p37;
+	@%p38 bra 	$L__BB0_2;
+	bra.uni 	$L__BB0_1;
+$L__BB0_2:                              // %__nv_rsqrtf.exit25
+	.loc	1 0 67                          // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:0:67
+	ld.param.u64 	%rd6, [triton_poi_fused_add_mul_sub_5_param_6];
+	ld.param.u64 	%rd5, [triton_poi_fused_add_mul_sub_5_param_5];
+	ld.param.u64 	%rd4, [triton_poi_fused_add_mul_sub_5_param_4];
+	mov.b32 	%f9, %r28;
+	mov.b32 	%f10, %r29;
+	mov.b32 	%f11, %r30;
+	mov.b32 	%f12, %r31;
+	mov.b32 	%f13, %r32;
+	mov.b32 	%f14, %r33;
+	mov.b32 	%f15, %r34;
+	mov.b32 	%f16, %r35;
+	cvt.s64.s32 	%rd1, %r68;
+	cvt.u64.u32 	%rd2, %r103;
+	mov.f32 	%f17, 0f43000000;
+	div.full.f32 	%f18, %f9, %f17;
+	div.full.f32 	%f19, %f10, %f17;
+	div.full.f32 	%f20, %f11, %f17;
+	div.full.f32 	%f21, %f12, %f17;
+	div.full.f32 	%f22, %f13, %f17;
+	div.full.f32 	%f23, %f14, %f17;
+	div.full.f32 	%f24, %f15, %f17;
+	div.full.f32 	%f25, %f16, %f17;
+	add.f32 	%f26, %f18, 0f358637BD;
+	add.f32 	%f27, %f19, 0f358637BD;
+	add.f32 	%f28, %f20, 0f358637BD;
+	add.f32 	%f29, %f21, 0f358637BD;
+	add.f32 	%f30, %f22, 0f358637BD;
+	add.f32 	%f31, %f23, 0f358637BD;
+	add.f32 	%f32, %f24, 0f358637BD;
+	add.f32 	%f33, %f25, 0f358637BD;
+	rsqrt.approx.ftz.f32 	%f1, %f26;
+	rsqrt.approx.ftz.f32 	%f2, %f27;
+	rsqrt.approx.ftz.f32 	%f3, %f28;
+	rsqrt.approx.ftz.f32 	%f4, %f29;
+	rsqrt.approx.ftz.f32 	%f5, %f30;
+	rsqrt.approx.ftz.f32 	%f6, %f31;
+	rsqrt.approx.ftz.f32 	%f7, %f32;
+	rsqrt.approx.ftz.f32 	%f8, %f33;
+	cvt.u32.u64 	%r121, %rd1;
+	.loc	1 31 57                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:31:57
+	mov.b32 	%f34, %r47;
+	mov.b32 	%f35, %r46;
+	mov.b32 	%f36, %r45;
+	mov.b32 	%f37, %r44;
+	mov.b32 	%f38, %r43;
+	mov.b32 	%f39, %r42;
+	mov.b32 	%f40, %r41;
+	mov.b32 	%f41, %r40;
+	.loc	1 46 67                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:46:67
+	bar.sync 	0;
+	.loc	1 47 31                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:47:31
+	shl.b64 	%rd95, %rd3, 8;
+	add.s64 	%rd96, %rd4, %rd95;
+	shl.b64 	%rd97, %rd1, 1;
+	add.s64 	%rd91, %rd96, %rd97;
+	.loc	1 47 48                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:47:48
+	// begin inline asm
+	mov.u32 %r105, 0x0;
+	mov.u32 %r106, 0x0;
+	mov.u32 %r107, 0x0;
+	mov.u32 %r108, 0x0;
+	@%p35 ld.global.v4.b32 { %r105, %r106, %r107, %r108 }, [ %rd91 + 0 ];
+	// end inline asm
+	.loc	1 50 21                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:50:21
+	div.full.f32 	%f43, %f41, %f17;
+	div.full.f32 	%f44, %f40, %f17;
+	div.full.f32 	%f45, %f39, %f17;
+	div.full.f32 	%f46, %f38, %f17;
+	div.full.f32 	%f47, %f37, %f17;
+	div.full.f32 	%f48, %f36, %f17;
+	div.full.f32 	%f49, %f35, %f17;
+	div.full.f32 	%f50, %f34, %f17;
+	.loc	1 51 20                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:51:20
+	add.f32 	%f51, %f43, 0f358637BD;
+	add.f32 	%f52, %f44, 0f358637BD;
+	add.f32 	%f53, %f45, 0f358637BD;
+	add.f32 	%f54, %f46, 0f358637BD;
+	add.f32 	%f55, %f47, 0f358637BD;
+	add.f32 	%f56, %f48, 0f358637BD;
+	add.f32 	%f57, %f49, 0f358637BD;
+	add.f32 	%f58, %f50, 0f358637BD;
+	.loc	1 52 28                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:52:28
+	rsqrt.approx.ftz.f32 	%f59, %f51;
+	rsqrt.approx.ftz.f32 	%f60, %f52;
+	rsqrt.approx.ftz.f32 	%f61, %f53;
+	rsqrt.approx.ftz.f32 	%f62, %f54;
+	rsqrt.approx.ftz.f32 	%f63, %f55;
+	rsqrt.approx.ftz.f32 	%f64, %f56;
+	rsqrt.approx.ftz.f32 	%f65, %f57;
+	rsqrt.approx.ftz.f32 	%f66, %f58;
+	.loc	1 30 85                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:30:85
+	mov.b32 	%r122, {%rs9, %rs10};
+	mov.b32 	%r123, {%rs11, %rs12};
+	mov.b32 	%r124, {%rs13, %rs14};
+	mov.b32 	%r125, {%rs15, %rs16};
+	.loc	1 56 31                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:56:31
+	shl.b64 	%rd98, %rd2, 1;
+	add.s64 	%rd92, %rd96, %rd98;
+	.loc	1 56 53                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:56:53
+	// begin inline asm
+	mov.u32 %r109, 0x0;
+	mov.u32 %r110, 0x0;
+	mov.u32 %r111, 0x0;
+	mov.u32 %r112, 0x0;
+	@%p35 ld.global.v4.b32 { %r109, %r110, %r111, %r112 }, [ %rd92 + 0 ];
+	// end inline asm
+	.loc	1 62 34                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:62:34
+	shl.b32 	%r126, %r2, 7;
+	.loc	1 62 30                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:62:30
+	add.s32 	%r127, %r126, %r121;
+	.loc	1 62 25                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:62:25
+	mul.wide.s32 	%rd99, %r127, 2;
+	add.s64 	%rd93, %rd5, %rd99;
+	.loc	1 26 64                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:26:64
+	mov.b32 	{%rs17, %rs18}, %r24;
+	cvt.f32.bf16 	%f67, %rs18;
+	cvt.f32.bf16 	%f68, %rs17;
+	.loc	1 39 18                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:39:18
+	mul.f32 	%f69, %f1, %f68;
+	mul.f32 	%f70, %f2, %f67;
+	.loc	1 28 76                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:28:76
+	mov.b32 	{%rs19, %rs20}, %r36;
+	cvt.f32.bf16 	%f71, %rs19;
+	cvt.f32.bf16 	%f72, %rs20;
+	.loc	1 41 19                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:41:19
+	mul.f32 	%f73, %f70, %f72;
+	mul.f32 	%f74, %f69, %f71;
+	.loc	1 47 58                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:47:58
+	mov.b32 	{%rs21, %rs22}, %r105;
+	cvt.f32.bf16 	%f75, %rs22;
+	cvt.f32.bf16 	%f76, %rs21;
+	.loc	1 30 95                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:30:95
+	mov.b32 	{%rs23, %rs24}, %r122;
+	cvt.f32.bf16 	%f77, %rs23;
+	cvt.f32.bf16 	%f78, %rs24;
+	.loc	1 32 81                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:32:81
+	mov.b32 	{%rs25, %rs26}, %r48;
+	cvt.f32.bf16 	%f79, %rs26;
+	cvt.f32.bf16 	%f80, %rs25;
+	.loc	1 53 20                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:53:20
+	mul.f32 	%f81, %f60, %f78;
+	mul.f32 	%f82, %f59, %f77;
+	.loc	1 55 20                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:55:20
+	mul.f32 	%f83, %f82, %f80;
+	mul.f32 	%f84, %f81, %f79;
+	.loc	1 56 63                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:56:63
+	mov.b32 	{%rs27, %rs28}, %r109;
+	cvt.f32.bf16 	%f85, %rs27;
+	cvt.f32.bf16 	%f86, %rs28;
+	.loc	1 57 20                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:57:20
+	mul.f32 	%f87, %f84, %f86;
+	mul.f32 	%f88, %f83, %f85;
+	.loc	1 58 20                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:58:20
+	neg.f32 	%f89, %f88;
+	fma.rn.f32 	%f90, %f74, %f76, %f89;
+	neg.f32 	%f91, %f87;
+	fma.rn.f32 	%f92, %f73, %f75, %f91;
+	.loc	1 62 46                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:62:46
+	cvt.rn.bf16x2.f32 	%r113, %f92, %f90;
+	.loc	1 26 64                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:26:64
+	mov.b32 	{%rs29, %rs30}, %r25;
+	cvt.f32.bf16 	%f93, %rs30;
+	cvt.f32.bf16 	%f94, %rs29;
+	.loc	1 39 18                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:39:18
+	mul.f32 	%f95, %f3, %f94;
+	mul.f32 	%f96, %f4, %f93;
+	.loc	1 28 76                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:28:76
+	mov.b32 	{%rs31, %rs32}, %r37;
+	cvt.f32.bf16 	%f97, %rs31;
+	cvt.f32.bf16 	%f98, %rs32;
+	.loc	1 41 19                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:41:19
+	mul.f32 	%f99, %f96, %f98;
+	mul.f32 	%f100, %f95, %f97;
+	.loc	1 47 58                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:47:58
+	mov.b32 	{%rs33, %rs34}, %r106;
+	cvt.f32.bf16 	%f101, %rs34;
+	cvt.f32.bf16 	%f102, %rs33;
+	.loc	1 30 95                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:30:95
+	mov.b32 	{%rs35, %rs36}, %r123;
+	cvt.f32.bf16 	%f103, %rs35;
+	cvt.f32.bf16 	%f104, %rs36;
+	.loc	1 32 81                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:32:81
+	mov.b32 	{%rs37, %rs38}, %r49;
+	cvt.f32.bf16 	%f105, %rs38;
+	cvt.f32.bf16 	%f106, %rs37;
+	.loc	1 53 20                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:53:20
+	mul.f32 	%f107, %f62, %f104;
+	mul.f32 	%f108, %f61, %f103;
+	.loc	1 55 20                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:55:20
+	mul.f32 	%f109, %f108, %f106;
+	mul.f32 	%f110, %f107, %f105;
+	.loc	1 56 63                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:56:63
+	mov.b32 	{%rs39, %rs40}, %r110;
+	cvt.f32.bf16 	%f111, %rs39;
+	cvt.f32.bf16 	%f112, %rs40;
+	.loc	1 57 20                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:57:20
+	mul.f32 	%f113, %f110, %f112;
+	mul.f32 	%f114, %f109, %f111;
+	.loc	1 58 20                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:58:20
+	neg.f32 	%f115, %f114;
+	fma.rn.f32 	%f116, %f100, %f102, %f115;
+	neg.f32 	%f117, %f113;
+	fma.rn.f32 	%f118, %f99, %f101, %f117;
+	.loc	1 62 46                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:62:46
+	cvt.rn.bf16x2.f32 	%r114, %f118, %f116;
+	.loc	1 26 64                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:26:64
+	mov.b32 	{%rs41, %rs42}, %r26;
+	cvt.f32.bf16 	%f119, %rs42;
+	cvt.f32.bf16 	%f120, %rs41;
+	.loc	1 39 18                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:39:18
+	mul.f32 	%f121, %f5, %f120;
+	mul.f32 	%f122, %f6, %f119;
+	.loc	1 28 76                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:28:76
+	mov.b32 	{%rs43, %rs44}, %r38;
+	cvt.f32.bf16 	%f123, %rs43;
+	cvt.f32.bf16 	%f124, %rs44;
+	.loc	1 41 19                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:41:19
+	mul.f32 	%f125, %f122, %f124;
+	mul.f32 	%f126, %f121, %f123;
+	.loc	1 47 58                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:47:58
+	mov.b32 	{%rs45, %rs46}, %r107;
+	cvt.f32.bf16 	%f127, %rs46;
+	cvt.f32.bf16 	%f128, %rs45;
+	.loc	1 30 95                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:30:95
+	mov.b32 	{%rs47, %rs48}, %r124;
+	cvt.f32.bf16 	%f129, %rs47;
+	cvt.f32.bf16 	%f130, %rs48;
+	.loc	1 32 81                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:32:81
+	mov.b32 	{%rs49, %rs50}, %r50;
+	cvt.f32.bf16 	%f131, %rs50;
+	cvt.f32.bf16 	%f132, %rs49;
+	.loc	1 53 20                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:53:20
+	mul.f32 	%f133, %f64, %f130;
+	mul.f32 	%f134, %f63, %f129;
+	.loc	1 55 20                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:55:20
+	mul.f32 	%f135, %f134, %f132;
+	mul.f32 	%f136, %f133, %f131;
+	.loc	1 56 63                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:56:63
+	mov.b32 	{%rs51, %rs52}, %r111;
+	cvt.f32.bf16 	%f137, %rs51;
+	cvt.f32.bf16 	%f138, %rs52;
+	.loc	1 57 20                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:57:20
+	mul.f32 	%f139, %f136, %f138;
+	mul.f32 	%f140, %f135, %f137;
+	.loc	1 58 20                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:58:20
+	neg.f32 	%f141, %f140;
+	fma.rn.f32 	%f142, %f126, %f128, %f141;
+	neg.f32 	%f143, %f139;
+	fma.rn.f32 	%f144, %f125, %f127, %f143;
+	.loc	1 62 46                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:62:46
+	cvt.rn.bf16x2.f32 	%r115, %f144, %f142;
+	.loc	1 26 64                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:26:64
+	mov.b32 	{%rs53, %rs54}, %r27;
+	cvt.f32.bf16 	%f145, %rs54;
+	cvt.f32.bf16 	%f146, %rs53;
+	.loc	1 39 18                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:39:18
+	mul.f32 	%f147, %f7, %f146;
+	mul.f32 	%f148, %f8, %f145;
+	.loc	1 28 76                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:28:76
+	mov.b32 	{%rs55, %rs56}, %r39;
+	cvt.f32.bf16 	%f149, %rs55;
+	cvt.f32.bf16 	%f150, %rs56;
+	.loc	1 41 19                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:41:19
+	mul.f32 	%f151, %f148, %f150;
+	mul.f32 	%f152, %f147, %f149;
+	.loc	1 47 58                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:47:58
+	mov.b32 	{%rs57, %rs58}, %r108;
+	cvt.f32.bf16 	%f153, %rs58;
+	cvt.f32.bf16 	%f154, %rs57;
+	.loc	1 30 95                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:30:95
+	mov.b32 	{%rs59, %rs60}, %r125;
+	cvt.f32.bf16 	%f155, %rs59;
+	cvt.f32.bf16 	%f156, %rs60;
+	.loc	1 32 81                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:32:81
+	mov.b32 	{%rs61, %rs62}, %r51;
+	cvt.f32.bf16 	%f157, %rs62;
+	cvt.f32.bf16 	%f158, %rs61;
+	.loc	1 53 20                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:53:20
+	mul.f32 	%f159, %f66, %f156;
+	mul.f32 	%f160, %f65, %f155;
+	.loc	1 55 20                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:55:20
+	mul.f32 	%f161, %f160, %f158;
+	mul.f32 	%f162, %f159, %f157;
+	.loc	1 56 63                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:56:63
+	mov.b32 	{%rs63, %rs64}, %r112;
+	cvt.f32.bf16 	%f163, %rs63;
+	cvt.f32.bf16 	%f164, %rs64;
+	.loc	1 57 20                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:57:20
+	mul.f32 	%f165, %f162, %f164;
+	mul.f32 	%f166, %f161, %f163;
+	.loc	1 58 20                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:58:20
+	neg.f32 	%f167, %f166;
+	fma.rn.f32 	%f168, %f152, %f154, %f167;
+	neg.f32 	%f169, %f165;
+	fma.rn.f32 	%f170, %f151, %f153, %f169;
+	.loc	1 62 46                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:62:46
+	cvt.rn.bf16x2.f32 	%r116, %f170, %f168;
+	// begin inline asm
+	@%p35 st.global.v4.b32 [ %rd93 + 0 ], { %r113, %r114, %r115, %r116 };
+	// end inline asm
+	.loc	1 63 25                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:63:25
+	add.s64 	%rd94, %rd6, %rd99;
+	.loc	1 60 20                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:60:20
+	mul.f32 	%f171, %f73, %f86;
+	mul.f32 	%f172, %f74, %f85;
+	.loc	1 61 20                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:61:20
+	fma.rn.f32 	%f173, %f83, %f76, %f172;
+	fma.rn.f32 	%f174, %f84, %f75, %f171;
+	.loc	1 63 46                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:63:46
+	cvt.rn.bf16x2.f32 	%r117, %f174, %f173;
+	.loc	1 60 20                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:60:20
+	mul.f32 	%f175, %f99, %f112;
+	mul.f32 	%f176, %f100, %f111;
+	.loc	1 61 20                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:61:20
+	fma.rn.f32 	%f177, %f109, %f102, %f176;
+	fma.rn.f32 	%f178, %f110, %f101, %f175;
+	.loc	1 63 46                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:63:46
+	cvt.rn.bf16x2.f32 	%r118, %f178, %f177;
+	.loc	1 60 20                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:60:20
+	mul.f32 	%f179, %f125, %f138;
+	mul.f32 	%f180, %f126, %f137;
+	.loc	1 61 20                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:61:20
+	fma.rn.f32 	%f181, %f135, %f128, %f180;
+	fma.rn.f32 	%f182, %f136, %f127, %f179;
+	.loc	1 63 46                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:63:46
+	cvt.rn.bf16x2.f32 	%r119, %f182, %f181;
+	.loc	1 60 20                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:60:20
+	mul.f32 	%f183, %f151, %f164;
+	mul.f32 	%f184, %f152, %f163;
+	.loc	1 61 20                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:61:20
+	fma.rn.f32 	%f185, %f161, %f154, %f184;
+	fma.rn.f32 	%f186, %f162, %f153, %f183;
+	.loc	1 63 46                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:63:46
+	cvt.rn.bf16x2.f32 	%r120, %f186, %f185;
+	// begin inline asm
+	@%p35 st.global.v4.b32 [ %rd94 + 0 ], { %r117, %r118, %r119, %r120 };
+	// end inline asm
+	.loc	1 63 4                          // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:63:4
+	ret;
+$L__BB0_1:
+	.loc	1 46 67                         // cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py:46:67
+	mov.u64 	%rd100, assertMessage_0;
+	cvta.global.u64 	%rd101, %rd100;
+	mov.u64 	%rd102, assertFile_0;
+	cvta.global.u64 	%rd103, %rd102;
+	mov.u64 	%rd104, assertFunc_0;
+	cvta.global.u64 	%rd105, %rd104;
+	{ // callseq 5, 0
+	.param .b64 param0;
+	st.param.b64 	[param0], %rd101;
+	.param .b64 param1;
+	st.param.b64 	[param1], %rd103;
+	.param .b32 param2;
+	st.param.b32 	[param2], 46;
+	.param .b64 param3;
+	st.param.b64 	[param3], %rd105;
+	.param .b64 param4;
+	st.param.b64 	[param4], 1;
+	call.uni 
+	__assertfail, 
+	(
+	param0, 
+	param1, 
+	param2, 
+	param3, 
+	param4
+	);
+	} // callseq 5
+	trap;
+$L__tmp1:
+$L__func_end0:
+                                        // -- End function
+}
+	.file	1 "/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qa/cqacf27gnb4cq4mxrxnso5befca6em7x55qklndfih37o2jzisxn.py"
+	.section	.debug_abbrev
+	{
+.b8 1                                   // Abbreviation Code
+.b8 17                                  // DW_TAG_compile_unit
+.b8 0                                   // DW_CHILDREN_no
+.b8 37                                  // DW_AT_producer
+.b8 8                                   // DW_FORM_string
+.b8 19                                  // DW_AT_language
+.b8 5                                   // DW_FORM_data2
+.b8 3                                   // DW_AT_name
+.b8 8                                   // DW_FORM_string
+.b8 16                                  // DW_AT_stmt_list
+.b8 6                                   // DW_FORM_data4
+.b8 27                                  // DW_AT_comp_dir
+.b8 8                                   // DW_FORM_string
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 0                                   // EOM(3)
+	}
+	.section	.debug_info
+	{
+.b32 155                                // Length of Unit
+.b8 2                                   // DWARF version number
+.b8 0
+.b32 .debug_abbrev                      // Offset Into Abbrev. Section
+.b8 8                                   // Address Size (in bytes)
+.b8 1                                   // Abbrev [1] 0xb:0x94 DW_TAG_compile_unit
+.b8 116                                 // DW_AT_producer
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 0
+.b8 2                                   // DW_AT_language
+.b8 0
+.b8 99                                  // DW_AT_name
+.b8 113
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+.b8 50
+.b8 55
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+.b8 105
+.b8 115
+.b8 120
+.b8 110
+.b8 46
+.b8 112
+.b8 121
+.b8 0
+.b32 .debug_line                        // DW_AT_stmt_list
+.b8 47                                  // DW_AT_comp_dir
+.b8 104
+.b8 111
+.b8 109
+.b8 101
+.b8 47
+.b8 120
+.b8 47
+.b8 46
+.b8 99
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+.b8 50
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+.b8 56
+.b8 102
+.b8 97
+.b8 49
+.b8 47
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+.b8 110
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+.b8 95
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+.b8 95
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+.b8 95
+.b8 99
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+.b8 99
+.b8 104
+.b8 101
+.b8 47
+.b8 113
+.b8 97
+.b8 0
+	}
+	.section	.debug_macinfo	{	}

platform/aiml/models/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/5QNFXQK6JWP7PWHCIPTXVA6ULATWO2SJ2G2H5LOACBZ3J7ASQHDA/triton_red_fused__to_copy_mean_pow_4.llir

@@ -0,0 +1,143 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+target datalayout = "e-p3:32:32-p4:32:32-p5:32:32-p6:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64"
+
+@global_smem = external addrspace(3) global [0 x i8], align 16
+
+define ptx_kernel void @triton_red_fused__to_copy_mean_pow_4(ptr addrspace(1) %0, ptr addrspace(1) %1, i32 %2, i32 %3, ptr addrspace(1) readnone captures(none) %4) local_unnamed_addr !dbg !6 {
+  %6 = tail call i32 @llvm.nvvm.read.ptx.sreg.ctaid.x(), !dbg !9
+  %7 = shl i32 %6, 3, !dbg !10
+  %8 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !11
+  %9 = lshr i32 %8, 5, !dbg !11
+  %10 = and i32 %9, 7, !dbg !11
+  %11 = and i32 %8, 7, !dbg !11
+  %12 = or disjoint i32 %10, %7, !dbg !12
+  %13 = or disjoint i32 %7, %11, !dbg !12
+  %14 = icmp slt i32 %12, %2, !dbg !13
+  %15 = icmp slt i32 %13, %2, !dbg !13
+  %16 = shl i32 %8, 2, !dbg !14
+  %17 = and i32 %16, 124, !dbg !14
+  %18 = sdiv i32 %12, 8, !dbg !15
+  %19 = mul i32 %18, 8, !dbg !16
+  %.decomposed = sub i32 %12, %19, !dbg !16
+  %20 = or disjoint i32 %17, 5120, !dbg !17
+  %21 = shl nsw i32 %.decomposed, 7, !dbg !18
+  %22 = add nsw i32 %20, %21, !dbg !19
+  %23 = mul i32 %18, 7168, !dbg !20
+  %24 = add i32 %22, %23, !dbg !21
+  %25 = sext i32 %24 to i64, !dbg !22
+  %26 = getelementptr bfloat, ptr addrspace(1) %0, i64 %25, !dbg !22
+  %27 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, $2;\0A\09mov.u32 $1, $3;\0A\09@$5 ld.global.L1::evict_first.v2.b32 { $0, $1 }, [ $4 + 0 ];", "=r,=r,r,r,l,b"(i32 0, i32 0, ptr addrspace(1) %26, i1 %14) #3, !dbg !23
+  %28 = extractvalue { i32, i32 } %27, 0, !dbg !23
+  %29 = bitcast i32 %28 to <2 x bfloat>, !dbg !23
+  %30 = extractvalue { i32, i32 } %27, 1, !dbg !23
+  %31 = bitcast i32 %30 to <2 x bfloat>, !dbg !23
+  %32 = extractelement <2 x bfloat> %29, i64 0, !dbg !23
+  %33 = extractelement <2 x bfloat> %29, i64 1, !dbg !23
+  %34 = extractelement <2 x bfloat> %31, i64 0, !dbg !23
+  %35 = extractelement <2 x bfloat> %31, i64 1, !dbg !23
+  %36 = fpext bfloat %32 to float, !dbg !24
+  %37 = fpext bfloat %33 to float, !dbg !24
+  %38 = fpext bfloat %34 to float, !dbg !24
+  %39 = fpext bfloat %35 to float, !dbg !24
+  %40 = fmul float %36, %36, !dbg !25
+  %41 = fmul float %37, %37, !dbg !25
+  %42 = fmul float %38, %38, !dbg !25
+  %43 = fmul float %39, %39, !dbg !25
+  %44 = fadd float %40, %41, !dbg !26
+  %45 = fadd float %42, %44, !dbg !26
+  %46 = fadd float %43, %45, !dbg !26
+  %47 = select i1 %14, float %46, float 0.000000e+00, !dbg !26
+  %48 = bitcast float %47 to i32, !dbg !31
+  %49 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %48, i32 16, i32 31), !dbg !31
+  %50 = bitcast i32 %49 to float, !dbg !31
+  %51 = fadd float %47, %50, !dbg !26
+  %52 = bitcast float %51 to i32, !dbg !31
+  %53 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %52, i32 8, i32 31), !dbg !31
+  %54 = bitcast i32 %53 to float, !dbg !31
+  %55 = fadd float %51, %54, !dbg !26
+  %56 = bitcast float %55 to i32, !dbg !31
+  %57 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %56, i32 4, i32 31), !dbg !31
+  %58 = bitcast i32 %57 to float, !dbg !31
+  %59 = fadd float %55, %58, !dbg !26
+  %60 = bitcast float %59 to i32, !dbg !31
+  %61 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %60, i32 2, i32 31), !dbg !31
+  %62 = bitcast i32 %61 to float, !dbg !31
+  %63 = fadd float %59, %62, !dbg !26
+  %64 = bitcast float %63 to i32, !dbg !31
+  %65 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %64, i32 1, i32 31), !dbg !31
+  %66 = bitcast i32 %65 to float, !dbg !31
+  %67 = fadd float %63, %66, !dbg !26
+  %68 = getelementptr inbounds nuw float, ptr addrspace(3) @global_smem, i32 %10, !dbg !32
+  %69 = bitcast float %67 to <1 x i32>, !dbg !32
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %68, <1 x i32> %69, i1 true) #3, !dbg !32
+  tail call void @llvm.nvvm.barrier0(), !dbg !32
+  %70 = getelementptr inbounds nuw float, ptr addrspace(3) @global_smem, i32 %11, !dbg !32
+  %71 = load i32, ptr addrspace(3) %70, align 4, !dbg !32
+  %72 = sext i32 %13 to i64, !dbg !33
+  %73 = getelementptr float, ptr addrspace(1) %1, i64 %72, !dbg !33
+  %74 = and i32 %8, 248, !dbg !34
+  %75 = icmp eq i32 %74, 0, !dbg !34
+  %76 = and i1 %75, %15, !dbg !34
+  tail call void asm sideeffect "@$2 st.global.b32 [ $1 + 0 ], { $0 };", "r,l,b"(i32 %71, ptr addrspace(1) %73, i1 %76) #3, !dbg !34
+  ret void, !dbg !35
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.ctaid.x() #0
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.x() #0
+
+; Function Attrs: convergent nocallback nounwind memory(inaccessiblemem: readwrite)
+declare i32 @llvm.nvvm.shfl.sync.bfly.i32(i32, i32, i32, i32) #1
+
+; Function Attrs: convergent nocallback nounwind
+declare void @llvm.nvvm.barrier0() #2
+
+attributes #0 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #1 = { convergent nocallback nounwind memory(inaccessiblemem: readwrite) }
+attributes #2 = { convergent nocallback nounwind }
+attributes #3 = { nounwind }
+
+!llvm.module.flags = !{!0, !1}
+!llvm.dbg.cu = !{!2}
+!nvvm.annotations = !{!4}
+!llvm.ident = !{!5}
+
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = !{i32 4, !"nvvm-reflect-ftz", i32 1}
+!2 = distinct !DICompileUnit(language: DW_LANG_C, file: !3, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: LineTablesOnly)
+!3 = !DIFile(filename: "cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py", directory: "/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qv")
+!4 = !{ptr @triton_red_fused__to_copy_mean_pow_4, !"reqntidx", i32 256}
+!5 = !{!"clang version 3.8.0 (tags/RELEASE_380/final)"}
+!6 = distinct !DISubprogram(name: "triton_red_fused__to_copy_mean_pow_4", linkageName: "triton_red_fused__to_copy_mean_pow_4", scope: !3, file: !3, line: 18, type: !7, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !2)
+!7 = !DISubroutineType(cc: DW_CC_normal, types: !8)
+!8 = !{}
+!9 = !DILocation(line: 22, column: 28, scope: !6)
+!10 = !DILocation(line: 22, column: 33, scope: !6)
+!11 = !DILocation(line: 23, column: 44, scope: !6)
+!12 = !DILocation(line: 23, column: 23, scope: !6)
+!13 = !DILocation(line: 24, column: 21, scope: !6)
+!14 = !DILocation(line: 25, column: 37, scope: !6)
+!15 = !DILocation(line: 28, column: 19, scope: !6)
+!16 = !DILocation(line: 27, column: 19, scope: !6)
+!17 = !DILocation(line: 37, column: 41, scope: !6)
+!18 = !DILocation(line: 37, column: 52, scope: !6)
+!19 = !DILocation(line: 37, column: 48, scope: !6)
+!20 = !DILocation(line: 37, column: 62, scope: !6)
+!21 = !DILocation(line: 37, column: 57, scope: !6)
+!22 = !DILocation(line: 37, column: 34, scope: !6)
+!23 = !DILocation(line: 37, column: 67, scope: !6)
+!24 = !DILocation(line: 37, column: 129, scope: !6)
+!25 = !DILocation(line: 39, column: 22, scope: !6)
+!26 = !DILocation(line: 256, column: 15, scope: !27, inlinedAt: !30)
+!27 = distinct !DILexicalBlockFile(scope: !29, file: !28, discriminator: 0)
+!28 = !DIFile(filename: "standard.py", directory: "/home/x/hfenv/lib/python3.12/site-packages/triton/language")
+!29 = distinct !DILexicalBlockFile(scope: !6, file: !28, discriminator: 0)
+!30 = !DILocation(line: 43, column: 25, scope: !6)
+!31 = !DILocation(line: 286, column: 36, scope: !29, inlinedAt: !30)
+!32 = !DILocation(line: 43, column: 28, scope: !6)
+!33 = !DILocation(line: 44, column: 25, scope: !6)
+!34 = !DILocation(line: 44, column: 36, scope: !6)
+!35 = !DILocation(line: 44, column: 4, scope: !6)

platform/aiml/models/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/6YBPZASPL7DBRURP7Z652K7LIYFEK5ZSHXU4QZLBY5E3KMX3NZ4A/__grp__triton_red_fused__to_copy_mean_pow_4.json

@@ -0,0 +1 @@
+{"child_paths": {"triton_red_fused__to_copy_mean_pow_4.ttir": "/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/6YBPZASPL7DBRURP7Z652K7LIYFEK5ZSHXU4QZLBY5E3KMX3NZ4A/triton_red_fused__to_copy_mean_pow_4.ttir", "triton_red_fused__to_copy_mean_pow_4.ttgir": "/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/6YBPZASPL7DBRURP7Z652K7LIYFEK5ZSHXU4QZLBY5E3KMX3NZ4A/triton_red_fused__to_copy_mean_pow_4.ttgir", "triton_red_fused__to_copy_mean_pow_4.llir": "/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/6YBPZASPL7DBRURP7Z652K7LIYFEK5ZSHXU4QZLBY5E3KMX3NZ4A/triton_red_fused__to_copy_mean_pow_4.llir", "triton_red_fused__to_copy_mean_pow_4.ptx": "/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/6YBPZASPL7DBRURP7Z652K7LIYFEK5ZSHXU4QZLBY5E3KMX3NZ4A/triton_red_fused__to_copy_mean_pow_4.ptx", "triton_red_fused__to_copy_mean_pow_4.cubin": "/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/6YBPZASPL7DBRURP7Z652K7LIYFEK5ZSHXU4QZLBY5E3KMX3NZ4A/triton_red_fused__to_copy_mean_pow_4.cubin", "triton_red_fused__to_copy_mean_pow_4.json": "/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/6YBPZASPL7DBRURP7Z652K7LIYFEK5ZSHXU4QZLBY5E3KMX3NZ4A/triton_red_fused__to_copy_mean_pow_4.json"}}

platform/aiml/models/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/6YBPZASPL7DBRURP7Z652K7LIYFEK5ZSHXU4QZLBY5E3KMX3NZ4A/triton_red_fused__to_copy_mean_pow_4.ptx

@@ -0,0 +1,421 @@
+//
+// Generated by LLVM NVPTX Back-End
+//
+
+.version 8.4
+.target sm_90a
+.address_size 64
+
+	// .globl	triton_red_fused__to_copy_mean_pow_4 // -- Begin function triton_red_fused__to_copy_mean_pow_4
+.extern .shared .align 16 .b8 global_smem[];
+                                        // @triton_red_fused__to_copy_mean_pow_4
+.visible .entry triton_red_fused__to_copy_mean_pow_4(
+	.param .u64 .ptr .global .align 1 triton_red_fused__to_copy_mean_pow_4_param_0,
+	.param .u64 .ptr .global .align 1 triton_red_fused__to_copy_mean_pow_4_param_1,
+	.param .u32 triton_red_fused__to_copy_mean_pow_4_param_2,
+	.param .u32 triton_red_fused__to_copy_mean_pow_4_param_3,
+	.param .u64 .ptr .global .align 1 triton_red_fused__to_copy_mean_pow_4_param_4
+)
+.reqntid 64, 1, 1
+{
+	.reg .pred 	%p<9>;
+	.reg .b16 	%rs<3>;
+	.reg .b32 	%r<43>;
+	.reg .f32 	%f<19>;
+	.reg .b64 	%rd<7>;
+	.loc	1 18 0                          // cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py:18:0
+$L__func_begin0:
+	.loc	1 18 0                          // cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py:18:0
+
+// %bb.0:
+	ld.param.u64 	%rd3, [triton_red_fused__to_copy_mean_pow_4_param_0];
+	ld.param.u64 	%rd4, [triton_red_fused__to_copy_mean_pow_4_param_1];
+$L__tmp0:
+	.loc	1 22 28                         // cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py:22:28
+	mov.u32 	%r10, %ctaid.x;
+	ld.param.u32 	%r11, [triton_red_fused__to_copy_mean_pow_4_param_2];
+	.loc	1 24 21                         // cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py:24:21
+	setp.lt.s32 	%p1, %r10, %r11;
+	.loc	1 25 37                         // cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py:25:37
+	mov.u32 	%r12, %tid.x;
+	and.b32  	%r13, %r12, 31;
+	shl.b32 	%r14, %r12, 1;
+	and.b32  	%r15, %r14, 126;
+	.loc	1 28 19                         // cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py:28:19
+	shr.s32 	%r16, %r10, 31;
+	shr.u32 	%r17, %r16, 29;
+	add.s32 	%r18, %r10, %r17;
+	shr.u32 	%r19, %r18, 3;
+	.loc	1 27 19                         // cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py:27:19
+	and.b32  	%r20, %r18, 33554424;
+	sub.s32 	%r21, %r10, %r20;
+	.loc	1 37 52                         // cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py:37:52
+	shl.b32 	%r22, %r21, 7;
+	.loc	1 37 48                         // cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py:37:48
+	or.b32  	%r23, %r22, %r15;
+	mad.lo.s32 	%r24, %r19, 7168, %r23;
+	.loc	1 37 57                         // cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py:37:57
+	add.s32 	%r25, %r24, 5120;
+	.loc	1 37 34                         // cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py:37:34
+	mul.wide.s32 	%rd5, %r25, 2;
+	add.s64 	%rd1, %rd3, %rd5;
+	mov.b32 	%r2, 0;
+	.loc	1 37 67                         // cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py:37:67
+	// begin inline asm
+	mov.u32 %r1, %r2;
+	@%p1 ld.global.L1::evict_first.b32 { %r1 }, [ %rd1 + 0 ];
+	// end inline asm
+	mov.b32 	{%rs1, %rs2}, %r1;
+	.loc	1 37 129                        // cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py:37:129
+	cvt.f32.bf16 	%f1, %rs1;
+	cvt.f32.bf16 	%f2, %rs2;
+	.loc	1 39 22                         // cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py:39:22
+	mul.f32 	%f3, %f2, %f2;
+$L__tmp1:
+	.loc	2 256 15                        // standard.py:256:15
+	fma.rn.f32 	%f4, %f1, %f1, %f3;
+	selp.f32 	%f5, %f4, 0f00000000, %p1;
+	.loc	2 286 36                        // standard.py:286:36
+	mov.b32 	%r26, %f5;
+	shfl.sync.bfly.b32	%r27, %r26, 16, 31, -1;
+	mov.b32 	%f6, %r27;
+	.loc	2 256 15                        // standard.py:256:15
+	add.f32 	%f7, %f5, %f6;
+	.loc	2 286 36                        // standard.py:286:36
+	mov.b32 	%r28, %f7;
+	shfl.sync.bfly.b32	%r29, %r28, 8, 31, -1;
+	mov.b32 	%f8, %r29;
+	.loc	2 256 15                        // standard.py:256:15
+	add.f32 	%f9, %f7, %f8;
+	.loc	2 286 36                        // standard.py:286:36
+	mov.b32 	%r30, %f9;
+	shfl.sync.bfly.b32	%r31, %r30, 4, 31, -1;
+	mov.b32 	%f10, %r31;
+	.loc	2 256 15                        // standard.py:256:15
+	add.f32 	%f11, %f9, %f10;
+	.loc	2 286 36                        // standard.py:286:36
+	mov.b32 	%r32, %f11;
+	shfl.sync.bfly.b32	%r33, %r32, 2, 31, -1;
+	mov.b32 	%f12, %r33;
+	.loc	2 256 15                        // standard.py:256:15
+	add.f32 	%f13, %f11, %f12;
+	.loc	2 286 36                        // standard.py:286:36
+	mov.b32 	%r34, %f13;
+	shfl.sync.bfly.b32	%r35, %r34, 1, 31, -1;
+	mov.b32 	%f14, %r35;
+	.loc	2 256 15                        // standard.py:256:15
+	add.f32 	%f15, %f13, %f14;
+	.loc	2 286 36                        // standard.py:286:36
+	setp.eq.s32 	%p2, %r13, 0;
+	shr.u32 	%r36, %r12, 3;
+	and.b32  	%r37, %r36, 4;
+	mov.u32 	%r38, global_smem;
+	add.s32 	%r3, %r38, %r37;
+	mov.b32 	%r4, %f15;
+	// begin inline asm
+	@%p2 st.shared.b32 [ %r3 + 0 ], %r4;
+	// end inline asm
+	bar.sync 	0;
+	setp.lt.s32 	%p3, %r12, 2;
+	shl.b32 	%r39, %r12, 2;
+	add.s32 	%r6, %r38, %r39;
+	// begin inline asm
+	@%p3 ld.shared.b32 %r5, [ %r6 + 0 ];
+	// end inline asm
+	mov.b32 	%f16, %r5;
+	shfl.sync.bfly.b32	%r40, %r5, 1, 31, -1;
+	mov.b32 	%f17, %r40;
+	.loc	2 256 15                        // standard.py:256:15
+	add.f32 	%f18, %f16, %f17;
+	.loc	2 286 36                        // standard.py:286:36
+	and.b32  	%r41, %r12, 1;
+	setp.eq.b32 	%p6, %r41, 1;
+	not.pred 	%p7, %p6;
+	and.pred  	%p4, %p3, %p7;
+	mov.b32 	%r8, %f18;
+	// begin inline asm
+	@%p4 st.shared.b32 [ %r6 + 0 ], %r8;
+	// end inline asm
+	bar.sync 	0;
+	ld.shared.u32 	%r9, [global_smem];
+$L__tmp2:
+	.loc	1 44 25                         // cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py:44:25
+	mul.wide.s32 	%rd6, %r10, 4;
+	add.s64 	%rd2, %rd4, %rd6;
+	.loc	1 44 36                         // cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py:44:36
+	and.b32  	%r42, %r12, 63;
+	setp.eq.s32 	%p8, %r42, 0;
+	and.pred  	%p5, %p8, %p1;
+	// begin inline asm
+	@%p5 st.global.b32 [ %rd2 + 0 ], { %r9 };
+	// end inline asm
+	.loc	1 44 4                          // cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py:44:4
+	ret;
+$L__tmp3:
+$L__func_end0:
+                                        // -- End function
+}
+	.file	1 "/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qv/cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py"
+	.file	2 "/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py"
+	.section	.debug_abbrev
+	{
+.b8 1                                   // Abbreviation Code
+.b8 17                                  // DW_TAG_compile_unit
+.b8 1                                   // DW_CHILDREN_yes
+.b8 37                                  // DW_AT_producer
+.b8 8                                   // DW_FORM_string
+.b8 19                                  // DW_AT_language
+.b8 5                                   // DW_FORM_data2
+.b8 3                                   // DW_AT_name
+.b8 8                                   // DW_FORM_string
+.b8 16                                  // DW_AT_stmt_list
+.b8 6                                   // DW_FORM_data4
+.b8 27                                  // DW_AT_comp_dir
+.b8 8                                   // DW_FORM_string
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 2                                   // Abbreviation Code
+.b8 46                                  // DW_TAG_subprogram
+.b8 0                                   // DW_CHILDREN_no
+.b8 3                                   // DW_AT_name
+.b8 8                                   // DW_FORM_string
+.b8 32                                  // DW_AT_inline
+.b8 11                                  // DW_FORM_data1
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 3                                   // Abbreviation Code
+.b8 46                                  // DW_TAG_subprogram
+.b8 1                                   // DW_CHILDREN_yes
+.b8 17                                  // DW_AT_low_pc
+.b8 1                                   // DW_FORM_addr
+.b8 18                                  // DW_AT_high_pc
+.b8 1                                   // DW_FORM_addr
+.b8 49                                  // DW_AT_abstract_origin
+.b8 19                                  // DW_FORM_ref4
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 4                                   // Abbreviation Code
+.b8 29                                  // DW_TAG_inlined_subroutine
+.b8 0                                   // DW_CHILDREN_no
+.b8 49                                  // DW_AT_abstract_origin
+.b8 19                                  // DW_FORM_ref4
+.b8 17                                  // DW_AT_low_pc
+.b8 1                                   // DW_FORM_addr
+.b8 18                                  // DW_AT_high_pc
+.b8 1                                   // DW_FORM_addr
+.b8 88                                  // DW_AT_call_file
+.b8 11                                  // DW_FORM_data1
+.b8 89                                  // DW_AT_call_line
+.b8 11                                  // DW_FORM_data1
+.b8 87                                  // DW_AT_call_column
+.b8 11                                  // DW_FORM_data1
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 0                                   // EOM(3)
+	}
+	.section	.debug_info
+	{
+.b32 241                                // Length of Unit
+.b8 2                                   // DWARF version number
+.b8 0
+.b32 .debug_abbrev                      // Offset Into Abbrev. Section
+.b8 8                                   // Address Size (in bytes)
+.b8 1                                   // Abbrev [1] 0xb:0xea DW_TAG_compile_unit
+.b8 116                                 // DW_AT_producer
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 0
+.b8 2                                   // DW_AT_language
+.b8 0
+.b8 99                                  // DW_AT_name
+.b8 113
+.b8 118
+.b8 99
+.b8 106
+.b8 106
+.b8 121
+.b8 118
+.b8 107
+.b8 107
+.b8 108
+.b8 97
+.b8 122
+.b8 97
+.b8 103
+.b8 113
+.b8 103
+.b8 108
+.b8 98
+.b8 100
+.b8 107
+.b8 109
+.b8 120
+.b8 121
+.b8 121
+.b8 107
+.b8 119
+.b8 121
+.b8 114
+.b8 118
+.b8 120
+.b8 55
+.b8 107
+.b8 103
+.b8 107
+.b8 118
+.b8 97
+.b8 102
+.b8 109
+.b8 103
+.b8 55
+.b8 51
+.b8 113
+.b8 112
+.b8 110
+.b8 113
+.b8 98
+.b8 115
+.b8 118
+.b8 106
+.b8 98
+.b8 97
+.b8 46
+.b8 112
+.b8 121
+.b8 0
+.b32 .debug_line                        // DW_AT_stmt_list
+.b8 47                                  // DW_AT_comp_dir
+.b8 104
+.b8 111
+.b8 109
+.b8 101
+.b8 47
+.b8 120
+.b8 47
+.b8 46
+.b8 99
+.b8 97
+.b8 99
+.b8 104
+.b8 101
+.b8 47
+.b8 118
+.b8 108
+.b8 108
+.b8 109
+.b8 47
+.b8 116
+.b8 111
+.b8 114
+.b8 99
+.b8 104
+.b8 95
+.b8 99
+.b8 111
+.b8 109
+.b8 112
+.b8 105
+.b8 108
+.b8 101
+.b8 95
+.b8 99
+.b8 97
+.b8 99
+.b8 104
+.b8 101
+.b8 47
+.b8 99
+.b8 50
+.b8 50
+.b8 48
+.b8 50
+.b8 51
+.b8 56
+.b8 102
+.b8 97
+.b8 49
+.b8 47
+.b8 114
+.b8 97
+.b8 110
+.b8 107
+.b8 95
+.b8 48
+.b8 95
+.b8 48
+.b8 47
+.b8 105
+.b8 110
+.b8 100
+.b8 117
+.b8 99
+.b8 116
+.b8 111
+.b8 114
+.b8 95
+.b8 99
+.b8 97
+.b8 99
+.b8 104
+.b8 101
+.b8 47
+.b8 113
+.b8 118
+.b8 0
+.b8 2                                   // Abbrev [2] 0x9f:0x27 DW_TAG_subprogram
+.b8 116                                 // DW_AT_name
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 114
+.b8 101
+.b8 100
+.b8 95
+.b8 102
+.b8 117
+.b8 115
+.b8 101
+.b8 100
+.b8 95
+.b8 95
+.b8 116
+.b8 111
+.b8 95
+.b8 99
+.b8 111
+.b8 112
+.b8 121
+.b8 95
+.b8 109
+.b8 101
+.b8 97
+.b8 110
+.b8 95
+.b8 112
+.b8 111
+.b8 119
+.b8 95
+.b8 52
+.b8 0
+.b8 1                                   // DW_AT_inline
+.b8 3                                   // Abbrev [3] 0xc6:0x2e DW_TAG_subprogram
+.b64 $L__func_begin0                    // DW_AT_low_pc
+.b64 $L__func_end0                      // DW_AT_high_pc
+.b32 159                                // DW_AT_abstract_origin
+.b8 4                                   // Abbrev [4] 0xdb:0x18 DW_TAG_inlined_subroutine
+.b32 159                                // DW_AT_abstract_origin
+.b64 $L__tmp1                           // DW_AT_low_pc
+.b64 $L__tmp2                           // DW_AT_high_pc
+.b8 1                                   // DW_AT_call_file
+.b8 43                                  // DW_AT_call_line
+.b8 25                                  // DW_AT_call_column
+.b8 0                                   // End Of Children Mark
+.b8 0                                   // End Of Children Mark
+	}
+	.section	.debug_macinfo	{	}

platform/aiml/models/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/7HT2CE63ZPWWLF6VHGICDOM4HYEUTA7M6AOLPDEXBH7GNCOWXFEA/__grp__triton_red_fused__to_copy_mean_pow_3.json

@@ -0,0 +1 @@
+{"child_paths": {"triton_red_fused__to_copy_mean_pow_3.ttir": "/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/7HT2CE63ZPWWLF6VHGICDOM4HYEUTA7M6AOLPDEXBH7GNCOWXFEA/triton_red_fused__to_copy_mean_pow_3.ttir", "triton_red_fused__to_copy_mean_pow_3.ttgir": "/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/7HT2CE63ZPWWLF6VHGICDOM4HYEUTA7M6AOLPDEXBH7GNCOWXFEA/triton_red_fused__to_copy_mean_pow_3.ttgir", "triton_red_fused__to_copy_mean_pow_3.llir": "/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/7HT2CE63ZPWWLF6VHGICDOM4HYEUTA7M6AOLPDEXBH7GNCOWXFEA/triton_red_fused__to_copy_mean_pow_3.llir", "triton_red_fused__to_copy_mean_pow_3.ptx": "/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/7HT2CE63ZPWWLF6VHGICDOM4HYEUTA7M6AOLPDEXBH7GNCOWXFEA/triton_red_fused__to_copy_mean_pow_3.ptx", "triton_red_fused__to_copy_mean_pow_3.cubin": "/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/7HT2CE63ZPWWLF6VHGICDOM4HYEUTA7M6AOLPDEXBH7GNCOWXFEA/triton_red_fused__to_copy_mean_pow_3.cubin", "triton_red_fused__to_copy_mean_pow_3.json": "/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/7HT2CE63ZPWWLF6VHGICDOM4HYEUTA7M6AOLPDEXBH7GNCOWXFEA/triton_red_fused__to_copy_mean_pow_3.json"}}

platform/aiml/models/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/DKJC6KBZEIH6ZOGVIFAIW7VXA3LXVK3VLGBW2L7TDJMATPYGEZTQ/triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2.json

@@ -0,0 +1 @@
+{"hash": "1a922f2839220fecb8d541408b7eb706d77aab7559836d2ff31a5809bf062667", "target": {"backend": "cuda", "arch": 90, "warp_size": 32}, "num_warps": 16, "num_ctas": 1, "num_stages": 1, "num_buffers_warp_spec": 0, "num_consumer_groups": 0, "reg_dec_producer": 0, "reg_inc_consumer": 0, "maxnreg": null, "cluster_dims": [1, 1, 1], "ptx_version": null, "enable_fp_fusion": true, "launch_cooperative_grid": false, "supported_fp8_dtypes": ["fp8e4b15", "fp8e4nv", "fp8e5"], "deprecated_fp8_dtypes": ["fp8e4b15"], "default_dot_input_precision": "tf32", "allowed_dot_input_precisions": ["tf32", "tf32x3", "ieee"], "max_num_imprecise_acc_default": 1073741824, "extern_libs": [["libdevice", "/home/x/hfenv/lib/python3.12/site-packages/triton/backends/nvidia/lib/libdevice.10.bc"]], "debug": true, "backend_name": "cuda", "sanitize_overflow": false, "arch": "sm90", "triton_version": "3.3.1", "shared": 64, "tmem_size": 0, "global_scratch_size": 0, "global_scratch_align": 1, "name": "triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2"}

platform/aiml/models/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/EGYPFKOE54X556JS3SOC5OEVFCJ6L734JZZKIZBMHRGAAAIJL2LQ/triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2.json

@@ -0,0 +1 @@
+{"hash": "21b0f2a9c4ef2fdef932dc9c2eb8952893e5ff7c4e72a4642c3c4c0001095e97", "target": {"backend": "cuda", "arch": 90, "warp_size": 32}, "num_warps": 16, "num_ctas": 1, "num_stages": 1, "num_buffers_warp_spec": 0, "num_consumer_groups": 0, "reg_dec_producer": 0, "reg_inc_consumer": 0, "maxnreg": null, "cluster_dims": [1, 1, 1], "ptx_version": null, "enable_fp_fusion": true, "launch_cooperative_grid": false, "supported_fp8_dtypes": ["fp8e4b15", "fp8e4nv", "fp8e5"], "deprecated_fp8_dtypes": ["fp8e4b15"], "default_dot_input_precision": "tf32", "allowed_dot_input_precisions": ["tf32", "tf32x3", "ieee"], "max_num_imprecise_acc_default": 1073741824, "extern_libs": [["libdevice", "/home/x/hfenv/lib/python3.12/site-packages/triton/backends/nvidia/lib/libdevice.10.bc"]], "debug": true, "backend_name": "cuda", "sanitize_overflow": false, "arch": "sm90", "triton_version": "3.3.1", "shared": 64, "tmem_size": 0, "global_scratch_size": 0, "global_scratch_align": 1, "name": "triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2"}

platform/aiml/models/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/EGYPFKOE54X556JS3SOC5OEVFCJ6L734JZZKIZBMHRGAAAIJL2LQ/triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2.ptx

@@ -0,0 +1,1152 @@
+//
+// Generated by LLVM NVPTX Back-End
+//
+
+.version 8.4
+.target sm_90a
+.address_size 64
+
+	// .globl	triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2 // -- Begin function triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2
+.extern .shared .align 16 .b8 global_smem[];
+.global .align 1 .b8 _$_str[11] = {95, 95, 67, 85, 68, 65, 95, 70, 84, 90};
+                                        // @triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2
+.visible .entry triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2(
+	.param .u64 .ptr .global .align 1 triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2_param_0,
+	.param .u64 .ptr .global .align 1 triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2_param_1,
+	.param .u64 .ptr .global .align 1 triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2_param_2,
+	.param .u64 .ptr .global .align 1 triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2_param_3,
+	.param .u64 .ptr .global .align 1 triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2_param_4,
+	.param .u64 .ptr .global .align 1 triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2_param_5,
+	.param .u32 triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2_param_6,
+	.param .u32 triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2_param_7,
+	.param .u64 .ptr .global .align 1 triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2_param_8
+)
+.reqntid 512, 1, 1
+{
+	.reg .pred 	%p<66>;
+	.reg .b16 	%rs<71>;
+	.reg .b32 	%r<164>;
+	.reg .f32 	%f<169>;
+	.reg .b64 	%rd<87>;
+	.loc	1 18 0                          // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:18:0
+$L__func_begin0:
+	.loc	1 18 0                          // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:18:0
+
+// %bb.0:
+	ld.param.u64 	%rd8, [triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2_param_5];
+	ld.param.u64 	%rd7, [triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2_param_4];
+	ld.param.u64 	%rd6, [triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2_param_3];
+	ld.param.u64 	%rd5, [triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2_param_2];
+	ld.param.u64 	%rd4, [triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2_param_1];
+	ld.param.u64 	%rd3, [triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2_param_0];
+$L__tmp0:
+	.loc	1 22 28                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:22:28
+	mov.u32 	%r1, %ctaid.x;
+	ld.param.u32 	%r8, [triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2_param_6];
+	.loc	1 24 21                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:24:21
+	setp.lt.s32 	%p35, %r1, %r8;
+	.loc	1 25 37                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:25:37
+	mov.u32 	%r3, %tid.x;
+	and.b32  	%r4, %r3, 31;
+	shr.u32 	%r5, %r3, 5;
+	shl.b32 	%r9, %r3, 1;
+	and.b32  	%r6, %r9, 1022;
+	.loc	1 35 46                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:35:46
+	mul.lo.s32 	%r7, %r1, 5120;
+	or.b32  	%r10, %r6, %r7;
+	.loc	1 35 34                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:35:34
+	cvt.s64.s32 	%rd1, %r10;
+	mul.wide.s32 	%rd9, %r10, 2;
+	add.s64 	%rd50, %rd3, %rd9;
+	shl.b64 	%rd86, %rd1, 1;
+	@%p35 bra 	$L__BB0_2;
+	bra.uni 	$L__BB0_1;
+$L__BB0_2:                              // %.split.us.preheader
+	.loc	1 0 34                          // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:0:34
+	cvt.u32.u64 	%r76, %rd1;
+	mov.b32 	%r47, 0;
+	mov.pred 	%p17, -1;
+	.loc	1 35 51                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:35:51
+	// begin inline asm
+	mov.u32 %r46, %r47;
+	@%p17 ld.global.L1::evict_last.b32 { %r46 }, [ %rd50 + 0 ];
+	// end inline asm
+	.loc	1 36 34                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:36:34
+	add.s64 	%rd31, %rd4, %rd86;
+	.loc	1 36 51                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:36:51
+	// begin inline asm
+	mov.u32 %r48, %r47;
+	@%p17 ld.global.L1::evict_last.b32 { %r48 }, [ %rd31 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:37:34
+	add.s64 	%rd32, %rd5, %rd86;
+	.loc	1 37 51                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:37:51
+	// begin inline asm
+	mov.u32 %r50, %r47;
+	@%p17 ld.global.L1::evict_last.b32 { %r50 }, [ %rd32 + 0 ];
+	// end inline asm
+	.loc	1 35 41                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:35:41
+	add.s32 	%r77, %r76, 1024;
+	.loc	1 35 34                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:35:34
+	mul.wide.s32 	%rd46, %r77, 2;
+	add.s64 	%rd33, %rd3, %rd46;
+	.loc	1 35 51                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:35:51
+	// begin inline asm
+	mov.u32 %r52, %r47;
+	@%p17 ld.global.L1::evict_last.b32 { %r52 }, [ %rd33 + 0 ];
+	// end inline asm
+	.loc	1 36 34                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:36:34
+	add.s64 	%rd34, %rd4, %rd46;
+	.loc	1 36 51                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:36:51
+	// begin inline asm
+	mov.u32 %r54, %r47;
+	@%p17 ld.global.L1::evict_last.b32 { %r54 }, [ %rd34 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:37:34
+	add.s64 	%rd35, %rd5, %rd46;
+	.loc	1 37 51                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:37:51
+	// begin inline asm
+	mov.u32 %r56, %r47;
+	@%p17 ld.global.L1::evict_last.b32 { %r56 }, [ %rd35 + 0 ];
+	// end inline asm
+	.loc	1 35 41                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:35:41
+	add.s32 	%r78, %r76, 2048;
+	.loc	1 35 34                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:35:34
+	mul.wide.s32 	%rd47, %r78, 2;
+	add.s64 	%rd36, %rd3, %rd47;
+	.loc	1 35 51                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:35:51
+	// begin inline asm
+	mov.u32 %r58, %r47;
+	@%p17 ld.global.L1::evict_last.b32 { %r58 }, [ %rd36 + 0 ];
+	// end inline asm
+	.loc	1 36 34                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:36:34
+	add.s64 	%rd37, %rd4, %rd47;
+	.loc	1 36 51                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:36:51
+	// begin inline asm
+	mov.u32 %r60, %r47;
+	@%p17 ld.global.L1::evict_last.b32 { %r60 }, [ %rd37 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:37:34
+	add.s64 	%rd38, %rd5, %rd47;
+	.loc	1 37 51                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:37:51
+	// begin inline asm
+	mov.u32 %r62, %r47;
+	@%p17 ld.global.L1::evict_last.b32 { %r62 }, [ %rd38 + 0 ];
+	// end inline asm
+	.loc	1 35 41                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:35:41
+	add.s32 	%r79, %r76, 3072;
+	.loc	1 35 34                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:35:34
+	mul.wide.s32 	%rd48, %r79, 2;
+	add.s64 	%rd39, %rd3, %rd48;
+	.loc	1 35 51                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:35:51
+	// begin inline asm
+	mov.u32 %r64, %r47;
+	@%p17 ld.global.L1::evict_last.b32 { %r64 }, [ %rd39 + 0 ];
+	// end inline asm
+	.loc	1 36 34                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:36:34
+	add.s64 	%rd40, %rd4, %rd48;
+	.loc	1 36 51                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:36:51
+	// begin inline asm
+	mov.u32 %r66, %r47;
+	@%p17 ld.global.L1::evict_last.b32 { %r66 }, [ %rd40 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:37:34
+	add.s64 	%rd41, %rd5, %rd48;
+	.loc	1 37 51                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:37:51
+	// begin inline asm
+	mov.u32 %r68, %r47;
+	@%p17 ld.global.L1::evict_last.b32 { %r68 }, [ %rd41 + 0 ];
+	// end inline asm
+	.loc	1 35 41                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:35:41
+	add.s32 	%r80, %r76, 4096;
+	.loc	1 35 34                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:35:34
+	mul.wide.s32 	%rd49, %r80, 2;
+	add.s64 	%rd42, %rd3, %rd49;
+	.loc	1 35 51                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:35:51
+	// begin inline asm
+	mov.u32 %r70, %r47;
+	@%p17 ld.global.L1::evict_last.b32 { %r70 }, [ %rd42 + 0 ];
+	// end inline asm
+	.loc	1 36 34                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:36:34
+	add.s64 	%rd43, %rd4, %rd49;
+	.loc	1 36 51                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:36:51
+	// begin inline asm
+	mov.u32 %r72, %r47;
+	@%p17 ld.global.L1::evict_last.b32 { %r72 }, [ %rd43 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:37:34
+	add.s64 	%rd44, %rd5, %rd49;
+	.loc	1 37 51                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:37:51
+	// begin inline asm
+	mov.u32 %r74, %r47;
+	@%p17 ld.global.L1::evict_last.b32 { %r74 }, [ %rd44 + 0 ];
+	// end inline asm
+	.loc	1 35 112                        // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:35:112
+	mov.b32 	{%rs1, %rs2}, %r46;
+	cvt.f32.bf16 	%f4, %rs1;
+	cvt.f32.bf16 	%f5, %rs2;
+	.loc	1 36 112                        // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:36:112
+	mov.b32 	{%rs3, %rs4}, %r48;
+	cvt.f32.bf16 	%f6, %rs4;
+	cvt.f32.bf16 	%f7, %rs3;
+	.loc	1 37 112                        // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:37:112
+	mov.b32 	{%rs5, %rs6}, %r50;
+	cvt.f32.bf16 	%f8, %rs6;
+	cvt.f32.bf16 	%f9, %rs5;
+	.loc	1 41 22                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:41:22
+	add.f32 	%f10, %f7, %f9;
+	add.f32 	%f11, %f6, %f8;
+	.loc	1 42 22                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:42:22
+	add.f32 	%f12, %f11, %f5;
+	add.f32 	%f13, %f10, %f4;
+	.loc	1 35 112                        // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:35:112
+	mov.b32 	{%rs7, %rs8}, %r52;
+	cvt.f32.bf16 	%f14, %rs8;
+	cvt.f32.bf16 	%f15, %rs7;
+	.loc	1 36 112                        // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:36:112
+	mov.b32 	{%rs9, %rs10}, %r54;
+	cvt.f32.bf16 	%f16, %rs9;
+	cvt.f32.bf16 	%f17, %rs10;
+	.loc	1 37 112                        // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:37:112
+	mov.b32 	{%rs11, %rs12}, %r56;
+	cvt.f32.bf16 	%f18, %rs11;
+	cvt.f32.bf16 	%f19, %rs12;
+	.loc	1 41 22                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:41:22
+	add.f32 	%f20, %f17, %f19;
+	add.f32 	%f21, %f16, %f18;
+	.loc	1 42 22                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:42:22
+	add.f32 	%f22, %f21, %f15;
+	add.f32 	%f23, %f20, %f14;
+	.loc	1 43 22                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:43:22
+	mul.f32 	%f24, %f23, %f23;
+	mul.f32 	%f25, %f22, %f22;
+	.loc	1 45 25                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:45:25
+	fma.rn.f32 	%f26, %f13, %f13, %f25;
+	fma.rn.f32 	%f27, %f12, %f12, %f24;
+	.loc	1 35 112                        // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:35:112
+	mov.b32 	{%rs13, %rs14}, %r58;
+	cvt.f32.bf16 	%f28, %rs14;
+	cvt.f32.bf16 	%f29, %rs13;
+	.loc	1 36 112                        // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:36:112
+	mov.b32 	{%rs15, %rs16}, %r60;
+	cvt.f32.bf16 	%f30, %rs15;
+	cvt.f32.bf16 	%f31, %rs16;
+	.loc	1 37 112                        // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:37:112
+	mov.b32 	{%rs17, %rs18}, %r62;
+	cvt.f32.bf16 	%f32, %rs17;
+	cvt.f32.bf16 	%f33, %rs18;
+	.loc	1 41 22                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:41:22
+	add.f32 	%f34, %f31, %f33;
+	add.f32 	%f35, %f30, %f32;
+	.loc	1 42 22                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:42:22
+	add.f32 	%f36, %f35, %f29;
+	add.f32 	%f37, %f34, %f28;
+	.loc	1 45 25                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:45:25
+	fma.rn.f32 	%f38, %f37, %f37, %f27;
+	fma.rn.f32 	%f39, %f36, %f36, %f26;
+	.loc	1 35 112                        // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:35:112
+	mov.b32 	{%rs19, %rs20}, %r64;
+	cvt.f32.bf16 	%f40, %rs19;
+	cvt.f32.bf16 	%f41, %rs20;
+	.loc	1 36 112                        // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:36:112
+	mov.b32 	{%rs21, %rs22}, %r66;
+	cvt.f32.bf16 	%f42, %rs22;
+	cvt.f32.bf16 	%f43, %rs21;
+	.loc	1 37 112                        // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:37:112
+	mov.b32 	{%rs23, %rs24}, %r68;
+	cvt.f32.bf16 	%f44, %rs24;
+	cvt.f32.bf16 	%f45, %rs23;
+	.loc	1 41 22                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:41:22
+	add.f32 	%f46, %f43, %f45;
+	add.f32 	%f47, %f42, %f44;
+	.loc	1 42 22                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:42:22
+	add.f32 	%f48, %f47, %f41;
+	add.f32 	%f49, %f46, %f40;
+	.loc	1 45 25                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:45:25
+	fma.rn.f32 	%f50, %f49, %f49, %f39;
+	fma.rn.f32 	%f51, %f48, %f48, %f38;
+	.loc	1 35 112                        // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:35:112
+	mov.b32 	{%rs25, %rs26}, %r70;
+	cvt.f32.bf16 	%f52, %rs26;
+	cvt.f32.bf16 	%f53, %rs25;
+	.loc	1 36 112                        // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:36:112
+	mov.b32 	{%rs27, %rs28}, %r72;
+	cvt.f32.bf16 	%f54, %rs27;
+	cvt.f32.bf16 	%f55, %rs28;
+	.loc	1 37 112                        // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:37:112
+	mov.b32 	{%rs29, %rs30}, %r74;
+	cvt.f32.bf16 	%f56, %rs29;
+	cvt.f32.bf16 	%f57, %rs30;
+	.loc	1 41 22                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:41:22
+	add.f32 	%f58, %f55, %f57;
+	add.f32 	%f59, %f54, %f56;
+	.loc	1 42 22                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:42:22
+	add.f32 	%f60, %f59, %f53;
+	add.f32 	%f61, %f58, %f52;
+	.loc	1 45 25                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:45:25
+	fma.rn.f32 	%f62, %f61, %f61, %f51;
+	fma.rn.f32 	%f63, %f60, %f60, %f50;
+$L__tmp1:
+	.loc	2 286 36                        // standard.py:286:36
+	add.f32 	%f168, %f63, %f62;
+	bra.uni 	$L__BB0_3;
+$L__tmp2:
+$L__BB0_1:                              // %.split.preheader
+	.loc	2 0 36                          // standard.py:0:36
+	cvt.u32.u64 	%r41, %rd1;
+	mov.b32 	%r12, 0;
+	mov.pred 	%p2, 0;
+	.loc	1 35 51                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:35:51
+	// begin inline asm
+	mov.u32 %r11, %r12;
+	@%p2 ld.global.L1::evict_last.b32 { %r11 }, [ %rd50 + 0 ];
+	// end inline asm
+	.loc	1 36 34                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:36:34
+	add.s64 	%rd11, %rd4, %rd86;
+	.loc	1 36 51                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:36:51
+	// begin inline asm
+	mov.u32 %r13, %r12;
+	@%p2 ld.global.L1::evict_last.b32 { %r13 }, [ %rd11 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:37:34
+	add.s64 	%rd12, %rd5, %rd86;
+	.loc	1 37 51                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:37:51
+	// begin inline asm
+	mov.u32 %r15, %r12;
+	@%p2 ld.global.L1::evict_last.b32 { %r15 }, [ %rd12 + 0 ];
+	// end inline asm
+	.loc	1 35 41                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:35:41
+	add.s32 	%r42, %r41, 1024;
+	.loc	1 35 34                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:35:34
+	mul.wide.s32 	%rd26, %r42, 2;
+	add.s64 	%rd13, %rd3, %rd26;
+	.loc	1 35 51                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:35:51
+	// begin inline asm
+	mov.u32 %r17, %r12;
+	@%p2 ld.global.L1::evict_last.b32 { %r17 }, [ %rd13 + 0 ];
+	// end inline asm
+	.loc	1 36 34                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:36:34
+	add.s64 	%rd14, %rd4, %rd26;
+	.loc	1 36 51                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:36:51
+	// begin inline asm
+	mov.u32 %r19, %r12;
+	@%p2 ld.global.L1::evict_last.b32 { %r19 }, [ %rd14 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:37:34
+	add.s64 	%rd15, %rd5, %rd26;
+	.loc	1 37 51                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:37:51
+	// begin inline asm
+	mov.u32 %r21, %r12;
+	@%p2 ld.global.L1::evict_last.b32 { %r21 }, [ %rd15 + 0 ];
+	// end inline asm
+	.loc	1 35 41                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:35:41
+	add.s32 	%r43, %r41, 2048;
+	.loc	1 35 34                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:35:34
+	mul.wide.s32 	%rd27, %r43, 2;
+	add.s64 	%rd16, %rd3, %rd27;
+	.loc	1 35 51                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:35:51
+	// begin inline asm
+	mov.u32 %r23, %r12;
+	@%p2 ld.global.L1::evict_last.b32 { %r23 }, [ %rd16 + 0 ];
+	// end inline asm
+	.loc	1 36 34                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:36:34
+	add.s64 	%rd17, %rd4, %rd27;
+	.loc	1 36 51                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:36:51
+	// begin inline asm
+	mov.u32 %r25, %r12;
+	@%p2 ld.global.L1::evict_last.b32 { %r25 }, [ %rd17 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:37:34
+	add.s64 	%rd18, %rd5, %rd27;
+	.loc	1 37 51                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:37:51
+	// begin inline asm
+	mov.u32 %r27, %r12;
+	@%p2 ld.global.L1::evict_last.b32 { %r27 }, [ %rd18 + 0 ];
+	// end inline asm
+	.loc	1 35 41                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:35:41
+	add.s32 	%r44, %r41, 3072;
+	.loc	1 35 34                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:35:34
+	mul.wide.s32 	%rd28, %r44, 2;
+	add.s64 	%rd19, %rd3, %rd28;
+	.loc	1 35 51                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:35:51
+	// begin inline asm
+	mov.u32 %r29, %r12;
+	@%p2 ld.global.L1::evict_last.b32 { %r29 }, [ %rd19 + 0 ];
+	// end inline asm
+	.loc	1 36 34                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:36:34
+	add.s64 	%rd20, %rd4, %rd28;
+	.loc	1 36 51                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:36:51
+	// begin inline asm
+	mov.u32 %r31, %r12;
+	@%p2 ld.global.L1::evict_last.b32 { %r31 }, [ %rd20 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:37:34
+	add.s64 	%rd21, %rd5, %rd28;
+	.loc	1 37 51                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:37:51
+	// begin inline asm
+	mov.u32 %r33, %r12;
+	@%p2 ld.global.L1::evict_last.b32 { %r33 }, [ %rd21 + 0 ];
+	// end inline asm
+	.loc	1 35 41                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:35:41
+	add.s32 	%r45, %r41, 4096;
+	.loc	1 35 34                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:35:34
+	mul.wide.s32 	%rd29, %r45, 2;
+	add.s64 	%rd22, %rd3, %rd29;
+	.loc	1 35 51                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:35:51
+	// begin inline asm
+	mov.u32 %r35, %r12;
+	@%p2 ld.global.L1::evict_last.b32 { %r35 }, [ %rd22 + 0 ];
+	// end inline asm
+	.loc	1 36 34                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:36:34
+	add.s64 	%rd23, %rd4, %rd29;
+	.loc	1 36 51                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:36:51
+	// begin inline asm
+	mov.u32 %r37, %r12;
+	@%p2 ld.global.L1::evict_last.b32 { %r37 }, [ %rd23 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:37:34
+	add.s64 	%rd24, %rd5, %rd29;
+	.loc	1 37 51                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:37:51
+	// begin inline asm
+	mov.u32 %r39, %r12;
+	@%p2 ld.global.L1::evict_last.b32 { %r39 }, [ %rd24 + 0 ];
+	// end inline asm
+	mov.f32 	%f168, 0f00000000;
+$L__BB0_3:                              // %__nv_rsqrtf.exit
+$L__tmp3:
+	.loc	2 286 36                        // standard.py:286:36
+	mov.b32 	%r137, %f168;
+	shfl.sync.bfly.b32	%r138, %r137, 16, 31, -1;
+	mov.b32 	%f64, %r138;
+	.loc	2 256 15                        // standard.py:256:15
+	add.f32 	%f65, %f168, %f64;
+	.loc	2 286 36                        // standard.py:286:36
+	mov.b32 	%r139, %f65;
+	shfl.sync.bfly.b32	%r140, %r139, 8, 31, -1;
+	mov.b32 	%f66, %r140;
+	.loc	2 256 15                        // standard.py:256:15
+	add.f32 	%f67, %f65, %f66;
+	.loc	2 286 36                        // standard.py:286:36
+	mov.b32 	%r141, %f67;
+	shfl.sync.bfly.b32	%r142, %r141, 4, 31, -1;
+	mov.b32 	%f68, %r142;
+	.loc	2 256 15                        // standard.py:256:15
+	add.f32 	%f69, %f67, %f68;
+	.loc	2 286 36                        // standard.py:286:36
+	mov.b32 	%r143, %f69;
+	shfl.sync.bfly.b32	%r144, %r143, 2, 31, -1;
+	mov.b32 	%f70, %r144;
+	.loc	2 256 15                        // standard.py:256:15
+	add.f32 	%f71, %f69, %f70;
+	.loc	2 286 36                        // standard.py:286:36
+	mov.b32 	%r145, %f71;
+	shfl.sync.bfly.b32	%r146, %r145, 1, 31, -1;
+	mov.b32 	%f72, %r146;
+	.loc	2 256 15                        // standard.py:256:15
+	add.f32 	%f73, %f71, %f72;
+	.loc	2 286 36                        // standard.py:286:36
+	and.b32  	%r147, %r5, 15;
+	setp.eq.s32 	%p32, %r4, 0;
+	shl.b32 	%r148, %r147, 2;
+	mov.u32 	%r149, global_smem;
+	add.s32 	%r81, %r149, %r148;
+	mov.b32 	%r82, %f73;
+	// begin inline asm
+	@%p32 st.shared.b32 [ %r81 + 0 ], %r82;
+	// end inline asm
+	bar.sync 	0;
+	setp.lt.s32 	%p33, %r3, 16;
+	shl.b32 	%r150, %r3, 2;
+	add.s32 	%r84, %r149, %r150;
+	// begin inline asm
+	@%p33 ld.shared.b32 %r83, [ %r84 + 0 ];
+	// end inline asm
+	mov.b32 	%f74, %r83;
+	shfl.sync.bfly.b32	%r151, %r83, 8, 31, -1;
+	mov.b32 	%f75, %r151;
+	.loc	2 256 15                        // standard.py:256:15
+	add.f32 	%f76, %f74, %f75;
+	.loc	2 286 36                        // standard.py:286:36
+	mov.b32 	%r152, %f76;
+	shfl.sync.bfly.b32	%r153, %r152, 4, 31, -1;
+	mov.b32 	%f77, %r153;
+	.loc	2 256 15                        // standard.py:256:15
+	add.f32 	%f78, %f76, %f77;
+	.loc	2 286 36                        // standard.py:286:36
+	mov.b32 	%r154, %f78;
+	shfl.sync.bfly.b32	%r155, %r154, 2, 31, -1;
+	mov.b32 	%f79, %r155;
+	.loc	2 256 15                        // standard.py:256:15
+	add.f32 	%f80, %f78, %f79;
+	.loc	2 286 36                        // standard.py:286:36
+	mov.b32 	%r156, %f80;
+	shfl.sync.bfly.b32	%r157, %r156, 1, 31, -1;
+	mov.b32 	%f81, %r157;
+	.loc	2 256 15                        // standard.py:256:15
+	add.f32 	%f82, %f80, %f81;
+	.loc	2 286 36                        // standard.py:286:36
+	and.b32  	%r158, %r3, 15;
+	setp.eq.s32 	%p65, %r158, 0;
+	and.pred  	%p34, %p33, %p65;
+	mov.b32 	%r86, %f82;
+	// begin inline asm
+	@%p34 st.shared.b32 [ %r84 + 0 ], %r86;
+	// end inline asm
+	bar.sync 	0;
+	ld.shared.f32 	%f83, [global_smem];
+	mov.f32 	%f84, 0f45A00000;
+$L__tmp4:
+	.loc	1 64 25                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:64:25
+	div.full.f32 	%f85, %f83, %f84;
+	.loc	1 66 24                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:66:24
+	add.f32 	%f86, %f85, 0f358637BD;
+	.loc	1 67 32                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:67:32
+	rsqrt.approx.ftz.f32 	%f87, %f86;
+	mov.b32 	%r88, 0;
+	.loc	1 54 52                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:54:52
+	// begin inline asm
+	mov.u32 %r87, %r88;
+	@%p35 ld.global.L1::evict_first.b32 { %r87 }, [ %rd50 + 0 ];
+	// end inline asm
+	.loc	1 55 35                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:55:35
+	add.s64 	%rd51, %rd4, %rd86;
+	.loc	1 55 52                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:55:52
+	// begin inline asm
+	mov.u32 %r89, %r88;
+	@%p35 ld.global.L1::evict_first.b32 { %r89 }, [ %rd51 + 0 ];
+	// end inline asm
+	.loc	1 56 35                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:56:35
+	add.s64 	%rd52, %rd5, %rd86;
+	.loc	1 56 52                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:56:52
+	// begin inline asm
+	mov.u32 %r91, %r88;
+	@%p35 ld.global.L1::evict_first.b32 { %r91 }, [ %rd52 + 0 ];
+	// end inline asm
+	.loc	1 57 35                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:57:35
+	mul.wide.u32 	%rd81, %r6, 2;
+	add.s64 	%rd53, %rd6, %rd81;
+	mov.pred 	%p38, -1;
+	.loc	1 57 42                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:57:42
+	// begin inline asm
+	mov.u32 %r93, %r88;
+	@%p38 ld.global.L1::evict_last.b32 { %r93 }, [ %rd53 + 0 ];
+	// end inline asm
+	.loc	1 72 29                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:72:29
+	add.s64 	%rd54, %rd7, %rd86;
+	.loc	1 54 114                        // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:54:114
+	mov.b32 	{%rs31, %rs32}, %r87;
+	cvt.f32.bf16 	%f88, %rs32;
+	cvt.f32.bf16 	%f89, %rs31;
+	.loc	1 55 114                        // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:55:114
+	mov.b32 	{%rs33, %rs34}, %r89;
+	cvt.f32.bf16 	%f90, %rs33;
+	cvt.f32.bf16 	%f91, %rs34;
+	.loc	1 56 114                        // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:56:114
+	mov.b32 	{%rs35, %rs36}, %r91;
+	cvt.f32.bf16 	%f92, %rs35;
+	cvt.f32.bf16 	%f93, %rs36;
+	.loc	1 57 95                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:57:95
+	mov.b32 	{%rs37, %rs38}, %r93;
+	cvt.f32.bf16 	%f94, %rs38;
+	cvt.f32.bf16 	%f95, %rs37;
+	.loc	1 61 24                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:61:24
+	add.f32 	%f96, %f91, %f93;
+	add.f32 	%f97, %f90, %f92;
+	.loc	1 62 24                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:62:24
+	add.f32 	%f98, %f97, %f89;
+	add.f32 	%f99, %f96, %f88;
+	.loc	1 68 24                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:68:24
+	mul.f32 	%f100, %f87, %f99;
+	mul.f32 	%f101, %f87, %f98;
+	.loc	1 70 24                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:70:24
+	mul.f32 	%f102, %f101, %f95;
+	mul.f32 	%f103, %f100, %f94;
+	.loc	1 72 53                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:72:53
+	cvt.rn.bf16x2.f32 	%r95, %f103, %f102;
+	// begin inline asm
+	@%p35 st.global.b32 [ %rd54 + 0 ], { %r95 };
+	// end inline asm
+	.loc	1 73 29                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:73:29
+	add.s64 	%rd55, %rd8, %rd86;
+	.loc	1 73 53                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:73:53
+	cvt.rn.bf16x2.f32 	%r96, %f99, %f98;
+	// begin inline asm
+	@%p35 st.global.b32 [ %rd55 + 0 ], { %r96 };
+	// end inline asm
+	.loc	1 54 42                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:54:42
+	add.s32 	%r159, %r7, %r6;
+	add.s32 	%r160, %r159, 1024;
+	.loc	1 54 35                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:54:35
+	mul.wide.s32 	%rd82, %r160, 2;
+	add.s64 	%rd56, %rd3, %rd82;
+	.loc	1 54 52                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:54:52
+	// begin inline asm
+	mov.u32 %r97, %r88;
+	@%p35 ld.global.L1::evict_first.b32 { %r97 }, [ %rd56 + 0 ];
+	// end inline asm
+	.loc	1 55 35                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:55:35
+	add.s64 	%rd57, %rd4, %rd82;
+	.loc	1 55 52                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:55:52
+	// begin inline asm
+	mov.u32 %r99, %r88;
+	@%p35 ld.global.L1::evict_first.b32 { %r99 }, [ %rd57 + 0 ];
+	// end inline asm
+	.loc	1 56 35                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:56:35
+	add.s64 	%rd58, %rd5, %rd82;
+	.loc	1 56 52                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:56:52
+	// begin inline asm
+	mov.u32 %r101, %r88;
+	@%p35 ld.global.L1::evict_first.b32 { %r101 }, [ %rd58 + 0 ];
+	// end inline asm
+	.loc	1 57 35                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:57:35
+	add.s64 	%rd59, %rd53, 2048;
+	.loc	1 57 42                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:57:42
+	// begin inline asm
+	mov.u32 %r103, %r88;
+	@%p38 ld.global.L1::evict_last.b32 { %r103 }, [ %rd59 + 0 ];
+	// end inline asm
+	.loc	1 72 29                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:72:29
+	add.s64 	%rd60, %rd7, %rd82;
+	.loc	1 54 114                        // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:54:114
+	mov.b32 	{%rs39, %rs40}, %r97;
+	cvt.f32.bf16 	%f104, %rs40;
+	cvt.f32.bf16 	%f105, %rs39;
+	.loc	1 55 114                        // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:55:114
+	mov.b32 	{%rs41, %rs42}, %r99;
+	cvt.f32.bf16 	%f106, %rs41;
+	cvt.f32.bf16 	%f107, %rs42;
+	.loc	1 56 114                        // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:56:114
+	mov.b32 	{%rs43, %rs44}, %r101;
+	cvt.f32.bf16 	%f108, %rs43;
+	cvt.f32.bf16 	%f109, %rs44;
+	.loc	1 57 95                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:57:95
+	mov.b32 	{%rs45, %rs46}, %r103;
+	cvt.f32.bf16 	%f110, %rs46;
+	cvt.f32.bf16 	%f111, %rs45;
+	.loc	1 61 24                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:61:24
+	add.f32 	%f112, %f107, %f109;
+	add.f32 	%f113, %f106, %f108;
+	.loc	1 62 24                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:62:24
+	add.f32 	%f114, %f113, %f105;
+	add.f32 	%f115, %f112, %f104;
+	.loc	1 68 24                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:68:24
+	mul.f32 	%f116, %f87, %f115;
+	mul.f32 	%f117, %f87, %f114;
+	.loc	1 70 24                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:70:24
+	mul.f32 	%f118, %f117, %f111;
+	mul.f32 	%f119, %f116, %f110;
+	.loc	1 72 53                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:72:53
+	cvt.rn.bf16x2.f32 	%r105, %f119, %f118;
+	// begin inline asm
+	@%p35 st.global.b32 [ %rd60 + 0 ], { %r105 };
+	// end inline asm
+	.loc	1 73 29                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:73:29
+	add.s64 	%rd61, %rd8, %rd82;
+	.loc	1 73 53                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:73:53
+	cvt.rn.bf16x2.f32 	%r106, %f115, %f114;
+	// begin inline asm
+	@%p35 st.global.b32 [ %rd61 + 0 ], { %r106 };
+	// end inline asm
+	.loc	1 54 42                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:54:42
+	add.s32 	%r161, %r159, 2048;
+	.loc	1 54 35                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:54:35
+	mul.wide.s32 	%rd83, %r161, 2;
+	add.s64 	%rd62, %rd3, %rd83;
+	.loc	1 54 52                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:54:52
+	// begin inline asm
+	mov.u32 %r107, %r88;
+	@%p35 ld.global.L1::evict_first.b32 { %r107 }, [ %rd62 + 0 ];
+	// end inline asm
+	.loc	1 55 35                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:55:35
+	add.s64 	%rd63, %rd4, %rd83;
+	.loc	1 55 52                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:55:52
+	// begin inline asm
+	mov.u32 %r109, %r88;
+	@%p35 ld.global.L1::evict_first.b32 { %r109 }, [ %rd63 + 0 ];
+	// end inline asm
+	.loc	1 56 35                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:56:35
+	add.s64 	%rd64, %rd5, %rd83;
+	.loc	1 56 52                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:56:52
+	// begin inline asm
+	mov.u32 %r111, %r88;
+	@%p35 ld.global.L1::evict_first.b32 { %r111 }, [ %rd64 + 0 ];
+	// end inline asm
+	.loc	1 57 35                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:57:35
+	add.s64 	%rd65, %rd53, 4096;
+	.loc	1 57 42                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:57:42
+	// begin inline asm
+	mov.u32 %r113, %r88;
+	@%p38 ld.global.L1::evict_last.b32 { %r113 }, [ %rd65 + 0 ];
+	// end inline asm
+	.loc	1 72 29                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:72:29
+	add.s64 	%rd66, %rd7, %rd83;
+	.loc	1 54 114                        // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:54:114
+	mov.b32 	{%rs47, %rs48}, %r107;
+	cvt.f32.bf16 	%f120, %rs48;
+	cvt.f32.bf16 	%f121, %rs47;
+	.loc	1 55 114                        // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:55:114
+	mov.b32 	{%rs49, %rs50}, %r109;
+	cvt.f32.bf16 	%f122, %rs49;
+	cvt.f32.bf16 	%f123, %rs50;
+	.loc	1 56 114                        // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:56:114
+	mov.b32 	{%rs51, %rs52}, %r111;
+	cvt.f32.bf16 	%f124, %rs51;
+	cvt.f32.bf16 	%f125, %rs52;
+	.loc	1 57 95                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:57:95
+	mov.b32 	{%rs53, %rs54}, %r113;
+	cvt.f32.bf16 	%f126, %rs54;
+	cvt.f32.bf16 	%f127, %rs53;
+	.loc	1 61 24                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:61:24
+	add.f32 	%f128, %f123, %f125;
+	add.f32 	%f129, %f122, %f124;
+	.loc	1 62 24                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:62:24
+	add.f32 	%f130, %f129, %f121;
+	add.f32 	%f131, %f128, %f120;
+	.loc	1 68 24                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:68:24
+	mul.f32 	%f132, %f87, %f131;
+	mul.f32 	%f133, %f87, %f130;
+	.loc	1 70 24                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:70:24
+	mul.f32 	%f134, %f133, %f127;
+	mul.f32 	%f135, %f132, %f126;
+	.loc	1 72 53                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:72:53
+	cvt.rn.bf16x2.f32 	%r115, %f135, %f134;
+	// begin inline asm
+	@%p35 st.global.b32 [ %rd66 + 0 ], { %r115 };
+	// end inline asm
+	.loc	1 73 29                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:73:29
+	add.s64 	%rd67, %rd8, %rd83;
+	.loc	1 73 53                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:73:53
+	cvt.rn.bf16x2.f32 	%r116, %f131, %f130;
+	// begin inline asm
+	@%p35 st.global.b32 [ %rd67 + 0 ], { %r116 };
+	// end inline asm
+	.loc	1 54 42                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:54:42
+	add.s32 	%r162, %r159, 3072;
+	.loc	1 54 35                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:54:35
+	mul.wide.s32 	%rd84, %r162, 2;
+	add.s64 	%rd68, %rd3, %rd84;
+	.loc	1 54 52                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:54:52
+	// begin inline asm
+	mov.u32 %r117, %r88;
+	@%p35 ld.global.L1::evict_first.b32 { %r117 }, [ %rd68 + 0 ];
+	// end inline asm
+	.loc	1 55 35                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:55:35
+	add.s64 	%rd69, %rd4, %rd84;
+	.loc	1 55 52                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:55:52
+	// begin inline asm
+	mov.u32 %r119, %r88;
+	@%p35 ld.global.L1::evict_first.b32 { %r119 }, [ %rd69 + 0 ];
+	// end inline asm
+	.loc	1 56 35                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:56:35
+	add.s64 	%rd70, %rd5, %rd84;
+	.loc	1 56 52                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:56:52
+	// begin inline asm
+	mov.u32 %r121, %r88;
+	@%p35 ld.global.L1::evict_first.b32 { %r121 }, [ %rd70 + 0 ];
+	// end inline asm
+	.loc	1 57 35                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:57:35
+	add.s64 	%rd71, %rd53, 6144;
+	.loc	1 57 42                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:57:42
+	// begin inline asm
+	mov.u32 %r123, %r88;
+	@%p38 ld.global.L1::evict_last.b32 { %r123 }, [ %rd71 + 0 ];
+	// end inline asm
+	.loc	1 72 29                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:72:29
+	add.s64 	%rd72, %rd7, %rd84;
+	.loc	1 54 114                        // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:54:114
+	mov.b32 	{%rs55, %rs56}, %r117;
+	cvt.f32.bf16 	%f136, %rs56;
+	cvt.f32.bf16 	%f137, %rs55;
+	.loc	1 55 114                        // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:55:114
+	mov.b32 	{%rs57, %rs58}, %r119;
+	cvt.f32.bf16 	%f138, %rs57;
+	cvt.f32.bf16 	%f139, %rs58;
+	.loc	1 56 114                        // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:56:114
+	mov.b32 	{%rs59, %rs60}, %r121;
+	cvt.f32.bf16 	%f140, %rs59;
+	cvt.f32.bf16 	%f141, %rs60;
+	.loc	1 57 95                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:57:95
+	mov.b32 	{%rs61, %rs62}, %r123;
+	cvt.f32.bf16 	%f142, %rs62;
+	cvt.f32.bf16 	%f143, %rs61;
+	.loc	1 61 24                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:61:24
+	add.f32 	%f144, %f139, %f141;
+	add.f32 	%f145, %f138, %f140;
+	.loc	1 62 24                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:62:24
+	add.f32 	%f146, %f145, %f137;
+	add.f32 	%f147, %f144, %f136;
+	.loc	1 68 24                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:68:24
+	mul.f32 	%f148, %f87, %f147;
+	mul.f32 	%f149, %f87, %f146;
+	.loc	1 70 24                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:70:24
+	mul.f32 	%f150, %f149, %f143;
+	mul.f32 	%f151, %f148, %f142;
+	.loc	1 72 53                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:72:53
+	cvt.rn.bf16x2.f32 	%r125, %f151, %f150;
+	// begin inline asm
+	@%p35 st.global.b32 [ %rd72 + 0 ], { %r125 };
+	// end inline asm
+	.loc	1 73 29                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:73:29
+	add.s64 	%rd73, %rd8, %rd84;
+	.loc	1 73 53                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:73:53
+	cvt.rn.bf16x2.f32 	%r126, %f147, %f146;
+	// begin inline asm
+	@%p35 st.global.b32 [ %rd73 + 0 ], { %r126 };
+	// end inline asm
+	.loc	1 54 42                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:54:42
+	add.s32 	%r163, %r159, 4096;
+	.loc	1 54 35                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:54:35
+	mul.wide.s32 	%rd85, %r163, 2;
+	add.s64 	%rd74, %rd3, %rd85;
+	.loc	1 54 52                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:54:52
+	// begin inline asm
+	mov.u32 %r127, %r88;
+	@%p35 ld.global.L1::evict_first.b32 { %r127 }, [ %rd74 + 0 ];
+	// end inline asm
+	.loc	1 55 35                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:55:35
+	add.s64 	%rd75, %rd4, %rd85;
+	.loc	1 55 52                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:55:52
+	// begin inline asm
+	mov.u32 %r129, %r88;
+	@%p35 ld.global.L1::evict_first.b32 { %r129 }, [ %rd75 + 0 ];
+	// end inline asm
+	.loc	1 56 35                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:56:35
+	add.s64 	%rd76, %rd5, %rd85;
+	.loc	1 56 52                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:56:52
+	// begin inline asm
+	mov.u32 %r131, %r88;
+	@%p35 ld.global.L1::evict_first.b32 { %r131 }, [ %rd76 + 0 ];
+	// end inline asm
+	.loc	1 57 35                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:57:35
+	add.s64 	%rd77, %rd53, 8192;
+	.loc	1 57 42                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:57:42
+	// begin inline asm
+	mov.u32 %r133, %r88;
+	@%p38 ld.global.L1::evict_last.b32 { %r133 }, [ %rd77 + 0 ];
+	// end inline asm
+	.loc	1 72 29                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:72:29
+	add.s64 	%rd78, %rd7, %rd85;
+	.loc	1 54 114                        // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:54:114
+	mov.b32 	{%rs63, %rs64}, %r127;
+	cvt.f32.bf16 	%f152, %rs64;
+	cvt.f32.bf16 	%f153, %rs63;
+	.loc	1 55 114                        // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:55:114
+	mov.b32 	{%rs65, %rs66}, %r129;
+	cvt.f32.bf16 	%f154, %rs65;
+	cvt.f32.bf16 	%f155, %rs66;
+	.loc	1 56 114                        // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:56:114
+	mov.b32 	{%rs67, %rs68}, %r131;
+	cvt.f32.bf16 	%f156, %rs67;
+	cvt.f32.bf16 	%f157, %rs68;
+	.loc	1 57 95                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:57:95
+	mov.b32 	{%rs69, %rs70}, %r133;
+	cvt.f32.bf16 	%f158, %rs70;
+	cvt.f32.bf16 	%f159, %rs69;
+	.loc	1 61 24                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:61:24
+	add.f32 	%f160, %f155, %f157;
+	add.f32 	%f161, %f154, %f156;
+	.loc	1 62 24                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:62:24
+	add.f32 	%f162, %f161, %f153;
+	add.f32 	%f163, %f160, %f152;
+	.loc	1 68 24                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:68:24
+	mul.f32 	%f164, %f87, %f163;
+	mul.f32 	%f165, %f87, %f162;
+	.loc	1 70 24                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:70:24
+	mul.f32 	%f166, %f165, %f159;
+	mul.f32 	%f167, %f164, %f158;
+	.loc	1 72 53                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:72:53
+	cvt.rn.bf16x2.f32 	%r135, %f167, %f166;
+	// begin inline asm
+	@%p35 st.global.b32 [ %rd78 + 0 ], { %r135 };
+	// end inline asm
+	.loc	1 73 29                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:73:29
+	add.s64 	%rd79, %rd8, %rd85;
+	.loc	1 73 53                         // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:73:53
+	cvt.rn.bf16x2.f32 	%r136, %f163, %f162;
+	// begin inline asm
+	@%p35 st.global.b32 [ %rd79 + 0 ], { %r136 };
+	// end inline asm
+	.loc	1 48 4                          // c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py:48:4
+	ret;
+$L__tmp5:
+$L__func_end0:
+                                        // -- End function
+}
+	.file	1 "/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/62/c62ht5sat4th6qg7lspfb4fa3jtzrr63akwvgp2t6k6gbvb4oigf.py"
+	.file	2 "/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py"
+	.section	.debug_abbrev
+	{
+.b8 1                                   // Abbreviation Code
+.b8 17                                  // DW_TAG_compile_unit
+.b8 1                                   // DW_CHILDREN_yes
+.b8 37                                  // DW_AT_producer
+.b8 8                                   // DW_FORM_string
+.b8 19                                  // DW_AT_language
+.b8 5                                   // DW_FORM_data2
+.b8 3                                   // DW_AT_name
+.b8 8                                   // DW_FORM_string
+.b8 16                                  // DW_AT_stmt_list
+.b8 6                                   // DW_FORM_data4
+.b8 27                                  // DW_AT_comp_dir
+.b8 8                                   // DW_FORM_string
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 2                                   // Abbreviation Code
+.b8 46                                  // DW_TAG_subprogram
+.b8 0                                   // DW_CHILDREN_no
+.b8 3                                   // DW_AT_name
+.b8 8                                   // DW_FORM_string
+.b8 32                                  // DW_AT_inline
+.b8 11                                  // DW_FORM_data1
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 3                                   // Abbreviation Code
+.b8 46                                  // DW_TAG_subprogram
+.b8 1                                   // DW_CHILDREN_yes
+.b8 17                                  // DW_AT_low_pc
+.b8 1                                   // DW_FORM_addr
+.b8 18                                  // DW_AT_high_pc
+.b8 1                                   // DW_FORM_addr
+.b8 49                                  // DW_AT_abstract_origin
+.b8 19                                  // DW_FORM_ref4
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 4                                   // Abbreviation Code
+.b8 29                                  // DW_TAG_inlined_subroutine
+.b8 0                                   // DW_CHILDREN_no
+.b8 49                                  // DW_AT_abstract_origin
+.b8 19                                  // DW_FORM_ref4
+.b8 17                                  // DW_AT_low_pc
+.b8 1                                   // DW_FORM_addr
+.b8 18                                  // DW_AT_high_pc
+.b8 1                                   // DW_FORM_addr
+.b8 88                                  // DW_AT_call_file
+.b8 11                                  // DW_FORM_data1
+.b8 89                                  // DW_AT_call_line
+.b8 11                                  // DW_FORM_data1
+.b8 87                                  // DW_AT_call_column
+.b8 11                                  // DW_FORM_data1
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 0                                   // EOM(3)
+	}
+	.section	.debug_info
+	{
+.b32 255                                // Length of Unit
+.b8 2                                   // DWARF version number
+.b8 0
+.b32 .debug_abbrev                      // Offset Into Abbrev. Section
+.b8 8                                   // Address Size (in bytes)
+.b8 1                                   // Abbrev [1] 0xb:0xf8 DW_TAG_compile_unit
+.b8 116                                 // DW_AT_producer
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 0
+.b8 2                                   // DW_AT_language
+.b8 0
+.b8 99                                  // DW_AT_name
+.b8 54
+.b8 50
+.b8 104
+.b8 116
+.b8 53
+.b8 115
+.b8 97
+.b8 116
+.b8 52
+.b8 116
+.b8 104
+.b8 54
+.b8 113
+.b8 103
+.b8 55
+.b8 108
+.b8 115
+.b8 112
+.b8 102
+.b8 98
+.b8 52
+.b8 102
+.b8 97
+.b8 51
+.b8 106
+.b8 116
+.b8 122
+.b8 114
+.b8 114
+.b8 54
+.b8 51
+.b8 97
+.b8 107
+.b8 119
+.b8 118
+.b8 103
+.b8 112
+.b8 50
+.b8 116
+.b8 54
+.b8 107
+.b8 54
+.b8 103
+.b8 98
+.b8 118
+.b8 98
+.b8 52
+.b8 111
+.b8 105
+.b8 103
+.b8 102
+.b8 46
+.b8 112
+.b8 121
+.b8 0
+.b32 .debug_line                        // DW_AT_stmt_list
+.b8 47                                  // DW_AT_comp_dir
+.b8 104
+.b8 111
+.b8 109
+.b8 101
+.b8 47
+.b8 120
+.b8 47
+.b8 46
+.b8 99
+.b8 97
+.b8 99
+.b8 104
+.b8 101
+.b8 47
+.b8 118
+.b8 108
+.b8 108
+.b8 109
+.b8 47
+.b8 116
+.b8 111
+.b8 114
+.b8 99
+.b8 104
+.b8 95
+.b8 99
+.b8 111
+.b8 109
+.b8 112
+.b8 105
+.b8 108
+.b8 101
+.b8 95
+.b8 99
+.b8 97
+.b8 99
+.b8 104
+.b8 101
+.b8 47
+.b8 99
+.b8 50
+.b8 50
+.b8 48
+.b8 50
+.b8 51
+.b8 56
+.b8 102
+.b8 97
+.b8 49
+.b8 47
+.b8 114
+.b8 97
+.b8 110
+.b8 107
+.b8 95
+.b8 48
+.b8 95
+.b8 48
+.b8 47
+.b8 105
+.b8 110
+.b8 100
+.b8 117
+.b8 99
+.b8 116
+.b8 111
+.b8 114
+.b8 95
+.b8 99
+.b8 97
+.b8 99
+.b8 104
+.b8 101
+.b8 47
+.b8 54
+.b8 50
+.b8 0
+.b8 2                                   // Abbrev [2] 0x9f:0x35 DW_TAG_subprogram
+.b8 116                                 // DW_AT_name
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 114
+.b8 101
+.b8 100
+.b8 95
+.b8 102
+.b8 117
+.b8 115
+.b8 101
+.b8 100
+.b8 95
+.b8 95
+.b8 116
+.b8 111
+.b8 95
+.b8 99
+.b8 111
+.b8 112
+.b8 121
+.b8 95
+.b8 97
+.b8 100
+.b8 100
+.b8 95
+.b8 109
+.b8 101
+.b8 97
+.b8 110
+.b8 95
+.b8 109
+.b8 117
+.b8 108
+.b8 95
+.b8 112
+.b8 111
+.b8 119
+.b8 95
+.b8 114
+.b8 115
+.b8 113
+.b8 114
+.b8 116
+.b8 95
+.b8 50
+.b8 0
+.b8 1                                   // DW_AT_inline
+.b8 3                                   // Abbrev [3] 0xd4:0x2e DW_TAG_subprogram
+.b64 $L__func_begin0                    // DW_AT_low_pc
+.b64 $L__func_end0                      // DW_AT_high_pc
+.b32 159                                // DW_AT_abstract_origin
+.b8 4                                   // Abbrev [4] 0xe9:0x18 DW_TAG_inlined_subroutine
+.b32 159                                // DW_AT_abstract_origin
+.b64 $L__tmp1                           // DW_AT_low_pc
+.b64 $L__tmp4                           // DW_AT_high_pc
+.b8 1                                   // DW_AT_call_file
+.b8 47                                  // DW_AT_call_line
+.b8 27                                  // DW_AT_call_column
+.b8 0                                   // End Of Children Mark
+.b8 0                                   // End Of Children Mark
+	}
+	.section	.debug_macinfo	{	}

platform/aiml/models/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/GYVDTKQVTOVBT7EHBNWUFZYSRBLO4IMUH537TRFNX6DB3IREUQ2A/__grp__triton_poi_fused_add_mul_sub_6.json

@@ -0,0 +1 @@
+{"child_paths": {"triton_poi_fused_add_mul_sub_6.ttir": "/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/GYVDTKQVTOVBT7EHBNWUFZYSRBLO4IMUH537TRFNX6DB3IREUQ2A/triton_poi_fused_add_mul_sub_6.ttir", "triton_poi_fused_add_mul_sub_6.ttgir": "/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/GYVDTKQVTOVBT7EHBNWUFZYSRBLO4IMUH537TRFNX6DB3IREUQ2A/triton_poi_fused_add_mul_sub_6.ttgir", "triton_poi_fused_add_mul_sub_6.llir": "/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/GYVDTKQVTOVBT7EHBNWUFZYSRBLO4IMUH537TRFNX6DB3IREUQ2A/triton_poi_fused_add_mul_sub_6.llir", "triton_poi_fused_add_mul_sub_6.ptx": "/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/GYVDTKQVTOVBT7EHBNWUFZYSRBLO4IMUH537TRFNX6DB3IREUQ2A/triton_poi_fused_add_mul_sub_6.ptx", "triton_poi_fused_add_mul_sub_6.cubin": "/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/GYVDTKQVTOVBT7EHBNWUFZYSRBLO4IMUH537TRFNX6DB3IREUQ2A/triton_poi_fused_add_mul_sub_6.cubin", "triton_poi_fused_add_mul_sub_6.json": "/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/GYVDTKQVTOVBT7EHBNWUFZYSRBLO4IMUH537TRFNX6DB3IREUQ2A/triton_poi_fused_add_mul_sub_6.json"}}

platform/aiml/models/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/GYVDTKQVTOVBT7EHBNWUFZYSRBLO4IMUH537TRFNX6DB3IREUQ2A/triton_poi_fused_add_mul_sub_6.json

@@ -0,0 +1 @@
+{"hash": "362a39aa159baa19fc870b6d42e7128856ee21943f77f9c4adbf861da224a434", "target": {"backend": "cuda", "arch": 90, "warp_size": 32}, "num_warps": 4, "num_ctas": 1, "num_stages": 1, "num_buffers_warp_spec": 0, "num_consumer_groups": 0, "reg_dec_producer": 0, "reg_inc_consumer": 0, "maxnreg": null, "cluster_dims": [1, 1, 1], "ptx_version": null, "enable_fp_fusion": true, "launch_cooperative_grid": false, "supported_fp8_dtypes": ["fp8e4b15", "fp8e4nv", "fp8e5"], "deprecated_fp8_dtypes": ["fp8e4b15"], "default_dot_input_precision": "tf32", "allowed_dot_input_precisions": ["tf32", "tf32x3", "ieee"], "max_num_imprecise_acc_default": 1073741824, "extern_libs": [["libdevice", "/home/x/hfenv/lib/python3.12/site-packages/triton/backends/nvidia/lib/libdevice.10.bc"]], "debug": true, "backend_name": "cuda", "sanitize_overflow": false, "arch": "sm90", "triton_version": "3.3.1", "shared": 0, "tmem_size": 0, "global_scratch_size": 0, "global_scratch_align": 1, "name": "triton_poi_fused_add_mul_sub_6"}

platform/aiml/models/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/GYVDTKQVTOVBT7EHBNWUFZYSRBLO4IMUH537TRFNX6DB3IREUQ2A/triton_poi_fused_add_mul_sub_6.llir

@@ -0,0 +1,673 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+target datalayout = "e-p3:32:32-p4:32:32-p5:32:32-p6:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64"
+
+@assertFunc_0 = internal constant [8 x i8] c"unknown\00"
+@assertFile_0 = internal constant [134 x i8] c"/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py\00"
+@assertMessage_0 = internal constant [41 x i8] c"index out of bounds: 0 <= tmp16 < 131072\00"
+@.str = private unnamed_addr constant [11 x i8] c"__CUDA_FTZ\00", align 1
+
+; Function Attrs: noreturn
+declare !dbg !6 void @__assertfail(ptr, ptr, i32, ptr, i64) local_unnamed_addr #0
+
+define ptx_kernel void @triton_poi_fused_add_mul_sub_6(ptr addrspace(1) %0, ptr addrspace(1) %1, ptr addrspace(1) %2, ptr addrspace(1) %3, ptr addrspace(1) %4, ptr addrspace(1) %5, ptr addrspace(1) %6, i32 %7, ptr addrspace(1) readnone captures(none) %8) local_unnamed_addr !dbg !10 {
+  %10 = tail call i32 @llvm.nvvm.read.ptx.sreg.ctaid.x(), !dbg !11
+  %11 = shl i32 %10, 10, !dbg !12
+  %12 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !13
+  %13 = shl i32 %12, 3, !dbg !13
+  %14 = and i32 %13, 1016, !dbg !13
+  %15 = or disjoint i32 %14, %11, !dbg !14
+  %16 = or disjoint i32 %15, 1, !dbg !14
+  %17 = or disjoint i32 %15, 2, !dbg !14
+  %18 = or disjoint i32 %15, 3, !dbg !14
+  %19 = or disjoint i32 %15, 4, !dbg !14
+  %20 = or disjoint i32 %15, 5, !dbg !14
+  %21 = or disjoint i32 %15, 6, !dbg !14
+  %22 = or disjoint i32 %15, 7, !dbg !14
+  %23 = icmp slt i32 %15, %7, !dbg !15
+  %24 = sdiv i32 %15, 64, !dbg !16
+  %25 = mul i32 %24, 64, !dbg !17
+  %.decomposed = sub i32 %15, %25, !dbg !17
+  %26 = srem i32 %16, 64, !dbg !17
+  %27 = srem i32 %17, 64, !dbg !17
+  %28 = srem i32 %18, 64, !dbg !17
+  %29 = srem i32 %19, 64, !dbg !17
+  %30 = srem i32 %20, 64, !dbg !17
+  %31 = srem i32 %21, 64, !dbg !17
+  %32 = srem i32 %22, 64, !dbg !17
+  %33 = srem i32 %24, 8, !dbg !18
+  %34 = sdiv i32 %15, 512, !dbg !19
+  %35 = shl nsw i32 %33, 7, !dbg !20
+  %36 = mul i32 %34, 7168, !dbg !21
+  %37 = add i32 %35, %36, !dbg !22
+  %38 = add i32 %37, 5120, !dbg !23
+  %39 = add i32 %38, %.decomposed, !dbg !24
+  %40 = sext i32 %39 to i64, !dbg !25
+  %41 = getelementptr bfloat, ptr addrspace(1) %0, i64 %40, !dbg !25
+  %42 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];", "=r,=r,=r,=r,l,b"(ptr addrspace(1) %41, i1 %23) #5, !dbg !26
+  %43 = sext i32 %24 to i64, !dbg !27
+  %44 = getelementptr float, ptr addrspace(1) %1, i64 %43, !dbg !27
+  %45 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %44, i1 %23) #5, !dbg !28
+  %46 = bitcast i32 %45 to float, !dbg !28
+  %47 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %44, i1 %23) #5, !dbg !28
+  %48 = bitcast i32 %47 to float, !dbg !28
+  %49 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %44, i1 %23) #5, !dbg !28
+  %50 = bitcast i32 %49 to float, !dbg !28
+  %51 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %44, i1 %23) #5, !dbg !28
+  %52 = bitcast i32 %51 to float, !dbg !28
+  %53 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %44, i1 %23) #5, !dbg !28
+  %54 = bitcast i32 %53 to float, !dbg !28
+  %55 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %44, i1 %23) #5, !dbg !28
+  %56 = bitcast i32 %55 to float, !dbg !28
+  %57 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %44, i1 %23) #5, !dbg !28
+  %58 = bitcast i32 %57 to float, !dbg !28
+  %59 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %44, i1 %23) #5, !dbg !28
+  %60 = bitcast i32 %59 to float, !dbg !28
+  %61 = sext i32 %.decomposed to i64, !dbg !29
+  %62 = getelementptr bfloat, ptr addrspace(1) %2, i64 %61, !dbg !29
+  %63 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];", "=r,=r,=r,=r,l,b"(ptr addrspace(1) %62, i1 %23) #5, !dbg !30
+  %64 = sext i32 %34 to i64, !dbg !31
+  %65 = getelementptr i64, ptr addrspace(1) %3, i64 %64, !dbg !31
+  %66 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %65, i1 %23) #5, !dbg !32
+  %67 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %65, i1 %23) #5, !dbg !32
+  %68 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %65, i1 %23) #5, !dbg !32
+  %69 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %65, i1 %23) #5, !dbg !32
+  %70 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %65, i1 %23) #5, !dbg !32
+  %71 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %65, i1 %23) #5, !dbg !32
+  %72 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %65, i1 %23) #5, !dbg !32
+  %73 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %65, i1 %23) #5, !dbg !32
+  %74 = add nsw i32 %.decomposed, 64, !dbg !33
+  %75 = add i32 %37, 5184, !dbg !34
+  %76 = add nsw i32 %75, %.decomposed, !dbg !35
+  %77 = add nsw i32 %75, %26, !dbg !35
+  %78 = add nsw i32 %75, %27, !dbg !35
+  %79 = add nsw i32 %75, %28, !dbg !35
+  %80 = add nsw i32 %75, %29, !dbg !35
+  %81 = add nsw i32 %75, %30, !dbg !35
+  %82 = add nsw i32 %75, %31, !dbg !35
+  %83 = add nsw i32 %75, %32, !dbg !35
+  %84 = sext i32 %76 to i64, !dbg !36
+  %85 = getelementptr bfloat, ptr addrspace(1) %0, i64 %84, !dbg !36
+  %86 = sext i32 %77 to i64, !dbg !36
+  %87 = getelementptr bfloat, ptr addrspace(1) %0, i64 %86, !dbg !36
+  %88 = sext i32 %78 to i64, !dbg !36
+  %89 = getelementptr bfloat, ptr addrspace(1) %0, i64 %88, !dbg !36
+  %90 = sext i32 %79 to i64, !dbg !36
+  %91 = getelementptr bfloat, ptr addrspace(1) %0, i64 %90, !dbg !36
+  %92 = sext i32 %80 to i64, !dbg !36
+  %93 = getelementptr bfloat, ptr addrspace(1) %0, i64 %92, !dbg !36
+  %94 = sext i32 %81 to i64, !dbg !36
+  %95 = getelementptr bfloat, ptr addrspace(1) %0, i64 %94, !dbg !36
+  %96 = sext i32 %82 to i64, !dbg !36
+  %97 = getelementptr bfloat, ptr addrspace(1) %0, i64 %96, !dbg !36
+  %98 = sext i32 %83 to i64, !dbg !36
+  %99 = getelementptr bfloat, ptr addrspace(1) %0, i64 %98, !dbg !36
+  %100 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.b16 { $0 }, [ $1 + 0 ];", "=c,l,b"(ptr addrspace(1) %85, i1 %23) #5, !dbg !37
+  %101 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.b16 { $0 }, [ $1 + 0 ];", "=c,l,b"(ptr addrspace(1) %87, i1 %23) #5, !dbg !37
+  %102 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.b16 { $0 }, [ $1 + 0 ];", "=c,l,b"(ptr addrspace(1) %89, i1 %23) #5, !dbg !37
+  %103 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.b16 { $0 }, [ $1 + 0 ];", "=c,l,b"(ptr addrspace(1) %91, i1 %23) #5, !dbg !37
+  %104 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.b16 { $0 }, [ $1 + 0 ];", "=c,l,b"(ptr addrspace(1) %93, i1 %23) #5, !dbg !37
+  %105 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.b16 { $0 }, [ $1 + 0 ];", "=c,l,b"(ptr addrspace(1) %95, i1 %23) #5, !dbg !37
+  %106 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.b16 { $0 }, [ $1 + 0 ];", "=c,l,b"(ptr addrspace(1) %97, i1 %23) #5, !dbg !37
+  %107 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.b16 { $0 }, [ $1 + 0 ];", "=c,l,b"(ptr addrspace(1) %99, i1 %23) #5, !dbg !37
+  %108 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %44, i1 %23) #5, !dbg !38
+  %109 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %44, i1 %23) #5, !dbg !38
+  %110 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %44, i1 %23) #5, !dbg !38
+  %111 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %44, i1 %23) #5, !dbg !38
+  %112 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %44, i1 %23) #5, !dbg !38
+  %113 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %44, i1 %23) #5, !dbg !38
+  %114 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %44, i1 %23) #5, !dbg !38
+  %115 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %44, i1 %23) #5, !dbg !38
+  %116 = zext nneg i32 %74 to i64, !dbg !39
+  %117 = getelementptr bfloat, ptr addrspace(1) %2, i64 %116, !dbg !39
+  %118 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];", "=r,=r,=r,=r,l,b"(ptr addrspace(1) %117, i1 %23) #5, !dbg !40
+  %119 = tail call float @llvm.nvvm.div.full(float %46, float 1.280000e+02), !dbg !41
+  %120 = tail call float @llvm.nvvm.div.full(float %48, float 1.280000e+02), !dbg !41
+  %121 = tail call float @llvm.nvvm.div.full(float %50, float 1.280000e+02), !dbg !41
+  %122 = tail call float @llvm.nvvm.div.full(float %52, float 1.280000e+02), !dbg !41
+  %123 = tail call float @llvm.nvvm.div.full(float %54, float 1.280000e+02), !dbg !41
+  %124 = tail call float @llvm.nvvm.div.full(float %56, float 1.280000e+02), !dbg !41
+  %125 = tail call float @llvm.nvvm.div.full(float %58, float 1.280000e+02), !dbg !41
+  %126 = tail call float @llvm.nvvm.div.full(float %60, float 1.280000e+02), !dbg !41
+  %127 = fadd float %119, 0x3EB0C6F7A0000000, !dbg !42
+  %128 = fadd float %120, 0x3EB0C6F7A0000000, !dbg !42
+  %129 = fadd float %121, 0x3EB0C6F7A0000000, !dbg !42
+  %130 = fadd float %122, 0x3EB0C6F7A0000000, !dbg !42
+  %131 = fadd float %123, 0x3EB0C6F7A0000000, !dbg !42
+  %132 = fadd float %124, 0x3EB0C6F7A0000000, !dbg !42
+  %133 = fadd float %125, 0x3EB0C6F7A0000000, !dbg !42
+  %134 = fadd float %126, 0x3EB0C6F7A0000000, !dbg !42
+  %135 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5, !dbg !43
+  %.not.i = icmp eq i32 %135, 0, !dbg !43
+  br i1 %.not.i, label %138, label %136, !dbg !43
+
+136:                                              ; preds = %9
+  %137 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %127), !dbg !43
+  br label %__nv_rsqrtf.exit, !dbg !43
+
+138:                                              ; preds = %9
+  %139 = tail call float @llvm.nvvm.rsqrt.approx.f(float %127), !dbg !43
+  br label %__nv_rsqrtf.exit, !dbg !43
+
+__nv_rsqrtf.exit:                                 ; preds = %136, %138
+  %.0.i = phi float [ %137, %136 ], [ %139, %138 ], !dbg !43
+  %140 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5, !dbg !43
+  %.not.i2 = icmp eq i32 %140, 0, !dbg !43
+  br i1 %.not.i2, label %143, label %141, !dbg !43
+
+141:                                              ; preds = %__nv_rsqrtf.exit
+  %142 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %128), !dbg !43
+  br label %__nv_rsqrtf.exit4, !dbg !43
+
+143:                                              ; preds = %__nv_rsqrtf.exit
+  %144 = tail call float @llvm.nvvm.rsqrt.approx.f(float %128), !dbg !43
+  br label %__nv_rsqrtf.exit4, !dbg !43
+
+__nv_rsqrtf.exit4:                                ; preds = %141, %143
+  %.0.i3 = phi float [ %142, %141 ], [ %144, %143 ], !dbg !43
+  %145 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5, !dbg !43
+  %.not.i5 = icmp eq i32 %145, 0, !dbg !43
+  br i1 %.not.i5, label %148, label %146, !dbg !43
+
+146:                                              ; preds = %__nv_rsqrtf.exit4
+  %147 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %129), !dbg !43
+  br label %__nv_rsqrtf.exit7, !dbg !43
+
+148:                                              ; preds = %__nv_rsqrtf.exit4
+  %149 = tail call float @llvm.nvvm.rsqrt.approx.f(float %129), !dbg !43
+  br label %__nv_rsqrtf.exit7, !dbg !43
+
+__nv_rsqrtf.exit7:                                ; preds = %146, %148
+  %.0.i6 = phi float [ %147, %146 ], [ %149, %148 ], !dbg !43
+  %150 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5, !dbg !43
+  %.not.i8 = icmp eq i32 %150, 0, !dbg !43
+  br i1 %.not.i8, label %153, label %151, !dbg !43
+
+151:                                              ; preds = %__nv_rsqrtf.exit7
+  %152 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %130), !dbg !43
+  br label %__nv_rsqrtf.exit10, !dbg !43
+
+153:                                              ; preds = %__nv_rsqrtf.exit7
+  %154 = tail call float @llvm.nvvm.rsqrt.approx.f(float %130), !dbg !43
+  br label %__nv_rsqrtf.exit10, !dbg !43
+
+__nv_rsqrtf.exit10:                               ; preds = %151, %153
+  %.0.i9 = phi float [ %152, %151 ], [ %154, %153 ], !dbg !43
+  %155 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5, !dbg !43
+  %.not.i11 = icmp eq i32 %155, 0, !dbg !43
+  br i1 %.not.i11, label %158, label %156, !dbg !43
+
+156:                                              ; preds = %__nv_rsqrtf.exit10
+  %157 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %131), !dbg !43
+  br label %__nv_rsqrtf.exit13, !dbg !43
+
+158:                                              ; preds = %__nv_rsqrtf.exit10
+  %159 = tail call float @llvm.nvvm.rsqrt.approx.f(float %131), !dbg !43
+  br label %__nv_rsqrtf.exit13, !dbg !43
+
+__nv_rsqrtf.exit13:                               ; preds = %156, %158
+  %.0.i12 = phi float [ %157, %156 ], [ %159, %158 ], !dbg !43
+  %160 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5, !dbg !43
+  %.not.i14 = icmp eq i32 %160, 0, !dbg !43
+  br i1 %.not.i14, label %163, label %161, !dbg !43
+
+161:                                              ; preds = %__nv_rsqrtf.exit13
+  %162 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %132), !dbg !43
+  br label %__nv_rsqrtf.exit16, !dbg !43
+
+163:                                              ; preds = %__nv_rsqrtf.exit13
+  %164 = tail call float @llvm.nvvm.rsqrt.approx.f(float %132), !dbg !43
+  br label %__nv_rsqrtf.exit16, !dbg !43
+
+__nv_rsqrtf.exit16:                               ; preds = %161, %163
+  %.0.i15 = phi float [ %162, %161 ], [ %164, %163 ], !dbg !43
+  %165 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5, !dbg !43
+  %.not.i17 = icmp eq i32 %165, 0, !dbg !43
+  br i1 %.not.i17, label %168, label %166, !dbg !43
+
+166:                                              ; preds = %__nv_rsqrtf.exit16
+  %167 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %133), !dbg !43
+  br label %__nv_rsqrtf.exit19, !dbg !43
+
+168:                                              ; preds = %__nv_rsqrtf.exit16
+  %169 = tail call float @llvm.nvvm.rsqrt.approx.f(float %133), !dbg !43
+  br label %__nv_rsqrtf.exit19, !dbg !43
+
+__nv_rsqrtf.exit19:                               ; preds = %166, %168
+  %.0.i18 = phi float [ %167, %166 ], [ %169, %168 ], !dbg !43
+  %170 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5, !dbg !43
+  %.not.i20 = icmp eq i32 %170, 0, !dbg !43
+  br i1 %.not.i20, label %173, label %171, !dbg !43
+
+171:                                              ; preds = %__nv_rsqrtf.exit19
+  %172 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %134), !dbg !43
+  br label %__nv_rsqrtf.exit22, !dbg !43
+
+173:                                              ; preds = %__nv_rsqrtf.exit19
+  %174 = tail call float @llvm.nvvm.rsqrt.approx.f(float %134), !dbg !43
+  br label %__nv_rsqrtf.exit22, !dbg !43
+
+__nv_rsqrtf.exit22:                               ; preds = %171, %173
+  %.0.i21 = phi float [ %172, %171 ], [ %174, %173 ], !dbg !43
+  %175 = lshr i64 %66, 46, !dbg !44
+  %176 = and i64 %175, 131072, !dbg !44
+  %177 = add i64 %176, %66, !dbg !44
+  %178 = icmp ugt i64 %177, 131071, !dbg !45
+  %.not1 = and i1 %23, %178, !dbg !46
+  br i1 %.not1, label %179, label %180, !dbg !46
+
+179:                                              ; preds = %__nv_rsqrtf.exit22
+  tail call void @__assertfail(ptr nonnull @assertMessage_0, ptr nonnull @assertFile_0, i32 46, ptr nonnull @assertFunc_0, i64 1), !dbg !46
+  unreachable, !dbg !46
+
+180:                                              ; preds = %__nv_rsqrtf.exit22
+  %181 = bitcast i32 %115 to float, !dbg !38
+  %182 = bitcast i32 %114 to float, !dbg !38
+  %183 = bitcast i32 %113 to float, !dbg !38
+  %184 = bitcast i32 %112 to float, !dbg !38
+  %185 = bitcast i32 %111 to float, !dbg !38
+  %186 = bitcast i32 %110 to float, !dbg !38
+  %187 = bitcast i32 %109 to float, !dbg !38
+  %188 = bitcast i32 %108 to float, !dbg !38
+  tail call void @llvm.nvvm.barrier0(), !dbg !46
+  %.idx = shl i64 %177, 8, !dbg !47
+  %189 = getelementptr i8, ptr addrspace(1) %4, i64 %.idx, !dbg !47
+  %190 = getelementptr bfloat, ptr addrspace(1) %189, i64 %61, !dbg !47
+  %191 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];", "=r,=r,=r,=r,l,b"(ptr addrspace(1) %190, i1 %23) #5, !dbg !48
+  %192 = tail call float @llvm.nvvm.div.full(float %188, float 1.280000e+02), !dbg !49
+  %193 = tail call float @llvm.nvvm.div.full(float %187, float 1.280000e+02), !dbg !49
+  %194 = tail call float @llvm.nvvm.div.full(float %186, float 1.280000e+02), !dbg !49
+  %195 = tail call float @llvm.nvvm.div.full(float %185, float 1.280000e+02), !dbg !49
+  %196 = tail call float @llvm.nvvm.div.full(float %184, float 1.280000e+02), !dbg !49
+  %197 = tail call float @llvm.nvvm.div.full(float %183, float 1.280000e+02), !dbg !49
+  %198 = tail call float @llvm.nvvm.div.full(float %182, float 1.280000e+02), !dbg !49
+  %199 = tail call float @llvm.nvvm.div.full(float %181, float 1.280000e+02), !dbg !49
+  %200 = fadd float %192, 0x3EB0C6F7A0000000, !dbg !50
+  %201 = fadd float %193, 0x3EB0C6F7A0000000, !dbg !50
+  %202 = fadd float %194, 0x3EB0C6F7A0000000, !dbg !50
+  %203 = fadd float %195, 0x3EB0C6F7A0000000, !dbg !50
+  %204 = fadd float %196, 0x3EB0C6F7A0000000, !dbg !50
+  %205 = fadd float %197, 0x3EB0C6F7A0000000, !dbg !50
+  %206 = fadd float %198, 0x3EB0C6F7A0000000, !dbg !50
+  %207 = fadd float %199, 0x3EB0C6F7A0000000, !dbg !50
+  %208 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5, !dbg !51
+  %.not.i23 = icmp eq i32 %208, 0, !dbg !51
+  br i1 %.not.i23, label %211, label %209, !dbg !51
+
+209:                                              ; preds = %180
+  %210 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %200), !dbg !51
+  br label %__nv_rsqrtf.exit25, !dbg !51
+
+211:                                              ; preds = %180
+  %212 = tail call float @llvm.nvvm.rsqrt.approx.f(float %200), !dbg !51
+  br label %__nv_rsqrtf.exit25, !dbg !51
+
+__nv_rsqrtf.exit25:                               ; preds = %209, %211
+  %.0.i24 = phi float [ %210, %209 ], [ %212, %211 ], !dbg !51
+  %213 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5, !dbg !51
+  %.not.i26 = icmp eq i32 %213, 0, !dbg !51
+  br i1 %.not.i26, label %216, label %214, !dbg !51
+
+214:                                              ; preds = %__nv_rsqrtf.exit25
+  %215 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %201), !dbg !51
+  br label %__nv_rsqrtf.exit28, !dbg !51
+
+216:                                              ; preds = %__nv_rsqrtf.exit25
+  %217 = tail call float @llvm.nvvm.rsqrt.approx.f(float %201), !dbg !51
+  br label %__nv_rsqrtf.exit28, !dbg !51
+
+__nv_rsqrtf.exit28:                               ; preds = %214, %216
+  %.0.i27 = phi float [ %215, %214 ], [ %217, %216 ], !dbg !51
+  %218 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5, !dbg !51
+  %.not.i29 = icmp eq i32 %218, 0, !dbg !51
+  br i1 %.not.i29, label %221, label %219, !dbg !51
+
+219:                                              ; preds = %__nv_rsqrtf.exit28
+  %220 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %202), !dbg !51
+  br label %__nv_rsqrtf.exit31, !dbg !51
+
+221:                                              ; preds = %__nv_rsqrtf.exit28
+  %222 = tail call float @llvm.nvvm.rsqrt.approx.f(float %202), !dbg !51
+  br label %__nv_rsqrtf.exit31, !dbg !51
+
+__nv_rsqrtf.exit31:                               ; preds = %219, %221
+  %.0.i30 = phi float [ %220, %219 ], [ %222, %221 ], !dbg !51
+  %223 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5, !dbg !51
+  %.not.i32 = icmp eq i32 %223, 0, !dbg !51
+  br i1 %.not.i32, label %226, label %224, !dbg !51
+
+224:                                              ; preds = %__nv_rsqrtf.exit31
+  %225 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %203), !dbg !51
+  br label %__nv_rsqrtf.exit34, !dbg !51
+
+226:                                              ; preds = %__nv_rsqrtf.exit31
+  %227 = tail call float @llvm.nvvm.rsqrt.approx.f(float %203), !dbg !51
+  br label %__nv_rsqrtf.exit34, !dbg !51
+
+__nv_rsqrtf.exit34:                               ; preds = %224, %226
+  %.0.i33 = phi float [ %225, %224 ], [ %227, %226 ], !dbg !51
+  %228 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5, !dbg !51
+  %.not.i35 = icmp eq i32 %228, 0, !dbg !51
+  br i1 %.not.i35, label %231, label %229, !dbg !51
+
+229:                                              ; preds = %__nv_rsqrtf.exit34
+  %230 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %204), !dbg !51
+  br label %__nv_rsqrtf.exit37, !dbg !51
+
+231:                                              ; preds = %__nv_rsqrtf.exit34
+  %232 = tail call float @llvm.nvvm.rsqrt.approx.f(float %204), !dbg !51
+  br label %__nv_rsqrtf.exit37, !dbg !51
+
+__nv_rsqrtf.exit37:                               ; preds = %229, %231
+  %.0.i36 = phi float [ %230, %229 ], [ %232, %231 ], !dbg !51
+  %233 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5, !dbg !51
+  %.not.i38 = icmp eq i32 %233, 0, !dbg !51
+  br i1 %.not.i38, label %236, label %234, !dbg !51
+
+234:                                              ; preds = %__nv_rsqrtf.exit37
+  %235 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %205), !dbg !51
+  br label %__nv_rsqrtf.exit40, !dbg !51
+
+236:                                              ; preds = %__nv_rsqrtf.exit37
+  %237 = tail call float @llvm.nvvm.rsqrt.approx.f(float %205), !dbg !51
+  br label %__nv_rsqrtf.exit40, !dbg !51
+
+__nv_rsqrtf.exit40:                               ; preds = %234, %236
+  %.0.i39 = phi float [ %235, %234 ], [ %237, %236 ], !dbg !51
+  %238 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5, !dbg !51
+  %.not.i41 = icmp eq i32 %238, 0, !dbg !51
+  br i1 %.not.i41, label %241, label %239, !dbg !51
+
+239:                                              ; preds = %__nv_rsqrtf.exit40
+  %240 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %206), !dbg !51
+  br label %__nv_rsqrtf.exit43, !dbg !51
+
+241:                                              ; preds = %__nv_rsqrtf.exit40
+  %242 = tail call float @llvm.nvvm.rsqrt.approx.f(float %206), !dbg !51
+  br label %__nv_rsqrtf.exit43, !dbg !51
+
+__nv_rsqrtf.exit43:                               ; preds = %239, %241
+  %.0.i42 = phi float [ %240, %239 ], [ %242, %241 ], !dbg !51
+  %243 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5, !dbg !51
+  %.not.i44 = icmp eq i32 %243, 0, !dbg !51
+  br i1 %.not.i44, label %246, label %244, !dbg !51
+
+244:                                              ; preds = %__nv_rsqrtf.exit43
+  %245 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %207), !dbg !51
+  br label %__nv_rsqrtf.exit46, !dbg !51
+
+246:                                              ; preds = %__nv_rsqrtf.exit43
+  %247 = tail call float @llvm.nvvm.rsqrt.approx.f(float %207), !dbg !51
+  br label %__nv_rsqrtf.exit46, !dbg !51
+
+__nv_rsqrtf.exit46:                               ; preds = %244, %246
+  %.0.i45 = phi float [ %245, %244 ], [ %247, %246 ], !dbg !51
+  %248 = extractvalue { i32, i32, i32, i32 } %42, 3, !dbg !26
+  %249 = bitcast i32 %248 to <2 x bfloat>, !dbg !26
+  %250 = extractvalue { i32, i32, i32, i32 } %63, 3, !dbg !30
+  %251 = bitcast i32 %250 to <2 x bfloat>, !dbg !30
+  %252 = extractvalue { i32, i32, i32, i32 } %191, 3, !dbg !48
+  %253 = bitcast i32 %252 to <2 x bfloat>, !dbg !48
+  %254 = extractvalue { i32, i32, i32, i32 } %42, 2, !dbg !26
+  %255 = bitcast i32 %254 to <2 x bfloat>, !dbg !26
+  %256 = extractvalue { i32, i32, i32, i32 } %63, 2, !dbg !30
+  %257 = bitcast i32 %256 to <2 x bfloat>, !dbg !30
+  %258 = extractvalue { i32, i32, i32, i32 } %191, 2, !dbg !48
+  %259 = bitcast i32 %258 to <2 x bfloat>, !dbg !48
+  %260 = extractvalue { i32, i32, i32, i32 } %42, 1, !dbg !26
+  %261 = bitcast i32 %260 to <2 x bfloat>, !dbg !26
+  %262 = extractvalue { i32, i32, i32, i32 } %63, 1, !dbg !30
+  %263 = bitcast i32 %262 to <2 x bfloat>, !dbg !30
+  %264 = extractvalue { i32, i32, i32, i32 } %191, 1, !dbg !48
+  %265 = bitcast i32 %264 to <2 x bfloat>, !dbg !48
+  %266 = extractvalue { i32, i32, i32, i32 } %42, 0, !dbg !26
+  %267 = bitcast i32 %266 to <2 x bfloat>, !dbg !26
+  %268 = extractvalue { i32, i32, i32, i32 } %63, 0, !dbg !30
+  %269 = bitcast i32 %268 to <2 x bfloat>, !dbg !30
+  %270 = extractvalue { i32, i32, i32, i32 } %191, 0, !dbg !48
+  %271 = bitcast i32 %270 to <2 x bfloat>, !dbg !48
+  %272 = insertelement <2 x i16> poison, i16 %100, i64 0, !dbg !37
+  %273 = insertelement <2 x i16> %272, i16 %101, i64 1, !dbg !37
+  %274 = bitcast <2 x i16> %273 to <2 x bfloat>, !dbg !37
+  %275 = insertelement <2 x i16> poison, i16 %102, i64 0, !dbg !37
+  %276 = insertelement <2 x i16> %275, i16 %103, i64 1, !dbg !37
+  %277 = bitcast <2 x i16> %276 to <2 x bfloat>, !dbg !37
+  %278 = insertelement <2 x i16> poison, i16 %104, i64 0, !dbg !37
+  %279 = insertelement <2 x i16> %278, i16 %105, i64 1, !dbg !37
+  %280 = bitcast <2 x i16> %279 to <2 x bfloat>, !dbg !37
+  %281 = insertelement <2 x i16> poison, i16 %106, i64 0, !dbg !37
+  %282 = insertelement <2 x i16> %281, i16 %107, i64 1, !dbg !37
+  %283 = bitcast <2 x i16> %282 to <2 x bfloat>, !dbg !37
+  %284 = extractvalue { i32, i32, i32, i32 } %118, 0, !dbg !40
+  %285 = bitcast i32 %284 to <2 x bfloat>, !dbg !40
+  %286 = extractvalue { i32, i32, i32, i32 } %118, 1, !dbg !40
+  %287 = bitcast i32 %286 to <2 x bfloat>, !dbg !40
+  %288 = extractvalue { i32, i32, i32, i32 } %118, 2, !dbg !40
+  %289 = bitcast i32 %288 to <2 x bfloat>, !dbg !40
+  %290 = extractvalue { i32, i32, i32, i32 } %118, 3, !dbg !40
+  %291 = bitcast i32 %290 to <2 x bfloat>, !dbg !40
+  %292 = getelementptr bfloat, ptr addrspace(1) %189, i64 %116, !dbg !52
+  %293 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];", "=r,=r,=r,=r,l,b"(ptr addrspace(1) %292, i1 %23) #5, !dbg !53
+  %294 = extractvalue { i32, i32, i32, i32 } %293, 0, !dbg !53
+  %295 = bitcast i32 %294 to <2 x bfloat>, !dbg !53
+  %296 = extractvalue { i32, i32, i32, i32 } %293, 1, !dbg !53
+  %297 = bitcast i32 %296 to <2 x bfloat>, !dbg !53
+  %298 = extractvalue { i32, i32, i32, i32 } %293, 2, !dbg !53
+  %299 = bitcast i32 %298 to <2 x bfloat>, !dbg !53
+  %300 = extractvalue { i32, i32, i32, i32 } %293, 3, !dbg !53
+  %301 = bitcast i32 %300 to <2 x bfloat>, !dbg !53
+  %302 = shl i32 %24, 7, !dbg !54
+  %303 = add i32 %302, %.decomposed, !dbg !55
+  %304 = sext i32 %303 to i64, !dbg !56
+  %305 = getelementptr bfloat, ptr addrspace(1) %5, i64 %304, !dbg !56
+  %306 = fpext <2 x bfloat> %267 to <2 x float>, !dbg !57
+  %307 = insertelement <2 x float> poison, float %.0.i, i64 0, !dbg !58
+  %308 = insertelement <2 x float> %307, float %.0.i3, i64 1, !dbg !58
+  %309 = fmul <2 x float> %308, %306, !dbg !58
+  %310 = fpext <2 x bfloat> %269 to <2 x float>, !dbg !59
+  %311 = fmul <2 x float> %309, %310, !dbg !60
+  %312 = fpext <2 x bfloat> %271 to <2 x float>, !dbg !61
+  %313 = fmul <2 x float> %311, %312, !dbg !62
+  %314 = fpext <2 x bfloat> %274 to <2 x float>, !dbg !63
+  %315 = fpext <2 x bfloat> %285 to <2 x float>, !dbg !64
+  %316 = insertelement <2 x float> poison, float %.0.i24, i64 0, !dbg !65
+  %317 = insertelement <2 x float> %316, float %.0.i27, i64 1, !dbg !65
+  %318 = fmul <2 x float> %317, %314, !dbg !65
+  %319 = fmul <2 x float> %318, %315, !dbg !66
+  %320 = fpext <2 x bfloat> %295 to <2 x float>, !dbg !67
+  %321 = fmul <2 x float> %319, %320, !dbg !68
+  %322 = fsub <2 x float> %313, %321, !dbg !69
+  %323 = fptrunc <2 x float> %322 to <2 x bfloat>, !dbg !70
+  %324 = fpext <2 x bfloat> %261 to <2 x float>, !dbg !57
+  %325 = insertelement <2 x float> poison, float %.0.i6, i64 0, !dbg !58
+  %326 = insertelement <2 x float> %325, float %.0.i9, i64 1, !dbg !58
+  %327 = fmul <2 x float> %326, %324, !dbg !58
+  %328 = fpext <2 x bfloat> %263 to <2 x float>, !dbg !59
+  %329 = fmul <2 x float> %327, %328, !dbg !60
+  %330 = fpext <2 x bfloat> %265 to <2 x float>, !dbg !61
+  %331 = fmul <2 x float> %329, %330, !dbg !62
+  %332 = fpext <2 x bfloat> %277 to <2 x float>, !dbg !63
+  %333 = fpext <2 x bfloat> %287 to <2 x float>, !dbg !64
+  %334 = insertelement <2 x float> poison, float %.0.i30, i64 0, !dbg !65
+  %335 = insertelement <2 x float> %334, float %.0.i33, i64 1, !dbg !65
+  %336 = fmul <2 x float> %335, %332, !dbg !65
+  %337 = fmul <2 x float> %336, %333, !dbg !66
+  %338 = fpext <2 x bfloat> %297 to <2 x float>, !dbg !67
+  %339 = fmul <2 x float> %337, %338, !dbg !68
+  %340 = fsub <2 x float> %331, %339, !dbg !69
+  %341 = fptrunc <2 x float> %340 to <2 x bfloat>, !dbg !70
+  %342 = fpext <2 x bfloat> %255 to <2 x float>, !dbg !57
+  %343 = insertelement <2 x float> poison, float %.0.i12, i64 0, !dbg !58
+  %344 = insertelement <2 x float> %343, float %.0.i15, i64 1, !dbg !58
+  %345 = fmul <2 x float> %344, %342, !dbg !58
+  %346 = fpext <2 x bfloat> %257 to <2 x float>, !dbg !59
+  %347 = fmul <2 x float> %345, %346, !dbg !60
+  %348 = fpext <2 x bfloat> %259 to <2 x float>, !dbg !61
+  %349 = fmul <2 x float> %347, %348, !dbg !62
+  %350 = fpext <2 x bfloat> %280 to <2 x float>, !dbg !63
+  %351 = fpext <2 x bfloat> %289 to <2 x float>, !dbg !64
+  %352 = insertelement <2 x float> poison, float %.0.i36, i64 0, !dbg !65
+  %353 = insertelement <2 x float> %352, float %.0.i39, i64 1, !dbg !65
+  %354 = fmul <2 x float> %353, %350, !dbg !65
+  %355 = fmul <2 x float> %354, %351, !dbg !66
+  %356 = fpext <2 x bfloat> %299 to <2 x float>, !dbg !67
+  %357 = fmul <2 x float> %355, %356, !dbg !68
+  %358 = fsub <2 x float> %349, %357, !dbg !69
+  %359 = fptrunc <2 x float> %358 to <2 x bfloat>, !dbg !70
+  %360 = fpext <2 x bfloat> %249 to <2 x float>, !dbg !57
+  %361 = insertelement <2 x float> poison, float %.0.i18, i64 0, !dbg !58
+  %362 = insertelement <2 x float> %361, float %.0.i21, i64 1, !dbg !58
+  %363 = fmul <2 x float> %362, %360, !dbg !58
+  %364 = fpext <2 x bfloat> %251 to <2 x float>, !dbg !59
+  %365 = fmul <2 x float> %363, %364, !dbg !60
+  %366 = fpext <2 x bfloat> %253 to <2 x float>, !dbg !61
+  %367 = fmul <2 x float> %365, %366, !dbg !62
+  %368 = fpext <2 x bfloat> %283 to <2 x float>, !dbg !63
+  %369 = fpext <2 x bfloat> %291 to <2 x float>, !dbg !64
+  %370 = insertelement <2 x float> poison, float %.0.i42, i64 0, !dbg !65
+  %371 = insertelement <2 x float> %370, float %.0.i45, i64 1, !dbg !65
+  %372 = fmul <2 x float> %371, %368, !dbg !65
+  %373 = fmul <2 x float> %372, %369, !dbg !66
+  %374 = fpext <2 x bfloat> %301 to <2 x float>, !dbg !67
+  %375 = fmul <2 x float> %373, %374, !dbg !68
+  %376 = fsub <2 x float> %367, %375, !dbg !69
+  %377 = fptrunc <2 x float> %376 to <2 x bfloat>, !dbg !70
+  %378 = bitcast <2 x bfloat> %323 to i32, !dbg !70
+  %379 = bitcast <2 x bfloat> %341 to i32, !dbg !70
+  %380 = bitcast <2 x bfloat> %359 to i32, !dbg !70
+  %381 = bitcast <2 x bfloat> %377 to i32, !dbg !70
+  tail call void asm sideeffect "@$5 st.global.v4.b32 [ $4 + 0 ], { $0, $1, $2, $3 };", "r,r,r,r,l,b"(i32 %378, i32 %379, i32 %380, i32 %381, ptr addrspace(1) %305, i1 %23) #5, !dbg !70
+  %382 = getelementptr bfloat, ptr addrspace(1) %6, i64 %304, !dbg !71
+  %383 = fmul <2 x float> %319, %312, !dbg !72
+  %384 = fmul <2 x float> %311, %320, !dbg !73
+  %385 = fadd <2 x float> %383, %384, !dbg !74
+  %386 = fptrunc <2 x float> %385 to <2 x bfloat>, !dbg !75
+  %387 = fmul <2 x float> %337, %330, !dbg !72
+  %388 = fmul <2 x float> %329, %338, !dbg !73
+  %389 = fadd <2 x float> %387, %388, !dbg !74
+  %390 = fptrunc <2 x float> %389 to <2 x bfloat>, !dbg !75
+  %391 = fmul <2 x float> %355, %348, !dbg !72
+  %392 = fmul <2 x float> %347, %356, !dbg !73
+  %393 = fadd <2 x float> %391, %392, !dbg !74
+  %394 = fptrunc <2 x float> %393 to <2 x bfloat>, !dbg !75
+  %395 = fmul <2 x float> %373, %366, !dbg !72
+  %396 = fmul <2 x float> %365, %374, !dbg !73
+  %397 = fadd <2 x float> %395, %396, !dbg !74
+  %398 = fptrunc <2 x float> %397 to <2 x bfloat>, !dbg !75
+  %399 = bitcast <2 x bfloat> %386 to i32, !dbg !75
+  %400 = bitcast <2 x bfloat> %390 to i32, !dbg !75
+  %401 = bitcast <2 x bfloat> %394 to i32, !dbg !75
+  %402 = bitcast <2 x bfloat> %398 to i32, !dbg !75
+  tail call void asm sideeffect "@$5 st.global.v4.b32 [ $4 + 0 ], { $0, $1, $2, $3 };", "r,r,r,r,l,b"(i32 %399, i32 %400, i32 %401, i32 %402, ptr addrspace(1) %382, i1 %23) #5, !dbg !75
+  ret void, !dbg !76
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.ctaid.x() #1
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.x() #1
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
+declare float @llvm.nvvm.div.full(float, float) #2
+
+; Function Attrs: convergent nocallback nounwind
+declare void @llvm.nvvm.barrier0() #3
+
+declare i32 @__nvvm_reflect(ptr) local_unnamed_addr #4
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
+declare float @llvm.nvvm.rsqrt.approx.ftz.f(float) #2
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
+declare float @llvm.nvvm.rsqrt.approx.f(float) #2
+
+attributes #0 = { noreturn }
+attributes #1 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #2 = { mustprogress nocallback nofree nosync nounwind willreturn memory(none) }
+attributes #3 = { convergent nocallback nounwind }
+attributes #4 = { "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #5 = { nounwind }
+
+!llvm.module.flags = !{!0, !1}
+!llvm.dbg.cu = !{!2}
+!nvvm.annotations = !{!4}
+!llvm.ident = !{!5}
+
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = !{i32 4, !"nvvm-reflect-ftz", i32 1}
+!2 = distinct !DICompileUnit(language: DW_LANG_C, file: !3, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: LineTablesOnly)
+!3 = !DIFile(filename: "cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py", directory: "/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng")
+!4 = !{ptr @triton_poi_fused_add_mul_sub_6, !"reqntidx", i32 128}
+!5 = !{!"clang version 3.8.0 (tags/RELEASE_380/final)"}
+!6 = !DISubprogram(name: "__assertfail", linkageName: "__assertfail", scope: !7, file: !7, type: !8, spFlags: DISPFlagOptimized)
+!7 = !DIFile(filename: "<unknown>", directory: "")
+!8 = !DISubroutineType(cc: DW_CC_normal, types: !9)
+!9 = !{}
+!10 = distinct !DISubprogram(name: "triton_poi_fused_add_mul_sub_6", linkageName: "triton_poi_fused_add_mul_sub_6", scope: !3, file: !3, line: 18, type: !8, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !2)
+!11 = !DILocation(line: 19, column: 28, scope: !10)
+!12 = !DILocation(line: 19, column: 33, scope: !10)
+!13 = !DILocation(line: 20, column: 36, scope: !10)
+!14 = !DILocation(line: 20, column: 23, scope: !10)
+!15 = !DILocation(line: 21, column: 21, scope: !10)
+!16 = !DILocation(line: 23, column: 21, scope: !10)
+!17 = !DILocation(line: 22, column: 19, scope: !10)
+!18 = !DILocation(line: 23, column: 27, scope: !10)
+!19 = !DILocation(line: 24, column: 19, scope: !10)
+!20 = !DILocation(line: 26, column: 46, scope: !10)
+!21 = !DILocation(line: 26, column: 56, scope: !10)
+!22 = !DILocation(line: 26, column: 37, scope: !10)
+!23 = !DILocation(line: 26, column: 42, scope: !10)
+!24 = !DILocation(line: 26, column: 51, scope: !10)
+!25 = !DILocation(line: 26, column: 30, scope: !10)
+!26 = !DILocation(line: 26, column: 61, scope: !10)
+!27 = !DILocation(line: 27, column: 30, scope: !10)
+!28 = !DILocation(line: 27, column: 35, scope: !10)
+!29 = !DILocation(line: 28, column: 31, scope: !10)
+!30 = !DILocation(line: 28, column: 36, scope: !10)
+!31 = !DILocation(line: 29, column: 31, scope: !10)
+!32 = !DILocation(line: 29, column: 36, scope: !10)
+!33 = !DILocation(line: 30, column: 63, scope: !10)
+!34 = !DILocation(line: 30, column: 43, scope: !10)
+!35 = !DILocation(line: 30, column: 77, scope: !10)
+!36 = !DILocation(line: 30, column: 31, scope: !10)
+!37 = !DILocation(line: 30, column: 87, scope: !10)
+!38 = !DILocation(line: 31, column: 57, scope: !10)
+!39 = !DILocation(line: 32, column: 31, scope: !10)
+!40 = !DILocation(line: 32, column: 41, scope: !10)
+!41 = !DILocation(line: 35, column: 19, scope: !10)
+!42 = !DILocation(line: 37, column: 18, scope: !10)
+!43 = !DILocation(line: 38, column: 27, scope: !10)
+!44 = !DILocation(line: 45, column: 35, scope: !10)
+!45 = !DILocation(line: 46, column: 38, scope: !10)
+!46 = !DILocation(line: 46, column: 67, scope: !10)
+!47 = !DILocation(line: 47, column: 31, scope: !10)
+!48 = !DILocation(line: 47, column: 48, scope: !10)
+!49 = !DILocation(line: 50, column: 21, scope: !10)
+!50 = !DILocation(line: 51, column: 20, scope: !10)
+!51 = !DILocation(line: 52, column: 28, scope: !10)
+!52 = !DILocation(line: 56, column: 31, scope: !10)
+!53 = !DILocation(line: 56, column: 53, scope: !10)
+!54 = !DILocation(line: 62, column: 34, scope: !10)
+!55 = !DILocation(line: 62, column: 30, scope: !10)
+!56 = !DILocation(line: 62, column: 25, scope: !10)
+!57 = !DILocation(line: 26, column: 71, scope: !10)
+!58 = !DILocation(line: 39, column: 18, scope: !10)
+!59 = !DILocation(line: 28, column: 76, scope: !10)
+!60 = !DILocation(line: 41, column: 19, scope: !10)
+!61 = !DILocation(line: 47, column: 58, scope: !10)
+!62 = !DILocation(line: 48, column: 20, scope: !10)
+!63 = !DILocation(line: 30, column: 97, scope: !10)
+!64 = !DILocation(line: 32, column: 81, scope: !10)
+!65 = !DILocation(line: 53, column: 20, scope: !10)
+!66 = !DILocation(line: 55, column: 20, scope: !10)
+!67 = !DILocation(line: 56, column: 63, scope: !10)
+!68 = !DILocation(line: 57, column: 20, scope: !10)
+!69 = !DILocation(line: 58, column: 20, scope: !10)
+!70 = !DILocation(line: 62, column: 46, scope: !10)
+!71 = !DILocation(line: 63, column: 25, scope: !10)
+!72 = !DILocation(line: 59, column: 20, scope: !10)
+!73 = !DILocation(line: 60, column: 20, scope: !10)
+!74 = !DILocation(line: 61, column: 20, scope: !10)
+!75 = !DILocation(line: 63, column: 46, scope: !10)
+!76 = !DILocation(line: 63, column: 4, scope: !10)

platform/aiml/models/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/GYVDTKQVTOVBT7EHBNWUFZYSRBLO4IMUH537TRFNX6DB3IREUQ2A/triton_poi_fused_add_mul_sub_6.ttgir

@@ -0,0 +1,196 @@
+#blocked = #ttg.blocked<{sizePerThread = [8], threadsPerWarp = [32], warpsPerCTA = [4], order = [0]}>
+#loc = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":18:0)
+module attributes {"ttg.num-ctas" = 1 : i32, "ttg.num-warps" = 4 : i32, ttg.target = "cuda:90", "ttg.threads-per-warp" = 32 : i32} {
+  tt.func public @triton_poi_fused_add_mul_sub_6(%arg0: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":18:0), %arg1: !tt.ptr<f32> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":18:0), %arg2: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":18:0), %arg3: !tt.ptr<i64> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":18:0), %arg4: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":18:0), %arg5: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":18:0), %arg6: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":18:0), %arg7: i32 {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":18:0)) attributes {noinline = false} {
+    %cst = arith.constant dense<1.280000e+02> : tensor<1024xf32, #blocked> loc(#loc1)
+    %cst_0 = arith.constant dense<9.99999997E-7> : tensor<1024xf32, #blocked> loc(#loc1)
+    %cst_1 = arith.constant dense<128> : tensor<1024xi64, #blocked> loc(#loc1)
+    %cst_2 = arith.constant dense<131072> : tensor<1024xi64, #blocked> loc(#loc1)
+    %cst_3 = arith.constant dense<0> : tensor<1024xi64, #blocked> loc(#loc1)
+    %c1024_i32 = arith.constant 1024 : i32 loc(#loc1)
+    %cst_4 = arith.constant dense<64> : tensor<1024xi32, #blocked> loc(#loc1)
+    %cst_5 = arith.constant dense<8> : tensor<1024xi32, #blocked> loc(#loc1)
+    %cst_6 = arith.constant dense<512> : tensor<1024xi32, #blocked> loc(#loc1)
+    %cst_7 = arith.constant dense<5120> : tensor<1024xi32, #blocked> loc(#loc1)
+    %cst_8 = arith.constant dense<128> : tensor<1024xi32, #blocked> loc(#loc1)
+    %cst_9 = arith.constant dense<7168> : tensor<1024xi32, #blocked> loc(#loc1)
+    %cst_10 = arith.constant dense<5184> : tensor<1024xi32, #blocked> loc(#loc1)
+    %cst_11 = arith.constant dense<true> : tensor<1024xi1, #blocked> loc(#loc1)
+    %0 = tt.get_program_id x : i32 loc(#loc2)
+    %1 = arith.muli %0, %c1024_i32 : i32 loc(#loc3)
+    %2 = tt.make_range {end = 1024 : i32, start = 0 : i32} : tensor<1024xi32, #blocked> loc(#loc4)
+    %3 = tt.splat %1 : i32 -> tensor<1024xi32, #blocked> loc(#loc5)
+    %4 = arith.addi %3, %2 : tensor<1024xi32, #blocked> loc(#loc5)
+    %5 = tt.splat %arg7 : i32 -> tensor<1024xi32, #blocked> loc(#loc6)
+    %6 = arith.cmpi slt, %4, %5 : tensor<1024xi32, #blocked> loc(#loc6)
+    %7 = arith.remsi %4, %cst_4 : tensor<1024xi32, #blocked> loc(#loc7)
+    %8 = arith.divsi %4, %cst_4 : tensor<1024xi32, #blocked> loc(#loc8)
+    %9 = arith.remsi %8, %cst_5 : tensor<1024xi32, #blocked> loc(#loc9)
+    %10 = arith.divsi %4, %cst_6 : tensor<1024xi32, #blocked> loc(#loc10)
+    %11 = arith.addi %7, %cst_7 : tensor<1024xi32, #blocked> loc(#loc11)
+    %12 = arith.muli %9, %cst_8 : tensor<1024xi32, #blocked> loc(#loc12)
+    %13 = arith.addi %11, %12 : tensor<1024xi32, #blocked> loc(#loc13)
+    %14 = arith.muli %10, %cst_9 : tensor<1024xi32, #blocked> loc(#loc14)
+    %15 = arith.addi %13, %14 : tensor<1024xi32, #blocked> loc(#loc15)
+    %16 = tt.splat %arg0 : !tt.ptr<bf16> -> tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc16)
+    %17 = tt.addptr %16, %15 : tensor<1024x!tt.ptr<bf16>, #blocked>, tensor<1024xi32, #blocked> loc(#loc16)
+    %18 = tt.load %17, %6 : tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc17)
+    %19 = arith.extf %18 : tensor<1024xbf16, #blocked> to tensor<1024xf32, #blocked> loc(#loc18)
+    %20 = tt.splat %arg1 : !tt.ptr<f32> -> tensor<1024x!tt.ptr<f32>, #blocked> loc(#loc19)
+    %21 = tt.addptr %20, %8 : tensor<1024x!tt.ptr<f32>, #blocked>, tensor<1024xi32, #blocked> loc(#loc19)
+    %22 = tt.load %21, %6 evictionPolicy = evict_last : tensor<1024x!tt.ptr<f32>, #blocked> loc(#loc20)
+    %23 = tt.splat %arg2 : !tt.ptr<bf16> -> tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc21)
+    %24 = tt.addptr %23, %7 : tensor<1024x!tt.ptr<bf16>, #blocked>, tensor<1024xi32, #blocked> loc(#loc21)
+    %25 = tt.load %24, %6 evictionPolicy = evict_last : tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc22)
+    %26 = arith.extf %25 : tensor<1024xbf16, #blocked> to tensor<1024xf32, #blocked> loc(#loc23)
+    %27 = tt.splat %arg3 : !tt.ptr<i64> -> tensor<1024x!tt.ptr<i64>, #blocked> loc(#loc24)
+    %28 = tt.addptr %27, %10 : tensor<1024x!tt.ptr<i64>, #blocked>, tensor<1024xi32, #blocked> loc(#loc24)
+    %29 = tt.load %28, %6 evictionPolicy = evict_last : tensor<1024x!tt.ptr<i64>, #blocked> loc(#loc25)
+    %30 = arith.addi %7, %cst_10 : tensor<1024xi32, #blocked> loc(#loc26)
+    %31 = arith.addi %30, %12 : tensor<1024xi32, #blocked> loc(#loc27)
+    %32 = arith.addi %7, %cst_4 : tensor<1024xi32, #blocked> loc(#loc28)
+    %33 = arith.divsi %32, %cst_8 : tensor<1024xi32, #blocked> loc(#loc29)
+    %34 = arith.muli %33, %cst_8 : tensor<1024xi32, #blocked> loc(#loc30)
+    %35 = arith.addi %31, %34 : tensor<1024xi32, #blocked> loc(#loc31)
+    %36 = arith.addi %35, %14 : tensor<1024xi32, #blocked> loc(#loc32)
+    %37 = tt.addptr %16, %36 : tensor<1024x!tt.ptr<bf16>, #blocked>, tensor<1024xi32, #blocked> loc(#loc33)
+    %38 = tt.load %37, %6 : tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc34)
+    %39 = arith.extf %38 : tensor<1024xbf16, #blocked> to tensor<1024xf32, #blocked> loc(#loc35)
+    %40 = arith.addi %8, %33 : tensor<1024xi32, #blocked> loc(#loc36)
+    %41 = tt.addptr %20, %40 : tensor<1024x!tt.ptr<f32>, #blocked>, tensor<1024xi32, #blocked> loc(#loc37)
+    %42 = tt.load %41, %6 evictionPolicy = evict_last : tensor<1024x!tt.ptr<f32>, #blocked> loc(#loc38)
+    %43 = tt.addptr %23, %32 : tensor<1024x!tt.ptr<bf16>, #blocked>, tensor<1024xi32, #blocked> loc(#loc39)
+    %44 = tt.load %43, %6 evictionPolicy = evict_last : tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc40)
+    %45 = arith.extf %44 : tensor<1024xbf16, #blocked> to tensor<1024xf32, #blocked> loc(#loc41)
+    %46 = arith.divf %22, %cst : tensor<1024xf32, #blocked> loc(#loc42)
+    %47 = arith.addf %46, %cst_0 : tensor<1024xf32, #blocked> loc(#loc43)
+    %48 = tt.extern_elementwise %47 {libname = "", libpath = "", pure = true, symbol = "__nv_rsqrtf"} : (tensor<1024xf32, #blocked>) -> tensor<1024xf32, #blocked> loc(#loc44)
+    %49 = arith.mulf %19, %48 : tensor<1024xf32, #blocked> loc(#loc45)
+    %50 = arith.mulf %49, %26 : tensor<1024xf32, #blocked> loc(#loc46)
+    %51 = arith.addi %29, %cst_2 : tensor<1024xi64, #blocked> loc(#loc47)
+    %52 = arith.cmpi slt, %29, %cst_3 : tensor<1024xi64, #blocked> loc(#loc48)
+    %53 = arith.select %52, %51, %29 : tensor<1024xi1, #blocked>, tensor<1024xi64, #blocked> loc(#loc49)
+    %54 = arith.cmpi sge, %53, %cst_3 : tensor<1024xi64, #blocked> loc(#loc50)
+    %55 = arith.cmpi slt, %53, %cst_2 : tensor<1024xi64, #blocked> loc(#loc51)
+    %56 = arith.andi %54, %55 : tensor<1024xi1, #blocked> loc(#loc52)
+    %57 = arith.xori %6, %cst_11 : tensor<1024xi1, #blocked> loc(#loc53)
+    %58 = arith.ori %56, %57 : tensor<1024xi1, #blocked> loc(#loc54)
+    tt.assert %58, "index out of bounds: 0 <= tmp16 < 131072" : tensor<1024xi1, #blocked> loc(#loc55)
+    %59 = arith.muli %53, %cst_1 : tensor<1024xi64, #blocked> loc(#loc56)
+    %60 = arith.extsi %7 : tensor<1024xi32, #blocked> to tensor<1024xi64, #blocked> loc(#loc57)
+    %61 = arith.addi %60, %59 : tensor<1024xi64, #blocked> loc(#loc57)
+    %62 = tt.splat %arg4 : !tt.ptr<bf16> -> tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc58)
+    %63 = tt.addptr %62, %61 : tensor<1024x!tt.ptr<bf16>, #blocked>, tensor<1024xi64, #blocked> loc(#loc58)
+    %64 = tt.load %63, %6 : tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc59)
+    %65 = arith.extf %64 : tensor<1024xbf16, #blocked> to tensor<1024xf32, #blocked> loc(#loc60)
+    %66 = arith.mulf %50, %65 : tensor<1024xf32, #blocked> loc(#loc61)
+    %67 = arith.divf %42, %cst : tensor<1024xf32, #blocked> loc(#loc62)
+    %68 = arith.addf %67, %cst_0 : tensor<1024xf32, #blocked> loc(#loc63)
+    %69 = tt.extern_elementwise %68 {libname = "", libpath = "", pure = true, symbol = "__nv_rsqrtf"} : (tensor<1024xf32, #blocked>) -> tensor<1024xf32, #blocked> loc(#loc64)
+    %70 = arith.mulf %39, %69 : tensor<1024xf32, #blocked> loc(#loc65)
+    %71 = arith.mulf %70, %45 : tensor<1024xf32, #blocked> loc(#loc66)
+    %72 = arith.extsi %32 : tensor<1024xi32, #blocked> to tensor<1024xi64, #blocked> loc(#loc67)
+    %73 = arith.addi %72, %59 : tensor<1024xi64, #blocked> loc(#loc67)
+    %74 = tt.addptr %62, %73 : tensor<1024x!tt.ptr<bf16>, #blocked>, tensor<1024xi64, #blocked> loc(#loc68)
+    %75 = tt.load %74, %6 : tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc69)
+    %76 = arith.extf %75 : tensor<1024xbf16, #blocked> to tensor<1024xf32, #blocked> loc(#loc70)
+    %77 = arith.mulf %71, %76 : tensor<1024xf32, #blocked> loc(#loc71)
+    %78 = arith.subf %66, %77 : tensor<1024xf32, #blocked> loc(#loc72)
+    %79 = arith.mulf %71, %65 : tensor<1024xf32, #blocked> loc(#loc73)
+    %80 = arith.mulf %50, %76 : tensor<1024xf32, #blocked> loc(#loc74)
+    %81 = arith.addf %79, %80 : tensor<1024xf32, #blocked> loc(#loc75)
+    %82 = arith.muli %8, %cst_8 : tensor<1024xi32, #blocked> loc(#loc76)
+    %83 = arith.addi %7, %82 : tensor<1024xi32, #blocked> loc(#loc77)
+    %84 = tt.splat %arg5 : !tt.ptr<bf16> -> tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc78)
+    %85 = tt.addptr %84, %83 : tensor<1024x!tt.ptr<bf16>, #blocked>, tensor<1024xi32, #blocked> loc(#loc78)
+    %86 = arith.truncf %78 : tensor<1024xf32, #blocked> to tensor<1024xbf16, #blocked> loc(#loc79)
+    tt.store %85, %86, %6 : tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc79)
+    %87 = tt.splat %arg6 : !tt.ptr<bf16> -> tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc80)
+    %88 = tt.addptr %87, %83 : tensor<1024x!tt.ptr<bf16>, #blocked>, tensor<1024xi32, #blocked> loc(#loc80)
+    %89 = arith.truncf %81 : tensor<1024xf32, #blocked> to tensor<1024xbf16, #blocked> loc(#loc81)
+    tt.store %88, %89, %6 : tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc81)
+    tt.return loc(#loc82)
+  } loc(#loc)
+} loc(#loc)
+#loc1 = loc(unknown)
+#loc2 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":19:28)
+#loc3 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":19:33)
+#loc4 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":20:36)
+#loc5 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":20:23)
+#loc6 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":21:21)
+#loc7 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":22:19)
+#loc8 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":23:21)
+#loc9 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":23:27)
+#loc10 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":24:19)
+#loc11 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":26:37)
+#loc12 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":26:46)
+#loc13 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":26:42)
+#loc14 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":26:56)
+#loc15 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":26:51)
+#loc16 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":26:30)
+#loc17 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":26:61)
+#loc18 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":26:71)
+#loc19 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":27:30)
+#loc20 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":27:35)
+#loc21 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":28:31)
+#loc22 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":28:36)
+#loc23 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":28:76)
+#loc24 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":29:31)
+#loc25 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":29:36)
+#loc26 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":30:38)
+#loc27 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":30:43)
+#loc28 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":30:63)
+#loc29 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":30:70)
+#loc30 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":30:57)
+#loc31 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":30:52)
+#loc32 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":30:77)
+#loc33 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":30:31)
+#loc34 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":30:87)
+#loc35 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":30:97)
+#loc36 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":31:37)
+#loc37 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":31:31)
+#loc38 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":31:57)
+#loc39 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":32:31)
+#loc40 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":32:41)
+#loc41 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":32:81)
+#loc42 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":35:19)
+#loc43 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":37:18)
+#loc44 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":38:27)
+#loc45 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":39:18)
+#loc46 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":41:19)
+#loc47 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":43:20)
+#loc48 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":44:20)
+#loc49 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":45:35)
+#loc50 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":46:28)
+#loc51 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":46:46)
+#loc52 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":46:38)
+#loc53 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":46:59)
+#loc54 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":46:57)
+#loc55 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":46:67)
+#loc56 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":47:40)
+#loc57 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":47:36)
+#loc58 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":47:31)
+#loc59 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":47:48)
+#loc60 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":47:58)
+#loc61 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":48:20)
+#loc62 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":50:21)
+#loc63 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":51:20)
+#loc64 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":52:28)
+#loc65 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":53:20)
+#loc66 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":55:20)
+#loc67 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":56:41)
+#loc68 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":56:31)
+#loc69 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":56:53)
+#loc70 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":56:63)
+#loc71 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":57:20)
+#loc72 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":58:20)
+#loc73 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":59:20)
+#loc74 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":60:20)
+#loc75 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":61:20)
+#loc76 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":62:34)
+#loc77 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":62:30)
+#loc78 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":62:25)
+#loc79 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":62:46)
+#loc80 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":63:25)
+#loc81 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":63:46)
+#loc82 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":63:4)

platform/aiml/models/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/GYVDTKQVTOVBT7EHBNWUFZYSRBLO4IMUH537TRFNX6DB3IREUQ2A/triton_poi_fused_add_mul_sub_6.ttir

@@ -0,0 +1,195 @@
+#loc = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":18:0)
+module {
+  tt.func public @triton_poi_fused_add_mul_sub_6(%arg0: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":18:0), %arg1: !tt.ptr<f32> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":18:0), %arg2: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":18:0), %arg3: !tt.ptr<i64> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":18:0), %arg4: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":18:0), %arg5: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":18:0), %arg6: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":18:0), %arg7: i32 {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":18:0)) attributes {noinline = false} {
+    %cst = arith.constant dense<0> : tensor<1024xi64> loc(#loc1)
+    %cst_0 = arith.constant dense<131072> : tensor<1024xi64> loc(#loc1)
+    %cst_1 = arith.constant dense<128> : tensor<1024xi64> loc(#loc1)
+    %cst_2 = arith.constant dense<true> : tensor<1024xi1> loc(#loc1)
+    %cst_3 = arith.constant dense<9.99999997E-7> : tensor<1024xf32> loc(#loc1)
+    %cst_4 = arith.constant dense<1.280000e+02> : tensor<1024xf32> loc(#loc1)
+    %cst_5 = arith.constant dense<5184> : tensor<1024xi32> loc(#loc1)
+    %cst_6 = arith.constant dense<7168> : tensor<1024xi32> loc(#loc1)
+    %cst_7 = arith.constant dense<128> : tensor<1024xi32> loc(#loc1)
+    %cst_8 = arith.constant dense<5120> : tensor<1024xi32> loc(#loc1)
+    %cst_9 = arith.constant dense<512> : tensor<1024xi32> loc(#loc1)
+    %cst_10 = arith.constant dense<8> : tensor<1024xi32> loc(#loc1)
+    %cst_11 = arith.constant dense<64> : tensor<1024xi32> loc(#loc1)
+    %c1024_i32 = arith.constant 1024 : i32 loc(#loc1)
+    %0 = tt.get_program_id x : i32 loc(#loc2)
+    %1 = arith.muli %0, %c1024_i32 : i32 loc(#loc3)
+    %2 = tt.make_range {end = 1024 : i32, start = 0 : i32} : tensor<1024xi32> loc(#loc4)
+    %3 = tt.splat %1 : i32 -> tensor<1024xi32> loc(#loc5)
+    %4 = arith.addi %3, %2 : tensor<1024xi32> loc(#loc5)
+    %5 = tt.splat %arg7 : i32 -> tensor<1024xi32> loc(#loc6)
+    %6 = arith.cmpi slt, %4, %5 : tensor<1024xi32> loc(#loc6)
+    %7 = arith.remsi %4, %cst_11 : tensor<1024xi32> loc(#loc7)
+    %8 = arith.divsi %4, %cst_11 : tensor<1024xi32> loc(#loc8)
+    %9 = arith.remsi %8, %cst_10 : tensor<1024xi32> loc(#loc9)
+    %10 = arith.divsi %4, %cst_9 : tensor<1024xi32> loc(#loc10)
+    %11 = arith.addi %7, %cst_8 : tensor<1024xi32> loc(#loc11)
+    %12 = arith.muli %9, %cst_7 : tensor<1024xi32> loc(#loc12)
+    %13 = arith.addi %11, %12 : tensor<1024xi32> loc(#loc13)
+    %14 = arith.muli %10, %cst_6 : tensor<1024xi32> loc(#loc14)
+    %15 = arith.addi %13, %14 : tensor<1024xi32> loc(#loc15)
+    %16 = tt.splat %arg0 : !tt.ptr<bf16> -> tensor<1024x!tt.ptr<bf16>> loc(#loc16)
+    %17 = tt.addptr %16, %15 : tensor<1024x!tt.ptr<bf16>>, tensor<1024xi32> loc(#loc16)
+    %18 = tt.load %17, %6 : tensor<1024x!tt.ptr<bf16>> loc(#loc17)
+    %19 = arith.extf %18 : tensor<1024xbf16> to tensor<1024xf32> loc(#loc18)
+    %20 = tt.splat %arg1 : !tt.ptr<f32> -> tensor<1024x!tt.ptr<f32>> loc(#loc19)
+    %21 = tt.addptr %20, %8 : tensor<1024x!tt.ptr<f32>>, tensor<1024xi32> loc(#loc19)
+    %22 = tt.load %21, %6 evictionPolicy = evict_last : tensor<1024x!tt.ptr<f32>> loc(#loc20)
+    %23 = tt.splat %arg2 : !tt.ptr<bf16> -> tensor<1024x!tt.ptr<bf16>> loc(#loc21)
+    %24 = tt.addptr %23, %7 : tensor<1024x!tt.ptr<bf16>>, tensor<1024xi32> loc(#loc21)
+    %25 = tt.load %24, %6 evictionPolicy = evict_last : tensor<1024x!tt.ptr<bf16>> loc(#loc22)
+    %26 = arith.extf %25 : tensor<1024xbf16> to tensor<1024xf32> loc(#loc23)
+    %27 = tt.splat %arg3 : !tt.ptr<i64> -> tensor<1024x!tt.ptr<i64>> loc(#loc24)
+    %28 = tt.addptr %27, %10 : tensor<1024x!tt.ptr<i64>>, tensor<1024xi32> loc(#loc24)
+    %29 = tt.load %28, %6 evictionPolicy = evict_last : tensor<1024x!tt.ptr<i64>> loc(#loc25)
+    %30 = arith.addi %7, %cst_5 : tensor<1024xi32> loc(#loc26)
+    %31 = arith.addi %30, %12 : tensor<1024xi32> loc(#loc27)
+    %32 = arith.addi %7, %cst_11 : tensor<1024xi32> loc(#loc28)
+    %33 = arith.divsi %32, %cst_7 : tensor<1024xi32> loc(#loc29)
+    %34 = arith.muli %33, %cst_7 : tensor<1024xi32> loc(#loc30)
+    %35 = arith.addi %31, %34 : tensor<1024xi32> loc(#loc31)
+    %36 = arith.addi %35, %14 : tensor<1024xi32> loc(#loc32)
+    %37 = tt.addptr %16, %36 : tensor<1024x!tt.ptr<bf16>>, tensor<1024xi32> loc(#loc33)
+    %38 = tt.load %37, %6 : tensor<1024x!tt.ptr<bf16>> loc(#loc34)
+    %39 = arith.extf %38 : tensor<1024xbf16> to tensor<1024xf32> loc(#loc35)
+    %40 = arith.addi %8, %33 : tensor<1024xi32> loc(#loc36)
+    %41 = tt.addptr %20, %40 : tensor<1024x!tt.ptr<f32>>, tensor<1024xi32> loc(#loc37)
+    %42 = tt.load %41, %6 evictionPolicy = evict_last : tensor<1024x!tt.ptr<f32>> loc(#loc38)
+    %43 = tt.addptr %23, %32 : tensor<1024x!tt.ptr<bf16>>, tensor<1024xi32> loc(#loc39)
+    %44 = tt.load %43, %6 evictionPolicy = evict_last : tensor<1024x!tt.ptr<bf16>> loc(#loc40)
+    %45 = arith.extf %44 : tensor<1024xbf16> to tensor<1024xf32> loc(#loc41)
+    %46 = arith.divf %22, %cst_4 : tensor<1024xf32> loc(#loc42)
+    %47 = arith.addf %46, %cst_3 : tensor<1024xf32> loc(#loc43)
+    %48 = tt.extern_elementwise %47 {libname = "", libpath = "", pure = true, symbol = "__nv_rsqrtf"} : (tensor<1024xf32>) -> tensor<1024xf32> loc(#loc44)
+    %49 = arith.mulf %19, %48 : tensor<1024xf32> loc(#loc45)
+    %50 = arith.mulf %49, %26 : tensor<1024xf32> loc(#loc46)
+    %51 = arith.addi %29, %cst_0 : tensor<1024xi64> loc(#loc47)
+    %52 = arith.cmpi slt, %29, %cst : tensor<1024xi64> loc(#loc48)
+    %53 = arith.select %52, %51, %29 : tensor<1024xi1>, tensor<1024xi64> loc(#loc49)
+    %54 = arith.cmpi sge, %53, %cst : tensor<1024xi64> loc(#loc50)
+    %55 = arith.cmpi slt, %53, %cst_0 : tensor<1024xi64> loc(#loc51)
+    %56 = arith.andi %54, %55 : tensor<1024xi1> loc(#loc52)
+    %57 = arith.xori %6, %cst_2 : tensor<1024xi1> loc(#loc53)
+    %58 = arith.ori %56, %57 : tensor<1024xi1> loc(#loc54)
+    tt.assert %58, "index out of bounds: 0 <= tmp16 < 131072" : tensor<1024xi1> loc(#loc55)
+    %59 = arith.muli %53, %cst_1 : tensor<1024xi64> loc(#loc56)
+    %60 = arith.extsi %7 : tensor<1024xi32> to tensor<1024xi64> loc(#loc57)
+    %61 = arith.addi %60, %59 : tensor<1024xi64> loc(#loc57)
+    %62 = tt.splat %arg4 : !tt.ptr<bf16> -> tensor<1024x!tt.ptr<bf16>> loc(#loc58)
+    %63 = tt.addptr %62, %61 : tensor<1024x!tt.ptr<bf16>>, tensor<1024xi64> loc(#loc58)
+    %64 = tt.load %63, %6 : tensor<1024x!tt.ptr<bf16>> loc(#loc59)
+    %65 = arith.extf %64 : tensor<1024xbf16> to tensor<1024xf32> loc(#loc60)
+    %66 = arith.mulf %50, %65 : tensor<1024xf32> loc(#loc61)
+    %67 = arith.divf %42, %cst_4 : tensor<1024xf32> loc(#loc62)
+    %68 = arith.addf %67, %cst_3 : tensor<1024xf32> loc(#loc63)
+    %69 = tt.extern_elementwise %68 {libname = "", libpath = "", pure = true, symbol = "__nv_rsqrtf"} : (tensor<1024xf32>) -> tensor<1024xf32> loc(#loc64)
+    %70 = arith.mulf %39, %69 : tensor<1024xf32> loc(#loc65)
+    %71 = arith.mulf %70, %45 : tensor<1024xf32> loc(#loc66)
+    %72 = arith.extsi %32 : tensor<1024xi32> to tensor<1024xi64> loc(#loc67)
+    %73 = arith.addi %72, %59 : tensor<1024xi64> loc(#loc67)
+    %74 = tt.addptr %62, %73 : tensor<1024x!tt.ptr<bf16>>, tensor<1024xi64> loc(#loc68)
+    %75 = tt.load %74, %6 : tensor<1024x!tt.ptr<bf16>> loc(#loc69)
+    %76 = arith.extf %75 : tensor<1024xbf16> to tensor<1024xf32> loc(#loc70)
+    %77 = arith.mulf %71, %76 : tensor<1024xf32> loc(#loc71)
+    %78 = arith.subf %66, %77 : tensor<1024xf32> loc(#loc72)
+    %79 = arith.mulf %71, %65 : tensor<1024xf32> loc(#loc73)
+    %80 = arith.mulf %50, %76 : tensor<1024xf32> loc(#loc74)
+    %81 = arith.addf %79, %80 : tensor<1024xf32> loc(#loc75)
+    %82 = arith.muli %8, %cst_7 : tensor<1024xi32> loc(#loc76)
+    %83 = arith.addi %7, %82 : tensor<1024xi32> loc(#loc77)
+    %84 = tt.splat %arg5 : !tt.ptr<bf16> -> tensor<1024x!tt.ptr<bf16>> loc(#loc78)
+    %85 = tt.addptr %84, %83 : tensor<1024x!tt.ptr<bf16>>, tensor<1024xi32> loc(#loc78)
+    %86 = arith.truncf %78 : tensor<1024xf32> to tensor<1024xbf16> loc(#loc79)
+    tt.store %85, %86, %6 : tensor<1024x!tt.ptr<bf16>> loc(#loc79)
+    %87 = tt.splat %arg6 : !tt.ptr<bf16> -> tensor<1024x!tt.ptr<bf16>> loc(#loc80)
+    %88 = tt.addptr %87, %83 : tensor<1024x!tt.ptr<bf16>>, tensor<1024xi32> loc(#loc80)
+    %89 = arith.truncf %81 : tensor<1024xf32> to tensor<1024xbf16> loc(#loc81)
+    tt.store %88, %89, %6 : tensor<1024x!tt.ptr<bf16>> loc(#loc81)
+    tt.return loc(#loc82)
+  } loc(#loc)
+} loc(#loc)
+#loc1 = loc(unknown)
+#loc2 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":19:28)
+#loc3 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":19:33)
+#loc4 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":20:36)
+#loc5 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":20:23)
+#loc6 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":21:21)
+#loc7 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":22:19)
+#loc8 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":23:21)
+#loc9 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":23:27)
+#loc10 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":24:19)
+#loc11 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":26:37)
+#loc12 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":26:46)
+#loc13 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":26:42)
+#loc14 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":26:56)
+#loc15 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":26:51)
+#loc16 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":26:30)
+#loc17 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":26:61)
+#loc18 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":26:71)
+#loc19 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":27:30)
+#loc20 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":27:35)
+#loc21 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":28:31)
+#loc22 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":28:36)
+#loc23 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":28:76)
+#loc24 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":29:31)
+#loc25 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":29:36)
+#loc26 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":30:38)
+#loc27 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":30:43)
+#loc28 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":30:63)
+#loc29 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":30:70)
+#loc30 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":30:57)
+#loc31 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":30:52)
+#loc32 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":30:77)
+#loc33 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":30:31)
+#loc34 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":30:87)
+#loc35 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":30:97)
+#loc36 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":31:37)
+#loc37 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":31:31)
+#loc38 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":31:57)
+#loc39 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":32:31)
+#loc40 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":32:41)
+#loc41 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":32:81)
+#loc42 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":35:19)
+#loc43 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":37:18)
+#loc44 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":38:27)
+#loc45 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":39:18)
+#loc46 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":41:19)
+#loc47 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":43:20)
+#loc48 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":44:20)
+#loc49 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":45:35)
+#loc50 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":46:28)
+#loc51 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":46:46)
+#loc52 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":46:38)
+#loc53 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":46:59)
+#loc54 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":46:57)
+#loc55 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":46:67)
+#loc56 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":47:40)
+#loc57 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":47:36)
+#loc58 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":47:31)
+#loc59 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":47:48)
+#loc60 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":47:58)
+#loc61 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":48:20)
+#loc62 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":50:21)
+#loc63 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":51:20)
+#loc64 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":52:28)
+#loc65 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":53:20)
+#loc66 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":55:20)
+#loc67 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":56:41)
+#loc68 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":56:31)
+#loc69 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":56:53)
+#loc70 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":56:63)
+#loc71 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":57:20)
+#loc72 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":58:20)
+#loc73 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":59:20)
+#loc74 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":60:20)
+#loc75 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":61:20)
+#loc76 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":62:34)
+#loc77 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":62:30)
+#loc78 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":62:25)
+#loc79 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":62:46)
+#loc80 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":63:25)
+#loc81 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":63:46)
+#loc82 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/ng/cng37hvzs332yaqbafgd3ewbs3ke3rwoclyys2i5n6c2ms7dbuxb.py":63:4)

platform/aiml/models/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/HTZTZWO7H4AVOC4TG2OKIFKB7NJF2F6PKS2P6NWRYNKSL5NSCINQ/__grp__triton_red_fused__to_copy_mean_pow_4.json

@@ -0,0 +1 @@
+{"child_paths": {"triton_red_fused__to_copy_mean_pow_4.ttir": "/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/HTZTZWO7H4AVOC4TG2OKIFKB7NJF2F6PKS2P6NWRYNKSL5NSCINQ/triton_red_fused__to_copy_mean_pow_4.ttir", "triton_red_fused__to_copy_mean_pow_4.ttgir": "/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/HTZTZWO7H4AVOC4TG2OKIFKB7NJF2F6PKS2P6NWRYNKSL5NSCINQ/triton_red_fused__to_copy_mean_pow_4.ttgir", "triton_red_fused__to_copy_mean_pow_4.llir": "/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/HTZTZWO7H4AVOC4TG2OKIFKB7NJF2F6PKS2P6NWRYNKSL5NSCINQ/triton_red_fused__to_copy_mean_pow_4.llir", "triton_red_fused__to_copy_mean_pow_4.ptx": "/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/HTZTZWO7H4AVOC4TG2OKIFKB7NJF2F6PKS2P6NWRYNKSL5NSCINQ/triton_red_fused__to_copy_mean_pow_4.ptx", "triton_red_fused__to_copy_mean_pow_4.cubin": "/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/HTZTZWO7H4AVOC4TG2OKIFKB7NJF2F6PKS2P6NWRYNKSL5NSCINQ/triton_red_fused__to_copy_mean_pow_4.cubin", "triton_red_fused__to_copy_mean_pow_4.json": "/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/HTZTZWO7H4AVOC4TG2OKIFKB7NJF2F6PKS2P6NWRYNKSL5NSCINQ/triton_red_fused__to_copy_mean_pow_4.json"}}

platform/aiml/models/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/HTZTZWO7H4AVOC4TG2OKIFKB7NJF2F6PKS2P6NWRYNKSL5NSCINQ/triton_red_fused__to_copy_mean_pow_4.llir

@@ -0,0 +1,169 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+target datalayout = "e-p3:32:32-p4:32:32-p5:32:32-p6:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64"
+
+@global_smem = external addrspace(3) global [0 x i8], align 16
+
+define ptx_kernel void @triton_red_fused__to_copy_mean_pow_4(ptr addrspace(1) %0, ptr addrspace(1) %1, i32 %2, i32 %3, ptr addrspace(1) readnone captures(none) %4) local_unnamed_addr !dbg !6 {
+  %6 = tail call i32 @llvm.nvvm.read.ptx.sreg.ctaid.x(), !dbg !9
+  %7 = shl i32 %6, 6, !dbg !10
+  %8 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !11
+  %9 = lshr i32 %8, 3, !dbg !11
+  %10 = and i32 %9, 63, !dbg !11
+  %11 = or disjoint i32 %10, %7, !dbg !12
+  %12 = icmp slt i32 %11, %2, !dbg !13
+  %13 = shl i32 %8, 3, !dbg !14
+  %14 = and i32 %13, 56, !dbg !14
+  %15 = sdiv i32 %11, 8, !dbg !15
+  %16 = mul i32 %15, 8, !dbg !16
+  %.decomposed = sub i32 %11, %16, !dbg !16
+  %17 = shl nsw i32 %.decomposed, 7, !dbg !17
+  %18 = mul i32 %15, 7168, !dbg !18
+  %19 = add nsw i32 %17, 5120
+  %20 = add i32 %19, %18
+  %21 = or disjoint i32 %20, %14, !dbg !19
+  %22 = sext i32 %21 to i64, !dbg !20
+  %23 = getelementptr bfloat, ptr addrspace(1) %0, i64 %22, !dbg !20
+  %24 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, $4;\0A\09mov.u32 $1, $5;\0A\09mov.u32 $2, $6;\0A\09mov.u32 $3, $7;\0A\09@$9 ld.global.L1::evict_first.v4.b32 { $0, $1, $2, $3 }, [ $8 + 0 ];", "=r,=r,=r,=r,r,r,r,r,l,b"(i32 0, i32 0, i32 0, i32 0, ptr addrspace(1) %23, i1 %12) #3, !dbg !21
+  %25 = extractvalue { i32, i32, i32, i32 } %24, 0, !dbg !21
+  %26 = bitcast i32 %25 to <2 x bfloat>, !dbg !21
+  %27 = extractvalue { i32, i32, i32, i32 } %24, 1, !dbg !21
+  %28 = bitcast i32 %27 to <2 x bfloat>, !dbg !21
+  %29 = extractvalue { i32, i32, i32, i32 } %24, 2, !dbg !21
+  %30 = bitcast i32 %29 to <2 x bfloat>, !dbg !21
+  %31 = extractvalue { i32, i32, i32, i32 } %24, 3, !dbg !21
+  %32 = bitcast i32 %31 to <2 x bfloat>, !dbg !21
+  %33 = or disjoint i32 %14, 64, !dbg !22
+  %34 = or disjoint i32 %20, %33, !dbg !19
+  %35 = sext i32 %34 to i64, !dbg !20
+  %36 = getelementptr bfloat, ptr addrspace(1) %0, i64 %35, !dbg !20
+  %37 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, $4;\0A\09mov.u32 $1, $5;\0A\09mov.u32 $2, $6;\0A\09mov.u32 $3, $7;\0A\09@$9 ld.global.L1::evict_first.v4.b32 { $0, $1, $2, $3 }, [ $8 + 0 ];", "=r,=r,=r,=r,r,r,r,r,l,b"(i32 0, i32 0, i32 0, i32 0, ptr addrspace(1) %36, i1 %12) #3, !dbg !21
+  %38 = extractvalue { i32, i32, i32, i32 } %37, 0, !dbg !21
+  %39 = bitcast i32 %38 to <2 x bfloat>, !dbg !21
+  %40 = extractvalue { i32, i32, i32, i32 } %37, 1, !dbg !21
+  %41 = bitcast i32 %40 to <2 x bfloat>, !dbg !21
+  %42 = extractvalue { i32, i32, i32, i32 } %37, 2, !dbg !21
+  %43 = bitcast i32 %42 to <2 x bfloat>, !dbg !21
+  %44 = extractvalue { i32, i32, i32, i32 } %37, 3, !dbg !21
+  %45 = bitcast i32 %44 to <2 x bfloat>, !dbg !21
+  %46 = fpext <2 x bfloat> %26 to <2 x float>, !dbg !23
+  %47 = fmul <2 x float> %46, %46, !dbg !24
+  %48 = fpext <2 x bfloat> %39 to <2 x float>, !dbg !23
+  %49 = fmul <2 x float> %48, %48, !dbg !24
+  %50 = fadd <2 x float> %47, %49, !dbg !25
+  %51 = fpext <2 x bfloat> %28 to <2 x float>, !dbg !23
+  %52 = fmul <2 x float> %51, %51, !dbg !24
+  %53 = fpext <2 x bfloat> %41 to <2 x float>, !dbg !23
+  %54 = fmul <2 x float> %53, %53, !dbg !24
+  %55 = fadd <2 x float> %52, %54, !dbg !25
+  %56 = fpext <2 x bfloat> %30 to <2 x float>, !dbg !23
+  %57 = fmul <2 x float> %56, %56, !dbg !24
+  %58 = fpext <2 x bfloat> %43 to <2 x float>, !dbg !23
+  %59 = fmul <2 x float> %58, %58, !dbg !24
+  %60 = fadd <2 x float> %57, %59, !dbg !25
+  %61 = fpext <2 x bfloat> %32 to <2 x float>, !dbg !23
+  %62 = fmul <2 x float> %61, %61, !dbg !24
+  %63 = fpext <2 x bfloat> %45 to <2 x float>, !dbg !23
+  %64 = fmul <2 x float> %63, %63, !dbg !24
+  %65 = fadd <2 x float> %62, %64, !dbg !25
+  %66 = and i32 %8, 63, !dbg !11
+  %67 = or disjoint i32 %7, %66, !dbg !12
+  %68 = icmp slt i32 %67, %2, !dbg !13
+  %shift = shufflevector <2 x float> %50, <2 x float> poison, <2 x i32> <i32 1, i32 poison>, !dbg !26
+  %69 = fadd <2 x float> %50, %shift, !dbg !26
+  %70 = fadd <2 x float> %55, %69, !dbg !26
+  %shift10 = shufflevector <2 x float> %55, <2 x float> poison, <2 x i32> <i32 1, i32 poison>, !dbg !26
+  %71 = fadd <2 x float> %shift10, %70, !dbg !26
+  %72 = fadd <2 x float> %60, %71, !dbg !26
+  %shift11 = shufflevector <2 x float> %60, <2 x float> poison, <2 x i32> <i32 1, i32 poison>, !dbg !26
+  %73 = fadd <2 x float> %shift11, %72, !dbg !26
+  %74 = fadd <2 x float> %65, %73, !dbg !26
+  %shift12 = shufflevector <2 x float> %65, <2 x float> poison, <2 x i32> <i32 1, i32 poison>, !dbg !26
+  %75 = fadd <2 x float> %shift12, %74, !dbg !26
+  %76 = extractelement <2 x float> %75, i64 0, !dbg !26
+  %77 = select i1 %12, float %76, float 0.000000e+00, !dbg !26
+  %78 = bitcast float %77 to i32, !dbg !31
+  %79 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %78, i32 4, i32 31), !dbg !31
+  %80 = bitcast i32 %79 to float, !dbg !31
+  %81 = fadd float %77, %80, !dbg !26
+  %82 = bitcast float %81 to i32, !dbg !31
+  %83 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %82, i32 2, i32 31), !dbg !31
+  %84 = bitcast i32 %83 to float, !dbg !31
+  %85 = fadd float %81, %84, !dbg !26
+  %86 = bitcast float %85 to i32, !dbg !31
+  %87 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %86, i32 1, i32 31), !dbg !31
+  %88 = bitcast i32 %87 to float, !dbg !31
+  %89 = fadd float %85, %88, !dbg !26
+  %90 = getelementptr inbounds nuw float, ptr addrspace(3) @global_smem, i32 %10, !dbg !32
+  %91 = bitcast float %89 to <1 x i32>, !dbg !32
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %90, <1 x i32> %91, i1 true) #3, !dbg !32
+  tail call void @llvm.nvvm.barrier0(), !dbg !32
+  %92 = getelementptr inbounds nuw float, ptr addrspace(3) @global_smem, i32 %66, !dbg !32
+  %93 = load i32, ptr addrspace(3) %92, align 4, !dbg !32
+  %94 = sext i32 %67 to i64, !dbg !33
+  %95 = getelementptr float, ptr addrspace(1) %1, i64 %94, !dbg !33
+  %96 = and i32 %8, 448, !dbg !34
+  %97 = icmp eq i32 %96, 0, !dbg !34
+  %98 = and i1 %97, %68, !dbg !34
+  tail call void asm sideeffect "@$2 st.global.b32 [ $1 + 0 ], { $0 };", "r,l,b"(i32 %93, ptr addrspace(1) %95, i1 %98) #3, !dbg !34
+  ret void, !dbg !35
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.ctaid.x() #0
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.x() #0
+
+; Function Attrs: convergent nocallback nounwind memory(inaccessiblemem: readwrite)
+declare i32 @llvm.nvvm.shfl.sync.bfly.i32(i32, i32, i32, i32) #1
+
+; Function Attrs: convergent nocallback nounwind
+declare void @llvm.nvvm.barrier0() #2
+
+attributes #0 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #1 = { convergent nocallback nounwind memory(inaccessiblemem: readwrite) }
+attributes #2 = { convergent nocallback nounwind }
+attributes #3 = { nounwind }
+
+!llvm.module.flags = !{!0, !1}
+!llvm.dbg.cu = !{!2}
+!nvvm.annotations = !{!4}
+!llvm.ident = !{!5}
+
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = !{i32 4, !"nvvm-reflect-ftz", i32 1}
+!2 = distinct !DICompileUnit(language: DW_LANG_C, file: !3, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: LineTablesOnly)
+!3 = !DIFile(filename: "cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py", directory: "/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qv")
+!4 = !{ptr @triton_red_fused__to_copy_mean_pow_4, !"reqntidx", i32 512}
+!5 = !{!"clang version 3.8.0 (tags/RELEASE_380/final)"}
+!6 = distinct !DISubprogram(name: "triton_red_fused__to_copy_mean_pow_4", linkageName: "triton_red_fused__to_copy_mean_pow_4", scope: !3, file: !3, line: 18, type: !7, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !2)
+!7 = !DISubroutineType(cc: DW_CC_normal, types: !8)
+!8 = !{}
+!9 = !DILocation(line: 22, column: 28, scope: !6)
+!10 = !DILocation(line: 22, column: 33, scope: !6)
+!11 = !DILocation(line: 23, column: 44, scope: !6)
+!12 = !DILocation(line: 23, column: 23, scope: !6)
+!13 = !DILocation(line: 24, column: 21, scope: !6)
+!14 = !DILocation(line: 25, column: 37, scope: !6)
+!15 = !DILocation(line: 28, column: 19, scope: !6)
+!16 = !DILocation(line: 27, column: 19, scope: !6)
+!17 = !DILocation(line: 37, column: 52, scope: !6)
+!18 = !DILocation(line: 37, column: 62, scope: !6)
+!19 = !DILocation(line: 37, column: 57, scope: !6)
+!20 = !DILocation(line: 37, column: 34, scope: !6)
+!21 = !DILocation(line: 37, column: 67, scope: !6)
+!22 = !DILocation(line: 32, column: 31, scope: !6)
+!23 = !DILocation(line: 37, column: 129, scope: !6)
+!24 = !DILocation(line: 39, column: 22, scope: !6)
+!25 = !DILocation(line: 41, column: 23, scope: !6)
+!26 = !DILocation(line: 256, column: 15, scope: !27, inlinedAt: !30)
+!27 = distinct !DILexicalBlockFile(scope: !29, file: !28, discriminator: 0)
+!28 = !DIFile(filename: "standard.py", directory: "/home/x/hfenv/lib/python3.12/site-packages/triton/language")
+!29 = distinct !DILexicalBlockFile(scope: !6, file: !28, discriminator: 0)
+!30 = !DILocation(line: 43, column: 25, scope: !6)
+!31 = !DILocation(line: 286, column: 36, scope: !29, inlinedAt: !30)
+!32 = !DILocation(line: 43, column: 28, scope: !6)
+!33 = !DILocation(line: 44, column: 25, scope: !6)
+!34 = !DILocation(line: 44, column: 36, scope: !6)
+!35 = !DILocation(line: 44, column: 4, scope: !6)

platform/aiml/models/vllm/torch_compile_cache/c220238fa1/rank_0_0/triton_cache/HTZTZWO7H4AVOC4TG2OKIFKB7NJF2F6PKS2P6NWRYNKSL5NSCINQ/triton_red_fused__to_copy_mean_pow_4.ttgir

@@ -0,0 +1,106 @@
+#blocked = #ttg.blocked<{sizePerThread = [1, 8], threadsPerWarp = [4, 8], warpsPerCTA = [16, 1], order = [1, 0]}>
+#blocked1 = #ttg.blocked<{sizePerThread = [1, 1], threadsPerWarp = [32, 1], warpsPerCTA = [2, 8], order = [0, 1]}>
+#loc = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qv/cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py":18:0)
+#loc1 = loc(unknown)
+#loc27 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qv/cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py":43:25)
+#loc34 = loc(callsite(#loc1 at #loc27))
+module attributes {"ttg.num-ctas" = 1 : i32, "ttg.num-warps" = 16 : i32, ttg.target = "cuda:90", "ttg.threads-per-warp" = 32 : i32} {
+  tt.func public @triton_red_fused__to_copy_mean_pow_4(%arg0: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qv/cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py":18:0), %arg1: !tt.ptr<f32> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qv/cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py":18:0), %arg2: i32 loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qv/cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py":18:0), %arg3: i32 {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qv/cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py":18:0)) attributes {noinline = false} {
+    %cst = arith.constant dense<0.000000e+00> : tensor<64x64xf32, #blocked> loc(#loc1)
+    %c0_i32 = arith.constant 0 : i32 loc(#loc1)
+    %c128_i32 = arith.constant 128 : i32 loc(#loc1)
+    %cst_0 = arith.constant dense<0.000000e+00> : tensor<64x64xbf16, #blocked> loc(#loc1)
+    %c64_i32 = arith.constant 64 : i32 loc(#loc1)
+    %cst_1 = arith.constant dense<8> : tensor<64x1xi32, #blocked> loc(#loc1)
+    %cst_2 = arith.constant dense<7168> : tensor<64x1xi32, #blocked> loc(#loc1)
+    %cst_3 = arith.constant dense<128> : tensor<64x1xi32, #blocked> loc(#loc1)
+    %cst_4 = arith.constant dense<5120> : tensor<1x64xi32, #blocked> loc(#loc1)
+    %cst_5 = arith.constant dense<128> : tensor<1x64xi32, #blocked> loc(#loc1)
+    %0 = tt.get_program_id x : i32 loc(#loc2)
+    %1 = arith.muli %0, %c64_i32 : i32 loc(#loc3)
+    %2 = tt.make_range {end = 64 : i32, start = 0 : i32} : tensor<64xi32, #ttg.slice<{dim = 1, parent = #blocked}>> loc(#loc4)
+    %3 = tt.make_range {end = 64 : i32, start = 0 : i32} : tensor<64xi32, #ttg.slice<{dim = 1, parent = #blocked1}>> loc(#loc4)
+    %4 = tt.expand_dims %2 {axis = 1 : i32} : tensor<64xi32, #ttg.slice<{dim = 1, parent = #blocked}>> -> tensor<64x1xi32, #blocked> loc(#loc4)
+    %5 = tt.expand_dims %3 {axis = 1 : i32} : tensor<64xi32, #ttg.slice<{dim = 1, parent = #blocked1}>> -> tensor<64x1xi32, #blocked1> loc(#loc4)
+    %6 = tt.splat %1 : i32 -> tensor<64x1xi32, #blocked> loc(#loc5)
+    %7 = tt.splat %1 : i32 -> tensor<64x1xi32, #blocked1> loc(#loc5)
+    %8 = arith.addi %6, %4 : tensor<64x1xi32, #blocked> loc(#loc5)
+    %9 = arith.addi %7, %5 : tensor<64x1xi32, #blocked1> loc(#loc5)
+    %10 = tt.splat %arg2 : i32 -> tensor<64x1xi32, #blocked> loc(#loc6)
+    %11 = tt.splat %arg2 : i32 -> tensor<64x1xi32, #blocked1> loc(#loc6)
+    %12 = arith.cmpi slt, %8, %10 : tensor<64x1xi32, #blocked> loc(#loc6)
+    %13 = arith.cmpi slt, %9, %11 : tensor<64x1xi32, #blocked1> loc(#loc6)
+    %14 = tt.make_range {end = 64 : i32, start = 0 : i32} : tensor<64xi32, #ttg.slice<{dim = 0, parent = #blocked}>> loc(#loc7)
+    %15 = tt.expand_dims %14 {axis = 0 : i32} : tensor<64xi32, #ttg.slice<{dim = 0, parent = #blocked}>> -> tensor<1x64xi32, #blocked> loc(#loc7)
+    %16 = arith.remsi %8, %cst_1 : tensor<64x1xi32, #blocked> loc(#loc8)
+    %17 = arith.divsi %8, %cst_1 : tensor<64x1xi32, #blocked> loc(#loc9)
+    %18 = arith.muli %16, %cst_3 : tensor<64x1xi32, #blocked> loc(#loc10)
+    %19 = tt.broadcast %18 : tensor<64x1xi32, #blocked> -> tensor<64x64xi32, #blocked> loc(#loc11)
+    %20 = arith.muli %17, %cst_2 : tensor<64x1xi32, #blocked> loc(#loc12)
+    %21 = tt.broadcast %20 : tensor<64x1xi32, #blocked> -> tensor<64x64xi32, #blocked> loc(#loc13)
+    %22 = tt.splat %arg0 : !tt.ptr<bf16> -> tensor<64x64x!tt.ptr<bf16>, #blocked> loc(#loc14)
+    %23 = tt.broadcast %12 : tensor<64x1xi1, #blocked> -> tensor<64x64xi1, #blocked> loc(#loc15)
+    %24 = scf.for %arg4 = %c0_i32 to %c128_i32 step %c64_i32 iter_args(%arg5 = %cst) -> (tensor<64x64xf32, #blocked>)  : i32 {
+      %30 = tt.splat %arg4 : i32 -> tensor<1x64xi32, #blocked> loc(#loc17)
+      %31 = arith.addi %30, %15 : tensor<1x64xi32, #blocked> loc(#loc17)
+      %32 = arith.cmpi slt, %31, %cst_5 : tensor<1x64xi32, #blocked> loc(#loc18)
+      %33 = arith.addi %31, %cst_4 : tensor<1x64xi32, #blocked> loc(#loc19)
+      %34 = tt.broadcast %33 : tensor<1x64xi32, #blocked> -> tensor<64x64xi32, #blocked> loc(#loc11)
+      %35 = arith.addi %34, %19 : tensor<64x64xi32, #blocked> loc(#loc11)
+      %36 = arith.addi %35, %21 : tensor<64x64xi32, #blocked> loc(#loc13)
+      %37 = tt.addptr %22, %36 : tensor<64x64x!tt.ptr<bf16>, #blocked>, tensor<64x64xi32, #blocked> loc(#loc14)
+      %38 = tt.broadcast %32 : tensor<1x64xi1, #blocked> -> tensor<64x64xi1, #blocked> loc(#loc15)
+      %39 = arith.andi %23, %38 : tensor<64x64xi1, #blocked> loc(#loc15)
+      %40 = tt.load %37, %39, %cst_0 evictionPolicy = evict_first : tensor<64x64x!tt.ptr<bf16>, #blocked> loc(#loc20)
+      %41 = arith.extf %40 : tensor<64x64xbf16, #blocked> to tensor<64x64xf32, #blocked> loc(#loc21)
+      %42 = arith.mulf %41, %41 : tensor<64x64xf32, #blocked> loc(#loc22)
+      %43 = arith.addf %arg5, %42 : tensor<64x64xf32, #blocked> loc(#loc23)
+      %44 = arith.select %39, %43, %arg5 : tensor<64x64xi1, #blocked>, tensor<64x64xf32, #blocked> loc(#loc24)
+      scf.yield %44 : tensor<64x64xf32, #blocked> loc(#loc25)
+    } loc(#loc16)
+    %25 = "tt.reduce"(%24) <{axis = 1 : i32}> ({
+    ^bb0(%arg4: f32 loc(callsite(#loc1 at #loc27)), %arg5: f32 loc(callsite(#loc1 at #loc27))):
+      %30 = arith.addf %arg4, %arg5 : f32 loc(#loc36)
+      tt.reduce.return %30 : f32 loc(#loc33)
+    }) : (tensor<64x64xf32, #blocked>) -> tensor<64xf32, #ttg.slice<{dim = 1, parent = #blocked}>> loc(#loc33)
+    %26 = ttg.convert_layout %25 : tensor<64xf32, #ttg.slice<{dim = 1, parent = #blocked}>> -> tensor<64xf32, #ttg.slice<{dim = 1, parent = #blocked1}>> loc(#loc29)
+    %27 = tt.expand_dims %26 {axis = 1 : i32} : tensor<64xf32, #ttg.slice<{dim = 1, parent = #blocked1}>> -> tensor<64x1xf32, #blocked1> loc(#loc29)
+    %28 = tt.splat %arg1 : !tt.ptr<f32> -> tensor<64x1x!tt.ptr<f32>, #blocked1> loc(#loc30)
+    %29 = tt.addptr %28, %9 : tensor<64x1x!tt.ptr<f32>, #blocked1>, tensor<64x1xi32, #blocked1> loc(#loc30)
+    tt.store %29, %27, %13 : tensor<64x1x!tt.ptr<f32>, #blocked1> loc(#loc31)
+    tt.return loc(#loc32)
+  } loc(#loc)
+} loc(#loc)
+#loc2 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qv/cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py":22:28)
+#loc3 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qv/cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py":22:33)
+#loc4 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qv/cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py":23:44)
+#loc5 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qv/cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py":23:23)
+#loc6 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qv/cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py":24:21)
+#loc7 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qv/cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py":25:37)
+#loc8 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qv/cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py":27:19)
+#loc9 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qv/cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py":28:19)
+#loc10 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qv/cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py":37:52)
+#loc11 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qv/cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py":37:48)
+#loc12 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qv/cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py":37:62)
+#loc13 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qv/cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py":37:57)
+#loc14 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qv/cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py":37:34)
+#loc15 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qv/cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py":37:75)
+#loc16 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qv/cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py":31:40)
+#loc17 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qv/cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py":32:31)
+#loc18 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qv/cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py":33:29)
+#loc19 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qv/cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py":37:41)
+#loc20 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qv/cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py":37:67)
+#loc21 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qv/cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py":37:129)
+#loc22 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qv/cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py":39:22)
+#loc23 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qv/cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py":41:23)
+#loc24 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qv/cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py":42:48)
+#loc25 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qv/cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py":42:8)
+#loc26 = loc("/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py":286:36)
+#loc28 = loc("/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py":256:15)
+#loc29 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qv/cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py":43:28)
+#loc30 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qv/cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py":44:25)
+#loc31 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qv/cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py":44:36)
+#loc32 = loc("/home/x/.cache/vllm/torch_compile_cache/c220238fa1/rank_0_0/inductor_cache/qv/cqvcjjyvkklazagqglbdkmxyykwyrvx7kgkvafmg73qpnqbsvjba.py":44:4)
+#loc33 = loc(callsite(#loc26 at #loc27))
+#loc35 = loc(callsite(#loc28 at #loc26))
+#loc36 = loc(callsite(#loc35 at #loc27))