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8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.9 Algorithm TA32 | |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.9.0 General | The Inputs and Outputs of the algorithm are: Parameter Size Input 1 Input 2 Input 3 120 bits 80 bits 16 bits Output 1 Output 2 80 bits 1 bit The algorithm is based on the BL2 structure and is shown in Figure 10. Input 1 is expanded and used as the input to BL2. Input 1 (expand) BL2 Output 1 128 bits 120 bits (shrink) O... |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.9.1 Input 1 expansion | The 128-bit data input to BL2 is derived from Input 1 in the following manner. If Input 1 is denoted by B, then the expansion is: |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.9.2 Key derivation | The 128-bit key is derived in the same way as described in clause 5.8.2, however, for TA32 the mentioned Input 2 and Input 3 has to be interchanged. ETSI ETSI TS 104 053-3 V1.1.1 (2024-07) 18 |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.9.3 Output derivation | The 120-bit output of BL2 is shrunk to the 80-bit Output 1 using SHR1 defined in clause 5.5.1. The one-bit Output 2 is the binary result of a check of the 120-bit output of BL2, denoted B14 β¦β¦. Bo, before shrinking: Output 2 = False if Bi = Bi + 1 β Bi + 2 for i = 0, 3, 6, 9, 12 Output 2 = True otherwise. |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.10 Algorithm TA5l | |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.10.0 General | The Inputs and Output of the algorithm are: Parameter Size Input 1 Input 2 Input 3 Input 4 80 bits 16 bits 128 bits 5 bits Output 120 bits The algorithm is based on the BL 1 structure as shown in Figure 11. The combination of Input 1 and Input 4 is expanded and used as the input to BLl. Input 2 is combined with Input 3... |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.10.1 Data input to BL1 | The 128-bit data input to BLl is derived from Input 1 and Input 4 in the following manner. Input 1 and Input 4 are concatenated as follows: β’ (Input 4 is proceeded by three zeroes). ETSI ETSI TS 104 053-3 V1.1.1 (2024-07) 19 β’ This string of 88 bits is expanded to 120 bits using EXP3 defined in clause 5.4.3. |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.10.2 Key derivation | The 128-bit key is derived from Input 2 and Input 3 as follows. If Input 2 is denoted as A and Input 3 as B, then: An128-bit string C is formed by concatenating eight copies of Input A. β’ C is XOR-ed with B and the result. β’ K = C β B is used as the key. |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.10.3 Output derivation | The 120-bit Output is derived as described in clause 5.8.3. |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.11 Algorithm TA52 | |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.11.0 General | The Inputs and Outputs of the algorithm are: The algorithm is based on the BL2 structure and is shown in Figure 12. Input 1 (expand) BL1 Output 1 128 bits 128 bits (shrink) Key (input2, input3 Output 3 Output 2 Figure 12: The TA52 Algorithm ETSI ETSI TS 104 053-3 V1.1.1 (2024-07) 20 Input 1 is expanded and used as the ... |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.11.1 Input 1 expansion | Input 1 is expanded to 128 bits as described in clause 5.9.1. |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.11.2 Key derivation | The 128-bit key is derived in the same way as described in clause 5.10.2, however for TA52 the mentioned Input 2 and Input 3 has to be interchanged. |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.11.3 Output derivation | The 120-bit output of BL2 is shrunk to the 88-bits using SHR2 defined in clause 5.5.1. The leftmost 80 bits are the Output 1; the rightmost 5 bits the Output 3. The one-bit Output 2 is the binary result of a check of the 120-bit output of BL2, denoted B 14... Bo, before shrinking: Output 2 = False if Bi = Bi+1 β Bi+2 β... |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.12 The Algorithm TA61 | |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.12.0 General | The Inputs and Output of the algorithm are: Parameter Size Input 1 Input 2 80 bits 24 bits Output 24 bits The structure of TA61 is shown in Figure 13. Input 1 is shrunk to 64 bits and used as the input to BC. Input 1 is also expanded and used as the key to BC. Input 2 is XOR-ed in three steps with three 24-bit strings ... |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.12.1 Input 1 shrinking | The 64-bit data input to BC is derived from Input 1 in the following manner. If Input 1 is denoted as A, then the 64-bit data input to BC is: |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.12.2 Key derivation | The Input 1 is expanded to a 128-bit key by using EXP4 defined in clause 5.4.4. |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.12.3 K-string derivation | The three 24-bit strings Ki, K2 and K3 are derived from the BC output in the following manner: ETSI ETSI TS 104 053-3 V1.1.1 (2024-07) 22 |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.12.4 Permutation P | The permutation P on the 24-bit strings (3 bytes) is done as follows. If the input to the permutation is: |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.13 The Algorithm TA71 | |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.13.0 General | The Inputs and Output of the algorithm are: Parameter Size Input 1 Input 2 80 bits 80 bits Output 80 bits The algorithm is based on the BL1 structure as shown in Figure 14. Input 1 and Input 2 are combined and used as the data input to BL1. Input 1 is combined with Input 2 and used to form the key. The Output is derive... |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.13.1 Data input | The 128-bit data input to BL1 is derived from Input 1 and Input 2 in the following manner: Input 1 is XOR-ed with Input 2 and the resultant 80-bit value is expanded to 128 bits using EXP2 as defined in clause 5.4.2. Input 1 (combine & expand) BL1 Output 128 bits 128 bits (shrink) Key (input1, input2 Input 2 Figure 14: ... |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.13.2 Key input | The 128-bit key is derived from Input 1 and Input 2 in the following manner: If Input 1 is denoted as A and Input 2 as B, then the key K is given by: |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.13.3 Output derivation | The 128-bit output of BLl is shrunk to the 80-bit Output using SHR3 defined in clause 5.5.3. |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.14 Algorithm TA81 | |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.14.0 General | The basic block structure BL1 specified in clause 5.2 is used to construct TA81. The Inputs and Output of the TA81 algorithm are: Parameter Size Input 1 Input 2 Input 3 Input 4 80 bits 16 bits 128 bits 16 bits Output 120 bits The algorithm is based on the BL1 structure as shown in Figure 15 below. The combination of In... |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.14.1 Data input to BL1 | The 128-bit data input to BL1 is derived from Input 1 and Input 4 in the following manner: 1) Input 1 and Input 4 are concatenated as follows: Input 1 Input 4 This 96-bit string denoted as a 12-byte string. B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 2) This 12-byte string is expanded to 16-byte string as described below: - ... |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.14.2 Key derivation | Derive the 128-bit key from Input 2 and Input 3 as follows. If Input 2 is denoted as A (2 bytes) and Input 3 as B (16 bytes), then: a 128-bit string C is formed by concatenating eight copies of Input A. C = A1A0A1A0A1A0A1A0A1A0A1A0A1A0A1A0 C is XOR-ed with B and the result. K=C β B is used as the key. |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.14.3 Output derivation | Derive the 120-bit Output as described in clause 5.8.3 that is. The 120-bit Output is: 015014013012011010090706050403020100 where 0 is the 128-bit output of BL1 and 0j is the j-th byte of 0. Note that byte O8 is discarded. |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.15 Algorithm TA82 | |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.15.0 General | The basic block structure BL2 specified in clause 5.3 is used to construct TA82. The Inputs and Outputs of the TA82 algorithm are: Parameter Size Input 1 Input 2 Input 3 120 bits 128 bits 16 bits Output 1 Output 2 Output 3 80 bits 1 bit 16 bits The algorithm is based on the BL2 structure and is shown in Figure 17. Figu... |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.15.1 Input 1 expansion | Input 1 (length 120 bits) is expanded to 128 bits as described in clause 5.9.1. That is if Input 1 is denoted by B (15 bytes), then the expansion is: B14B13B12B11B10B9B8 (zero byte) B7B6B5B4B3B2B1B0 |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.15.2 Key derivation | The 128-bit key is derived in the same way as described in clause 5.14.1. However, for TA82 the mentioned Input 2 and Input 3 has to be interchanged, that is derive the 128-bit key from Input 2 and Input 3 as follows: If Input 3 is denoted as A (2 bytes) and Input 2 as B (16 bytes), then: a 128-bit string C is formed b... |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.15.3 Output derivation | Denote the 16-byte output (see also clause 5.3 describing BL2) as: B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 The 10 bytes (80 bits) B15 B14 B13 B12 B10 B9 B8 B7 B5 B4 are set as the Output 1. The 2 bytes (16 bits) B3 B2 are set as the Output 3. The one-bit Output 2 is the binary result of a check of the out... |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.16 Algorithm TA91 | |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.16.0 General | The basic block structure BL1 specified in clause 5.2 is used to construct TA91. The Inputs and Output of the TA91 algorithm are: Parameter Size Input 1 Input 2 Input 3 96 bits 16 bits 128 bits Output 120 bits The algorithm is based on the BL1 structure as shown in Figure 18 below. ETSI ETSI TS 104 053-3 V1.1.1 (2024-0... |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.16.1 Data input to BL1 | The 128-bit data input to BL1 is derived from Input 1 in the following manner: 1) Input 1 is denoted as a 12-byte string. B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 2) This 12-byte string is expanded to 16-byte string as described below. - Compute the values A, C, and D, insert these into the 12-byte block and add an all ze... |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.16.2 Key derivation | Derive the 128-bit key from Input 2 and Input 3 as follows. If Input 2 is denoted as A (2 bytes) and Input 3 as B (16 bytes), then: a 128-bit string C is formed by concatenating eight copies of Input A. C = A1A0A1A0A1A0A1A0A1A0A1A0A1A0A1A0 Input 1 128 bits Key (input2, input3) ( expand ) BL1 128 bits Output ( shrink ) ... |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.16.3 Output derivation | The 120-bit Output is derived as described in clause 5.8.3 that is: The 120-bit Output is: O15O14O13O12O11O10O9O7O6O5O4O3O2O1O0 where: O is the 128-bit output of BL1; and Oj is the j-th byte of O. Note that byte O8 is discarded. |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.17 Algorithm TA92 | |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.17.0 General | The basic block structure BL2 specified in clause 5.3 is used to construct TA92. The Inputs and Outputs of the TA92 algorithm are: Parameter Size Input 1 Input 2 Input 3 120 bits 128 bits 16 bits Output 1 Output 2 96 bits 1 bit The algorithm is based on the BL2 structure and is shown in Figure 20. Figure 20: The TA92 A... |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.17.1 Input 1 expansion | Input 1 (length 120 bits) is expanded to 128 bits as described in clause 5.9.1. That is if Input 1 is denoted by B (15 bytes), then the expansion is: B14B13B12B11B10B9B8 (zero byte) B7B6B5B4B3B2B1B0 |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.17.2 Key derivation | The 128-bit key is derived in the same way as described in clause 5.16.2 of this addendum. However, for TA92 the mentioned Input 2 and Input 3 has to be interchanged, that is derive the 128-bit key from Input 2 and Input 3 as follows: Input 3 is denoted as A (2 bytes) and Input 2 as B (16 bytes), then: a 128-bit string... |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.17.3 Output derivation | Denote the 16-byte output see also clause 4.3.2 of BL2 as: B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 The 12 bytes (96 bits) B15 B14 B13 B12 B10 B9 B8 B7 B5 B4 B3 B2 are set as the Output 1. The one-bit Output 2 is the binary result of a check of the output of BL2: β’ Output 2 = FALSE if Bi = B4+i β B3+i β B2... |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.18 Algorithm TA101 | The Inputs and Output of the TA101 algorithm are: Parameter Size Input 1 (KS) Input 2 (GCK0) Input 3 (MNI) 128 bits 80 bits 24 bits Output (KSv) 128 bits TA101 uses the basic block structure BL1 of the TAA1 algorithm set. An intermediate 80-bit value Input 4 (INT) is generated by concatenating 3 copies of Input 3 and a... |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.19 Algorithm TB1 | The Input and Output of the algorithm are: Parameter Size Input 16-32 bits Output 128 bits The Output of this algorithm is the Input repeated until 128 bits are obtained starting with the leftmost bit of the Input as the leftmost bit of the Output. |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.20 Algorithm TB2 | The Input and Output of the algorithm are: Parameter Size Input 128 bits Output 128 bits The Output of this algorithm is the Input. ETSI ETSI TS 104 053-3 V1.1.1 (2024-07) 31 |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.21 Algorithm TB3 | The Inputs and Output of the algorithm are: Parameter Size Input 1 Input 2 128 bits 16-32 bits Output 128 bits The Output of this algorithm is the Input 1 XOR-ed with the repeated Input 2. Input 2 is repeated until 128 bits are obtained starting with the leftmost bit of the Input 2 as the leftmost bit of the Output. |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.22 Algorithm TB4 | The Input and Output. of the algorithm are: Parameter Size Input 1 Input 2 80 bits 80 bits Output 80 bits The Output of this algorithm is the Input 1 XOR-ed with Input 2. |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.23 Algorithm TB5 | The Inputs and Output of the TB5 algorithm are: Parameter Size Input 1 Input 2 Input 3 Input 4 80 bits 14 bits 12 bits 6 bits Output 80 bits The Output of this algorithm is input 1 XOR-ed with an intermediate value. The intermediate value consists of inputs 2, 3 and 4 concatenated with inputs 3 and 4 repeated; with the... |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.24 Algorithm TB6 | The Inputs and Output of the TB6 algorithm are: Parameter Size Input 1 (CK) Input 2 (CN) Input 3 (SSI) 80 bits 12 bits 24 bits Output (ECK) 80 bits The Output of this algorithm is input 1 XOR-ed with an intermediate output. The intermediate output consists of the concatenation in turn of inputs 2,3, 2, 3 and 3*; with t... |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 5.23 Algorithm TB7 | The Input and Output of the TB7 algorithm are: Parameter Size Input 96 bits Output 128 bits The 16-byte Output of this algorithm is obtained by adding 4 bytes to the 12-byte Input as described below: 1) Denote the 12-byte input at shown below: B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 ETSI ETSI TS 104 053-3 V1.1.1 (2024-07... |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 6 The HURDLE-II Algorithm | 6.0 General The functional structure of the HURDLE-II algorithm with the 16 round functions and the 16 round keys is shown in Figure 23 of clause 6.7. |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 6.1 Notation | Throughout the present documentbit strings are used. These are written with most significant bit on the left and least significant bit on the right. The bits of such a string are numbered from right to left, beginning at zero. Bit strings are divided into strings of bytes, again with most significant byte leftmost and ... |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 6.2 Encryption | The encryption of input P under key K is carried out as follows. Input P is divided into two 4-byte strings, L0 and R0, with:Β· ETSI ETSI TS 104 053-3 V1.1.1 (2024-07) 34 Then for each integer i with 1β€ i β€16, is defined as: (1) Equations (1) constitute the i-th round function of HURDLE-II, where f denotes the round fun... |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 6.3 Decryption | Decryption of the ciphertext C is achieved by encrypting it using as round keys K16...., K1. That is, following exactly the same procedure as above, but using round in round instead of round key K17-i. The decryption round keys are easily derived from the key K as described in clause 6.5. |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 6.4 The f Function of HURDLE-II | |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 6.4.0 General | The round function f of HURDLE-II, has as inputs a 4-byte value X = X3 X2 X1 X0 and a 12-byte round key, denoted by K i = Ki 11 Ki 10 β¦β¦β¦. K i0 (see clause 6.5). The computation of the f function proceeds in the following stages (see Figure 24 of clause 6.7): β’ expansion of the 4-byte input β’ addition of round key and ... |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 6.4.1 Data Expansion | The 4-byte input data X = X3 X2 X1 X0 is expanded to the following 12-byte string E: |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 6.4.2 Addition of Round Key and Chained Byte Substitution | E and the round key Ki the following 12-byte value T = T11T10β¦β¦β¦. T0 is computed where: with S as the byte permutation defined in Table 1 of clause 6.7. The table entries are given row-wise in hexadecimal in the order S [00], S[01], β¦β¦..S [ f f]. Thus, the expanded version of the data is added modulo 256 with the round... |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 6.4.3 Nibble selection | The 12-byte output T is reduced to the following 32-bit string: where, for each 0 β€ q < 12, Uq denotes the 4 least significant bits of Tq, i.e. the rightmost nibble of Tq. |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 6.4.4 Bit Permutation | The final 4-byte output of the function f is obtained by performing a bit permutation Ο on the 32-bit string U to produce a 4-byte value Y = Y3 Y2 Y1 Yo. The permutation Ο is given in Table 2 of 6.7 and its action on the bits of U is as follows: if the bits of U and Y are numbered from left to right by 31to 0, then bit... |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 6.5 Key Schedule Algorithm | In this clause the key schedule algorithm for HURDLE-II is defined. Recall that the 16-byte key is denoted by: K = K15K14β¦.K0 and the12 byte round keys by K1,β¦β¦, K16 A 16 -byte constant is specified as D = D15 D14 . . . D0 by: D = 3c a7 ec 25 79 57 df c0 38 0a 33 le f3 8c f4 f7 (hexadecimal values for each byte). An in... |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 6.6 Block cipher Generation | |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 6.6.1 Summary | The block cipher generation consists of the following phases: the initial loading of K and the running of the key scheduling process, the loading of P and the proper generation of the block cipher concerned. Thereafter, because the HURDLE-II algorithm remains in continuous encryption mode, subsequent P inputs can.be of... |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 6.6.2 K loading and Key Scheduling | After loading of the 16-byte key K the key scheduling process is performed .to determine the sixteen 12-byte round keys Ki as described in clause 6.5. |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 6.6.3 Block Cipher Generation | The loaded 64-bit input P/C is divided into two 4-byte strings and encrypted/ decrypted in sixteen rounds under the influence. of the round keys as described in clauses 6.2 and 6.3. All stages of the round function are explained in detail in clause 6.4. |
8ff52e6bc39b3a1de8033166295d69b0 | 104 053-3 | 6.7 Figures of HURDLE-II Algorithm | f Round function of HURDLE-II (see Figure 24) Li, Ri Two 4-byte strings (subscript 0 = input; 16 = output) K Round key Figure 23: HURDLE-II block cipher ETSI ETSI TS 104 053-3 V1.1.1 (2024-07) 37 X 32-bit input string E 12 byte expanded input data K 2 byte round key T 8 most significant output bytes of the key addition... |
b9577ffd31d53882333a2ffba47a2f9e | 104 053-1 | 1 Scope | The present document specifies the Terrestrial Trunked Radio system (TETRA) set A encryption algorithms TEA1, TEA2, TEA3 and TEA4. The TETRA Air interface security function provides mechanisms for confidentiality of control signalling and user speech and data at the air interface, authentication and key management mech... |
b9577ffd31d53882333a2ffba47a2f9e | 104 053-1 | 2 References | |
b9577ffd31d53882333a2ffba47a2f9e | 104 053-1 | 2.1 Normative references | References are either specific (identified by date of publication and/or edition number or version number) or non-specific. For specific references, only the cited version applies. For non-specific references, the latest version of the referenced document (including any amendments) applies. Referenced documents which a... |
b9577ffd31d53882333a2ffba47a2f9e | 104 053-1 | 2.2 Informative references | References are either specific (identified by date of publication and/or edition number or version number) or non-specific. For specific references, only the cited version applies. For non-specific references, the latest version of the referenced document (including any amendments) applies. NOTE: While any hyperlinks i... |
b9577ffd31d53882333a2ffba47a2f9e | 104 053-1 | 3 Definition of terms, symbols and abbreviations | |
b9577ffd31d53882333a2ffba47a2f9e | 104 053-1 | 3.1 Terms | For the purposes of the present document, the following terms apply: Cipher Key (CK): value that is used to determine the transformation of plain text to cipher text in a cryptographic algorithm cipher text: data produced through the use of encipherment ETSI ETSI TS 104 053-1 V1.2.1 (2025-02) 7 decipherment: reversal o... |
b9577ffd31d53882333a2ffba47a2f9e | 104 053-1 | 3.2 Symbols | Void. |
b9577ffd31d53882333a2ffba47a2f9e | 104 053-1 | 3.3 Abbreviations | For the purposes of the present document, the following abbreviations apply: CK Cipher key ISI Inter Systems Interface IV Initialization Vector KSG Key Stream Generator TC Technical Committee TCCE TETRA and Critical Communications Evolution TEA1 TETRA Encryption Algorithm No. 1 TEA2 TETRA Encryption Algorithm No. 2 TEA... |
b9577ffd31d53882333a2ffba47a2f9e | 104 053-1 | 4 TEA SET A Specifications | The algorithms TEA1, 2, 3 and 4 specified in the present document generate a sequence of key bytes from a Cipher Key CK and an Initialization Vector IV. The key bytes are used to encrypt or to decrypt information transmitted via the TETRA system. The Cipher Key has a length of 80 bits; the Initialization Vector is 29 b... |
b9577ffd31d53882333a2ffba47a2f9e | 104 053-1 | 5 TEA1 ALGORITHM DESCRIPTION | |
b9577ffd31d53882333a2ffba47a2f9e | 104 053-1 | 5.1 TEA1 Functional Components | |
b9577ffd31d53882333a2ffba47a2f9e | 104 053-1 | 5.1.1 Summary of Components | The cryptographic algorithm TEA1 consists of the following functional components as depicted in Figure 1: β’ A set of eight 8-bit wide shift registers, called Output Register (clause 5.1.3). β’ A set of four 8-bit wide shift registers, called Key Register (clause 5.1.4). β’ A byte permutation function P (byte substitution... |
b9577ffd31d53882333a2ffba47a2f9e | 104 053-1 | 5.1.2 Notation | The symbol β denotes the bytewise addition modulo two (exclusive or); i.e. msb of byte x is added to msb of byte y , ...., lsb of byte x to lsb of byte y. x (i) y(i) x(i) β y(i) 0 0 1 1 0 1 0 1 0 1 1 0 x(i) is bit i of byte x y(i) is bit i of byte y i = 0,...,7 |
b9577ffd31d53882333a2ffba47a2f9e | 104 053-1 | 5.1.3 Output Register | The output register is denoted by R0, R1..., R6, and R7, and functions as an 8-bit wide shift register. The output bytes of sections R1, R2 and R4 up to R6 are also used as input for the other functional components of the TEA1. The output of R7 is added to the outputs of the other functional components and returned to ... |
b9577ffd31d53882333a2ffba47a2f9e | 104 053-1 | 5.1.4 Key Register | The key register, denoted by K0, K1, K2 and K3, is a four section 8-bit wide shift register. The bytes of a Cipher Key (CK) are loaded into the key register as shown in Figure 2, and before the Initialization Vector is loaded into the Output Register. During loading the CK bytes are added modulo two to the result of th... |
b9577ffd31d53882333a2ffba47a2f9e | 104 053-1 | 5.1.5 Byte Permutation Function | The byte permutation function P is a randomly chosen permutation in the set of all 256 possible bytes. The look up table for this permutation is given in Figure 3. The higher nibble of the output is the left one of the output value, e.g. P (27 ) = 6A. |
b9577ffd31d53882333a2ffba47a2f9e | 104 053-1 | 5.1.6 Expander E | The expander function converts a two-byte input to a 32-bit word, i.e. eight 4-bit nibbles for the nonlinear functions f1 and f2. The structure of expander E and functions f1 and f2 is shown in Figure 4. In this figure, bits 1-8 are the bits of R2, respectively R6. Bits 9-16 are the bits of R1, respectively R5. Bits 1 ... |
b9577ffd31d53882333a2ffba47a2f9e | 104 053-1 | 5.1.7 Nonlinear Function f1 | The nonlinear functions f1 and f2 have the structure shown in Figure 4. Each of the boxes S1 to S8 receives the nibble input concerned from the expander E and computes a bit for the output byte. S1 is the most significant bit in the output byte, and S8 is the least significant one. The functions f1 and f2 are given in ... |
b9577ffd31d53882333a2ffba47a2f9e | 104 053-1 | 5.1.8 8-bit Permutation BP | The permutation BP is a so-called wire-crossing with a fixed pattern. If the eight bits of R4 are numbered 12345678 the order of the bits after BP becomes 58417326. The left bit in both bytes is the most significant; the right bit is the least significant. |
b9577ffd31d53882333a2ffba47a2f9e | 104 053-1 | 5.1.9 Feedback of output register | The results of the functional components BP, f1, f2 and CK byte permutation P are added in the feedback path of the output register and affect. the operation (i.e. operation after loading the CK and Initialization vector) as follows: with R'i denoting the next byte value (i.e. after one step) of the output register Sec... |
b9577ffd31d53882333a2ffba47a2f9e | 104 053-1 | 5.2 Key Stream Generation | |
b9577ffd31d53882333a2ffba47a2f9e | 104 053-1 | 5.2.1 Summary | The algorithm consists of four main phases: the CK loading, the IV loading, the run-up and the key byte generation proper. During the CK loading the initial state of the key register is determined. Next, the initial state of the output register is determined by loading of the Initialization Vector as described in claus... |
b9577ffd31d53882333a2ffba47a2f9e | 104 053-1 | 5.2.2 CK loading | The CK loading depends on the 80-bit Cipher Key, the feedback method and the permutation function P. The 10 CK bytes are loaded as depicted in clause 5.3, Figure 2. The reduced CK, i.e. the 32 bits available in the Ki register after the loading process, will affect the further initialization of the algorithm and the ge... |
b9577ffd31d53882333a2ffba47a2f9e | 104 053-1 | 5.2.3 IV loading | The output register is first loaded with a.29-bit Initialization Vector. This IV is converted to a 32-bit word by taking the three most significant bits as zeroes, and the remaining 29 bit as the given IV. For instance, if the running counter is the binary value: 11010 00011010 11100010 00000110 the 32-bit word becomes... |
b9577ffd31d53882333a2ffba47a2f9e | 104 053-1 | 5.2.4 Run-up | After the IV load into the output register all functional components of the TEA1 become operational and 53 initializing steps are performed to bring the algorithm in the CK and IV dependent starting point from which the generation of key bytes can start. For run-up and key byte generation a step is defined as applying ... |
b9577ffd31d53882333a2ffba47a2f9e | 104 053-1 | 5.2.5 Key byte generation | After the run-up cycle one step is made to produce the first key byte. Successive key bytes are generated each 19 steps. ETSI ETSI TS 104 053-1 V1.2.1 (2025-02) 12 |
b9577ffd31d53882333a2ffba47a2f9e | 104 053-1 | 5.3 Figures of TEA1 Algorithm | Figure 1: Functional components of TEA1 ETSI ETSI TS 104 053-1 V1.2.1 (2025-02) 13 Figure 2: Cipher Key Load Map Figure 3: Byte permutation lookup table ETSI ETSI TS 104 053-1 V1.2.1 (2025-02) 14 Figure 4: Structure of expander and functions f1 and f2 Figure 5: Truth table of f1 Figure 6: Truth table of f2 ETSI ETSI TS... |
b9577ffd31d53882333a2ffba47a2f9e | 104 053-1 | 6 TEA2 ALGORITHM DESCRIPTION | |
b9577ffd31d53882333a2ffba47a2f9e | 104 053-1 | 6.1 TEA2 Functional Components | |
b9577ffd31d53882333a2ffba47a2f9e | 104 053-1 | 6.1.1 Summary of Components | The cryptographic algorithm TEA2 consists of the following functional components as depicted in Figure 7: β’ A set of eight 8-bit wide shift registers, called Output Register (clause 6.1.3). β’ A set of ten 8-bit wide shift registers, called Cipher Key Register (clause 6.1.4). β’ A byte permutation function P (byte substi... |
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