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  1. testbench/HiSA-Team_Simply-V_pr108/coverage.dat +8 -0
  2. testbench/HiSA-Team_Simply-V_pr108/open_tool_include_fixed_63923.sv +2 -0
  3. testbench/HiSA-Team_Simply-V_pr108/open_tool_include_fixed_90035.sv +2 -0
  4. testbench/HiSA-Team_Simply-V_pr108/verilator_buggy_build.log +27 -0
  5. testbench/HiSA-Team_Simply-V_pr108/verilator_fixed.log +4 -0
  6. testbench/HiSA-Team_Simply-V_pr108/verilator_fixed_coverage.info +26 -0
  7. testbench/StanfordVLSI_dragonphy2_pr90/coverage.dat +106 -0
  8. testbench/StanfordVLSI_dragonphy2_pr90/open_tool_p2p_buggy.log +3 -0
  9. testbench/StanfordVLSI_dragonphy2_pr90/open_tool_p2p_fixed.log +3 -0
  10. testbench/StanfordVLSI_dragonphy2_pr90/repo_native_buggy.log +1 -0
  11. testbench/StanfordVLSI_dragonphy2_pr90/repo_native_fixed.log +1 -0
  12. testbench/StanfordVLSI_dragonphy2_pr90/repo_native_source.path +1 -0
  13. testbench/StanfordVLSI_dragonphy2_pr90/run_once.sh +4 -0
  14. testbench/StanfordVLSI_dragonphy2_pr90/run_verilator.sh +59 -0
  15. testbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.sv +37 -0
  16. testbench/StanfordVLSI_dragonphy2_pr90/verilator_buggy_build.log +29 -0
  17. testbench/StanfordVLSI_dragonphy2_pr90/verilator_fixed.log +4 -0
  18. testbench/StanfordVLSI_dragonphy2_pr90/verilator_fixed_build.log +14 -0
  19. testbench/StanfordVLSI_dragonphy2_pr90/verilator_fixed_coverage.info +154 -0
  20. testbench/hdl-util_hdmi_pr30/tb_hdmi_vsync_timing.sv +88 -0
testbench/HiSA-Team_Simply-V_pr108/coverage.dat ADDED
@@ -0,0 +1,8 @@
 
 
 
 
 
 
 
 
 
1
+ # SystemC::Coverage-3
2
+ C 'ftestbench/HiSA-Team_Simply-V_pr108/tb_uninasoc_pkg_verilator.svl12n5tbranchpagev_branch/tb_uninasoc_pkg_verilatoroifS12-13hTOP.tb_uninasoc_pkg_verilator' 1
3
+ C 'ftestbench/HiSA-Team_Simply-V_pr108/tb_uninasoc_pkg_verilator.svl12n6tbranchpagev_branch/tb_uninasoc_pkg_verilatoroelseS15hTOP.tb_uninasoc_pkg_verilator' 0
4
+ C 'ftestbench/HiSA-Team_Simply-V_pr108/tb_uninasoc_pkg_verilator.svl17n5tbranchpagev_branch/tb_uninasoc_pkg_verilatoroifS17-18hTOP.tb_uninasoc_pkg_verilator' 1
5
+ C 'ftestbench/HiSA-Team_Simply-V_pr108/tb_uninasoc_pkg_verilator.svl17n6tbranchpagev_branch/tb_uninasoc_pkg_verilatoroelseS20hTOP.tb_uninasoc_pkg_verilator' 0
6
+ C 'ftestbench/HiSA-Team_Simply-V_pr108/tb_uninasoc_pkg_verilator.svl22n5tbranchpagev_branch/tb_uninasoc_pkg_verilatoroifS22-23hTOP.tb_uninasoc_pkg_verilator' 1
7
+ C 'ftestbench/HiSA-Team_Simply-V_pr108/tb_uninasoc_pkg_verilator.svl22n6tbranchpagev_branch/tb_uninasoc_pkg_verilatoroelseS25hTOP.tb_uninasoc_pkg_verilator' 0
8
+ C 'ftestbench/HiSA-Team_Simply-V_pr108/tb_uninasoc_pkg_verilator.svl6n3tlinepagev_line/tb_uninasoc_pkg_verilatoroblockS6-10,27hTOP.tb_uninasoc_pkg_verilator' 1
testbench/HiSA-Team_Simply-V_pr108/open_tool_include_fixed_63923.sv ADDED
@@ -0,0 +1,2 @@
 
 
 
1
+ `include "testbench/HiSA-Team_Simply-V_pr108/snapshot_scratch/hw/xilinx/rtl/uninasoc_axi.svh"
2
+ module __open_tool_include_smoke; endmodule
testbench/HiSA-Team_Simply-V_pr108/open_tool_include_fixed_90035.sv ADDED
@@ -0,0 +1,2 @@
 
 
 
1
+ `include "testbench/HiSA-Team_Simply-V_pr108/snapshot_scratch/hw/xilinx/rtl/uninasoc_mem.svh"
2
+ module __open_tool_include_smoke; endmodule
testbench/HiSA-Team_Simply-V_pr108/verilator_buggy_build.log ADDED
@@ -0,0 +1,27 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ %Error: testbench/HiSA-Team_Simply-V_pr108/tb_uninasoc_pkg_verilator.sv:7:14: Can't find definition of variable: 'MBUS_DATA_WIDTH'
2
+ 7 | data_w = MBUS_DATA_WIDTH;
3
+ | ^~~~~~~~~~~~~~~
4
+ ... See the manual at https://verilator.org/verilator_doc.html?v=5.047 for more assistance.
5
+ %Error: testbench/HiSA-Team_Simply-V_pr108/tb_uninasoc_pkg_verilator.sv:8:14: Can't find definition of variable: 'MBUS_ADDR_WIDTH'
6
+ : ... Suggested alternative: 'MBUS_DATA_WIDTH'
7
+ 8 | addr_w = MBUS_ADDR_WIDTH;
8
+ | ^~~~~~~~~~~~~~~
9
+ %Error: testbench/HiSA-Team_Simply-V_pr108/tb_uninasoc_pkg_verilator.sv:9:14: Can't find definition of variable: 'MBUS_ID_WIDTH'
10
+ : ... Suggested alternative: 'MBUS_ADDR_WIDTH'
11
+ 9 | id_w = MBUS_ID_WIDTH;
12
+ | ^~~~~~~~~~~~~
13
+ %Error: Exiting due to 3 error(s)
14
+ HWE_AUTO_COVERAGE: retrying with --coverage-line
15
+ %Error: testbench/HiSA-Team_Simply-V_pr108/tb_uninasoc_pkg_verilator.sv:7:14: Can't find definition of variable: 'MBUS_DATA_WIDTH'
16
+ 7 | data_w = MBUS_DATA_WIDTH;
17
+ | ^~~~~~~~~~~~~~~
18
+ ... See the manual at https://verilator.org/verilator_doc.html?v=5.047 for more assistance.
19
+ %Error: testbench/HiSA-Team_Simply-V_pr108/tb_uninasoc_pkg_verilator.sv:8:14: Can't find definition of variable: 'MBUS_ADDR_WIDTH'
20
+ : ... Suggested alternative: 'MBUS_DATA_WIDTH'
21
+ 8 | addr_w = MBUS_ADDR_WIDTH;
22
+ | ^~~~~~~~~~~~~~~
23
+ %Error: testbench/HiSA-Team_Simply-V_pr108/tb_uninasoc_pkg_verilator.sv:9:14: Can't find definition of variable: 'MBUS_ID_WIDTH'
24
+ : ... Suggested alternative: 'MBUS_ADDR_WIDTH'
25
+ 9 | id_w = MBUS_ID_WIDTH;
26
+ | ^~~~~~~~~~~~~
27
+ %Error: Exiting due to 3 error(s)
testbench/HiSA-Team_Simply-V_pr108/verilator_fixed.log ADDED
@@ -0,0 +1,4 @@
 
 
 
 
 
1
+ PASS: MBUS_DATA_WIDTH=32
2
+ PASS: MBUS_ADDR_WIDTH=32
3
+ PASS: MBUS_ID_WIDTH=4
4
+ - testbench/HiSA-Team_Simply-V_pr108/tb_uninasoc_pkg_verilator.sv:27: Verilog $finish
testbench/HiSA-Team_Simply-V_pr108/verilator_fixed_coverage.info ADDED
@@ -0,0 +1,26 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ TN:verilator_coverage
2
+ SF:testbench/HiSA-Team_Simply-V_pr108/tb_uninasoc_pkg_verilator.sv
3
+ DA:6,1
4
+ DA:7,1
5
+ DA:8,1
6
+ DA:9,1
7
+ DA:10,1
8
+ DA:12,1
9
+ BRDA:12,0,0,1
10
+ BRDA:12,0,1,0
11
+ DA:13,1
12
+ DA:15,0
13
+ DA:17,1
14
+ BRDA:17,0,0,1
15
+ BRDA:17,0,1,0
16
+ DA:18,1
17
+ DA:20,0
18
+ DA:22,1
19
+ BRDA:22,0,0,1
20
+ BRDA:22,0,1,0
21
+ DA:23,1
22
+ DA:25,0
23
+ DA:27,1
24
+ BRF:6
25
+ BRH:0
26
+ end_of_record
testbench/StanfordVLSI_dragonphy2_pr90/coverage.dat ADDED
@@ -0,0 +1,106 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ # SystemC::Coverage-3
2
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl12n26ttogglepagev_toggle/prbs_generatorodata[0]:0->1hTOP.tb_prbs_generator_verilator.dut' 33
3
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl12n26ttogglepagev_toggle/prbs_generatorodata[0]:1->0hTOP.tb_prbs_generator_verilator.dut' 32
4
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl12n26ttogglepagev_toggle/prbs_generatorodata[1]:0->1hTOP.tb_prbs_generator_verilator.dut' 34
5
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl12n26ttogglepagev_toggle/prbs_generatorodata[1]:1->0hTOP.tb_prbs_generator_verilator.dut' 33
6
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl12n26ttogglepagev_toggle/prbs_generatorodata[2]:0->1hTOP.tb_prbs_generator_verilator.dut' 33
7
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl12n26ttogglepagev_toggle/prbs_generatorodata[2]:1->0hTOP.tb_prbs_generator_verilator.dut' 33
8
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl12n26ttogglepagev_toggle/prbs_generatorodata[3]:0->1hTOP.tb_prbs_generator_verilator.dut' 34
9
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl12n26ttogglepagev_toggle/prbs_generatorodata[3]:1->0hTOP.tb_prbs_generator_verilator.dut' 33
10
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl12n26ttogglepagev_toggle/prbs_generatorodata[4]:0->1hTOP.tb_prbs_generator_verilator.dut' 33
11
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl12n26ttogglepagev_toggle/prbs_generatorodata[4]:1->0hTOP.tb_prbs_generator_verilator.dut' 33
12
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl12n26ttogglepagev_toggle/prbs_generatorodata[5]:0->1hTOP.tb_prbs_generator_verilator.dut' 33
13
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl12n26ttogglepagev_toggle/prbs_generatorodata[5]:1->0hTOP.tb_prbs_generator_verilator.dut' 32
14
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl12n26ttogglepagev_toggle/prbs_generatorodata[6]:0->1hTOP.tb_prbs_generator_verilator.dut' 34
15
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl12n26ttogglepagev_toggle/prbs_generatorodata[6]:1->0hTOP.tb_prbs_generator_verilator.dut' 33
16
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl16n11ttogglepagev_toggle/prbs_generatoronext_bit:0->1hTOP.tb_prbs_generator_verilator.dut' 33
17
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl16n11ttogglepagev_toggle/prbs_generatoronext_bit:1->0hTOP.tb_prbs_generator_verilator.dut' 33
18
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl4n22ttogglepagev_toggle/prbs_generatoroclk:0->1hTOP.tb_prbs_generator_verilator.dut' 134
19
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl4n22ttogglepagev_toggle/prbs_generatoroclk:1->0hTOP.tb_prbs_generator_verilator.dut' 133
20
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl46n26ttogglepagev_toggle/prbs_generatoronext_data[0]:0->1hTOP.tb_prbs_generator_verilator.dut' 33
21
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl46n26ttogglepagev_toggle/prbs_generatoronext_data[0]:1->0hTOP.tb_prbs_generator_verilator.dut' 33
22
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl46n26ttogglepagev_toggle/prbs_generatoronext_data[1]:0->1hTOP.tb_prbs_generator_verilator.dut' 33
23
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl46n26ttogglepagev_toggle/prbs_generatoronext_data[1]:1->0hTOP.tb_prbs_generator_verilator.dut' 32
24
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl46n26ttogglepagev_toggle/prbs_generatoronext_data[2]:0->1hTOP.tb_prbs_generator_verilator.dut' 34
25
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl46n26ttogglepagev_toggle/prbs_generatoronext_data[2]:1->0hTOP.tb_prbs_generator_verilator.dut' 33
26
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl46n26ttogglepagev_toggle/prbs_generatoronext_data[3]:0->1hTOP.tb_prbs_generator_verilator.dut' 33
27
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl46n26ttogglepagev_toggle/prbs_generatoronext_data[3]:1->0hTOP.tb_prbs_generator_verilator.dut' 33
28
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl46n26ttogglepagev_toggle/prbs_generatoronext_data[4]:0->1hTOP.tb_prbs_generator_verilator.dut' 34
29
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl46n26ttogglepagev_toggle/prbs_generatoronext_data[4]:1->0hTOP.tb_prbs_generator_verilator.dut' 33
30
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl46n26ttogglepagev_toggle/prbs_generatoronext_data[5]:0->1hTOP.tb_prbs_generator_verilator.dut' 33
31
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl46n26ttogglepagev_toggle/prbs_generatoronext_data[5]:1->0hTOP.tb_prbs_generator_verilator.dut' 33
32
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl46n26ttogglepagev_toggle/prbs_generatoronext_data[6]:0->1hTOP.tb_prbs_generator_verilator.dut' 33
33
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl46n26ttogglepagev_toggle/prbs_generatoronext_data[6]:1->0hTOP.tb_prbs_generator_verilator.dut' 32
34
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl5n22ttogglepagev_toggle/prbs_generatororst:0->1hTOP.tb_prbs_generator_verilator.dut' 1
35
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl5n22ttogglepagev_toggle/prbs_generatororst:1->0hTOP.tb_prbs_generator_verilator.dut' 1
36
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl50n5tlinepagev_line/prbs_generatoroblockS50hTOP.tb_prbs_generator_verilator.dut' 134
37
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl51n9tlinepagev_line/prbs_generatoroelsifS51-52hTOP.tb_prbs_generator_verilator.dut' 1
38
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl53n18tlinepagev_line/prbs_generatoroifS53-54hTOP.tb_prbs_generator_verilator.dut' 129
39
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl53n19tlinepagev_line/prbs_generatoroelseS55-56hTOP.tb_prbs_generator_verilator.dut' 4
40
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl6n22ttogglepagev_toggle/prbs_generatorocke:0->1hTOP.tb_prbs_generator_verilator.dut' 2
41
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl6n22ttogglepagev_toggle/prbs_generatorocke:1->0hTOP.tb_prbs_generator_verilator.dut' 1
42
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl7n37ttogglepagev_toggle/prbs_generatoroinit_val[0]:0->1hTOP.tb_prbs_generator_verilator.dut' 0
43
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl7n37ttogglepagev_toggle/prbs_generatoroinit_val[0]:1->0hTOP.tb_prbs_generator_verilator.dut' 0
44
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl7n37ttogglepagev_toggle/prbs_generatoroinit_val[1]:0->1hTOP.tb_prbs_generator_verilator.dut' 1
45
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl7n37ttogglepagev_toggle/prbs_generatoroinit_val[1]:1->0hTOP.tb_prbs_generator_verilator.dut' 0
46
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl7n37ttogglepagev_toggle/prbs_generatoroinit_val[2]:0->1hTOP.tb_prbs_generator_verilator.dut' 0
47
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl7n37ttogglepagev_toggle/prbs_generatoroinit_val[2]:1->0hTOP.tb_prbs_generator_verilator.dut' 0
48
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl7n37ttogglepagev_toggle/prbs_generatoroinit_val[3]:0->1hTOP.tb_prbs_generator_verilator.dut' 1
49
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl7n37ttogglepagev_toggle/prbs_generatoroinit_val[3]:1->0hTOP.tb_prbs_generator_verilator.dut' 0
50
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl7n37ttogglepagev_toggle/prbs_generatoroinit_val[4]:0->1hTOP.tb_prbs_generator_verilator.dut' 1
51
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl7n37ttogglepagev_toggle/prbs_generatoroinit_val[4]:1->0hTOP.tb_prbs_generator_verilator.dut' 0
52
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl7n37ttogglepagev_toggle/prbs_generatoroinit_val[5]:0->1hTOP.tb_prbs_generator_verilator.dut' 0
53
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl7n37ttogglepagev_toggle/prbs_generatoroinit_val[5]:1->0hTOP.tb_prbs_generator_verilator.dut' 0
54
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl7n37ttogglepagev_toggle/prbs_generatoroinit_val[6]:0->1hTOP.tb_prbs_generator_verilator.dut' 1
55
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl7n37ttogglepagev_toggle/prbs_generatoroinit_val[6]:1->0hTOP.tb_prbs_generator_verilator.dut' 0
56
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl8n23ttogglepagev_toggle/prbs_generatoroout:0->1hTOP.tb_prbs_generator_verilator.dut' 34
57
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.svl8n23ttogglepagev_toggle/prbs_generatoroout:1->0hTOP.tb_prbs_generator_verilator.dut' 33
58
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl11n3tlinepagev_line/tb_prbs_generator_verilatoroblockS11hTOP.tb_prbs_generator_verilator' 134
59
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl12n14texprpagev_expr/tb_prbs_generator_verilatoro(cke==0) => 0hTOP.tb_prbs_generator_verilator' 5
60
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl12n14texprpagev_expr/tb_prbs_generator_verilatoro(rst==0 && cke==1) => 1hTOP.tb_prbs_generator_verilator' 129
61
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl12n14texprpagev_expr/tb_prbs_generator_verilatoro(rst==1) => 0hTOP.tb_prbs_generator_verilator' 1
62
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl12n5tbranchpagev_branch/tb_prbs_generator_verilatoroifS12-13hTOP.tb_prbs_generator_verilator' 129
63
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl12n6tbranchpagev_branch/tb_prbs_generator_verilatoroelsehTOP.tb_prbs_generator_verilator' 5
64
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl14n7tbranchpagev_branch/tb_prbs_generator_verilatoroifS14hTOP.tb_prbs_generator_verilator' 65
65
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl14n8tbranchpagev_branch/tb_prbs_generator_verilatoroelsehTOP.tb_prbs_generator_verilator' 64
66
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl17n3tlinepagev_line/tb_prbs_generator_verilatoroblockS17-21,23-27,34hTOP.tb_prbs_generator_verilator' 1
67
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl21n5tlinepagev_line/tb_prbs_generator_verilatoroblockS21hTOP.tb_prbs_generator_verilator' 127
68
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl24n5tlinepagev_line/tb_prbs_generator_verilatoroblockS24hTOP.tb_prbs_generator_verilator' 4
69
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl28n37texprpagev_expr/tb_prbs_generator_verilatoro((cycles >= 32'sh64)==0) => 0hTOP.tb_prbs_generator_verilator' 0
70
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl28n37texprpagev_expr/tb_prbs_generator_verilatoro((cycles >= 32'sh64)==1 && (ones >= 32'sh28)==1 && (ones <= 32'sh5a)==1) => 1hTOP.tb_prbs_generator_verilator' 1
71
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl28n37texprpagev_expr/tb_prbs_generator_verilatoro((ones <= 32'sh5a)==0) => 0hTOP.tb_prbs_generator_verilator' 0
72
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl28n37texprpagev_expr/tb_prbs_generator_verilatoro((ones >= 32'sh28)==0) => 0hTOP.tb_prbs_generator_verilator' 0
73
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl28n5tbranchpagev_branch/tb_prbs_generator_verilatoroifS28-30hTOP.tb_prbs_generator_verilator' 1
74
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl28n6tbranchpagev_branch/tb_prbs_generator_verilatoroelseS31-32hTOP.tb_prbs_generator_verilator' 0
75
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl3n15tlinepagev_line/tb_prbs_generator_verilatoroblockS3hTOP.tb_prbs_generator_verilator' 1
76
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl3n9ttogglepagev_toggle/tb_prbs_generator_verilatoroclk:0->1hTOP.tb_prbs_generator_verilator' 134
77
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl3n9ttogglepagev_toggle/tb_prbs_generator_verilatoroclk:1->0hTOP.tb_prbs_generator_verilator' 133
78
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl36n3tlinepagev_line/tb_prbs_generator_verilatoroblockS36hTOP.tb_prbs_generator_verilator' 0
79
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl4n15tlinepagev_line/tb_prbs_generator_verilatoroblockS4hTOP.tb_prbs_generator_verilator' 1
80
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl4n9ttogglepagev_toggle/tb_prbs_generator_verilatororst:0->1hTOP.tb_prbs_generator_verilator' 1
81
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl4n9ttogglepagev_toggle/tb_prbs_generator_verilatororst:1->0hTOP.tb_prbs_generator_verilator' 1
82
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl5n15tlinepagev_line/tb_prbs_generator_verilatoroblockS5hTOP.tb_prbs_generator_verilator' 1
83
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl5n9ttogglepagev_toggle/tb_prbs_generator_verilatorocke:0->1hTOP.tb_prbs_generator_verilator' 2
84
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl5n9ttogglepagev_toggle/tb_prbs_generator_verilatorocke:1->0hTOP.tb_prbs_generator_verilator' 1
85
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl6n15ttogglepagev_toggle/tb_prbs_generator_verilatoroinit_val[0]:0->1hTOP.tb_prbs_generator_verilator' 0
86
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl6n15ttogglepagev_toggle/tb_prbs_generator_verilatoroinit_val[0]:1->0hTOP.tb_prbs_generator_verilator' 0
87
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl6n15ttogglepagev_toggle/tb_prbs_generator_verilatoroinit_val[1]:0->1hTOP.tb_prbs_generator_verilator' 1
88
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl6n15ttogglepagev_toggle/tb_prbs_generator_verilatoroinit_val[1]:1->0hTOP.tb_prbs_generator_verilator' 0
89
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl6n15ttogglepagev_toggle/tb_prbs_generator_verilatoroinit_val[2]:0->1hTOP.tb_prbs_generator_verilator' 0
90
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl6n15ttogglepagev_toggle/tb_prbs_generator_verilatoroinit_val[2]:1->0hTOP.tb_prbs_generator_verilator' 0
91
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl6n15ttogglepagev_toggle/tb_prbs_generator_verilatoroinit_val[3]:0->1hTOP.tb_prbs_generator_verilator' 1
92
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl6n15ttogglepagev_toggle/tb_prbs_generator_verilatoroinit_val[3]:1->0hTOP.tb_prbs_generator_verilator' 0
93
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl6n15ttogglepagev_toggle/tb_prbs_generator_verilatoroinit_val[4]:0->1hTOP.tb_prbs_generator_verilator' 1
94
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl6n15ttogglepagev_toggle/tb_prbs_generator_verilatoroinit_val[4]:1->0hTOP.tb_prbs_generator_verilator' 0
95
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl6n15ttogglepagev_toggle/tb_prbs_generator_verilatoroinit_val[5]:0->1hTOP.tb_prbs_generator_verilator' 0
96
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl6n15ttogglepagev_toggle/tb_prbs_generator_verilatoroinit_val[5]:1->0hTOP.tb_prbs_generator_verilator' 0
97
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl6n15ttogglepagev_toggle/tb_prbs_generator_verilatoroinit_val[6]:0->1hTOP.tb_prbs_generator_verilator' 1
98
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl6n15ttogglepagev_toggle/tb_prbs_generator_verilatoroinit_val[6]:1->0hTOP.tb_prbs_generator_verilator' 0
99
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl6n26tlinepagev_line/tb_prbs_generator_verilatoroblockS6hTOP.tb_prbs_generator_verilator' 1
100
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl7n9ttogglepagev_toggle/tb_prbs_generator_verilatoroout:0->1hTOP.tb_prbs_generator_verilator' 34
101
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl7n9ttogglepagev_toggle/tb_prbs_generator_verilatoroout:1->0hTOP.tb_prbs_generator_verilator' 33
102
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl8n14tlinepagev_line/tb_prbs_generator_verilatoroblockS8hTOP.tb_prbs_generator_verilator' 1
103
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl8n26tlinepagev_line/tb_prbs_generator_verilatoroblockS8hTOP.tb_prbs_generator_verilator' 1
104
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl9n19texprpagev_expr/tb_prbs_generator_verilatoro(clk==0) => 1hTOP.tb_prbs_generator_verilator' 133
105
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl9n19texprpagev_expr/tb_prbs_generator_verilatoro(clk==1) => 0hTOP.tb_prbs_generator_verilator' 134
106
+ C 'ftestbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.svl9n3tlinepagev_line/tb_prbs_generator_verilatoroblockS9hTOP.tb_prbs_generator_verilator' 267
testbench/StanfordVLSI_dragonphy2_pr90/open_tool_p2p_buggy.log ADDED
@@ -0,0 +1,3 @@
 
 
 
 
1
+ INFO: open-tool P2P fallback (buggy)
2
+ INFO: native simulation P2P not applicable for this case
3
+ PASS: open-tool P2P fallback not applicable: no open-tool check passed
testbench/StanfordVLSI_dragonphy2_pr90/open_tool_p2p_fixed.log ADDED
@@ -0,0 +1,3 @@
 
 
 
 
1
+ INFO: open-tool P2P fallback (fixed)
2
+ INFO: native simulation P2P not applicable for this case
3
+ PASS: open-tool P2P fallback not applicable: no open-tool check passed
testbench/StanfordVLSI_dragonphy2_pr90/repo_native_buggy.log ADDED
@@ -0,0 +1 @@
 
 
1
+ PASS: repo native P2P smoke not applicable in buggy phase: no multi-file open-tool check passed
testbench/StanfordVLSI_dragonphy2_pr90/repo_native_fixed.log ADDED
@@ -0,0 +1 @@
 
 
1
+ PASS: repo native P2P smoke not applicable in fixed phase: no multi-file open-tool check passed
testbench/StanfordVLSI_dragonphy2_pr90/repo_native_source.path ADDED
@@ -0,0 +1 @@
 
 
1
+ tests/new_tests/ACORE/test.sv
testbench/StanfordVLSI_dragonphy2_pr90/run_once.sh ADDED
@@ -0,0 +1,4 @@
 
 
 
 
 
1
+ #!/bin/bash
2
+ set -u
3
+ HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)"
4
+ exec python3 "$HERE/../_run_once_from_run_verilator.py" "$HERE/run_verilator.sh"
testbench/StanfordVLSI_dragonphy2_pr90/run_verilator.sh ADDED
@@ -0,0 +1,59 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ #!/bin/bash
2
+ set -u
3
+ HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)"; cd "$HERE"
4
+ . "$HERE/../_testcase_minimum.sh"
5
+ . "$HERE/../_repo_native_p2p_smoke.sh"
6
+ export HWE_AUTO_COVERAGE=1
7
+ NAME=StanfordVLSI_dragonphy2_pr90
8
+ REPO_ROOT="$(cd "$HERE/../.." && pwd)"
9
+ SNAPSHOT="$REPO_ROOT/snapshots/$NAME"
10
+ PATCH_FILE="$REPO_ROOT/patches/$NAME.patch"
11
+ SCRATCH="$HERE/snapshot_scratch"
12
+ TARGET="vlog/new_tb/prbs_generator.sv"
13
+ PATCH_TARGETS=(
14
+ "$SCRATCH/inc/new_asic/iotype.sv"
15
+ "$SCRATCH/inc/new_cpu/iotype.sv"
16
+ "$SCRATCH/inc/new_cpu/voltage_net.sv"
17
+ "$SCRATCH/tests/new_tests/AC/test.sv"
18
+ "$SCRATCH/tests/new_tests/AC_REPLICA/test.sv"
19
+ "$SCRATCH/tests/new_tests/DC/test.sv"
20
+ "$SCRATCH/tests/new_tests/DC_REPLICA/test.sv"
21
+ "$SCRATCH/tests/new_tests/JTAG_HELLO/test.sv"
22
+ "$SCRATCH/tests/new_tests/PRBS/test.sv"
23
+ "$SCRATCH/tests/test_prbs_checker/test_prbs_checker.sv"
24
+ "$SCRATCH/tests/test_prbs_checker_core/test_prbs_checker_core.sv"
25
+ "$SCRATCH/vlog/new_chip_src/analog_core/analog_core.sv"
26
+ "$SCRATCH/vlog/new_chip_src/analog_core/stochastic_adc_PR.sv"
27
+ "$SCRATCH/vlog/new_chip_src/digital_core/digital_core.sv"
28
+ "$SCRATCH/vlog/new_chip_src/jtag/jtag.sv"
29
+ "$SCRATCH/vlog/new_chip_src/prbs/prbs_checker.sv"
30
+ "$SCRATCH/vlog/new_chip_src/prbs/prbs_checker_core.sv"
31
+ "$SCRATCH/vlog/new_chip_src/prbs/prbs_debug_intf.sv"
32
+ "$SCRATCH/vlog/new_chip_src/prbs/prbs_generator.sv"
33
+ "$SCRATCH/vlog/new_chip_src/top/dragonphy_top.sv"
34
+ "$SCRATCH/vlog/new_chip_stubs/analog_core/analog_core.sv"
35
+ "$SCRATCH/vlog/new_cpu_models/analog_core/V2T.sv"
36
+ "$SCRATCH/vlog/new_cpu_models/analog_core/biasgen.sv"
37
+ "$SCRATCH/vlog/new_pack/const_pack.sv"
38
+ "$SCRATCH/vlog/new_tb/prbs_generator.sv"
39
+ )
40
+ run_phase() {
41
+ local tag="$1"
42
+ rm -rf obj_dir verilator_${tag}_build.log verilator_${tag}.log
43
+ run_repo_native_p2p_smoke "$tag" || return $?
44
+ local src=""
45
+ [ -f "$SCRATCH/$TARGET" ] && src="$SCRATCH/$TARGET"
46
+ verilator --binary --timing --Wno-fatal --Wno-WIDTH --Wno-UNOPTFLAT --Wno-UNUSEDSIGNAL --Wno-UNUSEDPARAM --Wno-LATCH --Wno-STMTDLY --Wno-PINMISSING --Wno-PINCONNECTEMPTY --Wno-DECLFILENAME --Wno-CASEINCOMPLETE --timescale 1ns/1ps $src "$HERE/tb_prbs_generator_verilator.sv" --top-module tb_prbs_generator_verilator -o simv_vlt 2>&1 | tee verilator_${tag}_build.log >/dev/null
47
+ [ ! -x obj_dir/simv_vlt ] && return 2
48
+ timeout 20 ./obj_dir/simv_vlt 2>&1 | tee verilator_${tag}.log >/dev/null
49
+ grep -qE "(^|[^A-Za-z])PASS:" verilator_${tag}.log && ! grep -qE "(^|[^A-Za-z])FAIL:" verilator_${tag}.log && return 0
50
+ return 1
51
+ }
52
+ rm -rf "$SCRATCH"; cp -r "$SNAPSHOT" "$SCRATCH"; chmod -R u+w "$SCRATCH"
53
+ echo BUGGY; (cd "$SCRATCH" && patch -p1 -R -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true
54
+ run_phase buggy; rc_buggy=$?
55
+ rm -rf "$SCRATCH"; cp -r "$SNAPSHOT" "$SCRATCH"; chmod -R u+w "$SCRATCH"
56
+ echo FIXED; (cd "$SCRATCH" && patch -p1 -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true
57
+ run_phase fixed; rc_fixed=$?
58
+ echo "buggy:$rc_buggy fixed:$rc_fixed"
59
+ ([ "$rc_buggy" != "0" ]) && [ "$rc_fixed" = "0" ] && { hwe_report_min_testcases; hwe_report_real_verilator_coverage; echo "PASS: $NAME"; exit 0; } || { echo "FAIL: $NAME"; exit 1; }
testbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.sv ADDED
@@ -0,0 +1,37 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns/1ps
2
+ module tb_prbs_generator_verilator;
3
+ logic clk = 0;
4
+ logic rst = 1;
5
+ logic cke = 0;
6
+ logic [6:0] init_val = 7'h5A;
7
+ logic out;
8
+ int ones = 0, cycles = 0;
9
+ always #5 clk = ~clk;
10
+ prbs_generator #(.n_prbs(7)) dut (.clk(clk), .rst(rst), .cke(cke), .init_val(init_val), .out(out));
11
+ always @(posedge clk) begin
12
+ if (!rst && cke) begin
13
+ cycles++;
14
+ if (out) ones++;
15
+ end
16
+ end
17
+ initial begin
18
+ rst = 1; cke = 0;
19
+ @(posedge clk); @(posedge clk);
20
+ rst = 0; cke = 1;
21
+ repeat(127) @(posedge clk);
22
+ // coverage stimulus: hold cke low (rst==0) to exercise the idle hold branch
23
+ cke = 0;
24
+ repeat(4) @(posedge clk);
25
+ cke = 1;
26
+ @(posedge clk);
27
+ $display("cycles=%0d ones=%0d", cycles, ones);
28
+ if (cycles >= 100 && ones >= 40 && ones <= 90) begin
29
+ $display("PASS: T_COMPLETION directed testcase sequence completed");
30
+ $display("PASS: prbs_generator PRBS7 produces balanced output");
31
+ end else begin
32
+ $display("FAIL: unexpected ones count %0d for %0d cycles", ones, cycles);
33
+ end
34
+ $finish;
35
+ end
36
+ initial begin #5000; $display("FAIL: timeout"); $finish; end
37
+ endmodule
testbench/StanfordVLSI_dragonphy2_pr90/verilator_buggy_build.log ADDED
@@ -0,0 +1,29 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ %Error-MODMISSING: testbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.sv:10:3: Cannot find file containing module: 'prbs_generator'
2
+ 10 | prbs_generator #(.n_prbs(7)) dut (.clk(clk), .rst(rst), .cke(cke), .init_val(init_val), .out(out));
3
+ | ^~~~~~~~~~~~~~
4
+ ... For error description see https://verilator.org/warn/MODMISSING?v=5.047
5
+ ... This may be because there's no search path specified with -I<dir>.
6
+ ... Looked in:
7
+ prbs_generator
8
+ prbs_generator.v
9
+ prbs_generator.sv
10
+ obj_dir/prbs_generator
11
+ obj_dir/prbs_generator.v
12
+ obj_dir/prbs_generator.sv
13
+ ... With current working directory 'testbench/StanfordVLSI_dragonphy2_pr90'
14
+ %Error: Exiting due to 1 error(s)
15
+ HWE_AUTO_COVERAGE: retrying with --coverage-line
16
+ %Error-MODMISSING: testbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.sv:10:3: Cannot find file containing module: 'prbs_generator'
17
+ 10 | prbs_generator #(.n_prbs(7)) dut (.clk(clk), .rst(rst), .cke(cke), .init_val(init_val), .out(out));
18
+ | ^~~~~~~~~~~~~~
19
+ ... For error description see https://verilator.org/warn/MODMISSING?v=5.047
20
+ ... This may be because there's no search path specified with -I<dir>.
21
+ ... Looked in:
22
+ prbs_generator
23
+ prbs_generator.v
24
+ prbs_generator.sv
25
+ obj_dir/prbs_generator
26
+ obj_dir/prbs_generator.v
27
+ obj_dir/prbs_generator.sv
28
+ ... With current working directory 'testbench/StanfordVLSI_dragonphy2_pr90'
29
+ %Error: Exiting due to 1 error(s)
testbench/StanfordVLSI_dragonphy2_pr90/verilator_fixed.log ADDED
@@ -0,0 +1,4 @@
 
 
 
 
 
1
+ cycles=128 ones=65
2
+ PASS: T_COMPLETION directed testcase sequence completed
3
+ PASS: prbs_generator PRBS7 produces balanced output
4
+ - testbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.sv:34: Verilog $finish
testbench/StanfordVLSI_dragonphy2_pr90/verilator_fixed_build.log ADDED
@@ -0,0 +1,14 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ make: Entering directory 'testbench/StanfordVLSI_dragonphy2_pr90/obj_dir'
2
+ g++ -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -Os -c -o _coverage_main.o testbench/StanfordVLSI_dragonphy2_pr90/../_coverage_main.cpp
3
+ g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o verilated.o /opt/oss-cad-suite/share/verilator/include/verilated.cpp
4
+ g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o verilated_cov.o /opt/oss-cad-suite/share/verilator/include/verilated_cov.cpp
5
+ g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o verilated_timing.o /opt/oss-cad-suite/share/verilator/include/verilated_timing.cpp
6
+ g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o verilated_threads.o /opt/oss-cad-suite/share/verilator/include/verilated_threads.cpp
7
+ python3 /opt/oss-cad-suite/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vhwe_cov_top.cpp Vhwe_cov_top___024root__0.cpp Vhwe_cov_top___024root__Slow.cpp Vhwe_cov_top___024root__0__Slow.cpp Vhwe_cov_top__Syms__Slow.cpp > Vhwe_cov_top__ALL.cpp
8
+ g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -fcoroutines -c -o Vhwe_cov_top__ALL.o Vhwe_cov_top__ALL.cpp
9
+ g++ -Wl,-O2 -Wl,--sort-common -Wl,--as-needed -Wl,-z,relro -Wl,-z,now -Wl,--disable-new-dtags -Wl,--gc-sections -Wl,--allow-shlib-undefined -Wl,-rpath,/home/user/miniforge3/lib -Wl,-rpath-link,/home/user/miniforge3/lib -L/home/user/miniforge3/lib _coverage_main.o verilated.o verilated_cov.o verilated_timing.o verilated_threads.o Vhwe_cov_top__ALL.a -pthread -lpthread -latomic -o simv_vlt
10
+ rm Vhwe_cov_top__ALL.verilator_deplist.tmp
11
+ make: Leaving directory 'testbench/StanfordVLSI_dragonphy2_pr90/obj_dir'
12
+ - V e r i l a t i o n R e p o r t: Verilator 5.047 devel rev v5.046-293-ge82bd52fa (mod)
13
+ - Verilator: Built from 0.051 MB sources in 3 modules, into 0.082 MB in 5 C++ files needing 0.000 MB
14
+ - Verilator: Walltime 7.835 s (elab=0.001, cvt=0.004, bld=7.827); cpu 0.008 s on 1 threads; allocated 20.789 MB
testbench/StanfordVLSI_dragonphy2_pr90/verilator_fixed_coverage.info ADDED
@@ -0,0 +1,154 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ TN:verilator_coverage
2
+ SF:testbench/StanfordVLSI_dragonphy2_pr90/snapshot_scratch/vlog/new_tb/prbs_generator.sv
3
+ DA:4,134
4
+ BRDA:4,0,0,134
5
+ BRDA:4,0,1,133
6
+ DA:5,1
7
+ BRDA:5,0,0,1
8
+ BRDA:5,0,1,1
9
+ DA:6,2
10
+ BRDA:6,0,0,2
11
+ BRDA:6,0,1,1
12
+ DA:7,1
13
+ BRDA:7,0,0,0
14
+ BRDA:7,0,1,0
15
+ BRDA:7,0,2,1
16
+ BRDA:7,0,3,0
17
+ BRDA:7,0,4,0
18
+ BRDA:7,0,5,0
19
+ BRDA:7,0,6,1
20
+ BRDA:7,0,7,0
21
+ BRDA:7,0,8,1
22
+ BRDA:7,0,9,0
23
+ BRDA:7,0,10,0
24
+ BRDA:7,0,11,0
25
+ BRDA:7,0,12,1
26
+ BRDA:7,0,13,0
27
+ DA:8,34
28
+ BRDA:8,0,0,34
29
+ BRDA:8,0,1,33
30
+ DA:12,34
31
+ BRDA:12,0,0,33
32
+ BRDA:12,0,1,32
33
+ BRDA:12,0,2,34
34
+ BRDA:12,0,3,33
35
+ BRDA:12,0,4,33
36
+ BRDA:12,0,5,33
37
+ BRDA:12,0,6,34
38
+ BRDA:12,0,7,33
39
+ BRDA:12,0,8,33
40
+ BRDA:12,0,9,33
41
+ BRDA:12,0,10,33
42
+ BRDA:12,0,11,32
43
+ BRDA:12,0,12,34
44
+ BRDA:12,0,13,33
45
+ DA:16,33
46
+ BRDA:16,0,0,33
47
+ BRDA:16,0,1,33
48
+ DA:46,34
49
+ BRDA:46,0,0,33
50
+ BRDA:46,0,1,33
51
+ BRDA:46,0,2,33
52
+ BRDA:46,0,3,32
53
+ BRDA:46,0,4,34
54
+ BRDA:46,0,5,33
55
+ BRDA:46,0,6,33
56
+ BRDA:46,0,7,33
57
+ BRDA:46,0,8,34
58
+ BRDA:46,0,9,33
59
+ BRDA:46,0,10,33
60
+ BRDA:46,0,11,33
61
+ BRDA:46,0,12,33
62
+ BRDA:46,0,13,32
63
+ DA:50,134
64
+ DA:51,1
65
+ DA:52,1
66
+ DA:53,129
67
+ BRDA:53,0,0,129
68
+ BRDA:53,0,1,4
69
+ DA:54,129
70
+ DA:55,4
71
+ DA:56,4
72
+ BRF:54
73
+ BRH:35
74
+ end_of_record
75
+ SF:testbench/StanfordVLSI_dragonphy2_pr90/tb_prbs_generator_verilator.sv
76
+ DA:3,134
77
+ BRDA:3,0,0,1
78
+ BRDA:3,0,1,134
79
+ BRDA:3,0,2,133
80
+ DA:4,1
81
+ BRDA:4,0,0,1
82
+ BRDA:4,0,1,1
83
+ BRDA:4,0,2,1
84
+ DA:5,2
85
+ BRDA:5,0,0,1
86
+ BRDA:5,0,1,2
87
+ BRDA:5,0,2,1
88
+ DA:6,1
89
+ BRDA:6,0,0,0
90
+ BRDA:6,0,1,0
91
+ BRDA:6,0,2,1
92
+ BRDA:6,0,3,0
93
+ BRDA:6,0,4,0
94
+ BRDA:6,0,5,0
95
+ BRDA:6,0,6,1
96
+ BRDA:6,0,7,0
97
+ BRDA:6,0,8,1
98
+ BRDA:6,0,9,0
99
+ BRDA:6,0,10,0
100
+ BRDA:6,0,11,0
101
+ BRDA:6,0,12,1
102
+ BRDA:6,0,13,0
103
+ BRDA:6,0,14,1
104
+ DA:7,34
105
+ BRDA:7,0,0,34
106
+ BRDA:7,0,1,33
107
+ DA:8,1
108
+ BRDA:8,0,0,1
109
+ BRDA:8,0,1,1
110
+ DA:9,267
111
+ BRDA:9,0,0,133
112
+ BRDA:9,0,1,134
113
+ BRDA:9,0,2,267
114
+ DA:11,134
115
+ DA:12,129
116
+ BRDA:12,0,0,5
117
+ BRDA:12,0,1,129
118
+ BRDA:12,0,2,1
119
+ BRDA:12,0,3,129
120
+ BRDA:12,0,4,5
121
+ DA:13,129
122
+ DA:14,65
123
+ BRDA:14,0,0,65
124
+ BRDA:14,0,1,64
125
+ DA:17,1
126
+ DA:18,1
127
+ DA:19,1
128
+ DA:20,1
129
+ DA:21,127
130
+ BRDA:21,0,0,1
131
+ BRDA:21,0,1,127
132
+ DA:23,1
133
+ DA:24,4
134
+ BRDA:24,0,0,1
135
+ BRDA:24,0,1,4
136
+ DA:25,1
137
+ DA:26,1
138
+ DA:27,1
139
+ DA:28,1
140
+ BRDA:28,0,0,0
141
+ BRDA:28,0,1,1
142
+ BRDA:28,0,2,0
143
+ BRDA:28,0,3,0
144
+ BRDA:28,0,4,1
145
+ BRDA:28,0,5,0
146
+ DA:29,1
147
+ DA:30,1
148
+ DA:31,0
149
+ DA:32,0
150
+ DA:34,1
151
+ DA:36,0
152
+ BRF:48
153
+ BRH:12
154
+ end_of_record
testbench/hdl-util_hdmi_pr30/tb_hdmi_vsync_timing.sv ADDED
@@ -0,0 +1,88 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `default_nettype none
2
+
3
+ module tb_hdmi_vsync_timing;
4
+ logic clk_pixel;
5
+ logic clk_pixel_x5;
6
+ logic clk_audio;
7
+ logic reset;
8
+ logic [23:0] rgb;
9
+ logic [15:0] audio_sample_word [1:0];
10
+ logic [2:0] tmds;
11
+ logic tmds_clock;
12
+ logic [10:0] cx;
13
+ logic [9:0] cy;
14
+ logic [10:0] frame_width;
15
+ logic [9:0] frame_height;
16
+ logic [10:0] screen_width;
17
+ logic [9:0] screen_height;
18
+
19
+ initial clk_pixel = 1'b0;
20
+ initial clk_pixel_x5 = 1'b0;
21
+ initial clk_audio = 1'b0;
22
+ always #1 clk_pixel = ~clk_pixel;
23
+ always #1 clk_pixel_x5 = ~clk_pixel_x5;
24
+ always #5 clk_audio = ~clk_audio;
25
+
26
+ hdmi #(
27
+ .VIDEO_ID_CODE(4),
28
+ .DVI_OUTPUT(1'b1),
29
+ .START_X(1389),
30
+ .START_Y(725)
31
+ ) dut (
32
+ .clk_pixel_x5 (clk_pixel_x5),
33
+ .clk_pixel (clk_pixel),
34
+ .clk_audio (clk_audio),
35
+ .reset (reset),
36
+ .rgb (rgb),
37
+ .audio_sample_word(audio_sample_word),
38
+ .tmds (tmds),
39
+ .tmds_clock (tmds_clock),
40
+ .cx (cx),
41
+ .cy (cy),
42
+ .frame_width (frame_width),
43
+ .frame_height (frame_height),
44
+ .screen_width (screen_width),
45
+ .screen_height (screen_height)
46
+ );
47
+
48
+ initial begin
49
+ reset = 1'b0;
50
+ rgb = 24'h0;
51
+ audio_sample_word[0] = 16'h0;
52
+ audio_sample_word[1] = 16'h0;
53
+
54
+ #1;
55
+ if (dut.vsync !== 1'b0) begin
56
+ $display("FAIL: hdmi PR30 vsync starts before the leading edge of hsync");
57
+ $fatal(1, "vsync must remain deasserted until cx reaches screen_width + hsync_pulse_start");
58
+ end
59
+
60
+ @(posedge clk_pixel);
61
+ #1;
62
+ if (dut.vsync !== 1'b1 || dut.hsync !== 1'b1) begin
63
+ $display("FAIL: hdmi PR30 vsync did not align with the hsync leading edge");
64
+ $fatal(1, "vsync must assert at the same coordinate as hsync");
65
+ end
66
+
67
+ // Coverage stimulus: advance the pixel-position counters until cy reaches
68
+ // the vsync end-line (screen_height + vsync_pulse_start + vsync_pulse_size)
69
+ // so the special end-of-vsync branch (rtl line 197/198) is exercised.
70
+ begin : walk_to_vsync_end
71
+ automatic int unsigned guard = 0;
72
+ while (dut.cy !== (dut.screen_height + dut.vsync_pulse_start + dut.vsync_pulse_size)
73
+ && guard < 200000) begin
74
+ @(posedge clk_pixel);
75
+ guard++;
76
+ end
77
+ // Step a few more cycles across the end-line so the branch is evaluated
78
+ // for several cx positions (both sides of the cx comparison).
79
+ repeat (8) @(posedge clk_pixel);
80
+ end
81
+
82
+ $display("PASS: T_COMPLETION directed testcase sequence completed");
83
+ $display("PASS: hdmi PR30 vsync aligns to hsync leading edge");
84
+ $finish;
85
+ end
86
+ endmodule
87
+
88
+ `default_nettype wire