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snapshots/lowRISC_ibex_pr2214/vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_13.c

@@ -0,0 +1,318 @@
+
+/*
+ * outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_13.c
+ * Generated from gen_pmp_test.cc and test_pmp_csr_1.cc_skel.
+ * 
+ * This test program is verify the pmp CSR access when seccfg introduced.
+ * It's expected to executed from M mode.
+ * 
+ * Remarks:
+ * - CSR protection for non-M mode access is assumed and not coverred.
+ * - The access on invalid CSR index like pmpcfg1 for rv64 is not coverred.
+ * - Executed on RV64 only.
+ */
+
+/*
+ * Macros from encoding.h
+ */
+#define MSTATUS_MPP         0x00001800
+
+#define PMP_R     0x01
+#define PMP_W     0x02
+#define PMP_X     0x04
+#define PMP_A     0x18
+#define PMP_L     0x80
+#define PMP_SHIFT 2
+
+#if ((PMP_R | PMP_W | PMP_X) != 0x7)
+#error unexpected
+#endif
+
+#define PMP_OFF   0x0
+#define PMP_TOR   0x08
+#define PMP_NA4   0x10
+#define PMP_NAPOT 0x18
+
+#define MSECCFG_MML  0x1
+#define MSECCFG_MMWP 0x2
+#define MSECCFG_RLB  0x4
+
+#define TEST_RW 1
+#define TEST_FETCH 1
+/*
+ * Whether rwx share single cfg for M mode
+ * When @set_sec_mml@ set, it must be 0, otherwise unexpected exception
+ */
+#define M_MODE_RWX 0
+
+#define CAUSE_LOAD_ACCESS 0x5
+#define CAUSE_STORE_ACCESS 0x7
+
+typedef unsigned long reg_t;
+typedef unsigned long uintptr_t;
+
+/*
+ * functions from syscalls.c
+ */
+#if PRINTF_SUPPORTED
+int printf(const char* fmt, ...);
+#else
+#define printf(...)
+#endif
+
+void __attribute__((noreturn)) tohost_exit(uintptr_t code);
+void exit(int code);
+
+/*
+ * local status
+ */
+#define TEST_MEM_START 0x80200000
+#define TEST_MEM_END 0x80240000
+#define U_MEM_END (TEST_MEM_END + 0x10000)
+#define FAKE_ADDRESS 0x10000000
+
+static const unsigned long expected_seccfg_fail = 0;
+static unsigned actual_seccfg_fail = 0;
+
+static const unsigned long expected_pmpaddr_fail = 0;
+static unsigned actual_pmpaddr_fail = 0;
+
+static const unsigned long expected_pmpcfg_fail = 0;
+static unsigned actual_pmpcfg_fail = 0;
+
+static void checkTestResult(void);
+
+/*
+ * override syscalls.c.
+ *  currently simply skip to nexp instruction
+ */
+uintptr_t handle_trap(uintptr_t cause, uintptr_t epc, uintptr_t regs[32])
+{ 
+    tohost_exit(1337);
+}
+
+
+__attribute ((section(".text_test_foo"), noinline))
+void target_foo() {
+    asm volatile ("nop");
+}
+
+__attribute ((section(".data_test_arr"), aligned(8)))
+volatile unsigned char target_arr[100] = {
+        1,2,3,4,5,6,7,8,
+};
+
+__attribute ((section(".text_umode"), noinline))
+void target_foo_U() {
+    asm volatile ("nop");
+}
+
+__attribute ((section(".data_umode"), aligned(8)))
+volatile unsigned char target_arr_U[100] = {
+        1,2,3,4,5,6,7,8,
+};
+
+/*
+ * On processor_t::reset():
+ *  - set_csr(CSR_PMPADDR0, ~reg_t(0));
+ *    set_csr(CSR_PMPCFG0, PMP_R | PMP_W | PMP_X | PMP_NAPOT);
+ */
+static void set_cfg() {
+#if 1 // @set_rlb_at_start:int@
+    /*
+     * set MSECCFG_RLB to avoid locked at start
+     */
+    asm volatile ("csrs 0x747, %0 \n"::"r"(MSECCFG_RLB));
+    asm volatile ("nop");
+#endif
+    
+//------------------------Set current status before the test target (CSR access)
+    /*
+     * Set pmp0cfg for M mode (M_MEM), and pmp1cfg for base of TOR.
+     * Then use pmp2cfg for TEST_MEM. Both test code and data share PMP entrance.
+     * Also use pmp3cfg for fixed U mode (U_MEM).
+     */
+    asm volatile ("csrw pmpaddr7, %0 \n" :: "r"(0x8ffffff8 >> 2) : "memory");       // for ibex signature addr
+    asm volatile ("csrw pmpaddr3, %0 \n" :: "r"(U_MEM_END >> 2) : "memory");
+    asm volatile ("csrw pmpaddr2, %0 \n" :: "r"(TEST_MEM_END >> 2) : "memory");
+    asm volatile ("csrw pmpaddr1, %0 \n" :: "r"(TEST_MEM_START >> 2) : "memory");
+    
+#if M_MODE_RWX
+    asm volatile ("csrw pmpaddr0, %0 \n" :: "r"((0x80000000 >> 2) | 0xfffff) : "memory");
+    reg_t cfg0 = (PMP_R | PMP_W | PMP_X | PMP_NAPOT);
+    reg_t cfg1 = (PMP_R | PMP_W | PMP_NAPOT) << 24;
+#else
+    asm volatile ("csrw pmpaddr6, %0 \n" :: "r"(TEST_MEM_START >> 2) : "memory");   // for data
+    asm volatile ("csrw pmpaddr5, %0 \n" :: "r"(0x80010000 >> 2) : "memory");       // for code
+    asm volatile ("csrw pmpaddr4, %0 \n" :: "r"(0x80000000 >> 2) : "memory");       // addr start
+    reg_t cfg0 = PMP_OFF;
+    reg_t cfg1 = PMP_OFF | ((PMP_R | PMP_W | PMP_NAPOT) << 24)
+                         | ((PMP_R | PMP_W | PMP_TOR) << 16) 
+                         | ((PMP_X | PMP_TOR) << 8);
+#endif
+
+    if (0) {    // need to set L bit for M mode code access
+#if M_MODE_RWX
+        cfg0 |= PMP_L;
+        cfg1 |= (PMP_L << 24);
+#else
+        cfg1 |= ((PMP_L << 8) | (PMP_L << 16) | (PMP_L << 24));
+#endif
+    }
+    
+    reg_t sub_cfg = PMP_R | PMP_W | PMP_X | PMP_TOR | ((0 || 0) ? PMP_L : 0);
+    cfg0 |= sub_cfg << 24;    // for U_MEM
+    cfg0 |= sub_cfg << 16;    // for TEST_MEM
+    
+#if __riscv_xlen == 64
+    cfg0 |= (cfg1 << 32);
+#else
+    asm volatile ("csrw pmpcfg1, %0 \n"
+                :
+                : "r"(cfg1)
+                : "memory");
+#endif // __riscv_xlen == 64
+    
+    asm volatile ("csrw pmpcfg0, %0 \n"
+                :
+                : "r"(cfg0)
+                : "memory");
+
+    if (0 != 0) {
+        reg_t lock_bits = (PMP_L << 16) | ((reg_t)PMP_L << 24); // avoid use (default) int type
+        if (0) {
+            asm volatile ("csrs pmpcfg0, %0 \n"
+                            :
+                            : "r"(lock_bits)
+                            : "memory");
+        } else {
+            asm volatile ("csrc pmpcfg0, %0 \n"
+                            :
+                            : "r"(lock_bits)
+                            : "memory");
+        }
+    }
+    
+    // set proc->state.mseccfg
+    const unsigned seccfg_bits = (1 ? MSECCFG_RLB : 0) 
+            | (0 ? MSECCFG_MML : 0) 
+            | (1 ? MSECCFG_MMWP : 0);
+    asm volatile ("csrw 0x747, %0 \n"::"r"(seccfg_bits));
+    
+//------------------------Test target
+    asm volatile ("nop");
+    /*
+     * Need to separate pmp and seccfg access since pmplock_recorded status may be 
+     * updated again when accessing pmpcfg.
+     */
+    reg_t wval = 0, rval;
+    reg_t prev_val = 0;
+#if 1
+    asm volatile ("csrr %0, pmpaddr7 \n"
+            : "=r"(rval));
+    // give a valid value for both NAPOT and TOR
+    if (7 == 0) {
+        wval = ((rval + 1) << 1) - 1;   // NAPOT mask
+    } else {
+        wval = (rval << 1) + 65536;   
+    }
+    prev_val = rval;
+    asm volatile ("csrw pmpaddr7, %1 \n"
+                "\tcsrr %0, pmpaddr7 \n"
+            : "=r"(rval)
+            : "r"(wval)
+              : "memory");
+    if (wval != rval) {
+        actual_pmpaddr_fail = 1;
+    }
+    asm volatile ("csrw pmpaddr7, %0 \n"
+            :: "r"(prev_val));
+    // Update cfg0 to avoid changing idx other than 2
+    asm volatile ("csrr %0, pmpcfg2 \n"
+                    : "=r"(cfg0)
+                    :
+                    : "memory");
+    
+    // reuse lock_once here since it's for RLB and independent with pmp_lock
+    wval = cfg0 ^ ((reg_t)(3 | (0 ? PMP_L : 0)) << (2 * 8));
+    asm volatile ("csrw pmpcfg2, %1 \n"
+                "\tcsrr %0, pmpcfg2 \n"
+            : "=r"(rval)
+            : "r"(wval)
+              : "memory");
+    if (wval != rval) {
+        actual_pmpcfg_fail = 1;
+    }
+#else
+    /*
+     * need to set PMP_L for cfg0 otherwise next PC will illegal
+     * This is a little coverage hole for non-PMP_L + mml, which should be
+     * a restricted use case and can be accepted anyway.
+     */ 
+    if (1) {    
+#if M_MODE_RWX
+        asm volatile ("csrs pmpcfg0, %0 \n"::"r"(PMP_L));
+#else
+#if __riscv_xlen == 64
+        asm volatile ("csrs pmpcfg0, %0 \n"::"r"(((reg_t)PMP_L << 40) | ((reg_t)PMP_L << 48)));
+#else
+        asm volatile ("csrs pmpcfg1, %0 \n"::"r"((PMP_L << 8) | (PMP_L << 16) | (PMP_L << 24)));
+#endif // __riscv_xlen == 64
+#endif // M_MODE_RWX
+    }
+    
+    wval = (1 ? MSECCFG_RLB : 0) 
+            | (1 ? MSECCFG_MML : 0) 
+            | (1 ? MSECCFG_MMWP : 0);
+    asm volatile ("csrw 0x747, %1 \n"
+                "\tcsrr %0, 0x747 \n"
+            : "=r"(rval)
+            : "r"(wval)
+              : "memory");
+    reg_t expected_val = wval & (MSECCFG_RLB | MSECCFG_MML | MSECCFG_MMWP);
+    /*
+     * pre_sec_mml means cfg0 locked
+     * pmp_lock means cfg2/3 locked
+     * sec_mml is the test coverage hole just mentioned
+     */
+    if ((0 || 0 || 1) 
+            && 1 == 0) {
+        expected_val &= ~MSECCFG_RLB;
+    } 
+    if (0) {
+        expected_val |= MSECCFG_MML;
+    }
+    if (1) {
+        expected_val |= MSECCFG_MMWP;
+    }
+    
+    if (expected_val != rval) actual_seccfg_fail = 1;
+#endif
+}
+
+static void checkTestResult() {
+    int ret = 0;
+    if (expected_seccfg_fail != actual_seccfg_fail) {
+        ret += 1;
+    }
+
+    if (expected_pmpaddr_fail != actual_pmpaddr_fail) {
+        ret += 2;
+    }
+    
+    if (expected_pmpcfg_fail != actual_pmpcfg_fail) {
+        ret += 4;
+    }
+    
+    
+    exit(ret); 
+}
+
+int main() {
+    // assert in M mode
+    set_cfg();
+
+    checkTestResult();
+    return 0; // assert 0
+}
+

snapshots/lowRISC_ibex_pr2214/vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_02.c

@@ -0,0 +1,318 @@
+
+/*
+ * outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_02.c
+ * Generated from gen_pmp_test.cc and test_pmp_csr_1.cc_skel.
+ * 
+ * This test program is verify the pmp CSR access when seccfg introduced.
+ * It's expected to executed from M mode.
+ * 
+ * Remarks:
+ * - CSR protection for non-M mode access is assumed and not coverred.
+ * - The access on invalid CSR index like pmpcfg1 for rv64 is not coverred.
+ * - Executed on RV64 only.
+ */
+
+/*
+ * Macros from encoding.h
+ */
+#define MSTATUS_MPP         0x00001800
+
+#define PMP_R     0x01
+#define PMP_W     0x02
+#define PMP_X     0x04
+#define PMP_A     0x18
+#define PMP_L     0x80
+#define PMP_SHIFT 2
+
+#if ((PMP_R | PMP_W | PMP_X) != 0x7)
+#error unexpected
+#endif
+
+#define PMP_OFF   0x0
+#define PMP_TOR   0x08
+#define PMP_NA4   0x10
+#define PMP_NAPOT 0x18
+
+#define MSECCFG_MML  0x1
+#define MSECCFG_MMWP 0x2
+#define MSECCFG_RLB  0x4
+
+#define TEST_RW 1
+#define TEST_FETCH 1
+/*
+ * Whether rwx share single cfg for M mode
+ * When @set_sec_mml@ set, it must be 0, otherwise unexpected exception
+ */
+#define M_MODE_RWX 0
+
+#define CAUSE_LOAD_ACCESS 0x5
+#define CAUSE_STORE_ACCESS 0x7
+
+typedef unsigned long reg_t;
+typedef unsigned long uintptr_t;
+
+/*
+ * functions from syscalls.c
+ */
+#if PRINTF_SUPPORTED
+int printf(const char* fmt, ...);
+#else
+#define printf(...)
+#endif
+
+void __attribute__((noreturn)) tohost_exit(uintptr_t code);
+void exit(int code);
+
+/*
+ * local status
+ */
+#define TEST_MEM_START 0x80200000
+#define TEST_MEM_END 0x80240000
+#define U_MEM_END (TEST_MEM_END + 0x10000)
+#define FAKE_ADDRESS 0x10000000
+
+static const unsigned long expected_seccfg_fail = 0;
+static unsigned actual_seccfg_fail = 0;
+
+static const unsigned long expected_pmpaddr_fail = 0;
+static unsigned actual_pmpaddr_fail = 0;
+
+static const unsigned long expected_pmpcfg_fail = 0;
+static unsigned actual_pmpcfg_fail = 0;
+
+static void checkTestResult(void);
+
+/*
+ * override syscalls.c.
+ *  currently simply skip to nexp instruction
+ */
+uintptr_t handle_trap(uintptr_t cause, uintptr_t epc, uintptr_t regs[32])
+{ 
+    tohost_exit(1337);
+}
+
+
+__attribute ((section(".text_test_foo"), noinline))
+void target_foo() {
+    asm volatile ("nop");
+}
+
+__attribute ((section(".data_test_arr"), aligned(8)))
+volatile unsigned char target_arr[100] = {
+        1,2,3,4,5,6,7,8,
+};
+
+__attribute ((section(".text_umode"), noinline))
+void target_foo_U() {
+    asm volatile ("nop");
+}
+
+__attribute ((section(".data_umode"), aligned(8)))
+volatile unsigned char target_arr_U[100] = {
+        1,2,3,4,5,6,7,8,
+};
+
+/*
+ * On processor_t::reset():
+ *  - set_csr(CSR_PMPADDR0, ~reg_t(0));
+ *    set_csr(CSR_PMPCFG0, PMP_R | PMP_W | PMP_X | PMP_NAPOT);
+ */
+static void set_cfg() {
+#if 1 // @set_rlb_at_start:int@
+    /*
+     * set MSECCFG_RLB to avoid locked at start
+     */
+    asm volatile ("csrs 0x747, %0 \n"::"r"(MSECCFG_RLB));
+    asm volatile ("nop");
+#endif
+    
+//------------------------Set current status before the test target (CSR access)
+    /*
+     * Set pmp0cfg for M mode (M_MEM), and pmp1cfg for base of TOR.
+     * Then use pmp2cfg for TEST_MEM. Both test code and data share PMP entrance.
+     * Also use pmp3cfg for fixed U mode (U_MEM).
+     */
+    asm volatile ("csrw pmpaddr7, %0 \n" :: "r"(0x8ffffff8 >> 2) : "memory");       // for ibex signature addr
+    asm volatile ("csrw pmpaddr3, %0 \n" :: "r"(U_MEM_END >> 2) : "memory");
+    asm volatile ("csrw pmpaddr2, %0 \n" :: "r"(TEST_MEM_END >> 2) : "memory");
+    asm volatile ("csrw pmpaddr1, %0 \n" :: "r"(TEST_MEM_START >> 2) : "memory");
+    
+#if M_MODE_RWX
+    asm volatile ("csrw pmpaddr0, %0 \n" :: "r"((0x80000000 >> 2) | 0xfffff) : "memory");
+    reg_t cfg0 = (PMP_R | PMP_W | PMP_X | PMP_NAPOT);
+    reg_t cfg1 = (PMP_R | PMP_W | PMP_NAPOT) << 24;
+#else
+    asm volatile ("csrw pmpaddr6, %0 \n" :: "r"(TEST_MEM_START >> 2) : "memory");   // for data
+    asm volatile ("csrw pmpaddr5, %0 \n" :: "r"(0x80010000 >> 2) : "memory");       // for code
+    asm volatile ("csrw pmpaddr4, %0 \n" :: "r"(0x80000000 >> 2) : "memory");       // addr start
+    reg_t cfg0 = PMP_OFF;
+    reg_t cfg1 = PMP_OFF | ((PMP_R | PMP_W | PMP_NAPOT) << 24)
+                         | ((PMP_R | PMP_W | PMP_TOR) << 16) 
+                         | ((PMP_X | PMP_TOR) << 8);
+#endif
+
+    if (1) {    // need to set L bit for M mode code access
+#if M_MODE_RWX
+        cfg0 |= PMP_L;
+        cfg1 |= (PMP_L << 24);
+#else
+        cfg1 |= ((PMP_L << 8) | (PMP_L << 16) | (PMP_L << 24));
+#endif
+    }
+    
+    reg_t sub_cfg = PMP_R | PMP_W | PMP_X | PMP_TOR | ((1 || 0) ? PMP_L : 0);
+    cfg0 |= sub_cfg << 24;    // for U_MEM
+    cfg0 |= sub_cfg << 16;    // for TEST_MEM
+    
+#if __riscv_xlen == 64
+    cfg0 |= (cfg1 << 32);
+#else
+    asm volatile ("csrw pmpcfg1, %0 \n"
+                :
+                : "r"(cfg1)
+                : "memory");
+#endif // __riscv_xlen == 64
+    
+    asm volatile ("csrw pmpcfg0, %0 \n"
+                :
+                : "r"(cfg0)
+                : "memory");
+
+    if (1 != 0) {
+        reg_t lock_bits = (PMP_L << 16) | ((reg_t)PMP_L << 24); // avoid use (default) int type
+        if (0) {
+            asm volatile ("csrs pmpcfg0, %0 \n"
+                            :
+                            : "r"(lock_bits)
+                            : "memory");
+        } else {
+            asm volatile ("csrc pmpcfg0, %0 \n"
+                            :
+                            : "r"(lock_bits)
+                            : "memory");
+        }
+    }
+    
+    // set proc->state.mseccfg
+    const unsigned seccfg_bits = (1 ? MSECCFG_RLB : 0) 
+            | (1 ? MSECCFG_MML : 0) 
+            | (0 ? MSECCFG_MMWP : 0);
+    asm volatile ("csrw 0x747, %0 \n"::"r"(seccfg_bits));
+    
+//------------------------Test target
+    asm volatile ("nop");
+    /*
+     * Need to separate pmp and seccfg access since pmplock_recorded status may be 
+     * updated again when accessing pmpcfg.
+     */
+    reg_t wval = 0, rval;
+    reg_t prev_val = 0;
+#if 1
+    asm volatile ("csrr %0, pmpaddr2 \n"
+            : "=r"(rval));
+    // give a valid value for both NAPOT and TOR
+    if (2 == 0) {
+        wval = ((rval + 1) << 1) - 1;   // NAPOT mask
+    } else {
+        wval = (rval << 1) + 0;   
+    }
+    prev_val = rval;
+    asm volatile ("csrw pmpaddr2, %1 \n"
+                "\tcsrr %0, pmpaddr2 \n"
+            : "=r"(rval)
+            : "r"(wval)
+              : "memory");
+    if (wval != rval) {
+        actual_pmpaddr_fail = 1;
+    }
+    asm volatile ("csrw pmpaddr2, %0 \n"
+            :: "r"(prev_val));
+    // Update cfg0 to avoid changing idx other than 2
+    asm volatile ("csrr %0, pmpcfg0 \n"
+                    : "=r"(cfg0)
+                    :
+                    : "memory");
+    
+    // reuse lock_once here since it's for RLB and independent with pmp_lock
+    wval = cfg0 ^ ((reg_t)(2 | (1 ? PMP_L : 0)) << (2 * 8));
+    asm volatile ("csrw pmpcfg0, %1 \n"
+                "\tcsrr %0, pmpcfg0 \n"
+            : "=r"(rval)
+            : "r"(wval)
+              : "memory");
+    if (wval != rval) {
+        actual_pmpcfg_fail = 1;
+    }
+#else
+    /*
+     * need to set PMP_L for cfg0 otherwise next PC will illegal
+     * This is a little coverage hole for non-PMP_L + mml, which should be
+     * a restricted use case and can be accepted anyway.
+     */ 
+    if (1) {    
+#if M_MODE_RWX
+        asm volatile ("csrs pmpcfg0, %0 \n"::"r"(PMP_L));
+#else
+#if __riscv_xlen == 64
+        asm volatile ("csrs pmpcfg0, %0 \n"::"r"(((reg_t)PMP_L << 40) | ((reg_t)PMP_L << 48)));
+#else
+        asm volatile ("csrs pmpcfg1, %0 \n"::"r"((PMP_L << 8) | (PMP_L << 16) | (PMP_L << 24)));
+#endif // __riscv_xlen == 64
+#endif // M_MODE_RWX
+    }
+    
+    wval = (1 ? MSECCFG_RLB : 0) 
+            | (1 ? MSECCFG_MML : 0) 
+            | (1 ? MSECCFG_MMWP : 0);
+    asm volatile ("csrw 0x747, %1 \n"
+                "\tcsrr %0, 0x747 \n"
+            : "=r"(rval)
+            : "r"(wval)
+              : "memory");
+    reg_t expected_val = wval & (MSECCFG_RLB | MSECCFG_MML | MSECCFG_MMWP);
+    /*
+     * pre_sec_mml means cfg0 locked
+     * pmp_lock means cfg2/3 locked
+     * sec_mml is the test coverage hole just mentioned
+     */
+    if ((1 || 0 || 1) 
+            && 1 == 0) {
+        expected_val &= ~MSECCFG_RLB;
+    } 
+    if (1) {
+        expected_val |= MSECCFG_MML;
+    }
+    if (0) {
+        expected_val |= MSECCFG_MMWP;
+    }
+    
+    if (expected_val != rval) actual_seccfg_fail = 1;
+#endif
+}
+
+static void checkTestResult() {
+    int ret = 0;
+    if (expected_seccfg_fail != actual_seccfg_fail) {
+        ret += 1;
+    }
+
+    if (expected_pmpaddr_fail != actual_pmpaddr_fail) {
+        ret += 2;
+    }
+    
+    if (expected_pmpcfg_fail != actual_pmpcfg_fail) {
+        ret += 4;
+    }
+    
+    
+    exit(ret); 
+}
+
+int main() {
+    // assert in M mode
+    set_cfg();
+
+    checkTestResult();
+    return 0; // assert 0
+}
+

snapshots/lowRISC_ibex_pr2214/vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_12.c

@@ -0,0 +1,318 @@
+
+/*
+ * outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_12.c
+ * Generated from gen_pmp_test.cc and test_pmp_csr_1.cc_skel.
+ * 
+ * This test program is verify the pmp CSR access when seccfg introduced.
+ * It's expected to executed from M mode.
+ * 
+ * Remarks:
+ * - CSR protection for non-M mode access is assumed and not coverred.
+ * - The access on invalid CSR index like pmpcfg1 for rv64 is not coverred.
+ * - Executed on RV64 only.
+ */
+
+/*
+ * Macros from encoding.h
+ */
+#define MSTATUS_MPP         0x00001800
+
+#define PMP_R     0x01
+#define PMP_W     0x02
+#define PMP_X     0x04
+#define PMP_A     0x18
+#define PMP_L     0x80
+#define PMP_SHIFT 2
+
+#if ((PMP_R | PMP_W | PMP_X) != 0x7)
+#error unexpected
+#endif
+
+#define PMP_OFF   0x0
+#define PMP_TOR   0x08
+#define PMP_NA4   0x10
+#define PMP_NAPOT 0x18
+
+#define MSECCFG_MML  0x1
+#define MSECCFG_MMWP 0x2
+#define MSECCFG_RLB  0x4
+
+#define TEST_RW 1
+#define TEST_FETCH 1
+/*
+ * Whether rwx share single cfg for M mode
+ * When @set_sec_mml@ set, it must be 0, otherwise unexpected exception
+ */
+#define M_MODE_RWX 0
+
+#define CAUSE_LOAD_ACCESS 0x5
+#define CAUSE_STORE_ACCESS 0x7
+
+typedef unsigned long reg_t;
+typedef unsigned long uintptr_t;
+
+/*
+ * functions from syscalls.c
+ */
+#if PRINTF_SUPPORTED
+int printf(const char* fmt, ...);
+#else
+#define printf(...)
+#endif
+
+void __attribute__((noreturn)) tohost_exit(uintptr_t code);
+void exit(int code);
+
+/*
+ * local status
+ */
+#define TEST_MEM_START 0x80200000
+#define TEST_MEM_END 0x80240000
+#define U_MEM_END (TEST_MEM_END + 0x10000)
+#define FAKE_ADDRESS 0x10000000
+
+static const unsigned long expected_seccfg_fail = 0;
+static unsigned actual_seccfg_fail = 0;
+
+static const unsigned long expected_pmpaddr_fail = 0;
+static unsigned actual_pmpaddr_fail = 0;
+
+static const unsigned long expected_pmpcfg_fail = 0;
+static unsigned actual_pmpcfg_fail = 0;
+
+static void checkTestResult(void);
+
+/*
+ * override syscalls.c.
+ *  currently simply skip to nexp instruction
+ */
+uintptr_t handle_trap(uintptr_t cause, uintptr_t epc, uintptr_t regs[32])
+{ 
+    tohost_exit(1337);
+}
+
+
+__attribute ((section(".text_test_foo"), noinline))
+void target_foo() {
+    asm volatile ("nop");
+}
+
+__attribute ((section(".data_test_arr"), aligned(8)))
+volatile unsigned char target_arr[100] = {
+        1,2,3,4,5,6,7,8,
+};
+
+__attribute ((section(".text_umode"), noinline))
+void target_foo_U() {
+    asm volatile ("nop");
+}
+
+__attribute ((section(".data_umode"), aligned(8)))
+volatile unsigned char target_arr_U[100] = {
+        1,2,3,4,5,6,7,8,
+};
+
+/*
+ * On processor_t::reset():
+ *  - set_csr(CSR_PMPADDR0, ~reg_t(0));
+ *    set_csr(CSR_PMPCFG0, PMP_R | PMP_W | PMP_X | PMP_NAPOT);
+ */
+static void set_cfg() {
+#if 1 // @set_rlb_at_start:int@
+    /*
+     * set MSECCFG_RLB to avoid locked at start
+     */
+    asm volatile ("csrs 0x747, %0 \n"::"r"(MSECCFG_RLB));
+    asm volatile ("nop");
+#endif
+    
+//------------------------Set current status before the test target (CSR access)
+    /*
+     * Set pmp0cfg for M mode (M_MEM), and pmp1cfg for base of TOR.
+     * Then use pmp2cfg for TEST_MEM. Both test code and data share PMP entrance.
+     * Also use pmp3cfg for fixed U mode (U_MEM).
+     */
+    asm volatile ("csrw pmpaddr7, %0 \n" :: "r"(0x8ffffff8 >> 2) : "memory");       // for ibex signature addr
+    asm volatile ("csrw pmpaddr3, %0 \n" :: "r"(U_MEM_END >> 2) : "memory");
+    asm volatile ("csrw pmpaddr2, %0 \n" :: "r"(TEST_MEM_END >> 2) : "memory");
+    asm volatile ("csrw pmpaddr1, %0 \n" :: "r"(TEST_MEM_START >> 2) : "memory");
+    
+#if M_MODE_RWX
+    asm volatile ("csrw pmpaddr0, %0 \n" :: "r"((0x80000000 >> 2) | 0xfffff) : "memory");
+    reg_t cfg0 = (PMP_R | PMP_W | PMP_X | PMP_NAPOT);
+    reg_t cfg1 = (PMP_R | PMP_W | PMP_NAPOT) << 24;
+#else
+    asm volatile ("csrw pmpaddr6, %0 \n" :: "r"(TEST_MEM_START >> 2) : "memory");   // for data
+    asm volatile ("csrw pmpaddr5, %0 \n" :: "r"(0x80010000 >> 2) : "memory");       // for code
+    asm volatile ("csrw pmpaddr4, %0 \n" :: "r"(0x80000000 >> 2) : "memory");       // addr start
+    reg_t cfg0 = PMP_OFF;
+    reg_t cfg1 = PMP_OFF | ((PMP_R | PMP_W | PMP_NAPOT) << 24)
+                         | ((PMP_R | PMP_W | PMP_TOR) << 16) 
+                         | ((PMP_X | PMP_TOR) << 8);
+#endif
+
+    if (1) {    // need to set L bit for M mode code access
+#if M_MODE_RWX
+        cfg0 |= PMP_L;
+        cfg1 |= (PMP_L << 24);
+#else
+        cfg1 |= ((PMP_L << 8) | (PMP_L << 16) | (PMP_L << 24));
+#endif
+    }
+    
+    reg_t sub_cfg = PMP_R | PMP_W | PMP_X | PMP_TOR | ((1 || 0) ? PMP_L : 0);
+    cfg0 |= sub_cfg << 24;    // for U_MEM
+    cfg0 |= sub_cfg << 16;    // for TEST_MEM
+    
+#if __riscv_xlen == 64
+    cfg0 |= (cfg1 << 32);
+#else
+    asm volatile ("csrw pmpcfg1, %0 \n"
+                :
+                : "r"(cfg1)
+                : "memory");
+#endif // __riscv_xlen == 64
+    
+    asm volatile ("csrw pmpcfg0, %0 \n"
+                :
+                : "r"(cfg0)
+                : "memory");
+
+    if (1 != 0) {
+        reg_t lock_bits = (PMP_L << 16) | ((reg_t)PMP_L << 24); // avoid use (default) int type
+        if (0) {
+            asm volatile ("csrs pmpcfg0, %0 \n"
+                            :
+                            : "r"(lock_bits)
+                            : "memory");
+        } else {
+            asm volatile ("csrc pmpcfg0, %0 \n"
+                            :
+                            : "r"(lock_bits)
+                            : "memory");
+        }
+    }
+    
+    // set proc->state.mseccfg
+    const unsigned seccfg_bits = (1 ? MSECCFG_RLB : 0) 
+            | (1 ? MSECCFG_MML : 0) 
+            | (0 ? MSECCFG_MMWP : 0);
+    asm volatile ("csrw 0x747, %0 \n"::"r"(seccfg_bits));
+    
+//------------------------Test target
+    asm volatile ("nop");
+    /*
+     * Need to separate pmp and seccfg access since pmplock_recorded status may be 
+     * updated again when accessing pmpcfg.
+     */
+    reg_t wval = 0, rval;
+    reg_t prev_val = 0;
+#if 1
+    asm volatile ("csrr %0, pmpaddr7 \n"
+            : "=r"(rval));
+    // give a valid value for both NAPOT and TOR
+    if (7 == 0) {
+        wval = ((rval + 1) << 1) - 1;   // NAPOT mask
+    } else {
+        wval = (rval << 1) + 65536;   
+    }
+    prev_val = rval;
+    asm volatile ("csrw pmpaddr7, %1 \n"
+                "\tcsrr %0, pmpaddr7 \n"
+            : "=r"(rval)
+            : "r"(wval)
+              : "memory");
+    if (wval != rval) {
+        actual_pmpaddr_fail = 1;
+    }
+    asm volatile ("csrw pmpaddr7, %0 \n"
+            :: "r"(prev_val));
+    // Update cfg0 to avoid changing idx other than 3
+    asm volatile ("csrr %0, pmpcfg2 \n"
+                    : "=r"(cfg0)
+                    :
+                    : "memory");
+    
+    // reuse lock_once here since it's for RLB and independent with pmp_lock
+    wval = cfg0 ^ ((reg_t)(2 | (1 ? PMP_L : 0)) << (3 * 8));
+    asm volatile ("csrw pmpcfg2, %1 \n"
+                "\tcsrr %0, pmpcfg2 \n"
+            : "=r"(rval)
+            : "r"(wval)
+              : "memory");
+    if (wval != rval) {
+        actual_pmpcfg_fail = 1;
+    }
+#else
+    /*
+     * need to set PMP_L for cfg0 otherwise next PC will illegal
+     * This is a little coverage hole for non-PMP_L + mml, which should be
+     * a restricted use case and can be accepted anyway.
+     */ 
+    if (1) {    
+#if M_MODE_RWX
+        asm volatile ("csrs pmpcfg0, %0 \n"::"r"(PMP_L));
+#else
+#if __riscv_xlen == 64
+        asm volatile ("csrs pmpcfg0, %0 \n"::"r"(((reg_t)PMP_L << 40) | ((reg_t)PMP_L << 48)));
+#else
+        asm volatile ("csrs pmpcfg1, %0 \n"::"r"((PMP_L << 8) | (PMP_L << 16) | (PMP_L << 24)));
+#endif // __riscv_xlen == 64
+#endif // M_MODE_RWX
+    }
+    
+    wval = (1 ? MSECCFG_RLB : 0) 
+            | (1 ? MSECCFG_MML : 0) 
+            | (1 ? MSECCFG_MMWP : 0);
+    asm volatile ("csrw 0x747, %1 \n"
+                "\tcsrr %0, 0x747 \n"
+            : "=r"(rval)
+            : "r"(wval)
+              : "memory");
+    reg_t expected_val = wval & (MSECCFG_RLB | MSECCFG_MML | MSECCFG_MMWP);
+    /*
+     * pre_sec_mml means cfg0 locked
+     * pmp_lock means cfg2/3 locked
+     * sec_mml is the test coverage hole just mentioned
+     */
+    if ((1 || 0 || 1) 
+            && 1 == 0) {
+        expected_val &= ~MSECCFG_RLB;
+    } 
+    if (1) {
+        expected_val |= MSECCFG_MML;
+    }
+    if (0) {
+        expected_val |= MSECCFG_MMWP;
+    }
+    
+    if (expected_val != rval) actual_seccfg_fail = 1;
+#endif
+}
+
+static void checkTestResult() {
+    int ret = 0;
+    if (expected_seccfg_fail != actual_seccfg_fail) {
+        ret += 1;
+    }
+
+    if (expected_pmpaddr_fail != actual_pmpaddr_fail) {
+        ret += 2;
+    }
+    
+    if (expected_pmpcfg_fail != actual_pmpcfg_fail) {
+        ret += 4;
+    }
+    
+    
+    exit(ret); 
+}
+
+int main() {
+    // assert in M mode
+    set_cfg();
+
+    checkTestResult();
+    return 0; // assert 0
+}
+

snapshots/lowRISC_ibex_pr2214/vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_sec_02.c

@@ -0,0 +1,318 @@
+
+/*
+ * outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_sec_02.c
+ * Generated from gen_pmp_test.cc and test_pmp_csr_1.cc_skel.
+ * 
+ * This test program is verify the pmp CSR access when seccfg introduced.
+ * It's expected to executed from M mode.
+ * 
+ * Remarks:
+ * - CSR protection for non-M mode access is assumed and not coverred.
+ * - The access on invalid CSR index like pmpcfg1 for rv64 is not coverred.
+ * - Executed on RV64 only.
+ */
+
+/*
+ * Macros from encoding.h
+ */
+#define MSTATUS_MPP         0x00001800
+
+#define PMP_R     0x01
+#define PMP_W     0x02
+#define PMP_X     0x04
+#define PMP_A     0x18
+#define PMP_L     0x80
+#define PMP_SHIFT 2
+
+#if ((PMP_R | PMP_W | PMP_X) != 0x7)
+#error unexpected
+#endif
+
+#define PMP_OFF   0x0
+#define PMP_TOR   0x08
+#define PMP_NA4   0x10
+#define PMP_NAPOT 0x18
+
+#define MSECCFG_MML  0x1
+#define MSECCFG_MMWP 0x2
+#define MSECCFG_RLB  0x4
+
+#define TEST_RW 1
+#define TEST_FETCH 1
+/*
+ * Whether rwx share single cfg for M mode
+ * When @set_sec_mml@ set, it must be 0, otherwise unexpected exception
+ */
+#define M_MODE_RWX 0
+
+#define CAUSE_LOAD_ACCESS 0x5
+#define CAUSE_STORE_ACCESS 0x7
+
+typedef unsigned long reg_t;
+typedef unsigned long uintptr_t;
+
+/*
+ * functions from syscalls.c
+ */
+#if PRINTF_SUPPORTED
+int printf(const char* fmt, ...);
+#else
+#define printf(...)
+#endif
+
+void __attribute__((noreturn)) tohost_exit(uintptr_t code);
+void exit(int code);
+
+/*
+ * local status
+ */
+#define TEST_MEM_START 0x80200000
+#define TEST_MEM_END 0x80240000
+#define U_MEM_END (TEST_MEM_END + 0x10000)
+#define FAKE_ADDRESS 0x10000000
+
+static const unsigned long expected_seccfg_fail = 0;
+static unsigned actual_seccfg_fail = 0;
+
+static const unsigned long expected_pmpaddr_fail = 0;
+static unsigned actual_pmpaddr_fail = 0;
+
+static const unsigned long expected_pmpcfg_fail = 0;
+static unsigned actual_pmpcfg_fail = 0;
+
+static void checkTestResult(void);
+
+/*
+ * override syscalls.c.
+ *  currently simply skip to nexp instruction
+ */
+uintptr_t handle_trap(uintptr_t cause, uintptr_t epc, uintptr_t regs[32])
+{ 
+    tohost_exit(1337);
+}
+
+
+__attribute ((section(".text_test_foo"), noinline))
+void target_foo() {
+    asm volatile ("nop");
+}
+
+__attribute ((section(".data_test_arr"), aligned(8)))
+volatile unsigned char target_arr[100] = {
+        1,2,3,4,5,6,7,8,
+};
+
+__attribute ((section(".text_umode"), noinline))
+void target_foo_U() {
+    asm volatile ("nop");
+}
+
+__attribute ((section(".data_umode"), aligned(8)))
+volatile unsigned char target_arr_U[100] = {
+        1,2,3,4,5,6,7,8,
+};
+
+/*
+ * On processor_t::reset():
+ *  - set_csr(CSR_PMPADDR0, ~reg_t(0));
+ *    set_csr(CSR_PMPCFG0, PMP_R | PMP_W | PMP_X | PMP_NAPOT);
+ */
+static void set_cfg() {
+#if 1 // @set_rlb_at_start:int@
+    /*
+     * set MSECCFG_RLB to avoid locked at start
+     */
+    asm volatile ("csrs 0x747, %0 \n"::"r"(MSECCFG_RLB));
+    asm volatile ("nop");
+#endif
+    
+//------------------------Set current status before the test target (CSR access)
+    /*
+     * Set pmp0cfg for M mode (M_MEM), and pmp1cfg for base of TOR.
+     * Then use pmp2cfg for TEST_MEM. Both test code and data share PMP entrance.
+     * Also use pmp3cfg for fixed U mode (U_MEM).
+     */
+    asm volatile ("csrw pmpaddr7, %0 \n" :: "r"(0x8ffffff8 >> 2) : "memory");       // for ibex signature addr
+    asm volatile ("csrw pmpaddr3, %0 \n" :: "r"(U_MEM_END >> 2) : "memory");
+    asm volatile ("csrw pmpaddr2, %0 \n" :: "r"(TEST_MEM_END >> 2) : "memory");
+    asm volatile ("csrw pmpaddr1, %0 \n" :: "r"(TEST_MEM_START >> 2) : "memory");
+    
+#if M_MODE_RWX
+    asm volatile ("csrw pmpaddr0, %0 \n" :: "r"((0x80000000 >> 2) | 0xfffff) : "memory");
+    reg_t cfg0 = (PMP_R | PMP_W | PMP_X | PMP_NAPOT);
+    reg_t cfg1 = (PMP_R | PMP_W | PMP_NAPOT) << 24;
+#else
+    asm volatile ("csrw pmpaddr6, %0 \n" :: "r"(TEST_MEM_START >> 2) : "memory");   // for data
+    asm volatile ("csrw pmpaddr5, %0 \n" :: "r"(0x80010000 >> 2) : "memory");       // for code
+    asm volatile ("csrw pmpaddr4, %0 \n" :: "r"(0x80000000 >> 2) : "memory");       // addr start
+    reg_t cfg0 = PMP_OFF;
+    reg_t cfg1 = PMP_OFF | ((PMP_R | PMP_W | PMP_NAPOT) << 24)
+                         | ((PMP_R | PMP_W | PMP_TOR) << 16) 
+                         | ((PMP_X | PMP_TOR) << 8);
+#endif
+
+    if (0) {    // need to set L bit for M mode code access
+#if M_MODE_RWX
+        cfg0 |= PMP_L;
+        cfg1 |= (PMP_L << 24);
+#else
+        cfg1 |= ((PMP_L << 8) | (PMP_L << 16) | (PMP_L << 24));
+#endif
+    }
+    
+    reg_t sub_cfg = PMP_R | PMP_W | PMP_X | PMP_TOR | ((0 || 1) ? PMP_L : 0);
+    cfg0 |= sub_cfg << 24;    // for U_MEM
+    cfg0 |= sub_cfg << 16;    // for TEST_MEM
+    
+#if __riscv_xlen == 64
+    cfg0 |= (cfg1 << 32);
+#else
+    asm volatile ("csrw pmpcfg1, %0 \n"
+                :
+                : "r"(cfg1)
+                : "memory");
+#endif // __riscv_xlen == 64
+    
+    asm volatile ("csrw pmpcfg0, %0 \n"
+                :
+                : "r"(cfg0)
+                : "memory");
+
+    if (0 != 1) {
+        reg_t lock_bits = (PMP_L << 16) | ((reg_t)PMP_L << 24); // avoid use (default) int type
+        if (1) {
+            asm volatile ("csrs pmpcfg0, %0 \n"
+                            :
+                            : "r"(lock_bits)
+                            : "memory");
+        } else {
+            asm volatile ("csrc pmpcfg0, %0 \n"
+                            :
+                            : "r"(lock_bits)
+                            : "memory");
+        }
+    }
+    
+    // set proc->state.mseccfg
+    const unsigned seccfg_bits = (0 ? MSECCFG_RLB : 0) 
+            | (0 ? MSECCFG_MML : 0) 
+            | (0 ? MSECCFG_MMWP : 0);
+    asm volatile ("csrw 0x747, %0 \n"::"r"(seccfg_bits));
+    
+//------------------------Test target
+    asm volatile ("nop");
+    /*
+     * Need to separate pmp and seccfg access since pmplock_recorded status may be 
+     * updated again when accessing pmpcfg.
+     */
+    reg_t wval = 0, rval;
+    reg_t prev_val = 0;
+#if 0
+    asm volatile ("csrr %0, pmpaddr11 \n"
+            : "=r"(rval));
+    // give a valid value for both NAPOT and TOR
+    if (11 == 0) {
+        wval = ((rval + 1) << 1) - 1;   // NAPOT mask
+    } else {
+        wval = (rval << 1) + 65536;   
+    }
+    prev_val = rval;
+    asm volatile ("csrw pmpaddr11, %1 \n"
+                "\tcsrr %0, pmpaddr11 \n"
+            : "=r"(rval)
+            : "r"(wval)
+              : "memory");
+    if (wval != rval) {
+        actual_pmpaddr_fail = 1;
+    }
+    asm volatile ("csrw pmpaddr11, %0 \n"
+            :: "r"(prev_val));
+    // Update cfg0 to avoid changing idx other than 0
+    asm volatile ("csrr %0, pmpcfg2 \n"
+                    : "=r"(cfg0)
+                    :
+                    : "memory");
+    
+    // reuse lock_once here since it's for RLB and independent with pmp_lock
+    wval = cfg0 ^ ((reg_t)(7 | (0 ? PMP_L : 0)) << (0 * 8));
+    asm volatile ("csrw pmpcfg2, %1 \n"
+                "\tcsrr %0, pmpcfg2 \n"
+            : "=r"(rval)
+            : "r"(wval)
+              : "memory");
+    if (wval != rval) {
+        actual_pmpcfg_fail = 1;
+    }
+#else
+    /*
+     * need to set PMP_L for cfg0 otherwise next PC will illegal
+     * This is a little coverage hole for non-PMP_L + mml, which should be
+     * a restricted use case and can be accepted anyway.
+     */ 
+    if (0) {    
+#if M_MODE_RWX
+        asm volatile ("csrs pmpcfg0, %0 \n"::"r"(PMP_L));
+#else
+#if __riscv_xlen == 64
+        asm volatile ("csrs pmpcfg0, %0 \n"::"r"(((reg_t)PMP_L << 40) | ((reg_t)PMP_L << 48)));
+#else
+        asm volatile ("csrs pmpcfg1, %0 \n"::"r"((PMP_L << 8) | (PMP_L << 16) | (PMP_L << 24)));
+#endif // __riscv_xlen == 64
+#endif // M_MODE_RWX
+    }
+    
+    wval = (0 ? MSECCFG_RLB : 0) 
+            | (0 ? MSECCFG_MML : 0) 
+            | (1 ? MSECCFG_MMWP : 0);
+    asm volatile ("csrw 0x747, %1 \n"
+                "\tcsrr %0, 0x747 \n"
+            : "=r"(rval)
+            : "r"(wval)
+              : "memory");
+    reg_t expected_val = wval & (MSECCFG_RLB | MSECCFG_MML | MSECCFG_MMWP);
+    /*
+     * pre_sec_mml means cfg0 locked
+     * pmp_lock means cfg2/3 locked
+     * sec_mml is the test coverage hole just mentioned
+     */
+    if ((0 || 1 || 0) 
+            && 0 == 0) {
+        expected_val &= ~MSECCFG_RLB;
+    } 
+    if (0) {
+        expected_val |= MSECCFG_MML;
+    }
+    if (0) {
+        expected_val |= MSECCFG_MMWP;
+    }
+    
+    if (expected_val != rval) actual_seccfg_fail = 1;
+#endif
+}
+
+static void checkTestResult() {
+    int ret = 0;
+    if (expected_seccfg_fail != actual_seccfg_fail) {
+        ret += 1;
+    }
+
+    if (expected_pmpaddr_fail != actual_pmpaddr_fail) {
+        ret += 2;
+    }
+    
+    if (expected_pmpcfg_fail != actual_pmpcfg_fail) {
+        ret += 4;
+    }
+    
+    
+    exit(ret); 
+}
+
+int main() {
+    // assert in M mode
+    set_cfg();
+
+    checkTestResult();
+    return 0; // assert 0
+}
+

snapshots/lowRISC_ibex_pr2214/vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_17.c

@@ -0,0 +1,318 @@
+
+/*
+ * outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_17.c
+ * Generated from gen_pmp_test.cc and test_pmp_csr_1.cc_skel.
+ * 
+ * This test program is verify the pmp CSR access when seccfg introduced.
+ * It's expected to executed from M mode.
+ * 
+ * Remarks:
+ * - CSR protection for non-M mode access is assumed and not coverred.
+ * - The access on invalid CSR index like pmpcfg1 for rv64 is not coverred.
+ * - Executed on RV64 only.
+ */
+
+/*
+ * Macros from encoding.h
+ */
+#define MSTATUS_MPP         0x00001800
+
+#define PMP_R     0x01
+#define PMP_W     0x02
+#define PMP_X     0x04
+#define PMP_A     0x18
+#define PMP_L     0x80
+#define PMP_SHIFT 2
+
+#if ((PMP_R | PMP_W | PMP_X) != 0x7)
+#error unexpected
+#endif
+
+#define PMP_OFF   0x0
+#define PMP_TOR   0x08
+#define PMP_NA4   0x10
+#define PMP_NAPOT 0x18
+
+#define MSECCFG_MML  0x1
+#define MSECCFG_MMWP 0x2
+#define MSECCFG_RLB  0x4
+
+#define TEST_RW 1
+#define TEST_FETCH 1
+/*
+ * Whether rwx share single cfg for M mode
+ * When @set_sec_mml@ set, it must be 0, otherwise unexpected exception
+ */
+#define M_MODE_RWX 0
+
+#define CAUSE_LOAD_ACCESS 0x5
+#define CAUSE_STORE_ACCESS 0x7
+
+typedef unsigned long reg_t;
+typedef unsigned long uintptr_t;
+
+/*
+ * functions from syscalls.c
+ */
+#if PRINTF_SUPPORTED
+int printf(const char* fmt, ...);
+#else
+#define printf(...)
+#endif
+
+void __attribute__((noreturn)) tohost_exit(uintptr_t code);
+void exit(int code);
+
+/*
+ * local status
+ */
+#define TEST_MEM_START 0x80200000
+#define TEST_MEM_END 0x80240000
+#define U_MEM_END (TEST_MEM_END + 0x10000)
+#define FAKE_ADDRESS 0x10000000
+
+static const unsigned long expected_seccfg_fail = 0;
+static unsigned actual_seccfg_fail = 0;
+
+static const unsigned long expected_pmpaddr_fail = 0;
+static unsigned actual_pmpaddr_fail = 0;
+
+static const unsigned long expected_pmpcfg_fail = 0;
+static unsigned actual_pmpcfg_fail = 0;
+
+static void checkTestResult(void);
+
+/*
+ * override syscalls.c.
+ *  currently simply skip to nexp instruction
+ */
+uintptr_t handle_trap(uintptr_t cause, uintptr_t epc, uintptr_t regs[32])
+{ 
+    tohost_exit(1337);
+}
+
+
+__attribute ((section(".text_test_foo"), noinline))
+void target_foo() {
+    asm volatile ("nop");
+}
+
+__attribute ((section(".data_test_arr"), aligned(8)))
+volatile unsigned char target_arr[100] = {
+        1,2,3,4,5,6,7,8,
+};
+
+__attribute ((section(".text_umode"), noinline))
+void target_foo_U() {
+    asm volatile ("nop");
+}
+
+__attribute ((section(".data_umode"), aligned(8)))
+volatile unsigned char target_arr_U[100] = {
+        1,2,3,4,5,6,7,8,
+};
+
+/*
+ * On processor_t::reset():
+ *  - set_csr(CSR_PMPADDR0, ~reg_t(0));
+ *    set_csr(CSR_PMPCFG0, PMP_R | PMP_W | PMP_X | PMP_NAPOT);
+ */
+static void set_cfg() {
+#if 1 // @set_rlb_at_start:int@
+    /*
+     * set MSECCFG_RLB to avoid locked at start
+     */
+    asm volatile ("csrs 0x747, %0 \n"::"r"(MSECCFG_RLB));
+    asm volatile ("nop");
+#endif
+    
+//------------------------Set current status before the test target (CSR access)
+    /*
+     * Set pmp0cfg for M mode (M_MEM), and pmp1cfg for base of TOR.
+     * Then use pmp2cfg for TEST_MEM. Both test code and data share PMP entrance.
+     * Also use pmp3cfg for fixed U mode (U_MEM).
+     */
+    asm volatile ("csrw pmpaddr7, %0 \n" :: "r"(0x8ffffff8 >> 2) : "memory");       // for ibex signature addr
+    asm volatile ("csrw pmpaddr3, %0 \n" :: "r"(U_MEM_END >> 2) : "memory");
+    asm volatile ("csrw pmpaddr2, %0 \n" :: "r"(TEST_MEM_END >> 2) : "memory");
+    asm volatile ("csrw pmpaddr1, %0 \n" :: "r"(TEST_MEM_START >> 2) : "memory");
+    
+#if M_MODE_RWX
+    asm volatile ("csrw pmpaddr0, %0 \n" :: "r"((0x80000000 >> 2) | 0xfffff) : "memory");
+    reg_t cfg0 = (PMP_R | PMP_W | PMP_X | PMP_NAPOT);
+    reg_t cfg1 = (PMP_R | PMP_W | PMP_NAPOT) << 24;
+#else
+    asm volatile ("csrw pmpaddr6, %0 \n" :: "r"(TEST_MEM_START >> 2) : "memory");   // for data
+    asm volatile ("csrw pmpaddr5, %0 \n" :: "r"(0x80010000 >> 2) : "memory");       // for code
+    asm volatile ("csrw pmpaddr4, %0 \n" :: "r"(0x80000000 >> 2) : "memory");       // addr start
+    reg_t cfg0 = PMP_OFF;
+    reg_t cfg1 = PMP_OFF | ((PMP_R | PMP_W | PMP_NAPOT) << 24)
+                         | ((PMP_R | PMP_W | PMP_TOR) << 16) 
+                         | ((PMP_X | PMP_TOR) << 8);
+#endif
+
+    if (1) {    // need to set L bit for M mode code access
+#if M_MODE_RWX
+        cfg0 |= PMP_L;
+        cfg1 |= (PMP_L << 24);
+#else
+        cfg1 |= ((PMP_L << 8) | (PMP_L << 16) | (PMP_L << 24));
+#endif
+    }
+    
+    reg_t sub_cfg = PMP_R | PMP_W | PMP_X | PMP_TOR | ((0 || 1) ? PMP_L : 0);
+    cfg0 |= sub_cfg << 24;    // for U_MEM
+    cfg0 |= sub_cfg << 16;    // for TEST_MEM
+    
+#if __riscv_xlen == 64
+    cfg0 |= (cfg1 << 32);
+#else
+    asm volatile ("csrw pmpcfg1, %0 \n"
+                :
+                : "r"(cfg1)
+                : "memory");
+#endif // __riscv_xlen == 64
+    
+    asm volatile ("csrw pmpcfg0, %0 \n"
+                :
+                : "r"(cfg0)
+                : "memory");
+
+    if (0 != 1) {
+        reg_t lock_bits = (PMP_L << 16) | ((reg_t)PMP_L << 24); // avoid use (default) int type
+        if (1) {
+            asm volatile ("csrs pmpcfg0, %0 \n"
+                            :
+                            : "r"(lock_bits)
+                            : "memory");
+        } else {
+            asm volatile ("csrc pmpcfg0, %0 \n"
+                            :
+                            : "r"(lock_bits)
+                            : "memory");
+        }
+    }
+    
+    // set proc->state.mseccfg
+    const unsigned seccfg_bits = (0 ? MSECCFG_RLB : 0) 
+            | (1 ? MSECCFG_MML : 0) 
+            | (1 ? MSECCFG_MMWP : 0);
+    asm volatile ("csrw 0x747, %0 \n"::"r"(seccfg_bits));
+    
+//------------------------Test target
+    asm volatile ("nop");
+    /*
+     * Need to separate pmp and seccfg access since pmplock_recorded status may be 
+     * updated again when accessing pmpcfg.
+     */
+    reg_t wval = 0, rval;
+    reg_t prev_val = 0;
+#if 1
+    asm volatile ("csrr %0, pmpaddr9 \n"
+            : "=r"(rval));
+    // give a valid value for both NAPOT and TOR
+    if (9 == 0) {
+        wval = ((rval + 1) << 1) - 1;   // NAPOT mask
+    } else {
+        wval = (rval << 1) + 65536;   
+    }
+    prev_val = rval;
+    asm volatile ("csrw pmpaddr9, %1 \n"
+                "\tcsrr %0, pmpaddr9 \n"
+            : "=r"(rval)
+            : "r"(wval)
+              : "memory");
+    if (wval != rval) {
+        actual_pmpaddr_fail = 1;
+    }
+    asm volatile ("csrw pmpaddr9, %0 \n"
+            :: "r"(prev_val));
+    // Update cfg0 to avoid changing idx other than 0
+    asm volatile ("csrr %0, pmpcfg2 \n"
+                    : "=r"(cfg0)
+                    :
+                    : "memory");
+    
+    // reuse lock_once here since it's for RLB and independent with pmp_lock
+    wval = cfg0 ^ ((reg_t)(7 | (0 ? PMP_L : 0)) << (0 * 8));
+    asm volatile ("csrw pmpcfg2, %1 \n"
+                "\tcsrr %0, pmpcfg2 \n"
+            : "=r"(rval)
+            : "r"(wval)
+              : "memory");
+    if (wval != rval) {
+        actual_pmpcfg_fail = 1;
+    }
+#else
+    /*
+     * need to set PMP_L for cfg0 otherwise next PC will illegal
+     * This is a little coverage hole for non-PMP_L + mml, which should be
+     * a restricted use case and can be accepted anyway.
+     */ 
+    if (1) {    
+#if M_MODE_RWX
+        asm volatile ("csrs pmpcfg0, %0 \n"::"r"(PMP_L));
+#else
+#if __riscv_xlen == 64
+        asm volatile ("csrs pmpcfg0, %0 \n"::"r"(((reg_t)PMP_L << 40) | ((reg_t)PMP_L << 48)));
+#else
+        asm volatile ("csrs pmpcfg1, %0 \n"::"r"((PMP_L << 8) | (PMP_L << 16) | (PMP_L << 24)));
+#endif // __riscv_xlen == 64
+#endif // M_MODE_RWX
+    }
+    
+    wval = (1 ? MSECCFG_RLB : 0) 
+            | (1 ? MSECCFG_MML : 0) 
+            | (1 ? MSECCFG_MMWP : 0);
+    asm volatile ("csrw 0x747, %1 \n"
+                "\tcsrr %0, 0x747 \n"
+            : "=r"(rval)
+            : "r"(wval)
+              : "memory");
+    reg_t expected_val = wval & (MSECCFG_RLB | MSECCFG_MML | MSECCFG_MMWP);
+    /*
+     * pre_sec_mml means cfg0 locked
+     * pmp_lock means cfg2/3 locked
+     * sec_mml is the test coverage hole just mentioned
+     */
+    if ((1 || 1 || 1) 
+            && 0 == 0) {
+        expected_val &= ~MSECCFG_RLB;
+    } 
+    if (1) {
+        expected_val |= MSECCFG_MML;
+    }
+    if (1) {
+        expected_val |= MSECCFG_MMWP;
+    }
+    
+    if (expected_val != rval) actual_seccfg_fail = 1;
+#endif
+}
+
+static void checkTestResult() {
+    int ret = 0;
+    if (expected_seccfg_fail != actual_seccfg_fail) {
+        ret += 1;
+    }
+
+    if (expected_pmpaddr_fail != actual_pmpaddr_fail) {
+        ret += 2;
+    }
+    
+    if (expected_pmpcfg_fail != actual_pmpcfg_fail) {
+        ret += 4;
+    }
+    
+    
+    exit(ret); 
+}
+
+int main() {
+    // assert in M mode
+    set_cfg();
+
+    checkTestResult();
+    return 0; // assert 0
+}
+

snapshots/lowRISC_ibex_pr2214/vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_sec_02.c

@@ -0,0 +1,318 @@
+
+/*
+ * outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_sec_02.c
+ * Generated from gen_pmp_test.cc and test_pmp_csr_1.cc_skel.
+ * 
+ * This test program is verify the pmp CSR access when seccfg introduced.
+ * It's expected to executed from M mode.
+ * 
+ * Remarks:
+ * - CSR protection for non-M mode access is assumed and not coverred.
+ * - The access on invalid CSR index like pmpcfg1 for rv64 is not coverred.
+ * - Executed on RV64 only.
+ */
+
+/*
+ * Macros from encoding.h
+ */
+#define MSTATUS_MPP         0x00001800
+
+#define PMP_R     0x01
+#define PMP_W     0x02
+#define PMP_X     0x04
+#define PMP_A     0x18
+#define PMP_L     0x80
+#define PMP_SHIFT 2
+
+#if ((PMP_R | PMP_W | PMP_X) != 0x7)
+#error unexpected
+#endif
+
+#define PMP_OFF   0x0
+#define PMP_TOR   0x08
+#define PMP_NA4   0x10
+#define PMP_NAPOT 0x18
+
+#define MSECCFG_MML  0x1
+#define MSECCFG_MMWP 0x2
+#define MSECCFG_RLB  0x4
+
+#define TEST_RW 1
+#define TEST_FETCH 1
+/*
+ * Whether rwx share single cfg for M mode
+ * When @set_sec_mml@ set, it must be 0, otherwise unexpected exception
+ */
+#define M_MODE_RWX 0
+
+#define CAUSE_LOAD_ACCESS 0x5
+#define CAUSE_STORE_ACCESS 0x7
+
+typedef unsigned long reg_t;
+typedef unsigned long uintptr_t;
+
+/*
+ * functions from syscalls.c
+ */
+#if PRINTF_SUPPORTED
+int printf(const char* fmt, ...);
+#else
+#define printf(...)
+#endif
+
+void __attribute__((noreturn)) tohost_exit(uintptr_t code);
+void exit(int code);
+
+/*
+ * local status
+ */
+#define TEST_MEM_START 0x80200000
+#define TEST_MEM_END 0x80240000
+#define U_MEM_END (TEST_MEM_END + 0x10000)
+#define FAKE_ADDRESS 0x10000000
+
+static const unsigned long expected_seccfg_fail = 0;
+static unsigned actual_seccfg_fail = 0;
+
+static const unsigned long expected_pmpaddr_fail = 0;
+static unsigned actual_pmpaddr_fail = 0;
+
+static const unsigned long expected_pmpcfg_fail = 0;
+static unsigned actual_pmpcfg_fail = 0;
+
+static void checkTestResult(void);
+
+/*
+ * override syscalls.c.
+ *  currently simply skip to nexp instruction
+ */
+uintptr_t handle_trap(uintptr_t cause, uintptr_t epc, uintptr_t regs[32])
+{ 
+    tohost_exit(1337);
+}
+
+
+__attribute ((section(".text_test_foo"), noinline))
+void target_foo() {
+    asm volatile ("nop");
+}
+
+__attribute ((section(".data_test_arr"), aligned(8)))
+volatile unsigned char target_arr[100] = {
+        1,2,3,4,5,6,7,8,
+};
+
+__attribute ((section(".text_umode"), noinline))
+void target_foo_U() {
+    asm volatile ("nop");
+}
+
+__attribute ((section(".data_umode"), aligned(8)))
+volatile unsigned char target_arr_U[100] = {
+        1,2,3,4,5,6,7,8,
+};
+
+/*
+ * On processor_t::reset():
+ *  - set_csr(CSR_PMPADDR0, ~reg_t(0));
+ *    set_csr(CSR_PMPCFG0, PMP_R | PMP_W | PMP_X | PMP_NAPOT);
+ */
+static void set_cfg() {
+#if 1 // @set_rlb_at_start:int@
+    /*
+     * set MSECCFG_RLB to avoid locked at start
+     */
+    asm volatile ("csrs 0x747, %0 \n"::"r"(MSECCFG_RLB));
+    asm volatile ("nop");
+#endif
+    
+//------------------------Set current status before the test target (CSR access)
+    /*
+     * Set pmp0cfg for M mode (M_MEM), and pmp1cfg for base of TOR.
+     * Then use pmp2cfg for TEST_MEM. Both test code and data share PMP entrance.
+     * Also use pmp3cfg for fixed U mode (U_MEM).
+     */
+    asm volatile ("csrw pmpaddr7, %0 \n" :: "r"(0x8ffffff8 >> 2) : "memory");       // for ibex signature addr
+    asm volatile ("csrw pmpaddr3, %0 \n" :: "r"(U_MEM_END >> 2) : "memory");
+    asm volatile ("csrw pmpaddr2, %0 \n" :: "r"(TEST_MEM_END >> 2) : "memory");
+    asm volatile ("csrw pmpaddr1, %0 \n" :: "r"(TEST_MEM_START >> 2) : "memory");
+    
+#if M_MODE_RWX
+    asm volatile ("csrw pmpaddr0, %0 \n" :: "r"((0x80000000 >> 2) | 0xfffff) : "memory");
+    reg_t cfg0 = (PMP_R | PMP_W | PMP_X | PMP_NAPOT);
+    reg_t cfg1 = (PMP_R | PMP_W | PMP_NAPOT) << 24;
+#else
+    asm volatile ("csrw pmpaddr6, %0 \n" :: "r"(TEST_MEM_START >> 2) : "memory");   // for data
+    asm volatile ("csrw pmpaddr5, %0 \n" :: "r"(0x80010000 >> 2) : "memory");       // for code
+    asm volatile ("csrw pmpaddr4, %0 \n" :: "r"(0x80000000 >> 2) : "memory");       // addr start
+    reg_t cfg0 = PMP_OFF;
+    reg_t cfg1 = PMP_OFF | ((PMP_R | PMP_W | PMP_NAPOT) << 24)
+                         | ((PMP_R | PMP_W | PMP_TOR) << 16) 
+                         | ((PMP_X | PMP_TOR) << 8);
+#endif
+
+    if (1) {    // need to set L bit for M mode code access
+#if M_MODE_RWX
+        cfg0 |= PMP_L;
+        cfg1 |= (PMP_L << 24);
+#else
+        cfg1 |= ((PMP_L << 8) | (PMP_L << 16) | (PMP_L << 24));
+#endif
+    }
+    
+    reg_t sub_cfg = PMP_R | PMP_W | PMP_X | PMP_TOR | ((0 || 1) ? PMP_L : 0);
+    cfg0 |= sub_cfg << 24;    // for U_MEM
+    cfg0 |= sub_cfg << 16;    // for TEST_MEM
+    
+#if __riscv_xlen == 64
+    cfg0 |= (cfg1 << 32);
+#else
+    asm volatile ("csrw pmpcfg1, %0 \n"
+                :
+                : "r"(cfg1)
+                : "memory");
+#endif // __riscv_xlen == 64
+    
+    asm volatile ("csrw pmpcfg0, %0 \n"
+                :
+                : "r"(cfg0)
+                : "memory");
+
+    if (0 != 1) {
+        reg_t lock_bits = (PMP_L << 16) | ((reg_t)PMP_L << 24); // avoid use (default) int type
+        if (1) {
+            asm volatile ("csrs pmpcfg0, %0 \n"
+                            :
+                            : "r"(lock_bits)
+                            : "memory");
+        } else {
+            asm volatile ("csrc pmpcfg0, %0 \n"
+                            :
+                            : "r"(lock_bits)
+                            : "memory");
+        }
+    }
+    
+    // set proc->state.mseccfg
+    const unsigned seccfg_bits = (1 ? MSECCFG_RLB : 0) 
+            | (1 ? MSECCFG_MML : 0) 
+            | (1 ? MSECCFG_MMWP : 0);
+    asm volatile ("csrw 0x747, %0 \n"::"r"(seccfg_bits));
+    
+//------------------------Test target
+    asm volatile ("nop");
+    /*
+     * Need to separate pmp and seccfg access since pmplock_recorded status may be 
+     * updated again when accessing pmpcfg.
+     */
+    reg_t wval = 0, rval;
+    reg_t prev_val = 0;
+#if 0
+    asm volatile ("csrr %0, pmpaddr12 \n"
+            : "=r"(rval));
+    // give a valid value for both NAPOT and TOR
+    if (12 == 0) {
+        wval = ((rval + 1) << 1) - 1;   // NAPOT mask
+    } else {
+        wval = (rval << 1) + 65536;   
+    }
+    prev_val = rval;
+    asm volatile ("csrw pmpaddr12, %1 \n"
+                "\tcsrr %0, pmpaddr12 \n"
+            : "=r"(rval)
+            : "r"(wval)
+              : "memory");
+    if (wval != rval) {
+        actual_pmpaddr_fail = 1;
+    }
+    asm volatile ("csrw pmpaddr12, %0 \n"
+            :: "r"(prev_val));
+    // Update cfg0 to avoid changing idx other than 1
+    asm volatile ("csrr %0, pmpcfg2 \n"
+                    : "=r"(cfg0)
+                    :
+                    : "memory");
+    
+    // reuse lock_once here since it's for RLB and independent with pmp_lock
+    wval = cfg0 ^ ((reg_t)(7 | (0 ? PMP_L : 0)) << (1 * 8));
+    asm volatile ("csrw pmpcfg2, %1 \n"
+                "\tcsrr %0, pmpcfg2 \n"
+            : "=r"(rval)
+            : "r"(wval)
+              : "memory");
+    if (wval != rval) {
+        actual_pmpcfg_fail = 1;
+    }
+#else
+    /*
+     * need to set PMP_L for cfg0 otherwise next PC will illegal
+     * This is a little coverage hole for non-PMP_L + mml, which should be
+     * a restricted use case and can be accepted anyway.
+     */ 
+    if (0) {    
+#if M_MODE_RWX
+        asm volatile ("csrs pmpcfg0, %0 \n"::"r"(PMP_L));
+#else
+#if __riscv_xlen == 64
+        asm volatile ("csrs pmpcfg0, %0 \n"::"r"(((reg_t)PMP_L << 40) | ((reg_t)PMP_L << 48)));
+#else
+        asm volatile ("csrs pmpcfg1, %0 \n"::"r"((PMP_L << 8) | (PMP_L << 16) | (PMP_L << 24)));
+#endif // __riscv_xlen == 64
+#endif // M_MODE_RWX
+    }
+    
+    wval = (0 ? MSECCFG_RLB : 0) 
+            | (0 ? MSECCFG_MML : 0) 
+            | (1 ? MSECCFG_MMWP : 0);
+    asm volatile ("csrw 0x747, %1 \n"
+                "\tcsrr %0, 0x747 \n"
+            : "=r"(rval)
+            : "r"(wval)
+              : "memory");
+    reg_t expected_val = wval & (MSECCFG_RLB | MSECCFG_MML | MSECCFG_MMWP);
+    /*
+     * pre_sec_mml means cfg0 locked
+     * pmp_lock means cfg2/3 locked
+     * sec_mml is the test coverage hole just mentioned
+     */
+    if ((1 || 1 || 0) 
+            && 1 == 0) {
+        expected_val &= ~MSECCFG_RLB;
+    } 
+    if (1) {
+        expected_val |= MSECCFG_MML;
+    }
+    if (1) {
+        expected_val |= MSECCFG_MMWP;
+    }
+    
+    if (expected_val != rval) actual_seccfg_fail = 1;
+#endif
+}
+
+static void checkTestResult() {
+    int ret = 0;
+    if (expected_seccfg_fail != actual_seccfg_fail) {
+        ret += 1;
+    }
+
+    if (expected_pmpaddr_fail != actual_pmpaddr_fail) {
+        ret += 2;
+    }
+    
+    if (expected_pmpcfg_fail != actual_pmpcfg_fail) {
+        ret += 4;
+    }
+    
+    
+    exit(ret); 
+}
+
+int main() {
+    // assert in M mode
+    set_cfg();
+
+    checkTestResult();
+    return 0; // assert 0
+}
+

snapshots/lowRISC_ibex_pr2214/vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw00_x0_l0_match1_mmwp0_mml0.c

@@ -0,0 +1,346 @@
+
+/*
+ * outputs/test_pmp_ok_1_u0_rw00_x0_l0_match1_mmwp0_mml0.c
+ * Generated from gen_pmp_test.cc and test_pmp_ok_1.cc_skel.
+ * 
+ * This test program is expected to start executed from M mode.
+ * That will be easier for us to deal with pmp exception for test.
+ * 
+ * Remarks:
+ * - RW=01 not covered. U/M mode share will be tested separately
+ * - RLB is always 0. CSR access control will be tested separately
+ * 
+ * @changed 2020-Mar-2 soberl
+ *  For RWXL + MML, need to separate R and W combinations.
+ *  Skip RW=01 (share mode) at generator driver side.
+ */
+
+/*
+ * Macros from encoding.h
+ */
+#define MSTATUS_MPP         0x00001800
+
+#define PMP_R     0x01
+#define PMP_W     0x02
+#define PMP_X     0x04
+#define PMP_A     0x18
+#define PMP_L     0x80
+#define PMP_SHIFT 2
+
+#define PMP_OFF   0x0
+#define PMP_TOR   0x08
+#define PMP_NA4   0x10
+#define PMP_NAPOT 0x18
+
+#define MSECCFG_MML  0x1
+#define MSECCFG_MMWP 0x2
+#define MSECCFG_RLB  0x4
+
+#define TEST_RW 1
+#define TEST_FETCH 1
+/*
+ * Whether rwx share single cfg for M mode
+ * When @set_sec_mml@ set, it must be 0, otherwise unexpected exception
+ */
+#define M_MODE_RWX 0
+
+#define CAUSE_LOAD_ACCESS 0x5
+#define CAUSE_STORE_ACCESS 0x7
+
+typedef unsigned long reg_t;
+typedef unsigned long uintptr_t;
+
+/*
+ * functions from syscalls.c
+ */
+#if PRINTF_SUPPORTED
+int printf(const char* fmt, ...);
+#else
+#define printf(...)
+#endif
+
+void __attribute__((noreturn)) tohost_exit(uintptr_t code);
+void exit(int code);
+
+/*
+ * local status
+ */
+#define TEST_MEM_START 0x80200000
+#define TEST_MEM_END 0x80240000
+#define U_MEM_END (TEST_MEM_END + 0x10000)
+#define FAKE_ADDRESS 0x10000000
+
+static const unsigned long expected_rw_fail = 0;
+static unsigned actual_rw_fail = 0;
+
+static const unsigned long expected_x_fail = 0;
+static unsigned actual_x_fail = 0;
+static void checkTestResult(void);
+
+/*
+ * override syscalls.c.
+ *  currently simply skip to nexp instruction
+ */
+uintptr_t handle_trap(uintptr_t cause, uintptr_t epc, uintptr_t regs[32])
+{
+    if (epc >= TEST_MEM_START && epc < TEST_MEM_END) {
+        asm volatile ("nop");
+        actual_x_fail = 1;
+        checkTestResult();
+    } else if (cause == CAUSE_LOAD_ACCESS || cause == CAUSE_STORE_ACCESS) {
+        reg_t addr;
+        asm volatile ("csrr %0, mtval\n" : "=r"(addr));
+        if (addr >= TEST_MEM_START && addr < TEST_MEM_END) {
+            actual_rw_fail = 1;
+            return epc + 4;
+        }
+        
+        if (addr == FAKE_ADDRESS) {
+            asm volatile ("nop");
+            asm volatile ("nop");
+            checkTestResult();
+        }
+    }
+    
+    tohost_exit(1337);
+}
+
+
+// switch (eret) to U mode and resume next PC
+static void switch_to_U() {
+    reg_t tmp;
+    asm volatile (
+            "li %0, %1\n"
+            "\tcsrc mstatus, t0\n"
+            "\tla %0, try_access_umode \n"
+            "\tcsrw mepc, %0\n"
+            "\tli sp, %2\n"
+            "\tmret\n"
+            : "=r"(tmp) : "n"(MSTATUS_MPP), "n"(U_MEM_END) : "memory");
+}
+
+static void switch_mode() {
+#if 0
+    switch_to_U();
+#endif
+}
+
+__attribute ((section(".text_test_foo"), noinline))
+static void target_foo() {
+    asm volatile ("nop");
+    
+    actual_x_fail = 0;
+}
+
+/*
+ * avoid to access actual_x_fail lies in M mode
+ */
+__attribute ((section(".text_test_foo"), noinline))
+static void target_foo_umode() {
+    asm volatile ("nop");
+}
+
+__attribute ((section(".data_test_arr"), aligned(8)))
+static volatile unsigned char target_arr[100] = {
+        1,2,3,4,5,6,7,8,
+};
+
+static int detect_pmp_granularity(){
+    unsigned int granule;
+    unsigned long int temp_reg;
+    unsigned long int all_ones = ~0x0UL;
+
+    asm volatile ("csrw pmpaddr0, %0 \n" :: "r"(all_ones) : "memory");
+    asm volatile ("csrr %0, pmpaddr0 \n" : "=r"(temp_reg));
+    asm volatile ("csrw pmpaddr0, %0 \n" :: "r"(0x0) : "memory");
+
+    int g = 2;
+    for(uintptr_t i = 1; i; i<<=1) {
+        if((temp_reg & i) != 0)
+            break;
+        g++;
+    }
+    granule = 1UL << g;
+
+    return granule;
+}
+
+static int mismatch_addr_offset(int granule_size){
+    unsigned int addr_offset = 0;
+
+    if (addr_offset == 0x0){
+        return 0x0;
+    }
+    else {
+        unsigned int mismatch_offset   = granule_size;
+        while (mismatch_offset < addr_offset){
+            mismatch_offset = mismatch_offset << 0x1;
+        }
+        return mismatch_offset;
+    }
+}
+
+/*
+ * On processor_t::reset():
+ *  - set_csr(CSR_PMPADDR0, ~reg_t(0));
+ *    set_csr(CSR_PMPCFG0, PMP_R | PMP_W | PMP_X | PMP_NAPOT);
+ */
+static void set_cfg() {
+#if 1
+    /*
+     * set MSECCFG_RLB to avoid locked
+     */
+    unsigned rlb_value = MSECCFG_RLB;
+    asm volatile ("csrs 0x747, %0 \n"::"r"(rlb_value));
+#endif
+    
+    /*
+     * Set pmp0cfg for M mode (M_MEM), and pmp1cfg for base of TOR.
+     * Then use pmp2cfg for TEST_MEM. Both test code and data share PMP entrance.
+     * Also use pmp3cfg for fixed U mode (U_MEM).
+     * 
+     * Here @pmp_addr_offset:int@ is to create an address mismatch
+     * And @create_pmp_cfg:int@ is to create cfg mismatch.
+     */
+
+    unsigned int mismatch_offset = 0;
+
+    if (mismatch_offset != 0x0){
+        volatile int pmp_granularity = detect_pmp_granularity();
+        mismatch_offset = mismatch_addr_offset(pmp_granularity);
+    }
+    asm volatile ("csrw pmpaddr7, %0 \n" :: "r"(0x8ffffff8 >> 2) : "memory");       // for ibex signature addr
+    asm volatile ("csrw pmpaddr3, %0 \n" :: "r"(U_MEM_END >> 2) : "memory");
+    asm volatile ("csrw pmpaddr2, %0 \n" :: "r"(TEST_MEM_END >> 2) : "memory");
+    asm volatile ("csrw pmpaddr1, %0 \n" :: "r"((TEST_MEM_START + mismatch_offset) >> 2) : "memory");
+    
+#if M_MODE_RWX
+    asm volatile ("csrw pmpaddr0, %0 \n" :: "r"((0x80000000 >> 2) | 0xfffff) : "memory");
+    reg_t cfg0 = (PMP_R | PMP_W | PMP_X | PMP_NAPOT);
+    reg_t cfg1 = (PMP_R | PMP_W | PMP_NAPOT) << 24;
+#else
+    asm volatile ("csrw pmpaddr6, %0 \n" :: "r"(TEST_MEM_START >> 2) : "memory");   // for data
+    asm volatile ("csrw pmpaddr5, %0 \n" :: "r"(0x80010000 >> 2) : "memory");       // for code
+    asm volatile ("csrw pmpaddr4, %0 \n" :: "r"(0x80000000 >> 2) : "memory");       // addr start
+    reg_t cfg0 = PMP_OFF;
+    reg_t cfg1 = PMP_OFF | ((PMP_R | PMP_W | PMP_NAPOT) << 24)
+                         | ((PMP_R | PMP_W | PMP_TOR) << 16) 
+                         | ((PMP_X | PMP_TOR) << 8);
+#endif
+    
+    // Only true for Spike
+//    asm volatile ("csrr %0, pmpcfg0\n":"=r"(cfg0)); 
+//    if (cfg0 != (PMP_R | PMP_W | PMP_X | PMP_NAPOT)) {
+//        exit(cfg0);
+//    }
+    
+    if (0) {    // need to set L bit for M mode code like trap_handling
+#if M_MODE_RWX
+        cfg0 |= PMP_L;
+        cfg1 |= (PMP_L << 24);
+#else
+        cfg1 |= ((PMP_L << 8) | (PMP_L << 16) | (PMP_L << 24));
+#endif
+    }
+    
+    cfg0 |= (PMP_R | PMP_W | PMP_X | PMP_TOR) << 24;    // for U_MEM
+#if 1
+    cfg0 |= ( (0 ? PMP_R : 0)
+            | (0 ? PMP_W : 0)
+            | (0 ? PMP_X : 0) 
+            | PMP_TOR | (0 ? PMP_L : 0)) << 16;
+#endif   
+    
+#if __riscv_xlen == 64
+    cfg0 |= (cfg1 << 32);
+#else
+    asm volatile ("csrw pmpcfg1, %0 \n"
+                :
+                : "r"(cfg1)
+                : "memory");
+#endif // __riscv_xlen == 64
+    
+    asm volatile ("csrw pmpcfg0, %0 \n"
+                :
+                : "r"(cfg0)
+                : "memory");
+    
+    // set proc->state.mseccfg, for MML/MMWP
+    const unsigned seccfg_bits = (0 ? MSECCFG_MML : 0) | (0 ? MSECCFG_MMWP : 0);
+    if (seccfg_bits) {
+        asm volatile ("csrs 0x747, %0 \n"::"r"(seccfg_bits));
+    }
+    
+    // currently dummy since tlb flushed when set_csr on mseccfg
+    asm volatile ("fence.i \n");
+}
+
+// from pmp_ok() side,W/R/X is similar
+__attribute ((noinline))
+static void try_access() {
+#if TEST_RW
+    target_arr[0] += 1;
+    const unsigned long delta = (unsigned long)0x1020304005060708ULL;
+    *(long *)target_arr += delta;
+
+    if (*(long *)target_arr != (unsigned long)0x0807060504030201ULL + delta + 1) {
+        actual_rw_fail = 1;
+    }
+#endif
+
+#if TEST_FETCH
+    actual_x_fail = 1;  // reset inside target_foo()
+    target_foo();
+#endif
+}
+
+// in case mml set, printf cannot be used in U mode
+__attribute ((section(".text_umode")))
+void try_access_umode() {
+#if TEST_RW
+    target_arr[0] += 1;
+//    const unsigned long delta = 0x1020304005060708UL;
+//    *(long *)target_arr += delta;
+
+//    if (*(long *)target_arr != 0x0807060504030201UL + delta + 1) {
+//        actual_rw_fail = 1;
+//    }
+#endif
+
+#if TEST_FETCH
+    target_foo_umode();
+#endif
+    
+    /*
+     * switch to M mode by invoking a write access fault for special address.
+     */
+    volatile unsigned char * p = (unsigned char *)(FAKE_ADDRESS);
+    *p = 1;
+}
+
+static void checkTestResult() {
+    int ret = 0;
+    if (expected_rw_fail != actual_rw_fail) {
+        ret += 1;
+    }
+
+    if (expected_x_fail != actual_x_fail) {
+        ret += 2;
+    }
+    
+    
+    exit(ret); 
+}
+
+int main() {
+    // assert in M mode
+    set_cfg();
+
+    switch_mode();  // in case swith to u mode, branch to try_access_umode directly
+
+    try_access();
+
+    checkTestResult();
+    return 0; // assert 0
+}
+

snapshots/lowRISC_ibex_pr2214/vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw00_x1_l0_match0_mmwp0_mml1.c

@@ -0,0 +1,346 @@
+
+/*
+ * outputs/test_pmp_ok_1_u0_rw00_x1_l0_match0_mmwp0_mml1.c
+ * Generated from gen_pmp_test.cc and test_pmp_ok_1.cc_skel.
+ * 
+ * This test program is expected to start executed from M mode.
+ * That will be easier for us to deal with pmp exception for test.
+ * 
+ * Remarks:
+ * - RW=01 not covered. U/M mode share will be tested separately
+ * - RLB is always 0. CSR access control will be tested separately
+ * 
+ * @changed 2020-Mar-2 soberl
+ *  For RWXL + MML, need to separate R and W combinations.
+ *  Skip RW=01 (share mode) at generator driver side.
+ */
+
+/*
+ * Macros from encoding.h
+ */
+#define MSTATUS_MPP         0x00001800
+
+#define PMP_R     0x01
+#define PMP_W     0x02
+#define PMP_X     0x04
+#define PMP_A     0x18
+#define PMP_L     0x80
+#define PMP_SHIFT 2
+
+#define PMP_OFF   0x0
+#define PMP_TOR   0x08
+#define PMP_NA4   0x10
+#define PMP_NAPOT 0x18
+
+#define MSECCFG_MML  0x1
+#define MSECCFG_MMWP 0x2
+#define MSECCFG_RLB  0x4
+
+#define TEST_RW 1
+#define TEST_FETCH 1
+/*
+ * Whether rwx share single cfg for M mode
+ * When @set_sec_mml@ set, it must be 0, otherwise unexpected exception
+ */
+#define M_MODE_RWX 0
+
+#define CAUSE_LOAD_ACCESS 0x5
+#define CAUSE_STORE_ACCESS 0x7
+
+typedef unsigned long reg_t;
+typedef unsigned long uintptr_t;
+
+/*
+ * functions from syscalls.c
+ */
+#if PRINTF_SUPPORTED
+int printf(const char* fmt, ...);
+#else
+#define printf(...)
+#endif
+
+void __attribute__((noreturn)) tohost_exit(uintptr_t code);
+void exit(int code);
+
+/*
+ * local status
+ */
+#define TEST_MEM_START 0x80200000
+#define TEST_MEM_END 0x80240000
+#define U_MEM_END (TEST_MEM_END + 0x10000)
+#define FAKE_ADDRESS 0x10000000
+
+static const unsigned long expected_rw_fail = 0;
+static unsigned actual_rw_fail = 0;
+
+static const unsigned long expected_x_fail = 1;
+static unsigned actual_x_fail = 0;
+static void checkTestResult(void);
+
+/*
+ * override syscalls.c.
+ *  currently simply skip to nexp instruction
+ */
+uintptr_t handle_trap(uintptr_t cause, uintptr_t epc, uintptr_t regs[32])
+{
+    if (epc >= TEST_MEM_START && epc < TEST_MEM_END) {
+        asm volatile ("nop");
+        actual_x_fail = 1;
+        checkTestResult();
+    } else if (cause == CAUSE_LOAD_ACCESS || cause == CAUSE_STORE_ACCESS) {
+        reg_t addr;
+        asm volatile ("csrr %0, mtval\n" : "=r"(addr));
+        if (addr >= TEST_MEM_START && addr < TEST_MEM_END) {
+            actual_rw_fail = 1;
+            return epc + 4;
+        }
+        
+        if (addr == FAKE_ADDRESS) {
+            asm volatile ("nop");
+            asm volatile ("nop");
+            checkTestResult();
+        }
+    }
+    
+    tohost_exit(1337);
+}
+
+
+// switch (eret) to U mode and resume next PC
+static void switch_to_U() {
+    reg_t tmp;
+    asm volatile (
+            "li %0, %1\n"
+            "\tcsrc mstatus, t0\n"
+            "\tla %0, try_access_umode \n"
+            "\tcsrw mepc, %0\n"
+            "\tli sp, %2\n"
+            "\tmret\n"
+            : "=r"(tmp) : "n"(MSTATUS_MPP), "n"(U_MEM_END) : "memory");
+}
+
+static void switch_mode() {
+#if 0
+    switch_to_U();
+#endif
+}
+
+__attribute ((section(".text_test_foo"), noinline))
+static void target_foo() {
+    asm volatile ("nop");
+    
+    actual_x_fail = 0;
+}
+
+/*
+ * avoid to access actual_x_fail lies in M mode
+ */
+__attribute ((section(".text_test_foo"), noinline))
+static void target_foo_umode() {
+    asm volatile ("nop");
+}
+
+__attribute ((section(".data_test_arr"), aligned(8)))
+static volatile unsigned char target_arr[100] = {
+        1,2,3,4,5,6,7,8,
+};
+
+static int detect_pmp_granularity(){
+    unsigned int granule;
+    unsigned long int temp_reg;
+    unsigned long int all_ones = ~0x0UL;
+
+    asm volatile ("csrw pmpaddr0, %0 \n" :: "r"(all_ones) : "memory");
+    asm volatile ("csrr %0, pmpaddr0 \n" : "=r"(temp_reg));
+    asm volatile ("csrw pmpaddr0, %0 \n" :: "r"(0x0) : "memory");
+
+    int g = 2;
+    for(uintptr_t i = 1; i; i<<=1) {
+        if((temp_reg & i) != 0)
+            break;
+        g++;
+    }
+    granule = 1UL << g;
+
+    return granule;
+}
+
+static int mismatch_addr_offset(int granule_size){
+    unsigned int addr_offset = 256;
+
+    if (addr_offset == 0x0){
+        return 0x0;
+    }
+    else {
+        unsigned int mismatch_offset   = granule_size;
+        while (mismatch_offset < addr_offset){
+            mismatch_offset = mismatch_offset << 0x1;
+        }
+        return mismatch_offset;
+    }
+}
+
+/*
+ * On processor_t::reset():
+ *  - set_csr(CSR_PMPADDR0, ~reg_t(0));
+ *    set_csr(CSR_PMPCFG0, PMP_R | PMP_W | PMP_X | PMP_NAPOT);
+ */
+static void set_cfg() {
+#if 1
+    /*
+     * set MSECCFG_RLB to avoid locked
+     */
+    unsigned rlb_value = MSECCFG_RLB;
+    asm volatile ("csrs 0x747, %0 \n"::"r"(rlb_value));
+#endif
+    
+    /*
+     * Set pmp0cfg for M mode (M_MEM), and pmp1cfg for base of TOR.
+     * Then use pmp2cfg for TEST_MEM. Both test code and data share PMP entrance.
+     * Also use pmp3cfg for fixed U mode (U_MEM).
+     * 
+     * Here @pmp_addr_offset:int@ is to create an address mismatch
+     * And @create_pmp_cfg:int@ is to create cfg mismatch.
+     */
+
+    unsigned int mismatch_offset = 256;
+
+    if (mismatch_offset != 0x0){
+        volatile int pmp_granularity = detect_pmp_granularity();
+        mismatch_offset = mismatch_addr_offset(pmp_granularity);
+    }
+    asm volatile ("csrw pmpaddr7, %0 \n" :: "r"(0x8ffffff8 >> 2) : "memory");       // for ibex signature addr
+    asm volatile ("csrw pmpaddr3, %0 \n" :: "r"(U_MEM_END >> 2) : "memory");
+    asm volatile ("csrw pmpaddr2, %0 \n" :: "r"(TEST_MEM_END >> 2) : "memory");
+    asm volatile ("csrw pmpaddr1, %0 \n" :: "r"((TEST_MEM_START + mismatch_offset) >> 2) : "memory");
+    
+#if M_MODE_RWX
+    asm volatile ("csrw pmpaddr0, %0 \n" :: "r"((0x80000000 >> 2) | 0xfffff) : "memory");
+    reg_t cfg0 = (PMP_R | PMP_W | PMP_X | PMP_NAPOT);
+    reg_t cfg1 = (PMP_R | PMP_W | PMP_NAPOT) << 24;
+#else
+    asm volatile ("csrw pmpaddr6, %0 \n" :: "r"(TEST_MEM_START >> 2) : "memory");   // for data
+    asm volatile ("csrw pmpaddr5, %0 \n" :: "r"(0x80010000 >> 2) : "memory");       // for code
+    asm volatile ("csrw pmpaddr4, %0 \n" :: "r"(0x80000000 >> 2) : "memory");       // addr start
+    reg_t cfg0 = PMP_OFF;
+    reg_t cfg1 = PMP_OFF | ((PMP_R | PMP_W | PMP_NAPOT) << 24)
+                         | ((PMP_R | PMP_W | PMP_TOR) << 16) 
+                         | ((PMP_X | PMP_TOR) << 8);
+#endif
+    
+    // Only true for Spike
+//    asm volatile ("csrr %0, pmpcfg0\n":"=r"(cfg0)); 
+//    if (cfg0 != (PMP_R | PMP_W | PMP_X | PMP_NAPOT)) {
+//        exit(cfg0);
+//    }
+    
+    if (1) {    // need to set L bit for M mode code like trap_handling
+#if M_MODE_RWX
+        cfg0 |= PMP_L;
+        cfg1 |= (PMP_L << 24);
+#else
+        cfg1 |= ((PMP_L << 8) | (PMP_L << 16) | (PMP_L << 24));
+#endif
+    }
+    
+    cfg0 |= (PMP_R | PMP_W | PMP_X | PMP_TOR) << 24;    // for U_MEM
+#if 1
+    cfg0 |= ( (0 ? PMP_R : 0)
+            | (0 ? PMP_W : 0)
+            | (1 ? PMP_X : 0) 
+            | PMP_TOR | (0 ? PMP_L : 0)) << 16;
+#endif   
+    
+#if __riscv_xlen == 64
+    cfg0 |= (cfg1 << 32);
+#else
+    asm volatile ("csrw pmpcfg1, %0 \n"
+                :
+                : "r"(cfg1)
+                : "memory");
+#endif // __riscv_xlen == 64
+    
+    asm volatile ("csrw pmpcfg0, %0 \n"
+                :
+                : "r"(cfg0)
+                : "memory");
+    
+    // set proc->state.mseccfg, for MML/MMWP
+    const unsigned seccfg_bits = (1 ? MSECCFG_MML : 0) | (0 ? MSECCFG_MMWP : 0);
+    if (seccfg_bits) {
+        asm volatile ("csrs 0x747, %0 \n"::"r"(seccfg_bits));
+    }
+    
+    // currently dummy since tlb flushed when set_csr on mseccfg
+    asm volatile ("fence.i \n");
+}
+
+// from pmp_ok() side,W/R/X is similar
+__attribute ((noinline))
+static void try_access() {
+#if TEST_RW
+    target_arr[0] += 1;
+    const unsigned long delta = (unsigned long)0x1020304005060708ULL;
+    *(long *)target_arr += delta;
+
+    if (*(long *)target_arr != (unsigned long)0x0807060504030201ULL + delta + 1) {
+        actual_rw_fail = 1;
+    }
+#endif
+
+#if TEST_FETCH
+    actual_x_fail = 1;  // reset inside target_foo()
+    target_foo();
+#endif
+}
+
+// in case mml set, printf cannot be used in U mode
+__attribute ((section(".text_umode")))
+void try_access_umode() {
+#if TEST_RW
+    target_arr[0] += 1;
+//    const unsigned long delta = 0x1020304005060708UL;
+//    *(long *)target_arr += delta;
+
+//    if (*(long *)target_arr != 0x0807060504030201UL + delta + 1) {
+//        actual_rw_fail = 1;
+//    }
+#endif
+
+#if TEST_FETCH
+    target_foo_umode();
+#endif
+    
+    /*
+     * switch to M mode by invoking a write access fault for special address.
+     */
+    volatile unsigned char * p = (unsigned char *)(FAKE_ADDRESS);
+    *p = 1;
+}
+
+static void checkTestResult() {
+    int ret = 0;
+    if (expected_rw_fail != actual_rw_fail) {
+        ret += 1;
+    }
+
+    if (expected_x_fail != actual_x_fail) {
+        ret += 2;
+    }
+    
+    
+    exit(ret); 
+}
+
+int main() {
+    // assert in M mode
+    set_cfg();
+
+    switch_mode();  // in case swith to u mode, branch to try_access_umode directly
+
+    try_access();
+
+    checkTestResult();
+    return 0; // assert 0
+}
+

snapshots/lowRISC_ibex_pr2214/vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw10_x1_l0_match0_mmwp1_mml0.c

@@ -0,0 +1,346 @@
+
+/*
+ * outputs/test_pmp_ok_1_u0_rw10_x1_l0_match0_mmwp1_mml0.c
+ * Generated from gen_pmp_test.cc and test_pmp_ok_1.cc_skel.
+ * 
+ * This test program is expected to start executed from M mode.
+ * That will be easier for us to deal with pmp exception for test.
+ * 
+ * Remarks:
+ * - RW=01 not covered. U/M mode share will be tested separately
+ * - RLB is always 0. CSR access control will be tested separately
+ * 
+ * @changed 2020-Mar-2 soberl
+ *  For RWXL + MML, need to separate R and W combinations.
+ *  Skip RW=01 (share mode) at generator driver side.
+ */
+
+/*
+ * Macros from encoding.h
+ */
+#define MSTATUS_MPP         0x00001800
+
+#define PMP_R     0x01
+#define PMP_W     0x02
+#define PMP_X     0x04
+#define PMP_A     0x18
+#define PMP_L     0x80
+#define PMP_SHIFT 2
+
+#define PMP_OFF   0x0
+#define PMP_TOR   0x08
+#define PMP_NA4   0x10
+#define PMP_NAPOT 0x18
+
+#define MSECCFG_MML  0x1
+#define MSECCFG_MMWP 0x2
+#define MSECCFG_RLB  0x4
+
+#define TEST_RW 1
+#define TEST_FETCH 1
+/*
+ * Whether rwx share single cfg for M mode
+ * When @set_sec_mml@ set, it must be 0, otherwise unexpected exception
+ */
+#define M_MODE_RWX 1
+
+#define CAUSE_LOAD_ACCESS 0x5
+#define CAUSE_STORE_ACCESS 0x7
+
+typedef unsigned long reg_t;
+typedef unsigned long uintptr_t;
+
+/*
+ * functions from syscalls.c
+ */
+#if PRINTF_SUPPORTED
+int printf(const char* fmt, ...);
+#else
+#define printf(...)
+#endif
+
+void __attribute__((noreturn)) tohost_exit(uintptr_t code);
+void exit(int code);
+
+/*
+ * local status
+ */
+#define TEST_MEM_START 0x80200000
+#define TEST_MEM_END 0x80240000
+#define U_MEM_END (TEST_MEM_END + 0x10000)
+#define FAKE_ADDRESS 0x10000000
+
+static const unsigned long expected_rw_fail = 1;
+static unsigned actual_rw_fail = 0;
+
+static const unsigned long expected_x_fail = 1;
+static unsigned actual_x_fail = 0;
+static void checkTestResult(void);
+
+/*
+ * override syscalls.c.
+ *  currently simply skip to nexp instruction
+ */
+uintptr_t handle_trap(uintptr_t cause, uintptr_t epc, uintptr_t regs[32])
+{
+    if (epc >= TEST_MEM_START && epc < TEST_MEM_END) {
+        asm volatile ("nop");
+        actual_x_fail = 1;
+        checkTestResult();
+    } else if (cause == CAUSE_LOAD_ACCESS || cause == CAUSE_STORE_ACCESS) {
+        reg_t addr;
+        asm volatile ("csrr %0, mtval\n" : "=r"(addr));
+        if (addr >= TEST_MEM_START && addr < TEST_MEM_END) {
+            actual_rw_fail = 1;
+            return epc + 4;
+        }
+        
+        if (addr == FAKE_ADDRESS) {
+            asm volatile ("nop");
+            asm volatile ("nop");
+            checkTestResult();
+        }
+    }
+    
+    tohost_exit(1337);
+}
+
+
+// switch (eret) to U mode and resume next PC
+static void switch_to_U() {
+    reg_t tmp;
+    asm volatile (
+            "li %0, %1\n"
+            "\tcsrc mstatus, t0\n"
+            "\tla %0, try_access_umode \n"
+            "\tcsrw mepc, %0\n"
+            "\tli sp, %2\n"
+            "\tmret\n"
+            : "=r"(tmp) : "n"(MSTATUS_MPP), "n"(U_MEM_END) : "memory");
+}
+
+static void switch_mode() {
+#if 0
+    switch_to_U();
+#endif
+}
+
+__attribute ((section(".text_test_foo"), noinline))
+static void target_foo() {
+    asm volatile ("nop");
+    
+    actual_x_fail = 0;
+}
+
+/*
+ * avoid to access actual_x_fail lies in M mode
+ */
+__attribute ((section(".text_test_foo"), noinline))
+static void target_foo_umode() {
+    asm volatile ("nop");
+}
+
+__attribute ((section(".data_test_arr"), aligned(8)))
+static volatile unsigned char target_arr[100] = {
+        1,2,3,4,5,6,7,8,
+};
+
+static int detect_pmp_granularity(){
+    unsigned int granule;
+    unsigned long int temp_reg;
+    unsigned long int all_ones = ~0x0UL;
+
+    asm volatile ("csrw pmpaddr0, %0 \n" :: "r"(all_ones) : "memory");
+    asm volatile ("csrr %0, pmpaddr0 \n" : "=r"(temp_reg));
+    asm volatile ("csrw pmpaddr0, %0 \n" :: "r"(0x0) : "memory");
+
+    int g = 2;
+    for(uintptr_t i = 1; i; i<<=1) {
+        if((temp_reg & i) != 0)
+            break;
+        g++;
+    }
+    granule = 1UL << g;
+
+    return granule;
+}
+
+static int mismatch_addr_offset(int granule_size){
+    unsigned int addr_offset = 256;
+
+    if (addr_offset == 0x0){
+        return 0x0;
+    }
+    else {
+        unsigned int mismatch_offset   = granule_size;
+        while (mismatch_offset < addr_offset){
+            mismatch_offset = mismatch_offset << 0x1;
+        }
+        return mismatch_offset;
+    }
+}
+
+/*
+ * On processor_t::reset():
+ *  - set_csr(CSR_PMPADDR0, ~reg_t(0));
+ *    set_csr(CSR_PMPCFG0, PMP_R | PMP_W | PMP_X | PMP_NAPOT);
+ */
+static void set_cfg() {
+#if 1
+    /*
+     * set MSECCFG_RLB to avoid locked
+     */
+    unsigned rlb_value = MSECCFG_RLB;
+    asm volatile ("csrs 0x747, %0 \n"::"r"(rlb_value));
+#endif
+    
+    /*
+     * Set pmp0cfg for M mode (M_MEM), and pmp1cfg for base of TOR.
+     * Then use pmp2cfg for TEST_MEM. Both test code and data share PMP entrance.
+     * Also use pmp3cfg for fixed U mode (U_MEM).
+     * 
+     * Here @pmp_addr_offset:int@ is to create an address mismatch
+     * And @create_pmp_cfg:int@ is to create cfg mismatch.
+     */
+
+    unsigned int mismatch_offset = 256;
+
+    if (mismatch_offset != 0x0){
+        volatile int pmp_granularity = detect_pmp_granularity();
+        mismatch_offset = mismatch_addr_offset(pmp_granularity);
+    }
+    asm volatile ("csrw pmpaddr7, %0 \n" :: "r"(0x8ffffff8 >> 2) : "memory");       // for ibex signature addr
+    asm volatile ("csrw pmpaddr3, %0 \n" :: "r"(U_MEM_END >> 2) : "memory");
+    asm volatile ("csrw pmpaddr2, %0 \n" :: "r"(TEST_MEM_END >> 2) : "memory");
+    asm volatile ("csrw pmpaddr1, %0 \n" :: "r"((TEST_MEM_START + mismatch_offset) >> 2) : "memory");
+    
+#if M_MODE_RWX
+    asm volatile ("csrw pmpaddr0, %0 \n" :: "r"((0x80000000 >> 2) | 0xfffff) : "memory");
+    reg_t cfg0 = (PMP_R | PMP_W | PMP_X | PMP_NAPOT);
+    reg_t cfg1 = (PMP_R | PMP_W | PMP_NAPOT) << 24;
+#else
+    asm volatile ("csrw pmpaddr6, %0 \n" :: "r"(TEST_MEM_START >> 2) : "memory");   // for data
+    asm volatile ("csrw pmpaddr5, %0 \n" :: "r"(0x80010000 >> 2) : "memory");       // for code
+    asm volatile ("csrw pmpaddr4, %0 \n" :: "r"(0x80000000 >> 2) : "memory");       // addr start
+    reg_t cfg0 = PMP_OFF;
+    reg_t cfg1 = PMP_OFF | ((PMP_R | PMP_W | PMP_NAPOT) << 24)
+                         | ((PMP_R | PMP_W | PMP_TOR) << 16) 
+                         | ((PMP_X | PMP_TOR) << 8);
+#endif
+    
+    // Only true for Spike
+//    asm volatile ("csrr %0, pmpcfg0\n":"=r"(cfg0)); 
+//    if (cfg0 != (PMP_R | PMP_W | PMP_X | PMP_NAPOT)) {
+//        exit(cfg0);
+//    }
+    
+    if (0) {    // need to set L bit for M mode code like trap_handling
+#if M_MODE_RWX
+        cfg0 |= PMP_L;
+        cfg1 |= (PMP_L << 24);
+#else
+        cfg1 |= ((PMP_L << 8) | (PMP_L << 16) | (PMP_L << 24));
+#endif
+    }
+    
+    cfg0 |= (PMP_R | PMP_W | PMP_X | PMP_TOR) << 24;    // for U_MEM
+#if 1
+    cfg0 |= ( (1 ? PMP_R : 0)
+            | (0 ? PMP_W : 0)
+            | (1 ? PMP_X : 0) 
+            | PMP_TOR | (0 ? PMP_L : 0)) << 16;
+#endif   
+    
+#if __riscv_xlen == 64
+    cfg0 |= (cfg1 << 32);
+#else
+    asm volatile ("csrw pmpcfg1, %0 \n"
+                :
+                : "r"(cfg1)
+                : "memory");
+#endif // __riscv_xlen == 64
+    
+    asm volatile ("csrw pmpcfg0, %0 \n"
+                :
+                : "r"(cfg0)
+                : "memory");
+    
+    // set proc->state.mseccfg, for MML/MMWP
+    const unsigned seccfg_bits = (0 ? MSECCFG_MML : 0) | (1 ? MSECCFG_MMWP : 0);
+    if (seccfg_bits) {
+        asm volatile ("csrs 0x747, %0 \n"::"r"(seccfg_bits));
+    }
+    
+    // currently dummy since tlb flushed when set_csr on mseccfg
+    asm volatile ("fence.i \n");
+}
+
+// from pmp_ok() side,W/R/X is similar
+__attribute ((noinline))
+static void try_access() {
+#if TEST_RW
+    target_arr[0] += 1;
+    const unsigned long delta = (unsigned long)0x1020304005060708ULL;
+    *(long *)target_arr += delta;
+
+    if (*(long *)target_arr != (unsigned long)0x0807060504030201ULL + delta + 1) {
+        actual_rw_fail = 1;
+    }
+#endif
+
+#if TEST_FETCH
+    actual_x_fail = 1;  // reset inside target_foo()
+    target_foo();
+#endif
+}
+
+// in case mml set, printf cannot be used in U mode
+__attribute ((section(".text_umode")))
+void try_access_umode() {
+#if TEST_RW
+    target_arr[0] += 1;
+//    const unsigned long delta = 0x1020304005060708UL;
+//    *(long *)target_arr += delta;
+
+//    if (*(long *)target_arr != 0x0807060504030201UL + delta + 1) {
+//        actual_rw_fail = 1;
+//    }
+#endif
+
+#if TEST_FETCH
+    target_foo_umode();
+#endif
+    
+    /*
+     * switch to M mode by invoking a write access fault for special address.
+     */
+    volatile unsigned char * p = (unsigned char *)(FAKE_ADDRESS);
+    *p = 1;
+}
+
+static void checkTestResult() {
+    int ret = 0;
+    if (expected_rw_fail != actual_rw_fail) {
+        ret += 1;
+    }
+
+    if (expected_x_fail != actual_x_fail) {
+        ret += 2;
+    }
+    
+    
+    exit(ret); 
+}
+
+int main() {
+    // assert in M mode
+    set_cfg();
+
+    switch_mode();  // in case swith to u mode, branch to try_access_umode directly
+
+    try_access();
+
+    checkTestResult();
+    return 0; // assert 0
+}
+

snapshots/lowRISC_ibex_pr2214/vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw11_x1_l0_match0_mmwp0_mml0.c

@@ -0,0 +1,346 @@
+
+/*
+ * outputs/test_pmp_ok_1_u0_rw11_x1_l0_match0_mmwp0_mml0.c
+ * Generated from gen_pmp_test.cc and test_pmp_ok_1.cc_skel.
+ * 
+ * This test program is expected to start executed from M mode.
+ * That will be easier for us to deal with pmp exception for test.
+ * 
+ * Remarks:
+ * - RW=01 not covered. U/M mode share will be tested separately
+ * - RLB is always 0. CSR access control will be tested separately
+ * 
+ * @changed 2020-Mar-2 soberl
+ *  For RWXL + MML, need to separate R and W combinations.
+ *  Skip RW=01 (share mode) at generator driver side.
+ */
+
+/*
+ * Macros from encoding.h
+ */
+#define MSTATUS_MPP         0x00001800
+
+#define PMP_R     0x01
+#define PMP_W     0x02
+#define PMP_X     0x04
+#define PMP_A     0x18
+#define PMP_L     0x80
+#define PMP_SHIFT 2
+
+#define PMP_OFF   0x0
+#define PMP_TOR   0x08
+#define PMP_NA4   0x10
+#define PMP_NAPOT 0x18
+
+#define MSECCFG_MML  0x1
+#define MSECCFG_MMWP 0x2
+#define MSECCFG_RLB  0x4
+
+#define TEST_RW 1
+#define TEST_FETCH 1
+/*
+ * Whether rwx share single cfg for M mode
+ * When @set_sec_mml@ set, it must be 0, otherwise unexpected exception
+ */
+#define M_MODE_RWX 1
+
+#define CAUSE_LOAD_ACCESS 0x5
+#define CAUSE_STORE_ACCESS 0x7
+
+typedef unsigned long reg_t;
+typedef unsigned long uintptr_t;
+
+/*
+ * functions from syscalls.c
+ */
+#if PRINTF_SUPPORTED
+int printf(const char* fmt, ...);
+#else
+#define printf(...)
+#endif
+
+void __attribute__((noreturn)) tohost_exit(uintptr_t code);
+void exit(int code);
+
+/*
+ * local status
+ */
+#define TEST_MEM_START 0x80200000
+#define TEST_MEM_END 0x80240000
+#define U_MEM_END (TEST_MEM_END + 0x10000)
+#define FAKE_ADDRESS 0x10000000
+
+static const unsigned long expected_rw_fail = 0;
+static unsigned actual_rw_fail = 0;
+
+static const unsigned long expected_x_fail = 0;
+static unsigned actual_x_fail = 0;
+static void checkTestResult(void);
+
+/*
+ * override syscalls.c.
+ *  currently simply skip to nexp instruction
+ */
+uintptr_t handle_trap(uintptr_t cause, uintptr_t epc, uintptr_t regs[32])
+{
+    if (epc >= TEST_MEM_START && epc < TEST_MEM_END) {
+        asm volatile ("nop");
+        actual_x_fail = 1;
+        checkTestResult();
+    } else if (cause == CAUSE_LOAD_ACCESS || cause == CAUSE_STORE_ACCESS) {
+        reg_t addr;
+        asm volatile ("csrr %0, mtval\n" : "=r"(addr));
+        if (addr >= TEST_MEM_START && addr < TEST_MEM_END) {
+            actual_rw_fail = 1;
+            return epc + 4;
+        }
+        
+        if (addr == FAKE_ADDRESS) {
+            asm volatile ("nop");
+            asm volatile ("nop");
+            checkTestResult();
+        }
+    }
+    
+    tohost_exit(1337);
+}
+
+
+// switch (eret) to U mode and resume next PC
+static void switch_to_U() {
+    reg_t tmp;
+    asm volatile (
+            "li %0, %1\n"
+            "\tcsrc mstatus, t0\n"
+            "\tla %0, try_access_umode \n"
+            "\tcsrw mepc, %0\n"
+            "\tli sp, %2\n"
+            "\tmret\n"
+            : "=r"(tmp) : "n"(MSTATUS_MPP), "n"(U_MEM_END) : "memory");
+}
+
+static void switch_mode() {
+#if 0
+    switch_to_U();
+#endif
+}
+
+__attribute ((section(".text_test_foo"), noinline))
+static void target_foo() {
+    asm volatile ("nop");
+    
+    actual_x_fail = 0;
+}
+
+/*
+ * avoid to access actual_x_fail lies in M mode
+ */
+__attribute ((section(".text_test_foo"), noinline))
+static void target_foo_umode() {
+    asm volatile ("nop");
+}
+
+__attribute ((section(".data_test_arr"), aligned(8)))
+static volatile unsigned char target_arr[100] = {
+        1,2,3,4,5,6,7,8,
+};
+
+static int detect_pmp_granularity(){
+    unsigned int granule;
+    unsigned long int temp_reg;
+    unsigned long int all_ones = ~0x0UL;
+
+    asm volatile ("csrw pmpaddr0, %0 \n" :: "r"(all_ones) : "memory");
+    asm volatile ("csrr %0, pmpaddr0 \n" : "=r"(temp_reg));
+    asm volatile ("csrw pmpaddr0, %0 \n" :: "r"(0x0) : "memory");
+
+    int g = 2;
+    for(uintptr_t i = 1; i; i<<=1) {
+        if((temp_reg & i) != 0)
+            break;
+        g++;
+    }
+    granule = 1UL << g;
+
+    return granule;
+}
+
+static int mismatch_addr_offset(int granule_size){
+    unsigned int addr_offset = 256;
+
+    if (addr_offset == 0x0){
+        return 0x0;
+    }
+    else {
+        unsigned int mismatch_offset   = granule_size;
+        while (mismatch_offset < addr_offset){
+            mismatch_offset = mismatch_offset << 0x1;
+        }
+        return mismatch_offset;
+    }
+}
+
+/*
+ * On processor_t::reset():
+ *  - set_csr(CSR_PMPADDR0, ~reg_t(0));
+ *    set_csr(CSR_PMPCFG0, PMP_R | PMP_W | PMP_X | PMP_NAPOT);
+ */
+static void set_cfg() {
+#if 1
+    /*
+     * set MSECCFG_RLB to avoid locked
+     */
+    unsigned rlb_value = MSECCFG_RLB;
+    asm volatile ("csrs 0x747, %0 \n"::"r"(rlb_value));
+#endif
+    
+    /*
+     * Set pmp0cfg for M mode (M_MEM), and pmp1cfg for base of TOR.
+     * Then use pmp2cfg for TEST_MEM. Both test code and data share PMP entrance.
+     * Also use pmp3cfg for fixed U mode (U_MEM).
+     * 
+     * Here @pmp_addr_offset:int@ is to create an address mismatch
+     * And @create_pmp_cfg:int@ is to create cfg mismatch.
+     */
+
+    unsigned int mismatch_offset = 256;
+
+    if (mismatch_offset != 0x0){
+        volatile int pmp_granularity = detect_pmp_granularity();
+        mismatch_offset = mismatch_addr_offset(pmp_granularity);
+    }
+    asm volatile ("csrw pmpaddr7, %0 \n" :: "r"(0x8ffffff8 >> 2) : "memory");       // for ibex signature addr
+    asm volatile ("csrw pmpaddr3, %0 \n" :: "r"(U_MEM_END >> 2) : "memory");
+    asm volatile ("csrw pmpaddr2, %0 \n" :: "r"(TEST_MEM_END >> 2) : "memory");
+    asm volatile ("csrw pmpaddr1, %0 \n" :: "r"((TEST_MEM_START + mismatch_offset) >> 2) : "memory");
+    
+#if M_MODE_RWX
+    asm volatile ("csrw pmpaddr0, %0 \n" :: "r"((0x80000000 >> 2) | 0xfffff) : "memory");
+    reg_t cfg0 = (PMP_R | PMP_W | PMP_X | PMP_NAPOT);
+    reg_t cfg1 = (PMP_R | PMP_W | PMP_NAPOT) << 24;
+#else
+    asm volatile ("csrw pmpaddr6, %0 \n" :: "r"(TEST_MEM_START >> 2) : "memory");   // for data
+    asm volatile ("csrw pmpaddr5, %0 \n" :: "r"(0x80010000 >> 2) : "memory");       // for code
+    asm volatile ("csrw pmpaddr4, %0 \n" :: "r"(0x80000000 >> 2) : "memory");       // addr start
+    reg_t cfg0 = PMP_OFF;
+    reg_t cfg1 = PMP_OFF | ((PMP_R | PMP_W | PMP_NAPOT) << 24)
+                         | ((PMP_R | PMP_W | PMP_TOR) << 16) 
+                         | ((PMP_X | PMP_TOR) << 8);
+#endif
+    
+    // Only true for Spike
+//    asm volatile ("csrr %0, pmpcfg0\n":"=r"(cfg0)); 
+//    if (cfg0 != (PMP_R | PMP_W | PMP_X | PMP_NAPOT)) {
+//        exit(cfg0);
+//    }
+    
+    if (0) {    // need to set L bit for M mode code like trap_handling
+#if M_MODE_RWX
+        cfg0 |= PMP_L;
+        cfg1 |= (PMP_L << 24);
+#else
+        cfg1 |= ((PMP_L << 8) | (PMP_L << 16) | (PMP_L << 24));
+#endif
+    }
+    
+    cfg0 |= (PMP_R | PMP_W | PMP_X | PMP_TOR) << 24;    // for U_MEM
+#if 1
+    cfg0 |= ( (1 ? PMP_R : 0)
+            | (1 ? PMP_W : 0)
+            | (1 ? PMP_X : 0) 
+            | PMP_TOR | (0 ? PMP_L : 0)) << 16;
+#endif   
+    
+#if __riscv_xlen == 64
+    cfg0 |= (cfg1 << 32);
+#else
+    asm volatile ("csrw pmpcfg1, %0 \n"
+                :
+                : "r"(cfg1)
+                : "memory");
+#endif // __riscv_xlen == 64
+    
+    asm volatile ("csrw pmpcfg0, %0 \n"
+                :
+                : "r"(cfg0)
+                : "memory");
+    
+    // set proc->state.mseccfg, for MML/MMWP
+    const unsigned seccfg_bits = (0 ? MSECCFG_MML : 0) | (0 ? MSECCFG_MMWP : 0);
+    if (seccfg_bits) {
+        asm volatile ("csrs 0x747, %0 \n"::"r"(seccfg_bits));
+    }
+    
+    // currently dummy since tlb flushed when set_csr on mseccfg
+    asm volatile ("fence.i \n");
+}
+
+// from pmp_ok() side,W/R/X is similar
+__attribute ((noinline))
+static void try_access() {
+#if TEST_RW
+    target_arr[0] += 1;
+    const unsigned long delta = (unsigned long)0x1020304005060708ULL;
+    *(long *)target_arr += delta;
+
+    if (*(long *)target_arr != (unsigned long)0x0807060504030201ULL + delta + 1) {
+        actual_rw_fail = 1;
+    }
+#endif
+
+#if TEST_FETCH
+    actual_x_fail = 1;  // reset inside target_foo()
+    target_foo();
+#endif
+}
+
+// in case mml set, printf cannot be used in U mode
+__attribute ((section(".text_umode")))
+void try_access_umode() {
+#if TEST_RW
+    target_arr[0] += 1;
+//    const unsigned long delta = 0x1020304005060708UL;
+//    *(long *)target_arr += delta;
+
+//    if (*(long *)target_arr != 0x0807060504030201UL + delta + 1) {
+//        actual_rw_fail = 1;
+//    }
+#endif
+
+#if TEST_FETCH
+    target_foo_umode();
+#endif
+    
+    /*
+     * switch to M mode by invoking a write access fault for special address.
+     */
+    volatile unsigned char * p = (unsigned char *)(FAKE_ADDRESS);
+    *p = 1;
+}
+
+static void checkTestResult() {
+    int ret = 0;
+    if (expected_rw_fail != actual_rw_fail) {
+        ret += 1;
+    }
+
+    if (expected_x_fail != actual_x_fail) {
+        ret += 2;
+    }
+    
+    
+    exit(ret); 
+}
+
+int main() {
+    // assert in M mode
+    set_cfg();
+
+    switch_mode();  // in case swith to u mode, branch to try_access_umode directly
+
+    try_access();
+
+    checkTestResult();
+    return 0; // assert 0
+}
+

snapshots/lowRISC_ibex_pr2214/vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw00_x0_l0_match0_mmwp0_mml0.c

@@ -0,0 +1,346 @@
+
+/*
+ * outputs/test_pmp_ok_1_u1_rw00_x0_l0_match0_mmwp0_mml0.c
+ * Generated from gen_pmp_test.cc and test_pmp_ok_1.cc_skel.
+ * 
+ * This test program is expected to start executed from M mode.
+ * That will be easier for us to deal with pmp exception for test.
+ * 
+ * Remarks:
+ * - RW=01 not covered. U/M mode share will be tested separately
+ * - RLB is always 0. CSR access control will be tested separately
+ * 
+ * @changed 2020-Mar-2 soberl
+ *  For RWXL + MML, need to separate R and W combinations.
+ *  Skip RW=01 (share mode) at generator driver side.
+ */
+
+/*
+ * Macros from encoding.h
+ */
+#define MSTATUS_MPP         0x00001800
+
+#define PMP_R     0x01
+#define PMP_W     0x02
+#define PMP_X     0x04
+#define PMP_A     0x18
+#define PMP_L     0x80
+#define PMP_SHIFT 2
+
+#define PMP_OFF   0x0
+#define PMP_TOR   0x08
+#define PMP_NA4   0x10
+#define PMP_NAPOT 0x18
+
+#define MSECCFG_MML  0x1
+#define MSECCFG_MMWP 0x2
+#define MSECCFG_RLB  0x4
+
+#define TEST_RW 1
+#define TEST_FETCH 1
+/*
+ * Whether rwx share single cfg for M mode
+ * When @set_sec_mml@ set, it must be 0, otherwise unexpected exception
+ */
+#define M_MODE_RWX 0
+
+#define CAUSE_LOAD_ACCESS 0x5
+#define CAUSE_STORE_ACCESS 0x7
+
+typedef unsigned long reg_t;
+typedef unsigned long uintptr_t;
+
+/*
+ * functions from syscalls.c
+ */
+#if PRINTF_SUPPORTED
+int printf(const char* fmt, ...);
+#else
+#define printf(...)
+#endif
+
+void __attribute__((noreturn)) tohost_exit(uintptr_t code);
+void exit(int code);
+
+/*
+ * local status
+ */
+#define TEST_MEM_START 0x80200000
+#define TEST_MEM_END 0x80240000
+#define U_MEM_END (TEST_MEM_END + 0x10000)
+#define FAKE_ADDRESS 0x10000000
+
+static const unsigned long expected_rw_fail = 1;
+static unsigned actual_rw_fail = 0;
+
+static const unsigned long expected_x_fail = 1;
+static unsigned actual_x_fail = 0;
+static void checkTestResult(void);
+
+/*
+ * override syscalls.c.
+ *  currently simply skip to nexp instruction
+ */
+uintptr_t handle_trap(uintptr_t cause, uintptr_t epc, uintptr_t regs[32])
+{
+    if (epc >= TEST_MEM_START && epc < TEST_MEM_END) {
+        asm volatile ("nop");
+        actual_x_fail = 1;
+        checkTestResult();
+    } else if (cause == CAUSE_LOAD_ACCESS || cause == CAUSE_STORE_ACCESS) {
+        reg_t addr;
+        asm volatile ("csrr %0, mtval\n" : "=r"(addr));
+        if (addr >= TEST_MEM_START && addr < TEST_MEM_END) {
+            actual_rw_fail = 1;
+            return epc + 4;
+        }
+        
+        if (addr == FAKE_ADDRESS) {
+            asm volatile ("nop");
+            asm volatile ("nop");
+            checkTestResult();
+        }
+    }
+    
+    tohost_exit(1337);
+}
+
+
+// switch (eret) to U mode and resume next PC
+static void switch_to_U() {
+    reg_t tmp;
+    asm volatile (
+            "li %0, %1\n"
+            "\tcsrc mstatus, t0\n"
+            "\tla %0, try_access_umode \n"
+            "\tcsrw mepc, %0\n"
+            "\tli sp, %2\n"
+            "\tmret\n"
+            : "=r"(tmp) : "n"(MSTATUS_MPP), "n"(U_MEM_END) : "memory");
+}
+
+static void switch_mode() {
+#if 1
+    switch_to_U();
+#endif
+}
+
+__attribute ((section(".text_test_foo"), noinline))
+static void target_foo() {
+    asm volatile ("nop");
+    
+    actual_x_fail = 0;
+}
+
+/*
+ * avoid to access actual_x_fail lies in M mode
+ */
+__attribute ((section(".text_test_foo"), noinline))
+static void target_foo_umode() {
+    asm volatile ("nop");
+}
+
+__attribute ((section(".data_test_arr"), aligned(8)))
+static volatile unsigned char target_arr[100] = {
+        1,2,3,4,5,6,7,8,
+};
+
+static int detect_pmp_granularity(){
+    unsigned int granule;
+    unsigned long int temp_reg;
+    unsigned long int all_ones = ~0x0UL;
+
+    asm volatile ("csrw pmpaddr0, %0 \n" :: "r"(all_ones) : "memory");
+    asm volatile ("csrr %0, pmpaddr0 \n" : "=r"(temp_reg));
+    asm volatile ("csrw pmpaddr0, %0 \n" :: "r"(0x0) : "memory");
+
+    int g = 2;
+    for(uintptr_t i = 1; i; i<<=1) {
+        if((temp_reg & i) != 0)
+            break;
+        g++;
+    }
+    granule = 1UL << g;
+
+    return granule;
+}
+
+static int mismatch_addr_offset(int granule_size){
+    unsigned int addr_offset = 0;
+
+    if (addr_offset == 0x0){
+        return 0x0;
+    }
+    else {
+        unsigned int mismatch_offset   = granule_size;
+        while (mismatch_offset < addr_offset){
+            mismatch_offset = mismatch_offset << 0x1;
+        }
+        return mismatch_offset;
+    }
+}
+
+/*
+ * On processor_t::reset():
+ *  - set_csr(CSR_PMPADDR0, ~reg_t(0));
+ *    set_csr(CSR_PMPCFG0, PMP_R | PMP_W | PMP_X | PMP_NAPOT);
+ */
+static void set_cfg() {
+#if 1
+    /*
+     * set MSECCFG_RLB to avoid locked
+     */
+    unsigned rlb_value = MSECCFG_RLB;
+    asm volatile ("csrs 0x747, %0 \n"::"r"(rlb_value));
+#endif
+    
+    /*
+     * Set pmp0cfg for M mode (M_MEM), and pmp1cfg for base of TOR.
+     * Then use pmp2cfg for TEST_MEM. Both test code and data share PMP entrance.
+     * Also use pmp3cfg for fixed U mode (U_MEM).
+     * 
+     * Here @pmp_addr_offset:int@ is to create an address mismatch
+     * And @create_pmp_cfg:int@ is to create cfg mismatch.
+     */
+
+    unsigned int mismatch_offset = 0;
+
+    if (mismatch_offset != 0x0){
+        volatile int pmp_granularity = detect_pmp_granularity();
+        mismatch_offset = mismatch_addr_offset(pmp_granularity);
+    }
+    asm volatile ("csrw pmpaddr7, %0 \n" :: "r"(0x8ffffff8 >> 2) : "memory");       // for ibex signature addr
+    asm volatile ("csrw pmpaddr3, %0 \n" :: "r"(U_MEM_END >> 2) : "memory");
+    asm volatile ("csrw pmpaddr2, %0 \n" :: "r"(TEST_MEM_END >> 2) : "memory");
+    asm volatile ("csrw pmpaddr1, %0 \n" :: "r"((TEST_MEM_START + mismatch_offset) >> 2) : "memory");
+    
+#if M_MODE_RWX
+    asm volatile ("csrw pmpaddr0, %0 \n" :: "r"((0x80000000 >> 2) | 0xfffff) : "memory");
+    reg_t cfg0 = (PMP_R | PMP_W | PMP_X | PMP_NAPOT);
+    reg_t cfg1 = (PMP_R | PMP_W | PMP_NAPOT) << 24;
+#else
+    asm volatile ("csrw pmpaddr6, %0 \n" :: "r"(TEST_MEM_START >> 2) : "memory");   // for data
+    asm volatile ("csrw pmpaddr5, %0 \n" :: "r"(0x80010000 >> 2) : "memory");       // for code
+    asm volatile ("csrw pmpaddr4, %0 \n" :: "r"(0x80000000 >> 2) : "memory");       // addr start
+    reg_t cfg0 = PMP_OFF;
+    reg_t cfg1 = PMP_OFF | ((PMP_R | PMP_W | PMP_NAPOT) << 24)
+                         | ((PMP_R | PMP_W | PMP_TOR) << 16) 
+                         | ((PMP_X | PMP_TOR) << 8);
+#endif
+    
+    // Only true for Spike
+//    asm volatile ("csrr %0, pmpcfg0\n":"=r"(cfg0)); 
+//    if (cfg0 != (PMP_R | PMP_W | PMP_X | PMP_NAPOT)) {
+//        exit(cfg0);
+//    }
+    
+    if (0) {    // need to set L bit for M mode code like trap_handling
+#if M_MODE_RWX
+        cfg0 |= PMP_L;
+        cfg1 |= (PMP_L << 24);
+#else
+        cfg1 |= ((PMP_L << 8) | (PMP_L << 16) | (PMP_L << 24));
+#endif
+    }
+    
+    cfg0 |= (PMP_R | PMP_W | PMP_X | PMP_TOR) << 24;    // for U_MEM
+#if 0
+    cfg0 |= ( (0 ? PMP_R : 0)
+            | (0 ? PMP_W : 0)
+            | (0 ? PMP_X : 0) 
+            | PMP_TOR | (0 ? PMP_L : 0)) << 16;
+#endif   
+    
+#if __riscv_xlen == 64
+    cfg0 |= (cfg1 << 32);
+#else
+    asm volatile ("csrw pmpcfg1, %0 \n"
+                :
+                : "r"(cfg1)
+                : "memory");
+#endif // __riscv_xlen == 64
+    
+    asm volatile ("csrw pmpcfg0, %0 \n"
+                :
+                : "r"(cfg0)
+                : "memory");
+    
+    // set proc->state.mseccfg, for MML/MMWP
+    const unsigned seccfg_bits = (0 ? MSECCFG_MML : 0) | (0 ? MSECCFG_MMWP : 0);
+    if (seccfg_bits) {
+        asm volatile ("csrs 0x747, %0 \n"::"r"(seccfg_bits));
+    }
+    
+    // currently dummy since tlb flushed when set_csr on mseccfg
+    asm volatile ("fence.i \n");
+}
+
+// from pmp_ok() side,W/R/X is similar
+__attribute ((noinline))
+static void try_access() {
+#if TEST_RW
+    target_arr[0] += 1;
+    const unsigned long delta = (unsigned long)0x1020304005060708ULL;
+    *(long *)target_arr += delta;
+
+    if (*(long *)target_arr != (unsigned long)0x0807060504030201ULL + delta + 1) {
+        actual_rw_fail = 1;
+    }
+#endif
+
+#if TEST_FETCH
+    actual_x_fail = 1;  // reset inside target_foo()
+    target_foo();
+#endif
+}
+
+// in case mml set, printf cannot be used in U mode
+__attribute ((section(".text_umode")))
+void try_access_umode() {
+#if TEST_RW
+    target_arr[0] += 1;
+//    const unsigned long delta = 0x1020304005060708UL;
+//    *(long *)target_arr += delta;
+
+//    if (*(long *)target_arr != 0x0807060504030201UL + delta + 1) {
+//        actual_rw_fail = 1;
+//    }
+#endif
+
+#if TEST_FETCH
+    target_foo_umode();
+#endif
+    
+    /*
+     * switch to M mode by invoking a write access fault for special address.
+     */
+    volatile unsigned char * p = (unsigned char *)(FAKE_ADDRESS);
+    *p = 1;
+}
+
+static void checkTestResult() {
+    int ret = 0;
+    if (expected_rw_fail != actual_rw_fail) {
+        ret += 1;
+    }
+
+    if (expected_x_fail != actual_x_fail) {
+        ret += 2;
+    }
+    
+    
+    exit(ret); 
+}
+
+int main() {
+    // assert in M mode
+    set_cfg();
+
+    switch_mode();  // in case swith to u mode, branch to try_access_umode directly
+
+    try_access();
+
+    checkTestResult();
+    return 0; // assert 0
+}
+

snapshots/lowRISC_ibex_pr2214/vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw00_x0_l0_match1_mmwp0_mml1.c

@@ -0,0 +1,346 @@
+
+/*
+ * outputs/test_pmp_ok_1_u1_rw00_x0_l0_match1_mmwp0_mml1.c
+ * Generated from gen_pmp_test.cc and test_pmp_ok_1.cc_skel.
+ * 
+ * This test program is expected to start executed from M mode.
+ * That will be easier for us to deal with pmp exception for test.
+ * 
+ * Remarks:
+ * - RW=01 not covered. U/M mode share will be tested separately
+ * - RLB is always 0. CSR access control will be tested separately
+ * 
+ * @changed 2020-Mar-2 soberl
+ *  For RWXL + MML, need to separate R and W combinations.
+ *  Skip RW=01 (share mode) at generator driver side.
+ */
+
+/*
+ * Macros from encoding.h
+ */
+#define MSTATUS_MPP         0x00001800
+
+#define PMP_R     0x01
+#define PMP_W     0x02
+#define PMP_X     0x04
+#define PMP_A     0x18
+#define PMP_L     0x80
+#define PMP_SHIFT 2
+
+#define PMP_OFF   0x0
+#define PMP_TOR   0x08
+#define PMP_NA4   0x10
+#define PMP_NAPOT 0x18
+
+#define MSECCFG_MML  0x1
+#define MSECCFG_MMWP 0x2
+#define MSECCFG_RLB  0x4
+
+#define TEST_RW 1
+#define TEST_FETCH 1
+/*
+ * Whether rwx share single cfg for M mode
+ * When @set_sec_mml@ set, it must be 0, otherwise unexpected exception
+ */
+#define M_MODE_RWX 0
+
+#define CAUSE_LOAD_ACCESS 0x5
+#define CAUSE_STORE_ACCESS 0x7
+
+typedef unsigned long reg_t;
+typedef unsigned long uintptr_t;
+
+/*
+ * functions from syscalls.c
+ */
+#if PRINTF_SUPPORTED
+int printf(const char* fmt, ...);
+#else
+#define printf(...)
+#endif
+
+void __attribute__((noreturn)) tohost_exit(uintptr_t code);
+void exit(int code);
+
+/*
+ * local status
+ */
+#define TEST_MEM_START 0x80200000
+#define TEST_MEM_END 0x80240000
+#define U_MEM_END (TEST_MEM_END + 0x10000)
+#define FAKE_ADDRESS 0x10000000
+
+static const unsigned long expected_rw_fail = 1;
+static unsigned actual_rw_fail = 0;
+
+static const unsigned long expected_x_fail = 1;
+static unsigned actual_x_fail = 0;
+static void checkTestResult(void);
+
+/*
+ * override syscalls.c.
+ *  currently simply skip to nexp instruction
+ */
+uintptr_t handle_trap(uintptr_t cause, uintptr_t epc, uintptr_t regs[32])
+{
+    if (epc >= TEST_MEM_START && epc < TEST_MEM_END) {
+        asm volatile ("nop");
+        actual_x_fail = 1;
+        checkTestResult();
+    } else if (cause == CAUSE_LOAD_ACCESS || cause == CAUSE_STORE_ACCESS) {
+        reg_t addr;
+        asm volatile ("csrr %0, mtval\n" : "=r"(addr));
+        if (addr >= TEST_MEM_START && addr < TEST_MEM_END) {
+            actual_rw_fail = 1;
+            return epc + 4;
+        }
+        
+        if (addr == FAKE_ADDRESS) {
+            asm volatile ("nop");
+            asm volatile ("nop");
+            checkTestResult();
+        }
+    }
+    
+    tohost_exit(1337);
+}
+
+
+// switch (eret) to U mode and resume next PC
+static void switch_to_U() {
+    reg_t tmp;
+    asm volatile (
+            "li %0, %1\n"
+            "\tcsrc mstatus, t0\n"
+            "\tla %0, try_access_umode \n"
+            "\tcsrw mepc, %0\n"
+            "\tli sp, %2\n"
+            "\tmret\n"
+            : "=r"(tmp) : "n"(MSTATUS_MPP), "n"(U_MEM_END) : "memory");
+}
+
+static void switch_mode() {
+#if 1
+    switch_to_U();
+#endif
+}
+
+__attribute ((section(".text_test_foo"), noinline))
+static void target_foo() {
+    asm volatile ("nop");
+    
+    actual_x_fail = 0;
+}
+
+/*
+ * avoid to access actual_x_fail lies in M mode
+ */
+__attribute ((section(".text_test_foo"), noinline))
+static void target_foo_umode() {
+    asm volatile ("nop");
+}
+
+__attribute ((section(".data_test_arr"), aligned(8)))
+static volatile unsigned char target_arr[100] = {
+        1,2,3,4,5,6,7,8,
+};
+
+static int detect_pmp_granularity(){
+    unsigned int granule;
+    unsigned long int temp_reg;
+    unsigned long int all_ones = ~0x0UL;
+
+    asm volatile ("csrw pmpaddr0, %0 \n" :: "r"(all_ones) : "memory");
+    asm volatile ("csrr %0, pmpaddr0 \n" : "=r"(temp_reg));
+    asm volatile ("csrw pmpaddr0, %0 \n" :: "r"(0x0) : "memory");
+
+    int g = 2;
+    for(uintptr_t i = 1; i; i<<=1) {
+        if((temp_reg & i) != 0)
+            break;
+        g++;
+    }
+    granule = 1UL << g;
+
+    return granule;
+}
+
+static int mismatch_addr_offset(int granule_size){
+    unsigned int addr_offset = 0;
+
+    if (addr_offset == 0x0){
+        return 0x0;
+    }
+    else {
+        unsigned int mismatch_offset   = granule_size;
+        while (mismatch_offset < addr_offset){
+            mismatch_offset = mismatch_offset << 0x1;
+        }
+        return mismatch_offset;
+    }
+}
+
+/*
+ * On processor_t::reset():
+ *  - set_csr(CSR_PMPADDR0, ~reg_t(0));
+ *    set_csr(CSR_PMPCFG0, PMP_R | PMP_W | PMP_X | PMP_NAPOT);
+ */
+static void set_cfg() {
+#if 1
+    /*
+     * set MSECCFG_RLB to avoid locked
+     */
+    unsigned rlb_value = MSECCFG_RLB;
+    asm volatile ("csrs 0x747, %0 \n"::"r"(rlb_value));
+#endif
+    
+    /*
+     * Set pmp0cfg for M mode (M_MEM), and pmp1cfg for base of TOR.
+     * Then use pmp2cfg for TEST_MEM. Both test code and data share PMP entrance.
+     * Also use pmp3cfg for fixed U mode (U_MEM).
+     * 
+     * Here @pmp_addr_offset:int@ is to create an address mismatch
+     * And @create_pmp_cfg:int@ is to create cfg mismatch.
+     */
+
+    unsigned int mismatch_offset = 0;
+
+    if (mismatch_offset != 0x0){
+        volatile int pmp_granularity = detect_pmp_granularity();
+        mismatch_offset = mismatch_addr_offset(pmp_granularity);
+    }
+    asm volatile ("csrw pmpaddr7, %0 \n" :: "r"(0x8ffffff8 >> 2) : "memory");       // for ibex signature addr
+    asm volatile ("csrw pmpaddr3, %0 \n" :: "r"(U_MEM_END >> 2) : "memory");
+    asm volatile ("csrw pmpaddr2, %0 \n" :: "r"(TEST_MEM_END >> 2) : "memory");
+    asm volatile ("csrw pmpaddr1, %0 \n" :: "r"((TEST_MEM_START + mismatch_offset) >> 2) : "memory");
+    
+#if M_MODE_RWX
+    asm volatile ("csrw pmpaddr0, %0 \n" :: "r"((0x80000000 >> 2) | 0xfffff) : "memory");
+    reg_t cfg0 = (PMP_R | PMP_W | PMP_X | PMP_NAPOT);
+    reg_t cfg1 = (PMP_R | PMP_W | PMP_NAPOT) << 24;
+#else
+    asm volatile ("csrw pmpaddr6, %0 \n" :: "r"(TEST_MEM_START >> 2) : "memory");   // for data
+    asm volatile ("csrw pmpaddr5, %0 \n" :: "r"(0x80010000 >> 2) : "memory");       // for code
+    asm volatile ("csrw pmpaddr4, %0 \n" :: "r"(0x80000000 >> 2) : "memory");       // addr start
+    reg_t cfg0 = PMP_OFF;
+    reg_t cfg1 = PMP_OFF | ((PMP_R | PMP_W | PMP_NAPOT) << 24)
+                         | ((PMP_R | PMP_W | PMP_TOR) << 16) 
+                         | ((PMP_X | PMP_TOR) << 8);
+#endif
+    
+    // Only true for Spike
+//    asm volatile ("csrr %0, pmpcfg0\n":"=r"(cfg0)); 
+//    if (cfg0 != (PMP_R | PMP_W | PMP_X | PMP_NAPOT)) {
+//        exit(cfg0);
+//    }
+    
+    if (1) {    // need to set L bit for M mode code like trap_handling
+#if M_MODE_RWX
+        cfg0 |= PMP_L;
+        cfg1 |= (PMP_L << 24);
+#else
+        cfg1 |= ((PMP_L << 8) | (PMP_L << 16) | (PMP_L << 24));
+#endif
+    }
+    
+    cfg0 |= (PMP_R | PMP_W | PMP_X | PMP_TOR) << 24;    // for U_MEM
+#if 1
+    cfg0 |= ( (0 ? PMP_R : 0)
+            | (0 ? PMP_W : 0)
+            | (0 ? PMP_X : 0) 
+            | PMP_TOR | (0 ? PMP_L : 0)) << 16;
+#endif   
+    
+#if __riscv_xlen == 64
+    cfg0 |= (cfg1 << 32);
+#else
+    asm volatile ("csrw pmpcfg1, %0 \n"
+                :
+                : "r"(cfg1)
+                : "memory");
+#endif // __riscv_xlen == 64
+    
+    asm volatile ("csrw pmpcfg0, %0 \n"
+                :
+                : "r"(cfg0)
+                : "memory");
+    
+    // set proc->state.mseccfg, for MML/MMWP
+    const unsigned seccfg_bits = (1 ? MSECCFG_MML : 0) | (0 ? MSECCFG_MMWP : 0);
+    if (seccfg_bits) {
+        asm volatile ("csrs 0x747, %0 \n"::"r"(seccfg_bits));
+    }
+    
+    // currently dummy since tlb flushed when set_csr on mseccfg
+    asm volatile ("fence.i \n");
+}
+
+// from pmp_ok() side,W/R/X is similar
+__attribute ((noinline))
+static void try_access() {
+#if TEST_RW
+    target_arr[0] += 1;
+    const unsigned long delta = (unsigned long)0x1020304005060708ULL;
+    *(long *)target_arr += delta;
+
+    if (*(long *)target_arr != (unsigned long)0x0807060504030201ULL + delta + 1) {
+        actual_rw_fail = 1;
+    }
+#endif
+
+#if TEST_FETCH
+    actual_x_fail = 1;  // reset inside target_foo()
+    target_foo();
+#endif
+}
+
+// in case mml set, printf cannot be used in U mode
+__attribute ((section(".text_umode")))
+void try_access_umode() {
+#if TEST_RW
+    target_arr[0] += 1;
+//    const unsigned long delta = 0x1020304005060708UL;
+//    *(long *)target_arr += delta;
+
+//    if (*(long *)target_arr != 0x0807060504030201UL + delta + 1) {
+//        actual_rw_fail = 1;
+//    }
+#endif
+
+#if TEST_FETCH
+    target_foo_umode();
+#endif
+    
+    /*
+     * switch to M mode by invoking a write access fault for special address.
+     */
+    volatile unsigned char * p = (unsigned char *)(FAKE_ADDRESS);
+    *p = 1;
+}
+
+static void checkTestResult() {
+    int ret = 0;
+    if (expected_rw_fail != actual_rw_fail) {
+        ret += 1;
+    }
+
+    if (expected_x_fail != actual_x_fail) {
+        ret += 2;
+    }
+    
+    
+    exit(ret); 
+}
+
+int main() {
+    // assert in M mode
+    set_cfg();
+
+    switch_mode();  // in case swith to u mode, branch to try_access_umode directly
+
+    try_access();
+
+    checkTestResult();
+    return 0; // assert 0
+}
+

snapshots/lowRISC_ibex_pr2214/vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw00_x0_l1_match1_mmwp0_mml0.c

@@ -0,0 +1,346 @@
+
+/*
+ * outputs/test_pmp_ok_1_u1_rw00_x0_l1_match1_mmwp0_mml0.c
+ * Generated from gen_pmp_test.cc and test_pmp_ok_1.cc_skel.
+ * 
+ * This test program is expected to start executed from M mode.
+ * That will be easier for us to deal with pmp exception for test.
+ * 
+ * Remarks:
+ * - RW=01 not covered. U/M mode share will be tested separately
+ * - RLB is always 0. CSR access control will be tested separately
+ * 
+ * @changed 2020-Mar-2 soberl
+ *  For RWXL + MML, need to separate R and W combinations.
+ *  Skip RW=01 (share mode) at generator driver side.
+ */
+
+/*
+ * Macros from encoding.h
+ */
+#define MSTATUS_MPP         0x00001800
+
+#define PMP_R     0x01
+#define PMP_W     0x02
+#define PMP_X     0x04
+#define PMP_A     0x18
+#define PMP_L     0x80
+#define PMP_SHIFT 2
+
+#define PMP_OFF   0x0
+#define PMP_TOR   0x08
+#define PMP_NA4   0x10
+#define PMP_NAPOT 0x18
+
+#define MSECCFG_MML  0x1
+#define MSECCFG_MMWP 0x2
+#define MSECCFG_RLB  0x4
+
+#define TEST_RW 1
+#define TEST_FETCH 1
+/*
+ * Whether rwx share single cfg for M mode
+ * When @set_sec_mml@ set, it must be 0, otherwise unexpected exception
+ */
+#define M_MODE_RWX 0
+
+#define CAUSE_LOAD_ACCESS 0x5
+#define CAUSE_STORE_ACCESS 0x7
+
+typedef unsigned long reg_t;
+typedef unsigned long uintptr_t;
+
+/*
+ * functions from syscalls.c
+ */
+#if PRINTF_SUPPORTED
+int printf(const char* fmt, ...);
+#else
+#define printf(...)
+#endif
+
+void __attribute__((noreturn)) tohost_exit(uintptr_t code);
+void exit(int code);
+
+/*
+ * local status
+ */
+#define TEST_MEM_START 0x80200000
+#define TEST_MEM_END 0x80240000
+#define U_MEM_END (TEST_MEM_END + 0x10000)
+#define FAKE_ADDRESS 0x10000000
+
+static const unsigned long expected_rw_fail = 1;
+static unsigned actual_rw_fail = 0;
+
+static const unsigned long expected_x_fail = 1;
+static unsigned actual_x_fail = 0;
+static void checkTestResult(void);
+
+/*
+ * override syscalls.c.
+ *  currently simply skip to nexp instruction
+ */
+uintptr_t handle_trap(uintptr_t cause, uintptr_t epc, uintptr_t regs[32])
+{
+    if (epc >= TEST_MEM_START && epc < TEST_MEM_END) {
+        asm volatile ("nop");
+        actual_x_fail = 1;
+        checkTestResult();
+    } else if (cause == CAUSE_LOAD_ACCESS || cause == CAUSE_STORE_ACCESS) {
+        reg_t addr;
+        asm volatile ("csrr %0, mtval\n" : "=r"(addr));
+        if (addr >= TEST_MEM_START && addr < TEST_MEM_END) {
+            actual_rw_fail = 1;
+            return epc + 4;
+        }
+        
+        if (addr == FAKE_ADDRESS) {
+            asm volatile ("nop");
+            asm volatile ("nop");
+            checkTestResult();
+        }
+    }
+    
+    tohost_exit(1337);
+}
+
+
+// switch (eret) to U mode and resume next PC
+static void switch_to_U() {
+    reg_t tmp;
+    asm volatile (
+            "li %0, %1\n"
+            "\tcsrc mstatus, t0\n"
+            "\tla %0, try_access_umode \n"
+            "\tcsrw mepc, %0\n"
+            "\tli sp, %2\n"
+            "\tmret\n"
+            : "=r"(tmp) : "n"(MSTATUS_MPP), "n"(U_MEM_END) : "memory");
+}
+
+static void switch_mode() {
+#if 1
+    switch_to_U();
+#endif
+}
+
+__attribute ((section(".text_test_foo"), noinline))
+static void target_foo() {
+    asm volatile ("nop");
+    
+    actual_x_fail = 0;
+}
+
+/*
+ * avoid to access actual_x_fail lies in M mode
+ */
+__attribute ((section(".text_test_foo"), noinline))
+static void target_foo_umode() {
+    asm volatile ("nop");
+}
+
+__attribute ((section(".data_test_arr"), aligned(8)))
+static volatile unsigned char target_arr[100] = {
+        1,2,3,4,5,6,7,8,
+};
+
+static int detect_pmp_granularity(){
+    unsigned int granule;
+    unsigned long int temp_reg;
+    unsigned long int all_ones = ~0x0UL;
+
+    asm volatile ("csrw pmpaddr0, %0 \n" :: "r"(all_ones) : "memory");
+    asm volatile ("csrr %0, pmpaddr0 \n" : "=r"(temp_reg));
+    asm volatile ("csrw pmpaddr0, %0 \n" :: "r"(0x0) : "memory");
+
+    int g = 2;
+    for(uintptr_t i = 1; i; i<<=1) {
+        if((temp_reg & i) != 0)
+            break;
+        g++;
+    }
+    granule = 1UL << g;
+
+    return granule;
+}
+
+static int mismatch_addr_offset(int granule_size){
+    unsigned int addr_offset = 0;
+
+    if (addr_offset == 0x0){
+        return 0x0;
+    }
+    else {
+        unsigned int mismatch_offset   = granule_size;
+        while (mismatch_offset < addr_offset){
+            mismatch_offset = mismatch_offset << 0x1;
+        }
+        return mismatch_offset;
+    }
+}
+
+/*
+ * On processor_t::reset():
+ *  - set_csr(CSR_PMPADDR0, ~reg_t(0));
+ *    set_csr(CSR_PMPCFG0, PMP_R | PMP_W | PMP_X | PMP_NAPOT);
+ */
+static void set_cfg() {
+#if 1
+    /*
+     * set MSECCFG_RLB to avoid locked
+     */
+    unsigned rlb_value = MSECCFG_RLB;
+    asm volatile ("csrs 0x747, %0 \n"::"r"(rlb_value));
+#endif
+    
+    /*
+     * Set pmp0cfg for M mode (M_MEM), and pmp1cfg for base of TOR.
+     * Then use pmp2cfg for TEST_MEM. Both test code and data share PMP entrance.
+     * Also use pmp3cfg for fixed U mode (U_MEM).
+     * 
+     * Here @pmp_addr_offset:int@ is to create an address mismatch
+     * And @create_pmp_cfg:int@ is to create cfg mismatch.
+     */
+
+    unsigned int mismatch_offset = 0;
+
+    if (mismatch_offset != 0x0){
+        volatile int pmp_granularity = detect_pmp_granularity();
+        mismatch_offset = mismatch_addr_offset(pmp_granularity);
+    }
+    asm volatile ("csrw pmpaddr7, %0 \n" :: "r"(0x8ffffff8 >> 2) : "memory");       // for ibex signature addr
+    asm volatile ("csrw pmpaddr3, %0 \n" :: "r"(U_MEM_END >> 2) : "memory");
+    asm volatile ("csrw pmpaddr2, %0 \n" :: "r"(TEST_MEM_END >> 2) : "memory");
+    asm volatile ("csrw pmpaddr1, %0 \n" :: "r"((TEST_MEM_START + mismatch_offset) >> 2) : "memory");
+    
+#if M_MODE_RWX
+    asm volatile ("csrw pmpaddr0, %0 \n" :: "r"((0x80000000 >> 2) | 0xfffff) : "memory");
+    reg_t cfg0 = (PMP_R | PMP_W | PMP_X | PMP_NAPOT);
+    reg_t cfg1 = (PMP_R | PMP_W | PMP_NAPOT) << 24;
+#else
+    asm volatile ("csrw pmpaddr6, %0 \n" :: "r"(TEST_MEM_START >> 2) : "memory");   // for data
+    asm volatile ("csrw pmpaddr5, %0 \n" :: "r"(0x80010000 >> 2) : "memory");       // for code
+    asm volatile ("csrw pmpaddr4, %0 \n" :: "r"(0x80000000 >> 2) : "memory");       // addr start
+    reg_t cfg0 = PMP_OFF;
+    reg_t cfg1 = PMP_OFF | ((PMP_R | PMP_W | PMP_NAPOT) << 24)
+                         | ((PMP_R | PMP_W | PMP_TOR) << 16) 
+                         | ((PMP_X | PMP_TOR) << 8);
+#endif
+    
+    // Only true for Spike
+//    asm volatile ("csrr %0, pmpcfg0\n":"=r"(cfg0)); 
+//    if (cfg0 != (PMP_R | PMP_W | PMP_X | PMP_NAPOT)) {
+//        exit(cfg0);
+//    }
+    
+    if (0) {    // need to set L bit for M mode code like trap_handling
+#if M_MODE_RWX
+        cfg0 |= PMP_L;
+        cfg1 |= (PMP_L << 24);
+#else
+        cfg1 |= ((PMP_L << 8) | (PMP_L << 16) | (PMP_L << 24));
+#endif
+    }
+    
+    cfg0 |= (PMP_R | PMP_W | PMP_X | PMP_TOR) << 24;    // for U_MEM
+#if 1
+    cfg0 |= ( (0 ? PMP_R : 0)
+            | (0 ? PMP_W : 0)
+            | (0 ? PMP_X : 0) 
+            | PMP_TOR | (1 ? PMP_L : 0)) << 16;
+#endif   
+    
+#if __riscv_xlen == 64
+    cfg0 |= (cfg1 << 32);
+#else
+    asm volatile ("csrw pmpcfg1, %0 \n"
+                :
+                : "r"(cfg1)
+                : "memory");
+#endif // __riscv_xlen == 64
+    
+    asm volatile ("csrw pmpcfg0, %0 \n"
+                :
+                : "r"(cfg0)
+                : "memory");
+    
+    // set proc->state.mseccfg, for MML/MMWP
+    const unsigned seccfg_bits = (0 ? MSECCFG_MML : 0) | (0 ? MSECCFG_MMWP : 0);
+    if (seccfg_bits) {
+        asm volatile ("csrs 0x747, %0 \n"::"r"(seccfg_bits));
+    }
+    
+    // currently dummy since tlb flushed when set_csr on mseccfg
+    asm volatile ("fence.i \n");
+}
+
+// from pmp_ok() side,W/R/X is similar
+__attribute ((noinline))
+static void try_access() {
+#if TEST_RW
+    target_arr[0] += 1;
+    const unsigned long delta = (unsigned long)0x1020304005060708ULL;
+    *(long *)target_arr += delta;
+
+    if (*(long *)target_arr != (unsigned long)0x0807060504030201ULL + delta + 1) {
+        actual_rw_fail = 1;
+    }
+#endif
+
+#if TEST_FETCH
+    actual_x_fail = 1;  // reset inside target_foo()
+    target_foo();
+#endif
+}
+
+// in case mml set, printf cannot be used in U mode
+__attribute ((section(".text_umode")))
+void try_access_umode() {
+#if TEST_RW
+    target_arr[0] += 1;
+//    const unsigned long delta = 0x1020304005060708UL;
+//    *(long *)target_arr += delta;
+
+//    if (*(long *)target_arr != 0x0807060504030201UL + delta + 1) {
+//        actual_rw_fail = 1;
+//    }
+#endif
+
+#if TEST_FETCH
+    target_foo_umode();
+#endif
+    
+    /*
+     * switch to M mode by invoking a write access fault for special address.
+     */
+    volatile unsigned char * p = (unsigned char *)(FAKE_ADDRESS);
+    *p = 1;
+}
+
+static void checkTestResult() {
+    int ret = 0;
+    if (expected_rw_fail != actual_rw_fail) {
+        ret += 1;
+    }
+
+    if (expected_x_fail != actual_x_fail) {
+        ret += 2;
+    }
+    
+    
+    exit(ret); 
+}
+
+int main() {
+    // assert in M mode
+    set_cfg();
+
+    switch_mode();  // in case swith to u mode, branch to try_access_umode directly
+
+    try_access();
+
+    checkTestResult();
+    return 0; // assert 0
+}
+

snapshots/lowRISC_ibex_pr2214/vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw10_x0_l1_match0_mmwp1_mml1.c

@@ -0,0 +1,346 @@
+
+/*
+ * outputs/test_pmp_ok_1_u1_rw10_x0_l1_match0_mmwp1_mml1.c
+ * Generated from gen_pmp_test.cc and test_pmp_ok_1.cc_skel.
+ * 
+ * This test program is expected to start executed from M mode.
+ * That will be easier for us to deal with pmp exception for test.
+ * 
+ * Remarks:
+ * - RW=01 not covered. U/M mode share will be tested separately
+ * - RLB is always 0. CSR access control will be tested separately
+ * 
+ * @changed 2020-Mar-2 soberl
+ *  For RWXL + MML, need to separate R and W combinations.
+ *  Skip RW=01 (share mode) at generator driver side.
+ */
+
+/*
+ * Macros from encoding.h
+ */
+#define MSTATUS_MPP         0x00001800
+
+#define PMP_R     0x01
+#define PMP_W     0x02
+#define PMP_X     0x04
+#define PMP_A     0x18
+#define PMP_L     0x80
+#define PMP_SHIFT 2
+
+#define PMP_OFF   0x0
+#define PMP_TOR   0x08
+#define PMP_NA4   0x10
+#define PMP_NAPOT 0x18
+
+#define MSECCFG_MML  0x1
+#define MSECCFG_MMWP 0x2
+#define MSECCFG_RLB  0x4
+
+#define TEST_RW 1
+#define TEST_FETCH 1
+/*
+ * Whether rwx share single cfg for M mode
+ * When @set_sec_mml@ set, it must be 0, otherwise unexpected exception
+ */
+#define M_MODE_RWX 0
+
+#define CAUSE_LOAD_ACCESS 0x5
+#define CAUSE_STORE_ACCESS 0x7
+
+typedef unsigned long reg_t;
+typedef unsigned long uintptr_t;
+
+/*
+ * functions from syscalls.c
+ */
+#if PRINTF_SUPPORTED
+int printf(const char* fmt, ...);
+#else
+#define printf(...)
+#endif
+
+void __attribute__((noreturn)) tohost_exit(uintptr_t code);
+void exit(int code);
+
+/*
+ * local status
+ */
+#define TEST_MEM_START 0x80200000
+#define TEST_MEM_END 0x80240000
+#define U_MEM_END (TEST_MEM_END + 0x10000)
+#define FAKE_ADDRESS 0x10000000
+
+static const unsigned long expected_rw_fail = 1;
+static unsigned actual_rw_fail = 0;
+
+static const unsigned long expected_x_fail = 1;
+static unsigned actual_x_fail = 0;
+static void checkTestResult(void);
+
+/*
+ * override syscalls.c.
+ *  currently simply skip to nexp instruction
+ */
+uintptr_t handle_trap(uintptr_t cause, uintptr_t epc, uintptr_t regs[32])
+{
+    if (epc >= TEST_MEM_START && epc < TEST_MEM_END) {
+        asm volatile ("nop");
+        actual_x_fail = 1;
+        checkTestResult();
+    } else if (cause == CAUSE_LOAD_ACCESS || cause == CAUSE_STORE_ACCESS) {
+        reg_t addr;
+        asm volatile ("csrr %0, mtval\n" : "=r"(addr));
+        if (addr >= TEST_MEM_START && addr < TEST_MEM_END) {
+            actual_rw_fail = 1;
+            return epc + 4;
+        }
+        
+        if (addr == FAKE_ADDRESS) {
+            asm volatile ("nop");
+            asm volatile ("nop");
+            checkTestResult();
+        }
+    }
+    
+    tohost_exit(1337);
+}
+
+
+// switch (eret) to U mode and resume next PC
+static void switch_to_U() {
+    reg_t tmp;
+    asm volatile (
+            "li %0, %1\n"
+            "\tcsrc mstatus, t0\n"
+            "\tla %0, try_access_umode \n"
+            "\tcsrw mepc, %0\n"
+            "\tli sp, %2\n"
+            "\tmret\n"
+            : "=r"(tmp) : "n"(MSTATUS_MPP), "n"(U_MEM_END) : "memory");
+}
+
+static void switch_mode() {
+#if 1
+    switch_to_U();
+#endif
+}
+
+__attribute ((section(".text_test_foo"), noinline))
+static void target_foo() {
+    asm volatile ("nop");
+    
+    actual_x_fail = 0;
+}
+
+/*
+ * avoid to access actual_x_fail lies in M mode
+ */
+__attribute ((section(".text_test_foo"), noinline))
+static void target_foo_umode() {
+    asm volatile ("nop");
+}
+
+__attribute ((section(".data_test_arr"), aligned(8)))
+static volatile unsigned char target_arr[100] = {
+        1,2,3,4,5,6,7,8,
+};
+
+static int detect_pmp_granularity(){
+    unsigned int granule;
+    unsigned long int temp_reg;
+    unsigned long int all_ones = ~0x0UL;
+
+    asm volatile ("csrw pmpaddr0, %0 \n" :: "r"(all_ones) : "memory");
+    asm volatile ("csrr %0, pmpaddr0 \n" : "=r"(temp_reg));
+    asm volatile ("csrw pmpaddr0, %0 \n" :: "r"(0x0) : "memory");
+
+    int g = 2;
+    for(uintptr_t i = 1; i; i<<=1) {
+        if((temp_reg & i) != 0)
+            break;
+        g++;
+    }
+    granule = 1UL << g;
+
+    return granule;
+}
+
+static int mismatch_addr_offset(int granule_size){
+    unsigned int addr_offset = 256;
+
+    if (addr_offset == 0x0){
+        return 0x0;
+    }
+    else {
+        unsigned int mismatch_offset   = granule_size;
+        while (mismatch_offset < addr_offset){
+            mismatch_offset = mismatch_offset << 0x1;
+        }
+        return mismatch_offset;
+    }
+}
+
+/*
+ * On processor_t::reset():
+ *  - set_csr(CSR_PMPADDR0, ~reg_t(0));
+ *    set_csr(CSR_PMPCFG0, PMP_R | PMP_W | PMP_X | PMP_NAPOT);
+ */
+static void set_cfg() {
+#if 1
+    /*
+     * set MSECCFG_RLB to avoid locked
+     */
+    unsigned rlb_value = MSECCFG_RLB;
+    asm volatile ("csrs 0x747, %0 \n"::"r"(rlb_value));
+#endif
+    
+    /*
+     * Set pmp0cfg for M mode (M_MEM), and pmp1cfg for base of TOR.
+     * Then use pmp2cfg for TEST_MEM. Both test code and data share PMP entrance.
+     * Also use pmp3cfg for fixed U mode (U_MEM).
+     * 
+     * Here @pmp_addr_offset:int@ is to create an address mismatch
+     * And @create_pmp_cfg:int@ is to create cfg mismatch.
+     */
+
+    unsigned int mismatch_offset = 256;
+
+    if (mismatch_offset != 0x0){
+        volatile int pmp_granularity = detect_pmp_granularity();
+        mismatch_offset = mismatch_addr_offset(pmp_granularity);
+    }
+    asm volatile ("csrw pmpaddr7, %0 \n" :: "r"(0x8ffffff8 >> 2) : "memory");       // for ibex signature addr
+    asm volatile ("csrw pmpaddr3, %0 \n" :: "r"(U_MEM_END >> 2) : "memory");
+    asm volatile ("csrw pmpaddr2, %0 \n" :: "r"(TEST_MEM_END >> 2) : "memory");
+    asm volatile ("csrw pmpaddr1, %0 \n" :: "r"((TEST_MEM_START + mismatch_offset) >> 2) : "memory");
+    
+#if M_MODE_RWX
+    asm volatile ("csrw pmpaddr0, %0 \n" :: "r"((0x80000000 >> 2) | 0xfffff) : "memory");
+    reg_t cfg0 = (PMP_R | PMP_W | PMP_X | PMP_NAPOT);
+    reg_t cfg1 = (PMP_R | PMP_W | PMP_NAPOT) << 24;
+#else
+    asm volatile ("csrw pmpaddr6, %0 \n" :: "r"(TEST_MEM_START >> 2) : "memory");   // for data
+    asm volatile ("csrw pmpaddr5, %0 \n" :: "r"(0x80010000 >> 2) : "memory");       // for code
+    asm volatile ("csrw pmpaddr4, %0 \n" :: "r"(0x80000000 >> 2) : "memory");       // addr start
+    reg_t cfg0 = PMP_OFF;
+    reg_t cfg1 = PMP_OFF | ((PMP_R | PMP_W | PMP_NAPOT) << 24)
+                         | ((PMP_R | PMP_W | PMP_TOR) << 16) 
+                         | ((PMP_X | PMP_TOR) << 8);
+#endif
+    
+    // Only true for Spike
+//    asm volatile ("csrr %0, pmpcfg0\n":"=r"(cfg0)); 
+//    if (cfg0 != (PMP_R | PMP_W | PMP_X | PMP_NAPOT)) {
+//        exit(cfg0);
+//    }
+    
+    if (1) {    // need to set L bit for M mode code like trap_handling
+#if M_MODE_RWX
+        cfg0 |= PMP_L;
+        cfg1 |= (PMP_L << 24);
+#else
+        cfg1 |= ((PMP_L << 8) | (PMP_L << 16) | (PMP_L << 24));
+#endif
+    }
+    
+    cfg0 |= (PMP_R | PMP_W | PMP_X | PMP_TOR) << 24;    // for U_MEM
+#if 0
+    cfg0 |= ( (1 ? PMP_R : 0)
+            | (0 ? PMP_W : 0)
+            | (0 ? PMP_X : 0) 
+            | PMP_TOR | (1 ? PMP_L : 0)) << 16;
+#endif   
+    
+#if __riscv_xlen == 64
+    cfg0 |= (cfg1 << 32);
+#else
+    asm volatile ("csrw pmpcfg1, %0 \n"
+                :
+                : "r"(cfg1)
+                : "memory");
+#endif // __riscv_xlen == 64
+    
+    asm volatile ("csrw pmpcfg0, %0 \n"
+                :
+                : "r"(cfg0)
+                : "memory");
+    
+    // set proc->state.mseccfg, for MML/MMWP
+    const unsigned seccfg_bits = (1 ? MSECCFG_MML : 0) | (1 ? MSECCFG_MMWP : 0);
+    if (seccfg_bits) {
+        asm volatile ("csrs 0x747, %0 \n"::"r"(seccfg_bits));
+    }
+    
+    // currently dummy since tlb flushed when set_csr on mseccfg
+    asm volatile ("fence.i \n");
+}
+
+// from pmp_ok() side,W/R/X is similar
+__attribute ((noinline))
+static void try_access() {
+#if TEST_RW
+    target_arr[0] += 1;
+    const unsigned long delta = (unsigned long)0x1020304005060708ULL;
+    *(long *)target_arr += delta;
+
+    if (*(long *)target_arr != (unsigned long)0x0807060504030201ULL + delta + 1) {
+        actual_rw_fail = 1;
+    }
+#endif
+
+#if TEST_FETCH
+    actual_x_fail = 1;  // reset inside target_foo()
+    target_foo();
+#endif
+}
+
+// in case mml set, printf cannot be used in U mode
+__attribute ((section(".text_umode")))
+void try_access_umode() {
+#if TEST_RW
+    target_arr[0] += 1;
+//    const unsigned long delta = 0x1020304005060708UL;
+//    *(long *)target_arr += delta;
+
+//    if (*(long *)target_arr != 0x0807060504030201UL + delta + 1) {
+//        actual_rw_fail = 1;
+//    }
+#endif
+
+#if TEST_FETCH
+    target_foo_umode();
+#endif
+    
+    /*
+     * switch to M mode by invoking a write access fault for special address.
+     */
+    volatile unsigned char * p = (unsigned char *)(FAKE_ADDRESS);
+    *p = 1;
+}
+
+static void checkTestResult() {
+    int ret = 0;
+    if (expected_rw_fail != actual_rw_fail) {
+        ret += 1;
+    }
+
+    if (expected_x_fail != actual_x_fail) {
+        ret += 2;
+    }
+    
+    
+    exit(ret); 
+}
+
+int main() {
+    // assert in M mode
+    set_cfg();
+
+    switch_mode();  // in case swith to u mode, branch to try_access_umode directly
+
+    try_access();
+
+    checkTestResult();
+    return 0; // assert 0
+}
+

snapshots/lowRISC_ibex_pr2214/vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw11_x0_l1_match1_mmwp1_mml1.c

@@ -0,0 +1,346 @@
+
+/*
+ * outputs/test_pmp_ok_1_u1_rw11_x0_l1_match1_mmwp1_mml1.c
+ * Generated from gen_pmp_test.cc and test_pmp_ok_1.cc_skel.
+ * 
+ * This test program is expected to start executed from M mode.
+ * That will be easier for us to deal with pmp exception for test.
+ * 
+ * Remarks:
+ * - RW=01 not covered. U/M mode share will be tested separately
+ * - RLB is always 0. CSR access control will be tested separately
+ * 
+ * @changed 2020-Mar-2 soberl
+ *  For RWXL + MML, need to separate R and W combinations.
+ *  Skip RW=01 (share mode) at generator driver side.
+ */
+
+/*
+ * Macros from encoding.h
+ */
+#define MSTATUS_MPP         0x00001800
+
+#define PMP_R     0x01
+#define PMP_W     0x02
+#define PMP_X     0x04
+#define PMP_A     0x18
+#define PMP_L     0x80
+#define PMP_SHIFT 2
+
+#define PMP_OFF   0x0
+#define PMP_TOR   0x08
+#define PMP_NA4   0x10
+#define PMP_NAPOT 0x18
+
+#define MSECCFG_MML  0x1
+#define MSECCFG_MMWP 0x2
+#define MSECCFG_RLB  0x4
+
+#define TEST_RW 1
+#define TEST_FETCH 1
+/*
+ * Whether rwx share single cfg for M mode
+ * When @set_sec_mml@ set, it must be 0, otherwise unexpected exception
+ */
+#define M_MODE_RWX 0
+
+#define CAUSE_LOAD_ACCESS 0x5
+#define CAUSE_STORE_ACCESS 0x7
+
+typedef unsigned long reg_t;
+typedef unsigned long uintptr_t;
+
+/*
+ * functions from syscalls.c
+ */
+#if PRINTF_SUPPORTED
+int printf(const char* fmt, ...);
+#else
+#define printf(...)
+#endif
+
+void __attribute__((noreturn)) tohost_exit(uintptr_t code);
+void exit(int code);
+
+/*
+ * local status
+ */
+#define TEST_MEM_START 0x80200000
+#define TEST_MEM_END 0x80240000
+#define U_MEM_END (TEST_MEM_END + 0x10000)
+#define FAKE_ADDRESS 0x10000000
+
+static const unsigned long expected_rw_fail = 1;
+static unsigned actual_rw_fail = 0;
+
+static const unsigned long expected_x_fail = 1;
+static unsigned actual_x_fail = 0;
+static void checkTestResult(void);
+
+/*
+ * override syscalls.c.
+ *  currently simply skip to nexp instruction
+ */
+uintptr_t handle_trap(uintptr_t cause, uintptr_t epc, uintptr_t regs[32])
+{
+    if (epc >= TEST_MEM_START && epc < TEST_MEM_END) {
+        asm volatile ("nop");
+        actual_x_fail = 1;
+        checkTestResult();
+    } else if (cause == CAUSE_LOAD_ACCESS || cause == CAUSE_STORE_ACCESS) {
+        reg_t addr;
+        asm volatile ("csrr %0, mtval\n" : "=r"(addr));
+        if (addr >= TEST_MEM_START && addr < TEST_MEM_END) {
+            actual_rw_fail = 1;
+            return epc + 4;
+        }
+        
+        if (addr == FAKE_ADDRESS) {
+            asm volatile ("nop");
+            asm volatile ("nop");
+            checkTestResult();
+        }
+    }
+    
+    tohost_exit(1337);
+}
+
+
+// switch (eret) to U mode and resume next PC
+static void switch_to_U() {
+    reg_t tmp;
+    asm volatile (
+            "li %0, %1\n"
+            "\tcsrc mstatus, t0\n"
+            "\tla %0, try_access_umode \n"
+            "\tcsrw mepc, %0\n"
+            "\tli sp, %2\n"
+            "\tmret\n"
+            : "=r"(tmp) : "n"(MSTATUS_MPP), "n"(U_MEM_END) : "memory");
+}
+
+static void switch_mode() {
+#if 1
+    switch_to_U();
+#endif
+}
+
+__attribute ((section(".text_test_foo"), noinline))
+static void target_foo() {
+    asm volatile ("nop");
+    
+    actual_x_fail = 0;
+}
+
+/*
+ * avoid to access actual_x_fail lies in M mode
+ */
+__attribute ((section(".text_test_foo"), noinline))
+static void target_foo_umode() {
+    asm volatile ("nop");
+}
+
+__attribute ((section(".data_test_arr"), aligned(8)))
+static volatile unsigned char target_arr[100] = {
+        1,2,3,4,5,6,7,8,
+};
+
+static int detect_pmp_granularity(){
+    unsigned int granule;
+    unsigned long int temp_reg;
+    unsigned long int all_ones = ~0x0UL;
+
+    asm volatile ("csrw pmpaddr0, %0 \n" :: "r"(all_ones) : "memory");
+    asm volatile ("csrr %0, pmpaddr0 \n" : "=r"(temp_reg));
+    asm volatile ("csrw pmpaddr0, %0 \n" :: "r"(0x0) : "memory");
+
+    int g = 2;
+    for(uintptr_t i = 1; i; i<<=1) {
+        if((temp_reg & i) != 0)
+            break;
+        g++;
+    }
+    granule = 1UL << g;
+
+    return granule;
+}
+
+static int mismatch_addr_offset(int granule_size){
+    unsigned int addr_offset = 0;
+
+    if (addr_offset == 0x0){
+        return 0x0;
+    }
+    else {
+        unsigned int mismatch_offset   = granule_size;
+        while (mismatch_offset < addr_offset){
+            mismatch_offset = mismatch_offset << 0x1;
+        }
+        return mismatch_offset;
+    }
+}
+
+/*
+ * On processor_t::reset():
+ *  - set_csr(CSR_PMPADDR0, ~reg_t(0));
+ *    set_csr(CSR_PMPCFG0, PMP_R | PMP_W | PMP_X | PMP_NAPOT);
+ */
+static void set_cfg() {
+#if 1
+    /*
+     * set MSECCFG_RLB to avoid locked
+     */
+    unsigned rlb_value = MSECCFG_RLB;
+    asm volatile ("csrs 0x747, %0 \n"::"r"(rlb_value));
+#endif
+    
+    /*
+     * Set pmp0cfg for M mode (M_MEM), and pmp1cfg for base of TOR.
+     * Then use pmp2cfg for TEST_MEM. Both test code and data share PMP entrance.
+     * Also use pmp3cfg for fixed U mode (U_MEM).
+     * 
+     * Here @pmp_addr_offset:int@ is to create an address mismatch
+     * And @create_pmp_cfg:int@ is to create cfg mismatch.
+     */
+
+    unsigned int mismatch_offset = 0;
+
+    if (mismatch_offset != 0x0){
+        volatile int pmp_granularity = detect_pmp_granularity();
+        mismatch_offset = mismatch_addr_offset(pmp_granularity);
+    }
+    asm volatile ("csrw pmpaddr7, %0 \n" :: "r"(0x8ffffff8 >> 2) : "memory");       // for ibex signature addr
+    asm volatile ("csrw pmpaddr3, %0 \n" :: "r"(U_MEM_END >> 2) : "memory");
+    asm volatile ("csrw pmpaddr2, %0 \n" :: "r"(TEST_MEM_END >> 2) : "memory");
+    asm volatile ("csrw pmpaddr1, %0 \n" :: "r"((TEST_MEM_START + mismatch_offset) >> 2) : "memory");
+    
+#if M_MODE_RWX
+    asm volatile ("csrw pmpaddr0, %0 \n" :: "r"((0x80000000 >> 2) | 0xfffff) : "memory");
+    reg_t cfg0 = (PMP_R | PMP_W | PMP_X | PMP_NAPOT);
+    reg_t cfg1 = (PMP_R | PMP_W | PMP_NAPOT) << 24;
+#else
+    asm volatile ("csrw pmpaddr6, %0 \n" :: "r"(TEST_MEM_START >> 2) : "memory");   // for data
+    asm volatile ("csrw pmpaddr5, %0 \n" :: "r"(0x80010000 >> 2) : "memory");       // for code
+    asm volatile ("csrw pmpaddr4, %0 \n" :: "r"(0x80000000 >> 2) : "memory");       // addr start
+    reg_t cfg0 = PMP_OFF;
+    reg_t cfg1 = PMP_OFF | ((PMP_R | PMP_W | PMP_NAPOT) << 24)
+                         | ((PMP_R | PMP_W | PMP_TOR) << 16) 
+                         | ((PMP_X | PMP_TOR) << 8);
+#endif
+    
+    // Only true for Spike
+//    asm volatile ("csrr %0, pmpcfg0\n":"=r"(cfg0)); 
+//    if (cfg0 != (PMP_R | PMP_W | PMP_X | PMP_NAPOT)) {
+//        exit(cfg0);
+//    }
+    
+    if (1) {    // need to set L bit for M mode code like trap_handling
+#if M_MODE_RWX
+        cfg0 |= PMP_L;
+        cfg1 |= (PMP_L << 24);
+#else
+        cfg1 |= ((PMP_L << 8) | (PMP_L << 16) | (PMP_L << 24));
+#endif
+    }
+    
+    cfg0 |= (PMP_R | PMP_W | PMP_X | PMP_TOR) << 24;    // for U_MEM
+#if 1
+    cfg0 |= ( (1 ? PMP_R : 0)
+            | (1 ? PMP_W : 0)
+            | (0 ? PMP_X : 0) 
+            | PMP_TOR | (1 ? PMP_L : 0)) << 16;
+#endif   
+    
+#if __riscv_xlen == 64
+    cfg0 |= (cfg1 << 32);
+#else
+    asm volatile ("csrw pmpcfg1, %0 \n"
+                :
+                : "r"(cfg1)
+                : "memory");
+#endif // __riscv_xlen == 64
+    
+    asm volatile ("csrw pmpcfg0, %0 \n"
+                :
+                : "r"(cfg0)
+                : "memory");
+    
+    // set proc->state.mseccfg, for MML/MMWP
+    const unsigned seccfg_bits = (1 ? MSECCFG_MML : 0) | (1 ? MSECCFG_MMWP : 0);
+    if (seccfg_bits) {
+        asm volatile ("csrs 0x747, %0 \n"::"r"(seccfg_bits));
+    }
+    
+    // currently dummy since tlb flushed when set_csr on mseccfg
+    asm volatile ("fence.i \n");
+}
+
+// from pmp_ok() side,W/R/X is similar
+__attribute ((noinline))
+static void try_access() {
+#if TEST_RW
+    target_arr[0] += 1;
+    const unsigned long delta = (unsigned long)0x1020304005060708ULL;
+    *(long *)target_arr += delta;
+
+    if (*(long *)target_arr != (unsigned long)0x0807060504030201ULL + delta + 1) {
+        actual_rw_fail = 1;
+    }
+#endif
+
+#if TEST_FETCH
+    actual_x_fail = 1;  // reset inside target_foo()
+    target_foo();
+#endif
+}
+
+// in case mml set, printf cannot be used in U mode
+__attribute ((section(".text_umode")))
+void try_access_umode() {
+#if TEST_RW
+    target_arr[0] += 1;
+//    const unsigned long delta = 0x1020304005060708UL;
+//    *(long *)target_arr += delta;
+
+//    if (*(long *)target_arr != 0x0807060504030201UL + delta + 1) {
+//        actual_rw_fail = 1;
+//    }
+#endif
+
+#if TEST_FETCH
+    target_foo_umode();
+#endif
+    
+    /*
+     * switch to M mode by invoking a write access fault for special address.
+     */
+    volatile unsigned char * p = (unsigned char *)(FAKE_ADDRESS);
+    *p = 1;
+}
+
+static void checkTestResult() {
+    int ret = 0;
+    if (expected_rw_fail != actual_rw_fail) {
+        ret += 1;
+    }
+
+    if (expected_x_fail != actual_x_fail) {
+        ret += 2;
+    }
+    
+    
+    exit(ret); 
+}
+
+int main() {
+    // assert in M mode
+    set_cfg();
+
+    switch_mode();  // in case swith to u mode, branch to try_access_umode directly
+
+    try_access();
+
+    checkTestResult();
+    return 0; // assert 0
+}
+

snapshots/lowRISC_ibex_pr2214/vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw11_x1_l0_match1_mmwp1_mml1.c

@@ -0,0 +1,346 @@
+
+/*
+ * outputs/test_pmp_ok_1_u1_rw11_x1_l0_match1_mmwp1_mml1.c
+ * Generated from gen_pmp_test.cc and test_pmp_ok_1.cc_skel.
+ * 
+ * This test program is expected to start executed from M mode.
+ * That will be easier for us to deal with pmp exception for test.
+ * 
+ * Remarks:
+ * - RW=01 not covered. U/M mode share will be tested separately
+ * - RLB is always 0. CSR access control will be tested separately
+ * 
+ * @changed 2020-Mar-2 soberl
+ *  For RWXL + MML, need to separate R and W combinations.
+ *  Skip RW=01 (share mode) at generator driver side.
+ */
+
+/*
+ * Macros from encoding.h
+ */
+#define MSTATUS_MPP         0x00001800
+
+#define PMP_R     0x01
+#define PMP_W     0x02
+#define PMP_X     0x04
+#define PMP_A     0x18
+#define PMP_L     0x80
+#define PMP_SHIFT 2
+
+#define PMP_OFF   0x0
+#define PMP_TOR   0x08
+#define PMP_NA4   0x10
+#define PMP_NAPOT 0x18
+
+#define MSECCFG_MML  0x1
+#define MSECCFG_MMWP 0x2
+#define MSECCFG_RLB  0x4
+
+#define TEST_RW 1
+#define TEST_FETCH 1
+/*
+ * Whether rwx share single cfg for M mode
+ * When @set_sec_mml@ set, it must be 0, otherwise unexpected exception
+ */
+#define M_MODE_RWX 0
+
+#define CAUSE_LOAD_ACCESS 0x5
+#define CAUSE_STORE_ACCESS 0x7
+
+typedef unsigned long reg_t;
+typedef unsigned long uintptr_t;
+
+/*
+ * functions from syscalls.c
+ */
+#if PRINTF_SUPPORTED
+int printf(const char* fmt, ...);
+#else
+#define printf(...)
+#endif
+
+void __attribute__((noreturn)) tohost_exit(uintptr_t code);
+void exit(int code);
+
+/*
+ * local status
+ */
+#define TEST_MEM_START 0x80200000
+#define TEST_MEM_END 0x80240000
+#define U_MEM_END (TEST_MEM_END + 0x10000)
+#define FAKE_ADDRESS 0x10000000
+
+static const unsigned long expected_rw_fail = 0;
+static unsigned actual_rw_fail = 0;
+
+static const unsigned long expected_x_fail = 0;
+static unsigned actual_x_fail = 0;
+static void checkTestResult(void);
+
+/*
+ * override syscalls.c.
+ *  currently simply skip to nexp instruction
+ */
+uintptr_t handle_trap(uintptr_t cause, uintptr_t epc, uintptr_t regs[32])
+{
+    if (epc >= TEST_MEM_START && epc < TEST_MEM_END) {
+        asm volatile ("nop");
+        actual_x_fail = 1;
+        checkTestResult();
+    } else if (cause == CAUSE_LOAD_ACCESS || cause == CAUSE_STORE_ACCESS) {
+        reg_t addr;
+        asm volatile ("csrr %0, mtval\n" : "=r"(addr));
+        if (addr >= TEST_MEM_START && addr < TEST_MEM_END) {
+            actual_rw_fail = 1;
+            return epc + 4;
+        }
+        
+        if (addr == FAKE_ADDRESS) {
+            asm volatile ("nop");
+            asm volatile ("nop");
+            checkTestResult();
+        }
+    }
+    
+    tohost_exit(1337);
+}
+
+
+// switch (eret) to U mode and resume next PC
+static void switch_to_U() {
+    reg_t tmp;
+    asm volatile (
+            "li %0, %1\n"
+            "\tcsrc mstatus, t0\n"
+            "\tla %0, try_access_umode \n"
+            "\tcsrw mepc, %0\n"
+            "\tli sp, %2\n"
+            "\tmret\n"
+            : "=r"(tmp) : "n"(MSTATUS_MPP), "n"(U_MEM_END) : "memory");
+}
+
+static void switch_mode() {
+#if 1
+    switch_to_U();
+#endif
+}
+
+__attribute ((section(".text_test_foo"), noinline))
+static void target_foo() {
+    asm volatile ("nop");
+    
+    actual_x_fail = 0;
+}
+
+/*
+ * avoid to access actual_x_fail lies in M mode
+ */
+__attribute ((section(".text_test_foo"), noinline))
+static void target_foo_umode() {
+    asm volatile ("nop");
+}
+
+__attribute ((section(".data_test_arr"), aligned(8)))
+static volatile unsigned char target_arr[100] = {
+        1,2,3,4,5,6,7,8,
+};
+
+static int detect_pmp_granularity(){
+    unsigned int granule;
+    unsigned long int temp_reg;
+    unsigned long int all_ones = ~0x0UL;
+
+    asm volatile ("csrw pmpaddr0, %0 \n" :: "r"(all_ones) : "memory");
+    asm volatile ("csrr %0, pmpaddr0 \n" : "=r"(temp_reg));
+    asm volatile ("csrw pmpaddr0, %0 \n" :: "r"(0x0) : "memory");
+
+    int g = 2;
+    for(uintptr_t i = 1; i; i<<=1) {
+        if((temp_reg & i) != 0)
+            break;
+        g++;
+    }
+    granule = 1UL << g;
+
+    return granule;
+}
+
+static int mismatch_addr_offset(int granule_size){
+    unsigned int addr_offset = 0;
+
+    if (addr_offset == 0x0){
+        return 0x0;
+    }
+    else {
+        unsigned int mismatch_offset   = granule_size;
+        while (mismatch_offset < addr_offset){
+            mismatch_offset = mismatch_offset << 0x1;
+        }
+        return mismatch_offset;
+    }
+}
+
+/*
+ * On processor_t::reset():
+ *  - set_csr(CSR_PMPADDR0, ~reg_t(0));
+ *    set_csr(CSR_PMPCFG0, PMP_R | PMP_W | PMP_X | PMP_NAPOT);
+ */
+static void set_cfg() {
+#if 1
+    /*
+     * set MSECCFG_RLB to avoid locked
+     */
+    unsigned rlb_value = MSECCFG_RLB;
+    asm volatile ("csrs 0x747, %0 \n"::"r"(rlb_value));
+#endif
+    
+    /*
+     * Set pmp0cfg for M mode (M_MEM), and pmp1cfg for base of TOR.
+     * Then use pmp2cfg for TEST_MEM. Both test code and data share PMP entrance.
+     * Also use pmp3cfg for fixed U mode (U_MEM).
+     * 
+     * Here @pmp_addr_offset:int@ is to create an address mismatch
+     * And @create_pmp_cfg:int@ is to create cfg mismatch.
+     */
+
+    unsigned int mismatch_offset = 0;
+
+    if (mismatch_offset != 0x0){
+        volatile int pmp_granularity = detect_pmp_granularity();
+        mismatch_offset = mismatch_addr_offset(pmp_granularity);
+    }
+    asm volatile ("csrw pmpaddr7, %0 \n" :: "r"(0x8ffffff8 >> 2) : "memory");       // for ibex signature addr
+    asm volatile ("csrw pmpaddr3, %0 \n" :: "r"(U_MEM_END >> 2) : "memory");
+    asm volatile ("csrw pmpaddr2, %0 \n" :: "r"(TEST_MEM_END >> 2) : "memory");
+    asm volatile ("csrw pmpaddr1, %0 \n" :: "r"((TEST_MEM_START + mismatch_offset) >> 2) : "memory");
+    
+#if M_MODE_RWX
+    asm volatile ("csrw pmpaddr0, %0 \n" :: "r"((0x80000000 >> 2) | 0xfffff) : "memory");
+    reg_t cfg0 = (PMP_R | PMP_W | PMP_X | PMP_NAPOT);
+    reg_t cfg1 = (PMP_R | PMP_W | PMP_NAPOT) << 24;
+#else
+    asm volatile ("csrw pmpaddr6, %0 \n" :: "r"(TEST_MEM_START >> 2) : "memory");   // for data
+    asm volatile ("csrw pmpaddr5, %0 \n" :: "r"(0x80010000 >> 2) : "memory");       // for code
+    asm volatile ("csrw pmpaddr4, %0 \n" :: "r"(0x80000000 >> 2) : "memory");       // addr start
+    reg_t cfg0 = PMP_OFF;
+    reg_t cfg1 = PMP_OFF | ((PMP_R | PMP_W | PMP_NAPOT) << 24)
+                         | ((PMP_R | PMP_W | PMP_TOR) << 16) 
+                         | ((PMP_X | PMP_TOR) << 8);
+#endif
+    
+    // Only true for Spike
+//    asm volatile ("csrr %0, pmpcfg0\n":"=r"(cfg0)); 
+//    if (cfg0 != (PMP_R | PMP_W | PMP_X | PMP_NAPOT)) {
+//        exit(cfg0);
+//    }
+    
+    if (1) {    // need to set L bit for M mode code like trap_handling
+#if M_MODE_RWX
+        cfg0 |= PMP_L;
+        cfg1 |= (PMP_L << 24);
+#else
+        cfg1 |= ((PMP_L << 8) | (PMP_L << 16) | (PMP_L << 24));
+#endif
+    }
+    
+    cfg0 |= (PMP_R | PMP_W | PMP_X | PMP_TOR) << 24;    // for U_MEM
+#if 1
+    cfg0 |= ( (1 ? PMP_R : 0)
+            | (1 ? PMP_W : 0)
+            | (1 ? PMP_X : 0) 
+            | PMP_TOR | (0 ? PMP_L : 0)) << 16;
+#endif   
+    
+#if __riscv_xlen == 64
+    cfg0 |= (cfg1 << 32);
+#else
+    asm volatile ("csrw pmpcfg1, %0 \n"
+                :
+                : "r"(cfg1)
+                : "memory");
+#endif // __riscv_xlen == 64
+    
+    asm volatile ("csrw pmpcfg0, %0 \n"
+                :
+                : "r"(cfg0)
+                : "memory");
+    
+    // set proc->state.mseccfg, for MML/MMWP
+    const unsigned seccfg_bits = (1 ? MSECCFG_MML : 0) | (1 ? MSECCFG_MMWP : 0);
+    if (seccfg_bits) {
+        asm volatile ("csrs 0x747, %0 \n"::"r"(seccfg_bits));
+    }
+    
+    // currently dummy since tlb flushed when set_csr on mseccfg
+    asm volatile ("fence.i \n");
+}
+
+// from pmp_ok() side,W/R/X is similar
+__attribute ((noinline))
+static void try_access() {
+#if TEST_RW
+    target_arr[0] += 1;
+    const unsigned long delta = (unsigned long)0x1020304005060708ULL;
+    *(long *)target_arr += delta;
+
+    if (*(long *)target_arr != (unsigned long)0x0807060504030201ULL + delta + 1) {
+        actual_rw_fail = 1;
+    }
+#endif
+
+#if TEST_FETCH
+    actual_x_fail = 1;  // reset inside target_foo()
+    target_foo();
+#endif
+}
+
+// in case mml set, printf cannot be used in U mode
+__attribute ((section(".text_umode")))
+void try_access_umode() {
+#if TEST_RW
+    target_arr[0] += 1;
+//    const unsigned long delta = 0x1020304005060708UL;
+//    *(long *)target_arr += delta;
+
+//    if (*(long *)target_arr != 0x0807060504030201UL + delta + 1) {
+//        actual_rw_fail = 1;
+//    }
+#endif
+
+#if TEST_FETCH
+    target_foo_umode();
+#endif
+    
+    /*
+     * switch to M mode by invoking a write access fault for special address.
+     */
+    volatile unsigned char * p = (unsigned char *)(FAKE_ADDRESS);
+    *p = 1;
+}
+
+static void checkTestResult() {
+    int ret = 0;
+    if (expected_rw_fail != actual_rw_fail) {
+        ret += 1;
+    }
+
+    if (expected_x_fail != actual_x_fail) {
+        ret += 2;
+    }
+    
+    
+    exit(ret); 
+}
+
+int main() {
+    // assert in M mode
+    set_cfg();
+
+    switch_mode();  // in case swith to u mode, branch to try_access_umode directly
+
+    try_access();
+
+    checkTestResult();
+    return 0; // assert 0
+}
+

snapshots/lowRISC_ibex_pr2214/vendor/riscv-tests/debug/targets/RISC-V/spike-1.cfg

@@ -0,0 +1,33 @@
+adapter_khz     10000
+
+interface remote_bitbang
+remote_bitbang_host $::env(REMOTE_BITBANG_HOST)
+remote_bitbang_port $::env(REMOTE_BITBANG_PORT)
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+
+set _TARGETNAME $_CHIPNAME.cpu
+if {$::env(USE_FREERTOS)} {
+    target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos FreeRTOS
+} else {
+    target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+}
+$_TARGETNAME configure -work-area-phys $::env(WORK_AREA) -work-area-size 8096 -work-area-backup 1
+
+gdb_report_data_abort enable
+gdb_report_register_access_error enable
+
+# Expose an unimplemented CSR so we can test non-existent register access
+# behavior.
+riscv expose_csrs 2288
+riscv expose_custom 1,12345-12348
+
+init
+
+set challenge [riscv authdata_read]
+riscv authdata_write [expr $challenge + 1]
+
+halt
+
+arm semihosting enable

snapshots/lowRISC_ibex_pr2214/vendor/riscv-tests/debug/targets/RISC-V/spike64-2-rtos.py

@@ -0,0 +1,19 @@
+import spike64  # pylint: disable=import-error
+
+import targets
+import testlib
+
+class spike64_2_rtos(targets.Target):
+    harts = [spike64.spike64_hart(misa=0x8000000000141129),
+            spike64.spike64_hart(misa=0x8000000000141129)]
+    openocd_config_path = "spike-rtos.cfg"
+    timeout_sec = 60
+    implements_custom_test = True
+    support_hasel = False
+    test_semihosting = False
+    support_manual_hwbp = False # not supported with `-rtos riscv`
+    support_memory_sampling = False # not supported with `-rtos riscv`
+
+    def create(self):
+        return testlib.Spike(self, abstract_rti=30, support_hasel=False,
+                support_abstract_csr=False)

snapshots/lowRISC_ibex_pr2214/vendor/riscv-tests/debug/targets/RISC-V/spike64.lds

@@ -0,0 +1,36 @@
+OUTPUT_ARCH( "riscv" )
+
+SECTIONS
+{
+  . = 0x1212340000;
+  .text : 
+  {
+    *(.text.entry)
+    *(.text)
+  }
+
+  /* data segment */
+  .data : { *(.data) }
+
+  .sdata : {
+    __global_pointer$ = . + 0x800;
+    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
+    *(.srodata*)
+    *(.sdata .sdata.* .gnu.linkonce.s.*)
+  }
+
+  /* bss segment */
+  __bss_start = .;
+  .sbss : {
+    *(.sbss .sbss.* .gnu.linkonce.sb.*)
+    *(.scommon)
+  }
+  .bss : { *(.bss) }
+  __bss_end = .;
+
+  __malloc_start = .;
+  . = . + 512;
+
+  /* End of uninitalized data segement */
+  _end = .;
+}

snapshots/lowRISC_ibex_pr2214/vendor/riscv-tests/debug/targets/RISC-V/spike64.py

@@ -0,0 +1,25 @@
+import targets
+import testlib
+
+class spike64_hart(targets.Hart):
+    xlen = 64
+    ram = 0x1212340000
+    ram_size = 0x10000000
+    bad_address = ram - 8
+    instruction_hardware_breakpoint_count = 4
+    reset_vectors = [0x1000]
+    link_script_path = "spike64.lds"
+    misa = 0x8000000000141125
+
+class spike64(targets.Target):
+    harts = [spike64_hart()]
+    openocd_config_path = "spike-1.cfg"
+    timeout_sec = 30
+    implements_custom_test = True
+    freertos_binary = "bin/RTOSDemo64.axf"
+
+    def create(self):
+        # 32-bit FPRs only
+        return testlib.Spike(self, isa="RV64IMAFC", progbufsize=0,
+                abstract_rti=30, support_abstract_csr=True,
+                support_abstract_fpr=True)