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snapshots/bespoke-silicon-group_basejump_stl_pr706/bsg_noc/bsg_mesh_router.sv

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+/**
+ *    bsg_mesh_router.sv
+ *
+ *
+ *    dims_p      network
+ *    ------------------------
+ *      1         1-D mesh
+ *      2         2-D mesh
+ *      3         2-D mesh + half ruche x
+ *      4         2-D mesh + full ruche
+ *
+ *      ruche_factor_X/Y_p determines the number of hops that ruche links extend in the direction.
+ *
+ *      Currently only tested for
+ *      - 2-D mesh
+ *      - 2-D mesh + half ruche x
+ *
+ *   In theory, we could drop data bits (e.g. the X coordinate) as we switch to different dimensions, but the code would be a little complicated.
+ */  
+
+`include "bsg_defines.sv"
+
+
+module bsg_mesh_router
+  import bsg_noc_pkg::*;
+  import bsg_mesh_router_pkg::*;
+  #(parameter `BSG_INV_PARAM(width_p )
+    , parameter `BSG_INV_PARAM(x_cord_width_p )
+    , parameter `BSG_INV_PARAM(y_cord_width_p )
+    , parameter ruche_factor_X_p = 0
+    , parameter ruche_factor_Y_p = 0
+    , parameter dims_p = 2
+    , parameter dirs_lp = (2*dims_p)+1
+    , parameter XY_order_p = 1
+    , parameter depopulated_p = 1
+    , parameter bit [dirs_lp-1:0][dirs_lp-1:0]  routing_matrix_p = 
+      (dims_p == 2) ? (XY_order_p ? StrictXY : StrictYX) : (
+      (dims_p == 3) ? (depopulated_p ? (XY_order_p ? HalfRucheX_StrictXY : HalfRucheX_StrictYX) 
+                                     : (XY_order_p ? HalfRucheX_FullyPopulated_StrictXY : HalfRucheX_FullyPopulated_StrictYX)) : (
+      (dims_p == 4) ? (depopulated_p ? (XY_order_p ? FullRuche_StrictXY : FullRuche_StrictYX)
+                                     : (XY_order_p ? FullRuche_FullyPopulated_StrictXY : FullRuche_FullyPopulated_StrictYX))
+                    : "inv"))
+
+    , parameter debug_p = 0
+  )
+  (
+    input clk_i
+    , input reset_i
+
+    , input [dirs_lp-1:0][width_p-1:0] data_i
+    , input [dirs_lp-1:0]              v_i
+    , output logic [dirs_lp-1:0]       yumi_o
+
+    , input   [dirs_lp-1:0]               ready_and_i
+    , output  [dirs_lp-1:0][width_p-1:0]  data_o
+    , output logic [dirs_lp-1:0]          v_o
+
+    // node's x and y coord
+    , input   [x_cord_width_p-1:0] my_x_i           
+    , input   [y_cord_width_p-1:0] my_y_i
+  );
+
+
+  // input x,y coords
+  logic [dirs_lp-1:0][x_cord_width_p-1:0] x_dirs;
+  logic [dirs_lp-1:0][y_cord_width_p-1:0] y_dirs;
+
+  for (genvar i = 0; i < dirs_lp; i++) begin
+    assign x_dirs[i] = data_i[i][0+:x_cord_width_p];
+    assign y_dirs[i] = data_i[i][x_cord_width_p+:y_cord_width_p];
+  end
+
+
+  // dimension-ordered routing logic
+  logic [dirs_lp-1:0][dirs_lp-1:0] req, req_t;
+
+  for (genvar i = 0; i < dirs_lp; i++) begin: dor
+    logic [dirs_lp-1:0] temp_req;
+
+    bsg_mesh_router_decoder_dor #(
+      .x_cord_width_p(x_cord_width_p)
+      ,.y_cord_width_p(y_cord_width_p)
+      ,.ruche_factor_X_p(ruche_factor_X_p)
+      ,.ruche_factor_Y_p(ruche_factor_Y_p)
+      ,.dims_p(dims_p)
+      ,.XY_order_p(XY_order_p)
+      ,.from_p((dirs_lp)'(1 << i))
+      ,.depopulated_p(depopulated_p)
+      ,.debug_p(debug_p)
+    ) dor_decoder (
+      .clk_i(clk_i)
+      ,.reset_i(reset_i)
+      ,.x_dirs_i(x_dirs[i])
+      ,.y_dirs_i(y_dirs[i])
+      ,.my_x_i(my_x_i)
+      ,.my_y_i(my_y_i)
+
+      ,.req_o(temp_req)
+    );
+    
+    assign req[i] = {dirs_lp{v_i[i]}} & temp_req;
+  end
+
+  bsg_transpose #(
+    .width_p(dirs_lp)
+    ,.els_p(dirs_lp) 
+  ) req_tp (
+    .i(req)
+    ,.o(req_t)
+  );
+
+
+
+  // Instantiate crossbars for each output direction
+  logic [dirs_lp-1:0][dirs_lp-1:0] yumi_lo, yumi_lo_t;
+
+  for (genvar i = 0; i < dirs_lp; i++) begin: xbar
+
+    localparam input_els_lp = `BSG_COUNTONES_SYNTH(routing_matrix_p[i]);
+
+    logic [input_els_lp-1:0][width_p-1:0] conc_data;
+    logic [input_els_lp-1:0] conc_req;
+    logic [input_els_lp-1:0] grants;
+    
+    bsg_array_concentrate_static #(
+      .pattern_els_p(routing_matrix_p[i])
+      ,.width_p(width_p)
+    ) conc0 (
+      .i(data_i)
+      ,.o(conc_data)
+    );
+
+    bsg_concentrate_static #(
+      .pattern_els_p(routing_matrix_p[i])
+    ) conc1 (
+      .i(req_t[i])
+      ,.o(conc_req)
+    );
+
+    assign v_o[i] = |conc_req;
+
+    bsg_arb_round_robin #(
+      .width_p(input_els_lp)
+    ) rr (
+      .clk_i(clk_i)
+      ,.reset_i(reset_i)
+
+      ,.reqs_i(conc_req)
+      ,.grants_o(grants)
+      ,.yumi_i(v_o[i] & ready_and_i[i])
+    );
+
+    bsg_mux_one_hot #(
+      .els_p(input_els_lp)
+      ,.width_p(width_p)
+    ) data_mux (
+      .data_i(conc_data)
+      ,.sel_one_hot_i(grants)
+      ,.data_o(data_o[i])
+    );
+
+    bsg_unconcentrate_static #(
+      .pattern_els_p(routing_matrix_p[i])
+      ,.unconnected_val_p(1'b0)
+    ) unconc0 (
+      .i(grants & {input_els_lp{ready_and_i[i]}})
+      ,.o(yumi_lo[i])
+    );
+
+  end
+
+
+  bsg_transpose #(
+    .width_p(dirs_lp)
+    ,.els_p(dirs_lp) 
+  ) yumi_tp (
+    .i(yumi_lo)
+    ,.o(yumi_lo_t)
+  );
+
+
+  for (genvar i = 0; i < dirs_lp; i++) begin
+    assign yumi_o[i] = |yumi_lo_t[i];
+  end
+
+
+
+`ifndef BSG_HIDE_FROM_SYNTHESIS
+  if (debug_p) begin
+    always_ff @ (negedge clk_i) begin
+
+      if (~reset_i) begin
+        for (integer i = 0; i < dirs_lp; i++) begin
+          assert($countones(yumi_lo_t[i]) < 2)
+            else $error("multiple yumi detected. i=%d, %b", i, yumi_lo_t[i]);
+        end
+      end
+ 
+    end
+  end
+`endif
+
+
+
+
+
+
+
+endmodule
+
+`BSG_ABSTRACT_MODULE(bsg_mesh_router)

snapshots/bespoke-silicon-group_basejump_stl_pr706/bsg_noc/bsg_mesh_router_buffered.sv

@@ -0,0 +1,201 @@
+/**
+ *    bsg_mesh_router_buffered.sv
+ *
+ */
+
+
+`include "bsg_defines.sv"
+`include "bsg_noc_links.svh"
+
+
+module bsg_mesh_router_buffered
+  import bsg_mesh_router_pkg::*;
+  #(parameter `BSG_INV_PARAM(width_p        )
+    , parameter `BSG_INV_PARAM(x_cord_width_p )
+    , parameter `BSG_INV_PARAM(y_cord_width_p )
+    , parameter debug_p       = 0
+    , parameter ruche_factor_X_p = 0
+    , parameter ruche_factor_Y_p = 0
+    , parameter dims_p        = 2
+    , parameter dirs_lp       = (2*dims_p)+1
+    , parameter stub_p        = { dirs_lp {1'b0}}  // SNEWP
+    , parameter XY_order_p    = 1
+    , parameter depopulated_p = 1
+    , parameter bsg_ready_and_link_sif_width_lp=`bsg_ready_and_link_sif_width(width_p)
+    // select whether to buffer the output
+    , parameter repeater_output_p = { dirs_lp {1'b0}}  // SNEWP
+    // credit interface
+    , parameter use_credits_p = {dirs_lp{1'b0}}
+    , parameter int fifo_els_p[dirs_lp-1:0] = '{2,2,2,2,2}
+  )
+  (
+    input clk_i
+    , input reset_i
+
+    , input  [dirs_lp-1:0][bsg_ready_and_link_sif_width_lp-1:0] link_i
+    , output [dirs_lp-1:0][bsg_ready_and_link_sif_width_lp-1:0] link_o
+
+    , input [x_cord_width_p-1:0] my_x_i
+    , input [y_cord_width_p-1:0] my_y_i
+  );
+
+   `declare_bsg_ready_and_link_sif_s(width_p,bsg_ready_and_link_sif_s);
+
+   bsg_ready_and_link_sif_s [dirs_lp-1:0] link_i_cast, link_o_cast;
+
+   assign link_i_cast =link_i;
+   assign link_o = link_o_cast;
+
+   logic [dirs_lp-1:0]              fifo_valid;
+   logic [dirs_lp-1:0][width_p-1:0] fifo_data;
+   logic [dirs_lp-1:0]              fifo_yumi;
+
+   genvar                           i;
+
+`ifndef BSG_HIDE_FROM_SYNTHESIS
+   if (debug_p)
+     for (i = 0; i < dirs_lp;i=i+1)
+       begin
+          always_ff @(negedge clk_i)
+            $display("%m x=%d y=%d SNEWP[%d] v_i=%b ready_o=%b v_o=%b ready_i=%b %b"
+                     ,my_x_i,my_y_i,i,link_i_cast[i].v,link_o_cast[i].ready_and_rev,
+                     link_o_cast[i].v,link_i_cast[i].ready_and_rev,link_i[i]);
+       end
+`endif
+
+  for (i = 0; i < dirs_lp; i=i+1) begin: rof
+    if (stub_p[i]) begin: fi
+      assign fifo_data   [i] = width_p ' (0);
+      assign fifo_valid  [i] = 1'b0;
+
+      // accept no data from outside of stubbed port
+      assign link_o_cast[i].ready_and_rev = 1'b0;
+
+`ifndef BSG_HIDE_FROM_SYNTHESIS
+      always @(negedge clk_i)
+        assert (reset_i !== '0 || ~link_o_cast[i].v) else
+          $warning("## stubbed port %x received word %x",i,link_i_cast[i].data);
+`endif
+    end
+    else begin: fi
+      logic fifo_ready_lo;
+
+      bsg_fifo_1r1w_small #(
+        .width_p(width_p)
+        ,.els_p(fifo_els_p[i])
+      ) fifo (
+        .clk_i(clk_i)
+        ,.reset_i(reset_i)
+
+        ,.v_i     (link_i_cast[i].v            )
+        ,.data_i  (link_i_cast[i].data         )
+        ,.ready_param_o (fifo_ready_lo)
+
+        ,.v_o     (fifo_valid[i])
+        ,.data_o  (fifo_data [i])
+        ,.yumi_i  (fifo_yumi [i])
+      );
+      
+      if (use_credits_p[i]) begin: cr
+        bsg_dff_reset #(
+          .width_p(1)
+          ,.reset_val_p(0)
+        ) dff0 (
+          .clk_i(clk_i)
+          ,.reset_i(reset_i)
+          ,.data_i(fifo_yumi[i])
+          ,.data_o(link_o_cast[i].ready_and_rev)
+        );
+        
+`ifndef BSG_HIDE_FROM_SYNTHESIS
+        always_ff @ (negedge clk_i) begin
+          if (~reset_i) begin
+            if (link_i_cast[i].v) begin
+              assert(fifo_ready_lo)
+                else $error("Trying to enque when there is no space in FIFO, while using credit interface. i =%d", i);
+            end
+          end
+        end
+`endif
+
+      end
+      else begin
+        assign link_o_cast[i].ready_and_rev = fifo_ready_lo;      
+      end
+
+    end
+  end
+
+   // router does not have symmetric interfaces;
+   // so we do not use bsg_ready_and_link_sif
+   // and manually convert. support for arrays
+   // of interfaces in systemverilog would
+   // fix this.
+
+   logic [dirs_lp-1:0]              valid_lo;
+   logic [dirs_lp-1:0][width_p-1:0] data_lo;
+   logic [dirs_lp-1:0]              ready_li;
+
+   for (i = 0; i < dirs_lp; i=i+1)
+     begin: rof2
+        assign link_o_cast[i].v    = valid_lo[i];
+
+        if (repeater_output_p[i] & ~stub_p[i])
+          begin : macro
+	     wire [width_p-1:0] tmp;
+
+`ifndef BSG_HIDE_FROM_SYNTHESIS
+            initial
+               begin
+                  $display("%m with buffers on %d",i);
+               end
+`endif
+             bsg_inv #(.width_p(width_p),.vertical_p(i < 3)) data_lo_inv
+               (.i (data_lo[i]         )
+                ,.o(tmp)
+                );
+
+             bsg_inv #(.width_p(width_p),.vertical_p(i < 3)) data_lo_rep
+               (.i (tmp)
+                ,.o(link_o_cast[i].data)
+                );
+
+          end
+        else
+          assign link_o_cast[i].data = data_lo [i];
+
+        assign ready_li[i] = link_i_cast[i].ready_and_rev;
+     end
+
+   bsg_mesh_router #( .width_p      (width_p      )
+                      ,.x_cord_width_p(x_cord_width_p)
+                      ,.y_cord_width_p(y_cord_width_p)
+                      ,.ruche_factor_X_p(ruche_factor_X_p)
+                      ,.ruche_factor_Y_p(ruche_factor_Y_p)
+                      ,.dims_p        (dims_p)
+                      ,.XY_order_p   (XY_order_p   )
+                      ,.depopulated_p  (depopulated_p   )
+                      ) bmr
+   (.clk_i
+    ,.reset_i
+    ,.v_i    (fifo_valid)
+    ,.data_i (fifo_data )
+    ,.yumi_o (fifo_yumi )
+
+    ,.v_o   (valid_lo)
+    ,.data_o(data_lo)
+
+    // this will be hardwired to 1 by inside of this module
+    // if port is stubbed
+
+    ,.ready_and_i(ready_li)
+
+    ,.my_x_i
+    ,.my_y_i
+    );
+
+
+endmodule
+
+`BSG_ABSTRACT_MODULE(bsg_mesh_router_buffered)
+

snapshots/bespoke-silicon-group_basejump_stl_pr706/bsg_noc/bsg_mesh_router_decoder_dor.sv

@@ -0,0 +1,291 @@
+/**
+ *    bsg_mesh_router_decoder_dor.sv
+ *
+ *    Dimension ordered routing decoder
+ *    
+ *    depopulated ruche router.
+ */
+
+`include "bsg_defines.sv"
+
+module bsg_mesh_router_decoder_dor
+  import bsg_noc_pkg::*;
+  import bsg_mesh_router_pkg::*;
+  #(parameter `BSG_INV_PARAM(x_cord_width_p )
+    , parameter `BSG_INV_PARAM(y_cord_width_p )
+    , parameter dims_p = 2
+    , parameter dirs_lp = (2*dims_p)+1
+    , parameter ruche_factor_X_p=0
+    , parameter ruche_factor_Y_p=0
+    // XY_order_p = 1 :  X then Y
+    // XY_order_p = 0 :  Y then X
+    , parameter XY_order_p = 1
+    , parameter depopulated_p = 1
+    , parameter from_p = {dirs_lp{1'b0}}  // one-hot, indicates which direction is the input coming from.
+
+    , parameter debug_p = 1
+  )
+  (
+    input clk_i         // debug only
+    , input reset_i     // debug only
+
+    //, input v_i
+
+    , input [x_cord_width_p-1:0] x_dirs_i
+    , input [y_cord_width_p-1:0] y_dirs_i
+
+    , input [x_cord_width_p-1:0] my_x_i
+    , input [y_cord_width_p-1:0] my_y_i
+
+    , output [dirs_lp-1:0] req_o
+  );
+
+
+  // check parameters
+
+`ifndef BSG_HIDE_FROM_SYNTHESIS
+  initial begin
+    if (ruche_factor_X_p > 0) begin
+      assert(dims_p > 2) else $fatal(1, "ruche in X direction requires dims_p greater than 2.");
+    end
+    
+    if (ruche_factor_Y_p > 0) begin
+      assert(dims_p > 3) else $fatal(1, "ruche in Y direction requires dims_p greater than 3.");
+    end
+
+    assert($countones(from_p) == 1) else $fatal(1, "Must define from_p as one-hot value.");
+
+    assert(ruche_factor_X_p < (1<<x_cord_width_p)) else $fatal(1, "ruche factor in X direction is too large");
+    assert(ruche_factor_Y_p < (1<<y_cord_width_p)) else $fatal(1, "ruche factor in Y direction is too large");
+  end
+`endif
+
+
+
+
+  // compare coordinates
+  wire x_eq = (x_dirs_i == my_x_i);
+  wire y_eq = (y_dirs_i == my_y_i);
+  wire x_gt = x_dirs_i > my_x_i;
+  wire y_gt = y_dirs_i > my_y_i;
+  wire x_lt = ~x_gt & ~x_eq;
+  wire y_lt = ~y_gt & ~y_eq;
+
+  // valid signal
+  logic [dirs_lp-1:0] req;
+  assign req_o = req;
+
+
+  // P-port
+  assign req[P] = x_eq & y_eq;
+
+
+  if (ruche_factor_X_p > 0) begin
+
+    if (XY_order_p) begin
+      // make sure there is no under/overflow.
+      wire [x_cord_width_p:0] re_cord = (x_cord_width_p+1)'(my_x_i + ruche_factor_X_p);
+      wire send_rw, send_re;
+
+      if (depopulated_p) begin
+        assign send_rw = (my_x_i > (x_cord_width_p)'(ruche_factor_X_p)) && (x_dirs_i < (my_x_i - (x_cord_width_p)'(ruche_factor_X_p)));
+        assign send_re = !re_cord[x_cord_width_p] && (x_dirs_i > re_cord[0+:x_cord_width_p]);
+      end
+      else begin
+        assign send_rw = (my_x_i >= (x_cord_width_p)'(ruche_factor_X_p)) && (x_dirs_i <= (my_x_i - (x_cord_width_p)'(ruche_factor_X_p)));
+        assign send_re = !re_cord[x_cord_width_p] && (x_dirs_i >= re_cord[0+:x_cord_width_p]); // check no overflow
+      end
+
+      assign req[W]  = x_lt & ~send_rw;
+      assign req[RW] = send_rw;
+      assign req[E]  = x_gt & ~send_re;
+      assign req[RE] = send_re;
+    end
+    else begin
+
+      wire [x_cord_width_p-1:0] dxp = (x_cord_width_p)'((x_dirs_i - my_x_i) % ruche_factor_X_p);
+      wire [x_cord_width_p-1:0] dxn = (x_cord_width_p)'((my_x_i - x_dirs_i) % ruche_factor_X_p);
+
+      if (from_p[S] | from_p[N] | from_p[P]) begin
+        if (depopulated_p) begin
+          assign req[W]  = y_eq & x_lt;
+          assign req[RW] = 1'b0;
+          assign req[E]  = y_eq & x_gt;
+          assign req[RE] = 1'b0;
+        end
+        else begin
+          assign req[W]  = y_eq & x_lt & (dxn != '0);
+          assign req[RW] = y_eq & x_lt & (dxn == '0);
+          assign req[E]  = y_eq & x_gt & (dxp != '0);
+          assign req[RE] = y_eq & x_gt & (dxp == '0);
+        end
+      end
+      else if(from_p[W]) begin
+        assign req[RE] = y_eq & x_gt & (dxp == '0);
+        assign req[E]  = y_eq & x_gt & (dxp != '0);
+        assign req[RW] = 1'b0;
+        assign req[W]  = 1'b0;
+      end
+      else if (from_p[E]) begin
+        assign req[RE] = 1'b0;
+        assign req[E]  = 1'b0;
+        assign req[RW] = y_eq & x_lt & (dxn == '0);
+        assign req[W]  = y_eq & x_lt & (dxn != '0);
+      end
+      else if (from_p[RW]) begin
+        assign req[RE] = y_eq & x_gt;
+        assign req[E]  = 1'b0;
+        assign req[RW] = 1'b0;
+        assign req[W]  = 1'b0;
+      end
+      else if (from_p[RE]) begin
+        assign req[RE] = 1'b0;
+        assign req[E]  = 1'b0;
+        assign req[RW] = y_eq & x_lt;
+        assign req[W]  = 1'b0;
+      end
+      else if (from_p[RN] | from_p[RS]) begin
+        if (depopulated_p) begin
+          // If depopulated, there wouldn't be these paths.
+          assign req[RE] = 1'b0;
+          assign req[E]  = 1'b0;
+          assign req[RW] = 1'b0;
+          assign req[W]  = 1'b0;
+        end
+        else begin
+          assign req[W]  = y_eq & x_lt & (dxn != '0);
+          assign req[RW] = y_eq & x_lt & (dxn == '0);
+          assign req[E]  = y_eq & x_gt & (dxp != '0);
+          assign req[RE] = y_eq & x_gt & (dxp == '0);
+        end
+      end
+    end
+  end
+  else begin
+    if (XY_order_p) begin
+      assign req[W] = x_lt;
+      assign req[E] = x_gt;
+    end
+    else begin
+      assign req[W] = y_eq & x_lt;
+      assign req[E] = y_eq & x_gt;
+    end
+  end
+
+
+  
+  if (ruche_factor_Y_p > 0) begin
+    if (XY_order_p == 0) begin
+      // make sure there is no under/overflow.
+      wire [y_cord_width_p:0] rs_cord = (y_cord_width_p+1)'(my_y_i + ruche_factor_Y_p);
+      wire send_rn, send_rs;
+
+      if (depopulated_p) begin
+        assign send_rn = (my_y_i > (y_cord_width_p)'(ruche_factor_Y_p)) && (y_dirs_i < (my_y_i - (y_cord_width_p)'(ruche_factor_Y_p)));
+        assign send_rs = !rs_cord[y_cord_width_p] && (y_dirs_i > rs_cord[0+:y_cord_width_p]);
+      end
+      else begin
+        assign send_rn = (my_y_i >= (y_cord_width_p)'(ruche_factor_Y_p)) && (y_dirs_i <= (my_y_i - (y_cord_width_p)'(ruche_factor_Y_p)));
+        assign send_rs = !rs_cord[y_cord_width_p] && (y_dirs_i >= rs_cord[0+:y_cord_width_p]);
+      end
+
+      assign req[N]  = y_lt & ~send_rn;
+      assign req[RN] = send_rn;
+      assign req[S]  = y_gt & ~send_rs;
+      assign req[RS] = send_rs;
+    end
+    else begin
+
+      wire [y_cord_width_p-1:0] dyp = (y_cord_width_p)'((y_dirs_i - my_y_i) % ruche_factor_Y_p);
+      wire [y_cord_width_p-1:0] dyn = (y_cord_width_p)'((my_y_i - y_dirs_i) % ruche_factor_Y_p);
+
+      if (from_p[E] | from_p[W] | from_p[P]) begin
+        if (depopulated_p) begin
+          assign req[N]  = x_eq & y_lt;
+          assign req[RN] = 1'b0;
+          assign req[S]  = x_eq & y_gt;
+          assign req[RS] = 1'b0;
+        end
+        else begin
+          assign req[N]  = x_eq & y_lt & (dyn != '0);
+          assign req[RN] = x_eq & y_lt & (dyn == '0);
+          assign req[S]  = x_eq & y_gt & (dyp != '0);
+          assign req[RS] = x_eq & y_gt & (dyp == '0);
+        end
+      end
+      else if (from_p[N]) begin
+        assign req[RS] = x_eq & y_gt & (dyp == '0);
+        assign req[S]  = x_eq & y_gt & (dyp != '0);
+        assign req[RN] = 1'b0;
+        assign req[N]  = 1'b0;
+      end
+      else if (from_p[S]) begin
+        assign req[RS] = 1'b0;
+        assign req[S]  = 1'b0;
+        assign req[RN] = x_eq & y_lt & (dyn == '0);
+        assign req[N]  = x_eq & y_lt & (dyn != '0);
+      end
+      else if (from_p[RN]) begin
+        assign req[RS] = x_eq & y_gt;
+        assign req[S]  = 1'b0;
+        assign req[RN] = 1'b0;
+        assign req[N]  = 1'b0;
+      end
+      else if (from_p[RS]) begin
+        assign req[RS] = 1'b0;
+        assign req[S]  = 1'b0;
+        assign req[RN] = x_eq & y_lt;
+        assign req[N]  = 1'b0;
+      end
+      else if (from_p[RW] | from_p[RE]) begin
+        if (depopulated_p) begin
+          // If depopulated, there wouldn't be these paths.
+          assign req[RS] = 1'b0;
+          assign req[S]  = 1'b0;
+          assign req[RN] = 1'b0;
+          assign req[N]  = 1'b0;
+        end
+        else begin
+          assign req[N]  = x_eq & y_lt & (dyn != '0);
+          assign req[RN] = x_eq & y_lt & (dyn == '0);
+          assign req[S]  = x_eq & y_gt & (dyp != '0);
+          assign req[RS] = x_eq & y_gt & (dyp == '0);
+        end
+      end
+    end
+
+  end
+  else begin
+    if (XY_order_p == 0) begin
+      assign req[N] = y_lt;
+      assign req[S] = y_gt;
+    end
+    else begin
+      assign req[N] = x_eq & y_lt;
+      assign req[S] = x_eq & y_gt;
+    end
+  end
+
+
+`ifndef BSG_HIDE_FROM_SYNTHESIS
+  if (debug_p) begin
+    always_ff @ (negedge clk_i) begin
+      if (~reset_i) begin
+        assert($countones(req_o) < 2)
+          else $fatal(1, "multiple req_o detected. %b", req_o);
+      end
+    end
+  end
+  else begin
+    wire unused0 = clk_i;
+    wire unused1 = reset_i;
+  end
+`endif
+
+
+
+
+endmodule
+
+`BSG_ABSTRACT_MODULE(bsg_mesh_router_decoder_dor)
+

snapshots/bespoke-silicon-group_basejump_stl_pr706/bsg_noc/bsg_mesh_stitch.sv

@@ -0,0 +1,67 @@
+// bsg_mesh_stitch
+//
+// MBT 5-26-16
+//
+// stitches together wires according to a mesh topology; edges
+// are returned in hor and ver arrays.
+//
+
+`include "bsg_defines.sv"
+
+module bsg_mesh_stitch
+  import bsg_noc_pkg::*; // P=0, W, E, N, S
+  #(parameter `BSG_INV_PARAM(width_p ) // data width
+    , x_max_p = "inv"
+    , y_max_p = "inv"
+    , nets_p  = 1 // optional parameter that allows for multiple networks to be routed together
+    )
+   (input    [y_max_p-1:0][x_max_p-1:0][nets_p-1:0][S:W][width_p-1:0] outs_i // for each node, each direction
+    , output [y_max_p-1:0][x_max_p-1:0][nets_p-1:0][S:W][width_p-1:0] ins_o
+
+    // these are the edge of the greater tile
+    , input  [E:W][y_max_p-1:0][nets_p-1:0][width_p-1:0] hor_i
+    , output [E:W][y_max_p-1:0][nets_p-1:0][width_p-1:0] hor_o
+    , input  [S:N][x_max_p-1:0][nets_p-1:0][width_p-1:0] ver_i
+    , output [S:N][x_max_p-1:0][nets_p-1:0][width_p-1:0] ver_o
+    );
+
+   genvar r,c,net;
+
+   for (net = 0; net < nets_p; net=net+1)
+     begin: _n
+
+        for (r = 0; r < y_max_p; r=r+1)
+          begin: _r
+             assign hor_o[E][r][net] = outs_i[r][x_max_p-1][net][E];
+             assign hor_o[W][r][net] = outs_i[r][0        ][net][W];
+
+             for (c = 0; c < x_max_p; c=c+1)
+               begin: _c
+                 assign ins_o[r][c][net][S] = (r == y_max_p-1)
+                                            ? ver_i[S][c][net]
+                                            : outs_i[(r == y_max_p-1) ? r : r+1][c][net][N]; // ?: for warning
+                 assign ins_o[r][c][net][N] = (r == 0)
+                                            ? ver_i[N][c][net]
+                                            : outs_i[r ? r-1: 0][c][net][S]; // ?: to eliminate warning
+                 assign ins_o[r][c][net][E] = (c == x_max_p-1)
+                                            ? hor_i[E][r][net]
+                                            : outs_i[r][(c == x_max_p-1) ? c : (c+1)][net][W]; // ?: for warning
+                 assign ins_o[r][c][net][W] = (c == 0)
+                                            ? hor_i[W][r][net]
+                                            : outs_i[r][c ? (c-1) :0][net][E]; // ?: to eliminate warning
+               end // block: c
+          end // block: r
+
+        for (c = 0; c < x_max_p; c=c+1)
+          begin: _c
+             assign ver_o[S][c][net] = outs_i[y_max_p-1][c][net][S];
+             assign ver_o[N][c][net] = outs_i[0        ][c][net][N];
+          end
+     end // block: _n
+
+endmodule
+
+`BSG_ABSTRACT_MODULE(bsg_mesh_stitch)
+
+
+

snapshots/bespoke-silicon-group_basejump_stl_pr706/bsg_noc/bsg_noc_repeater_node.sv

@@ -0,0 +1,74 @@
+//
+// This module instantiates num_nodes_p two-element-fifos in chains
+// It supports multiple bsg_noc_links in parallel
+//
+// Insert this module into long routings on chip, which can become critical path
+//
+// Node that side_A_reset_i signal shoule be close to side A
+// If reset happens to be close to side B, please swap side A and side B connection, 
+// since side A and side B are symmetric, functionality will not be affected.
+//
+
+`include "bsg_defines.sv"
+`include "bsg_noc_links.svh"
+
+module bsg_noc_repeater_node
+
+#(parameter `BSG_INV_PARAM(width_p )
+, parameter bsg_ready_and_link_sif_width_lp = `bsg_ready_and_link_sif_width(width_p)
+)
+
+( input  clk_i
+, input  reset_i
+
+, input  [bsg_ready_and_link_sif_width_lp-1:0] side_A_links_i
+, output [bsg_ready_and_link_sif_width_lp-1:0] side_A_links_o
+
+, input  [bsg_ready_and_link_sif_width_lp-1:0] side_B_links_i
+, output [bsg_ready_and_link_sif_width_lp-1:0] side_B_links_o
+);
+
+  // declare the bsg_ready_and_link_sif_s struct
+  `declare_bsg_ready_and_link_sif_s(width_p, bsg_ready_and_link_sif_s);
+  
+  // noc links
+  bsg_ready_and_link_sif_s links_A_cast_i, links_B_cast_i;
+  bsg_ready_and_link_sif_s links_A_cast_o, links_B_cast_o;
+ 
+  assign links_A_cast_i = side_A_links_i;
+  assign links_B_cast_i = side_B_links_i;
+
+  assign side_A_links_o = links_A_cast_o;
+  assign side_B_links_o = links_B_cast_o;
+
+  bsg_two_fifo #(.width_p(width_p))
+   A_to_B
+    (.clk_i           ( clk_i   )
+     ,.reset_i        ( reset_i )
+
+     ,.v_i            ( links_A_cast_i.v    )
+     ,.data_i         ( links_A_cast_i.data )
+     ,.ready_param_o  ( links_A_cast_o.ready_and_rev )
+
+     ,.v_o            ( links_B_cast_o.v    )
+     ,.data_o         ( links_B_cast_o.data )
+     ,.yumi_i         ( links_B_cast_i.ready_and_rev & links_B_cast_o.v )
+     );
+
+  bsg_two_fifo #(.width_p(width_p))
+   B_to_A
+    (.clk_i           ( clk_i   )
+     ,.reset_i        ( reset_i )
+
+     ,.v_i            ( links_B_cast_i.v    )
+     ,.data_i         ( links_B_cast_i.data )
+     ,.ready_param_o  ( links_B_cast_o.ready_and_rev )
+
+     ,.v_o            ( links_A_cast_o.v    )
+     ,.data_o         ( links_A_cast_o.data )
+     ,.yumi_i         ( links_A_cast_i.ready_and_rev & links_A_cast_o.v )
+     );
+
+endmodule
+
+`BSG_ABSTRACT_MODULE(bsg_noc_repeater_node)

snapshots/bespoke-silicon-group_basejump_stl_pr706/bsg_noc/bsg_wormhole_concentrator.sv

@@ -0,0 +1,121 @@
+//
+// bsg_wormhole_concentrator.sv
+// 
+// 08/2019
+//
+// This is an adapter between 1 concentrated wormhole link and N unconcentrated wormhole links.
+// Extra bits (cid) are used in wormhole header to indicate wormhole packet destination.
+//
+// From implementation perspective this is a simplified version bsg_wormhole_router.
+// Wormhole_router relies on 2D routing_matrix, while wormhole_concentrator has fixed 1-to-n 
+// and n-to-1 routing. This concentrator reuses most of the building blocks of wormhole_router, 
+// concentrator header struct is defined in bsg_wormhole_router.svh.
+//
+// This concentrator has 1-cycle delay from input wormhole link(s) to output wormhole link(s).
+// It has zero bubble between wormhole packets.
+//
+//
+
+`include "bsg_defines.sv"
+`include "bsg_noc_links.svh"
+`include "bsg_wormhole_router.svh"
+
+module bsg_wormhole_concentrator
+
+  #(parameter `BSG_INV_PARAM(flit_width_p)
+    ,parameter `BSG_INV_PARAM(len_width_p)
+    ,parameter `BSG_INV_PARAM(cid_width_p)
+    ,parameter `BSG_INV_PARAM(cord_width_p)
+    ,parameter num_in_p            = 1
+    ,parameter debug_lp            = 0
+    ,parameter link_width_lp       = `bsg_ready_and_link_sif_width(flit_width_p)
+    // Hold on valid sets the arbitration policy such that once an output tag is selected, it
+    // remains selected until it is acked, then the round-robin scheduler continues cycling
+    // from the selected tag. This is consistent with BaseJump STL handshake assumptions.
+    // Notably, this parameter is required to work with bsg_parallel_in_serial_out_passthrough.
+    // This policy has a slight throughput degradation but effectively arbitrates based on age,
+    // so minimizes worst case latency.
+    ,parameter hold_on_valid_p     = 0
+   )
+
+  (input clk_i
+  ,input reset_i
+
+  // unconcentrated multiple links
+  ,input  [num_in_p-1:0][link_width_lp-1:0] links_i
+  ,output [num_in_p-1:0][link_width_lp-1:0] links_o
+
+  // concentrated single link
+  ,input  [link_width_lp-1:0] concentrated_link_i
+  ,output [link_width_lp-1:0] concentrated_link_o
+  );
+
+  `declare_bsg_ready_and_link_sif_s(flit_width_p,bsg_ready_and_link_sif_s);
+  
+  bsg_ready_and_link_sif_s [num_in_p-1:0] links_i_cast, links_o_cast;
+  bsg_ready_and_link_sif_s [num_in_p-1:0] links_o_stubbed_v, links_o_stubbed_ready;
+  
+  bsg_ready_and_link_sif_s concentrated_link_i_cast, concentrated_link_o_cast;
+  bsg_ready_and_link_sif_s concentrated_link_o_stubbed_v, concentrated_link_o_stubbed_ready;
+  
+  assign links_i_cast = links_i;
+  assign links_o = links_o_cast;
+
+  assign concentrated_link_i_cast = concentrated_link_i;
+  assign concentrated_link_o = concentrated_link_o_cast;
+  
+  for (genvar i = 0; i < num_in_p; i++)
+    begin : cast
+      assign links_o_cast[i].data          = links_o_stubbed_ready[i].data;
+      assign links_o_cast[i].v             = links_o_stubbed_ready[i].v;
+      assign links_o_cast[i].ready_and_rev = links_o_stubbed_v[i].ready_and_rev;
+    end
+
+  assign concentrated_link_o_cast.data          = concentrated_link_o_stubbed_ready.data;
+  assign concentrated_link_o_cast.v             = concentrated_link_o_stubbed_ready.v;
+  assign concentrated_link_o_cast.ready_and_rev = concentrated_link_o_stubbed_v.ready_and_rev;
+
+  bsg_wormhole_concentrator_in
+   #(.flit_width_p(flit_width_p)
+     ,.len_width_p(len_width_p)
+     ,.cid_width_p(cid_width_p)
+     ,.num_in_p(num_in_p)
+     ,.cord_width_p(cord_width_p)
+     ,.debug_lp(debug_lp)
+     ,.hold_on_valid_p(hold_on_valid_p)
+     )
+   concentrator_in
+    (.clk_i(clk_i)
+     ,.reset_i(reset_i)
+
+     ,.links_i(links_i)
+     ,.links_o(links_o_stubbed_v)
+
+     ,.concentrated_link_i(concentrated_link_i)
+     ,.concentrated_link_o(concentrated_link_o_stubbed_ready)
+     );
+
+  bsg_wormhole_concentrator_out
+   #(.flit_width_p(flit_width_p)
+     ,.len_width_p(len_width_p)
+     ,.cid_width_p(cid_width_p)
+     ,.num_in_p(num_in_p)
+     ,.cord_width_p(cord_width_p)
+     ,.debug_lp(debug_lp)
+     ,.hold_on_valid_p(hold_on_valid_p)
+     )
+   concentrator_out
+    (.clk_i(clk_i)
+     ,.reset_i(reset_i)
+
+     ,.links_i(links_i)
+     ,.links_o(links_o_stubbed_ready)
+
+     ,.concentrated_link_i(concentrated_link_i)
+     ,.concentrated_link_o(concentrated_link_o_stubbed_v)
+     );
+
+endmodule
+
+
+`BSG_ABSTRACT_MODULE(bsg_wormhole_concentrator)

snapshots/bespoke-silicon-group_basejump_stl_pr706/bsg_noc/bsg_wormhole_router.sv

@@ -0,0 +1,268 @@
+`include "bsg_defines.sv"
+`include "bsg_noc_links.svh"
+`include "bsg_wormhole_router.svh"
+
+module bsg_wormhole_router
+     import bsg_wormhole_router_pkg::StrictXY;
+     import bsg_wormhole_router_pkg::StrictX;
+  #(parameter `BSG_INV_PARAM(flit_width_p)
+   ,parameter dims_p              = 2 // 1
+   ,parameter dirs_lp         = dims_p*2+1
+
+    // this list determines the range of bit values used to determine each dimension in the N-D router
+    // cord_dims_p is normally the same as dims_p.  However, the override allows users to pass
+    // a larger cord array than necessary, useful for parameterizing between 1d/nd networks
+   ,parameter cord_dims_p = dims_p
+   ,parameter int cord_markers_pos_p[cord_dims_p:0] =   '{ 5, 4, 0 }  // '{5,0} //
+   ,parameter bit [1:0][dirs_lp-1:0][dirs_lp-1:0] routing_matrix_p =  (dims_p == 2) ? StrictXY : StrictX
+   ,parameter reverse_order_p       = 0
+   ,parameter `BSG_INV_PARAM(len_width_p)
+   ,parameter debug_lp              = 0
+   // Hold on valid sets the arbitration policy such that once an output tag is selected, it
+   // remains selected until it is acked, then the round-robin scheduler continues cycling
+   // from the selected tag. This is consistent with BaseJump STL handshake assumptions.
+   // Notably, this parameter is required to work with bsg_parallel_in_serial_out_passthrough.
+   // This policy has a slight throughput degradation but effectively arbitrates based on age,
+   // so minimizes worst case latency.
+   ,parameter hold_on_valid_p       = 0
+   )
+
+  (input clk_i
+  ,input reset_i
+
+  // Traffics
+  ,input  [dirs_lp-1:0][`bsg_ready_and_link_sif_width(flit_width_p)-1:0] link_i
+  ,output [dirs_lp-1:0][`bsg_ready_and_link_sif_width(flit_width_p)-1:0] link_o
+
+  // My coordinate data
+   ,input [cord_markers_pos_p[dims_p]-1:0] my_cord_i
+  );
+
+  localparam input_dirs_lp  = dirs_lp;
+  localparam output_dirs_lp = dirs_lp;
+
+  // FIXME: move to bsg_wormhole_router.svh
+  `declare_bsg_wormhole_router_header_s(cord_markers_pos_p[dims_p], len_width_p, bsg_wormhole_router_header_s);
+
+`ifndef BSG_HIDE_FROM_SYNTHESIS
+    wire [dirs_lp-1:0][dirs_lp-1:0] matrix_out_in_transpose;
+
+    bsg_transpose #(.width_p(dirs_lp),.els_p(dirs_lp)) tr (.i(routing_matrix_p[0])
+                                                          ,.o(matrix_out_in_transpose)
+                                                          );
+    always_ff @(negedge reset_i)
+      begin
+        assert (routing_matrix_p[1] == matrix_out_in_transpose)
+          else $error("inconsistent matrixes");
+      end
+`endif
+
+  // we collect the information for each FIFO here
+  wire [input_dirs_lp-1:0][flit_width_p-1:0] fifo_data_lo;
+  wire [input_dirs_lp-1:0]                     fifo_valid_lo;
+
+  // one for each input channel; it broadcasts that it is finished to all of the outputs
+  wire [dirs_lp-1:0] releases;
+
+  // from each input to each output
+  wire [dirs_lp-1:0][dirs_lp-1:0] reqs,     reqs_transpose;
+
+  // from each output to each input
+  wire [dirs_lp-1:0][dirs_lp-1:0] yumis,    yumis_transpose;
+
+  `declare_bsg_ready_and_link_sif_s(flit_width_p,bsg_ready_and_link_sif_s);
+  bsg_ready_and_link_sif_s [dirs_lp-1:0] link_i_cast, link_o_cast;
+
+  assign link_i_cast = link_i;
+  assign link_o = link_o_cast;
+
+  genvar i,j;
+
+  for (i = 0; i < input_dirs_lp; i=i+1)
+    begin: in_ch
+      localparam output_dirs_sparse_lp = `BSG_COUNTONES_SYNTH(routing_matrix_p[0][i]);
+
+      // live decoding of output dirs from header
+
+      wire [output_dirs_lp-1:0]        decoded_dest_lo;
+      wire [output_dirs_sparse_lp-1:0] decoded_dest_sparse_lo;
+      wire [output_dirs_sparse_lp-1:0] reqs_lo, yumis_li;
+
+      bsg_concentrate_static #(.pattern_els_p(routing_matrix_p[0][i])) conc
+      (.i(yumis_transpose[i])
+       ,.o(yumis_li)
+      );
+
+      wire any_yumi = | yumis_li;
+
+      bsg_two_fifo #(.width_p(flit_width_p)) twofer
+        (.clk_i
+         ,.reset_i
+        ,.ready_param_o (link_o_cast[i].ready_and_rev)
+        ,.data_i        (link_i_cast[i].data)
+        ,.v_i           (link_i_cast[i].v)
+        ,.v_o           (fifo_valid_lo[i])
+        ,.data_o        (fifo_data_lo [i])
+        ,.yumi_i        (any_yumi)
+         );
+
+      bsg_wormhole_router_header_s hdr;
+
+      assign hdr = fifo_data_lo[i][$bits(bsg_wormhole_router_header_s)-1:0];
+
+`ifndef BSG_HIDE_FROM_SYNTHESIS
+      if (debug_lp)
+        begin
+           logic release_r;
+
+           always_ff @(posedge clk_i)
+             release_r <= releases[i];
+
+           always_ff @(negedge clk_i)
+             begin
+                if (releases[i] & ~release_r)
+                  $display("%m in  ch%2d: packet finished last cycle",i);
+
+                if ((reset_i === 1'b0) && link_i_cast[i].v && !link_o_cast[i].ready_and_rev)
+                  $display("%m in  ch%2d: nacking   packet %h",i,link_i_cast[i].data);
+                else
+                  if ((reset_i === 1'b0) && link_i_cast[i].v && link_o_cast[i].ready_and_rev)
+                    $display("%m in  ch%2d: accepting packet %h",i,link_i_cast[i].data);
+                if ((reset_i === 1'b0) && any_yumi)
+                  begin
+                     assert (fifo_valid_lo[i]) else $error("Error dequeing when data not available");
+                     if (reqs_lo)
+                       $display("%m in  ch%2d: dequeing  header %h (outch=%b,len=%b,dest=%b)",i,fifo_data_lo[i],reqs_lo,hdr.len,hdr.cord);
+                     else
+                       $display ("%m in  ch%2d: dequeing  packet %h",i, fifo_data_lo[i]);
+                  end
+
+             end // always_ff @
+        end
+`endif
+
+      bsg_wormhole_router_decoder_dor #(.dims_p(dims_p)
+                                       ,.cord_dims_p(cord_dims_p)
+                                       ,.reverse_order_p(reverse_order_p)
+                                       ,.cord_markers_pos_p(cord_markers_pos_p)
+                                       ) dor
+      (.target_cord_i(hdr.cord)
+       ,.my_cord_i
+       ,.req_o(decoded_dest_lo)
+      );
+
+      bsg_concentrate_static #(.pattern_els_p(routing_matrix_p[0][i])) conc_dec
+      (.i(decoded_dest_lo)
+       ,.o(decoded_dest_sparse_lo)
+      );
+
+      // fixme: add assertions for stubbed out parameters
+
+      wire detected_header_lo;
+
+      bsg_wormhole_router_input_control #(.output_dirs_p(output_dirs_sparse_lp), .payload_len_bits_p($bits(hdr.len))) wic
+      (.clk_i
+       ,.reset_i
+       ,.fifo_v_i           (fifo_valid_lo[i])
+       ,.fifo_yumi_i        (any_yumi)
+       ,.fifo_decoded_dest_i(decoded_dest_sparse_lo)
+       ,.fifo_payload_len_i (hdr.len)
+       ,.reqs_o             (reqs_lo)
+       ,.release_o          (releases[i]) // broadcast to all
+       ,.detected_header_o  (detected_header_lo)
+      );
+
+       // switch to dense matrix form
+      bsg_unconcentrate_static #(.pattern_els_p(routing_matrix_p[0][i])) unc
+        (.i  (reqs_lo)
+         ,.o (reqs[i]) // unicast
+       );
+
+`ifndef BSG_HIDE_FROM_SYNTHESIS
+      always_ff @(negedge clk_i)
+        if (debug_lp)
+          assert (detected_header_lo!==1'b1 || !(decoded_dest_lo & ~ routing_matrix_p[0][i]))
+            else $error("%m input port %d request to route in direction not supported by router %b %b",i,decoded_dest_lo, routing_matrix_p[0][i]);
+`endif
+
+    end
+
+   // flip signal wires from input-indexed to output-indexed
+   // this is swizzling the wires that connect input ports and output ports
+   bsg_transpose #(.width_p(dirs_lp),.els_p(dirs_lp)) reqs_trans
+   (.i(reqs)
+    ,.o(reqs_transpose)
+   );
+
+  // iterate through each output channel
+  for (i = 0; i < output_dirs_lp; i=i+1)
+    begin: out_ch
+      localparam input_dirs_sparse_lp = `BSG_COUNTONES_SYNTH(routing_matrix_p[1][i]);
+      wire [input_dirs_sparse_lp-1:0] reqs_li, release_li, valids_li, yumis_lo, data_sel_lo;
+      wire [input_dirs_sparse_lp-1:0][flit_width_p-1:0] fifo_data_sparse_lo;
+
+      bsg_concentrate_static #(.pattern_els_p(routing_matrix_p[1][i])) conc
+      (.i(reqs_transpose[i]),.o(reqs_li));
+
+      bsg_concentrate_static #(.pattern_els_p(routing_matrix_p[1][i])) conc2
+      (.i(releases),.o(release_li));
+
+      bsg_concentrate_static #(.pattern_els_p(routing_matrix_p[1][i])) conc3
+      (.i(fifo_valid_lo),.o(valids_li));
+
+      bsg_array_concentrate_static #(.width_p(flit_width_p), .pattern_els_p(routing_matrix_p[1][i])) conc4
+      (.i(fifo_data_lo),.o(fifo_data_sparse_lo));
+
+      bsg_wormhole_router_output_control
+      #(.input_dirs_p(input_dirs_sparse_lp), .hold_on_valid_p(hold_on_valid_p)) woc
+      (.clk_i
+      ,.reset_i
+      ,.reqs_i      (reqs_li   )
+      ,.release_i   (release_li)
+      ,.valid_i     (valids_li )
+      ,.yumi_o      (yumis_lo  )
+      ,.ready_and_i (link_i_cast[i].ready_and_rev)
+      ,.valid_o     (link_o_cast[i].v)
+      ,.data_sel_o  (data_sel_lo)
+      );
+
+`ifndef BSG_HIDE_FROM_SYNTHESIS
+       always_ff @(negedge clk_i)
+         begin
+            if (debug_lp)
+              begin
+                if ((reset_i === 1'b0) && link_o_cast[i].v)
+                  begin
+                    if (link_i_cast[i].ready_and_rev)
+                      begin
+                        $display("%m out ch%2d: sending   packet %h",i,link_o_cast[i].data);
+                      end
+                  end
+              end
+         end
+`endif
+
+      bsg_mux_one_hot #(.width_p(flit_width_p)
+                       ,.els_p(input_dirs_sparse_lp)
+                       ) data_mux
+      (.data_i(fifo_data_sparse_lo)
+       ,.sel_one_hot_i(data_sel_lo)
+       ,.data_o(link_o_cast[i].data)
+      );
+
+      bsg_unconcentrate_static #(.pattern_els_p(routing_matrix_p[1][i])) unc1
+      (.i (yumis_lo)
+       ,.o (yumis[i])
+      );
+    end
+
+   // flip signal wires from output-indexed to input-indexed
+   // this is swizzling the wires that connect input ports and output ports
+   bsg_transpose #(.width_p(dirs_lp),.els_p(dirs_lp)) yumis_trans
+   (.i(yumis)
+    ,.o(yumis_transpose)
+   );
+
+endmodule
+
+`BSG_ABSTRACT_MODULE(bsg_wormhole_router)

snapshots/bespoke-silicon-group_basejump_stl_pr706/bsg_noc/bsg_wormhole_router.svh

@@ -0,0 +1,46 @@
+// this is a partial packet header should always go at the bottom bits of a header flit
+// move to bsg_wormhole_router.svh
+// FIXME:  have them pass in the cord_markers_pos_p
+//         struct, then it will match bsg_wormhole_router
+//
+
+`define declare_bsg_wormhole_router_header_s(cord_width_mp, len_width_mp, struct_name_mp) \
+typedef struct packed {                 \
+  logic [len_width_mp-1:0]    len;      \
+  logic [cord_width_mp-1:0 ]  cord;     \
+} struct_name_mp
+
+`define declare_bsg_wormhole_concentrator_header_s(cord_width_mp, len_width_mp, cid_width, struct_name_mp) \
+  typedef struct packed {               \
+    logic [cid_width-1:0]     cid;      \
+    logic [len_width_mp-1:0]  len;      \
+    logic [cord_width_mp-1:0] cord;     \
+  } struct_name_mp
+
+`define declare_bsg_wormhole_router_packet_s(cord_width_mp, len_width_mp, payload_width_mp, struct_name_mp) \
+typedef struct packed {                 \
+  logic [payload_width_mp-1:0] payload; \
+  logic [len_width_mp-1:0]     len;     \
+  logic [cord_width_mp-1:0]    cord;    \
+} struct_name_mp
+
+`define declare_bsg_wormhole_concentrator_packet_s(cord_width_mp, len_width_mp, cid_width_mp, payload_width_mp, struct_name_mp) \
+typedef struct packed {                 \
+  logic [payload_width_mp-1:0] payload; \
+  logic [cid_width_mp-1:0]     cid;     \
+  logic [len_width_mp-1:0]     len;     \
+  logic [cord_width_mp-1:0]    cord;    \
+} struct_name_mp
+
+`define bsg_wormhole_router_header_width(cord_width_mp, len_width_mp) \
+  (cord_width_mp + len_width_mp)
+
+`define bsg_wormhole_concentrator_header_width(cord_width_mp, len_width_mp, cid_width_mp) \
+  (cord_width_mp + len_width_mp + cid_width_mp)
+
+`define bsg_wormhole_concentrator_packet_width(cord_width_mp, len_width_mp, cid_width_mp, payload_width_mp) \
+  (cord_width_mp + len_width_mp + cid_width_mp + payload_width_mp)
+
+`define bsg_wormhole_router_packet_width(cord_width_mp, len_width_mp, payload_width_mp) \
+  (cord_width_mp + len_width_mp + payload_width_mp)
+

snapshots/bespoke-silicon-group_basejump_stl_pr706/bsg_noc/bsg_wormhole_router_adapter_in.sv

@@ -0,0 +1,75 @@
+/**
+ *  bsg_wormhole_router_adapter_in.sv
+ *
+ *  packet = {payload, length, cord}
+ *
+ *  Goes from a wide register containing an entire packet to a serialized packet.
+ *  Most useful for testbenches, and in hardware, shorter packets where the data is
+ *  not naturally serialized.
+ */
+
+`include "bsg_defines.sv"
+
+`include "bsg_noc_links.svh"
+`include "bsg_wormhole_router.svh"
+
+module bsg_wormhole_router_adapter_in
+  #(parameter `BSG_INV_PARAM(max_payload_width_p )
+    , parameter `BSG_INV_PARAM(len_width_p       )
+    , parameter `BSG_INV_PARAM(cord_width_p      )
+    , parameter `BSG_INV_PARAM(flit_width_p      )
+
+    , localparam bsg_ready_and_link_sif_width_lp =
+        `bsg_ready_and_link_sif_width(flit_width_p)
+    , localparam bsg_wormhole_packet_width_lp = 
+        `bsg_wormhole_router_packet_width(cord_width_p, len_width_p, max_payload_width_p)
+    )
+   (input                                          clk_i
+    , input                                        reset_i
+
+    , input [bsg_wormhole_packet_width_lp-1:0]     packet_i
+    , input                                        packet_v_i
+    , output                                       packet_ready_and_o
+
+    , output [flit_width_p-1:0]                    link_data_o
+    , output                                       link_v_o
+    , input                                        link_ready_and_i
+    );
+
+  `declare_bsg_wormhole_router_packet_s(cord_width_p, len_width_p, max_payload_width_p, bsg_wormhole_packet_s);
+  bsg_wormhole_packet_s packet_cast_i;
+  assign packet_cast_i = packet_i;
+
+  localparam max_num_flits_lp = `BSG_CDIV($bits(bsg_wormhole_packet_s), flit_width_p);
+  localparam protocol_len_lp  = `BSG_SAFE_CLOG2(max_num_flits_lp);
+  wire [max_num_flits_lp*flit_width_p-1:0] packet_padded_li = packet_i;
+
+  bsg_parallel_in_serial_out_dynamic
+   #(.width_p(flit_width_p)
+     ,.max_els_p(max_num_flits_lp)
+     )
+   piso
+    (.clk_i(clk_i)
+     ,.reset_i(reset_i)
+
+     ,.v_i(packet_v_i)
+     ,.len_i(protocol_len_lp'(packet_cast_i.len))
+     ,.data_i(packet_padded_li)
+     ,.ready_and_o(packet_ready_and_o)
+
+     ,.v_o(link_v_o)
+     ,.len_v_o(/* unused */)
+     ,.data_o(link_data_o)
+     ,.yumi_i(link_ready_and_i & link_v_o)
+     );
+
+`ifndef BSG_HIDE_FROM_SYNTHESIS
+  always_ff @(negedge clk_i)
+    assert(reset_i || ~packet_v_i || (packet_cast_i.len <= max_num_flits_lp))
+      else 
+        $error("Packet received with len: %x > max_num_flits: %x", packet_cast_i.len, max_num_flits_lp);
+`endif
+
+endmodule
+
+`BSG_ABSTRACT_MODULE(bsg_wormhole_router_adapter_in)

snapshots/bespoke-silicon-group_basejump_stl_pr706/bsg_noc/bsg_wormhole_router_adapter_out.sv

@@ -0,0 +1,95 @@
+/**
+ *  bsg_wormhole_router_adapter_out.sv
+ *
+ *  packet = {payload, length, cord}
+ *
+ *  Basic module that deserializes an incoming wormhole packet into a wide register.
+ *  This is especially useful for testbenches. (For hardware,
+ *  full deserialization adds latency and area, this is often undesireable, but for
+ *  small packets, it may make sense to use it.)
+ */
+
+`include "bsg_defines.sv"
+
+`include "bsg_noc_links.svh"
+`include "bsg_wormhole_router.svh"
+
+module bsg_wormhole_router_adapter_out
+  #(parameter `BSG_INV_PARAM(max_payload_width_p )
+    , parameter `BSG_INV_PARAM(len_width_p       )
+    , parameter `BSG_INV_PARAM(cord_width_p      )
+    , parameter `BSG_INV_PARAM(flit_width_p      )
+
+    , localparam bsg_ready_and_link_sif_width_lp =
+        `bsg_ready_and_link_sif_width(flit_width_p)
+    , localparam bsg_wormhole_packet_width_lp =
+        `bsg_wormhole_router_packet_width(cord_width_p, len_width_p, max_payload_width_p)
+    )
+   (input                                          clk_i
+    , input                                        reset_i
+
+    , input                                        link_v_i
+    , input  [max_payload_width_p-1:0]             link_data_i
+    , output                                       link_ready_and_o
+
+    , output [bsg_wormhole_packet_width_lp-1:0]    packet_o
+    , output                                       packet_v_o
+    , input                                        packet_yumi_i
+    );
+
+  `declare_bsg_wormhole_router_header_s(cord_width_p, len_width_p, bsg_wormhole_header_s);
+  bsg_wormhole_header_s header_li;
+  assign header_li = link_data_i;
+
+  `declare_bsg_wormhole_router_packet_s(cord_width_p,len_width_p,max_payload_width_p,bsg_wormhole_packet_s);
+
+  localparam max_num_flits_lp = `BSG_CDIV($bits(bsg_wormhole_packet_s), flit_width_p);
+  localparam protocol_len_lp  = `BSG_SAFE_CLOG2(max_num_flits_lp);
+  logic [max_num_flits_lp*flit_width_p-1:0] packet_padded_lo;
+  bsg_serial_in_parallel_out_dynamic
+   #(.width_p(flit_width_p)
+     ,.max_els_p(max_num_flits_lp)
+     )
+   sipo
+    (.clk_i(clk_i)
+     ,.reset_i(reset_i)
+
+     ,.data_i(link_data_i)
+     ,.len_i(protocol_len_lp'(header_li.len))
+     ,.ready_and_o(link_ready_and_o)
+     ,.len_ready_o(/* unused */)
+     ,.v_i(link_v_i)
+
+     ,.v_o(packet_v_o)
+     ,.data_o(packet_padded_lo)
+     ,.yumi_i(packet_yumi_i)
+     );
+  assign packet_o = packet_padded_lo[0+:bsg_wormhole_packet_width_lp];
+
+
+
+`ifndef BSG_HIDE_FROM_SYNTHESIS
+  logic recv_r;
+  bsg_dff_reset_en
+   #(.width_p(1))
+   recv_reg
+    (.clk_i(clk_i)
+     ,.reset_i(reset_i)
+     ,.en_i(link_v_i || packet_yumi_i)
+
+     ,.data_i(link_v_i)
+     ,.data_o(recv_r)
+     );
+  wire new_header_li = ~recv_r & link_v_i;
+
+  // TODO: This assertion is buggy and fires erroneously
+  //always_ff @(negedge clk_i)
+  //  assert(reset_i || ~new_header_li || (header_li.len <= max_num_flits_lp))
+  //    else 
+  //      $error("Header received with len: %x > max_num_flits: %x", header_li.len, max_num_flits_lp);
+`endif
+
+endmodule
+
+`BSG_ABSTRACT_MODULE(bsg_wormhole_router_adapter_out)
+

snapshots/bespoke-silicon-group_basejump_stl_pr706/bsg_noc/bsg_wormhole_router_output_control.sv

@@ -0,0 +1,67 @@
+`include "bsg_defines.sv"
+
+module bsg_wormhole_router_output_control
+  #(parameter `BSG_INV_PARAM(input_dirs_p)
+    // Hold on valid sets the arbitration policy such that once an output tag is selected, it
+    // remains selected until it is acked, then the round-robin scheduler continues cycling
+    // from the selected tag. This is consistent with BaseJump STL handshake assumptions.
+    // Notably, this parameter is required to work with bsg_parallel_in_serial_out_passthrough.
+    // This policy has a slight throughput degradation but effectively arbitrates based on age,
+    // so minimizes worst case latency.
+    , parameter hold_on_valid_p = 0
+    )
+   (input clk_i
+    , input reset_i
+
+    // this input channel has a header packet at the head of the FIFO for this output
+    , input  [input_dirs_p-1:0] reqs_i
+
+    // the input channel finished a packet on the previous cycle
+    // note: it is up to this module to verify that the input channel was allocated to this output channel
+    , input  [input_dirs_p-1:0] release_i
+
+    // from input fifos
+    , input [input_dirs_p-1:0] valid_i
+    , output [input_dirs_p-1:0] yumi_o
+
+    // channel outputs
+    , input ready_and_i
+    , output valid_o
+    , output [input_dirs_p-1:0] data_sel_o
+    );
+
+   wire [input_dirs_p-1:0] scheduled_r, scheduled_with_release, scheduled_n, grants_lo;
+
+   bsg_dff_reset #(.width_p(input_dirs_p)) scheduled_reg (.clk_i, .reset_i, .data_i(scheduled_n), .data_o(scheduled_r));
+
+   assign scheduled_with_release = scheduled_r & ~release_i;
+
+   wire                     free_to_schedule = !scheduled_with_release;
+
+   bsg_round_robin_arb
+     #(.inputs_p(input_dirs_p), .hold_on_valid_p(hold_on_valid_p))
+   brr
+   (.clk_i
+    ,.reset_i
+    ,.grants_en_i  (free_to_schedule)      // ports are all free
+    ,.reqs_i       (reqs_i)                // requests from input ports
+    ,.grants_o     (grants_lo)             // output grants, takes into account grants_en_i
+    ,.sel_one_hot_o()                      // output grants, does not take into account grants_en_i
+    ,.v_o          ()                      // some reqs_i was set
+    ,.tag_o        ()
+    // make sure to only allocate the port if we succeeded in transmitting the header
+    // otherwise the input will try to allocate again on the next cycle
+    ,.yumi_i       (free_to_schedule & ready_and_i & valid_o) // update round_robin
+    );
+
+   assign scheduled_n = grants_lo | scheduled_with_release;
+   assign data_sel_o = scheduled_n;
+   assign valid_o = (|(scheduled_n & valid_i));
+   assign yumi_o  = ready_and_i ? (scheduled_n & valid_i) : '0;
+endmodule
+
+`BSG_ABSTRACT_MODULE(bsg_wormhole_router_output_control)
+
+
+
+

snapshots/bespoke-silicon-group_basejump_stl_pr706/bsg_noc/bsg_wormhole_router_pkg.sv

@@ -0,0 +1,145 @@
+`include "bsg_defines.sv"
+
+package bsg_wormhole_router_pkg;
+  localparam  bit [1:0][2:0][2:0] StrictX
+                             = {   // EWP (input)
+                                {  3'b011 // E
+                                  ,3'b101 // W
+                                  ,3'b111 // P (output)
+                                }
+                               ,   // EWP (output)
+                                {  3'b011 // E
+                                  ,3'b101 // W
+                                  ,3'b111 // P (input)
+                                }
+                              };
+
+  localparam  bit [1:0][2:0][2:0] X_AllowLoopBack  // for testing only; you should never build a machine like this 
+                             = {   // EWP (input)    // it will deadlock
+                                {  3'b100 // E
+                                  ,3'b010 // W
+                                  ,3'b000 // P (output)
+                                }
+                               ,   // EWP (output)
+                                {  3'b111 // E
+                                  ,3'b111 // W
+                                  ,3'b111 // P (input)
+                                }
+                              };
+
+  localparam bit [1:0][4:0][4:0] StrictXY
+                            = {
+                               {//  SNEWP (input)
+                                 5'b01111  // S
+                                ,5'b10111  // N
+                                ,5'b00011  // E
+                                ,5'b00101  // W
+                                ,5'b11111  // P (output)
+                                }
+                               ,
+                               {//  SNEWP (output)
+                                 5'b01001  // S
+                                ,5'b10001  // N
+                                ,5'b11011  // E
+                                ,5'b11101  // W
+                                ,5'b11111  // P (input)
+                                }
+                               };
+
+  localparam bit [1:0][4:0][4:0] StrictYX
+                            = {
+                               {//  SNEWP (input)
+                                 5'b01001  // S
+                                ,5'b10001  // N
+                                ,5'b11011  // E
+                                ,5'b11101  // W
+                                ,5'b11111  // P (output)
+                                }
+                               ,
+                               {//  SNEWP (output)
+                                 5'b01111  // S
+                                ,5'b10111  // N
+                                ,5'b00011  // E
+                                ,5'b00101  // W
+                                ,5'b11111  // P (input)
+                                }
+                               };
+
+  // These are "OR-in" matrices, that are intended to be layered upon StrictYX or Strict XY.
+ localparam bit [1:0][4:0][4:0] XY_Allow_S
+                            = {
+                               {//  SNEWP (input)
+                                 5'b00000  // S
+                                ,5'b00000  // N
+                                ,5'b10000  // E
+                                ,5'b10000  // W
+                                ,5'b00000  // P (output)
+                                }
+                               ,
+                               {//  SNEWP (output)
+                                 5'b00110  // S
+                                ,5'b00000  // N
+                                ,5'b00000  // E
+                                ,5'b00000  // W
+                                ,5'b00000  // P (input)
+                                }
+                               };
+
+ localparam bit [1:0][4:0][4:0]  XY_Allow_N
+                            = {
+                               {//  SNEWP (input)
+                                 5'b00000  // S
+                                ,5'b00000  // N
+                                ,5'b01000  // E
+                                ,5'b01000  // W
+                                ,5'b00000  // P (output)
+                                }
+                               ,
+                               {//  SNEWP (output)
+                                 5'b00000  // S
+                                ,5'b00110  // N
+                                ,5'b00000  // E
+                                ,5'b00000  // W
+                                ,5'b00000  // P (input)
+                                }
+                               };
+
+ localparam bit
+   [1:0][4:0][4:0] YX_Allow_W = {
+                               {//  SNEWP (input)
+                                 5'b00010  // S
+                                ,5'b00010  // N
+                                ,5'b00000  // E
+                                ,5'b00000  // W
+                                ,5'b00000  // P (output)
+                                }
+                               ,
+                               {//  SNEWP (output)
+                                 5'b00000  // S
+                                ,5'b00000  // N
+                                ,5'b00000  // E
+                                ,5'b11000  // W
+                                ,5'b00000  // P (input)
+                                }
+                               };
+
+ localparam bit
+   [1:0][4:0][4:0] YX_Allow_E = {
+                               {//  SNEWP (input)
+                                 5'b00100  // S
+                                ,5'b00100  // N
+                                ,5'b00000  // E
+                                ,5'b00000  // W
+                                ,5'b00000  // P (output)
+                                }
+                               ,
+                               {//  SNEWP (output)
+                                 5'b00000  // S
+                                ,5'b00000  // N
+                                ,5'b11000  // E
+                                ,5'b00000  // W
+                                ,5'b00000  // P (input)
+                                }
+                               };
+
+endpackage

snapshots/bespoke-silicon-group_basejump_stl_pr706/bsg_tag/README

@@ -0,0 +1,7 @@
+See this LatchUp 2023 slide deck for a detailed rational and description of bsg_tag:
+
+https://docs.google.com/presentation/d/18ILrko9kOfioF4d6rrcotiHvpBK8Bl3xfFB93Xv0of4/edit#slide=id.p
+
+bsg_tag is quite fast (400 mbps) for many configuration tasks, but for gate-level sims of large chips, it can be helpful to accelerate evermore. 
+One approach is to directly manipulate the lines coming out of bsg_tag master. Partial orders between tag addresses can be encoded in a file, and
+then a scheduler can derive the maximally parallel bsg_tag sequence that can boot the chip through a SystemVerilog testbench.

snapshots/bespoke-silicon-group_basejump_stl_pr706/bsg_tag/bsg_tag.svh

@@ -0,0 +1,59 @@
+// bsg_tag
+//
+// bsg_tag implements a serial configuration network. 
+//
+// the abstraction is that you have a number of multibit registers inside your chip that
+// you would like to configure, either before the
+// chip boots, or even as the chip runs. bsg_tag correctly handles
+// clock domain crossings, so multibit registers will be updated atomically, allowing on-the-fly
+// configuration changes. however, for this to happen, both the tag clock and the destination
+// clock must be active, and enough clock cycles must pass on both sides for the data to be absorbed.
+//
+// bsg_tag enables this capability using only three
+// external pins on the chip -- one for a clock, one for data, and one for a failsafe enable.
+//
+// each multibit register has a nodeID, and a customized length, and is implemented with a bsg_tag_client
+//
+// when you stream data into the chip, a single bsg_tag_master module demultiplexes the incoming packets 
+// according to nodeID out to the bsg_tag_client nodes. each client has a 4-wire connection to the master
+// -- the shared tag clock, the failsafe enable, and a two-bit opcode. the opcode encodes 4 operations:
+// shift in 1, shift in 0, reset, and noop. A noop immediately following a shift indicates that the 
+// transfer is done and should be sent across the CDC.
+//
+// - to reset the bsg_tag_master node, a stream of 0's is sent. 
+// - to reset the client, you
+//   transmit a 1, then the nodeID, a 0, then a length, and then length ' 1 bits.
+// - to transmit data to a client, you 
+//   transmit a 1, then the nodeID, a 1, then the length, then the data.
+// - to not send data, transmit 0's.
+//
+// the enable signal is an out-of-band signal. if enable is low, then all of the bsg_tag_clients
+// are disconnected from the masters. it should not be asserted / deasserted 
+// when trying to send data at the same time. 
+//
+// when using bsg_tag to program the clock generators, the enable signal must be low
+// initially because the clock generators must already be running in order to absorb data
+// from the bsg_tag and be programmed. =)
+//
+// see bsg_ip_cores/testing/bsg_clk_gen/bsg_nonsynth_clk_gen_tester.sv for an example usage
+//
+// the bsg_tag clock should be asserted 180 degrees out of phase with the data/en signals, to
+// avoid setup/hold time violations. i.e. use negedge clock.
+//
+
+`ifndef BSG_TAG_VH
+`define BSG_TAG_VH
+
+`define declare_bsg_tag_header_s(PARAM_els,PARAM_lg_width)                  \
+                                                                            \
+   typedef struct packed {                                                  \
+      logic [`BSG_SAFE_CLOG2((PARAM_els))-1:0]       nodeID;                \
+      logic                                          data_not_reset;        \
+      logic [(PARAM_lg_width)-1:0] len;                                     \
+      } bsg_tag_header_s;
+
+`define bsg_tag_max_packet_len(PARAM_els,PARAM_lg_width) ((1 << (PARAM_lg_width)) - 1 + $bits(bsg_tag_header_s))
+`define bsg_tag_reset_len(PARAM_els,PARAM_lg_width) ((1 << `BSG_SAFE_CLOG2(`bsg_tag_max_packet_len((PARAM_els),(PARAM_lg_width))+1))+1)
+
+
+`endif //  `ifndef BSG_TAG_VH

snapshots/bespoke-silicon-group_basejump_stl_pr706/bsg_tag/bsg_tag_bitbang.sv

@@ -0,0 +1,75 @@
+
+`include "bsg_defines.sv"
+
+/*
+ * This module takes 1 bit of data and sends it out along with a clock pulse.
+ *
+ * When this module receives a bit, tag_clk_r_o becomes low and the
+ *   received data is put on tag_data_r_o on the current cycle. On next cycle,
+ *   tag_clk_r_o will become high and generate a positive clock edge. The clock
+ *   signal will remain high until the next data comes in.
+ *
+ *                -----+
+ * v_i:                |
+ *                     +-----------------------------
+ *
+ *                     +-----+     +-----+     +-----
+ * clk_i:              |     |     |     |     |
+ *                -----+     +-----+     +-----+
+ *
+ *                -----+           +-----------------
+ * tag_clk_r_o:        |           |
+ *                     +-----------+
+ *
+ *                     +-----------------------+
+ * tag_data_r_o:       |                       |
+ *                -----+                       +-----
+ *
+ * One use case is to write sequence of data from software through bsg_tag_bitbang
+ *   to bsg tag master. This eliminates the need of dedicated hardware, like a ROM
+ *   and a tag trace replay module.
+ *
+ */                                        
+
+module bsg_tag_bitbang(
+    input clk_i
+  , input reset_i
+  , input data_i
+  , input v_i
+  , output logic ready_and_o // throughput: clk_i / 2
+
+  // tag clock is a synchronously generated variable frequency clock that toggles
+  //   once for every data bit that is transmitted.
+  , output logic tag_clk_r_o
+  , output logic tag_data_r_o
+);
+
+  logic tag_clk_r;
+  logic tag_data_r;
+  // Lower tag clock for one cycle upon a successful handshake
+  wire tag_clk_n = ~(ready_and_o & v_i);
+
+  bsg_dff_reset #(
+     .width_p(1)
+    ,.reset_val_p(1)
+  ) tag_clk_reg (
+     .clk_i(clk_i)
+    ,.reset_i(reset_i)
+    ,.data_i(tag_clk_n)
+    ,.data_o(tag_clk_r)
+  );
+
+  bsg_dff_en #(.width_p(1)
+  ) tag_data_reg (
+     .clk_i(clk_i)
+    ,.data_i(data_i)
+    ,.en_i(~tag_clk_n)
+    ,.data_o(tag_data_r)
+  );
+
+  assign tag_data_r_o = tag_data_r;
+  assign tag_clk_r_o = tag_clk_r;
+  assign ready_and_o = tag_clk_r;
+
+endmodule
+

snapshots/bespoke-silicon-group_basejump_stl_pr706/bsg_tag/bsg_tag_client_unsync.sv

@@ -0,0 +1,109 @@
+//
+// bsg_tag_client_unsync
+//
+// simple serial on-chip configuration network
+//
+// this client has only the shift register that captures data from the client
+// no attempt is made to perform any synchronzation, or to hide intermediate toggles
+// of bits as values are shifted in.
+//
+// generally speaking, this version should only be used in special cases:
+//
+// - where values are not intended to be updated on the fly as the chip runs;
+//   i.e. configuration prior to reset
+//
+// - where receive logic has been explicitly coded separately
+//
+// 5/26/2018 MBT
+//
+//
+// RESET SEMANTICS
+//
+// 1. Shift in the value you want to use.
+// 2. Deassert reset on the receive side module.
+//
+
+`include "bsg_defines.sv"
+
+module bsg_tag_client_unsync
+  import bsg_tag_pkg::bsg_tag_s;
+   #(parameter `BSG_INV_PARAM(width_p), harden_p=1, debug_level_lp=0)
+   (
+    input 		 bsg_tag_s bsg_tag_i
+
+    ,output [width_p-1:0] data_async_r_o
+    );
+
+   logic   op_r, param_r;
+
+   always_ff @(posedge bsg_tag_i.clk)
+     begin
+        op_r    <= bsg_tag_i.op;
+        param_r <= bsg_tag_i.param;
+     end
+
+   wire shift_op = op_r;
+   wire no_op    = ~op_r & ~param_r;
+
+   logic [width_p-1:0] tag_data_r, tag_data_n, tag_data_shift;
+
+   // shift in new state
+   if (width_p > 1)
+     begin : fi
+	assign tag_data_shift = { param_r, tag_data_r[width_p-1:1] };
+     end
+   else
+     begin: fi
+	assign tag_data_shift = param_r;
+     end
+	
+   bsg_mux2_gatestack #(.width_p(width_p),.harden_p(harden_p)) tag_data_mux
+     (.i0 (tag_data_r            ) // sel=0
+      ,.i1(tag_data_shift        ) // sel=1
+      ,.i2({ width_p {shift_op} }) // sel var
+      ,.o (tag_data_n)
+      );
+
+
+   // Veri lator did not like bsg_dff_gatestack with the replicated clock signal
+   // hopefully this replacement does not cause inordinate problems =)
+   
+   bsg_dff #(.width_p(width_p), .harden_p(harden_p)) tag_data_reg
+	     (.clk_i(bsg_tag_i.clk)
+	      ,.data_i(tag_data_n)
+	      ,.data_o(tag_data_r)
+	      );
+	     
+/*	     
+   bsg_dff_gatestack #(.width_p(width_p),.harden_p(harden_p)) tag_data_reg
+     (
+      .i0 (tag_data_n                    )
+      ,.i1( { width_p { bsg_tag_i.clk } })
+      ,.o (tag_data_r                    )
+      );
+  */ 
+   
+
+`ifndef BSG_HIDE_FROM_SYNTHESIS
+   if (debug_level_lp > 1)
+     begin: debug
+	wire reset_op = ~op_r & param_r;
+	always @(negedge bsg_tag_i.clk)
+	  begin
+	     //if (reset_op)
+	     //  $display("## bsg_tag_client RESET HI (%m)");
+             if (reset_op & ~(~bsg_tag_i.op & bsg_tag_i.param))
+               $display("## bsg_tag_client RESET DEASSERTED time %t (%m)",$time);
+             if (~reset_op & (~bsg_tag_i.op & bsg_tag_i.param))
+               $display("## bsg_tag_client RESET ASSERTED time   %t  (%m)",$time);
+             if (shift_op)
+               $display("## bsg_tag_client (send) SHIFTING  %b (%m)",tag_data_r);
+	  end
+     end
+`endif
+
+   assign data_async_r_o = tag_data_r;
+
+endmodule
+
+`BSG_ABSTRACT_MODULE(bsg_tag_client_unsync)

snapshots/bespoke-silicon-group_basejump_stl_pr706/bsg_tag/bsg_tag_master.sv

@@ -0,0 +1,260 @@
+// bsg_tag_master
+//
+// 8/30/2016
+//
+// Usage: send a stream of 0's to reset master node and/or noop.
+// Then, send a single <1> followed by a packet:
+//        < id >       < data_not_reset > < payload length >             < payload >
+// ****************************************************************************
+// $clog2(els_p+1)      1        $clog2(max_payload_length+1)  (variable size)
+//
+// To reset client nodes, set data_not_reset to 0, and payload to 1's.
+//
+//
+
+`include "bsg_defines.sv"
+
+`include "bsg_tag.svh"
+
+// will not build in verilator without this
+// possibly resulting incorrect behavior :(
+
+// verilator lint_off BLKANDNBLK
+
+module bsg_tag_master
+  import bsg_tag_pkg::bsg_tag_s;
+
+   // els_p is the number of clients to attach
+   // lg_width_p is the number of bits used to describe the payload size
+   
+   #(parameter `BSG_INV_PARAM(els_p), `BSG_INV_PARAM(lg_width_p), debug_level_lp=2)
+   (
+    // from pins
+    input clk_i
+    ,input en_i
+    ,input data_i
+    , output bsg_tag_s [els_p-1:0] clients_r_o
+    );
+
+   `declare_bsg_tag_header_s(els_p,lg_width_p)
+
+   localparam max_packet_len_lp    = `bsg_tag_max_packet_len(els_p,lg_width_p);
+
+   localparam reset_len_lp = `bsg_tag_reset_len(els_p,lg_width_p);
+   
+   // counts 0..max_packet_len_lp
+   localparam lg_max_packet_len_lp = `BSG_SAFE_CLOG2(max_packet_len_lp+1);
+
+`ifndef BSG_HIDE_FROM_SYNTHESIS
+   if (debug_level_lp > 2)
+     always @(negedge clk_i)
+       $display("## bsg_tag_master clients=%b (%m)",clients_r_o);
+`endif
+
+   logic  data_i_r;
+
+   always @(posedge clk_i)
+     data_i_r <= data_i;
+
+   // ***************************
+   // RESET LOGIC
+   // extra bit to detect carry out in counter
+
+   localparam ctr_width_lp = lg_max_packet_len_lp+1;
+   logic [ctr_width_lp-1:0] zeros_ctr_r;
+
+
+   wire tag_reset_req = zeros_ctr_r[ctr_width_lp-1];
+
+   // this self-clearing counter detects a certain number
+   // of consecutive 0's
+   // indicating a tag_master reset condition
+   //
+
+   bsg_counter_clear_up #(.max_val_p((1 << ctr_width_lp)-1)
+                          ,.init_val_p(0)
+                          ) bccu
+   (.clk_i   (clk_i)
+    ,.reset_i(1'b0)
+    // we clear the counter if we hit the limit
+    ,.clear_i(data_i_r | tag_reset_req)
+    ,.up_i   (~data_i_r)
+    ,.count_o(zeros_ctr_r)
+    );
+
+   // veri lator doesn't support -d
+`ifndef BSG_HIDE_FROM_SYNTHESIS
+   initial
+        $display("## %m instantiating bsg_tag_master with els_p=%d, lg_width_p=%d, max_packet_len_lp=%d, reset_zero_len=%d"
+                 ,els_p,lg_width_p,max_packet_len_lp,reset_len_lp);
+`endif
+
+   //
+   // END RESET LOGIC
+   // ***************************
+
+   logic [lg_max_packet_len_lp-1:0] hdr_ptr_r, hdr_ptr_n;
+   bsg_tag_header_s hdr_r, hdr_n;
+
+   // sending
+   logic  v_n;
+   // value to send
+   bsg_tag_s bsg_tag_n;
+
+   typedef enum logic [1:0] {eStart, eHeader, eTransfer, eStuck} state_e;
+
+   state_e state_r, state_n;
+
+   // synopsys sync_set_reset "tag_reset_req, data_i_r"
+
+   always_ff @(posedge clk_i)
+     // if we hit the counter AND (subtle bug) there is no valid incoming data that would get lost
+     if (tag_reset_req & ~data_i_r)
+       begin
+`ifndef BSG_HIDE_FROM_SYNTHESIS
+          if (debug_level_lp > 2) $display("## bsg_tag_master RESET time %t (%m)",$time);
+`endif
+          state_r   <= eStart;
+
+          // we put this here because DC did not currently infer "reset" logic
+          hdr_ptr_r <= 0;
+       end
+     else
+       begin
+          state_r   <= state_n;
+          hdr_ptr_r <= hdr_ptr_n;
+       end
+
+   always_ff @(posedge clk_i)
+        hdr_r <= hdr_n;
+
+`ifndef BSG_HIDE_FROM_SYNTHESIS
+   always_ff @(negedge clk_i)
+     if (state_n != state_r)
+       if (debug_level_lp > 1) $display("## bsg_tag_master STATE CHANGE  # %s --> %s #",state_r.name(),state_n.name());
+`endif
+
+   always_comb
+     begin
+        state_n   = state_r;
+        hdr_ptr_n = hdr_ptr_r;
+        hdr_n     = hdr_r;
+
+        // outgoing
+        v_n             = 1'b0;
+        bsg_tag_n.op    = 1'b0;
+        bsg_tag_n.param = 1'b0;
+
+        case (state_r)
+          // first 1 after zero indicates beginning of packet
+          eStart:
+               begin
+                  if (data_i_r)
+                    state_n = eHeader;
+
+                  hdr_ptr_n = 0;
+                  hdr_n     = 0;
+               end
+          eHeader:
+               begin
+`ifndef BSG_HIDE_FROM_SYNTHESIS
+                  if (debug_level_lp > 1)
+                    $display("## bsg_tag_master RECEIVING HEADER (%m) (%d) = %b",hdr_ptr_r,data_i_r);
+`endif
+
+                  hdr_n     = { data_i_r, hdr_r[1+:($bits(bsg_tag_header_s)-1)] };
+                  hdr_ptr_n = hdr_ptr_r + 1'b1;
+                  // if we are at the next to last value
+                  if (hdr_ptr_r == lg_max_packet_len_lp'($bits(bsg_tag_header_s)-1))
+                    begin
+                       if (hdr_n.len == 0)
+                         begin
+                            state_n = eStart;
+`ifndef BSG_HIDE_FROM_SYNTHESIS
+                            $display("## bsg_tag_master NULL PACKET, len=0 (%m)");
+`endif
+                         end
+                       else
+                         begin
+
+`ifndef BSG_HIDE_FROM_SYNTHESIS
+                            if (debug_level_lp > 1)
+                              $display("## bsg_tag_master PACKET HEADER RECEIVED (length=%b,data_not_reset=%b,nodeID=%b) (%m) "
+                                       ,hdr_n.len,hdr_n.data_not_reset,hdr_n.nodeID);
+`endif
+
+                            // if we have data to transfer go to transfer state
+                            state_n = eTransfer;
+                         end
+                    end
+               end // case: eHeader
+          eTransfer:
+               begin
+                  // transmit data
+                  // if hdr_r.reset = 1, then we send <0,data> for hdr_r.len cycles
+                  // otherwise we send <1,data> for hdr_r.len cycles
+                  // typically for reset, we will send 1's.
+
+                  v_n             = 1'b1;
+                  bsg_tag_n.op    = hdr_r.data_not_reset;
+                  bsg_tag_n.param = data_i_r;
+
+`ifndef BSG_HIDE_FROM_SYNTHESIS
+                  if (debug_level_lp > 2)
+                    $display("## bsg_tag_master PACKET TRANSFER op,param=<%b,%b> (%m)", bsg_tag_n.op, bsg_tag_n.param);
+`endif
+
+                  // finishing words
+                  if (hdr_r.len== lg_width_p ' (1))
+                    begin
+                       state_n = eStart;
+
+`ifndef BSG_HIDE_FROM_SYNTHESIS
+                       if (debug_level_lp > 1) $display("## bsg_tag_master PACKET END (%m)");
+`endif
+
+                    end
+                  hdr_n.len = hdr_r.len - 1;
+               end
+          eStuck:
+            state_n = eStuck;
+
+            default:
+              begin
+                 state_n = eStuck;
+
+`ifndef BSG_HIDE_FROM_SYNTHESIS
+                 $display("## bsg_tag_master transitioning to error state; be sure to run gate-level netlist to avoid sim/synth mismatch (%m)");
+`endif
+
+              end
+        endcase // case (state_r)
+
+     end // always_comb
+
+   genvar i;
+
+   // demultiplex the stream to the target node
+
+   wire [els_p-1:0] clients_decode = (v_n << hdr_r.nodeID);
+
+
+   for (i = 0; i < els_p; i=i+1)
+     begin: rof
+        always_ff @(posedge clk_i)
+          begin
+             clients_r_o[i].op    <= clients_decode[i] & bsg_tag_n.op;
+             clients_r_o[i].param <= clients_decode[i] & bsg_tag_n.param;
+          end
+
+
+        assign clients_r_o[i].clk = clk_i;
+        assign clients_r_o[i].en  = en_i;
+     end
+
+   
+endmodule // bsg_tag_master
+
+`BSG_ABSTRACT_MODULE(bsg_tag_master)
+
+// verilator lint_on BLKANDNBLK

snapshots/bespoke-silicon-group_basejump_stl_pr706/bsg_tag/bsg_tag_master_decentralized.sv

@@ -0,0 +1,276 @@
+// bsg_tag_master
+//
+// 8/30/2016
+//
+// Usage: send a stream of 0's to reset master node and/or noop.
+// Then, send a single <1> followed by a packet:
+//        < id >       < data_not_reset > < payload length >             < payload >
+// ****************************************************************************
+// $clog2(els_p+1)      1        $clog2(max_payload_length+1)  (variable size)
+//
+// To reset client nodes, set data_not_reset to 0, and payload to 1's.
+//
+//
+
+`include "bsg_defines.sv"
+
+`include "bsg_tag.svh"
+
+// will not build in verilator without this
+// possibly resulting incorrect behavior :(
+
+// verilator lint_off BLKANDNBLK
+
+module bsg_tag_master_decentralized
+  import bsg_tag_pkg::bsg_tag_s;
+
+   // els_p is the maximum number of clients supported in system
+   // local_els_p is the number of clients to attach
+   // lg_width_p is the number of bits used to describe the payload size
+
+   #(`BSG_INV_PARAM(els_p)
+    ,`BSG_INV_PARAM(local_els_p)
+    ,`BSG_INV_PARAM(lg_width_p)
+    ,debug_level_lp=1
+    ,lg_els_lp=`BSG_SAFE_CLOG2(els_p)
+    ,lg_local_els_lp=`BSG_SAFE_CLOG2(local_els_p)
+    )
+
+   (
+    // from pins
+    input clk_i
+    ,input data_i
+    // node_id_offset_i is used to filter incoming packets.
+    // packets with nodeID < node_id_offset_i or nodeID >= node_id_offset_i+local_els_p
+    // will be ignored.
+    ,input [lg_els_lp-1:0] node_id_offset_i
+    ,output bsg_tag_s [local_els_p-1:0] clients_o
+    );
+
+   `declare_bsg_tag_header_s(els_p,lg_width_p)
+
+   localparam max_packet_len_lp    = `bsg_tag_max_packet_len(els_p,lg_width_p);
+
+   localparam reset_len_lp = `bsg_tag_reset_len(els_p,lg_width_p);
+   
+   // counts 0..max_packet_len_lp
+   localparam lg_max_packet_len_lp = `BSG_SAFE_CLOG2(max_packet_len_lp+1);
+
+`ifndef BSG_HIDE_FROM_SYNTHESIS
+   if (debug_level_lp > 2)
+     always @(negedge clk_i)
+       $display("## bsg_tag_master clients=%b (%m)",clients_o);
+`endif
+
+   logic  data_i_r;
+
+   always @(posedge clk_i)
+     data_i_r <= data_i;
+
+   // ***************************
+   // RESET LOGIC
+   // extra bit to detect carry out in counter
+
+   localparam ctr_width_lp = lg_max_packet_len_lp+1;
+   logic [ctr_width_lp-1:0] zeros_ctr_r;
+
+
+   wire tag_reset_req = zeros_ctr_r[ctr_width_lp-1];
+
+   // this self-clearing counter detects a certain number
+   // of consecutive 0's
+   // indicating a tag_master reset condition
+   //
+
+   bsg_counter_clear_up #(.max_val_p((1 << ctr_width_lp)-1)
+                          ,.init_val_p(0)
+                          ) bccu
+   (.clk_i   (clk_i)
+    ,.reset_i(1'b0)
+    // we clear the counter if we hit the limit
+    ,.clear_i(data_i_r | tag_reset_req)
+    ,.up_i   (~data_i_r)
+    ,.count_o(zeros_ctr_r)
+    );
+
+   // veri lator doesn't support -d
+`ifndef BSG_HIDE_FROM_SYNTHESIS
+   initial
+        $display("## %m instantiating bsg_tag_master_decentralized with els_p=%d, local_els_p=%d, lg_width_p=%d, max_packet_len_lp=%d, reset_zero_len=%d"
+                 ,els_p,local_els_p,lg_width_p,max_packet_len_lp,reset_len_lp);
+`endif
+
+   //
+   // END RESET LOGIC
+   // ***************************
+
+   logic [lg_max_packet_len_lp-1:0] hdr_ptr_r, hdr_ptr_n;
+   bsg_tag_header_s hdr_r, hdr_n;
+
+   // sending
+   logic  v_n;
+   // value to send
+   bsg_tag_s bsg_tag_n;
+
+   typedef enum logic [1:0] {eStart, eHeader, eTransfer, eStuck} state_e;
+
+   state_e state_r, state_n;
+
+   // synopsys sync_set_reset "tag_reset_req, data_i_r"
+
+   always_ff @(posedge clk_i)
+     // if we hit the counter AND (subtle bug) there is no valid incoming data that would get lost
+     if (tag_reset_req & ~data_i_r)
+       begin
+`ifndef BSG_HIDE_FROM_SYNTHESIS
+          if (debug_level_lp > 2) $display("## bsg_tag_master RESET time %t (%m)",$time);
+`endif
+          state_r   <= eStart;
+
+          // we put this here because DC did not currently infer "reset" logic
+          hdr_ptr_r <= 0;
+       end
+     else
+       begin
+          state_r   <= state_n;
+          hdr_ptr_r <= hdr_ptr_n;
+       end
+
+   always_ff @(posedge clk_i)
+        hdr_r <= hdr_n;
+
+`ifndef BSG_HIDE_FROM_SYNTHESIS
+   always_ff @(negedge clk_i)
+     if (state_n != state_r)
+       if (debug_level_lp > 1) $display("## bsg_tag_master STATE CHANGE  # %s --> %s #",state_r.name(),state_n.name());
+`endif
+
+   always_comb
+     begin
+        state_n   = state_r;
+        hdr_ptr_n = hdr_ptr_r;
+        hdr_n     = hdr_r;
+
+        // outgoing
+        v_n             = 1'b0;
+        bsg_tag_n.op    = 1'b0;
+        bsg_tag_n.param = 1'b0;
+
+        case (state_r)
+          // first 1 after zero indicates beginning of packet
+          eStart:
+               begin
+                  if (data_i_r)
+                    state_n = eHeader;
+
+                  hdr_ptr_n = 0;
+                  hdr_n     = 0;
+               end
+          eHeader:
+               begin
+`ifndef BSG_HIDE_FROM_SYNTHESIS
+                  if (debug_level_lp > 1)
+                    $display("## bsg_tag_master RECEIVING HEADER (%m) (%d) = %b",hdr_ptr_r,data_i_r);
+`endif
+
+                  hdr_n     = { data_i_r, hdr_r[1+:($bits(bsg_tag_header_s)-1)] };
+                  hdr_ptr_n = hdr_ptr_r + 1'b1;
+                  // if we are at the next to last value
+                  if (hdr_ptr_r == lg_max_packet_len_lp'($bits(bsg_tag_header_s)-1))
+                    begin
+                       if (hdr_n.len == 0)
+                         begin
+                            state_n = eStart;
+`ifndef BSG_HIDE_FROM_SYNTHESIS
+                            $display("## bsg_tag_master NULL PACKET, len=0 (%m)");
+`endif
+                         end
+                       else
+                         begin
+
+`ifndef BSG_HIDE_FROM_SYNTHESIS
+                            if (debug_level_lp > 1)
+                              $display("## bsg_tag_master PACKET HEADER RECEIVED (length=%b,data_not_reset=%b,nodeID=%b) (%m) "
+                                       ,hdr_n.len,hdr_n.data_not_reset,hdr_n.nodeID);
+`endif
+
+                            // if we have data to transfer go to transfer state
+                            state_n = eTransfer;
+                         end
+                    end
+               end // case: eHeader
+          eTransfer:
+               begin
+                  // transmit data
+                  // if hdr_r.reset = 1, then we send <0,data> for hdr_r.len cycles
+                  // otherwise we send <1,data> for hdr_r.len cycles
+                  // typically for reset, we will send 1's.
+
+                  v_n             = 1'b1;
+                  bsg_tag_n.op    = hdr_r.data_not_reset;
+                  bsg_tag_n.param = data_i_r;
+
+`ifndef BSG_HIDE_FROM_SYNTHESIS
+                  if (debug_level_lp > 2)
+                    $display("## bsg_tag_master PACKET TRANSFER op,param=<%b,%b> (%m)", bsg_tag_n.op, bsg_tag_n.param);
+`endif
+
+                  // finishing words
+                  if (hdr_r.len== lg_width_p ' (1))
+                    begin
+                       state_n = eStart;
+
+`ifndef BSG_HIDE_FROM_SYNTHESIS
+                       if (debug_level_lp > 1) $display("## bsg_tag_master PACKET END (%m)");
+`endif
+
+                    end
+                  hdr_n.len = hdr_r.len - 1;
+               end
+          eStuck:
+            state_n = eStuck;
+
+            default:
+              begin
+                 state_n = eStuck;
+
+`ifndef BSG_HIDE_FROM_SYNTHESIS
+                 $display("## bsg_tag_master transitioning to error state; be sure to run gate-level netlist to avoid sim/synth mismatch (%m)");
+`endif
+
+              end
+        endcase // case (state_r)
+
+     end // always_comb
+
+   genvar i;
+
+   // calculate local nodeID
+   // must have lg_els_lp bits to prevent overflow
+   // (underflow is okay in this case)
+   wire [lg_els_lp-1:0] local_node_id = hdr_r.nodeID - node_id_offset_i;
+
+   // demultiplex the stream to the target node
+   // use only lg_local_els_lp bits to simplify decoder logic
+   wire [local_els_p-1:0] clients_decode = (v_n << local_node_id[lg_local_els_lp-1:0]);
+
+   // determine if incoming packet is within the nodeID range
+   wire node_id_above_offset = (hdr_r.nodeID >= node_id_offset_i);
+   wire local_node_id_below_limit = (local_node_id < local_els_p);
+   wire node_id_match = (node_id_above_offset && local_node_id_below_limit);
+
+   // output to bsg_tag_clients directly without flops
+   for (i = 0; i < local_els_p; i=i+1)
+     begin: rof
+        assign clients_o[i].clk   = clk_i;
+        assign clients_o[i].op    = node_id_match & clients_decode[i] & bsg_tag_n.op;
+        assign clients_o[i].param = node_id_match & clients_decode[i] & bsg_tag_n.param;
+        assign clients_o[i].en    = 1'b1;
+     end
+
+   
+endmodule // bsg_tag_master
+
+`BSG_ABSTRACT_MODULE(bsg_tag_master_decentralized)
+
+// verilator lint_on BLKANDNBLK

snapshots/bespoke-silicon-group_basejump_stl_pr706/bsg_tag/bsg_tag_pkg.sv

@@ -0,0 +1,15 @@
+package bsg_tag_pkg;
+   typedef struct packed {
+      logic clk;
+                   //  op param
+      logic op;    //   1   D   shift D
+      logic param; //   0   0   nop (also "send", immediately after shift operation)
+                   //   0   1   reset
+
+      logic en;    // this signal disables thru-transmit of new values
+} bsg_tag_s;
+
+
+endpackage // bsg_tag_pkg
+
+