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issues/AsFigo_pyslint_pr166

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+# VLT: no clocking blocks in interface
+
+- Source URL: https://github.com/AsFigo/pyslint/issues/165
+
+Verilator does not support clocking block based driving (as of today). Add a rule to check.
+
+## PR Content from GitHub
+
+# PR Summary
+
+**PR Title:** Added rule for CB check for Verilator issue 165
+
+**PR Number:** #166
+
+**Status:** Merged
+
+**Author:** svenka3
+
+**Merge Date:** December 6, 2023
+
+---
+
+## PR Description Body
+
+The PR description was not fully visible in the provided content. Only a reference appears:
+
+**Comment by svenka3:**
+"Fixes #165"
+
+---
+
+## Linked Issue
+
+**Issue #165 Title:** VLT: no clocking blocks in interface
+
+The issue details were not included in the available content, but the PR was designed to address this specific Verilator-related constraint.
+
+---
+
+## Additional Context
+
+The pull request contained 1 commit (ea905ff) that was merged into the main branch. The change implements a rule to check for clocking blocks within interfaces, addressing a Verilator linting requirement.

issues/FPGA-MAFIA_fpga_mafia_pr451

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+# Remove the Parameter override from the build.
+
+- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/441
+
+https://github.com/FPGA-MAFIA/fpga_mafia/blob/931deaa13c92a1fe5d29dee95ba23c76531a68f2/build.py#L241C16-L241C16
+
+I think there is room for creating a script that can override the parameter value by name - both in source (AKA rtl) and in verif
+
+The way it should work is as following:
+In the cfg file add a field that is called "parameter_override"
+``` json
+{
+    "I_MEM_OFFSET": 0,
+    "I_MEM_LENGTH": 65536,
+    "D_MEM_OFFSET": 65536,
+    "D_MEM_LENGTH": 61440,
+    "crt0_file"   : "crt0_mini_rv32e.S",
+    "rv32_gcc"    : "rv32e -mabi=ilp32e",
+    "name"        : "rv32e",
+    "rtl_parameter_override"  : {
+        "RF_NUM_MSB"  : 31,
+        "RF_NUM_LSB"  : 0,
+        "OTHER_EXAMPLE" : 31
+    },
+    "verif_pkg_parameter_override"  : {
+        "TIMEOUT" : 1000000,
+        "OTHER_EXAMPLE" : 65403540
+    }
+}
+```
+
+Then in the "build" call a new script that you need to create that accepts the list of parameters you need to change.
+Make sure use correct regular expression so it overrides only the "parameter <name> = value" instances
+
+The scipt will search, find and replace the values that are mentioned in the cfg json file.
+The scipt will also log the info by printing to the screen what he found, where, and what he has changed.
+
+During the find replace - add a comment in the line of parameter
+Example:
+```systemverilog
+parameter EXAMPLE = 15; // Note: This line was inserted using parameter override script
+```
+
+*Note:*
+This Parameter change will actually change the value of the RTL!! 
+This is fine - as long as we test correctly the different parameter variations in the workflow.
+
+This is not the best solution because this may cause many redundant commit changes in the git. (the Change in Value is tracked in the git add/commit flow)
+But i think for us - this is a good solution.
+(We are not really expected to manually change the RTL parameters very often. but we want to make sure they are correct)
+
+
+I will note that the alternative is override the parameter value in the command line (simular to what i just added) but i have some trouble with overriding specific values in the param_pkg.
+Another good alternative is to pass the parameter in the instance of each module -> but this also can get annoying. 
+I think will need to this to the most common parameter overrides so we can simply intergrade different version of the same module in the same system. (similar to what we did with the RF_NUM_MSB which is getting override in the module instance)
+
+I think you can do this fairly simple
+Let me know if you have any questions

issues/FPGA-MAFIA_fpga_mafia_pr655

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+# Cache - support partiol read/write (byte enable)
+
+- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/583
+
+Cache - support partial read/write (byte enable)
+LHU, LBU, LW,LH,LB SW,SH,SB
+Also, support signed and unsigned extends for the memory load request.
+
+PR Title: modify chach_tasks.vh to support random partial reads and writes
+PR Number: #655
+Status: Merged
+Repository: FPGA-MAFIA/fpga_mafia
+
+Description:
+No formal description was provided by the author.
+
+Comments:
+amichai-bd (May 28, 2024):
+"Small refactor into a single 'Case'"
+The reviewer noted a code consolidation effort with an accompanying image reference.
+
+amichai-bd (May 28, 2024):
+"I will also note that the verification env for this Cache is not really good.. It takes a long time to build and simulate - i suspect its due to something wring we did here.. Also a lot of code is duplicated - we should be able to use parameters to have different flavors of similar tasks."
+The reviewer raised concerns about verification environment performance and code duplication, suggesting future refactoring opportunities.
+
+Linked Issue:
+#583 - "Cache - support partiol read/write (byte enable)" (Closed by this PR)
+
+Commits Overview:
+13 commits were merged, including initial test additions, byte offset support for D_CACHE, partial read/write handling, and byte enable offset fixes across fill requests.

issues/HiSA-Team_Simply-V_pr102

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+# [bugfix/sync_pbus_interrupts] Add synchronizers for PBUS interrupts
+
+- Source URL: https://github.com/HiSA-Team/Simply-V/issues/101
+
+## Issue Title
+[bugfix/sync_pbus_interrupts] Add synchronizers for PBUS interrupts
+
+## Issue Description
+During CDC (#91) we forgot to re-synchronize PBUS outgoing interrupts to the MAIN_CLOCK_DOMAIN.
+
+This could be fixed by adding a NUM_IRQ-wide xpm_cdc_async_rst in pbus between int_o and each peripheral interrupt, instead of just assigning them as in the prior implementation.
+
+Additionally, here we could also fix unassigned int_o bits.
+
+## Issue Comments
+None visible.
+
+## Issue Metadata
+- Status: Closed (via PR #102)
+- Assignee: DOTTORM5
+- Milestone: MCU release
+- Author: MaistoV
+- Date Opened: April 8, 2025
+
+## Linked Issues / PRs
+- PR #102 — fix
+- Refers back to #91 (prior CDC work)

issues/HiSA-Team_Simply-V_pr166

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+# [feature/rvv/ara] Integrate PULP Ara for RVV support
+
+- Source URL: https://github.com/HiSA-Team/Simply-V/issues/119
+
+## Issue Title
+[feature/rvv/ara] Integrate PULP Ara for RVV support
+
+## Issue Description
+- Need finalized CVA6 support
+- Integrate CVA6 + Ara as a single custom IP (different than standalone cv64a6)
+- Use Ara 2-lanes, matching CVA6 data width, e.g. 64-bits
+
+TODO (move to another issue):
+- Ara 4- and 8-lanes: Attach Ara AXI master to HBUS
+
+## Issue Comments
+None visible.
+
+## Issue Metadata
+- Status: Closed (with associated PR #166)
+- Assignee: MaistoV
+
+## Linked Issues / PRs
+- PR #166 — addresses this feature request

issues/MiSTer-devel_Saturn_MiSTer_pr249

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+# [FEATURE REQUEST] (Shuttle) Mouse support
+
+- Source URL: https://github.com/MiSTer-devel/Saturn_MiSTer/issues/146
+
+Some users have asked on the Discord if it would be possible to support the Shuttle mouse (or even just a more basic mouse) on the core in the future.
+
+---
+
+## Pull Request
+
+**PR Title:** Shuttle mouse support
+
+**PR Number:** #249
+
+**Status:** Merged
+
+**Merged by:** srg320 on Sep 18, 2024
+
+### Description
+
+The pull request implements mouse support for Saturn games. Key features include:
+
+- Maps USB mice to player 1/player 2 Saturn Shuttle mouse functionality
+- Fixes joypad analog stick behavior when used as a mouse
+- Enables input merging between USB mouse and joypad, allowing seamless switching during gameplay
+- Maps left/middle/right USB mouse buttons to corresponding Shuttle Mouse buttons
+- Routes additional USB mouse buttons (side buttons, etc.) to function as the 4th button/Start
+- Scales joypad analog sensitivity to 37.5% to prevent oversensitivity
+
+This addresses issue #146, a feature request for Shuttle Mouse support.
+
+### Comments
+
+**Zet-sensei** (Sep 17, 2024): Confirmed working functionality across multiple titles including Virtua Cop series, Tokimeki Memorial, Sakura Taisen series, Dokyuusei variants, and Policenauts.
+
+**rattboi** (Sep 18, 2024): Provided compiled RBF file link for easy access.
+
+### Linked Issue
+
+**#146:** "[FEATURE REQUEST] (Shuttle) Mouse support" — Successfully closed by this merge.

issues/MiSTer-devel_ao486_MiSTer_pr172

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+# BOOM and Allegro freeze
+
+- Source URL: https://github.com/MiSTer-devel/ao486_MiSTer/issues/128
+
+Tested in working DOS 6.22 and FreeDOS environments. All versions of BOOM and Allegro (ASETUP, the setup EXE) freeze when I try to run them. It locks at a blinking cursor, I've waited for 10 minutes or so.
+
+(DOOM and DOOM2 all work in FreeDOS just fine.)
+
+This is the version that comes packaged with other versions of FreeDOS, plus I have tried the classic version of BOOM available online.
+
+## Fetched Issue/PR Details
+
+Title: BOOM and Allegro freeze (#128)
+
+Description: The reporter tested BOOM and Allegro (including the ASETUP setup executable) in working DOS 6.22 and FreeDOS environments. When attempting to run these applications, they "freeze when I try to run them. It locks at a blinking cursor, I've waited for 10 minutes or so." The user notes that DOOM and DOOM2 work fine in FreeDOS. They tested both the version packaged with FreeDOS and the classic BOOM version available online, with the same freezing behavior occurring.
+
+Status: Closed (linked to PR #172)
+
+Comments: None visible on the page.
+
+Linked Issues: Resolving PR #172.

issues/MiSTle-Dev_MiSTeryNano_pr99

@@ -0,0 +1,46 @@
+# Does second hid joystick work?
+
+- Source URL: https://github.com/MiSTle-Dev/MiSTeryNano/issues/97
+
+I've connected two USB gamepads via raspberry pico and I see in logs JOY0 and JOY1 that send command to FPGA, but when I wanted to test two joysticks in a game. Second one never works, so I tried to understand if second joystick port is supported on FPGA, so started reading Verilog (I'm beginner) and I found in misterynano.sv this:
+
+        .joystick0(hid_joy),
+        .joystick1()
+
+Does it means that joystick1 (second joy) is not wired to hid data, which means second joy is not implemented?
+
+If my analysis is correct, do you plan to implement second hid joy support?
+
+---
+
+## Pull Request
+
+**PR Title:** Add support for second usb joy and auto switch between joystick and mouse #99
+
+**PR Number:** #99
+
+**Status:** Merged
+
+### Description
+
+The contributor's opening statement explains: "Please find changes adding support for second HID joystick. I also added possibility in menu to switch between mapping HID joy to ports."
+
+The implementation addresses several goals:
+
+1. **Dual joystick support** – Enables configuration where a DB9 joystick operates on port 2 while an HID joystick functions on port 1, allowing two-player gameplay.
+
+2. **Input switching mechanism** – Since joystick and mouse cannot operate simultaneously on port 1, the solution activates either device when its button is pressed, disabling the alternate input method.
+
+3. **Testing validation** – The author confirmed functionality "works great and tested on Bubble bobble."
+
+### Comments
+
+**harbaum (Collaborator)** merged the PR and noted: "Again, thanks a lot. And yes, switching between mouse and joystick via the buttons is how those auto-switchers back in the day also worked."
+
+**pawelka (Author)** responded: "I haven't know that there where any auto switchers in a past, I switched manually in my Atari."
+
+**harbaum** later added: "A fixed a small issue where the register with was 2 bit instead of 1."
+
+### Linked Issue
+
+This PR closes **Issue #97:** "Does second hid joystick work?"

issues/Panda-Cores_PandaZero_pr7

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+# Dbg module
+
+Instance: Panda-Cores_PandaZero_pr7
+Source: https://github.com/Panda-Cores/PandaZero/pull/7
+Fetched: 2026-05-03
+Repository: Panda-Cores/PandaZero
+Pull request: #7
+Author: GorgeousWalrus
+State: closed
+Base branch: master
+Head branch: dbg_module
+Created: 2020-08-02
+Updated: 2020-08-02
+Closed: 2020-08-02
+Merged: 2020-08-02
+
+## PR Title
+Dbg module
+
+## PR Description
+Debug module improved, wishbone on newest state.
+
+## PR Comments
+
+**GorgeousWalrus** (Aug 2, 2020):
+"Debug module improved, wishbone on newest state"
+
+## Linked Issues
+
+**Issue #5: Upgrade Wishbone**
+common repo has new wishbone interfaces, upgrade time!
+
+**Issue #6: upgrade debug module**
+(Closed by this PR; body not available.)

issues/SpiNNakerManchester_spif_pr8

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+# SpiNNaker peripheral output support
+
+- Source URL: https://github.com/SpiNNakerManchester/spif/issues/4
+
+spif does __not__ currently support SpiNNaker peripheral output.
+
+Some of the hardware is already in place:
+
+- The SpiNNaker FPGAs __do__ support peripheral output. The routing is done using peripheral routing key and mask registers.
+
+- spif demultiplexes SpiNNaker packets into _configuration_ and _peripheral_ streams. Configuration packets are handled by the spif register bank while peripheral packets are simply dumped.
+
+
+**Where should peripheral output be sent to?**
+
+The best option seems to be to send them over Ethernet to a peripheral device at a specified IP address/UDP port. There should be registers to hold these values. These registers should be accessible from SpiNNaker and should also be accessible from the peripheral. SpiNNaker should use the existing spif configuration route. Peripheral devices should send a UDP frame to spif directed at a known UDP port and spif will write the sender IP address and UDP port into these registers.
+
+
+**When should peripheral output be sent?**
+
+A UDP frame sholud be triggered when one of two conditions arises:
+1. the memory buffer holding events fills above a high watermark,
+2. a periodic timer triggers. The timer period should be configurable through a spif register. A default of 2ms seems adequate.
+
+
+**SpiNNaker packet to peripheral event mapping**
+
+It is not clear how spif should map SpiNNaker packet MC keys into peripheral events. Events may even need some form of data value that is carried as SpiNNaker packet payload. Simply reversing the input mapping does __not__ appear to be a good solution.
+
+
+**spif output pipeline microarchitecture**
+
+- spif HW should receive SpiNNaker packets, map them to peripheral events and store them in a memory buffer previously reserved for this purpose by the spif kernel module. The kernel module currently reserves memory for peripheral input only.
+
+- spif HW should interrupt spif SW when a UDP frame should be triggered, _i.e._, when one of the conditions listed above is met.
+
+- when interrupted, spif SW reads peripheral events from the memory buffer and sends them over Ethernet to the registered IP address and UDP port. It may need to send several UDP frames if the number of events exceeds the frame maximum size.
+
+- spif SW for peripheral output could be incorporated into spiffer as an additional thread.

issues/StanfordVLSI_dragonphy2_pr141

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+# Remove combo logic loop in qr_4t1_mux_top
+
+- Source URL: https://github.com/StanfordVLSI/dragonphy2/issues/140
+
+There is currently a combo logic loop in ``qr_4t1_mux_top``, where ``data`` appears on both the ``RHS`` and ``LHS`` of an ``assign`` statement:
+https://github.com/StanfordVLSI/dragonphy2/blob/1f1c97ba5f52445fe06aa39ac60585e053916806/vlog/chip_src/tx_16t1/qr_4t1_mux_top.sv#L47
+
+I believe this was added to prevent glitches if clocks are non-overlapping, but there may be other ways to deal with this, for example given the 4-bit select signal ``{Q, I, QB, IB}``:
+* ``4'b1100`` or ``4'b0100``: choose ``D1MQ``
+* ``4'b0110`` or ``4'b0010``: choose ``D1MI``
+* ``4'b0011`` or ``4'b0001``: choose ``D2MQB``
+* ``4'b1001`` or ``4'b1000``: choose ``D2MIB``
+
+However, because this is such a critical block, it would be helpful to think about what the intended digital circuit is, so that we can make sure that is what will be produced by the Verilog.
+
+PR title: Combinational loop removed
+
+Source: https://github.com/StanfordVLSI/dragonphy2/pull/141
+
+PR description:
+No description was provided by the pull request author.
+
+Comments:
+- CansWang (October 27, 2020): No additional context provided beyond the PR title.
+- sgherbst (October 28, 2020): "just noticed that the branch was out-of-date so I updated it. If the tests are still passing (will find out in ~1hr), then I'll merge the changes."
+- sgherbst (Approval, October 28, 2020): "LGTM, thanks!"
+
+Linked issue:
+- #140 "Remove combo logic loop in qr_4t1_mux_top"
+
+Key details:
+- Status: Merged
+- Merge date: October 28, 2020
+- Commits: 2 commits merged
+- Reviewers: sgherbst (approved)
+- Participants: CansWang, sgherbst

issues/UTOSS_risc-v_pr107

@@ -0,0 +1,35 @@
+# Set up basic execution environment for running on DE1-SoC
+
+Instance: UTOSS_risc-v_pr107
+Source: https://github.com/UTOSS/risc-v/pull/107
+Fetched: 2026-05-03
+Repository: UTOSS/risc-v
+Pull request: #107
+Author: TheDeepestSpace
+State: closed
+Base branch: main
+Head branch: boris/basic-execution-environment
+Created: 2025-10-31
+Updated: 2025-11-30
+Closed: 2025-11-30
+Merged: 2025-11-30
+
+## PR Title
+Set up basic execution environment for running on DE1-SoC
+
+## PR Description
+Addresses issues #103 and #104 by establishing two separate execution environments for the project: one for simulation (used by testbenches and RISCOF) and one for the DE1-SoC FPGA deployment target. The core architectural change is extracting the memory (MA) out of the processor core, treating it as a peripheral rather than an internal component. The PR also lays down a basic memory map for the DE1-SoC platform with LEDR MMIO, demonstrating buildable and loadable code as a proof-of-concept. Memory currently infers as general logic; future work targets on-chip SRAM. Pending follow-ups: documentation for building/running on DE1-SoC and overall README/repository organization.
+
+## PR Comments
+**TheDeepestSpace** (Oct 31, 2025): Initial submission with the description above. Multiple loading errors prevented some early comments from rendering when the page was fetched.
+
+**TheDeepestSpace** (Oct 31, 2025, code review): On the memory-map implementation - "This line breaks the RAM inference when Quartus is synthesizing." Recommended a more advanced memory map with a separated canonical RAM module in a follow-up issue.
+
+**TheDeepestSpace** (Nov 25, 2025): "note to self: need to figure out whats up with the ugly stack trace in the silently failing riscof task"
+
+The PR contains 32 commits and modifies multiple environment-configuration and source files.
+
+## Linked Issues
+- **Issue #103 - "Set up Quartus project"** (closed by this PR)
+  Body: "Use Quartus ecosystem to set up a basic project that will compile top module for deployment onto DE1-SoC. Fix any issues stoping synthesis from succeeding."
+- **Issue #104 - "Set up execution environment with basic peripheral"** (also closed by this PR; body not fetched).

issues/UTOSS_risc-v_pr59

@@ -0,0 +1,41 @@
+# lui tb and auipc tb and related FSM changes
+
+Instance: UTOSS_risc-v_pr59
+Source: https://github.com/UTOSS/risc-v/pull/59
+Fetched: 2026-05-03
+Repository: UTOSS/risc-v
+Pull request: #59
+Author: houjingl
+State: closed
+Base branch: main
+Head branch: JerryHou/lui
+Created: 2025-09-06
+Updated: 2025-09-07
+Closed: 2025-09-07
+Merged: 2025-09-07
+
+## PR Title
+lui tb and auipc tb and related FSM changes
+
+## PR Description
+The PR introduces testbenches for the `lui` and `auipc` instructions, alongside modifications to the finite state machine, the instruction decoder, and the datapath needed to support these new instructions.
+
+## PR Comments
+**houjingl** (Sep 6, 2025): "Added tb for lui and auipc instructions. Modified the FSM, instruction decoder and datapath to adapt new instructions"
+
+**TheDeepestSpace** (Sep 6, 2025): Questioned whether the new instructions should route through the EXECUTEI state for potential pipelining benefits, noting an original similar approach was taken.
+
+16 commits in total covered testbench additions, FSM parameter updates, instruction-decoder modifications, and various bug fixes and naming corrections.
+
+## Linked Issues
+**Issue #45 - "Implement starter-pack instructions for RISCOF framework"** (this PR contributes `lui` and `auipc`).
+
+Issue body (verbatim from the source URL):
+"We need a couple of instructions before we can run the RISCOF arch-test quite, specifically:
+
+- [x] `addi` @DanielTaoHuang123 (#50)
+- [x] `auipc` @DanielTaoHuang123 / @houjingl (#59)
+- [x] `lui`  @houjingl / @TheDeepestSpace (#56, #59)
+- [x] `srli` @MM871 / @DanielTaoHuang123 (#54)
+- [x] `nop` @MM871 / @TheDeepestSpace / @joon2022park (#63)
+- [x] `or` @TheDeepestSpace  (#48)"

issues/UTOSS_risc-v_pr80

@@ -0,0 +1,37 @@
+# Fix some test cases of lb, lbu, lh, lhu
+
+Instance: UTOSS_risc-v_pr80
+Source: https://github.com/UTOSS/risc-v/pull/80
+Fetched: 2026-05-03
+Repository: UTOSS/risc-v
+Pull request: #80
+Author: Invisipac
+State: closed
+Base branch: main
+Head branch: load-fixes
+Created: 2025-10-19
+Updated: 2025-10-26
+Closed: 2025-10-26
+Merged: 2025-10-26
+
+## PR Title
+Fix some test cases of lb, lbu, lh, lhu
+
+## PR Description
+No description provided. Across 5 commits this PR adds explicit `funct3` cases in `top` for the byte/half-word load instructions and corrects the data path so that `lb`, `lbu`, `lh`, and `lhu` produce the expected results.
+
+## PR Comments
+No conversation comments were posted on the PR. Commits:
+1. "fix a few of the test cases for the load instructions by adding cases for funct3 in top" (6c33fa5)
+2. "add some comments for funct3" (816b7f7)
+3. "made all load commands work" (8b318ef)
+4. "add some comments" (3d01d6b)
+5. "fixed small typo" (7c697bf)
+
+Participants: Invisipac (author), DanielTaoHuang123 (reviewer/merger).
+
+## Linked Issues
+**Issue #71 - "Review RISCOF's `RV32I` failures"** (this PR contributes load-instruction fixes).
+
+Issue body (verbatim from the source URL):
+"Review latest RISCOF report (see artifacts of `main` branch's CI run) and fix issues individually as you find them."

issues/UTOSS_risc-v_pr81

@@ -0,0 +1,36 @@
+# Fix testcases for sb, sh
+
+Instance: UTOSS_risc-v_pr81
+Source: https://github.com/UTOSS/risc-v/pull/81
+Fetched: 2026-05-03
+Repository: UTOSS/risc-v
+Pull request: #81
+Author: DanielTaoHuang123
+State: closed
+Base branch: main
+Head branch: daniel-sb-sh-fix
+Created: 2025-10-26
+Updated: 2025-11-03
+Closed: 2025-11-03
+Merged: 2025-11-03
+
+## PR Title
+Fix testcases for sb, sh
+
+## PR Description
+"change the WE in MA from 1 bit to 4 bits to support byte level write; change the WE of FSM accordingly; fix sb and sh (fix WD)"
+
+This is the follow-up to PR #80 (which fixed `lb`/`lh`/`lhu`). The Memory-Access Write Enable signal is widened from 1 bit to 4 bits to support byte-granularity writes; the FSM is updated accordingly; the `sb` and `sh` store instructions are corrected (including the write-data path). The MemoryLoader module is also enhanced to prepare data for storing into memory, where dataB is the raw word from the CPU and `__tmp_MemData` together with `MemWriteByteAddress` selects which byte to write.
+
+## PR Comments
+**TheDeepestSpace** (Nov 2, 2025): Clarified the architectural intent: "MemoryLoader now also prepares the data for storing it into memory...dataB is essentially the raw word from the CPU to write to memory, and `__tmp_MemData` together with `MemWriteByteAddress` tell us exactly which byte to write."
+
+**DanielTaoHuang123** (Nov 9, 2025): "yes" (confirming the explanation).
+
+Merged by TheDeepestSpace on Nov 3, 2025.
+
+## Linked Issues
+**Issue #71 - "Review RISCOF's `RV32I` failures"** (this PR fixes the `sb`/`sh` failures).
+
+Issue body (verbatim from the source URL):
+"Review latest RISCOF report (see artifacts of `main` branch's CI run) and fix issues individually as you find them."

issues/UTOSS_risc-v_pr85

@@ -0,0 +1,30 @@
+# Add jalr feature, fix tb issues and add more tb for jal and jalr
+
+Instance: UTOSS_risc-v_pr85
+Source: https://github.com/UTOSS/risc-v/pull/85
+Fetched: 2026-05-03
+Repository: UTOSS/risc-v
+Pull request: #85
+Author: RunzeZhu28
+State: closed
+Base branch: main
+Head branch: tony_jalr
+Created: 2025-10-27
+Updated: 2025-10-28
+Closed: 2025-10-28
+Merged: 2025-10-28
+
+## PR Title
+Add jalr feature, fix tb issues and add more tb for jal and jalr
+
+## PR Description
+No description was provided. The PR adds support for `jalr`, fixes existing testbench issues, and expands tests for both `jal` and `jalr`. Two commits: 9828b2f and 5fef62b.
+
+## PR Comments
+**TheDeepestSpace** (Oct 28, 2025): Suggested minimising FSM states to reduce flip-flops. Noted that `JALR_CALC` duplicates `MEMADR` functionality and recommended renaming `JALR_STEP2` to `JALRWB` for consistency. Approved with "Looks great, thanks Tony!"
+
+## Linked Issues
+**Issue #71 - "Review RISCOF's `RV32I` failures"** (this PR contributes `jal`/`jalr` fixes).
+
+Issue body (verbatim from the source URL):
+"Review latest RISCOF report (see artifacts of `main` branch's CI run) and fix issues individually as you find them."

issues/YosysHQ_picorv32_pr9

@@ -0,0 +1,40 @@
+# Deassert pcpi_valid upon asserting sbreak IRQ
+
+Instance: YosysHQ_picorv32_pr9
+Source: https://github.com/YosysHQ/picorv32/pull/9
+Fetched: 2026-05-03
+Repository: YosysHQ/picorv32
+Pull request: #9
+Author: stevekerrison
+State: closed
+Base branch: master
+Head branch: master (stevekerrison/picorv32 fork)
+Created: 2016-05-31
+Updated: 2016-06-01
+Closed: 2016-06-01
+Merged: 2016-06-01
+
+## PR Title
+Deassert pcpi_valid upon asserting sbreak IRQ
+
+## PR Description
+Addresses issue #8 (incorrect handling of SBREAK / illegal instructions when PCPI is enabled): on `sbreak` / illegal instruction the core now deasserts `pcpi_valid` when raising the SBREAK IRQ, so the next valid PCPI instruction is not mis-flagged as another `sbreak`.
+
+The author notes two remaining considerations:
+1. Instructions like `sbreak` take roughly 16 cycles to trigger an IRQ because of PCPI timeout delays; immediate IRQ triggering for these instructions could be useful, though external PCPI modules might handle it differently.
+2. The behaviour of `sbreak` or illegal instructions inside ISRs is not examined here, although trapping seems like the natural answer.
+
+## PR Comments
+**stevekerrison** (May 31, 2016): "This fixes #8" along with the two unresolved follow-up considerations described above.
+
+The PR was merged on Jun 1, 2016.
+
+## Linked Issues
+**Issue #8 - "Incorrect handling of SBREAK/ILLNSN with PCPI"** (closed by this PR).
+
+Issue body (verbatim from the source URL):
+"I'm trying to put a minimal example of this together (or a patch if I get there quicker), but won't get a chance until tomorrow. I leave this here for now as a test of my own sanity.
+
+If PCPI is enabled and an illegal instruction or `sbreak` occur, upon `retirq`, the signal `pcpi_valid` remains asserted. The eventual effect of this is that when the next valid PCPI instruction comes along, it causes another `SBREAK` IRQ to occur, presumably because the PCPI timeout never got reset.
+
+I actually want to handle `ecall`, and I guess I could do it with another PCPI extension, but that seems like a less graceful solution."

issues/aolofsson_oh_pr110

@@ -0,0 +1,19 @@
+# Add "tech config" pass-through for technology-specific GPIO configuration
+
+Instance: aolofsson_oh_pr110
+Source: https://github.com/aolofsson/oh/pull/110
+Fetched: 2026-04-26
+Repository: aolofsson/oh
+Pull request: #110
+Author: nmoroze
+State: closed
+Base branch: master
+Head branch: master
+Created: 2021-08-10T14:36:30Z
+Updated: 2021-08-16T02:49:10Z
+Closed: 2021-08-16T02:49:10Z
+Merged: 2021-08-16T02:49:10Z
+
+Sorry for the large diff, oh_padring.v had something going on with a mix of tabs and spaces that was screwing up my editor, so I fixed that up. 
+
+Also, I'm not 100% sold on the name tech_cfg, so happy to take suggestions there.

issues/aolofsson_oh_pr58

@@ -0,0 +1,38 @@
+# Initial Commit of 8b10b Encoder and Decoder
+
+Instance: aolofsson_oh_pr58
+Source: https://github.com/aolofsson/oh/pull/58
+Fetched: 2026-04-26
+Repository: aolofsson/oh
+Pull request: #58
+Author: prasadp4009
+State: closed
+Base branch: master
+Head branch: master
+Created: 2016-03-25T23:08:19Z
+Updated: 2016-03-25T23:19:44Z
+Closed: 2016-03-25T23:19:44Z
+Merged: 2016-03-25T23:19:44Z
+
+## PR Title
+Initial Commit of 8b10b Encoder and Decoder
+
+## PR Description
+Signed-off-by: Prasad Pandit <prasadp4009@gmail.com>
+
+## PR Comments
+
+**prasadp4009** (Mar 25, 2016):
+"Both 8b10b Encoder and Decoder use K-map optimized logic. Further improvements are on way with pipeline to improve performance. Current synthesis report explains the both modules perform at 385MHz on Virtex II. Suggestions and improvements are welcome."
+
+**aolofsson** (Mar 25, 2016):
+"Awesome!"
+
+## Merge Information
+- Merged by: aolofsson
+- Merge commit: 0142315
+- Source branch: prasadp4009:master
+- Target branch: aolofsson:master
+
+## Linked Issues
+None identified in the pull request content.

issues/apfaudio_eurorack-pmod_pr36

@@ -0,0 +1,25 @@
+# VCO example seems broken after clocking rewrite
+
+All the examples seem to work fine after switching to 48kHz all round and rewriting the clocking architecture -- except for the VCO example. It smells like a timing issue and this deserves investigation.
+
+- Actually this example still seems to work on the ECP5, it's only broken on ICE40
+
+## PR Content from GitHub
+
+# Pull Request #36: cores/vco - Fix and Modularize VCO Example
+
+## PR Title
+"cores/vco: fix and modularize vco example"
+
+## PR Description
+The PR description is not fully visible in the provided content, but the PR appears to address issues with the VCO (Voltage Controlled Oscillator) example implementation.
+
+## Comments
+**vk2seb** (Sep 17, 2023):
+"Seems to fix #35"
+
+## Linked Issue
+**Issue #35 Title:** "VCO example seems broken after clocking rewrite"
+
+## Status
+The pull request was merged on September 17, 2023. However, it was subsequently reverted on September 19, 2023 (commit 7a3af8c) due to place-and-route dependency issues on the icebreaker platform. The changes were later reapplied in October 2023 (commits 20a6b1e and d497970).

issues/bensampson5_libsv_pr109

@@ -0,0 +1,57 @@
+# 8b/10b decoder improvements
+
+- Source URL: https://github.com/bensampson5/libsv/issues/107
+
+Feature list
+- Add input clock, reset, and move running disparity to an internal calculation
+- Add enable input ``i_en``
+- Register outputs
+
+Additional TODO
+- Fix testbench
+- Update docs for 8b10b decoder (take a look at 8b10b encoder)
+
+## PR Content from GitHub
+
+# PR Summary: 8b/10b Decoder Improvements
+
+**PR Title:** 8b/10b decoder improvements #109
+
+**Status:** Merged (November 28, 2021)
+
+---
+
+## PR Description
+
+This pull request addresses issue #107 and implements several enhancements to the 8b/10b decoder module:
+
+**Features Added:**
+- Input clock, reset signals, with running disparity moved to internal calculation
+- Enable input (`i_en`)
+- Registered outputs
+
+**Pending Tasks:**
+- Fix testbench
+- Update documentation (referencing the 8b10b encoder documentation as a model)
+
+---
+
+## PR Activity Timeline
+
+**Commits:** 4 commits were merged
+- Implementation of new 8b/10b decoder features
+- Format fixes
+- Linting corrections
+- Documentation updates
+
+**Labels:** enhancement (New feature or request)
+
+**Assignee:** bensampson5 (repository owner)
+
+**Linked Issue:** Successfully closes issue #107 regarding 8b/10b decoder improvements
+
+---
+
+## Discussion
+
+The PR shows standard GitHub workflow activity with commit additions, label application, and self-assignment by the author. No reviewer comments or additional discussion beyond the initial feature list was documented.

issues/bespoke-silicon-group_basejump_stl_pr392

@@ -0,0 +1,21 @@
+# [bsg_tag_client] is widht_p=1 supported?
+
+https://github.com/bespoke-silicon-group/basejump_stl/blob/1862705e8bbb59c84dc9d942a8b1b31874f60406/bsg_tag/bsg_tag_client.v#L94
+
+when width_p=1,
+```
+
+Error-[IRIPS] Illegal range in part select
+/mnt/users/ssd1/homes/dcjung/bsg/basejump_stl/bsg_tag/bsg_tag_client.v, 94
+  The range of the part select is illegal:
+  tag_data_r[(width_p - 1):1]
+
+
+Lint-[CAWM-L] Width mismatch
+/mnt/users/ssd1/homes/dcjung/bsg/basejump_stl/bsg_tag/bsg_tag_client.v, 94
+  Continuous assignment width mismatch
+  1 bits (lhs) versus 3 bits (rhs).
+  Source info: assign tag_data_shift = {param_r, tag_data_r[(width_p - 1):1]};
+ 
+
+```

issues/bespoke-silicon-group_basejump_stl_pr735

@@ -0,0 +1,28 @@
+# Define BSG_HIDE_FROM_SYNTHESIS_EXPR macro
+
+Instance: bespoke-silicon-group_basejump_stl_pr735
+Source: https://github.com/bespoke-silicon-group/basejump_stl/pull/735
+Fetched: 2026-04-26
+Repository: bespoke-silicon-group/basejump_stl
+Pull request: #735
+Author: taylor-bsg
+State: closed
+Base branch: master
+Head branch: taylor-bsg-patch-4
+Created: 2025-09-23T17:48:57Z
+Updated: 2025-09-23T17:49:24Z
+Closed: 2025-09-23T17:49:24Z
+Merged: 2025-09-23T17:49:24Z
+
+PR Title: Define BSG_HIDE_FROM_SYNTHESIS_EXPR macro
+
+PR Description:
+Add macro for conditional synthesis hiding expression
+
+PR Comments:
+(No additional discussion comments beyond the commit message.)
+
+Linked Issues:
+The PR indicates "Successfully merging this pull request may close these issues," but no specific issue titles or bodies are visible.
+
+Status: Merged on Sep 23, 2025 by taylor-bsg.

issues/black-parrot_black-parrot_pr1089

@@ -0,0 +1,32 @@
+PR Title: Fix nonsynth cache UC store hit bug
+
+PR Description:
+The PR fixes issue #1086. According to the description: "Root cause was implementation of the nonsynth cache used in the ME testbench. Uncached stores targeting valid cache blocks were not self-invalidating the block, causing the store to get lost if targeted by following cacheable load. Bug is only present in the ME testbench, not in a real BP system."
+
+PR Comments:
+- dpetrisko (May 4, 2022): "Great find!"
+
+Linked Issue #1086: Referenced as fixed by this PR (issue body not provided in the page content).
+
+Metadata:
+- Author: muwyse
+- Reviewer/Approver: dpetrisko
+- Labels: bug, testing
+- Merged: May 4, 2022
+
+Original local content (issue body context):
+Area
+me_regress testing, ucode
+
+Current behavior
+me_regress fails under current CI for:
+bp_cce.e_bp_test_multicore_half_cce_ucode_cfg.msi.set_test.mixed.sim.cce.none.err
+bp_cce.e_bp_test_multicore_half_cce_ucode_cfg.msi-nonspec.set_test.mixed.sim.cce.none.err
+
+I've tried to rewind SDK/ucode and RTL and no combination seems to pass within reasonable scope
+
+Verification
+me_regress passing
+
+Additional Context
+https://gitlab.com/black-parrot/black-parrot/-/jobs/2343047561/artifacts/browse/bp_me/syn/reports/vcs/

issues/chili-chips-ba_openeye-CamSI_pr15

@@ -0,0 +1,20 @@
+# issue#2 - Testbench for I2C subsystem
+
+## Writing Testbench for I2C Part of Our Camera
+
+We need to write a testbench for the I2C part of our camera. For this purpose, we have utilized the `cocotbext-i2c` library. Specifically, we used only the `I2CDevice.py` module from this library, which emulates the slave device. The master part, however, was implemented directly in RTL.
+
+### Challenges Encountered:
+1. **SDA/SCL Bidirectional Signals**:
+   - The primary challenge was handling the bidirectional (inout) nature of the SDA and SCL lines.
+   - To resolve this, we had to define these lines as follows in our RTL code:
+     ```verilog
+     inout tri1 i2c_sda,
+     inout tri1 i2c_scl,
+     ```
+   - This specific declaration was necessary for cocotb to properly drive these signals.
+
+2. **Simulator Selection**:
+   - Another significant issue was choosing the appropriate simulator.
+   - Verilator, which is commonly used, does not support 'Z (high impedance) and 'X (unknown) values, supporting only log0 and log1.
+   - This limitation made it unsuitable for our testbench, requiring us to explore alternative simulators that can handle these signal states.

issues/chili-chips-ba_openeye-CamSI_pr26

@@ -0,0 +1,23 @@
+# issue#7 - Enable HiRez Sony camera
+
+# Add support for the 4-lane "OneInch" camera (Sony IMX283)
+## Description:
+
+The next project milestone is to expand the existing 2-lane CSI to 4-lane, and establish video datapath for this particular high-end camera. This milestone encompasses the following tasks: 
+
+### 1. Upgrade simulation environment to allow both 2 and 4-lane data paths, with 4 video formats: RAW8, RAW10, RAW12, RAW14
+- [x] CSI BFM 
+- [x] Testbench and relevant sim scripts
+- [ ] Time permitting, also add 1-lane option 
+
+### 2. Extend RTL from only RAW8 to also support RAW10, RAW12, and RAW14 image formats
+- [x] RAW2RGB block -- If it's too messy to support all 4 formats in one file, implement it in 4 separate files 
+- [x] Integration
+
+### 3. End-to-end simulations
+- [x] Verify old and new data path options in functional simulation through the entirety of video processing chain 
+
+### 4. Validate OneInch sensor and new data path on the real hardware
+- [x] Work out I2C configurations for the camera (as our sim setup does not cover that part)
+- [x] Check video pipeline stages from CSI all the way to HDMI. If needed, use Chipscope ILA for debug
+- [x] Crate a new demo, similar to the earlier for 2-lane RPi camera, but now with higher resolution Sony IMX294 camera

issues/chili-chips-ba_openeye-CamSI_pr30

@@ -0,0 +1,37 @@
+PR Title: Updated i2c part according to issue#30
+
+PR Description:
+(No description was provided by the author.)
+
+PR Comments:
+- Juninho99 (Oct 29, 2024): No comment text provided.
+- Juninho99: Requested review from chili-chips-ba and self-assigned the PR.
+- chili-chips-ba (Nov 6, 2024): Merged the pull request into main.
+
+Linked Issue Title: "Implementing Variable Pauses After I2C Register Writes in i2c_ctrl Module #29"
+Status: Closed (by this PR)
+
+Linked Issue body (issue#9):
+# issue#9 - Implementing Variable Pauses After I2C Register Writes in i2c_ctrl Module
+
+## Description:
+According to the camera's specification (**Sony IMX283**), after certain registers are written, there needs to be a pause of a few milliseconds before proceeding to the next set of registers.
+
+## Objective:
+Modify the existing `i2c_ctrl` module and `i2c_top` module to implement variable pauses after specific I2C register writes, as specified by the camera's requirements.
+
+## Problem Statement:
+The challenge is to introduce variable pauses after writing certain registers, as required by the camera's specification. These pauses are not periodic and occur only after specific registers. The pauses need to be controlled dynamically, allowing for different durations specified in milliseconds.
+
+## Proposed Solution:
+- Modify the `i2c_init.mem` file to include the pause duration for each register write.
+- Update the `i2c_data_init` array in the `i2c_top` module to read the pause durations along with register addresses and data.
+- Adjust the `i2c_ctrl` module to implement a **WAIT** state that counts the required pause duration using nested counters, avoiding resource-intensive multiplication.
+- Ensure that pauses are dynamically controlled based on the data read from i2c_init.mem.
+
+Key Details:
+The PR contains 2 commits:
+1. "Updated i2c part according to issue" (d6b71f5)
+2. "Changed names of .mem files" (3c69f4b)
+
+The changes were merged from the `issue#9` branch into `main` on November 6, 2024.

issues/chipsalliance_Cores-VeeR-EL2_pr363

@@ -0,0 +1,27 @@
+# Request to review Lint Issues in Veer RTL
+
+- Source URL: https://github.com/chipsalliance/Cores-VeeR-EL2/issues/166
+
+Hi, I am filling this issue to review couple of Lint issues inside Veer RTL.
+
+1. In **el2_veer.sv** file, below highlighted signals are read but never set.
+
+   assign ifu_axi_bready_int                  = pt.BUILD_AHB_LITE ? **ifu_axi_bready_ahb** : ifu_axi_bready;
+   assign lsu_axi_bready_int                  = pt.BUILD_AHB_LITE ? **lsu_axi_bready_ahb** : lsu_axi_bready;
+   assign sb_axi_bready_int                   = pt.BUILD_AHB_LITE ? **sb_axi_bready_ahb** : sb_axi_bready;
+
+
+2. Output signal highlighted below is never set.
+
+Output '**ifu_bp_fa_index_f**' is never set. (veer_el2/rtl/ifu/el2_ifu_bp_ctl.sv)
+Output '**exu_mp_pkt.br_start_error**' is never set. (veer_el2/rtl/exu/el2_exu.sv)
+Output '**exu_mp_pkt.br_error**' is never set. (veer_el2/rtl/exu/el2_exu.sv)
+Output '**exu_mp_pkt.prett[31:1]**' is never set. (veer_el2/rtl/exu/el2_exu.sv)
+Output '**lsu_ld_data_r[31:0]**' is never set. (veer_el2/rtl/lsu/el2_lsu_dccm_ctl.sv)
+Output '**dccm_rdata_lo_r[31:0]**' is never set. (veer_el2/rtl/lsu/el2_lsu_dccm_ctl.sv)
+Output '**dccm_rdata_hi_r[31:0]**' is never set. (veer_el2/rtl/lsu/el2_lsu_dccm_ctl.sv)
+Output '**dccm_data_ecc_lo_r[6:0]**' is never set. (veer_el2/rtl/lsu/el2_lsu_dccm_ctl.sv)
+Output '**dccm_data_ecc_hi_r[6:0]**' is never set. (veer_el2/rtl/lsu/el2_lsu_dccm_ctl.sv)
+Output '**ic_parerr[1:0]**' is never set. (veer_el2/rtl/el2_mem.sv)
+
+Request to clean up the code to keep Lint happy.

issues/chipsalliance_caliptra-ss_pr838

@@ -0,0 +1,23 @@
+# [Question] Regarding FcAxiFilterDaiAccessError_A assertion
+
+- Source URL: https://github.com/chipsalliance/caliptra-ss/issues/833
+
+Hello calipra team,
+
+I have found FcAxiFilterDaiAccessError_A assertion error during caliptra_ss_fuse_ctrl_axi_id test when a valid write follows a discard write.
+
+https://github.com/chipsalliance/caliptra-ss/blob/28ef1cefb5bfcf22e258419cd5db8f836527042f/src/integration/asserts/caliptra_ss_top_sva.sv#L75-L78
+
+I think that discard_fuse_write signal remains asserted for two more cycles after otp_operation_done toggles, so the assertion impacts on the next valid write as well.
+Therefore, I’ve just tried it as below.
+I’d appreciate your feedback on these changes.
+
+  ```
+`CALIPTRA_ASSERT(FcAxiFilterDaiAccessError_A,
+                 dai_write_req ##1       // <=== add
+                 `FC_PATH.discard_fuse_write ##1
+                 `FC_PATH.otp_operation_done[->1] |=>
+                 `FC_PATH.u_otp_ctrl_dai.error_o == {AccessError})
+
+```
+Regards,

issues/darklife_darkriscv_pr95

@@ -0,0 +1,28 @@
+# Add cycle and instret counters ("Zicntr" extension)
+
+- Source URL: https://github.com/darklife/darkriscv/issues/94
+
+Hello,
+
+The ISA suggests it should be implemented, as it serves basic performance analysis. I need it too for Dhrystone benchmark.
+I can see that clocks and instructions are being counted with `__PERFMETER__` enabled. Why not make them accessible via CSRs?
+
+
+
+
+
+
+
+# GitHub Issue #94: Add cycle and instret counters ("Zicntr" extension)
+
+## Issue Body
+The reporter notes that the RISC-V ISA suggests implementing cycle and instruction counters for basic performance analysis. They mention that clock and instruction counting already exist when `__PERFMETER__` is enabled, but these metrics should be made accessible through Control and Status Registers (CSRs). The requester needs this functionality for Dhrystone benchmark testing.
+
+## Status
+Closed (with associated PR #95)
+
+## Assignees
+samsoniuk, MrJake222
+
+## Notes
+The webpage content provided does not include visible comments from other users or additional linked issue details beyond the issue title and description shown.

issues/dawsonjon_fpu_pr16

@@ -0,0 +1,36 @@
+# Fix sign bug
+
+Instance: dawsonjon_fpu_pr16
+Source: https://github.com/dawsonjon/fpu/pull/16
+Fetched: 2026-04-26
+Repository: dawsonjon/fpu
+Pull request: #16
+Author: andreast271
+State: closed
+Base branch: master
+Head branch: master
+Created: 2019-01-21T16:34:51Z
+Updated: 2019-01-21T18:26:12Z
+Closed: 2019-01-21T18:26:12Z
+Merged: 2019-01-21T18:26:12Z
+
+The result of -a + a should be +0 (positive zero). Without this fix, the module returns -0 (negative zero).
+
+# PR #16: Fix sign bug
+
+## Title
+Fix sign bug
+
+## Description
+The result of -a + a should be +0 (positive zero). Without this fix, the module returns -0 (negative zero).
+
+## Comment by andreast271 (Jan 21, 2019)
+"The result of -a + a should be +0 (positive zero). Without this fix, the module returns -0 (negative zero)."
+
+## Merge Status
+Merged by dawsonjon on Jan 21, 2019
+
+## Commit
+c75ffcf92183c1777e84a87170e6759eaff70d17
+
+No linked issues or additional comments were present in the pull request.

issues/gtaylormb_opl3_fpga_pr51

@@ -0,0 +1,24 @@
+# Linting for boosting RTL quality and QA consistency
+
+- Source URL: https://github.com/gtaylormb/opl3_fpga/issues/48
+
+## Issue Title
+Linting for boosting RTL quality and QA consistency
+
+## Issue Description
+The issue body referenced a related discussion from the openCologne project (https://github.com/chili-chips-ba/openCologne/issues/16). The issue is focused on implementing linting tools and processes to improve the quality and consistency of the RTL (Register Transfer Level) code within this FPGA design project.
+
+## Issue Comments
+None visible.
+
+## Issue Metadata
+- Status: Closed (resolved via PR #51)
+- Author: chili-chips-ba
+- Created: June 12, 2024
+- Assignees: None
+- Labels: None
+- Milestone: None
+
+## Linked Issues / PRs
+- PR #51 — resolves this issue
+- Related discussion: openCologne #16

issues/hdl-util_hdmi_pr16

@@ -0,0 +1,33 @@
+# Switch to GH action
+
+Instance: hdl-util_hdmi_pr16
+Source: https://github.com/hdl-util/hdmi/pull/16
+Fetched: 2026-04-26
+Repository: hdl-util/hdmi
+Pull request: #16
+Author: sameer
+State: closed
+Base branch: master
+Head branch: github-action
+Created: 2021-02-07T00:33:51Z
+Updated: 2021-02-07T01:23:04Z
+Closed: 2021-02-07T01:23:01Z
+Merged: 2021-02-07T01:23:01Z
+
+## PR Title
+Switch to GH action
+
+## PR Description
+No description provided.
+
+## PR Comments
+No substantive comments were recorded in the conversation thread beyond the automated merge notification.
+
+## PR Metadata
+- Status: Merged
+- Author force-pushed the github-action branch multiple times before merging
+- Purpose: transition the project's CI/CD infrastructure from Travis CI to GitHub Actions and update ModelSim dependencies
+- Branch deleted after merge: github-action
+
+## Linked Issues
+No linked issues are referenced in this pull request.

issues/hdl-util_hdmi_pr21

@@ -0,0 +1,37 @@
+# move screen to upper left corner in frame
+
+Instance: hdl-util_hdmi_pr21
+Source: https://github.com/hdl-util/hdmi/pull/21
+Fetched: 2026-04-26
+Repository: hdl-util/hdmi
+Pull request: #21
+Author: sameer
+State: closed
+Base branch: master
+Head branch: origin_is_screen_origin
+Created: 2021-03-06T05:28:53Z
+Updated: 2021-03-07T16:55:16Z
+Closed: 2021-03-07T16:55:13Z
+Merged: 2021-03-07T16:55:13Z
+
+## PR Title
+move screen to upper left corner in frame
+
+## PR Description
+this way, origin = screen origin
+
+## PR Comments
+
+**sameer** (Mar 6, 2021):
+"this way, origin = screen origin"
+
+## PR Metadata
+- Status: Merged
+- Commit: c003eba
+- Reviewers: None
+- Assignees: None
+- Labels: None
+- Branch deleted after merge: origin_is_screen_origin
+
+## Linked Issues
+No linked issues are referenced in this pull request.

issues/hdl-util_hdmi_pr29

@@ -0,0 +1,25 @@
+# hdmi: allow setting start x/y with parameters
+
+Instance: hdl-util_hdmi_pr29
+Source: https://github.com/hdl-util/hdmi/pull/29
+Fetched: 2026-04-26
+Repository: hdl-util/hdmi
+Pull request: #29
+Author: bkoropoff
+State: closed
+Base branch: master
+Head branch: start-coord
+Created: 2022-01-23T00:08:30Z
+Updated: 2022-01-27T01:22:16Z
+Closed: 2022-01-27T01:22:16Z
+Merged: 2022-01-27T01:22:16Z
+
+gbaHD needs this synchronize the hdmi output with the start of a GBA
+frame, with the GBA image centered within the HDMI frame instead of
+starting at 0,0.
+
+It's easier and uses fewer FPGA resources to start the hdmi block in the
+middle of a frame than to count off the right number of cycles from GBA
+vsync to achieve the same phase relationship.  Receivers need to be able
+to synchronize from mid-stream anyway, so this doesn't cause any
+problems.

issues/jotego_jt12_pr64

@@ -0,0 +1,23 @@
+# Genesis Regression: Bimini Run audio playing too fast
+
+- Source URL: https://github.com/jotego/jt12/issues/62
+
+## Issue Title
+Genesis Regression: Bimini Run audio playing too fast
+
+## Issue Description
+https://github.com/MiSTer-devel/Genesis_MiSTer/issues/26#issuecomment-1117934103 — as confirmed by gyurco, Bimini Run has a regression that points to this commit: https://github.com/jotego/jt12/commit/66eb9ee162e1b1cd3f31f7549af969c7bc191951
+
+The issue reports a regression in the Bimini Run game where audio plays at an increased speed.
+
+## Issue Comments
+None visible.
+
+## Issue Metadata
+- Status: Closed (resolved via PR #64)
+- Project: JTCores
+
+## Linked Issues / PRs
+- PR #64 — resolution
+- References Genesis_MiSTer #26
+- Points to commit 66eb9ee162e1b1cd3f31f7549af969c7bc191951

issues/jotego_jtcores_pr1111

@@ -0,0 +1,22 @@
+# ngp/ngpc: brown line appearing at the bottom of the screen
+
+- Source URL: https://github.com/jotego/jtcores/issues/994
+
+## Issue Title
+ngp/ngpc: brown line appearing at the bottom of the screen
+
+## Issue Description
+Tested for commit 31abc75893f2108052617b8c119cc2f7d7731b3f on Analogue Pocket.
+
+(Issue body details beyond the test commit reference were not fully captured.)
+
+## Issue Comments
+None visible.
+
+## Issue Metadata
+- Status: Closed (marked Done in JTCores project)
+- Assignee: rp-jt
+
+## Linked Issues / PRs
+- PR #1111
+- PR #1069

issues/jotego_jtcores_pr1169

@@ -0,0 +1,25 @@
+# suratk: sprite on sprite shade
+
+- Source URL: https://github.com/jotego/jtcores/issues/1160
+
+## Issue Title
+suratk: sprite on sprite shade
+
+## Issue Description
+Sprites can currently cast a shadow on the background but not on other sprites. This feature is missing on master.
+
+It works on the suratk-1160 branch but the change may be not be backwards compatible.
+
+(Two screenshot images were provided showing the visual difference between the current state and the desired implementation with sprite-on-sprite shadowing.)
+
+## Issue Comments
+None visible.
+
+## Issue Metadata
+- Status: Closed (linked to PR #1169)
+- Assignee: rp-jt
+- Labels: core bug, new core
+- Project: JTCores (Status: Done)
+
+## Linked Issues / PRs
+- PR #1169 — resolution

issues/jotego_jtcores_pr1279

@@ -0,0 +1,22 @@
+# kiwi: Dr Toppel's Adventure Graphical Issue
+
+- Source URL: https://github.com/jotego/jtcores/issues/1276
+
+Copying from here: https://github.com/jotego/jtcores_mister/issues/13
+
+> https://youtu.be/UEeqoD7jRxc?t=56 timestamp - please notice the orange issues where background graphics are not drawing in properly - I am not sure when this started, I utilized update_all on 11/22/2025 prior to testing.
+Note - I tried all 3 MRAs and all have this issue (World, USA, and Japan).
+I also noticed sound seems a little off but I am not as well versed to know if this is inaccurate or an issue.
+
+## Fetched Issue/PR Details
+
+Title: kiwi: Dr Toppel's Adventure Graphical Issue (#1276)
+
+Description: The issue references a graphical problem in Dr. Toppel's Adventure where there are "orange issues where background graphics are not drawing in properly." The reporter tested all three MRAs (World, USA, and Japan) and experienced the same graphical glitch after running an update on November 22, 2025. They also noted potential sound anomalies but were uncertain whether these represent actual bugs.
+
+Status: Closed (linked to PR #1279)
+Project: JTCores
+
+Comments: No comments were visible beyond the initial issue description.
+
+Linked Issues: References https://github.com/jotego/jtcores_mister/issues/13 (the original report copied into this issue).

issues/jotego_jtcores_pr634

@@ -0,0 +1,25 @@
+# toki: latches
+
+- Source URL: https://github.com/jotego/jtcores/issues/606
+
+Hi @vertrex
+
+There are some latches in the current design. You will get a latch warning when using `jtcore` to compile. Latches tend to cause obscure bugs so it is better to have a fully synchronous design without them.
+
+Please try to remove them.
+
+Thanks
+
+## Fetched Issue/PR Details
+
+Title: toki: latches (#606)
+
+Description: jotego opened the issue on April 8, 2024, asking vertrex to remove latches from the design. The message states: "There are some latches in the current design. You will get a latch warning when using `jtcore` to compile. Latches tend to cause obscure bugs so it is better to have a fully synchronous design without them."
+
+Status: Closed (resolved via PR #634)
+Assignees: vertrex, jotego
+Project: JTCores
+
+Comments: No comments from other users were included in the page content.
+
+Linked Issues: None beyond the resolving PR #634.

issues/jotego_jtcores_pr960

@@ -0,0 +1,22 @@
+# Adjusting Volume using keyboard does not work on pocket.
+
+- Source URL: https://github.com/jotego/jtcores/issues/935
+
+On Mister it is possible to adjust the volume using F4 and F5 but this does not work on Analogue Pocket.
+Since it is not possible to adjust the volume on Analogue Pocket while in dock It would be useful if this was working.
+
+## Fetched Issue/PR Details
+
+Title: Adjusting Volume using keyboard does not work on pocket. (#935)
+
+Description: The reporter notes that on Mister, volume adjustment via F4 and F5 keyboard keys functions properly, but this capability is absent on Analogue Pocket. They request implementation of this feature, particularly since manual volume adjustment isn't possible while the Pocket is docked.
+
+Status: Closed (resolved via PR #960)
+Assignee: rp-jt
+Label: Enhancement
+Project: JTCores
+Created: January 17, 2025
+
+Comments: None visible on the page.
+
+Linked Issues: Resolving PR #960.

issues/lowRISC_ibex_pr2269

@@ -0,0 +1,31 @@
+# [bug][ibex_decoder] Report a bug in Ibex
+
+- Source URL: https://github.com/lowRISC/ibex/pull/2269
+
+Hi all!
+
+I am using a static analysis to found a various bugs in open source RTL designs.
+
+It was founded that in `ibex_decoder.sv` RTL file dead code is exists [here](https://github.com/lowRISC/ibex/blob/master/rtl/ibex_decoder.sv#L439).
+
+This assignment under `else` statement is never executed due to [this](https://github.com/lowRISC/ibex/blob/master/rtl/ibex_decoder.sv#L406) external `else` branch with `!instr[26]` condition.
+
+## Fetched Issue/PR Details
+
+Title: [rtl] Minor tweak to decoder to avoid dead code (PR #2269)
+
+Description: The PR addresses dead code in the instruction decoder. According to the submitter, an else branch was unreachable because the surrounding condition already established that instr[26] was zero, making a redundant check impossible to execute.
+
+Status: Merged
+Merged by: andreaskurth
+Merge date: April 25, 2025
+Reviewers: marnovandermaas, andreaskurth, vogelpi (awaiting)
+Checks passed: 11
+
+Comments:
+- rswarbrick (Apr 23, 2025): "The 'else' part of the if/else check here wasn't possible because the surrounding else branch...is already in the case where instr[26] is zero."
+- marnovandermaas (Apr 24, 2025): Suggested adding an assertion to clarify the constraint.
+- rswarbrick (response): Noted that the project lacks procedural assertions in RTL code and the constraint is syntactically visible.
+- andreaskurth (Apr 25, 2025): Approved with "LGTM, thx @rswarbrick".
+
+Linked Issues: Fixes issue #2268 ("[bug][ibex_decoder] Report a bug in Ibex").

issues/merledu_azadi-soc_pr14

@@ -0,0 +1,19 @@
+# Need a coverage plan for ibex core!
+
+- Source URL: https://github.com/merledu/azadi-soc/issues/13
+
+
+## Fetched Issue/PR Details
+
+Title: Need a coverage plan for ibex core! (#13)
+
+Description: No description provided in the original issue body. The issue appears to be a request for establishing test coverage documentation or strategy for the Ibex core component within the Azadi SoC project.
+
+Repository: merledu/azadi-soc
+Status: Closed (linked to PR #14)
+Author: za1nrkhan
+Created: November 19, 2021
+
+Comments: None visible.
+
+Linked Issues: Resolving PR #14.

issues/merledu_azadi-soc_pr2

@@ -0,0 +1,25 @@
+# Input signal declared as output
+
+- Source URL: https://github.com/merledu/azadi-soc/issues/1
+
+When simulating with Xcelium, these warnings appear:
+
+```
+xmelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
+    .rd_data_o  (frm_q),
+                     |
+xmelab: *W,ENUMERR (/home/zrkhan/Desktop/uvm-runs/azadi-new/hw/vendor/lowrisc_ibex/rtl/ibex_cs_registers.sv,849|21): This assignment is a violation of SystemVerilog strong typing rules for enumeration datatypes.
+    .tag_i          ( 1                ),
+                      |
+xmelab: *W,CUVMPW (/home/zrkhan/Desktop/uvm-runs/azadi-new/hw/vendor/lowrisc_ibex/rtl/ibex_core.sv,1205|22): port sizes differ in port connection(32/1) for the instance(core_ibex_tb_top.dut.u_ibex_core) .
+      .fp_load_o                       ( fp_load               )
+               |
+```
+Followed by this error message
+```
+xmelab: *E,MULDRN (/home/zrkhan/Desktop/uvm-runs/azadi-new/hw/vendor/lowrisc_ibex/rtl/ibex_core.sv,712|15): Variable 'core_ibex_tb_top.dut.u_ibex_core.fp_load' has multiple conflicting drivers and the indicated output port connection in scope 'core_ibex_tb_top.dut.u_ibex_core' is contributing to this conflict set.
+    .fp_load_i                      ( fp_load                      )
+             |
+```
+
+The issue points out to the invalid port direction of `ibex_wb_write` module.

issues/muneeb-mbytes_pulpino__spi_master__ip_verification_pr39

@@ -0,0 +1,52 @@
+# Integrate RTL and VIPs
+
+- Source URL: https://github.com/muneeb-mbytes/pulpino__spi_master__ip_verification/issues/9
+
+Title: Integrate RTL and VIPs
+
+Body: Integrate the RTL design and VIPs by developing the top module
+
+Comments: None
+
+Linked PR: #39 (closed)
+
+Metadata:
+- Assignee: Nadeem-Ahmed-S
+- Milestone: 💻 Development
+- Status: Closed
+- Created: February 5, 2022
+
+---
+
+## Pull Request
+
+**PR Title:** Integration of RTL and VIPs done as in TB Architecture
+
+**PR Number:** #39
+
+**Status:** Merged on February 18, 2022
+
+**Branch:** `rtl_vips_integration` → `development_branch_v1`
+
+### Description
+
+The initial PR description outlined several key objectives:
+
+- "Created two tops hvl_top and hdl_top inside dv folder"
+- "Added the bfm sides of both apb_master and spi_slave in hdl_top.sv file"
+- "Mapped the apb_master interface and spi_slave interface to rtl"
+- "Printing the topology as in the architecture diagram"
+
+The PR addressed issues #9 (Integrate RTL and VIPs) and #11 (Develop TB components).
+
+### Comments
+
+**Nadeem-Ahmed-S** (February 17, 2022) provided an update describing additional work:
+
+Added comparisons for write data and MOSI data. Developed check and report phases within the scoreboard through separate commits addressing run_phase, check_phase, and report_phase implementations.
+
+### Review & Merge
+
+**muneebullashariff** approved the changes on February 18, 2022, with the comment: "Merging the changes." The branch was subsequently deleted on March 1, 2022.
+
+**Participants:** 5 contributors including Nadeem-Ahmed-S, muneebullashariff, sahanapalesh, sivareddykostam, and Shwetapatil05.

issues/nand2mario_nestang_pr75

@@ -0,0 +1,36 @@
+# NES controller connection issue
+
+- Source URL: https://github.com/nand2mario/nestang/pull/75
+
+Title: Fix NES controllers
+
+Body: Fixes #74
+
+Comments:
+- nikitalita (May 23, 2024): "Fixes #74"
+- nand2mario (May 23, 2024): Merged commit 705d9c1 into master
+
+Linked Issue: NES controller connection issue (#74)
+Linked Issue Body: I see you recently added support for them; which pins do they connect to? I'm going to make my own connector with a breadboard and a voltage logic level converter.
+
+Status: Merged on May 23, 2024
+
+## PR Title
+Fix NES controllers
+
+## PR Description
+Fixes #74
+
+## PR Comments
+No substantive comments are documented in the conversation thread beyond the PR description referencing the issue.
+
+## Linked Issue
+#74: NES controller connection issue
+Body: I see you recently added support for them; which pins do they connect to? I'm going to make my own connector with a breadboard and a voltage logic level converter.
+
+## PR Metadata
+- Author: nikitalita
+- Repository: nand2mario/nestang
+- Merge commit: 705d9c14f0be84c54476b1f54e463fa971530bfb
+- Status: Merged on May 23, 2024 by nand2mario into master
+- Participants: nikitalita, nand2mario

issues/olofk_serv_pr107

@@ -0,0 +1,33 @@
+# support for W=4
+
+Instance: olofk_serv_pr107
+Source: https://github.com/olofk/serv/pull/107
+Fetched: 2026-04-26
+Repository: olofk/serv
+Pull request: #107
+Author: uhit332
+State: closed
+Base branch: main
+Head branch: incremental
+Created: 2023-10-31T12:34:06Z
+Updated: 2023-10-31T14:54:12Z
+Closed: 2023-10-31T14:53:37Z
+Merged: 2023-10-31T14:53:37Z
+
+## PR Title
+support for W=4
+
+## PR Description
+No description provided.
+
+## PR Comments
+
+**olofk** (October 31, 2023):
+"Perfect! Picked and pushed!"
+
+## Linked Issues
+No linked issues.
+
+## PR Metadata
+- Participants: uhit332 (contributor), olofk (owner)
+- Status: Merged into olofk:main on October 31, 2023

issues/openhwgroup_core-v-verif_pr2585

@@ -0,0 +1,34 @@
+Minimal fail-to-pass extraction for openhwgroup/core-v-verif PR 2585, "Restore
+Verilator compile/simulation".
+
+The reduced testbench wrapper models the real Verilator compile fix where the
+CV32E40P wrapper module was renamed to `cv32e40p_core_tb_wrapper` and the
+Verilator top instantiates the renamed wrapper.  The buggy snapshot has the
+renamed file/top reference but the old module declaration, reproducing the
+missing-module compile failure.  The patch renames the module so the Verilator
+testbench can build and drive `fetch_enable_i`.
+
+## PR Title
+Restore Verilator compile/simulation
+
+## PR Description
+Resolves #2584, and cleans up DSim compiles as well.
+
+## PR Comments
+
+**cairo-caplan** (Feb 11, 2025):
+Suggested that the "-std=gnu++11" compiler flag removal was necessary because recent Verilator versions no longer require it. They also recommended applying similar changes to cv32e40s and cv32e40x Makefiles and noted the filename should match the module name for consistency.
+
+**MikeOpenHWGroup** (Feb 11, 2025):
+Referenced Verilator Issue #4898, which recommends removing "-std=c++11". They acknowledged that cv32e40s and cv32e40x should receive similar updates on their respective development branches and confirmed they had updated the filename to match the renamed module.
+
+**cairo-caplan** (Feb 11, 2025):
+Approval. Confirmed testing on Verilator 5.033 and validated the changes resolved the original issue.
+
+## Linked Issue
+#2584: Followed the quick start for cv32e40p but got hit with 7 warnings (Status: Closed)
+
+## PR Metadata
+- Author: MikeOpenHWGroup
+- Target Branch: openhwgroup:cv32e40p/dev
+- Status: Merged (April 1, 2025)

issues/openhwgroup_core-v-xif_pr139

@@ -0,0 +1,25 @@
+# CV-X-IF vs. CORE-V-XIF
+
+In https://github.com/openhwgroup/core-v-xif/pull/124/commits/8d7a432ceaca51b62af772b449af29e26120ad02 the term `CORE-V-XIF` is replaced by `CV-X-IF` in `README.md` and `intro.rst` files.
+
+Is there any reason to keep `CORE-V-XIF` in `x_ext.rst` file? For the sake of consistency, it would be preferable to use only one acronym.
+
+## PR Title
+Replacing CORE-V-XIF with CV-X-IF
+
+## PR Description
+No description provided.
+
+## PR Comments
+Christian Herber (contributor) requested a review from ASintzoff on February 6, 2024 at 08:37 AM.
+
+## Linked Issue
+#138: CV-X-IF vs. CORE-V-XIF
+
+## PR Metadata
+- Submitter: christian-herber-nxp
+- Reviewer/Merger: ASintzoff
+- Source Branch: 138-cv-x-if-vs-core-v-xif
+- Target Branch: main
+- Status: Merged (February 6, 2024)
+- Participants: christian-herber-nxp, ASintzoff

issues/openhwgroup_cv-hpdcache_pr48

@@ -0,0 +1,26 @@
+# Incorrect flagging of write request event
+
+Hi, I have noticed that the write request event (`evt_write_req_o`) is not flagged when there is a write request with a write-back policy and the memory produces a response with the error bit set.
+
+## How to reproduce the issue
+
+Using the verilator testbench, run the following command:
+
+```
+make run SEQUENCE=random LOG_LEVEL=3 NTRANSACTIONS=69 SEED=42
+```
+
+The faulting transaction will be the last one.
+
+## Issue description
+
+The core makes a store request, using a write-back policy. This request causes a miss, causing the cache to issue a load request to memory due to the write-allocate policy. The write miss event (`evt_cache_write_miss_o`) is flagged, but the write request event (`evt_write_req_o`)  is not. The request is put in the RTAB while the cache waits for the memory response.
+
+Once the response arrives, it has the error bit set. The original request is then replayed from the RTAB. Because it has been flagged with the error bit, it only sends a response to the core with this flag set. However, it does not flag any event and does not proceed any further. 
+
+Under normal circumstances, when the error bit is not set, the directory would be updated and the replayed request would hit the cache. It is under this logic when the write request event is flagged (see [hpdcache_ctrl_pe.sv:881](https://github.com/openhwgroup/cv-hpdcache/blob/master/rtl/src/hpdcache_ctrl_pe.sv#L881)).
+
+## Possible solutions
+
+- When replaying a request with the error bit set, check if it's a store with the write-back policy, and flag the event then (inside hpdcache_ctrl_pe.sv:404).
+- When there is a write-back store making a hit in the cache, check if it's a core request or a replay from the RTAB. Emit the write request event both when there is a miss and when the core (and not a replay due to a miss) makes a hit.