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snapshots/bespoke-silicon-group_basejump_stl_pr706/bsg_comm_link/master_calib_skip/bsg_comm_link_master_calib_skip_rom.trace.in

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+#######################################################################################################
+#
+#
+# trace (for bsg_fsb_node_trace_replay) to have the master do a quick wakeup of the ASIC comm link
+#
+#
+# format:   <4 bit op> <16 bits>
+#   op = 0000: wait one cycle
+#   op = 0001: write data <addr2 data14>
+#                          00 data14     --> write channel <valid1, data8> reg
+#                          01 data14     --> write channel override reg  <1bit>
+#                          10 data14     --> write master_master test_pass_reg <6bit>
+#                          11 data14     --> write match_reg  < out_calib_prep1, out_calibration_state3 >
+#   op = 0010:  00_0000_0000_0000 --> wait until match reg matches < out_calib_prep1, out_calibration_state6 > 
+#               (check data)
+#
+#   op = 0011: done; disable but do not stop
+#   op = 0100: call $finish
+#   op = 0101: cycle counter decrement and wait
+#   op = 0110   initialize cycle counter with 16 bits
+#
+#
+# op4  adr2  field
+#
+# 0001__00___00_000V_DDDD_DDDD  #  --> channel write valid1,data8
+# 0001__01___00_0000_0000_000R  #  --> channel write override reg 1bit
+# 0001__10___00_0000_00PP_PPPP  #  --> channel write master_master test_pass_reg
+# 0001__11___00_0000_0000_PMMM  #  --> channel write prep1, calib_state3 match reg
+# 0010__0000_0000_0000_0000     #  --> wait for match reg to match
+# 0110__CCCC_CCCC_CCCC_CCCC     #  --> initialize cycle counter to C cycles
+# 0101__0000_0000_0000_0000     #  --> decrement and wait on cycle counter
+# 0011__0000_0000_0000_0000     #  --> stop
+#
+#
+# 0001__00___00_000V_DDDD_DDDD  #  --> channel write valid1,data8                  (0,F5 == reset clock)
+0001__00___00_0000_1111_0101
+# 0001__01___00_0000_0000_000R  #  --> channel write override reg 1bit             (1 = override)
+0001__01___00_0000_0000_0001
+# 0001__11___00_0000_0000_PMMM  #  --> channel write prep1, calib_state3 match reg wait for (prep=1,state=000)
+0001__11___00_0000_0000_1000
+# 0010__0000_0000_0000_0000     #  --> wait for match reg to match                 (wait for prep=1)
+0010__0000_0000_0000_0000
+# 0110__CCCC_CCCC_CCCC_CCCC     #  --> initialize cycle counter to C cycles        (init 32 cycles)
+0110__0000_0000_0010_0000
+# 0101__0000_0000_0000_0000     #  --> decrement and wait on cycle counter         (wait 32 cycles)
+0101__0000_0000_0000_0000
+# 0001__00___00_000V_DDDD_DDDD  #  --> channel write valid1,data8                  (1,81 == reset token)
+0001__00___00_0001_1000_0001
+# 0110__CCCC_CCCC_CCCC_CCCC     #  --> initialize cycle counter to C cycles        (init 32 cycles)
+0110__0000_0000_0010_0000
+# 0101__0000_0000_0000_0000     #  --> decrement and wait on cycle counter         (wait 32 cycles)
+0101__0000_0000_0000_0000
+# 0001__00___00_000V_DDDD_DDDD  #  --> channel write valid1,data8                  (0,F5 == reset clock)
+0001__00___00_0000_1111_0101
+# 0110__CCCC_CCCC_CCCC_CCCC     #  --> initialize cycle counter to C cycles        (init 64 cycles) extra time for token CDC
+0110__0000_0000_0100_0000
+# 0101__0000_0000_0000_0000     #  --> decrement and wait on cycle counter         (wait 64 cycles)
+0101__0000_0000_0000_0000
+# 0001__10___00_0000_00PP_PPPP  #  --> channel write master_master test_pass_reg   (passed test 1), turn reset low
+0001__10___00_0000_0000_0001
+# 0110__CCCC_CCCC_CCCC_CCCC     #  --> initialize cycle counter to C cycles        (init 32 cycles)
+0110__0000_0000_0010_0000
+# 0101__0000_0000_0000_0000     #  --> decrement and wait on cycle counter         (wait 32 cycles)
+0101__0000_0000_0000_0000
+# 0001__00___00_000V_DDDD_DDDD  #  --> channel write valid1,data8                  (0,6A == activate channel)
+0001__00___00_0000_0110_1010
+# 0110__CCCC_CCCC_CCCC_CCCC     #  --> initialize cycle counter to C cycles        (init 32 cycles)
+0110__0000_0000_0010_0000
+# 0101__0000_0000_0000_0000     #  --> decrement and wait on cycle counter         (wait 32 cycles)
+0101__0000_0000_0000_0000
+# 0001__10___00_0000_00PP_PPPP  #  --> channel write master_master test_pass_reg   (passed test 2), turn reset high
+0001__10___00_0000_0000_0010
+# 0110__CCCC_CCCC_CCCC_CCCC     #  --> initialize cycle counter to C cycles        (init 32 cycles)
+0110__0000_0000_0010_0000
+# 0101__0000_0000_0000_0000     #  --> decrement and wait on cycle counter         (wait 32 cycles)
+0101__0000_0000_0000_0000
+# 0001__00___00_000V_DDDD_DDDD  #  --> channel write valid1,data8                  (1,81 == reset token)
+0001__00___00_0001_1000_0001
+# 0110__CCCC_CCCC_CCCC_CCCC     #  --> initialize cycle counter to C cycles        (init 32 cycles)
+0110__0000_0000_0010_0000
+# 0101__0000_0000_0000_0000     #  --> decrement and wait on cycle counter         (wait 32 cycles)
+0101__0000_0000_0000_0000
+# 0001__00___00_000V_DDDD_DDDD  #  --> channel write valid1,data8                  (0,6A == activate channel)
+0001__00___00_0000_0110_1010
+# 0110__CCCC_CCCC_CCCC_CCCC     #  --> initialize cycle counter to C cycles        (init 64 cycles) extra time for token CDC
+0110__0000_0000_0100_0000
+# 0101__0000_0000_0000_0000     #  --> decrement and wait on cycle counter         (wait 64 cycles)
+0101__0000_0000_0000_0000
+# 0001__10___00_0000_00PP_PPPP  #  --> channel write master_master test_pass_reg   (passed test 3), turn reset low
+0001__10___00_0000_0000_0100
+# 0110__CCCC_CCCC_CCCC_CCCC     #  --> initialize cycle counter to C cycles        (init 32 cycles)
+0110__0000_0000_0010_0000
+# 0101__0000_0000_0000_0000     #  --> decrement and wait on cycle counter         (wait 32 cycles)
+0101__0000_0000_0000_0000
+# 0001__01___00_0000_0000_000R  #  --> channel write override reg 1bit             disable override of output (0 = override)
+0001__01___00_0000_0000_0000
+# 0001__10___00_0000_00PP_PPPP  #  --> channel write master_master test_pass_reg   (passed test 6), activate channel
+0001__10___00_0000_0011_1111
+# 0011__0000_0000_0000_0000     #  --> stop script
+0011__0000_0000_0000_0000
+

snapshots/bespoke-silicon-group_basejump_stl_pr706/bsg_comm_link/master_calib_skip/bsg_source_sync_channel_control_master_master.sv

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+// MBT 5-1-2017
+//
+// fast version of the gateway reset sequence
+//
+// this version assumes that all channels work
+// and is just for gatelevel simulation.
+//
+
+
+`include "bsg_defines.sv"
+
+module bsg_source_sync_channel_control_master_master
+  #(parameter `BSG_INV_PARAM( link_channels_p  )
+    , parameter `BSG_INV_PARAM(tests_p          )
+    , parameter `BSG_INV_PARAM(prepare_cycles_p )   // ignored
+    , parameter `BSG_INV_PARAM(timeout_cycles_p ))  // ignored
+  (input clk_i   // from io_master_clk_i
+   , input reset_i // from im_reset_i
+
+   // we should begin the calibration stuff
+
+   , input start_i
+
+   // from masters, signals that that channel thinks it is done with the test
+
+   , input  [tests_p+1-1:0][link_channels_p-1:0]    test_scoreboard_i
+   , output [$clog2(tests_p+1)-1:0] test_index_r_o
+
+   // simultaneously a reset signal and a signal to the masters
+
+   , output prepare_o
+   , output done_o        // we are done with all of this calibration stuff.
+   );
+
+   logic done_r, done_n;
+
+   logic [$clog2(tests_p+1)-1:0] test_index_n, test_index_r;
+   assign test_index_r_o = test_index_r;
+
+   logic                         started_r;
+
+   always_ff @(posedge clk_i)
+     if (reset_i)
+       started_r <= 0;
+     else
+       started_r <= started_r | start_i;
+
+   // we assert reset on states that end in 0
+
+   assign prepare_o = ~(test_index_r[0]) & started_r & ~done_r;
+
+   always_ff @(posedge clk_i)
+     begin
+        if (reset_i)
+          test_index_r <= 0;
+        else
+          test_index_r <= test_index_n;
+     end
+
+   assign done_o =  done_r;
+
+   always @(posedge clk_i)
+     if (reset_i)
+       done_r <= 0;
+     else
+       done_r <= done_n;
+
+   always_comb
+     begin
+        done_n = done_r;
+        if (&test_scoreboard_i[tests_p])
+          done_n = 1'b1;
+     end
+
+   // move to the next test if everybody is happy
+
+   always_comb
+     begin
+        test_index_n = test_index_r;
+
+        if (!done_r & started_r & (&test_scoreboard_i[test_index_r]))
+          test_index_n = test_index_r+1;
+     end
+
+
+endmodule
+
+`BSG_ABSTRACT_MODULE(bsg_source_sync_channel_control_master_master)

snapshots/bespoke-silicon-group_basejump_stl_pr706/bsg_comm_link/tests/test_bsg_assembler/test_bsg_assembler.sv

@@ -0,0 +1,530 @@
+// MBT 8-20-2014
+//
+// Test assembler
+//
+// We model here two cores that have different clocks and are
+// communicating over an I/O channel which has a third clock.
+//
+// Includes model reset logic with synchronizers and delayed
+// communication after reset.
+//
+
+// these defines can be overridden by command line parameters
+
+`include "bsg_defines.sv"
+
+`include "test_assembler_defines.sv"
+
+module test_assembler;
+
+   initial begin
+      $vcdpluson;
+      $vcdplusmemon;
+      end
+
+   // three separate clocks: I/O, and the two cores communicating with each other
+   localparam core_0_half_period_lp    = `CORE_0_HALF_PERIOD;
+   localparam io_master_half_period_lp = `IO_MASTER_HALF_PERIOD;
+   localparam core_1_half_period_lp    = `CORE_1_HALF_PERIOD;
+
+   localparam iterations_lp            = `ITERATIONS;
+
+   // number of bits width of a channel
+   localparam channel_width_lp         = `CHANNEL_WIDTH;
+   localparam num_channels_lp          = `NUM_CHANNELS;
+
+   // this is the number of bytes that a ring packet is
+   localparam ring_bytes_lp            = `RING_BYTES;
+
+   // across all frequency combinations, we need a little over 20 fifo slots
+   // so we round up to 32, to allow for delay in the FPGA
+
+   localparam lg_input_fifo_depth_lp = 5;
+
+   // for DDR at 500 mbps, we make token go at / 8 = 66 mbps
+   // this will keep the token clock nice and slow
+
+   localparam lg_credit_to_token_decimation_lp=3;
+
+
+
+   // *************************************************
+   // independent clocks
+   //
+   //
+
+   logic core_0_clk, core_1_clk, io_master_clk;
+
+   initial core_0_clk = 0;
+   always #(core_0_half_period_lp) core_0_clk = ~core_0_clk;
+
+
+   initial io_master_clk = 0;
+   always #(io_master_half_period_lp) io_master_clk = ~io_master_clk;
+
+   initial core_1_clk = 0;
+   always #(core_1_half_period_lp) core_1_clk = ~core_1_clk;
+
+
+   // *************************************************
+   // master resets
+   //
+
+   logic core_0_reset, core_1_reset;
+
+   localparam core_reset_cycles_hi_lp = 256;
+   localparam core_reset_cycles_lo_lp = 16;
+
+   // we model this as if the FPGA is driving this with an unknown clock.
+   initial
+     begin
+        core_0_reset = 0;
+        core_1_reset = 0;
+        // simple hack to wait based on maximum of clock periods
+        repeat (core_reset_cycles_lo_lp)
+          begin
+             @(negedge core_0_clk);
+             @(negedge core_1_clk);
+             @(negedge io_master_clk);
+          end
+
+        core_0_reset = 1;
+        core_1_reset = 1;
+        // simple hack to wait based on maximum of clock periods
+        repeat (core_reset_cycles_hi_lp)
+          begin
+             @(negedge core_0_clk);
+             @(negedge core_1_clk);
+             @(negedge io_master_clk);
+          end
+
+        core_0_reset = 0;
+        core_1_reset = 0;
+
+        $display("__________ ___________  _______________________________");
+        $display("\\______   \\\\_   _____/ /   _____/\\_   _____/\\__    ___/");
+        $display(" |       _/ |    __)_  \\_____  \\  |    __)_   |    |   ");
+        $display(" |    |   \\ |        \\ /        \\ |        \\  |    |   ");
+        $display(" |____|_  //_______  //_______  //_______  /  |____|   ");
+        $display("        \\/         \\/         \\/         \\/            ");
+     end
+
+   //**********************************************************************
+   //  CORE 0 (sender)
+   //    ______ _____  ______  _______    _______ _______ ______   _____
+   //   / _____) ___ \(_____ \(_______)  (_______|_______|_____ \ / ___ \
+   //  | /    | |   | |_____) )_____        __    _____   _____) ) |   | |
+   //  | |    | |   | (_____ (|  ___)      / /   |  ___) (_____ (| |   | |
+   //  | \____| |___| |     | | |_____    / /____| |_____      | | |___| |
+   //   \______)_____/      |_|_______)  (_______)_______)     |_|\_____/
+   //
+   //**********************************************************************
+
+   wire core_0_reset_sync, io_master_reset_sync, token_reset_sync;
+
+   // reset synchronizer: core clock reset
+   bsg_sync_sync #(.width_p(1)) bss_core_reset
+     (.oclk_i(core_0_clk)
+      ,.iclk_data_i(core_0_reset)
+      ,.oclk_data_o(core_0_reset_sync)
+      );
+
+   // reset synchronizer: master clock reset
+   bsg_sync_sync #(.width_p(1)) bss_io_master_reset
+     (.oclk_i(io_master_clk)
+      ,.iclk_data_i(core_0_reset)
+      ,.oclk_data_o(io_master_reset_sync)
+      );
+
+   // reset synchronizer: token reset
+   bsg_sync_sync #(.width_p(1)) bss_token_reset
+     (.oclk_i(io_master_clk)
+      ,.iclk_data_i(core_0_reset)
+      ,.oclk_data_o(token_reset_sync)
+      );
+
+   logic [channel_width_lp-1:0] core_0_data_r;
+   logic core_0_valid_r;
+
+   // wait a certain number of cycles after reset before restarting
+   localparam lg_wait_cycles_activate_lp = 4;
+   wire  core_reset_ready;
+
+   bsg_wait_after_reset #(.lg_wait_cycles_p(lg_wait_cycles_activate_lp)) bwar
+     (.reset_i(core_0_reset_sync)
+      ,.clk_i(core_0_clk)
+      ,.ready_r_o(core_reset_ready)
+      );
+
+   // only start sending after a certain number of cycles
+   assign core_0_valid_r = core_reset_ready;
+
+   wire  core_0_assembler_ready;
+   wire  core_0_yumi = core_0_assembler_ready & core_0_valid_r;
+
+   // transmit sequence of data values
+   always @(posedge core_0_clk)
+     if (core_0_reset_sync)
+       core_0_data_r <= 0;
+     else
+       if (core_0_yumi)
+         core_0_data_r <= core_0_data_r + 1;
+
+
+   // ***********************************************
+   // TOKEN RESET LOGIC
+   //
+   // reset logic for clearing output channel's
+   // token-clocked logic.
+   //
+
+   logic io_override_en;
+   logic [channel_width_lp+1-1:0] io_override_valid_data;
+   logic                          io_master_reset_sync_r;
+   logic [10:0]                   io_reset_counter_r;
+
+   always @(posedge io_master_clk)
+     begin
+        io_master_reset_sync_r <= io_master_reset_sync;
+
+        // on positive edge of reset, we initialize the counter
+        // the counter continuously counts during reset
+        // and is zero'd when not in reset
+        if (io_master_reset_sync)
+          begin
+             if (~io_master_reset_sync_r)
+               io_reset_counter_r <= 1;
+             else
+               io_reset_counter_r <= io_reset_counter_r + 1;
+          end
+        else
+          io_reset_counter_r <= 0;
+     end
+
+   // this asserts the override data while the reset counter
+   // is in its active portion
+
+   always_comb
+     begin
+        io_override_en = io_master_reset_sync;
+        io_override_valid_data = { 0'b0, 0'h00 };
+
+        // for 2^6 cycles, assert the "token reset code"
+        if (io_reset_counter_r[10:6] == 5'b00001)
+          io_override_valid_data = { 1'b1, 8'h80 };
+     end
+
+   // entertainingly, we need to label both sides
+   // of the if statement the same thing in order
+   // to have the variable top_active_channel
+   // resolve later in the file (to xkr.top_active_channel)
+   if (num_channels_lp < 2)
+     begin: xkr
+        wire top_active_channel = 1'b0;
+     end
+   else
+     begin: xkr
+        wire [$clog2(num_channels_lp)-1:0] top_active_channel
+          = $clog2(num_channels_lp)' (num_channels_lp-1'b1);
+     end
+
+   genvar i;
+
+   wire [channel_width_lp-1:0] core_0_send_data [ring_bytes_lp-1:0];
+
+   localparam lg_ring_bytes_lp = $clog2(ring_bytes_lp);
+
+   wire [$max(lg_ring_bytes_lp-1,0):0] ring_bytes
+                                       = $max(lg_ring_bytes_lp,1) ' (ring_bytes_lp);
+
+   if (ring_bytes_lp > 1)
+     for (i = 0; i < ring_bytes_lp; i++)
+       begin
+          wire [lg_ring_bytes_lp-1:0] my_id = i[lg_ring_bytes_lp-1:0];
+          assign core_0_send_data[i]
+            = { my_id, core_0_data_r[0+:channel_width_lp-lg_ring_bytes_lp]};
+       end
+   else
+     assign core_0_send_data[0] = core_0_data_r;
+
+   // ***********************************************
+   //
+   // out assembler
+   //
+   //
+
+   wire [num_channels_lp-1:0]  channel_valids;
+   wire [num_channels_lp-1:0]  channel_readys;
+   wire [channel_width_lp-1:0] channel_datas [num_channels_lp-1:0];
+
+   // de-bond channel into multiple individual channels
+   bsg_assembler_out #(.width_p(channel_width_lp)
+                       ,.num_in_p(ring_bytes_lp)
+                       ,.num_out_p(num_channels_lp)
+                       ,.out_channel_count_mask_p(1 << (num_channels_lp-1)) // fixme
+                       ) bao
+   (.clk(core_0_clk)
+    ,.reset(core_0_reset_sync)
+    ,.valid_i(core_0_valid_r)
+    ,.data_i(core_0_send_data )
+    ,.ready_o(core_0_assembler_ready)
+
+    ,.in_top_channel_i(ring_bytes-1'b1)
+    ,.out_top_channel_i(xkr.top_active_channel)
+
+    ,.valid_o(channel_valids)
+    ,.data_o( channel_datas)
+    ,.ready_i(channel_readys)
+    );
+
+   // ***********************************************
+   // declare signals going out over transmission lines
+   // between input and output channel
+   //
+
+   wire [num_channels_lp-1:0]  io_clk_tline, io_valid_tline;
+   wire [channel_width_lp-1:0] io_data_tline [num_channels_lp-1:0];
+   wire [num_channels_lp-1:0]  token_clk_tline;
+
+
+   // create a bunch of channels
+   for (i = 0; i < num_channels_lp; i=i+1)
+     begin: bsso
+        bsg_source_sync_output
+            #(.lg_start_credits_p(lg_input_fifo_depth_lp)
+              ,.lg_credit_to_token_decimation_p(lg_credit_to_token_decimation_lp)
+              ,.channel_width_p(channel_width_lp)
+              ) bsso
+            (.core_clk_i(core_0_clk)
+             ,.core_reset_i(core_0_reset_sync)
+
+             // core 0 side logical signals
+             ,.core_data_i(channel_datas[i])
+             ,.core_valid_i(channel_valids[i])
+             ,.core_ready_o(channel_readys[i])
+
+             ,.io_master_clk_i(io_master_clk)
+             ,.io_reset_i(io_master_reset_sync)
+
+             ,.io_override_en_i(io_override_en)
+             ,.io_override_valid_data_i(io_override_valid_data)
+
+             ,.io_clk_r_o(io_clk_tline[i])                // output to other node
+             ,.io_data_r_o(io_data_tline[i])              // output to other node
+             ,.io_valid_r_o(io_valid_tline[i])            // output to other node
+
+             ,.token_clk_i(token_clk_tline[i])            // input from other node
+             // from core 0  // fixme is this signal correctly named?
+             ,.token_reset_i(token_reset_sync)
+      );
+
+     end
+
+   //************************************************************
+   //  CORE 1 (input side)
+   //   ______ _____  ______  _______     _____  ______  _______
+   //  / _____) ___ \(_____ \(_______)   / ___ \|  ___ \(_______)
+   // | /    | |   | |_____) )_____     | |   | | |   | |_____
+   // | |    | |   | (_____ (|  ___)    | |   | | |   | |  ___)
+   // | \____| |___| |     | | |_____   | |___| | |   | | |_____
+   //  \______)_____/      |_|_______)   \_____/|_|   |_|_______)
+   //
+   //************************************************************
+
+   localparam lg_io_delay_reset_lp = 6;
+
+   wire [num_channels_lp-1:0] io_1_reset_sync;
+   wire core_1_reset_sync;
+
+   bsg_sync_sync #(.width_p(1)) bss_core_1_reset
+     (.oclk_i(core_1_clk)
+      ,.iclk_data_i(core_1_reset)
+      ,.oclk_data_o(core_1_reset_sync)
+      );
+
+
+   wire [num_channels_lp-1:0]  core_1_assembler_yumi;
+   wire [num_channels_lp-1:0]  core_1_assembler_valid;
+   wire [channel_width_lp-1:0] core_1_assembler_data [num_channels_lp-1:0];
+
+   // merged channel
+   wire                        core_1_valid, core_1_yumi;
+   wire [channel_width_lp*ring_bytes_lp-1:0] core_1_data;
+
+   // create a bunch of channels
+   for (i = 0; i < num_channels_lp; i=i+1)
+     begin
+        bsg_sync_sync #(.width_p(1)) bss_io_1_reset
+            (.oclk_i(io_clk_tline[i])
+             ,.iclk_data_i(core_1_reset)
+             ,.oclk_data_o(io_1_reset_sync[i])
+             );
+
+        bsg_source_sync_input
+          #(.lg_fifo_depth_p(lg_input_fifo_depth_lp)
+            ,.lg_credit_to_token_decimation_p(lg_credit_to_token_decimation_lp)
+            ,.channel_width_p(channel_width_lp)
+            ) bssi
+            (.io_clk_i(io_clk_tline[i])               // input from other node; starts on reset
+             ,.io_reset_i(io_1_reset_sync[i])
+             ,.io_data_i(io_data_tline[i])      // input from other node
+             ,.io_valid_i(io_valid_tline[i])    // input from other node
+
+             ,.io_edge_i(2'b11)                 // latch on both edges
+
+             ,.io_token_r_o(token_clk_tline[i]) // output to other node
+
+             ,.io_snoop_r_o()                // snoop input channel;
+                                             // for establishing calibration state
+                                             // on reset
+
+             ,.io_trigger_mode_en_i(1'b0)        // enable loop-back trigger mode
+             ,.io_trigger_mode_alt_en_i(1'b0)    // enable loop-back trigger mode: alternate trigger
+
+             ,.core_clk_i(core_1_clk)
+             ,.core_reset_i(core_1_reset_sync)
+
+             // core 1 side logical signals
+             ,.core_data_o(core_1_assembler_data[i])
+             ,.core_valid_o(core_1_assembler_valid[i])
+             ,.core_yumi_i(core_1_assembler_yumi[i])
+             );
+     end
+
+   // merge them into one bonded channel
+   bsg_assembler_in #(.width_p(channel_width_lp)
+                       ,.num_in_p(num_channels_lp)
+                       ,.num_out_p(ring_bytes_lp)
+                       ,.in_channel_count_mask_p(1 << (num_channels_lp-1)) // fixme
+                       ) bai
+   (.clk(core_1_clk)
+    ,.reset(core_1_reset_sync)
+    ,.valid_i(core_1_assembler_valid)
+    ,.data_i(core_1_assembler_data)
+    ,.yumi_o(core_1_assembler_yumi)
+
+    ,.in_top_channel_i(xkr.top_active_channel)
+    ,.out_top_channel_i(ring_bytes-1'b1)
+
+    ,.valid_o(core_1_valid)
+    ,.data_o(core_1_data)
+    ,.yumi_i(core_1_yumi)
+    );
+
+   // consume all data
+   assign core_1_yumi = core_1_valid;
+
+   localparam cycle_counter_width_lp=32;
+
+   logic [cycle_counter_width_lp-1:0] core_0_ctr;
+   bsg_cycle_counter #(.width_p(cycle_counter_width_lp))
+   bcc_core0 (core_0_clk, core_0_reset_sync, core_0_ctr);
+
+   logic [cycle_counter_width_lp-1:0] core_1_ctr;
+   bsg_cycle_counter #(.width_p(cycle_counter_width_lp))
+   bcc_core1 (core_1_clk, core_1_reset_sync, core_1_ctr);
+
+   logic [cycle_counter_width_lp-1:0] io_ctr;
+   bsg_cycle_counter #(.width_p(cycle_counter_width_lp))
+   bcc_io (io_master_clk, io_master_reset_sync, io_ctr);
+
+
+   // non-synthesizable, TEST ONLY
+   logic [7:0] core_1_last_n, core_1_last_r = -1;
+   logic [5:0] top_bits = 0;
+
+   assign core_1_last_n = core_1_last_r+8'b1;
+
+   wire [ring_bytes_lp*channel_width_lp-1:0] core_1_check_data;
+
+   if (ring_bytes_lp > 1)
+     for (i = 0; i < ring_bytes_lp; i++)
+       begin
+          wire [lg_ring_bytes_lp-1:0] my_id = i[lg_ring_bytes_lp-1:0];
+          assign core_1_check_data[channel_width_lp*i+:channel_width_lp]
+            = { my_id, core_1_last_n[0+:channel_width_lp-lg_ring_bytes_lp]};
+       end
+   else
+     assign core_1_check_data = core_1_last_n;
+
+   // *******************************************************
+   // *
+   // * Logging.
+   // *
+   // * These statements allow you to see, in time, when values
+   // * are transmitted and received.
+   // *
+   // *
+   // * For this test, the number of cycles on the slowest clock should
+   // * match the number of words
+   // * transmitted plus a small constant.
+   // *
+   // *
+
+   logic [31:0]                       core_1_words_received_r;
+
+   always @(negedge core_1_clk)
+     if (core_1_reset_sync)
+       core_1_words_received_r <= 0;
+     else
+       core_1_words_received_r <= core_1_words_received_r + core_1_valid;
+
+   integer                            verbose = 0;
+
+   always @(negedge core_1_clk)
+     if (core_1_valid)
+       begin
+          if (verbose)
+            $display("## ", core_0_ctr, io_ctr, core_1_ctr
+                     , " ## core 1 recv %d, %x",top_bits,core_1_data);
+
+          assert (core_1_check_data == core_1_data)
+            else $error("## transmission error %x, %x"
+                        , core_1_check_data, core_1_data);
+          core_1_last_r <= core_1_last_n;
+          if (core_1_last_n == 8'hff)
+            begin
+               if (top_bits == iterations_lp)
+                 begin
+                    $display("## DONE CHANNEL_WIDTH=%1d",channel_width_lp
+                             ," RING_BYTES=%2d",ring_bytes_lp
+                             ," NUM_CHAN=%1d",num_channels_lp
+                             ," C0_HP=%1d",core_0_half_period_lp
+                             ," IO_HP=%1d",io_master_half_period_lp
+                             ," C1_PD=%1d",core_1_half_period_lp,
+                             ," (Cycles Per Word) "
+                             , real'(core_0_ctr) / real'(core_1_words_received_r)," "
+                             , real'(io_ctr) / real'(core_1_words_received_r), " "
+                             , real'(core_1_ctr) / real'(core_1_words_received_r));
+                    $finish("##");
+                 end
+               top_bits = top_bits+1;
+            end
+       end
+
+   always @(negedge core_0_clk)
+     if (core_0_yumi)
+       if (verbose)
+         $display("## ", core_0_ctr, io_ctr, core_1_ctr
+                  , " ## core 0 sent %lx",core_0_send_data);
+
+   for (i = 0; i < num_channels_lp; i=i+1)
+     begin
+        always @(negedge io_master_clk)
+          if (verbose)
+            begin
+               if (io_valid_tline[i])
+                 $display("## ", core_0_ctr, io_ctr, core_1_ctr
+                          , " ## channel %1d", i
+                          , " (p,n)=(%2d",bsso[i].bsso.bacc1.r_free_credits
+                          ,",%2d",bsso[i].bsso.bacc2.r_free_credits,") "
+                          ," ## io     xmit %x",io_data_tline[i]);
+               else
+                 $display("## ", core_0_ctr, io_ctr, core_1_ctr
+                          , " ## channel %1d", i, " (p,n)=(%2d"
+                          ,bsso[i].bsso.bacc1.r_free_credits
+                          ,",%2d",bsso[i].bsso.bacc2.r_free_credits,") ");
+            end
+     end
+endmodule
+

snapshots/bespoke-silicon-group_basejump_stl_pr706/bsg_comm_link/tests/test_bsg_comm_link/test_bsg_comm_link.sv

@@ -0,0 +1,307 @@
+
+`include "bsg_defines.sv"
+
+`include "test_assembler_defines.sv"
+
+module test_bsg_comm_link;
+
+`include "test_bsg_clock_params.sv"
+
+
+   // number of bits width of a channel
+   // must be >= 3; with channel_width = 3
+   // calibration will be limited
+
+   localparam channel_width_lp         = `CHANNEL_WIDTH;
+   localparam num_channels_lp          = `NUM_CHANNELS;
+
+   // this is the number of bytes that a ring packet is
+   localparam ring_bytes_lp            = `RING_BYTES;
+
+   localparam iterations_lp            = `ITERATIONS;
+
+   localparam verbose_lp  = 1;
+
+   // most flexible configuration for assembler
+   // any subset of channels (4,3,2,1) may be used
+   localparam channel_mask_lp          = (1 << num_channels_lp) - 1;
+
+   genvar                      i,j;
+
+   // *************************************************
+   // independent clocks and reset
+   //
+   //
+
+   logic [1:0] core_clk;
+   logic [1:0] io_master_clk;
+
+   test_bsg_clock_gen #(.cycle_time_p(core_0_period_lp))  c0_clk    (.o(     core_clk[0]));
+   test_bsg_clock_gen #(.cycle_time_p(core_1_period_lp))  c1_clk    (.o(     core_clk[1]));
+
+   initial
+     $display("%m creating clocks",core_0_period_lp, core_1_period_lp, io_master_0_period_lp, io_master_1_period_lp);
+
+   test_bsg_clock_gen #(.cycle_time_p(io_master_0_period_lp)) i0_clk (.o(io_master_clk[0]));
+   test_bsg_clock_gen #(.cycle_time_p(io_master_1_period_lp)) i1_clk (.o(io_master_clk[1]));
+
+
+   logic async_reset;
+
+   localparam core_reset_cycles_hi_lp = 256;
+   localparam core_reset_cycles_lo_lp = 16;
+
+   test_bsg_reset_gen
+     #(.num_clocks_p(4)
+       ,.reset_cycles_lo_p(core_reset_cycles_lo_lp)
+       ,.reset_cycles_hi_p(core_reset_cycles_hi_lp)
+       ) reset_gen
+   (.clk_i({ core_clk, io_master_clk })
+    ,.async_reset_o(async_reset)
+    );
+
+   // Defines for Core Zero and One
+
+   wire [1:0]                                core_reset_in;
+   wire [1:0]                                core_calib_reset;
+
+   wire [1:0]                                core_valid_out;
+   wire [ring_bytes_lp*channel_width_lp-1:0] core_data_out [1:0];
+   wire [1:0]                                core_yumi_out;
+
+   wire [1:0]                                core_valid_in;
+   wire [ring_bytes_lp*channel_width_lp-1:0] core_data_in  [1:0];
+   wire [1:0]                                core_ready_in;
+
+  //**********************************************************************
+   //  CORE 0 (sender)
+   //    ______ _____  ______  _______    _______ _______ ______   _____
+   //   / _____) ___ \(_____ \(_______)  (_______|_______|_____ \ / ___ \
+   //  | /    | |   | |_____) )_____        __    _____   _____) ) |   | |
+   //  | |    | |   | (_____ (|  ___)      / /   |  ___) (_____ (| |   | |
+   //  | \____| |___| |     | | |_____    / /____| |_____      | | |___| |
+   //   \______)_____/      |_|_______)  (_______)_______)     |_|\_____/
+   //
+   //**********************************************************************
+
+
+   // CORE ZERO Send (speaking valid/ready protocol)
+   // core_ready signal will be held low by comm_link
+   // module until calibration is done.
+
+   assign core_valid_out[0] = ~core_reset_in[0];
+
+   test_bsg_data_gen #(.channel_width_p(channel_width_lp)
+                       ,.num_channels_p(ring_bytes_lp)
+                       ) tbdg_send
+   (.clk_i(core_clk[0]      )
+    ,.reset_i(core_reset_in[0]) // this is a core, so should be woken up
+                                // when cores wakeup
+    ,.yumi_i (core_yumi_out[0])
+    ,.o      (core_data_out[0])
+    );
+
+   // CORE ZERO Receive (speaking valid/yumi protocol)
+   //
+
+   // always eat the data
+   assign core_ready_in[0] = 1'b1;
+
+
+   //************************************************************
+   //  CORE 1 (input side)
+   //   ______ _____  ______  _______     _____  ______  _______
+   //  / _____) ___ \(_____ \(_______)   / ___ \|  ___ \(_______)
+   // | /    | |   | |_____) )_____     | |   | | |   | |_____
+   // | |    | |   | (_____ (|  ___)    | |   | | |   | |  ___)
+   // | \____| |___| |     | | |_____   | |___| | |   | | |_____
+   //  \______)_____/      |_|_______)   \_____/|_|   |_|_______)
+   //
+   //************************************************************
+
+
+   logic  [1:0]                  core_async_reset, core_async_reset_r;
+
+   bsg_two_fifo #( .width_p(channel_width_lp*ring_bytes_lp)) core_one_fifo
+     (.clk_i(core_clk[1])
+
+      ,.reset_i(core_reset_in[1])
+
+      ,.ready_param_o(core_ready_in[1])
+      ,.v_i    (core_valid_in[1])
+      ,.data_i (core_data_in [1])
+
+      ,.v_o   (core_valid_out[1])
+      ,.data_o(core_data_out [1])
+      ,.yumi_i(core_yumi_out [1])
+      );
+
+   always @(posedge io_master_clk[1])
+     begin
+        core_async_reset_r[1] <= core_async_reset[1];
+        if (~core_async_reset[1] & core_async_reset_r[1])
+          begin
+             $display("            _                                       ");
+             $display("           (_)                                  _   ");
+             $display(" _____  ___ _  ____     ____ _____  ___ _____ _| |_ ");
+             $display("(____ |/___) |/ ___)   / ___) ___ |/___) ___ (_   _)");
+             $display("/ ___ |___ | ( (___   | |   | ____|___ | ____| | |_ ");
+             $display("\\_____(___/|_|\\____)  |_|   |_____|___/|_____)  \\__)");
+             $display("                                                    ");
+          end
+     end
+
+
+   //************************************************************
+   //  CORE 1 (input side)
+   //   ______ _____  ______  _______     ______              __
+   //  / _____) ___ \(_____ \(_______)   / __   |     _      /  |
+   // | /    | |   | |_____) )_____     | | //| |   _| |_   /_/ |
+   // | |    | |   | (_____ (|  ___)    | |// | |  (_   _)    | |
+   // | \____| |___| |     | | |_____   |  /__| |    |_|      | |
+   //  \______)_____/      |_|_______)   \_____/              |_|
+   //
+   //************************************************************
+
+   // external signals
+   logic [num_channels_lp-1:0]  io_clk_tline  [1:0], io_valid_tline [1:0];
+   logic [channel_width_lp-1:0] io_data_tline [1:0] [num_channels_lp-1:0];
+   logic [num_channels_lp-1:0]  token_clk_tline                     [1:0];
+   wire [1:0]                  slave_reset_tline;
+
+
+   //************************************************************
+   // BREAK PCB WIRES HERE.
+   //
+   // modify these lines to test stuck-at faults due to assembly
+   // issues or just even bad silicon.
+   //
+   // watch this crazy thing adapt to faults!
+   //
+
+   // A. to FPGA
+
+   // always @(io_data_tline[1][0]) force io_data_tline[1][0][channel_width_lp-1] = 1; // 0
+   // always @(io_data_tline[1][0]) force io_data_tline[1][1][channel_width_lp-1] = 1; // 1
+   // always @(io_data_tline[1][0]) force io_data_tline[1][2][channel_width_lp-1] = 1; // 2
+   // always @(io_data_tline[1][0]) force io_data_tline[1][3][channel_width_lp-1] = 1; // 3
+
+   // always @(io_data_tline[1][0]) force io_data_tline[0][0][channel_width_lp-1] = 1;
+   // always @(io_data_tline[1][0]) force io_data_tline[0][1][channel_width_lp-1] = 1; // 1
+   // always @(io_data_tline[1][0]) force io_data_tline[0][2][channel_width_lp-2] = 1; // 2
+
+   // B. to ASIC
+
+   // also: test contamination of calibration code
+   // always @(io_data_tline[1][0]) force io_data_tline[0][3][channel_width_lp-1] = 0; //  3
+   // always @(io_data_tline[1][0]) force io_valid_tline[0][3] = 1;  //  3
+
+   for (i = 0; i < 2; i++)
+     begin : core
+
+        wire [ring_bytes_lp*channel_width_lp-1:0] core_node_data_lo [0:0];
+        wire [ring_bytes_lp*channel_width_lp-1:0] core_node_data_li [0:0];
+
+        // type translation
+        assign core_data_in     [i] = core_node_data_lo[0];
+        assign core_node_data_li[0] = core_data_out    [i];
+
+        // convention: for signals going between cores
+        // the "from core" is used as the index.
+
+        bsg_comm_link #(.channel_width_p  (channel_width_lp)
+                        , .core_channels_p   (ring_bytes_lp)
+                        , .link_channels_p (num_channels_lp)
+                        , .nodes_p(1)
+                        , .channel_mask_p(channel_mask_lp)
+                        , .master_p(!i)
+                        , .master_to_slave_speedup_p(master_to_slave_speedup_lp)
+                        , .snoop_vec_p(1'b1)           // ignore packet formats
+                        , .enabled_at_start_vec_p(1'b1) // enable at start
+                        , .master_bypass_test_p(5'b1_1_1_1_1)
+                        ) comm_link
+          (.core_clk_i           (core_clk        [i] )
+           , .async_reset_i      ( (i ? slave_reset_tline[0] : async_reset) )
+           , .core_calib_reset_r_o(core_calib_reset [i] )
+
+           , .io_master_clk_i    (io_master_clk   [i] )
+
+           // in from core
+           , .core_node_v_i(core_valid_out [i])
+           , .core_node_data_i(core_node_data_li)
+           , .core_node_yumi_o(core_yumi_out[i])
+
+           // out to core
+           , .core_node_v_o(core_valid_in    [i])
+           , .core_node_data_o(core_node_data_lo)
+           , .core_node_ready_i(core_ready_in [i])
+
+           // ignore enable and reset.
+           , .core_node_en_r_o()
+           , .core_node_reset_r_o(core_reset_in[i])
+
+           // in from i/o
+           , .io_valid_tline_i(      io_valid_tline [!i])
+           , .io_data_tline_i(        io_data_tline [!i])
+           , .io_clk_tline_i(          io_clk_tline [!i])  // clk
+           , .io_token_clk_tline_o( token_clk_tline [i] )  // clk
+
+           // out to i/o
+           , .im_valid_tline_o(io_valid_tline[i])
+           , .im_data_tline_o(  io_data_tline[i])
+           , .im_clk_tline_o(    io_clk_tline[i])             // clk
+
+           , .im_slave_reset_tline_r_o ( slave_reset_tline[i])
+           , .token_clk_tline_i(token_clk_tline[!i])          // clk
+
+           // use core_calib_reset instead!
+           , .core_async_reset_danger_o (core_async_reset      [i] )
+           );
+     end
+
+   localparam cycle_counter_width_lp=32;
+
+   // create some counters to track the four clocks in the system
+   logic [cycle_counter_width_lp-1:0] core_ctr[1:0];
+   logic [cycle_counter_width_lp-1:0] io_ctr  [1:0];
+
+   // valid only in testbench code: reset violation
+
+   for (i = 0; i < 2; i=i+1)
+     begin
+	bsg_cycle_counter #(.width_p(cycle_counter_width_lp))
+	my_core_ctr (.clk_i(core_clk[i]), .reset_i(core_calib_reset[i]), .ctr_r_o(core_ctr[i]));
+
+	bsg_cycle_counter #(.width_p(cycle_counter_width_lp))
+	my_io_ctr   (.clk_i(io_master_clk[i]), .reset_i(core_calib_reset[i]), .ctr_r_o(io_ctr[i]));
+
+        test_bsg_comm_link_checker
+            #(.channel_width_p(channel_width_lp)
+              ,.num_channels_p(num_channels_lp)
+              ,.ring_bytes_p  (ring_bytes_lp)
+              ,.verbose_p     (verbose_lp)
+              ,.iterations_p  (iterations_lp)
+              ,.core_0_period_p(core_0_period_lp)
+              ,.core_1_period_p(core_1_period_lp)
+              ,.io_master_0_period_p(io_master_0_period_lp)
+              ,.io_master_1_period_p(io_master_1_period_lp)
+              ,.cycle_counter_width_p(cycle_counter_width_lp)
+	      ,.node_num_p(i)
+              ) checker
+            (.clk           (core_clk[i])
+             ,.valid_in(core_valid_in[i])
+             ,.ready_in(core_ready_in[i])
+             ,.data_in (core_data_in[i] )
+             ,.data_out(core_data_out[i])
+             ,.yumi_out(core_yumi_out[i])
+             ,.async_reset(core_async_reset[i])
+             ,.slave_reset_tline(slave_reset_tline[i])
+             ,.io_valid_tline(io_valid_tline[i])
+             ,.io_data_tline (io_data_tline[i])
+	     ,.core_ctr(core_ctr)
+	     ,.io_ctr(io_ctr)
+             );
+     end
+
+ endmodule
+

snapshots/bespoke-silicon-group_basejump_stl_pr706/bsg_comm_link/tests/test_bsg_source_sync/Makefile

@@ -0,0 +1,27 @@
+export LM_LICENSE_FILE = 27000@bbfs-00.calit2.net
+export SYNOPSYS_DIR=/gro/cad/synopsys
+export VCS_RELEASE=vcs/G-2012.09-SP1
+export VCS_HOME = $(SYNOPSYS_DIR)/$(VCS_RELEASE)
+export VCS_BIN = $(VCS_HOME)/bin
+export DVE_BIN = $(VCS_HOME)/bin
+
+
+ASYNC_FILES = bsg_async_credit_counter.sv bsg_async_fifo.sv bsg_async_ptr_gray.sv bsg_gray_to_binary.sv bsg_launch_sync_sync.sv bsg_sync_sync.sv bsg_wait_after_reset.sv 
+SOURCE_SYNC_FILES = bsg_source_sync_input.sv bsg_source_sync_output.sv bsg_cycle_counter.sv
+TEST_FILES = test_bsg_source_sync.sv
+
+
+all:  $(foreach x,$(ASYNC_FILES),../bsg_async_fifo/$(x)) $(SOURCE_SYNC_FILES) $(TEST_FILES)
+	$(VCS_BIN)/vcs -PP -full64 +lint=all +v2k -sverilog -timescale=1ns/10ps $^
+
+run:
+	./simv
+
+dve:
+	$(DVE_BIN)/dve -full64 -vpd vcdplus.vpd &
+
+%.echo:
+	echo $($*)
+
+clean:
+	rm -rf simv csrc simv.daidir

snapshots/bespoke-silicon-group_basejump_stl_pr706/bsg_comm_link/tests/test_bsg_source_sync/test_bsg_source_sync.sv

@@ -0,0 +1,343 @@
+// MBT 7-28-2014
+//
+// Test source synchronous link.
+//
+// We model here two cores that have different clocks and are
+// communicating over an I/O channel which has a third clock.
+//
+// Includes model reset logic with synchronizers and delayed
+// communication after reset.
+//
+
+`include "bsg_defines.sv"
+
+module test_bsg_source_sync_input;
+
+   initial begin
+      $vcdpluson;
+      end
+
+   // three separate clocks: I/O, and the two cores communicating with each other
+   localparam core_0_half_period_lp = 5;
+   localparam io_master_half_period_lp = 7;
+   localparam core_1_half_period_lp = 6;
+
+   // across all frequency combinations, we need a little over 20 fifo slots
+   // so we round up to 32.
+
+   localparam lg_input_fifo_depth_lp = 5;
+
+   // for DDR at 500 mbps, we make token go at / 8 = 66 mbps
+   // this will keep the token clock nice and slow
+
+   localparam lg_credit_to_token_decimation_lp=3;
+
+   // number of bits width of a channel
+   localparam channel_width_lp=8;
+
+   // *************************************************
+   // independent clocks
+   //
+   //
+
+   logic core_0_clk, core_1_clk, io_master_clk;
+
+   initial core_0_clk = 0;
+   always #(core_0_half_period_lp) core_0_clk = ~core_0_clk;
+
+
+   initial io_master_clk = 0;
+   always #(io_master_half_period_lp) io_master_clk = ~io_master_clk;
+
+   initial core_1_clk = 0;
+   always #(core_1_half_period_lp) core_1_clk = ~core_1_clk;
+
+
+   // *************************************************
+   // master resets
+   //
+
+   logic core_0_reset, core_1_reset;
+
+   localparam core_reset_cycles_hi_lp = 256;
+   localparam core_reset_cycles_lo_lp = 16;
+
+   // we model this as if the FPGA is driving this with an unknown clock.
+   initial
+     begin
+        core_0_reset = 0;
+        core_1_reset = 0;
+        // simple hack to wait based on maximum of clock periods
+        repeat (core_reset_cycles_lo_lp)
+          begin
+             @(negedge core_0_clk);
+             @(negedge core_1_clk);
+             @(negedge io_master_clk);
+          end
+
+        core_0_reset = 1;
+        core_1_reset = 1;
+        // simple hack to wait based on maximum of clock periods
+        repeat (core_reset_cycles_hi_lp)
+          begin
+             @(negedge core_0_clk);
+             @(negedge core_1_clk);
+             @(negedge io_master_clk);
+          end
+
+        core_0_reset = 0;
+        core_1_reset = 0;
+
+        $display("__________ ___________  _______________________________");
+        $display("\\______   \\\\_   _____/ /   _____/\\_   _____/\\__    ___/");
+        $display(" |       _/ |    __)_  \\_____  \\  |    __)_   |    |   ");
+        $display(" |    |   \\ |        \\ /        \\ |        \\  |    |   ");
+        $display(" |____|_  //_______  //_______  //_______  /  |____|   ");
+        $display("        \\/         \\/         \\/         \\/            ");
+     end
+
+   // *****************************************
+   // * CORE 0 (sender)
+   // *
+   // *
+   // *
+
+   wire core_0_reset_sync, io_master_reset_sync, token_reset_sync;
+
+   // reset synchronizer: core clock reset
+   bsg_sync_sync #(.width_p(1)) bss_core_reset
+     (.oclk_i(core_0_clk)
+      ,.iclk_data_i(core_0_reset)
+      ,.oclk_data_o(core_0_reset_sync)
+      );
+
+   // reset synchronizer: master clock reset
+   bsg_sync_sync #(.width_p(1)) bss_io_master_reset
+     (.oclk_i(io_master_clk)
+      ,.iclk_data_i(core_0_reset)
+      ,.oclk_data_o(io_master_reset_sync)
+      );
+
+   // reset synchronizer: token reset
+   bsg_sync_sync #(.width_p(1)) bss_token_reset
+     (.oclk_i(io_master_clk)
+      ,.iclk_data_i(core_0_reset)
+      ,.oclk_data_o(token_reset_sync)
+      );
+
+   logic [channel_width_lp-1:0] core_0_data_r;
+   logic core_0_valid_r;
+
+   // wait a certain number of cycles after reset before restarting
+   localparam lg_wait_cycles_activate_lp = 4;
+   wire  core_reset_ready;
+
+   bsg_wait_after_reset #(.lg_wait_cycles_p(lg_wait_cycles_activate_lp)) bwar
+     (.reset_i(core_0_reset_sync)
+      ,.clk_i(core_0_clk)
+      ,.ready_r_o(core_reset_ready)
+      );
+
+   // only start sending after a certain number of cycles
+   assign core_0_valid_r = core_reset_ready;
+   wire  core_0_yumi;
+
+   // transmit sequence of data values
+   always @(posedge core_0_clk)
+     if (core_0_reset_sync)
+       core_0_data_r <= 0;
+     else
+       if (core_0_yumi)
+         core_0_data_r <= core_0_data_r + 1;
+
+
+   // ***********************************************
+   // TOKEN RESET LOGIC
+   //
+   // reset logic for clearing output channel's
+   // token-clocked logic.
+   //
+
+   logic io_override_en;
+   logic [channel_width_lp+1-1:0] io_override_valid_data;
+   logic                          io_master_reset_sync_r;
+   logic [10:0]                   io_reset_counter_r;
+
+   always @(posedge io_master_clk)
+     begin
+        io_master_reset_sync_r <= io_master_reset_sync;
+
+        // on positive edge of reset, we initialize the counter
+        // the counter continuously counts during reset
+        // and is zero'd when not in reset
+        if (io_master_reset_sync)
+          begin
+             if (~io_master_reset_sync_r)
+               io_reset_counter_r <= 1;
+             else
+               io_reset_counter_r <= io_reset_counter_r + 1;
+          end
+        else
+          io_reset_counter_r <= 0;
+     end
+
+   // this asserts the override data while the reset counter
+   // is in its active portion
+
+   always_comb
+     begin
+        io_override_en = io_master_reset_sync;
+        io_override_valid_data = { 0'b0, 0'h00 };
+
+        // for 2^6 cycles, assert the "token reset code"
+        if (io_reset_counter_r[10:6] == 5'b00001)
+          io_override_valid_data = { 1'b1, 8'h80 };
+     end
+
+   // ***********************************************
+   // declare signals going out over transmission lines
+   // between input and output channel
+   //
+
+   wire io_clk_tline, io_valid_tline;
+   wire [channel_width_lp-1:0] io_data_tline;
+   wire token_clk_tline;
+
+   bsg_source_sync_output #(.lg_start_credits_p(lg_input_fifo_depth_lp)
+                            ,.lg_credit_to_token_decimation_p(lg_credit_to_token_decimation_lp)
+                            ,.channel_width_p(channel_width_lp)
+                            ) bsso_o1
+     (.core_clk_i(core_0_clk)
+      ,.core_reset_i(core_0_reset_sync)
+
+      // core 0 side logical signals
+      ,.core_data_i(core_0_data_r)
+      ,.core_valid_i(core_0_valid_r)
+      ,.core_yumi_o(core_0_yumi)
+
+      ,.io_master_clk_i(io_master_clk)
+      ,.io_reset_i(io_master_reset_sync)
+
+      ,.io_override_en_i(io_override_en)
+      ,.io_override_valid_data_i(io_override_valid_data)
+
+      ,.io_clk_r_o(io_clk_tline)                // output to other node
+      ,.io_data_r_o(io_data_tline)              // output to other node
+      ,.io_valid_r_o(io_valid_tline)            // output to other node
+
+      ,.token_clk_i(token_clk_tline)            // input from other node
+      ,.token_reset_i(token_reset_sync) // from core 0
+      );
+
+   // *****************************************
+   // * CORE 1 (input side)
+   // *
+   // *
+   // *
+
+   localparam lg_io_delay_reset_lp = 6;
+
+   wire io_1_reset_sync, core_1_reset_sync;
+
+   bsg_sync_sync #(.width_p(1)) bss_core_1_reset
+     (.oclk_i(core_1_clk)
+      ,.iclk_data_i(core_1_reset)
+      ,.oclk_data_o(core_1_reset_sync)
+      );
+
+
+   bsg_sync_sync #(.width_p(1)) bss_io_1_reset
+     (.oclk_i(io_clk_tline)
+      ,.iclk_data_i(core_1_reset)
+      ,.oclk_data_o(io_1_reset_sync)
+      );
+
+   wire core_1_yumi;
+   wire core_1_valid;
+   wire [channel_width_lp-1:0] core_1_data;
+
+   bsg_source_sync_input #(.lg_fifo_depth_p(lg_input_fifo_depth_lp)
+                           ,.lg_credit_to_token_decimation_p(lg_credit_to_token_decimation_lp)
+                           ,.channel_width_p(channel_width_lp)
+                           ) bssi_i1
+     (.io_clk_i(io_clk_tline)               // input from other node; starts on reset
+      ,.io_reset_i(io_1_reset_sync)
+      ,.io_data_i(io_data_tline)      // input from other node
+      ,.io_valid_i(io_valid_tline)    // input from other node
+
+      ,.io_edge_i(2'b11)              // latch on both edges
+
+      ,.io_token_r_o(token_clk_tline) // output to other node
+
+      ,.io_snoop_r_o()                // snoop input channel;
+                                      // for establishing calibration state
+                                      // on reset
+
+      ,.io_trigger_mode_en_i(1'b0)        // enable loop-back trigger mode
+      ,.io_trigger_mode_alt_en_i(1'b0)    // enable loop-back trigger mode: alternate trigger
+
+      ,.core_clk_i(core_1_clk)
+      ,.core_reset_i(core_1_reset_sync)
+
+      // core 1 side logical signals
+      ,.core_data_o(core_1_data)
+      ,.core_valid_o(core_1_valid)
+      ,.core_yumi_i(core_1_yumi)
+      );
+
+   // consume all data
+   assign core_1_yumi = core_1_valid;
+
+   localparam cycle_counter_width_lp=32;
+
+   logic [cycle_counter_width_lp-1:0] core_0_ctr;
+   bsg_cycle_counter #(.width_p(cycle_counter_width_lp)) bcc_core0 (core_0_clk, core_0_reset_sync, core_0_ctr);
+
+   logic [cycle_counter_width_lp-1:0] core_1_ctr;
+   bsg_cycle_counter #(.width_p(cycle_counter_width_lp)) bcc_core1 (core_1_clk, core_1_reset_sync, core_1_ctr);
+
+   logic [cycle_counter_width_lp-1:0] io_ctr;
+   bsg_cycle_counter #(.width_p(cycle_counter_width_lp)) bcc_io (io_master_clk, io_master_reset_sync, io_ctr);
+
+
+   // non-synthesizable, TEST ONLY
+   logic [7:0] core_1_last_n, core_1_last_r = -1;
+   logic [5:0] top_bits = 0;
+
+   assign core_1_last_n = core_1_last_r+8'b1;
+
+   // *******************************************************
+   // *
+   // * Logging.
+   // *
+   // * These statements allow you to see, in time, when values are transmitted and received.
+   // *
+   // *
+   // * For this test, the number of cycles on the slowest clock should match the number of words
+   // * transmitted plus a small constant.
+   // *
+   // *
+
+   always @(negedge core_1_clk)
+     if (core_1_valid)
+       begin
+          $display("## ", core_0_ctr, io_ctr, core_1_ctr, " ## core 1 recv %d, %d",top_bits*256,core_1_data);
+          assert (core_1_last_n == core_1_data) else $error("##transmission error", core_1_last_r, core_1_data);
+          core_1_last_r <= core_1_last_n;
+          if (core_1_data == 8'hff)
+            begin
+               if (top_bits == 6'b000_111)
+                 $finish("## DONE");
+               top_bits = top_bits+1;
+            end
+       end
+
+   always @(negedge core_0_clk)
+     if (core_0_yumi)
+       $display("## ", core_0_ctr, io_ctr, core_1_ctr, " ## core 0 sent %d",core_0_data_r);
+
+   always @(negedge io_master_clk)
+     if (io_valid_tline)
+       $display("## ", core_0_ctr, io_ctr, core_1_ctr, " ## io     xmit %d",io_data_tline);
+endmodule
+

snapshots/bespoke-silicon-group_basejump_stl_pr706/hard/fakeram/bsg_mem_1rw_sync_macros.svh

@@ -0,0 +1,24 @@
+
+`ifndef BSG_MEM_1RW_SYNC_MACROS
+`define BSG_MEM_1RW_SYNC_MACROS
+
+`define bsg_mem_1rw_sync_1rf_macro(words,bits,tag) \
+  `bsg_mem_1rw_sync_1sram_macro(words,bits)
+`define bsg_mem_1rw_sync_1hdsram_macro(words,bits,tag) \
+  `bsg_mem_1rw_sync_1sram_macro(words,bits)
+
+`define bsg_mem_1rw_sync_1sram_macro(words,bits,tag) \
+  if (els_p == words && width_p == bits)             \
+    begin: macro                                     \
+       fakeram_d``words``_w``bits`` mem              \
+         (.clk(clk_i)                                \
+         ,.ce_in(v_i)                                \
+         ,.we_in(w_i)                                \
+         ,.wd_in(data_i)                             \
+         ,.w_mask_in('1)                             \
+         ,.addr_in(addr_i)                           \
+         ,.rd_out(data_o)                            \
+         );                                          \
+    end
+
+`endif

snapshots/bespoke-silicon-group_basejump_stl_pr706/hard/fakeram/bsg_mem_1rw_sync_mask_write_bit_macros.svh

@@ -0,0 +1,24 @@
+
+`ifndef BSG_MEM_1RW_SYNC_MASK_WRITE_BIT_MACROS
+`define BSG_MEM_1RW_SYNC_MASK_WRITE_BIT_MACROS
+
+`define bsg_mem_1rw_sync_mask_write_bit_1rf_macro(words,bits,tag) \
+  `bsg_mem_1rw_sync_mask_write_bit_1sram_macro(words,bits)
+`define bsg_mem_1rw_sync_mask_write_bit_1hdsram_macro(words,bits,tag) \
+  `bsg_mem_1rw_sync_mask_write_bit_1sram_macro(words,bits)
+
+`define bsg_mem_1rw_sync_mask_write_bit_1sram_macro(words,bits,tag) \
+  if (els_p == words && width_p == bits)                            \
+    begin: macro                                                    \
+       fakeram_d``words``_w``bits`` mem                             \
+         (.clk(clk_i)                                               \
+         ,.ce_in(v_i)                                               \
+         ,.we_in(w_i)                                               \
+         ,.wd_in(data_i)                                            \
+         ,.w_mask_in(w_mask_i)                                      \
+         ,.addr_in(addr_i)                                          \
+         ,.rd_out(data_o)                                           \
+         );                                                         \
+    end
+
+`endif

snapshots/bespoke-silicon-group_basejump_stl_pr706/hard/fakeram/bsg_mem_1rw_sync_mask_write_byte_macros.svh

@@ -0,0 +1,32 @@
+
+`ifndef BSG_MEM_1RW_SYNC_MASK_WRITE_BYTE_MACROS
+`define BSG_MEM_1RW_SYNC_MASK_WRITE_BYTE_MACROS
+
+`define bsg_mem_1rw_sync_mask_write_byte_1rf_macro(words,bits,tag) \
+  `bsg_mem_1rw_sync_mask_write_byte_1sram_macro(words,bits)
+`define bsg_mem_1rw_sync_mask_write_byte_1hdsram_macro(words,bits,tag) \
+  `bsg_mem_1rw_sync_mask_write_byte_1sram_macro(words,bits)
+
+`define bsg_mem_1rw_sync_mask_write_byte_1sram_macro(words,bits,tag) \
+  if (els_p == words && data_width_p == bits)                        \
+    begin: macro                                                     \
+       logic [data_width_p-1:0] w_mask_lo;                           \
+       bsg_expand_bitmask                                            \
+        #(.in_width_p(write_mask_width_lp), .expand_p(8))            \
+        wmask_expand                                                 \
+         (.i(write_mask_i)                                           \
+          ,.o(w_mask_lo)                                             \
+          );                                                         \
+                                                                     \
+       fakeram_d``words``_w``bits`` mem                              \
+         (.clk(clk_i)                                                \
+         ,.ce_in(v_i)                                                \
+         ,.we_in(w_i)                                                \
+         ,.wd_in(data_i)                                             \
+         ,.w_mask_in(w_mask_lo)                                      \
+         ,.addr_in(addr_i)                                           \
+         ,.rd_out(data_o)                                            \
+         );                                                          \
+    end
+
+`endif

snapshots/bespoke-silicon-group_basejump_stl_pr706/hard/gf_14/README.md

@@ -0,0 +1,17 @@
+# GF14 Hard Directory
+
+This directory contains hardened (process specific) variants of basejump_stl
+RTL modules. These modules should be swapped with the RTL modules of the same
+name during the chip implementation flow.
+
+## Special Attributes
+
+Cell instances with the `*BSG_DONT_TOUCH*` in the name should get a dont_touch
+attribute applied to these instances in the backend flow.
+
+All instances of library cell `*SYNC*DFF*` should automatically get a dont_touch
+attribute (regardless of the instance name).
+
+Cell instances with the `*BSG_NO_CLOCK_GATE*` in the name should get an attribute
+to prevent clock gating on this module/cell.
+

snapshots/bespoke-silicon-group_basejump_stl_pr706/hard/tsmc_16/bsg_async/bsg_launch_sync_sync.sv

@@ -0,0 +1,170 @@
+// MBT 7/24/2014
+//
+// This is a launch/synchronization complex.
+// The launch flop prevents combinational glitching.
+// The two sync flops reduce probability of metastability.
+// See MBT's note on async design and CDC.
+//
+// The three flops should be don't touched in synopsys
+// and abutted in physical design to reduce chances of metastability.
+//
+// Use of reset is optional; it can be used to hold a known value during reset
+// if for instance, the value is coming off chip.
+//
+
+// the code is structured this way because synopsys's
+// support for hierarchical placement groups appears
+// not to work for parameterized modules.
+// so we must have a non-parameterized module
+// in order to abut the three registers, which
+// have two different clocks.
+//
+
+`define bsg_launch_sync_sync_unit_hard(EDGE,bits)                       \
+                                                                        \
+module bsg_launch_sync_sync_``EDGE``_``bits``_unit                      \
+  (input             iclk_i                                             \
+  ,input             iclk_reset_i                                       \
+  ,input             oclk_i                                             \
+  ,input  [bits-1:0] iclk_data_i                                        \
+  ,output [bits-1:0] iclk_data_o                                        \
+  ,output [bits-1:0] oclk_data_o                                        \
+  );                                                                    \
+                                                                        \
+  genvar i;                                                             \
+                                                                        \
+  logic [bits-1:0] bsg_SYNC_LNCH_r;                                     \
+  logic [bits-1:0] bsg_SYNC_2_r;                                        \
+                                                                        \
+  assign iclk_data_o = bsg_SYNC_LNCH_r;                                 \
+  assign oclk_data_o = bsg_SYNC_2_r;                                    \
+                                                                        \
+  always_ff @(EDGE iclk_i)                                              \
+    begin                                                               \
+      if (iclk_reset_i)                                                 \
+        bsg_SYNC_LNCH_r <= {bits{1'b0}};                                \
+      else                                                              \
+        bsg_SYNC_LNCH_r <= iclk_data_i;                                 \
+    end                                                                 \
+                                                                        \
+  for (i = 0; i < bits; i = i + 1)                                      \
+    begin : blss_unit                                                   \
+      SDFFYQ2D_X2N_A7P5PP96PTS_C16 hard_sync_int                        \
+        (.D  (bsg_SYNC_LNCH_r[i])                                       \
+        ,.CK (oclk_i)                                                   \
+        ,.SI (1'b0)                                                     \
+        ,.SE (1'b0)                                                     \
+        ,.Q  (bsg_SYNC_2_r[i])                                          \
+        );                                                              \
+    end                                                                 \
+                                                                        \
+endmodule
+
+`BSG_ABSTRACT_MODULE(bsg_launch_sync_sync)
+
+
+// bsg_launch_sync_sync_posedge_1_unit
+`bsg_launch_sync_sync_unit_hard(posedge,1)
+`bsg_launch_sync_sync_unit_hard(posedge,2)
+`bsg_launch_sync_sync_unit_hard(posedge,3)
+`bsg_launch_sync_sync_unit_hard(posedge,4)
+`bsg_launch_sync_sync_unit_hard(posedge,5)
+`bsg_launch_sync_sync_unit_hard(posedge,6)
+`bsg_launch_sync_sync_unit_hard(posedge,7)
+`bsg_launch_sync_sync_unit_hard(posedge,8)
+
+// bsg_launch_sync_sync_negedge_1_unit
+`bsg_launch_sync_sync_unit_hard(negedge,1)
+`bsg_launch_sync_sync_unit_hard(negedge,2)
+`bsg_launch_sync_sync_unit_hard(negedge,3)
+`bsg_launch_sync_sync_unit_hard(negedge,4)
+`bsg_launch_sync_sync_unit_hard(negedge,5)
+`bsg_launch_sync_sync_unit_hard(negedge,6)
+`bsg_launch_sync_sync_unit_hard(negedge,7)
+`bsg_launch_sync_sync_unit_hard(negedge,8)
+
+// warning: if you make this != 8, you need
+// to modify other parts of this code
+
+`define blss_max_block 8
+
+// handle trailer bits
+`define blss_if_clause(EDGE,num) if ((width_p % `blss_max_block) == num) begin: z            \
+                                     bsg_launch_sync_sync_``EDGE``_``num``_unit blss \
+                                        (.iclk_i                                     \
+                                         ,.iclk_reset_i                              \
+                                         ,.oclk_i                                    \
+                                         ,.iclk_data_i(iclk_data_i[width_p-1-:num])  \
+                                         ,.iclk_data_o(iclk_data_o[width_p-1-:num])  \
+                                         ,.oclk_data_o(oclk_data_o[width_p-1-:num])  \
+                                         ); end
+
+module bsg_launch_sync_sync #(parameter `BSG_INV_PARAM(width_p)
+                              , parameter use_negedge_for_launch_p = 0)
+   (input iclk_i
+    , input iclk_reset_i
+    , input oclk_i
+    , input  [width_p-1:0] iclk_data_i
+    , output [width_p-1:0] iclk_data_o // after launch flop
+    , output [width_p-1:0] oclk_data_o // after sync flops
+    );
+
+   genvar i;
+
+`ifndef BSG_HIDE_FROM_SYNTHESIS
+   initial assert (iclk_reset_i !== 'z)
+     else
+       begin
+          $error("%m iclk_reset should be connected");
+          $finish();
+       end
+`endif
+
+   if (use_negedge_for_launch_p)
+     begin: n
+        for (i = 0; i < (width_p/`blss_max_block); i = i + 1)
+          begin : maxb
+             bsg_launch_sync_sync_negedge_8_unit blss
+                 (.iclk_i
+                  ,.iclk_reset_i
+                  ,.oclk_i
+                  ,.iclk_data_i(iclk_data_i[i*`blss_max_block+:`blss_max_block])
+                  ,.iclk_data_o(iclk_data_o[i*`blss_max_block+:`blss_max_block])
+                  ,.oclk_data_o(oclk_data_o[i*`blss_max_block+:`blss_max_block])
+                  );
+          end
+
+        `blss_if_clause(negedge,1) else
+          `blss_if_clause(negedge,2) else
+            `blss_if_clause(negedge,3) else
+              `blss_if_clause(negedge,4) else
+                `blss_if_clause(negedge,5) else
+                  `blss_if_clause(negedge,6) else
+                    `blss_if_clause(negedge,7)
+     end
+   else
+     begin: p
+        for (i = 0; i < (width_p/`blss_max_block); i = i + 1)
+          begin : maxb
+             bsg_launch_sync_sync_posedge_8_unit blss
+                 (.iclk_i
+                  ,.iclk_reset_i
+                  ,.oclk_i
+                  ,.iclk_data_i(iclk_data_i[i*`blss_max_block+:`blss_max_block])
+                  ,.iclk_data_o(iclk_data_o[i*`blss_max_block+:`blss_max_block])
+                  ,.oclk_data_o(oclk_data_o[i*`blss_max_block+:`blss_max_block])
+                  );
+          end
+
+        `blss_if_clause(posedge,1) else
+          `blss_if_clause(posedge,2) else
+            `blss_if_clause(posedge,3) else
+              `blss_if_clause(posedge,4) else
+                `blss_if_clause(posedge,5) else
+                  `blss_if_clause(posedge,6) else
+                    `blss_if_clause(posedge,7)
+     end
+
+endmodule
+
+`BSG_ABSTRACT_MODULE(bsg_launch_sync_sync)

snapshots/bespoke-silicon-group_basejump_stl_pr706/hard/tsmc_16/bsg_async/bsg_sync_sync.sv

@@ -0,0 +1,90 @@
+// MBT 7/24/2014
+//
+// bsg_sync_sync
+//
+// This is just two synchronization flops.
+//
+// We use the rp placement flop from synopsys.
+// Fixme: move this into asic-specific components.
+//
+
+`define bsg_sync_sync_unit_hard(width_p)                                \
+                                                                        \
+module bsg_sync_sync_``width_p``_unit                                   \
+  (input                oclk_i                                          \
+  ,input  [width_p-1:0] iclk_data_i                                     \
+  ,output [width_p-1:0] oclk_data_o // after sync flops                 \
+  );                                                                    \
+                                                                        \
+  genvar i;                                                             \
+                                                                        \
+  logic [width_p-1:0] bsg_SYNC_2_r;                                     \
+                                                                        \
+  assign oclk_data_o = bsg_SYNC_2_r;                                    \
+                                                                        \
+  for (i = 0; i < width_p; i = i + 1)                                   \
+    begin : bss_unit                                                    \
+      SDFFYQ2D_X2N_A7P5PP96PTS_C16 hard_sync_int                        \
+        (.D  (iclk_data_i[i])                                           \
+        ,.CK (oclk_i)                                                   \
+        ,.SI (1'b0)                                                     \
+        ,.SE (1'b0)                                                     \
+        ,.Q  (bsg_SYNC_2_r[i])                                          \
+        );                                                              \
+    end                                                                 \
+                                                                        \
+endmodule
+
+`BSG_ABSTRACT_MODULE(bsg_sync_sync)
+
+`bsg_sync_sync_unit_hard(1)
+`bsg_sync_sync_unit_hard(2)
+`bsg_sync_sync_unit_hard(3)
+`bsg_sync_sync_unit_hard(4)
+`bsg_sync_sync_unit_hard(5)
+`bsg_sync_sync_unit_hard(6)
+`bsg_sync_sync_unit_hard(7)
+`bsg_sync_sync_unit_hard(8)
+
+// warning: if you make this != 8, you need to modify other
+// parts of this code.
+
+`define bss_max_block 8
+
+`define bss_if_clause(num) if ((width_p % `bss_max_block) == num) begin: z\
+                            bsg_sync_sync_``num``_unit bss                \
+                              (.oclk_i                                    \
+                               ,.iclk_data_i(iclk_data_i[width_p-1-:num]) \
+                               ,.oclk_data_o(oclk_data_o[width_p-1-:num]) \
+                               ); end
+
+
+module bsg_sync_sync #(parameter `BSG_INV_PARAM(width_p ))
+   (
+      input oclk_i
+    , input  [width_p-1:0] iclk_data_i
+    , output [width_p-1:0] oclk_data_o // after sync flops
+    );
+
+   genvar   i;
+
+   for (i = 0; i < (width_p/`bss_max_block); i = i + 1)
+     begin : maxb
+        bsg_sync_sync_8_unit bss8
+            (.oclk_i
+             ,.iclk_data_i(iclk_data_i[i*`bss_max_block+:`bss_max_block])
+             ,.oclk_data_o(oclk_data_o[i*`bss_max_block+:`bss_max_block])
+             );
+     end
+
+   `bss_if_clause(1) else
+     `bss_if_clause(2) else
+       `bss_if_clause(3) else
+         `bss_if_clause(4) else
+           `bss_if_clause(5) else
+             `bss_if_clause(6) else
+               `bss_if_clause(7)
+
+endmodule
+
+`BSG_ABSTRACT_MODULE(bsg_sync_sync)

snapshots/bespoke-silicon-group_basejump_stl_pr706/hard/tsmc_16/bsg_mem/bsg_mem_1r1w_sync_mask_write_bit.sv

@@ -0,0 +1,132 @@
+// ctorng 2/22/2017
+//
+// 1 read-port, 1 write-port ram
+//
+// reads are synchronous
+//
+// Ports for tsmc16_2rw (sram_2p_uhde)
+//
+//   CLK   // in
+//   AA    // in
+//   CENA  // active low
+//   QA    // out
+//
+//   AB    // in
+//   DB    // in
+//   CENB  // active low
+//   WENB  // active low
+//
+//   STOVAB// 1'b0 (is really a don't care, but we drive it)
+//   STOV  // 1'b0 default
+//   EMA   // 3'd2 default
+//   EMAW  // 2'd1 default
+//   EMAS  // 1'b0 default
+//   EMAP  // 1'b0 default
+//   RET1N // 1'b1, active low, 1'b1 is disabled (retention mode)
+//
+
+`define bsg_mem_1r1w_sync_mask_write_bit_macro(words,bits,lgEls)     \
+if (els_p == words && width_p == bits)                               \
+  begin: macro                                                       \
+      tsmc16_1r1w_lg``lgEls``_w``bits``_bit mem (                    \
+         .CLK   (clk_i)                                              \
+        ,.AA    (r_addr_i)                                           \
+        ,.CENA  (~r_v_i)                                             \
+        ,.QA    (r_data_o)                                           \
+                                                                     \
+        ,.AB    (w_addr_i)                                           \
+        ,.DB    (w_data_i)                                           \
+        ,.CENB  (~w_v_i)                                             \
+        ,.WENB  (~w_mask_i)                                          \
+                                                                     \
+        ,.STOV  (1'd0  )                                             \
+        ,.STOVAB(1'd0  )                                             \
+        ,.EMA   (3'd3  )                                             \
+        ,.EMAW  (2'd1  )                                             \
+        ,.EMAS  (1'b0  )                                             \
+        ,.EMAP  (1'b0  )                                             \
+        ,.RET1N (1'b1  )                                             \
+        );                                                           \
+  end
+
+`define bsg_mem_1r1w_sync_mask_write_bit_macro_rf(words,bits,lgEls)  \
+if (els_p == words && width_p == bits)                               \
+  begin: macro                                                       \
+      tsmc16_1r1w_rf_lg``lgEls``_w``bits``_bit mem (                 \
+         .CLKA  (clk_i)                                              \
+        ,.AA    (r_addr_i)                                           \
+        ,.CENA  (~r_v_i)                                             \
+        ,.QA    (r_data_o)                                           \
+                                                                     \
+        ,.CLKB  (clk_i)                                              \
+        ,.AB    (w_addr_i)                                           \
+        ,.DB    (w_data_i)                                           \
+        ,.CENB  (~w_v_i)                                             \
+        ,.WENB  (~w_mask_i)                                          \
+                                                                     \
+        ,.STOV  (1'd0  )                                             \
+        ,.EMAA  (3'd3  )                                             \
+        ,.EMAB  (3'd3  )                                             \
+        ,.EMASA (1'd1  )                                             \
+        ,.RET1N (1'b1  )                                             \
+        );                                                           \
+  end
+
+module bsg_mem_1r1w_sync_mask_write_bit #(parameter `BSG_INV_PARAM(width_p)
+                                        , parameter `BSG_INV_PARAM(els_p)
+                                        , parameter read_write_same_addr_p=0
+                                        , parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
+                                        , parameter harden_p=1
+                                        )
+  ( input                      clk_i
+  , input                      reset_i
+
+  , input                      w_v_i
+  , input [width_p-1:0]        w_mask_i
+  , input [addr_width_lp-1:0]  w_addr_i
+  , input [width_p-1:0]        w_data_i
+
+  // currently unused
+  , input                      r_v_i
+  , input [addr_width_lp-1:0]  r_addr_i
+
+  , output logic [width_p-1:0] r_data_o
+  );
+
+  `bsg_mem_1r1w_sync_mask_write_bit_macro(64,88,6) else
+  `bsg_mem_1r1w_sync_mask_write_bit_macro(256,128,8) else
+     bsg_mem_1r1w_sync_mask_write_bit_synth
+       #(.width_p(width_p)
+         ,.els_p (els_p  )
+         ,.read_write_same_addr_p(read_write_same_addr_p)
+         ,.harden_p(harden_p)
+         ) synth
+         (.*);
+
+`ifndef BSG_HIDE_FROM_SYNTHESIS
+
+   always_ff @(posedge clk_i)
+     if (w_v_i)
+       begin
+          assert (w_addr_i < els_p)
+            else $error("Invalid address %x to %m of size %x\n", w_addr_i, els_p);
+
+          assert (~(r_addr_i == w_addr_i && w_v_i && r_v_i && !read_write_same_addr_p))
+            else
+              begin
+                 //$error("%m: Attempt to read and write same address (reset_i %b, %x <= %x (mask %x) old_val %x",reset_i, w_addr_i,w_data_i,w_mask_i,mem[r_addr_i]);
+                 $error("%m: Attempt to read and write same address (reset_i %b, %x <= %x (mask %x)",reset_i, w_addr_i,w_data_i,w_mask_i);
+                 //$finish();
+              end
+       end
+
+   initial
+     begin
+        $display("## %L: instantiating width_p=%d, els_p=%d, read_write_same_addr_p=%d harden_p=%d (%m)",width_p,els_p,read_write_same_addr_p, harden_p);
+     end
+
+`endif
+
+endmodule
+
+`BSG_ABSTRACT_MODULE(bsg_mem_1r1w_sync_mask_write_bit)

snapshots/bespoke-silicon-group_basejump_stl_pr706/hard/tsmc_16/bsg_mem/bsg_mem_1rw_sync.sv

@@ -0,0 +1,108 @@
+// MBT 11/9/2014
+//
+// Synchronous 1-port ram.
+// Only one read or one write may be done per cycle.
+//
+
+`define bsg_mem_1rw_sync_macro(words,bits,lgEls,newBits)                       \
+if (els_p == words && width_p == bits)                                         \
+  begin: macro                                                                 \
+     tsmc16_1rw_lg``lgEls``_w``newBits``_all mem                               \
+       (.CLK   (clk_i )                                                        \
+       ,.Q     (data_o) // out                                                 \
+       ,.CEN   (~v_i  ) // lo true                                             \
+       ,.GWEN  (~w_i  ) // lo true                                             \
+       ,.A     (addr_i) // in                                                  \
+       ,.D     (data_i) // in                                                  \
+       ,.STOV  (1'd0  ) // Self-timing Override - disabled                     \
+       ,.EMA   (3'd3  ) // Extra Margin Adjustment - default value             \
+       ,.EMAW  (2'd1  ) // Extra Margin Adjustment Write - default value       \
+       ,.EMAS  (1'd0  ) // Extra Margin Adjustment Sense Amp. - default value  \
+       ,.RET1N (1'b1  ) // Retention Mode (active low) - disabled              \
+       );                                                                      \
+  end // block: macro
+
+`define bsg_mem_1rw_sync_macro_rf(words,bits,lgEls,newBits)                   \
+if (els_p == words && width_p == bits)                                        \
+  begin: macro                                                                \
+     tsmc16_1rf_lg``lgEls``_w``newBits``_all mem                              \
+       (.Q     (data_o)                                                       \
+       ,.CLK   (clk_i )                                                       \
+       ,.CEN   (~v_i  )                                                       \
+       ,.GWEN  (~w_i  )                                                       \
+       ,.A     (addr_i)                                                       \
+       ,.D     (data_i)                                                       \
+       ,.STOV  (1'd0  ) // Self-timing Override - disabled                    \
+       ,.EMA   (3'd3  ) // Extra Margin Adjustment - default value            \
+       ,.EMAW  (2'd1  ) // Extra Margin Adjustment Write - default value      \
+       ,.EMAS  (1'd0  ) // Extra Margin Adjustment Sense Amp. - default value \
+       ,.RET1N (1'b1  ) // Retention Mode (active low) - disabled             \
+       );                                                                     \
+  end // block: macro
+
+module bsg_mem_1rw_sync #(parameter `BSG_INV_PARAM(width_p)
+                         ,parameter `BSG_INV_PARAM(els_p)
+                         ,parameter addr_width_lp=$clog2(els_p)
+                         // whether to substitute a 1r1w
+                         ,parameter substitute_1r1w_p=1)
+  (input                      clk_i
+  ,input                      reset_i
+  ,input [width_p-1:0]        data_i
+  ,input [addr_width_lp-1:0]  addr_i
+  ,input                      v_i
+  ,input                      w_i
+  ,output logic [width_p-1:0] data_o
+  );
+
+  `bsg_mem_1rw_sync_macro    (1024, 32, 10,  32) else
+  `bsg_mem_1rw_sync_macro_rf (128,  66,  7,  66) else
+  `bsg_mem_1rw_sync_macro_rf (128,  62,  7,  62) else
+  `bsg_mem_1rw_sync_macro_rf (256, 128,  8, 128) else
+
+  begin: z
+    // we substitute a 1r1w macro
+    // fixme: theoretically there may be
+    // a more efficient way to generate a 1rw synthesized ram
+    if (substitute_1r1w_p)
+      begin: s1r1w
+
+        logic [width_p-1:0] data_lo;
+
+        bsg_mem_1r1w #(.width_p(width_p)
+                      ,.els_p(els_p)
+                      ,.read_write_same_addr_p(0)
+                      ) mem
+          (.w_clk_i   (clk_i     )
+          ,.w_reset_i (reset_i   )
+          ,.w_v_i     (v_i & w_i )
+          ,.w_addr_i  (addr_i    )
+          ,.w_data_i  (data_i    )
+          ,.r_addr_i  (addr_i    )
+          ,.r_v_i     (v_i & ~w_i)
+          ,.r_data_o  (data_lo   )
+          );
+
+        // register output data to convert sync to async
+        always_ff @(posedge clk_i)
+          data_o <= data_lo;
+
+      end // block: s1r1w
+    else
+      begin: notmacro
+
+        // Instantiate a synthesizable 1rw sync ram
+        bsg_mem_1rw_sync_synth #(.width_p(width_p), .els_p(els_p)) synth (.*);
+
+      end // block: notmacro
+  end // block: z
+
+`ifndef BSG_HIDE_FROM_SYNTHESIS
+  initial
+    begin
+      $display("## %L: instantiating width_p=%d, els_p=%d, substitute_1r1w_p=%d (%m)",width_p,els_p,substitute_1r1w_p);
+    end
+`endif
+
+endmodule
+
+`BSG_ABSTRACT_MODULE(bsg_mem_1rw_sync)

snapshots/bespoke-silicon-group_basejump_stl_pr706/hard/tsmc_16/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.sv

@@ -0,0 +1,97 @@
+// ctorng 2-23-17
+//
+// Synchronous 1-port ram with bit masking
+// Only one read or one write may be done per cycle.
+//
+// Ports for tsmc16_1rw and tsmc16_1rf
+//
+//   CLK   // in
+//   Q     // out
+//   CEN   // lo true
+//   WEN   // lo true
+//   GWEN  // lo true
+//   A     // in
+//   D     // in
+//   STOV  // Self-timing Override - disabled
+//   EMA   // Extra Margin Adjustment - default value
+//   EMAW  // Extra Margin Adjustment Write - default value
+//   EMAS  // Extra Margin Adjustment Sense Amp. - default value
+//   RET1N // Retention Mode (active low) - disabled
+
+`define bsg_mem_1rw_sync_mask_write_bit_macro(words,bits,lgEls)     \
+if (els_p == words && width_p == bits)               \
+  begin: macro                                       \
+      tsmc16_1rw_lg``lgEls``_w``bits``_bit mem       \
+        (.CLK   (clk_i )                             \
+        ,.Q     (data_o)                             \
+        ,.CEN   (~v_i  )                             \
+        ,.WEN   (~w_mask_i)                          \
+        ,.GWEN  (~w_i  )                             \
+        ,.A     (addr_i)                             \
+        ,.D     (data_i)                             \
+        ,.STOV  (1'd0  )                             \
+        ,.EMA   (3'd3  )                             \
+        ,.EMAW  (2'd1  )                             \
+        ,.EMAS  (1'd0  )                             \
+        ,.RET1N (1'b1  )                             \
+        );                                           \
+  end // block: macro
+
+`define bsg_mem_1rw_sync_mask_write_bit_macro_rf(words,bits,lgEls)  \
+if (els_p == words && width_p == bits)               \
+  begin: macro                                       \
+      tsmc16_1rf_lg``lgEls``_w``bits``_bit mem       \
+        (.Q     (data_o)                             \
+        ,.CLK   (clk_i )                             \
+        ,.CEN   (~v_i  )                             \
+        ,.WEN   (~w_mask_i)                          \
+        ,.GWEN  (~w_i  )                             \
+        ,.A     (addr_i)                             \
+        ,.D     (data_i)                             \
+        ,.STOV  (1'd0  )                             \
+        ,.EMA   (3'd3  )                             \
+        ,.EMAW  (2'd1  )                             \
+        ,.EMAS  (1'd0  )                             \
+        ,.RET1N (1'b1  )                             \
+        );                                           \
+  end // block: macro
+
+module bsg_mem_1rw_sync_mask_write_bit #(parameter `BSG_INV_PARAM(width_p)
+                                       , parameter `BSG_INV_PARAM(els_p)
+                                       , parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p))
+   (input   clk_i
+    , input reset_i
+    , input [width_p-1:0] data_i
+    , input [addr_width_lp-1:0] addr_i
+    , input v_i
+    , input [width_p-1:0] w_mask_i
+    , input w_i
+    , output [width_p-1:0]  data_o
+    );
+
+   `bsg_mem_1rw_sync_mask_write_bit_macro_rf(64,80,6) else
+   bsg_mem_1rw_sync_mask_write_bit_synth
+     #(.width_p(width_p)
+       ,.els_p(els_p)
+       ) synth
+       (.*);
+
+`ifndef BSG_HIDE_FROM_SYNTHESIS
+
+   always_ff @(posedge clk_i)
+     if (v_i)
+       assert (addr_i < els_p)
+         else $error("Invalid address %x to %m of size %x\n", addr_i, els_p);
+
+   initial
+     begin
+        $display("## %L: instantiating width_p=%d, els_p=%d (%m)",width_p,els_p);
+     end
+
+`endif
+
+
+endmodule
+
+`BSG_ABSTRACT_MODULE(bsg_mem_1rw_sync_mask_write_bit)
+

snapshots/bespoke-silicon-group_basejump_stl_pr706/hard/tsmc_16/bsg_mem/bsg_mem_1rw_sync_mask_write_byte.sv

@@ -0,0 +1,65 @@
+// STD 10-30-16
+//
+// Synchronous 1-port ram with byte masking
+// Only one read or one write may be done per cycle.
+//
+module bsg_mem_1rw_sync_mask_write_byte #(parameter `BSG_INV_PARAM(els_p )
+                                         ,parameter `BSG_INV_PARAM(data_width_p )
+                                         ,parameter addr_width_lp = `BSG_SAFE_CLOG2(els_p)
+                                         ,parameter write_mask_width_lp = data_width_p>>3
+                                         )
+  (input                           clk_i
+  ,input                           reset_i
+  ,input                           v_i
+  ,input                           w_i
+  ,input [addr_width_lp-1:0]       addr_i
+  ,input [data_width_p-1:0]        data_i
+  ,input [write_mask_width_lp-1:0] write_mask_i
+  ,output [data_width_p-1:0]       data_o
+  );
+
+  if ((els_p == 1024) & (data_width_p == 32))
+    begin : macro
+      wire [31:0] wen = ~{{8{write_mask_i[3]}}
+                         ,{8{write_mask_i[2]}}
+                         ,{8{write_mask_i[1]}}
+                         ,{8{write_mask_i[0]}}};
+      tsmc16_1rw_lg10_w32_byte mem
+        (.CLK   (clk_i )
+        ,.Q     (data_o) // out
+        ,.CEN   (~v_i  ) // lo true
+        ,.WEN   (wen   )
+        ,.GWEN  (~w_i  ) // lo true
+        ,.A     (addr_i) // in
+        ,.D     (data_i) // in
+        ,.STOV  (1'd0  ) // Self-timing Override - disabled
+        ,.EMA   (3'd3  ) // Extra Margin Adjustment - default value
+        ,.EMAW  (2'd1  ) // Extra Margin Adjustment Write - default value
+        ,.EMAS  (1'd0  ) // Extra Margin Adjustment Sense Amp. - default value
+        ,.RET1N (1'b1  ) // Retention Mode (active low) - disabled
+        );
+    end // block: macro
+  
+  // no hardened version found
+  else
+    begin: notmacro
+
+      // Instantiate a synthesizale 1rw sync mask write byte
+      bsg_mem_1rw_sync_mask_write_byte_synth #(.els_p(els_p), .data_width_p(data_width_p)) synth (.*);
+
+    end // block: notmacro
+
+`ifndef BSG_HIDE_FROM_SYNTHESIS
+  always_comb
+    assert (data_width_p % 8 == 0)
+      else $error("data width should be a multiple of 8 for byte masking");
+
+  initial
+    begin
+      $display("## bsg_mem_1rw_sync_mask_write_byte: instantiating data_width_p=%d, els_p=%d (%m)",data_width_p,els_p);
+    end
+`endif
+   
+endmodule
+
+`BSG_ABSTRACT_MODULE(bsg_mem_1rw_sync_mask_write_byte)

snapshots/bespoke-silicon-group_basejump_stl_pr706/hard/tsmc_16/bsg_mem/bsg_mem_2r1w_sync.sv

@@ -0,0 +1,122 @@
+//
+// 2 read-port, 1 write-port ram
+//
+// reads are synchronous
+//
+//
+
+module bsg_mem_2r1w_sync #(parameter `BSG_INV_PARAM(width_p)
+                           , parameter `BSG_INV_PARAM(els_p)
+                           , parameter read_write_same_addr_p=0
+                           , parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
+                           , parameter harden_p=0
+                           )
+   (input   clk_i
+    , input reset_i
+
+    , input                     w_v_i
+    , input [addr_width_lp-1:0] w_addr_i
+    , input [width_p-1:0]       w_data_i
+
+    // currently unused
+    , input                      r0_v_i
+    , input [addr_width_lp-1:0]  r0_addr_i
+    , output logic [width_p-1:0] r0_data_o
+
+    , input                      r1_v_i
+    , input [addr_width_lp-1:0]  r1_addr_i
+    , output logic [width_p-1:0] r1_data_o
+    );
+
+   wire                   unused = reset_i;
+
+   if ((width_p == 32) && (els_p == 32))
+     begin: macro
+
+        tsmc16_2rf_lg5_w32_all mem0
+          (
+           // read port
+           .CLKA (clk_i)
+           ,.AA  (r0_addr_i)
+           ,.CENA(~r0_v_i)
+
+           // output
+           ,.QA  (r0_data_o)
+
+           // write port
+           ,.CLKB(clk_i)
+           ,.AB  (w_addr_i)
+           ,.DB  (w_data_i)
+           ,.CENB(~w_v_i)
+
+           ,.STOV (1'd0  ) // Self-timing Override - disabled
+           ,.EMAA (3'd3  ) // Extra Margin Adjustment - default value
+           ,.EMAB (3'd3  ) // Extra Margin Adjustment - default value
+           ,.EMASA(1'd1  ) // Extra Margin Adjustment Sense Amp. - default value
+           ,.RET1N(1'b1  ) // Retention Mode (active low) - disabled
+           );
+
+        tsmc16_2rf_lg5_w32_all mem1
+          (
+           .CLKA (clk_i)
+           ,.AA  (r1_addr_i)
+           ,.CENA(~r1_v_i)
+
+           // output
+           ,.QA  (r1_data_o)
+
+           // write port
+           ,.CLKB(clk_i)
+           ,.AB  (w_addr_i)
+           ,.DB  (w_data_i)
+           ,.CENB(~w_v_i)
+
+           ,.STOV (1'd0  ) // Self-timing Override - disabled
+           ,.EMAA (3'd3  ) // Extra Margin Adjustment - default value
+           ,.EMAB (3'd3  ) // Extra Margin Adjustment - default value
+           ,.EMASA(1'd1  ) // Extra Margin Adjustment Sense Amp. - default value
+           ,.RET1N(1'b1  ) // Retention Mode (active low) - disabled
+           );
+
+     end // block: macro
+   else
+     begin: notmacro
+
+	bsg_mem_2r1w_sync_synth
+	  #(.width_p(width_p)
+	    ,.els_p(els_p)
+	    ,.read_write_same_addr_p(read_write_same_addr_p)
+	    ,.harden_p(harden_p)
+	    ) synth
+	    (.*);
+     end
+
+
+`ifndef BSG_HIDE_FROM_SYNTHESIS
+
+   always_ff @(posedge clk_i)
+     if (w_v_i)
+       begin
+          assert (w_addr_i < els_p)
+            else $error("Invalid address %x to %m of size %x\n", w_addr_i, els_p);
+
+          assert (~(r0_addr_i == w_addr_i && w_v_i && r0_v_i && !read_write_same_addr_p))
+            else $error("%m: port 0 Attempt to read and write same address");
+
+          assert (~(r1_addr_i == w_addr_i && w_v_i && r1_v_i && !read_write_same_addr_p))
+            else $error("%m: port 1 Attempt to read and write same address");
+       end
+
+   initial
+     begin
+        $display("## %L: instantiating width_p=%d, els_p=%d, read_write_same_addr_p=%d, harden_p=%d (%m)"
+		 ,width_p,els_p,read_write_same_addr_p,harden_p);
+     end
+
+`endif
+
+   
+
+endmodule
+
+`BSG_ABSTRACT_MODULE(bsg_mem_2r1w_sync)

snapshots/bespoke-silicon-group_basejump_stl_pr706/hard/tsmc_16/bsg_misc/bsg_level_shift_up_down_sink.sv

@@ -0,0 +1,32 @@
+// bsg_level_shift_up_down_sink
+//
+// An up-down level shifter can transform a signal to a higher or lower
+// voltage. A sink level shifter is designed to be in the same power
+// domain as the signals destination.
+//
+// Author: Scott Davidson
+// Date:   4-4-17
+//
+module bsg_level_shift_up_down_sink #(parameter `BSG_INV_PARAM(width_p ))
+(
+  input        [width_p-1:0] v0_data_i,
+  input                      v1_en_i,
+  output logic [width_p-1:0] v1_data_o
+);
+
+genvar i;
+
+for (i = 0; i < width_p; i++)
+  begin : n
+
+    A2LVLU_X2N_A7P5PP96PTS_C18 level_shift_sink (
+      .EN(v1_en_i),    // active high
+      .A(v0_data_i[i]),
+      .Y(v1_data_o[i])
+    );
+
+  end : n
+
+endmodule
+
+`BSG_ABSTRACT_MODULE(bsg_level_shift_up_down_sink)

snapshots/bespoke-silicon-group_basejump_stl_pr706/hard/tsmc_16/bsg_misc/bsg_level_shift_up_down_source.sv

@@ -0,0 +1,32 @@
+// bsg_level_shift_up_down_source
+//
+// An up-down level shifter can transform a signal to a higher or lower
+// voltage. A source level shifter is designed to be in the same power
+// domain as the signals source.
+//
+// Author: Scott Davidson
+// Date:   4-4-17
+//
+module bsg_level_shift_up_down_source #(parameter `BSG_INV_PARAM(width_p ))
+(
+  input                      v0_en_i,
+  input        [width_p-1:0] v0_data_i,
+  output logic [width_p-1:0] v1_data_o
+);
+
+genvar i;
+
+for (i = 0; i < width_p; i++)
+  begin : n
+
+    A2LVLUO_X2N_A7P5PP96PTS_C18 level_shift_source (
+      .EN(v0_en_i),     // active high
+      .A(v0_data_i[i]),
+      .Y(v1_data_o[i])
+    );
+
+  end : n
+
+endmodule
+
+`BSG_ABSTRACT_MODULE(bsg_level_shift_up_down_source)

snapshots/bespoke-silicon-group_basejump_stl_pr706/hard/tsmc_16/bsg_misc/bsg_mux.sv

@@ -0,0 +1,45 @@
+module bsg_mux #(
+  parameter `BSG_INV_PARAM(width_p    ),
+  parameter `BSG_INV_PARAM(els_p      ),
+  parameter harden_p   = 1,
+  parameter balanced_p = 0,
+  parameter lg_els_lp  = `BSG_SAFE_CLOG2(els_p)
+) (
+  input  [els_p-1:0][width_p-1:0] data_i,
+  input  [lg_els_lp-1:0]          sel_i,
+  output [width_p-1:0]            data_o
+);
+
+    if (harden_p && balanced_p && (els_p==2) && (width_p==1))
+      begin: macro
+
+        logic lo;
+
+        // This cell has great edge balancing characteristics
+        // on pins B and D if A=1 and C=1
+        MXIT4_X2N_A7P5PP96PTS_C16 mxit4 (
+          .A(1'b1),
+          .B(data_i[0]),
+          .C(1'b1),
+          .D(data_i[1]),
+          .S0(1'b1),
+          .S1(sel_i[0]),
+          .Y(lo)
+        );
+
+        INV_X16N_A7P5PP96PTS_C16 inv (
+          .A(lo),
+          .Y(data_o)
+        );
+        
+      end: macro
+    else
+      begin: notmacro
+         initial assert (harden_p==0) else $error("## %m: warning, failed to harden bsg_mux width=%d, els=%d, balanced=%d",width_p, els_p, balanced_p);
+         assign data_o = data_i[sel_i];
+      end: notmacro
+
+endmodule
+
+`BSG_ABSTRACT_MODULE(bsg_mux)
+