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snapshots/jotego_jtcores_pr1111/cores/kiwi/cfg/files.yaml

@@ -0,0 +1,39 @@
+kiwi:
+  - get:
+    - jtkiwi_game.v
+    - jtkiwi_main.v
+    - jtkiwi_video.v
+    - jtkiwi_colmix.v
+    - jtkiwi_snd.v
+    - jtkiwi_gfx.v
+    - jtkiwi_obj.v
+    - jtkiwi_draw.v
+    - jtkiwi_tilemap.v
+jtframe:
+  - get:
+      - jtframe_ff.v
+      - jtframe_sort.v
+  - from: clocking
+    get:
+      - jtframe_cen48.v
+      - jtframe_cen24.v
+  - from: ram
+    get:
+      - jtframe_ram.v
+      - jtframe_dual_ram16.v
+      - jtframe_obj_buffer.v
+      - jtframe_prom.v
+  - from: video
+    get:
+      - jtframe_vtimer.v
+      - jtframe_blank.v
+  - from: cpu
+    get:
+      # Z80
+      - jtframe_z80.yaml
+      # MCU
+      - jtframe_i8742.v
+      - upi41.yaml
+jt12:
+  - get:
+    - jt03.yaml

snapshots/jotego_jtcores_pr1111/cores/kiwi/cfg/macros.def

@@ -0,0 +1,49 @@
+[*]
+CORENAME=JTKIWI
+
+# Controls
+JTFRAME_BUTTONS=3
+JTFRAME_JOY_DURL
+JTFRAME_DIAL
+JTFRAME_DIALEMU_LEFT=0
+JTFRAME_NOMULTIWAY
+
+# Extermination, Kageki, etc. are vertical games
+JTFRAME_VERTICAL
+JTFRAME_CREDITS_HIDEVERT
+
+# ROM loading
+BRAM_OFFSET=0x100000
+JTFRAME_HEADER=4
+JTFRAME_BA1_START=0x20000
+JTFRAME_BA2_START=0x30000
+PCM_START=0x40000
+JTFRAME_BA3_START=0x50000
+JTFRAME_PROM_START=0x250000
+MCU_START=0x251000
+
+# Video
+JTFRAME_COLORW=5
+JTFRAME_WIDTH=256
+JTFRAME_HEIGHT=224
+
+# Debug options
+JTFRAME_STATUS
+
+# Clocks
+JTFRAME_PXLCLK=6
+
+[mister]
+JTFRAME_ARX=5
+JTFRAME_ARY=4
+CORE_OSD=OD,Button aid,Off,On
+
+[mist]
+-JTFRAME_CREDITS
+NOCREDITS
+JTFRAME_OSD_NOCREDITS
+NOKABUKIZ
+
+[sidi]
+# does not fit any more
+JTFRAME_SKIP

snapshots/jotego_jtcores_pr1111/cores/kiwi/cfg/mame2mra.toml

@@ -0,0 +1,91 @@
+[global]
+author=["jotego"]
+platform="jtkiwi"
+
+[parse]
+sourcefile=[ "tnzs.cpp" ]
+skip = { setnames = [
+    # Inputs not working
+    "plumppop",     # most left column missing, see service screen
+    "chukatai",     # top screen row missing for objects plus garbage at top left
+    "chukataij",
+    "chukataija",
+    "chukataiu",
+
+    # Korean hack on mostly unrelated hardware
+    "jpopnics",
+]}
+debug = { machine="kabukiz" }
+
+[Audio]
+volume = [
+    { machine="arknoid2", value=0x93 },
+    { machine="drtoppel", value=0x66 },
+    { machine="extrmatn", value=0x71 },
+    { machine="insectx", value=0xAD },
+    { machine="kageki", value=0x86 },
+    { machine="tnzs", value=0xFF },
+    { machine="kabukiz", value=0xFF },
+]
+
+[header]
+info="""bit 0 = MCU
+             bit 1 = color PROM
+             bit 2 = Kabuki Z (specific sound features)
+             bit 3 = Kageki   (specific sound features)
+             bit 4 = banked RAM
+             bit 5 = coin XOR
+             bit 6 = dip_flip XOR
+             bit 7 = HB delay
+             Byte 1:
+             bit 0 = service XOR
+             bit 1 = button aid
+             bit 2 = 3 MHz for FM module
+             bit 3 = Kabuki Z with different memory map  """
+data=[
+    { setnames=["tnzso","tnzsjo","tnzsoa","tnzsop","tnzsuo"], data="B1 04" }, # HB dly, Banked RAM, MCU, 3MHz FM
+    { machines=["chukatai"], data="41" }, # MCU
+    { machines=["insectx"],  data="40" }, # dip_flip inversion
+    { machines=["drtoppel"], data="03" },
+    { machines=["extrmatn","plumppop" ], data="03" }, # MCU - Color PROM
+    { machines=["arknoid2"], data="03 03" }, # MCU - Color PROM, Service XOR, Button aid
+    { machine="kabukiz",  data="14 04" }, # Kabuki Z sound subsystem, Banked RAM, 3MHz FM
+    { setnames=["tnzs","tnzsj"],  data="94 0C" }, # Kabuki Z sound subsystem (with mod), Banked RAM, 3MHz FM, HB dly
+    { machine="kageki" ,  data="08" }, # Kageki   sound subsystem
+]
+
+[buttons]
+Names = [ { machine="insectx",  names="Fire,Warp"},
+          { machine="extrmatn", names="Fire,Warp"},
+          { machine="tnzs",     names="Shoot,Jump"},
+          { machine="kabuki",   names="Attack,Block"},
+          { machine="kageki",   names="Left jab,Right hook"},
+          { machine="arknoid2", names="Shoot"},
+]
+
+[dipsw]
+bitcnt = 16
+delete=[{names=["Unused","Unknown"]}]
+rename = [{ name="P1 & P2 Children Collision", to="P1/P2 Collision" }]
+
+[ROM]
+regions = [
+    { name="maincpu", No_offset=true   },
+    { name="sub", start="JTFRAME_BA1_START" },
+    { name="audiocpu", start="JTFRAME_BA2_START" },
+    { name="samples", start="PCM_START" },
+    { name="gfx1", start="JTFRAME_BA3_START", width=32, sequence=[2,0,3,1] },
+    { machines=["kageki", "tnzs", "chukatai","drtoppel" ], name="gfx1", start="JTFRAME_BA3_START", width=32, sequence=[4,0,6,2, 5,1,7,3] },
+    { machines=["plumppop"], name="gfx1", start="JTFRAME_BA3_START", width=32, sequence=[4,0,6,2, 4,0,6,2, 5,1,7,3, 5,1,7,3 ] },
+    { machine="insectx",           name="gfx1", start="JTFRAME_BA3_START", width=16, no_offset=true },
+    { name="proms", start="JTFRAME_PROM_START", No_offset=true },
+    { name="mcu", start="MCU_START", No_offset=true, len=0x800, custom={ dev="8042" } },
+    { name="pal", skip=true },
+]
+
+order = [
+    "maincpu", "sub", "audiocpu", "samples",
+    "gfx1", "proms", "mcu"
+]
+
+

snapshots/jotego_jtcores_pr1111/cores/kiwi/doc/arkanoid2.cpp

@@ -0,0 +1,242 @@
+void arknoid2_state::mcu_reset()
+{
+    m_mcu_initializing = 3;
+    m_mcu_coinage_init = 0;
+    m_mcu_coinage[0] = 1;
+    m_mcu_coinage[1] = 1;
+    m_mcu_coinage[2] = 1;
+    m_mcu_coinage[3] = 1;
+    m_mcu_coins_a = 0;
+    m_mcu_coins_b = 0;
+    m_mcu_credits = 0;
+    m_mcu_reportcoin = 0;
+    m_mcu_command = 0;
+}
+
+void arknoid2_state::mcu_handle_coins( int coin )
+{
+    /* The coin inputs and coin counters are managed by the i8742 mcu. */
+    /* Here we simulate it. */
+    /* Credits are limited to 9, so more coins should be rejected */
+    /* Coin/Play settings must also be taken into consideration */
+
+    if (coin & 0x08)    /* tilt */
+        m_mcu_reportcoin = coin;
+    else if (coin && coin != m_insertcoin)
+    {
+        if (coin & 0x01)    /* coin A */
+        {
+//          logerror("Coin dropped into slot A\n");
+            machine().bookkeeping().coin_counter_w(0,1); machine().bookkeeping().coin_counter_w(0,0); /* Count slot A */
+            m_mcu_coins_a++;
+            if (m_mcu_coins_a >= m_mcu_coinage[0])
+            {
+                m_mcu_coins_a -= m_mcu_coinage[0];
+                m_mcu_credits += m_mcu_coinage[1];
+                if (m_mcu_credits >= 9)
+                {
+                    m_mcu_credits = 9;
+                    machine().bookkeeping().coin_lockout_global_w(1); /* Lock all coin slots */
+                }
+                else
+                {
+                    machine().bookkeeping().coin_lockout_global_w(0); /* Unlock all coin slots */
+                }
+            }
+        }
+
+        if (coin & 0x02)    /* coin B */
+        {
+//          logerror("Coin dropped into slot B\n");
+            machine().bookkeeping().coin_counter_w(1,1); machine().bookkeeping().coin_counter_w(1,0); /* Count slot B */
+            m_mcu_coins_b++;
+            if (m_mcu_coins_b >= m_mcu_coinage[2])
+            {
+                m_mcu_coins_b -= m_mcu_coinage[2];
+                m_mcu_credits += m_mcu_coinage[3];
+                if (m_mcu_credits >= 9)
+                {
+                    m_mcu_credits = 9;
+                    machine().bookkeeping().coin_lockout_global_w(1); /* Lock all coin slots */
+                }
+                else
+                {
+                    machine().bookkeeping().coin_lockout_global_w(0); /* Unlock all coin slots */
+                }
+            }
+        }
+
+        if (coin & 0x04)    /* service */
+        {
+//          logerror("Coin dropped into service slot C\n");
+            m_mcu_credits++;
+        }
+
+        m_mcu_reportcoin = coin;
+    }
+    else
+    {
+        if (m_mcu_credits < 9)
+            machine().bookkeeping().coin_lockout_global_w(0); /* Unlock all coin slots */
+
+        m_mcu_reportcoin = 0;
+    }
+    m_insertcoin = coin;
+}
+
+uint8_t arknoid2_state::mcu_r(offs_t offset)
+{
+    static const char mcu_startup[] = "\x55\xaa\x5a";
+
+    //logerror("%s: read mcu %04x\n", m_maincpu->pc(), 0xc000 + offset);
+
+    if (offset == 0)
+    {
+        /* if the mcu has just been reset, return startup code */
+        if (m_mcu_initializing)
+        {
+            m_mcu_initializing--;
+            return mcu_startup[2 - m_mcu_initializing];
+        }
+
+        switch (m_mcu_command)
+        {
+            case 0x41:
+                return m_mcu_credits;
+
+            case 0xc1:
+                /* Read the credit counter or the inputs */
+                if (m_mcu_readcredits == 0)
+                {
+                    m_mcu_readcredits = 1;
+                    if (m_mcu_reportcoin & 0x08)
+                    {
+                        m_mcu_initializing = 3;
+                        return 0xee;    /* tilt */
+                    }
+                    else return m_mcu_credits;
+                }
+                else return m_in0->read();  /* buttons */
+
+            default:
+                logerror("error, unknown mcu command\n");
+                /* should not happen */
+                return 0xff;
+        }
+    }
+    else
+    {
+        /*
+        status bits:
+        0 = mcu is ready to send data (read from c000)
+        1 = mcu has read data (from c000)
+        2 = unused
+        3 = unused
+        4-7 = coin code
+              0 = nothing
+              1,2,3 = coin switch pressed
+              e = tilt
+        */
+        if (m_mcu_reportcoin & 0x08) return 0xe1;   /* tilt */
+        if (m_mcu_reportcoin & 0x01) return 0x11;   /* coin 1 (will trigger "coin inserted" sound) */
+        if (m_mcu_reportcoin & 0x02) return 0x21;   /* coin 2 (will trigger "coin inserted" sound) */
+        if (m_mcu_reportcoin & 0x04) return 0x31;   /* coin 3 (will trigger "coin inserted" sound) */
+        return 0x01;
+    }
+}
+
+void arknoid2_state::mcu_w(offs_t offset, uint8_t data)
+{
+    if (offset == 0)
+    {
+        //logerror("%s: write %02x to mcu %04x\n", m_maincpu->pc(), data, 0xc000 + offset);
+        if (m_mcu_command == 0x41)
+        {
+            m_mcu_credits = (m_mcu_credits + data) & 0xff;
+        }
+    }
+    else
+    {
+        /*
+        0xc1: read number of credits, then buttons
+        0x54+0x41: add value to number of credits
+        0x15: sub 1 credit (when "Continue Play" only)
+        0x84: coin 1 lockout (issued only in test mode)
+        0x88: coin 2 lockout (issued only in test mode)
+        0x80: release coin lockout (issued only in test mode)
+        during initialization, a sequence of 4 bytes sets coin/credit settings
+        */
+        //logerror("%s: write %02x to mcu %04x\n", m_maincpu->pc(), data, 0xc000 + offset);
+
+        if (m_mcu_initializing)
+        {
+            /* set up coin/credit settings */
+            m_mcu_coinage[m_mcu_coinage_init++] = data;
+            if (m_mcu_coinage_init == 4)
+                m_mcu_coinage_init = 0; /* must not happen */
+        }
+
+        if (data == 0xc1)
+            m_mcu_readcredits = 0;  /* reset input port number */
+
+        if (data == 0x15)
+        {
+            m_mcu_credits = (m_mcu_credits - 1) & 0xff;
+            if (m_mcu_credits == 0xff)
+                m_mcu_credits = 0;
+        }
+        m_mcu_command = data;
+    }
+}
+
+INTERRUPT_GEN_MEMBER(arknoid2_state::mcu_interrupt)
+{
+    int coin = ((m_coin1->read() & 1) << 0);
+    coin |= ((m_coin2->read() & 1) << 1);
+    coin |= ((m_in2->read() & 3) << 2);
+    coin ^= 0x0c;
+    mcu_handle_coins(coin);
+
+    device.execute().set_input_line(0, HOLD_LINE);
+}
+
+void arknoid2_state::machine_reset()
+{
+    /* initialize the mcu simulation */
+    mcu_reset();
+
+    m_mcu_readcredits = 0;
+    m_insertcoin = 0;
+}
+
+void arknoid2_state::machine_start()
+{
+    tnzs_base_state::machine_start();
+
+    save_item(NAME(m_mcu_readcredits));
+    save_item(NAME(m_insertcoin));
+    save_item(NAME(m_mcu_initializing));
+    save_item(NAME(m_mcu_coinage_init));
+    save_item(NAME(m_mcu_coinage));
+    save_item(NAME(m_mcu_coins_a));
+    save_item(NAME(m_mcu_coins_b));
+    save_item(NAME(m_mcu_credits));
+    save_item(NAME(m_mcu_reportcoin));
+    save_item(NAME(m_mcu_command));
+
+    // kludge to make device work with active-high coin inputs
+    m_upd4701->left_w(0);
+    m_upd4701->middle_w(0);
+}
+
+void arknoid2_state::bankswitch1_w(uint8_t data)
+{
+    tnzs_base_state::bankswitch1_w(data);
+
+    if (BIT(data, 2))
+        mcu_reset();
+
+    // never actually written by arknoid2 (though code exists to do it)
+    m_upd4701->resetx_w(BIT(data, 5));
+    m_upd4701->resety_w(BIT(data, 5));
+}

snapshots/jotego_jtcores_pr1111/cores/kiwi/doc/seta001.cpp

@@ -0,0 +1,502 @@
+// license:BSD-3-Clause
+// copyright-holders:Luca Elia, David Haywood
+	/*
+	emulation of Seta sprite chips
+	X1-001A  X1-002A (SDIP64)
+
+	these always seem to be used as a pair, some board have been seen without the
+	'A', so it's probably a chip revision / bugfix.
+
+	used by:
+
+	seta.cpp
+	taito_x.cpp
+	tnzs.cpp
+	srmp2.cpp
+	champbwl.cpp
+	cchance.cpp
+	thedealr.cpp
+
+	note: the data bus is almost certainly 8-bit, dating back to the earliest
+	    hardware the games were used on.  the RAM arrangements changes
+	    slightly between games depending on how the RAM is hooked up to the
+	    main cpu.
+
+	'y' low bits are NEVER buffered?
+
+	TODO:
+	use getter callbacks in drivers for spriterams rather than allocating memory
+	here, then we won't have to allocate extra memory for seta.cpp games which
+	appear to have 0x800 bytes of RAM that isn't connected to the sprite chip
+	between the banks.
+
+	This should implement device_video_interface, since it generates the vertical
+	and horizontal blanking and sync signals from a master clock.
+
+	understand sprite limits / how sprite 0 sometimes must be skipped, maybe
+	layers being enabled counts against limits? maybe some chip revisions skip
+	the first sprite? see note in device_start
+
+	understand why we need offset kludges for some games, they can even differ
+	from layer to layer
+
+	*/
+
+#include "emu.h"
+#include "seta001.h"
+#include "screen.h"
+
+
+DEFINE_DEVICE_TYPE(SETA001_SPRITE, seta001_device, "seta001", "Seta SETA001 Sprites")
+
+seta001_device::seta001_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+	: device_t(mconfig, SETA001_SPRITE, tag, owner, clock)
+	, device_gfx_interface(mconfig, *this)
+	, m_gfxbank_cb(*this)
+	, m_fg_flipxoffs(0)
+	, m_fg_noflipxoffs(0)
+	, m_fg_flipyoffs(0)
+	, m_fg_noflipyoffs(0)
+	, m_bg_flipyoffs(0)
+	, m_bg_noflipyoffs(0)
+	, m_bg_flipxoffs(0)
+	, m_bg_noflipxoffs(0)
+	, m_colorbase(0)
+	, m_spritelimit(0x1ff)
+	, m_transpen(0)
+{
+}
+
+void seta001_device::device_start()
+{
+	m_spriteylow = std::make_unique<uint8_t[]>(0x300); // 0x200 low y + 0x100 bg stuff
+	m_spritecodelow = std::make_unique<uint8_t[]>(0x2000);
+	m_spritecodehigh = std::make_unique<uint8_t[]>(0x2000);
+
+	/* chukatai draws a column on the left from uninitialized RAM which causes garbage
+
+	   the reason for this is because the m_spriteylow only gets populated from 0x000 to 0x17d
+	   with the remainder of the ram (0x17e - 0x1ff) never being written to.
+
+	   If we initialize ram to 0xff it has a single line in the top left instead, but
+	   the PCB has no error at all, initializing to 0xf8 is better, but unlikely from a hardware
+	   perspective.
+
+	   jjsquawk has a garbage tile in the bottom left instead, but in this case the entire
+	   m_spriteylow is initalized (to 0), but sprite entry 0 for the other tables is never
+	   written to, again meaning it picks up whatever we clear the RAM to as positional
+	   values.
+
+	   we can't simply skip sprite 0 as other games (mostly tnzs.cpp ones, eg. kabukiz) rely
+	   on it being rendered, even if a number of seta.cpp games specifically avoid it.
+
+	   maybe other components on the board determine the sprite start / end limits on a per
+	   game basis?
+
+	*/
+
+	memset(m_spritectrl,0xff,4);
+	memset(m_spriteylow.get(),0xff,0x300);
+	memset(m_spritecodelow.get(),0xff,0x2000);
+	memset(m_spritecodehigh.get(),0xff,0x2000);
+
+	m_bgflag = 0x00;
+
+	m_gfxbank_cb.resolve();
+
+	save_item(NAME(m_bgflag));
+	save_item(NAME(m_spritectrl));
+	save_pointer(NAME(m_spriteylow),0x300);
+	save_pointer(NAME(m_spritecodelow),0x2000);
+	save_pointer(NAME(m_spritecodehigh),0x2000);
+}
+
+void seta001_device::device_reset()
+{
+}
+
+uint16_t seta001_device::spritectrl_r16(offs_t offset)
+{
+	return m_spritectrl[offset];
+}
+
+void seta001_device::spritectrl_w16(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+	if (ACCESSING_BITS_0_7)
+	{
+		m_spritectrl[offset] = data;
+	}
+}
+
+uint8_t seta001_device::spritectrl_r8(offs_t offset)
+{
+	return m_spritectrl[offset];
+}
+
+void seta001_device::spritectrl_w8(offs_t offset, uint8_t data)
+{
+	m_spritectrl[offset] = data;
+}
+
+uint16_t seta001_device::spriteylow_r16(offs_t offset)
+{
+	return m_spriteylow[offset];
+}
+
+void seta001_device::spriteylow_w16(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+	if (ACCESSING_BITS_0_7)
+	{
+		m_spriteylow[offset] = data;
+	}
+}
+
+uint8_t seta001_device::spriteylow_r8(offs_t offset)
+{
+	return m_spriteylow[offset];
+}
+
+void seta001_device::spriteylow_w8(offs_t offset, uint8_t data)
+{
+	m_spriteylow[offset] = data;
+}
+
+
+uint8_t seta001_device::spritecodelow_r8(offs_t offset)
+{
+	return m_spritecodelow[offset];
+}
+
+void seta001_device::spritecodelow_w8(offs_t offset, uint8_t data)
+{
+	m_spritecodelow[offset] = data;
+}
+
+uint8_t seta001_device::spritecodehigh_r8(offs_t offset)
+{
+	return m_spritecodehigh[offset];
+}
+
+void seta001_device::spritecodehigh_w8(offs_t offset, uint8_t data)
+{
+	m_spritecodehigh[offset] = data;
+}
+
+uint16_t seta001_device::spritecode_r16(offs_t offset)
+{
+	uint16_t ret = m_spritecodelow[offset];
+	ret |= m_spritecodehigh[offset] << 8;
+	return ret;
+}
+
+void seta001_device::spritecode_w16(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+	if (ACCESSING_BITS_0_7) m_spritecodelow[offset] = data & 0x00ff;
+	if (ACCESSING_BITS_8_15)  m_spritecodehigh[offset] = (data & 0xff00)>>8;
+}
+
+void seta001_device::spritebgflag_w8(uint8_t data)
+{
+	m_bgflag = data;
+}
+
+/***************************************************************************
+
+
+                                Sprites Drawing
+
+
+***************************************************************************/
+
+/*
+
+these mostly seem to be controlling the tilemap part of the chip
+
+twineagl:   10 2d 0f 10   (ship)
+tndrcade:   58 2d 07 18   (start of game - yes, flip on!)
+arbalest:   18 2d 0f 10   (logo)
+metafox :   18 21 0f f0   (bomb)
+zingzip :   10 2c 00 0f   (bomb)
+wrofaero:   10 21 00 ff   (test mode)
+thunderl:   10 6c 00 ff   (always?)
+krzybowl:   11 28 c0 ff   (game)
+kiwame  :   16 21 7f 00   (logo)
+oisipuzl:   59 20 00 00   (game - yes, flip on!)
+superman:   10 21 07 38   (game)
+twineagl:   00 27 00 0f   (test mode)
+doraemon:   19 2a 00 03   (always)
+srmp2:      1e 20 xx xx
+tnzs:       1a 20 xx xx
+
+format
+ byte 0     byte 1     byte 2     byte3
+ -f-e uUss  -Bb- cccc  ---- ----  ---- ----
+
+ f = flipy
+ e = possible enable (only disabled in twineagl test mode? check if it needs sprites)
+ u = sometimes set
+ U = sometimes set (srmp2)
+ s = start column
+ B = buffering control - toggles often (kabukiz doesn't seem to use these like the other games)
+ b = buffering control
+ c = number of columns, 0x0 = disabled, 0x01 = 16 columns 0x2 = 2 coluns ... 0xf = 15 columns
+
+ bytes 2 and 3 get set in a bitwize way in the tnzs driver games while horizontal scrolling happens, dependong on how
+ far we've scrolled, what they actually do is unclear.
+
+*/
+
+
+
+
+void seta001_device::draw_background( bitmap_ind16 &bitmap, const rectangle &cliprect, int bank_size)
+{
+	int transpen;
+
+	int offs, col;
+	int xoffs, yoffs;
+
+	int const total_color_codes   =   gfx(0)->colors();
+
+	int const ctrl    =   m_spritectrl[0];
+	int const ctrl2   =   m_spritectrl[1];
+
+	bool const flip   =   BIT(ctrl, 6);
+	int numcol  =   ctrl2 & 0x0f;
+
+	int scrollx, scrolly;
+
+	uint32_t upper;
+
+	const uint8_t* scrollram = &m_spriteylow[0x200];
+
+	/* Sprites Banking and/or Sprites Buffering */
+	uint16_t bank = ( ((ctrl2 ^ (~ctrl2<<1)) & 0x40) ? bank_size : 0 ); // bank_size = 0x800
+
+	int const max_y   =   0xf0;
+
+	int startcol = 0;
+
+	if (ctrl & 0x01)
+		startcol += 0x4;
+
+	if (ctrl & 0x02)
+		startcol += 0x8;
+
+	xoffs = flip ? m_bg_flipxoffs : m_bg_noflipxoffs;
+	yoffs = flip ? m_bg_flipyoffs : m_bg_noflipyoffs;
+
+	if (m_bgflag & 0x80)
+		transpen = -1;
+	else
+		transpen = m_transpen;
+
+	if (numcol == 1)
+		numcol = 16;
+
+	upper = m_spritectrl[2] + m_spritectrl[3] * 256;
+
+	for (col = 0; col < numcol; col++)
+	{
+		scrollx = scrollram[col * 0x10 + 4];
+		scrolly = scrollram[col * 0x10];
+
+		/* draw this column */
+		for ( offs = 0 ; offs < 0x20; offs += 1 )
+		{
+			int i = ((col+startcol)&0xf) * 32 + offs;
+
+			int code = ((m_spritecodehigh[i+0x400+bank]) << 8) | m_spritecodelow[i+0x400+bank];
+			int color =((m_spritecodehigh[i+0x600+bank]) << 8) | m_spritecodelow[i+0x600+bank];
+
+			int flipx   =   code & 0x8000;
+			int flipy   =   code & 0x4000;
+
+			int sx      =     scrollx + xoffs  + (offs & 1) * 16;
+			int sy      =   -(scrolly + yoffs) + (offs / 2) * 16;
+
+			if (upper & (1 << col)) sx -= 256;
+
+			if (flip)
+			{
+				sy = max_y - sy;
+				flipx = !flipx;
+				flipy = !flipy;
+			}
+
+			color   =   ( color >> (16-5) ) % total_color_codes;
+			code &= 0x3fff;
+
+			gfx(0)->transpen(bitmap,cliprect,
+					code,
+					color,
+					flipx,flipy,
+					((sx) & 0x1ff),((sy) & 0x0ff),
+					transpen);
+
+			gfx(0)->transpen(bitmap,cliprect,
+					code,
+					color,
+					flipx,flipy,
+					((sx) & 0x1ff)-512,((sy) & 0x0ff),
+					transpen);
+
+			gfx(0)->transpen(bitmap,cliprect,
+					code,
+					color,
+					flipx,flipy,
+					((sx) & 0x1ff),((sy) & 0x0ff)-256,
+					transpen);
+
+			gfx(0)->transpen(bitmap,cliprect,
+					code,
+					color,
+					flipx,flipy,
+					((sx) & 0x1ff)-512,((sy) & 0x0ff)-256,
+					transpen);
+
+		}
+	}
+}
+
+
+void seta001_device::draw_foreground( screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect, int bank_size)
+{
+	int const screenflip = (m_spritectrl[0] & 0x40) >> 6;
+	int const ctrl2 = m_spritectrl[1];
+
+	int const total_color_codes   =   gfx(0)->colors();
+
+	uint8_t *char_pointer = &m_spritecodelow[0x0000];
+	uint8_t *ctrl_pointer = &m_spritecodehigh[0x0000];
+	uint8_t *x_pointer = &m_spritecodelow[0x0200];
+	uint8_t *color_pointer = &m_spritecodehigh[0x0200];
+
+	// note that drgnunit, stg and qzkklogy run on the same board, yet they need different alignment
+	int xoffs = screenflip ? m_fg_flipxoffs : m_fg_noflipxoffs;
+	int yoffs = screenflip ? m_fg_flipyoffs : m_fg_noflipyoffs;
+
+	if ((ctrl2 ^ (~ctrl2 << 1)) & 0x40)
+	{
+		char_pointer += bank_size;
+		x_pointer += bank_size;
+		ctrl_pointer += bank_size;
+		color_pointer += bank_size;
+	}
+
+	int const max_y = screen.height();
+
+	/* Draw up to 512 sprites, mjyuugi has glitches if you draw them all.. */
+	for (int i = m_spritelimit; i >= 0; i--)
+	{
+		int code, color, sx, sy, flipx, flipy;
+
+		code = char_pointer[i] + ((ctrl_pointer[i] & 0x3f) << 8);
+		color = (color_pointer[i] & 0xf8) >> 3;
+
+		sx = x_pointer[i] - ((color_pointer[i] & 1) << 8);
+		sy =  (m_spriteylow[i] & 0xff);
+		flipx = ctrl_pointer[i] & 0x80;
+		flipy = ctrl_pointer[i] & 0x40;
+
+		if (!m_gfxbank_cb.isnull()) code = m_gfxbank_cb(code, color_pointer[i]);
+
+		color %= total_color_codes;
+
+		color += m_colorbase;
+
+		if (screenflip)
+		{
+			sy = max_y - sy
+				+(screen.height() - (screen.visible_area().max_y + 1));
+			flipx = !flipx;
+			flipy = !flipy;
+		}
+
+		gfx(0)->transpen(bitmap,cliprect,
+				code,
+				color,
+				flipx,flipy,
+				((sx + xoffs)&0x1ff),
+				max_y - ((sy + yoffs) & 0x0ff),m_transpen);
+
+		/* wrap around x */
+		gfx(0)->transpen(bitmap,cliprect,
+				code,
+				color,
+				flipx,flipy,
+				((sx + xoffs)&0x1ff) - 512,
+				max_y - ((sy + yoffs) & 0x0ff),m_transpen);
+
+
+		gfx(0)->transpen(bitmap,cliprect,
+				code,
+				color,
+				flipx,flipy,
+				((sx + xoffs)&0x1ff),
+				max_y - ((sy + yoffs) & 0x0ff)-256,m_transpen);
+
+		/* wrap around x */
+		gfx(0)->transpen(bitmap,cliprect,
+				code,
+				color,
+				flipx,flipy,
+				((sx + xoffs)&0x1ff) - 512,
+				max_y - ((sy + yoffs) & 0x0ff)-256,m_transpen);
+
+	}
+}
+
+
+
+void seta001_device::setac_eof()
+{
+	// is this handling right?
+	// it differs to tnzs, and thundercade has sprite flickering issues (not related to the devicification)
+
+	int const ctrl2 = m_spritectrl[1];
+
+	if (~ctrl2 & 0x20)
+	{
+		if (ctrl2 & 0x40)
+		{
+			memcpy( &m_spritecodelow[0x0000], &m_spritecodelow[0x1000],0x800);
+			memcpy(&m_spritecodehigh[0x0000],&m_spritecodehigh[0x1000],0x800);
+		}
+		else
+		{
+			memcpy( &m_spritecodelow[0x1000], &m_spritecodelow[0x0000],0x800);
+			memcpy(&m_spritecodehigh[0x1000],&m_spritecodehigh[0x0000],0x800);
+		}
+	}
+}
+
+void seta001_device::tnzs_eof( void )
+{
+	int const ctrl2 = m_spritectrl[1];
+	if (~ctrl2 & 0x20)
+	{
+		// note I copy sprites only. setac implementation also copies the "floating tilemap"
+		if (ctrl2 & 0x40)
+		{
+			memcpy( &m_spritecodelow[0x0000],  &m_spritecodelow[0x0800], 0x0400);
+			memcpy(&m_spritecodehigh[0x0000], &m_spritecodehigh[0x0800], 0x0400);
+		}
+		else
+		{
+			memcpy( &m_spritecodelow[0x0800],  &m_spritecodelow[0x0000], 0x0400);
+			memcpy(&m_spritecodehigh[0x0800], &m_spritecodehigh[0x0000], 0x0400);
+		}
+
+		// and I copy the "floating tilemap" BACKWARDS - this fixes kabukiz
+		memcpy( &m_spritecodelow[0x0400],  &m_spritecodelow[0x0c00], 0x0400);
+		memcpy(&m_spritecodehigh[0x0400], &m_spritecodehigh[0x0c00], 0x0400);
+	}
+
+}
+
+void seta001_device::draw_sprites(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect, int bank_size)
+{
+	draw_background(bitmap, cliprect, bank_size);
+	draw_foreground(screen, bitmap, cliprect, bank_size);
+}

snapshots/jotego_jtcores_pr1111/cores/kiwi/doc/seta001.h

@@ -0,0 +1,91 @@
+// license:BSD-3-Clause
+// copyright-holders:Luca Elia, David Haywood
+#ifndef MAME_VIDEO_SETA001_H
+#define MAME_VIDEO_SETA001_H
+
+#pragma once
+
+typedef device_delegate<int (uint16_t code, uint8_t color)> gfxbank_cb_delegate;
+
+#define SETA001_SPRITE_GFXBANK_CB_MEMBER(_name) int _name(uint16_t code, uint8_t color)
+
+class seta001_device : public device_t, public device_gfx_interface
+{
+public:
+	seta001_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+	template <typename T> seta001_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, T &&palette_tag, const gfx_decode_entry *gfxinfo)
+		: seta001_device(mconfig, tag, owner, clock)
+	{
+		set_info(gfxinfo);
+		set_palette(std::forward<T>(palette_tag));
+	}
+
+	// configuration
+	template <typename... T> void set_gfxbank_callback(T &&... args) { m_gfxbank_cb.set(std::forward<T>(args)...); }
+
+	void spritebgflag_w8(uint8_t data);
+
+	uint16_t spritectrl_r16(offs_t offset);
+	void spritectrl_w16(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+	uint8_t spritectrl_r8(offs_t offset);
+	void spritectrl_w8(offs_t offset, uint8_t data);
+
+	uint16_t spriteylow_r16(offs_t offset);
+	void spriteylow_w16(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+	uint8_t spriteylow_r8(offs_t offset);
+	void spriteylow_w8(offs_t offset, uint8_t data);
+
+	uint8_t spritecodelow_r8(offs_t offset);
+	void spritecodelow_w8(offs_t offset, uint8_t data);
+	uint8_t spritecodehigh_r8(offs_t offset);
+	void spritecodehigh_w8(offs_t offset, uint8_t data);
+	uint16_t spritecode_r16(offs_t offset);
+	void spritecode_w16(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+
+	void draw_sprites(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect, int bank_size);
+
+	void setac_eof();
+	void tnzs_eof();
+
+	// position kludges for seta.cpp & srmp2.cpp
+	void set_fg_xoffsets(int flip, int noflip) { m_fg_flipxoffs = flip; m_fg_noflipxoffs = noflip; }
+	void set_fg_yoffsets(int flip, int noflip) { m_fg_flipyoffs = flip; m_fg_noflipyoffs = noflip; }
+	void set_bg_yoffsets(int flip, int noflip) { m_bg_flipyoffs = flip; m_bg_noflipyoffs = noflip; }
+	void set_bg_xoffsets(int flip, int noflip) { m_bg_flipxoffs = flip; m_bg_noflipxoffs = noflip; }
+
+	void set_colorbase(int base) { m_colorbase = base; }
+	void set_spritelimit(int limit) { m_spritelimit = limit; }
+	void set_transpen(int pen) { m_transpen = pen; }
+
+	int is_flipped() { return ((m_spritectrl[ 0 ] & 0x40) >> 6); }
+
+protected:
+	virtual void device_start() override;
+	virtual void device_reset() override;
+
+private:
+	void draw_background(bitmap_ind16 &bitmap, const rectangle &cliprect, int bank_size);
+	void draw_foreground(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect, int bank_size);
+
+	gfxbank_cb_delegate m_gfxbank_cb;
+
+	// configuration
+	int m_fg_flipxoffs, m_fg_noflipxoffs;
+	int m_fg_flipyoffs, m_fg_noflipyoffs;
+	int m_bg_flipyoffs, m_bg_noflipyoffs;
+	int m_bg_flipxoffs, m_bg_noflipxoffs;
+	int m_colorbase;
+	int m_spritelimit;
+	int m_transpen;
+
+	// live state
+	uint8_t m_bgflag = 0;
+	uint8_t m_spritectrl[4];
+	std::unique_ptr<uint8_t[]> m_spriteylow;
+	std::unique_ptr<uint8_t[]> m_spritecodelow; // tnzs.cpp stuff only uses half?
+	std::unique_ptr<uint8_t[]> m_spritecodehigh; // ^
+};
+
+DECLARE_DEVICE_TYPE(SETA001_SPRITE, seta001_device)
+
+#endif // MAME_VIDEO_SETA001_H

snapshots/jotego_jtcores_pr1111/cores/kiwi/doc/tnzs.h

@@ -0,0 +1,302 @@
+// license:BSD-3-Clause
+// copyright-holders:Luca Elia, Mirko Buffoni, Takahiro Nogi
+#ifndef MAME_INCLUDES_TNZS_H
+#define MAME_INCLUDES_TNZS_H
+
+#pragma once
+
+
+#include "cpu/mcs48/mcs48.h"
+#include "machine/bankdev.h"
+#include "machine/gen_latch.h"
+#include "machine/upd4701.h"
+#include "sound/dac.h"
+#include "sound/samples.h"
+#include "video/seta001.h"
+#include "emupal.h"
+#include "screen.h"
+
+class tnzs_base_state : public driver_device
+{
+public:
+	tnzs_base_state(const machine_config &mconfig, device_type type, const char *tag)
+		: driver_device(mconfig, type, tag)
+		, m_maincpu(*this, "maincpu")
+		, m_subcpu(*this, "sub")
+		, m_seta001(*this, "spritegen")
+		, m_palette(*this, "palette")
+		, m_screen(*this, "screen")
+		, m_mainbank(*this, "mainbank")
+		, m_subbank(*this, "subbank")
+	{ }
+
+	void tnzs_base(machine_config &config);
+	void tnzs_mainbank(machine_config &config);
+
+protected:
+	virtual void machine_start() override;
+
+	virtual void bankswitch1_w(uint8_t data);
+
+	void ramrom_bankswitch_w(uint8_t data);
+
+	void prompalette(palette_device &palette) const;
+	uint32_t screen_update_tnzs(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
+	DECLARE_WRITE_LINE_MEMBER(screen_vblank_tnzs);
+
+	void base_sub_map(address_map &map);
+	void main_map(address_map &map);
+	void mainbank_map(address_map &map);
+
+	/* devices */
+	required_device<cpu_device> m_maincpu;
+	optional_device<cpu_device> m_subcpu;
+	required_device<seta001_device> m_seta001;
+	required_device<palette_device> m_palette;
+	required_device<screen_device> m_screen;
+	optional_device<address_map_bank_device> m_mainbank; /* FIXME: optional because of reuse from cchance.cpp */
+	optional_memory_bank m_subbank; /* FIXME: optional because of reuse from cchance.cpp */
+
+	/* misc / mcu */
+	int      m_bank2 = 0;
+};
+
+class tnzs_mcu_state : public tnzs_base_state
+{
+public:
+	tnzs_mcu_state(const machine_config &mconfig, device_type type, const char *tag, bool lockout_level)
+		: tnzs_base_state(mconfig, type, tag)
+		, m_mcu(*this, "mcu")
+		, m_upd4701(*this, "upd4701")
+		, m_in0(*this, "IN0")
+		, m_in1(*this, "IN1")
+		, m_in2(*this, "IN2")
+		, m_input_select(0)
+		, m_lockout_level(lockout_level)
+	{ }
+
+	void tnzs(machine_config &config);
+
+protected:
+	virtual void bankswitch1_w(uint8_t data) override;
+
+	uint8_t mcu_port1_r();
+	void mcu_port2_w(uint8_t data);
+	uint8_t mcu_r(offs_t offset);
+	void mcu_w(offs_t offset, uint8_t data);
+
+	uint8_t analog_r(offs_t offset);
+
+	void tnzs_sub_map(address_map &map);
+
+	required_device<upi41_cpu_device> m_mcu;
+	optional_device<upd4701_device> m_upd4701;
+
+	required_ioport m_in0;
+	required_ioport m_in1;
+	required_ioport m_in2;
+
+	int      m_input_select = 0;
+	bool     m_lockout_level = false;
+};
+
+class tnzs_state : public tnzs_mcu_state
+{
+public:
+	tnzs_state(const machine_config &mconfig, device_type type, const char *tag)
+		: tnzs_mcu_state(mconfig, type, tag, true)
+	{ }
+};
+
+class extrmatn_state : public tnzs_mcu_state
+{
+public:
+	extrmatn_state(const machine_config &mconfig, device_type type, const char *tag)
+		: tnzs_mcu_state(mconfig, type, tag, false)
+	{ }
+	void extrmatn(machine_config &config);
+	void plumppop(machine_config &config);
+
+protected:
+	void prompal_main_map(address_map &map);
+};
+
+class arknoid2_state : public extrmatn_state
+{
+public:
+	arknoid2_state(const machine_config &mconfig, device_type type, const char *tag)
+		: extrmatn_state(mconfig, type, tag)
+		, m_coin1(*this, "COIN1")
+		, m_coin2(*this, "COIN2")
+		, m_in0(*this, "IN0")
+		, m_in1(*this, "IN1")
+		, m_in2(*this, "IN2")
+	{ }
+
+	void arknoid2(machine_config &config);
+
+private:
+	virtual void machine_start() override;
+	virtual void machine_reset() override;
+
+	virtual void bankswitch1_w(uint8_t data) override;
+
+	uint8_t mcu_r(offs_t offset);
+	void mcu_w(offs_t offset, uint8_t data);
+	INTERRUPT_GEN_MEMBER(mcu_interrupt);
+
+	void arknoid2_sub_map(address_map &map);
+
+	required_ioport m_coin1;
+	required_ioport m_coin2;
+	required_ioport m_in0;
+	required_ioport m_in1;
+	required_ioport m_in2;
+
+	void mcu_reset();
+
+	int      m_mcu_initializing = 0;
+	int      m_mcu_coinage_init = 0;
+	int      m_mcu_command = 0;
+	int      m_mcu_readcredits = 0;
+	int      m_mcu_reportcoin = 0;
+	int      m_insertcoin = 0;
+	uint8_t    m_mcu_coinage[4]{};
+	uint8_t    m_mcu_coins_a = 0;
+	uint8_t    m_mcu_coins_b = 0;
+	uint8_t    m_mcu_credits = 0;
+
+	void mcu_handle_coins(int coin);
+};
+
+class kageki_state : public tnzs_base_state
+{
+public:
+	kageki_state(const machine_config &mconfig, device_type type, const char *tag)
+		: tnzs_base_state(mconfig, type, tag)
+		, m_samples(*this, "samples")
+		, m_dswa(*this, "DSWA")
+		, m_dswb(*this, "DSWB")
+		, m_csport_sel(0)
+	{ }
+
+	void kageki(machine_config &config);
+
+	void init_kageki();
+
+protected:
+	virtual void machine_start() override;
+	virtual void machine_reset() override;
+
+private:
+	static constexpr unsigned MAX_SAMPLES = 0x2f;
+
+	virtual void bankswitch1_w(uint8_t data) override;
+
+	uint8_t csport_r();
+	void csport_w(uint8_t data);
+
+	DECLARE_MACHINE_RESET(kageki);
+
+	SAMPLES_START_CB_MEMBER(init_samples);
+
+	void kageki_sub_map(address_map &map);
+
+	required_device<samples_device> m_samples;
+
+	required_ioport m_dswa;
+	required_ioport m_dswb;
+
+	/* sound-related */
+	std::unique_ptr<int16_t[]>    m_sampledata[MAX_SAMPLES];
+	int      m_samplesize[MAX_SAMPLES]{};
+
+	int      m_csport_sel = 0;
+};
+
+class jpopnics_state : public tnzs_base_state
+{
+public:
+	jpopnics_state(const machine_config &mconfig, device_type type, const char *tag)
+		: tnzs_base_state(mconfig, type, tag)
+		, m_upd4701(*this, "upd4701")
+	{ }
+
+	void jpopnics(machine_config &config);
+
+protected:
+	virtual void machine_reset() override;
+
+private:
+	void subbankswitch_w(uint8_t data);
+
+	void jpopnics_main_map(address_map &map);
+	void jpopnics_sub_map(address_map &map);
+	required_device<upd4701_device> m_upd4701;
+};
+
+class insectx_state : public tnzs_base_state
+{
+public:
+	insectx_state(const machine_config &mconfig, device_type type, const char *tag)
+		: tnzs_base_state(mconfig, type, tag)
+	{ }
+
+	void insectx(machine_config &config);
+
+private:
+	virtual void bankswitch1_w(uint8_t data) override;
+	void insectx_sub_map(address_map &map);
+};
+
+class tnzsb_state : public tnzs_base_state
+{
+public:
+	tnzsb_state(const machine_config &mconfig, device_type type, const char *tag)
+		: tnzs_base_state(mconfig, type, tag)
+		, m_audiocpu(*this, "audiocpu")
+		, m_soundlatch(*this, "soundlatch")
+	{ }
+
+	void tnzsb(machine_config &config);
+
+protected:
+	DECLARE_WRITE_LINE_MEMBER(ym2203_irqhandler);
+
+	void sound_command_w(uint8_t data);
+
+	virtual void bankswitch1_w(uint8_t data) override;
+
+	void tnzsb_base_sub_map(address_map &map);
+	void tnzsb_cpu2_map(address_map &map);
+	void tnzsb_io_map(address_map &map);
+	void tnzsb_main_map(address_map &map);
+	void tnzsb_sub_map(address_map &map);
+
+	required_device<cpu_device> m_audiocpu;
+	required_device<generic_latch_8_device> m_soundlatch;
+};
+
+class kabukiz_state : public tnzsb_state
+{
+public:
+	kabukiz_state(const machine_config &mconfig, device_type type, const char *tag)
+		: tnzsb_state(mconfig, type, tag)
+		, m_audiobank(*this, "audiobank")
+	{ }
+
+	void kabukiz(machine_config &config);
+
+protected:
+	virtual void machine_start() override;
+
+private:
+	void sound_bank_w(uint8_t data);
+
+	void kabukiz_cpu2_map(address_map &map);
+	void kabukiz_sub_map(address_map &map);
+
+	required_memory_bank m_audiobank;
+};
+
+#endif // MAME_INCLUDES_TNZS_H

snapshots/jotego_jtcores_pr1111/cores/kiwi/doc/tnzs_m.cpp

@@ -0,0 +1,498 @@
+// license:BSD-3-Clause
+// copyright-holders:Luca Elia, Mirko Buffoni, Takahiro Nogi,Stephane Humbert
+/***************************************************************************
+
+  machine.c
+
+  Functions to emulate general aspects of the machine (RAM, ROM, interrupts,
+  I/O ports)
+
+  The I8742 MCU takes care of handling the coin inputs and the tilt switch.
+  To simulate this, we read the status in the interrupt handler for the main
+  CPU and update the counters appropriately. We also must take care of
+  handling the coin/credit settings ourselves.
+
+***************************************************************************/
+
+#include "emu.h"
+#include "cpu/mcs48/mcs48.h"
+#include "tnzs.h"
+
+uint8_t tnzs_mcu_state::mcu_r(offs_t offset)
+{
+	uint8_t data = m_mcu->upi41_master_r(offset & 1);
+	m_subcpu->yield();
+
+//  logerror("%s: read %02x from mcu $c00%01x\n", m_maincpu->pcbase(), data, offset);
+
+	return data;
+}
+
+void tnzs_mcu_state::mcu_w(offs_t offset, uint8_t data)
+{
+//  logerror("%s: write %02x to mcu $c00%01x\n", m_maincpu->pcbase(), data, offset);
+
+	m_mcu->upi41_master_w(offset & 1, data);
+}
+
+uint8_t tnzs_mcu_state::mcu_port1_r()
+{
+	int data = 0;
+
+	switch (m_input_select)
+	{
+		case 0x0a:  data = m_in2->read(); break;
+		case 0x0c:  data = m_in0->read(); break;
+		case 0x0d:  data = m_in1->read(); break;
+		default:    data = 0xff; break;
+	}
+
+//  logerror("%s:  Read %02x from port 1\n", m_maincpu->pcbase(), data);
+
+	return data;
+}
+
+void tnzs_mcu_state::mcu_port2_w(uint8_t data)
+{
+	machine().bookkeeping().coin_lockout_w(0, (data & 0x40) != 0 ? m_lockout_level : !m_lockout_level);
+	machine().bookkeeping().coin_lockout_w(1, (data & 0x80) != 0 ? m_lockout_level : !m_lockout_level);
+	machine().bookkeeping().coin_counter_w(0, (~data & 0x10));
+	machine().bookkeeping().coin_counter_w(1, (~data & 0x20));
+
+	m_input_select = data & 0xf;
+}
+
+uint8_t tnzs_mcu_state::analog_r(offs_t offset)
+{
+	return m_upd4701.found() ? m_upd4701->read_xy(offset) : 0;
+}
+
+void arknoid2_state::mcu_reset()
+{
+	m_mcu_initializing = 3;
+	m_mcu_coinage_init = 0;
+	m_mcu_coinage[0] = 1;
+	m_mcu_coinage[1] = 1;
+	m_mcu_coinage[2] = 1;
+	m_mcu_coinage[3] = 1;
+	m_mcu_coins_a = 0;
+	m_mcu_coins_b = 0;
+	m_mcu_credits = 0;
+	m_mcu_reportcoin = 0;
+	m_mcu_command = 0;
+}
+
+void arknoid2_state::mcu_handle_coins( int coin )
+{
+	/* The coin inputs and coin counters are managed by the i8742 mcu. */
+	/* Here we simulate it. */
+	/* Credits are limited to 9, so more coins should be rejected */
+	/* Coin/Play settings must also be taken into consideration */
+
+	if (coin & 0x08)    /* tilt */
+		m_mcu_reportcoin = coin;
+	else if (coin && coin != m_insertcoin)
+	{
+		if (coin & 0x01)    /* coin A */
+		{
+//          logerror("Coin dropped into slot A\n");
+			machine().bookkeeping().coin_counter_w(0,1); machine().bookkeeping().coin_counter_w(0,0); /* Count slot A */
+			m_mcu_coins_a++;
+			if (m_mcu_coins_a >= m_mcu_coinage[0])
+			{
+				m_mcu_coins_a -= m_mcu_coinage[0];
+				m_mcu_credits += m_mcu_coinage[1];
+				if (m_mcu_credits >= 9)
+				{
+					m_mcu_credits = 9;
+					machine().bookkeeping().coin_lockout_global_w(1); /* Lock all coin slots */
+				}
+				else
+				{
+					machine().bookkeeping().coin_lockout_global_w(0); /* Unlock all coin slots */
+				}
+			}
+		}
+
+		if (coin & 0x02)    /* coin B */
+		{
+//          logerror("Coin dropped into slot B\n");
+			machine().bookkeeping().coin_counter_w(1,1); machine().bookkeeping().coin_counter_w(1,0); /* Count slot B */
+			m_mcu_coins_b++;
+			if (m_mcu_coins_b >= m_mcu_coinage[2])
+			{
+				m_mcu_coins_b -= m_mcu_coinage[2];
+				m_mcu_credits += m_mcu_coinage[3];
+				if (m_mcu_credits >= 9)
+				{
+					m_mcu_credits = 9;
+					machine().bookkeeping().coin_lockout_global_w(1); /* Lock all coin slots */
+				}
+				else
+				{
+					machine().bookkeeping().coin_lockout_global_w(0); /* Unlock all coin slots */
+				}
+			}
+		}
+
+		if (coin & 0x04)    /* service */
+		{
+//          logerror("Coin dropped into service slot C\n");
+			m_mcu_credits++;
+		}
+
+		m_mcu_reportcoin = coin;
+	}
+	else
+	{
+		if (m_mcu_credits < 9)
+			machine().bookkeeping().coin_lockout_global_w(0); /* Unlock all coin slots */
+
+		m_mcu_reportcoin = 0;
+	}
+	m_insertcoin = coin;
+}
+
+/*********************************
+
+TNZS sync bug kludge
+
+In all TNZS versions there is code like this:
+
+0C5E: ld   ($EF10),a
+0C61: ld   a,($EF10)
+0C64: inc  a
+0C65: ret  nz
+0C66: jr   $0C61
+
+which is sometimes executed by the main cpu when it writes to shared RAM a
+command for the second CPU. The intended purpose of the code is to wait an
+acknowledge from the sub CPU: the sub CPU writes FF to the same location
+after reading the command.
+
+However the above code is wrong. The "ret nz" instruction means that the
+loop will be exited only when the contents of $EF10 are *NOT* $FF!!
+On the real board, this casues little harm: the main CPU will just write
+the command, read it back and, since it's not $FF, return immediately. There
+is a chance that the command might go lost, but this will cause no major
+harm, the worse that can happen is that the background tune will not change.
+
+In MAME, however, since CPU interleaving is not perfect, it can happen that
+the main CPU ends its timeslice after writing to EF10 but before reading it
+back. In the meantime, the sub CPU will run, read the command and write FF
+there - therefore causing the main CPU to enter an endless loop.
+
+Unlike the usual sync problems in MAME, which can be fixed by increasing the
+interleave factor, in this case increasing it will actually INCREASE the
+chance of entering the endless loop - because it will increase the chances of
+the main CPU ending its timeslice at the wrong moment.
+
+So what we do here is catch writes by the main CPU to the RAM location, and
+process them using a timer, in order to
+a) force a resync of the two CPUs
+b) make sure the main CPU will be the first one to run after the location is
+   changed
+
+Since the answer from the sub CPU is ignored, we don't even need to boost
+interleave.
+
+*********************************/
+
+/*
+TIMER_CALLBACK_MEMBER(tnzs_base_state::kludge_callback)
+{
+    tnzs_sharedram[0x0f10] = param;
+}
+
+void tnzs_base_state::tnzs_sync_kludge_w(uint8_t data)
+{
+    machine().scheduler().synchronize(timer_expired_delegate(FUNC(tnzs_base_state::kludge_callback),this), data);
+}
+*/
+
+uint8_t arknoid2_state::mcu_r(offs_t offset)
+{
+	static const char mcu_startup[] = "\x55\xaa\x5a";
+
+	//logerror("%s: read mcu %04x\n", m_maincpu->pc(), 0xc000 + offset);
+
+	if (offset == 0)
+	{
+		/* if the mcu has just been reset, return startup code */
+		if (m_mcu_initializing)
+		{
+			m_mcu_initializing--;
+			return mcu_startup[2 - m_mcu_initializing];
+		}
+
+		switch (m_mcu_command)
+		{
+			case 0x41:
+				return m_mcu_credits;
+
+			case 0xc1:
+				/* Read the credit counter or the inputs */
+				if (m_mcu_readcredits == 0)
+				{
+					m_mcu_readcredits = 1;
+					if (m_mcu_reportcoin & 0x08)
+					{
+						m_mcu_initializing = 3;
+						return 0xee;    /* tilt */
+					}
+					else return m_mcu_credits;
+				}
+				else return m_in0->read();  /* buttons */
+
+			default:
+				logerror("error, unknown mcu command\n");
+				/* should not happen */
+				return 0xff;
+		}
+	}
+	else
+	{
+		/*
+		status bits:
+		0 = mcu is ready to send data (read from c000)
+		1 = mcu has read data (from c000)
+		2 = unused
+		3 = unused
+		4-7 = coin code
+		      0 = nothing
+		      1,2,3 = coin switch pressed
+		      e = tilt
+		*/
+		if (m_mcu_reportcoin & 0x08) return 0xe1;   /* tilt */
+		if (m_mcu_reportcoin & 0x01) return 0x11;   /* coin 1 (will trigger "coin inserted" sound) */
+		if (m_mcu_reportcoin & 0x02) return 0x21;   /* coin 2 (will trigger "coin inserted" sound) */
+		if (m_mcu_reportcoin & 0x04) return 0x31;   /* coin 3 (will trigger "coin inserted" sound) */
+		return 0x01;
+	}
+}
+
+void arknoid2_state::mcu_w(offs_t offset, uint8_t data)
+{
+	if (offset == 0)
+	{
+		//logerror("%s: write %02x to mcu %04x\n", m_maincpu->pc(), data, 0xc000 + offset);
+		if (m_mcu_command == 0x41)
+		{
+			m_mcu_credits = (m_mcu_credits + data) & 0xff;
+		}
+	}
+	else
+	{
+		/*
+		0xc1: read number of credits, then buttons
+		0x54+0x41: add value to number of credits
+		0x15: sub 1 credit (when "Continue Play" only)
+		0x84: coin 1 lockout (issued only in test mode)
+		0x88: coin 2 lockout (issued only in test mode)
+		0x80: release coin lockout (issued only in test mode)
+		during initialization, a sequence of 4 bytes sets coin/credit settings
+		*/
+		//logerror("%s: write %02x to mcu %04x\n", m_maincpu->pc(), data, 0xc000 + offset);
+
+		if (m_mcu_initializing)
+		{
+			/* set up coin/credit settings */
+			m_mcu_coinage[m_mcu_coinage_init++] = data;
+			if (m_mcu_coinage_init == 4)
+				m_mcu_coinage_init = 0; /* must not happen */
+		}
+
+		if (data == 0xc1)
+			m_mcu_readcredits = 0;  /* reset input port number */
+
+		if (data == 0x15)
+		{
+			m_mcu_credits = (m_mcu_credits - 1) & 0xff;
+			if (m_mcu_credits == 0xff)
+				m_mcu_credits = 0;
+		}
+		m_mcu_command = data;
+	}
+}
+
+INTERRUPT_GEN_MEMBER(arknoid2_state::mcu_interrupt)
+{
+	int coin = ((m_coin1->read() & 1) << 0);
+	coin |= ((m_coin2->read() & 1) << 1);
+	coin |= ((m_in2->read() & 3) << 2);
+	coin ^= 0x0c;
+	mcu_handle_coins(coin);
+
+	device.execute().set_input_line(0, HOLD_LINE);
+}
+
+void arknoid2_state::machine_reset()
+{
+	/* initialize the mcu simulation */
+	mcu_reset();
+
+	m_mcu_readcredits = 0;
+	m_insertcoin = 0;
+}
+
+void kageki_state::machine_reset()
+{
+	tnzs_base_state::machine_reset();
+	m_csport_sel = 0;
+}
+
+void tnzs_base_state::machine_start()
+{
+	uint8_t *sub = memregion("sub")->base();
+
+	m_bank2 = 0;
+	m_mainbank->set_bank(2);
+
+	m_subbank->configure_entries(0, 4, &sub[0x08000], 0x2000);
+	m_subbank->set_entry(m_bank2);
+
+	save_item(NAME(m_bank2));
+}
+
+void arknoid2_state::machine_start()
+{
+	tnzs_base_state::machine_start();
+
+	save_item(NAME(m_mcu_readcredits));
+	save_item(NAME(m_insertcoin));
+	save_item(NAME(m_mcu_initializing));
+	save_item(NAME(m_mcu_coinage_init));
+	save_item(NAME(m_mcu_coinage));
+	save_item(NAME(m_mcu_coins_a));
+	save_item(NAME(m_mcu_coins_b));
+	save_item(NAME(m_mcu_credits));
+	save_item(NAME(m_mcu_reportcoin));
+	save_item(NAME(m_mcu_command));
+
+	// kludge to make device work with active-high coin inputs
+	m_upd4701->left_w(0);
+	m_upd4701->middle_w(0);
+}
+
+void kageki_state::machine_start()
+{
+	tnzs_base_state::machine_start();
+	save_item(NAME(m_csport_sel));
+}
+
+void kabukiz_state::machine_start()
+{
+	tnzs_base_state::machine_start();
+	uint8_t *sound = memregion("audiocpu")->base();
+	m_audiobank->configure_entries(0, 8, &sound[0x00000], 0x4000);
+}
+
+void tnzs_base_state::ramrom_bankswitch_w(uint8_t data)
+{
+//  logerror("%s: writing %02x to bankswitch\n", m_maincpu->pc(),data);
+
+	// bit 4 resets the second CPU
+	m_subcpu->set_input_line(INPUT_LINE_RESET, BIT(data, 4) ? CLEAR_LINE : ASSERT_LINE);
+
+	// bits 0-2 select RAM/ROM bank
+	m_mainbank->set_bank(data & 0x07);
+}
+
+void arknoid2_state::bankswitch1_w(uint8_t data)
+{
+	tnzs_base_state::bankswitch1_w(data);
+
+	if (BIT(data, 2))
+		mcu_reset();
+
+	// never actually written by arknoid2 (though code exists to do it)
+	m_upd4701->resetx_w(BIT(data, 5));
+	m_upd4701->resety_w(BIT(data, 5));
+}
+
+void insectx_state::bankswitch1_w(uint8_t data)
+{
+	tnzs_base_state::bankswitch1_w(data);
+
+	machine().bookkeeping().coin_lockout_w(0, BIT(~data, 2));
+	machine().bookkeeping().coin_lockout_w(1, BIT(~data, 3));
+	machine().bookkeeping().coin_counter_w(0, BIT(data, 4));
+	machine().bookkeeping().coin_counter_w(1, BIT(data, 5));
+}
+
+void tnzsb_state::bankswitch1_w(uint8_t data) // kabukiz_state
+{
+	tnzs_base_state::bankswitch1_w(data);
+
+	machine().bookkeeping().coin_lockout_w(0, BIT(~data, 4));
+	machine().bookkeeping().coin_lockout_w(1, BIT(~data, 5));
+	machine().bookkeeping().coin_counter_w(0, BIT(data, 2));
+	machine().bookkeeping().coin_counter_w(1, BIT(data, 3));
+}
+
+void kageki_state::bankswitch1_w(uint8_t data)
+{
+	tnzs_base_state::bankswitch1_w(data);
+
+	machine().bookkeeping().coin_lockout_global_w(BIT(~data, 5));
+	machine().bookkeeping().coin_counter_w(0, BIT(data, 2));
+	machine().bookkeeping().coin_counter_w(1, BIT(data, 3));
+}
+
+void tnzs_mcu_state::bankswitch1_w(uint8_t data)
+{
+	tnzs_base_state::bankswitch1_w(data);
+
+	if (BIT(data, 2) && m_mcu)
+		m_mcu->pulse_input_line(INPUT_LINE_RESET, attotime::zero);
+
+	// written only at startup by plumppop?
+	if (m_upd4701.found())
+	{
+		m_upd4701->resetx_w(BIT(data, 5));
+		m_upd4701->resety_w(BIT(data, 5));
+	}
+}
+
+void tnzs_base_state::bankswitch1_w(uint8_t data)
+{
+//  logerror("%s: writing %02x to bankswitch 1\n", m_maincpu->pc(),data);
+
+	// bits 0-1 select ROM bank
+	m_bank2 = data & 0x03;
+	m_subbank->set_entry(m_bank2);
+}
+
+void jpopnics_state::machine_reset()
+{
+	tnzs_base_state::machine_reset();
+}
+
+void jpopnics_state::subbankswitch_w(uint8_t data)
+{
+	// bits 0-1 select ROM bank
+	m_subbank->set_entry(data & 0x03);
+
+	// written once at startup
+	m_upd4701->resetx_w(BIT(data, 5));
+	m_upd4701->resety_w(BIT(data, 5));
+}
+
+void tnzsb_state::sound_command_w(uint8_t data)
+{
+	m_soundlatch->write(data);
+	m_audiocpu->set_input_line_and_vector(0, HOLD_LINE, 0xff); // Z80
+}
+
+// handler called by the 2203 emulator when the internal timers cause an IRQ
+WRITE_LINE_MEMBER(tnzsb_state::ym2203_irqhandler)
+{
+	m_audiocpu->set_input_line(INPUT_LINE_NMI, state ? ASSERT_LINE : CLEAR_LINE);
+}
+
+void kabukiz_state::sound_bank_w(uint8_t data)
+{
+	// to avoid the write when the sound chip is initialized
+	if (data != 0xff)
+		m_audiobank->set_entry(data & 0x07);
+}

snapshots/jotego_jtcores_pr1111/cores/kiwi/doc/x1-007.v

@@ -0,0 +1,39 @@
+// x1-007 model by Furrtek
+
+module x1_007(
+    input PXCLK,
+    input nVBLK,
+    input nHSYNC, nVSYNC,
+    input RGB[14:0],
+    input PIN26,
+    output CSYNC,
+    output reg R[5:0],
+    output reg G[5:0],
+    output reg B[5:0],
+    output reg PIN11
+);
+ 
+reg PIN26_reg;
+reg [14:0] RGB_reg;
+reg nVBLK_A_reg, nVBLK_B_reg;
+ 
+assign CSYNC = ~(nHSYNC | nVSYNC);  // BOTO
+ 
+always @(negedge PXCLK) begin
+    PIN26_reg <= PIN26;             // AGIT
+    nVBLK_A_reg <= nVBLK;           // AFAX
+    nVBLK_B_reg <= nVBLK_A_reg;     // BOLO
+    PIN11 <= nVBLK_A_reg ? PIN26_reg : 1'b0;    // BEDI
+end
+ 
+always @(posedge PXCLK)
+    RGB_reg <= RGB;     // 15x FD1S cells
+ 
+always @(posedge PXCLK or negedge nVBLK_B_reg) begin
+    if (!nVBLK_B_reg)
+        {R, G, B} <= 18'd0; // 18x FD2S cells
+    else
+        {R, G, B} <= {RGB_reg[14:10], |{RGB_reg[14:10]}, RGB_reg[9:5], |{RGB_reg[9:5]} , RGB_reg[4:0], |{RGB_reg[4:0]}};
+end
+ 
+endmodule

snapshots/jotego_jtcores_pr1111/cores/kiwi/hdl/jtkiwi_colmix.v

@@ -0,0 +1,140 @@
+/*  This file is part of JTCORES.
+    JTCORES program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    JTCORES program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with JTCORES.  If not, see <http://www.gnu.org/licenses/>.
+
+    Author: Jose Tejada Gomez. Twitter: @topapate
+    Version: 1.0
+    Date: 18-9-2022 */
+
+module jtkiwi_colmix(
+    input        clk,
+    input        clk_cpu,
+    input        pxl_cen,
+    input        LHBL,
+    input        LVBL,
+
+    input  [8:0] scr_pxl,
+    input  [8:0] obj_pxl,
+
+    input  [9:0] cpu_addr,
+    input  [7:0] cpu_dout,
+    input        cpu_rnw,
+    output [7:0] cpu_din,
+    input        pal_cs,
+
+    input        pal2_cs,
+    input  [7:0] cpu2_dout,
+    input        cpu2_rnw,
+    input  [9:0] cpu2_addr,
+
+    input  [9:0] prog_addr,
+    input  [7:0] prog_data,
+    input        prom_we,
+    input        colprom_en,
+
+    input  [7:0] debug_bus,
+    input  [3:0] gfx_en,
+    output [4:0] red,
+    output [4:0] green,
+    output [4:0] blue
+);
+
+wire [ 7:0] pal_dout;
+wire [ 9:0] pal_addr;
+reg  [ 7:0] pall;
+reg  [ 8:0] coll, col_addr;
+reg  [14:0] rgb;
+wire        pal_we;
+wire        blank;
+reg         half, obj_sel;
+// PROM variation
+wire [15:0] prom_dout;
+wire        promhi_we, promlo_we;
+wire [ 3:0] sort;
+
+assign pal_addr = { coll, half };
+assign pal_we   = (pal_cs & ~cpu_rnw) | (pal2_cs & ~cpu2_rnw);
+assign blank    = ~(LVBL & LHBL);
+assign {red,green,blue} = {15{~blank}} & rgb;
+// PROM
+assign promhi_we = prom_we & ~prog_addr[9];
+assign promlo_we = prom_we &  prog_addr[9];
+
+always @* begin
+    obj_sel = obj_pxl[3:0] != 4'h0;
+    case( {gfx_en[3],gfx_en[0]})
+        2'b00: col_addr = 0;
+        2'b01: col_addr = scr_pxl;
+        2'b10: col_addr = obj_pxl;
+        2'b11: col_addr = obj_sel ? obj_pxl : scr_pxl; // simple priority for now.
+    endcase
+end
+
+always @(posedge clk) begin
+    half <= ~half;
+    if( pxl_cen ) begin
+`ifdef GRAY
+        rgb <= ~{3{ {coll[3:0]}, 1'b0 } };
+`else
+        rgb <= colprom_en ? prom_dout[14:0] : { pal_dout[6:0], pall };
+`endif
+        half <= 1;
+        coll <= col_addr;
+    end
+    pall <= pal_dout;
+end
+
+jtframe_sort u_sort(
+    .debug_bus  ( debug_bus ),
+    .busin      ( col_addr[3:0]    ),
+    .busout     ( sort  )
+);
+
+// Palette RAM X1-007 chip
+jtframe_dual_ram #(.AW(10),.SIMFILE("pal.bin")) u_comm(
+    .clk0   ( clk_cpu      ),
+    .clk1   ( clk          ),
+    // Main/Sub CPU
+    .addr0  ( pal2_cs ? cpu2_addr : cpu_addr ),
+    .data0  ( pal2_cs ? cpu2_dout : cpu_dout ),
+    .we0    ( pal_we       ),
+    .q0     ( cpu_din      ),
+    // Color mixer
+    .addr1  ( pal_addr     ),
+    .data1  (              ),
+    .we1    ( 1'b0         ),
+    .q1     ( pal_dout     )
+);
+
+// PROM for Extermination
+jtframe_prom #( .AW(9), .SIMFILE("../../../../rom/extrmatn/b06-09.15f")) u_promhi(
+    .clk    ( clk       ),
+    .cen    ( 1'b1      ),
+    .data   ( prog_data ),
+    .rd_addr( {col_addr[8:4], sort}  ),
+    .wr_addr( prog_addr[8:0]  ),
+    .we     ( promhi_we ),
+    .q      ( prom_dout[15:8] )
+);
+
+jtframe_prom #( .AW(9), .SIMFILE("../../../../rom/extrmatn/b06-08.17f")) u_promlo(
+    .clk    ( clk       ),
+    .cen    ( 1'b1      ),
+    .data   ( prog_data ),
+    .rd_addr( {col_addr[8:4], sort}  ),
+    .wr_addr( prog_addr[8:0] ),
+    .we     ( promlo_we ),
+    .q      ( prom_dout[7:0] )
+);
+
+endmodule

snapshots/jotego_jtcores_pr1111/cores/kiwi/hdl/jtkiwi_draw.v

@@ -0,0 +1,108 @@
+/*  This file is part of JTCORES.
+    JTCORES program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    JTCORES program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with JTCORES.  If not, see <http://www.gnu.org/licenses/>.
+
+    Author: Jose Tejada Gomez. Twitter: @topapate
+    Version: 1.0
+    Date: 7-11-2022 */
+
+// This is tile map section of the SETA chip
+// This one uses an independent line buffer
+// from that of the sprites
+
+module jtkiwi_draw(
+    input               rst,
+    input               clk,
+
+    input               draw,
+    output reg          busy,
+    input      [13:0]   code,
+    input      [ 8:0]   xpos,
+    input      [ 3:0]   ysub,
+    input               flip,
+
+    input               hflip,
+    input               vflip,
+    input      [ 4:0]   pal,
+
+    output     [20:2]   rom_addr,
+    output reg          rom_cs,
+    input               rom_ok,
+    input      [31:0]   rom_data,
+
+    output reg [ 8:0]   buf_addr,
+    output              buf_we,
+    output     [ 8:0]   buf_din,
+
+    input      [ 7:0]   debug_bus
+);
+
+// Each tile is 16x16 and comes from the same ROM
+// but it looks like the sprites have the two 8x16 halves swapped
+parameter SWAP_HALVES = 1'b0;
+
+reg  [31:0] pxl_data;
+reg         rom_lsb;
+reg  [ 3:0] cnt;
+wire [ 3:0] ysubf, pxl_in;
+
+assign ysubf    = ysub^{4{vflip}};
+assign buf_din  = { pal, pxl_in };
+assign pxl_in   = hflip ?
+    { pxl_data[23], pxl_data[ 7], pxl_data[31], pxl_data[15] } :
+    { pxl_data[16], pxl_data[ 0], pxl_data[24], pxl_data[ 8] };
+
+    // { pxl_data[15], pxl_data[31], pxl_data[ 7], pxl_data[23] } :
+    // { pxl_data[ 8], pxl_data[24], pxl_data[ 0], pxl_data[16] } };
+
+assign rom_addr = { code, ysubf[3], rom_lsb^SWAP_HALVES, ysubf[2:0] };
+assign buf_we   = busy & ~cnt[3];
+
+always @(posedge clk, posedge rst) begin
+    if( rst ) begin
+        rom_cs   <= 0;
+        buf_addr <= 0;
+        pxl_data <= 0;
+        busy     <= 0;
+        cnt      <= 0;
+    end else begin
+        if( !busy ) begin
+            if( draw ) begin
+                rom_lsb  <= hflip; // 14+4 = 18 (+2=20)
+                rom_cs   <= 1;
+                buf_addr <= xpos;
+                busy     <= 1;
+                cnt      <= 8;
+            end
+        end else begin
+            if( rom_ok && rom_cs && cnt[3]) begin
+                pxl_data <= rom_data;
+                cnt[3]   <= 0;
+                if( rom_lsb^hflip ) begin
+                    rom_cs <= 0;
+                end else begin
+                    rom_cs <= 1;
+                end
+            end
+            if( !cnt[3] ) begin
+                cnt      <= cnt+1'd1;
+                buf_addr <= buf_addr+1'd1;
+                pxl_data <= hflip ? pxl_data << 1 : pxl_data >> 1;
+                rom_lsb  <= ~hflip;
+                if( cnt[2:0]==7 && !rom_cs ) busy <= 0;
+            end
+        end
+    end
+end
+
+endmodule

snapshots/jotego_jtcores_pr1111/cores/kiwi/hdl/jtkiwi_game.v

@@ -0,0 +1,246 @@
+/*  This file is part of JTCORES.
+    JTCORES program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    JTCORES program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with JTCORES.  If not, see <http://www.gnu.org/licenses/>.
+
+    Author: Jose Tejada Gomez. Twitter: @topapate
+    Version: 1.0
+    Date: 02-05-2020 */
+
+module jtkiwi_game(
+    `include "jtframe_game_ports.inc" // see $JTFRAME/hdl/inc/jtframe_game_ports.inc
+);
+
+wire        sub_rnw, shr_cs, mshramen, snd_rstn;
+wire [ 7:0] shr_din, shr_dout, main_st, gfx_st, snd_st,
+            vram_dout, pal_dout, cpu_dout;
+wire [ 8:0] hdump;
+wire [ 1:0] eff_coin;
+wire [12:0] shr_addr, cpu_addr;
+
+wire        bram_cs, vram_cs,  pal_cs, pal2_cs, flip;
+wire        cpu_rnw, vctrl_cs, vflag_cs,
+            button_aid, // merges 1P, coin and
+            colprom_we, mcuprom_we, eff_service;
+reg         hb_dly=0, dip_flip_xor=0,
+            coin_xor=0, banked_ram=0,
+            kageki=0, kabuki=0, kabuki_mod = 0, service_xor=0,
+            colprom_en=0, mcu_en=0, aid_en, fast_fm=0;
+
+assign dip_flip   = ~flip ^ dip_flip_xor;
+assign debug_view = st_addr[7:6]==0 ? { hb_dly, dip_flip_xor, coin_xor, banked_ram,
+                                        kageki, kabuki, colprom_en, mcu_en } :
+                    st_addr[7:6]==1 ? main_st :
+                    st_addr[7:6]==2 ? gfx_st  : snd_st;
+assign colprom_we = prom_we && prog_addr[15:10]==0;
+assign mcuprom_we = prom_we && prog_addr >= `MCU_START;
+assign st_dout    = debug_view;
+// Banked RAM
+assign bram_we    = bram_cs & ~cpu_rnw;
+// assign bram_dsn   = { 1'd1, bram_cs & cpu_rnw };
+assign bram_din   = cpu_dout;
+// button_aid will make up/down inputs to work as coins too. This helps
+// button mapping for spinners in MiSTer
+assign eff_coin   = {2{coin_xor}}^( coin[1:0] & ({2{~button_aid}}| {&joystick2[3:2],&joystick1[3:2]}));
+assign eff_service= service_xor ^ service;
+assign button_aid = `ifdef MISTER status[13]&aid_en `else 0 `endif ;
+
+always @(posedge clk) begin
+    if( prog_we && header ) begin
+        if( prog_addr==0 )
+            { hb_dly, dip_flip_xor, coin_xor, banked_ram,
+              kageki, kabuki, colprom_en, mcu_en } <= prog_data;
+        else if( prog_addr==1 )
+            { kabuki_mod, fast_fm, aid_en, service_xor } <= prog_data[3:0];
+    end
+end
+
+/* verilator tracing_on */
+jtkiwi_main u_main(
+    .rst            ( rst           ),
+    .clk            ( clk           ),
+    .cen6           ( cen6          ),
+
+    .LVBL           ( LVBL          ),
+    .hcnt           ( hdump         ),
+    .colprom_en     ( colprom_en    ),
+    // Banked RAM
+    .banked_ram     ( banked_ram    ),
+    .bram_cs        ( bram_cs       ),
+    .bram_ok        ( 1'b1 ), //bram_ok       ),
+    .bram_data      ( bram_dout     ),
+    .bram_addr      ( bram_addr     ),
+    // Main CPU ROM
+    .rom_addr       ( main_addr     ),
+    .rom_cs         ( main_cs       ),
+    .rom_data       ( main_data     ),
+
+    // Sub CPU access to shared RAM
+    .shr_addr       ( shr_addr      ),
+    .shr_dout       ( shr_dout      ),
+    .sub_rnw        ( sub_rnw       ),
+    .shr_din        ( shr_din       ),
+    .shr_cs         ( shr_cs        ),
+    .mshramen       ( mshramen      ),
+    // Sound
+    .snd_rstn       ( snd_rstn      ),
+
+    // Video
+    .cpu_addr       ( cpu_addr      ),
+    .cpu_dout       ( cpu_dout      ),
+    .cpu_rnw        ( cpu_rnw       ),
+
+    .vctrl_cs       ( vctrl_cs      ),
+    .vram_cs        ( vram_cs       ),
+    .vflag_cs       ( vflag_cs      ),
+    .vram_dout      ( vram_dout     ),
+
+    .pal_cs         ( pal_cs        ),
+    .pal_dout       ( pal_dout      ),
+    .dip_pause      ( dip_pause     ),
+    .debug_bus      ( debug_bus     ),
+    .st_dout        ( main_st       )
+);
+
+/* verilator tracing_on */
+jtkiwi_video u_video(
+    .rst            ( rst           ),
+    .clk            ( clk           ),
+    .clk_cpu        ( clk           ),
+
+    .pxl2_cen       ( pxl2_cen      ),
+    .pxl_cen        ( pxl_cen       ),
+    .hb_dly         ( hb_dly        ),
+    .LHBL           ( LHBL          ),
+    .LVBL           ( LVBL          ),
+    .HS             ( HS            ),
+    .VS             ( VS            ),
+    .flip           ( flip          ),
+    .hdump          ( hdump         ),
+    // PROMs
+    .prom_we        ( colprom_we    ),
+    .prog_addr      ( prog_addr[9:0]),
+    .prog_data      ( prog_data     ),
+    .colprom_en     ( colprom_en    ),
+    // GFX - CPU interface
+    .cpu_rnw        ( cpu_rnw       ),
+    .cpu_addr       ( cpu_addr      ),
+    .cpu_dout       ( cpu_dout      ),
+
+    .vram_cs        ( vram_cs       ),
+    .vctrl_cs       ( vctrl_cs      ),
+    .vflag_cs       ( vflag_cs      ),
+    .vram_dout      ( vram_dout     ),
+
+    .pal_cs         ( pal_cs        ),
+    .pal_dout       ( pal_dout      ),
+
+    .pal2_cs        ( pal2_cs       ),
+    .cpu2_dout      ( shr_din       ),
+    .cpu2_rnw       ( sub_rnw       ),
+    .cpu2_addr      ( shr_addr[9:0] ),
+
+    // SDRAM
+    .scr_addr       ( scr_addr      ),
+    .scr_data       ( scr_data      ),
+    .scr_ok         ( scr_ok        ),
+    .scr_cs         ( scr_cs        ),
+
+    .obj_addr       ( obj_addr      ),
+    .obj_data       ( obj_data      ),
+    .obj_ok         ( obj_ok        ),
+    .obj_cs         ( obj_cs        ),
+    // pixels
+    .red            ( red           ),
+    .green          ( green         ),
+    .blue           ( blue          ),
+    // Test
+    .gfx_en         ( gfx_en        ),
+    .debug_bus      ( debug_bus     ),
+    .st_dout        ( gfx_st        )
+);
+
+/* verilator tracing_off */
+jtkiwi_snd u_sound(
+    .rst        ( rst           ),
+    .clk        ( clk           ),
+    .snd_rstn   ( snd_rstn      ),
+    .fast_fm    ( fast_fm       ),
+    .cen6       ( cen6          ),
+    .cen3       ( cen3          ),
+    .cen1p5     ( cen1p5        ),
+    .LVBL       ( LVBL          ),
+    // Game variations
+`ifdef NOKABUKIZ
+    .kabuki     ( 1'b0          ),
+    .kabuki_mod ( 1'b0          ),
+`else
+    .kabuki     ( kabuki        ),
+    .kabuki_mod ( kabuki_mod    ), // different memory map for TNZS
+`endif
+    .kageki     ( kageki        ),
+
+    // PCM
+    .pcm_addr   ( pcm_addr      ),
+    .pcm_data   ( pcm_data      ),
+    .pcm_ok     ( pcm_ok        ),
+    .pcm_cs     ( pcm_cs        ),
+
+    // cabinet I/O
+    .cab_1p     ( cab_1p[1:0]   ),
+    .coin       ( eff_coin      ),
+    .joystick1  ( joystick1     ),
+    .joystick2  ( joystick2     ),
+    .service    ( eff_service   ),
+    .tilt       ( tilt          ),
+    .dial_x     ( dial_x        ),
+    .dial_y     ( dial_y        ),
+    // DIP switches
+    .dipsw      ( dipsw[15:0]   ),
+    .dip_pause  ( dip_pause     ),
+
+    // Shared RAM
+    .ram_addr   ( shr_addr      ),
+    .ram_din    ( shr_din       ),
+    .ram_dout   ( shr_dout      ),
+    .cpu_rnw    ( sub_rnw       ),
+    .ram_cs     ( shr_cs        ),
+    .mshramen   ( mshramen      ),
+    .pal_cs     ( pal2_cs       ),
+    .pal_dout   ( pal_dout      ),
+    // MCU
+    .mcu_en     ( mcu_en        ),
+    .prog_addr  ( prog_addr[10:0]),
+    .prog_data  ( prog_data     ),
+    .prom_we    ( mcuprom_we    ),
+
+    // ROM
+    .rom_addr   ( sub_addr      ),
+    .rom_cs     ( sub_cs        ),
+    .rom_data   ( sub_data      ),
+
+    .audiocpu_addr ( audiocpu_addr ),
+    .audiocpu_cs   ( audiocpu_cs   ),
+    .audiocpu_data ( audiocpu_data ),
+    .audiocpu_ok   ( audiocpu_ok   ),
+
+    // Sound output
+    .fm         ( fm            ),
+    .psg        ( psg           ),
+    .pcm        ( pcm           ),
+    // Debug
+    .debug_bus  ( debug_bus     ),
+    .st_addr    ( st_addr       ),
+    .st_dout    ( snd_st        )
+);
+
+endmodule

snapshots/jotego_jtcores_pr1111/cores/kiwi/hdl/jtkiwi_gfx.v

@@ -0,0 +1,308 @@
+/*  This file is part of JTCORES.
+    JTCORES program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    JTCORES program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a dma_bsy of the GNU General Public License
+    along with JTCORES.  If not, see <http://www.gnu.org/licenses/>.
+
+    Author: Jose Tejada Gomez. Twitter: @topapate
+    Version: 1.0
+    Date: 18-09-2022 */
+
+// There is bus contention to access the memories
+// in this module, based. When H4 is high, the
+// GPU is in control. When H4 is low, it's the CPU
+
+module jtkiwi_gfx(
+    input               rst,
+    input               clk,
+    input               clk_cpu,
+
+    input               pxl2_cen,
+    input               pxl_cen,
+
+    input               LHBL,
+    input               LVBL,
+    input               hs,
+    input               vs,
+    output              flip,
+
+    input      [ 8:0]   vdump,
+    input      [ 8:0]   vrender,
+    input      [ 8:0]   hdump,
+
+    input               cpu_rnw,
+    input      [12:0]   cpu_addr,
+    input      [ 7:0]   cpu_dout,
+    input               vram_cs,
+    input               vctrl_cs,
+    input               vflag_cs,
+    output     [ 7:0]   cpu_din,
+
+    // SDRAM interface
+    output     [20:2]   scr_addr,
+    input      [31:0]   scr_data,
+    input               scr_ok,
+    output              scr_cs,
+
+    output     [20:2]   obj_addr,
+    input      [31:0]   obj_data,
+    input               obj_ok,
+    output              obj_cs,
+
+    output      [ 8:0]  scr_pxl,
+    output      [ 8:0]  obj_pxl,
+    input       [ 7:0]  debug_bus,
+    output      [ 7:0]  st_dout
+);
+
+wire        yram_we, video_en;
+wire [ 1:0] vram_we;
+wire [11:0] tm_addr, lut_addr;
+reg  [11:0] code_addr;
+reg  [ 9:0] col_addr;
+wire [ 7:0] yram_dout, col_data;
+wire [ 7:0] scol_addr;
+reg  [ 7:0] attr, xpos, ypos;
+reg  [ 7:0] cfg[0:3], flag;
+reg         scan_cen, done, dr_start, dr_busy,
+            match, xflip, yflip,
+            yram_cs, cfg_cs;
+reg  [ 2:0] st;
+reg  [13:0] code;
+reg  [ 1:0] cen_cnt;
+wire        tm_page, obj_bufb;
+wire [15:0] vram_dout, code_dout, col_xmsb;
+wire [ 3:0] col_cfg;
+wire [ 1:0] col0;
+reg         tm_cen, lut_cen;
+// Objects
+wire [ 8:0] y_addr;
+
+`ifdef SIMULATION
+wire [7:0] cfg0 = cfg[0], cfg1 = cfg[1], cfg2 = cfg[2], cfg3 = cfg[3];
+`endif
+
+assign vram_we  = {2{vram_cs  & ~cpu_rnw}} & { cpu_addr[12], ~cpu_addr[12] };
+assign yram_we  = yram_cs & ~cpu_rnw;
+assign flip     = ~cfg[0][6]; // only flip y?
+assign video_en = cfg[0][4]; // uncertain
+assign col0     = cfg[0][1:0]; // start column in the tilemap VRAM
+assign tm_page  = cfg[1][6];
+assign obj_bufb = cfg[1][5];
+assign col_cfg  = cfg[1][3:0];
+assign col_xmsb = { cfg[3], cfg[2] };
+assign cpu_din  = yram_cs ? yram_dout :
+                  vram_cs ? (cpu_addr[12] ? vram_dout[15:8] : vram_dout[7:0]) : 8'h00;
+assign st_dout  = { flip, video_en, col0, col_cfg };
+
+always @* begin
+    yram_cs = 0;
+    cfg_cs  = 0;
+    if( vctrl_cs ) case( cpu_addr[9:8] )
+        0,1,2: yram_cs = 1;
+        3: cfg_cs  = 1;
+        default:;
+    endcase
+end
+
+always @(posedge clk, posedge rst) begin
+    if( rst ) begin
+        cen_cnt <= 0;
+        tm_cen  <= 0;
+        lut_cen <= 0;
+    end else begin
+        cen_cnt <= cen_cnt + 1'd1;
+        tm_cen  <= cen_cnt==0;
+        lut_cen <= cen_cnt==2;
+    end
+end
+
+`ifdef NOMAIN
+initial $readmemh("seta_cfg.hex",cfg);
+`endif
+
+always @(posedge clk, posedge rst) begin
+`ifndef NOMAIN
+    if( rst ) begin
+        cfg[0]  <= 0;
+        cfg[1]  <= 9;
+        cfg[2]  <= 0;
+        cfg[3]  <= 0;
+    end else
+`endif
+    begin
+        if( cfg_cs  ) cfg[ cpu_addr[1:0] ] <= cpu_dout;
+        if( vflag_cs ) flag <= cpu_dout;
+    end
+end
+
+always @* begin
+    case( cen_cnt )
+        0,1: begin
+            col_addr  = { 2'b10, scol_addr };
+            code_addr = tm_addr;
+        end
+        2,3: begin // objects
+            col_addr  = { 1'b0, y_addr };
+            code_addr = lut_addr;
+        end
+    endcase
+end
+
+jtkiwi_tilemap u_tilemap(
+    .rst        ( rst       ),
+    .clk        ( clk       ),
+    .pxl_cen    ( pxl_cen   ),
+    .tm_cen     ( tm_cen    ),
+
+    .hs         ( hs        ),
+    .flip       ( flip      ),
+    .page       ( tm_page   ),
+
+    .col_xmsb   ( col_xmsb  ),
+    .col_cfg    ( col_cfg   ),
+    .col0       ( col0      ),
+
+    .tm_addr    ( tm_addr   ),
+    .tm_data    ( code_dout ),
+
+    // Column scroll
+    .col_addr   ( scol_addr ),
+    .col_data   ( col_data  ),
+
+    .rom_addr   ( scr_addr  ),
+    .rom_cs     ( scr_cs    ),
+    .rom_ok     ( scr_ok    ),
+    .rom_data   ( scr_data  ),
+
+    .vrender    ( vdump     ),
+    .hdump      ( hdump     ),
+    .pxl        ( scr_pxl   ),
+    .debug_bus  ( debug_bus )
+);
+
+jtkiwi_obj u_obj(
+    .rst        ( rst       ),
+    .clk        ( clk       ),
+    .lut_cen    ( lut_cen   ),
+    .pxl_cen    ( pxl_cen   ),
+
+    .hs         ( hs        ),
+    .flip       ( flip      ),
+    .page       ( tm_page ^ ~obj_bufb),
+
+    .lut_addr   ( lut_addr  ),
+    .lut_data   ( code_dout ),
+
+    // Column scroll
+    .y_addr     ( y_addr    ),
+    .y_data     ( col_data  ),
+
+    .rom_addr   ( obj_addr  ),
+    .rom_cs     ( obj_cs    ),
+    .rom_ok     ( obj_ok    ),
+    .rom_data   ( obj_data  ),
+
+    .vdump      ( vdump     ),
+    .hdump      ( hdump     ),
+    .pxl        ( obj_pxl   ),
+    .debug_bus  ( debug_bus )
+);
+
+// This is an external memory chip. The original
+// one is an 8-bit memory. Changed to 16-bit access
+// to ease the drawing logic
+// the upper byte refers to the upper half of the
+// memory for the CPU
+// In MAME the lower half is called spritecodelow
+// and the upper spritecodehigh
+
+reg  [9:0] dma_addr;
+reg        LVBLl;
+reg        dma_st;
+reg        dma_obj = 0;
+reg        dma_tm = 0;
+reg        dma_start = 0;
+wire       dma_bsy = dma_obj | dma_tm;
+
+// DMA when cfg[1][5] == 0
+// Sprite DMA starts with VBLANK
+// Tilemap DMA starts with writing to cfg[1]
+always @(posedge clk) begin
+    if (cfg_cs && cpu_addr[1:0] == 1 && !cpu_rnw && !cpu_dout[5]) dma_start <= 1;
+    LVBLl <= LVBL;
+
+    if (~obj_bufb && LVBLl && !LVBL) begin
+        // Start sprite dma_bsy
+        dma_addr <= 0;
+        dma_obj <= 1;
+        dma_st <= 0;
+    end else if (dma_start && !dma_bsy) begin
+        // Start tilemap dma_bsy
+        dma_start <= 0;
+        dma_addr <= 0;
+        dma_tm <= 1;
+        dma_st <= 0;
+    end else if (dma_bsy && pxl_cen ) begin // executed at 6MHz. Needs confirmation from PCB measurements
+        dma_st <= ~dma_st;
+        if (!dma_st) begin
+            // read phase
+            ;
+        end else begin
+            // write phase
+            dma_addr <= dma_addr + 1'd1;
+            if (&dma_addr) begin
+                dma_addr <= 0;
+                dma_obj <= 0;
+                dma_tm <= 0;
+            end
+        end
+    end
+end
+
+jtframe_dual_ram16 #(.AW(12),
+    .SIMFILE_LO("vram_lo.bin"),
+    .SIMFILE_HI("vram_hi.bin")
+) u_vram(
+    .clk0   ( clk_cpu    ),
+    .clk1   ( clk        ),
+    // Main CPU
+    // probably the CPU should be WAIT-ed during DMA access, but it's
+    // very fast, thus there's no overlap with CPU VRAM access
+    .addr0  ( dma_bsy ? {dma_tm ^ tm_page ^ dma_st, dma_tm, dma_addr} : cpu_addr[11:0] ),
+    .data0  ( dma_bsy ? vram_dout : {2{cpu_dout}}  ),
+    .we0    ( dma_bsy ? {2{dma_st}} : vram_we ),
+    .q0     ( vram_dout  ),
+    // GFX
+    .addr1  ( code_addr  ),
+    .data1  ( 16'd0      ),
+    .we1    ( 2'd0       ),
+    .q1     ( code_dout  )
+);
+
+// This memory is internal to the SETA-X1-001 chip
+// this is called spriteylow by MAME
+jtframe_dual_ram #(.AW(10),.SIMFILE("col.bin")) u_yram(
+    .clk0   ( clk_cpu    ),
+    .clk1   ( clk        ),
+    // Main CPU
+    .addr0  (cpu_addr[9:0]),
+    .data0  ( cpu_dout   ),
+    .we0    ( yram_we    ),
+    .q0     ( yram_dout  ),
+    // GFX
+    .addr1  ( col_addr   ),
+    .data1  ( 8'd0       ),
+    .we1    ( 1'd0       ),
+    .q1     ( col_data   )
+);
+
+endmodule

snapshots/jotego_jtcores_pr1111/cores/kiwi/hdl/jtkiwi_main.v

@@ -0,0 +1,254 @@
+/*  This file is part of JTCORES.
+    JTCORES program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    JTCORES program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with JTCORES.  If not, see <http://www.gnu.org/licenses/>.
+
+    Author: Jose Tejada Gomez. Twitter: @topapate
+    Version: 1.0
+    Date: 17-9-2022 */
+
+module jtkiwi_main(
+    input               rst,
+    input               clk,
+    input               cen6,
+    input               LVBL,
+    input               colprom_en,
+
+    // Video devices
+    output reg          vram_cs,
+    output reg          vctrl_cs,
+    output reg          vflag_cs,
+    output reg          pal_cs,
+    input      [ 7:0]   pal_dout,
+    input      [ 7:0]   vram_dout,
+    input      [ 8:0]   hcnt,
+
+    output     [12:0]   cpu_addr,
+    output     [ 7:0]   cpu_dout,
+    output              cpu_rnw,
+
+    // Sub CPU (sound)
+    output reg          snd_rstn,
+    //      access to RAM
+    input      [12:0]   shr_addr,
+    input      [ 7:0]   shr_din,
+    input               sub_rnw,
+    input               shr_cs,
+    output reg          mshramen,
+    output     [ 7:0]   shr_dout,
+
+    input               dip_pause,
+
+    // Banked RAM (TNZS)
+    input               banked_ram,
+    input      [ 7:0]   bram_data,
+    output reg [14:0]   bram_addr,
+    output reg          bram_cs,
+    input               bram_ok,
+    // ROM interface
+    output     [16:0]   rom_addr,
+    output reg          rom_cs,
+    input      [ 7:0]   rom_data,
+    // Debug
+    input      [ 7:0]   debug_bus,
+    output     [ 7:0]   st_dout
+);
+`ifndef NOMAIN
+wire        irq_ack, mreq_n, m1_n, iorq_n, rd_n, wr_n,
+            rfsh_n, int_n, ram_we, cpu_cen;
+reg  [ 7:0] din;
+wire [ 7:0] dout, ram_dout;
+reg  [ 2:0] bank;
+wire [15:0] A;
+reg         ram_cs, bank_cs,
+            sshramen, dev_busy, obj_vram_en;
+wire        mem_acc;
+
+assign cpu_rnw  = wr_n | ~cpu_cen;
+assign cpu_addr = A[12:0];
+assign cpu_dout = dout;
+assign irq_ack  = /*!m1_n &&*/ !iorq_n; // The original PCB just uses iorq_n,
+    // the orthodox way to do it is to use m1_n too
+assign ram_we   = mshramen & ~wr_n;
+assign rom_addr = { A[15] ? bank : {2'd0, A[14]}, A[13:0] };
+assign st_dout  = { 3'd0, ~snd_rstn, 1'd0, bank };
+assign mem_acc  = ~mreq_n & rfsh_n;
+
+`ifdef SIMULATION
+wire rombank_cs = rom_cs && A[15:12]>=8;
+`endif
+
+always @(posedge clk, posedge rst) begin
+    if ( rst ) begin
+        bram_cs   <= 0;
+        rom_cs    <= 0;
+        vram_cs   <= 0;
+        ram_cs    <= 0;
+        vctrl_cs  <= 0;
+        vflag_cs  <= 0;
+        bank_cs   <= 0;
+        pal_cs    <= 0;
+        bram_addr <= 0;
+    end else begin
+        bram_cs  <= 0;
+        rom_cs   <= mem_acc && A[15:12]  < 4'hc;
+        vram_cs  <= mem_acc && A[15:13] == 3'b110; // C,D
+        ram_cs   <= mem_acc && A[15:12] == 4'he; // A[12:0] used in Insector X (?)
+        vctrl_cs <= mem_acc && A[15:10] == 6'b1111_00; // internal RAM and config registers
+        vflag_cs <= mem_acc && A[15: 9] == 7'b1111_010 && !wr_n; // config registers
+        bank_cs  <= mem_acc && A[15: 9] == 7'b1111_011 && !wr_n; // f6xx/f7xx
+        pal_cs   <= mem_acc && A[15:11] == 5'h1f && !colprom_en;
+        if( mem_acc && banked_ram && bank<2 && A[15:12]>=8 && A[15:12]<4'hc ) begin
+            rom_cs  <= 0;
+            bram_cs <= 1;
+            bram_addr <= { bank[0], A[13:0] };
+        end
+    end
+end
+
+always @* begin
+    obj_vram_en = mem_acc && (
+       (A[15:11]==5'b11110 && !A[9]) ||
+       A[15:10]==6'b111100 ||
+       A[15:13]==3'b110 );
+    dev_busy = (sshramen & ram_cs) || (obj_vram_en && hcnt[1:0]!=0) || (bram_cs&&!bram_ok);
+end
+
+always @(posedge clk) begin
+    din <= rom_cs  ? rom_data  :
+        ram_cs  ? ram_dout  :
+        bram_cs ? bram_data :
+        (vram_cs | vctrl_cs) ? vram_dout :
+        pal_cs  ? pal_dout  : 8'h00;
+end
+
+always @(posedge clk, posedge rst) begin
+    if( rst ) begin
+        bank     <= 0;
+        snd_rstn <= 0;
+    end else begin
+        if( bank_cs ) begin
+            bank <= dout[2:0];
+            snd_rstn <= dout[4];
+`ifdef SIMULATION
+            if( !snd_rstn && dout[4] ) $display("Sound CPU reset released");
+            if( snd_rstn && !dout[4] ) $display("Sound CPU reset");
+`endif
+        end
+    end
+end
+
+`ifdef SIMULATION
+    integer line_cnt=1;
+
+    always @(negedge ram_cs, posedge rst) begin
+        if( rst )
+            line_cnt <= 1;
+        else
+            line_cnt <= line_cnt+1;
+    end
+`endif
+
+jtframe_ff u_irq(
+    .clk    ( clk       ),
+    .rst    ( rst       ),
+    .cen    ( 1'b1      ),
+    .din    ( 1'b1      ),
+    .q      (           ),
+    .qn     ( int_n     ),
+    .set    ( 1'b0      ),
+    .clr    ( irq_ack   ),
+    .sigedge( ~LVBL & dip_pause  )
+);
+
+// To do: add dev_busy to match the wait signal
+// when accessing the VRAM
+jtframe_z80_devwait #(.RECOVERY(0)) u_gamecpu(
+    .rst_n    ( ~rst   ),
+    .clk      ( clk    ),
+    .cen      ( cen6   ),
+    .cpu_cen  ( cpu_cen),
+`ifdef NOINT
+    .int_n    ( 1'b1   ),
+`else
+    .int_n    ( int_n  ),
+`endif
+    .nmi_n    ( 1'b1   ),
+    .busrq_n  ( 1'b1   ),
+    .m1_n     ( m1_n   ),
+    .mreq_n   ( mreq_n ),
+    .iorq_n   ( iorq_n ),
+    .rd_n     ( rd_n   ),
+    .wr_n     ( wr_n   ),
+    .rfsh_n   ( rfsh_n ),
+    .halt_n   (        ),
+    .busak_n  (        ),
+    .A        ( A      ),
+    .din      ( din    ),
+    .dout     ( dout   ),
+    .rom_cs   ( rom_cs ),
+    .rom_ok   ( 1'b1   ),
+    .dev_busy ( dev_busy )
+);
+
+// first come, first served
+always @(posedge clk, posedge rst) begin
+    if( rst ) begin
+        mshramen <= 0;
+        sshramen <= 0;
+    end else begin
+        // Main CPU drives the RAM
+        if( ram_cs && !sshramen )
+            mshramen <= 1;
+        if( !ram_cs ) mshramen <= 0;
+        // Sub CPU drives the RAM
+        if( shr_cs && !mshramen && !ram_cs )
+            sshramen <= 1;
+        if( !shr_cs ) sshramen <= 0;
+    end
+end
+
+jtframe_dual_ram #(.AW(13),.DUMPFILE("mainmem")) u_comm(
+    .clk0   ( clk        ),
+    .clk1   ( clk        ),
+    // Main CPU
+    .addr0  ( A[12:0]    ),
+    .data0  ( dout       ),
+    .we0    ( ram_we     ),
+    .q0     ( ram_dout   ),
+    // MCU
+    .addr1  ( shr_addr   ),
+    .data1  ( shr_din    ),
+    .we1    ( sshramen & ~sub_rnw ),
+    .q1     ( shr_dout   )
+`ifdef JTFRAME_DUAL_RAM_DUMP
+    ,.dump   ( LVBL       )
+`endif
+);
+`else // NOMAIN
+    initial begin
+        rom_cs   = 0;
+        rom_addr = 0;
+        vram_cs  = 0;
+        vflag_cs = 0;
+        vctrl_cs = 0;
+        pal_cs   = 0;
+        snd_rstn = 0;
+        mshramen = 0;
+    end
+    assign cpu_rnw  = 1;
+    assign cpu_addr = 1;
+    assign cpu_dout = 0;
+    assign shr_dout = 0;
+    assign st_dout  = 0;
+`endif
+endmodule

snapshots/jotego_jtcores_pr1111/cores/kiwi/hdl/jtkiwi_obj.v

@@ -0,0 +1,172 @@
+/*  This file is part of JTCORES.
+    JTCORES program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    JTCORES program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with JTCORES.  If not, see <http://www.gnu.org/licenses/>.
+
+    Author: Jose Tejada Gomez. Twitter: @topapate
+    Version: 1.0
+    Date: 7-11-2022 */
+
+// This is object processor section of the SETA chip
+
+module jtkiwi_obj(
+    input               rst,
+    input               clk,
+    input               lut_cen,
+    input               pxl_cen,
+
+    input               hs,
+    input               flip,
+    input               page,
+
+    output     [11:0]   lut_addr,
+    input      [15:0]   lut_data,
+
+    output     [ 8:0]   y_addr,
+    input      [ 7:0]   y_data,
+
+    output     [20:2]   rom_addr,
+    output              rom_cs,
+    input               rom_ok,
+    input      [31:0]   rom_data,
+
+    input      [ 8:0]   vdump,
+    input      [ 8:0]   hdump,
+    output     [ 8:0]   pxl,
+
+    input      [ 7:0]   debug_bus
+);
+
+reg         done;
+reg  [ 8:0] objcnt;
+reg  [ 4:0] pal, dr_pal;
+reg  [ 3:0] dr_ysub, ysub;
+reg  [ 8:0] ydiff, dr_xpos;
+reg  [ 8:0] xpos;
+wire [ 8:0] vf;
+reg  [ 1:0] st;
+reg         dr_draw, dr_hflip, dr_vflip,
+            match, vflip, hflip;
+reg  [15:0] code;
+reg  [13:0] dr_code;
+wire        dr_busy;
+wire [ 8:0] buf_din, buf_addr;
+wire        buf_we;
+
+assign lut_addr = { page, 1'b0, ~st[1], objcnt }; // 1 + 1 + 1 + 9 = 12
+assign y_addr   = objcnt;
+assign vf       = {9{flip}} ^ (vdump-9'd1);
+
+always @* begin
+    ydiff = { 1'b0, vf[7:0] } - {1'b0, y_data };
+    match = ydiff[8:4]==0;
+end
+
+// Columns are 32-pixel wide
+always @(posedge clk, posedge rst) begin
+    if( rst ) begin
+        st      <= 0;
+        objcnt  <= 0;
+        dr_draw <= 0;
+        dr_code <= 0;
+        dr_pal  <= 0;
+        dr_hflip<= 0;
+        dr_vflip<= 0;
+        dr_xpos <= 0;
+        dr_ysub <= 0;
+    end else begin
+        dr_draw <= 0;
+        if( hs || vdump>9'hf8 ) begin
+            objcnt  <= 9'h1ff;
+            done    <= 0;
+            st      <= 0;
+            dr_draw <= 0;
+        end else if( !done && lut_cen ) begin
+            st <= st + 1'd1;
+            case( st )
+                0: begin
+                    ysub <= ydiff[3:0];
+                    if( !match ) begin
+                        objcnt <= objcnt - 1'd1;
+                        st     <= 0;
+                        done   <= objcnt==0;
+                    end
+                end
+                1: { pal, code[15:14], xpos } <= lut_data;
+                2: { hflip, vflip, code[13:0] } <= lut_data;
+                3: begin
+                    if( !dr_busy )  begin
+                        dr_draw  <= 1;
+                        dr_code  <= code[13:0];
+                        dr_hflip <= hflip^flip;
+                        dr_vflip <= vflip;
+                        dr_pal   <= pal;
+                        dr_xpos  <= xpos;
+                        dr_ysub  <= ~ysub;
+                        objcnt   <= objcnt - 1'd1;
+                        done     <= objcnt==0;
+                    end else begin
+                        st <= st;
+                    end
+                end
+            endcase
+        end
+    end
+end
+
+jtkiwi_draw #(.SWAP_HALVES(1'b1)) u_draw (
+    .rst        ( rst           ),
+    .clk        ( clk           ),
+
+    .draw       ( dr_draw       ),
+    .busy       ( dr_busy       ),
+    .code       ( dr_code       ),
+    .pal        ( dr_pal        ),
+    .hflip      ( dr_hflip      ),
+    .vflip      ( dr_vflip      ),
+    .xpos       ( dr_xpos       ),
+    .ysub       ( dr_ysub       ),
+    .flip       ( flip          ),
+
+    .rom_addr   ( rom_addr      ),
+    .rom_cs     ( rom_cs        ),
+    .rom_ok     ( rom_ok        ),
+    .rom_data   ( rom_data      ),
+
+    .buf_addr   ( buf_addr      ),
+    .buf_we     ( buf_we        ),
+    .buf_din    ( buf_din       ),
+    .debug_bus  ( 8'd0          )
+    //.debug_bus  ( debug_bus     )
+);
+
+// During HS the contents of the memory are cleared
+
+jtframe_obj_buffer #(
+    .DW   ( 9 ),
+    .ALPHA( 0 ),
+    .FLIP_OFFSET(9'h100)
+) u_linebuf(
+    .clk    ( clk       ),
+    .flip   ( 1'b0      ),
+    .LHBL   ( ~hs       ),
+    // New line writting
+    .we     ( buf_we    ),
+    .wr_data( buf_din   ),
+    .wr_addr( buf_addr  ),
+    // Previous line reading
+    .rd     ( pxl_cen   ),
+    .rd_addr( hdump     ),
+    .rd_data( pxl       )
+);
+
+endmodule

snapshots/jotego_jtcores_pr1111/cores/kiwi/hdl/jtkiwi_snd.v

@@ -0,0 +1,543 @@
+/*  This file is part of JTCORES.
+    JTCORES program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    JTCORES program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with JTCORES.  If not, see <http://www.gnu.org/licenses/>.
+
+    Author: Jose Tejada Gomez. Twitter: @topapate
+    Version: 1.0
+    Date: 18-9-2022 */
+
+module jtkiwi_snd(
+    input               rst,
+    input               clk,
+    input               cen6,
+    input               cen3,
+    input               cen1p5,
+
+    input               LVBL,
+    input               fast_fm,
+
+    // MCU
+    input               mcu_en,
+    input               kabuki,
+    input               kabuki_mod,
+    input               kageki,
+    input      [10:0]   prog_addr,  // 2kB
+    input      [ 7:0]   prog_data,
+    input               prom_we,
+
+    // Cabinet inputs
+    input      [ 1:0]   cab_1p,
+    input      [ 1:0]   coin,
+    input      [ 6:0]   joystick1,
+    input      [ 6:0]   joystick2,
+    input      [ 1:0]   dial_x,
+    input      [ 1:0]   dial_y,
+
+    // ROM interface
+    output reg [15:0]   rom_addr,
+    output reg          rom_cs,
+    input      [ 7:0]   rom_data,
+
+    // Audio CPU (Z80)
+    output     [16:0]   audiocpu_addr,
+    output              audiocpu_cs,
+    input      [ 7:0]   audiocpu_data,
+    input               audiocpu_ok,
+
+    // Sub CPU (sound)
+    input               snd_rstn,
+
+    // PCM (Kageki)
+    output reg [15:0]   pcm_addr,
+    input      [ 7:0]   pcm_data,
+    input               pcm_ok,
+    output              pcm_cs,
+    //      access to RAM
+    output     [12:0]   ram_addr,
+    output     [ 7:0]   ram_din,
+    output              cpu_rnw,
+    output reg          ram_cs,
+    input      [ 7:0]   ram_dout,
+    input               mshramen,
+    output reg          pal_cs,
+    input      [ 7:0]   pal_dout,
+
+    // DIP switches
+    input               dip_pause,
+    input               service,
+    input               tilt,
+    input      [15:0]   dipsw,
+
+    // Sound output
+    output signed [15:0] fm,
+    output        [ 9:0] psg,
+    output        [ 7:0] pcm,
+    // Debug
+    input      [ 7:0]    debug_bus,
+    input      [ 7:0]    st_addr,
+    output reg [ 7:0]    st_dout
+);
+`ifndef NOSOUND
+
+wire        irq_ack, mreq_n, m1_n, iorq_n, rd_n, wr_n, sample,
+            fmint_n, int_n, cpu_cen, rfsh_n;
+reg  [ 7:0] din, cab_dout, psg_gain, p1_din, porta_din;
+wire [ 7:0] fm_dout, dout, p2_din, p2_dout, mcu_dout, mcu_st, porta_dout, portb_dout,
+            dial_dout, p1_dout;
+reg  [ 1:0] bank, dial_rst;
+wire [15:0] A;
+reg         bank_cs, fm_cs, cab_cs, mcu_cs, dial_cs, kabuki_dipsnd,
+            dev_busy, fm_busy, fmcs_l,
+            mcu_rstn, comb_rstn=0;
+wire        mem_acc, mcu_comb_rst;
+wire  [1:0] mcu_we, mcu_rd;
+
+`ifdef SIMULATION
+wire shared_rd = ram_cs && !A[0] && !rd_n;
+wire shared_wr = ram_cs && !A[0] && !wr_n;
+`endif
+
+assign mem_acc  = ~mreq_n & rfsh_n;
+assign ram_din  = dout;
+assign ram_addr = A[12:0];
+assign cpu_rnw  = wr_n | ~cpu_cen;
+assign mcu_comb_rst = ~(mcu_rstn & comb_rstn);
+// assign mcu_comb_rst = ~comb_rstn;
+assign p2_din   = { 6'h3f, tilt, service };
+assign pcm_cs   = kageki;
+assign mcu_we   = {2{mcu_cs & ~wr_n}} & { A[0], ~A[0] };
+assign mcu_rd   = {2{mcu_cs & ~rd_n}} & { A[0], ~A[0] };
+assign pcm      = kabuki ? portb_dout : pcm_re;
+
+assign irq_ack = /*!m1_n &&*/ !iorq_n; // The original PCB just uses iorq_n,
+    // the orthodox way to do it is to use m1_n too
+
+always @* begin
+    rom_addr = A;
+    if( A[15] ) begin // Bank access
+        rom_addr[14:13] = bank;
+    end
+end
+
+always @* begin
+    dev_busy = mshramen & ram_cs | fm_busy;
+end
+
+always @(posedge clk) begin
+    comb_rstn <= snd_rstn & ~rst;
+    if( cen6 ) begin
+        fmcs_l <= fm_cs;
+        fm_busy <= fm_cs & ~fmcs_l;
+    end
+end
+
+always @(posedge clk) begin
+    rom_cs  <= mem_acc &&  A[15:12]  < 4'ha;
+    bank_cs <= mem_acc &&  A[15:12] == 4'ha; // this cleans the watchdog counter - not implemented
+    fm_cs   <= mem_acc &&  A[15:12] == 4'hb && !kabuki;
+    kabuki_dipsnd <= mem_acc && A[15:12] == 4'hb && kabuki;
+    cab_cs  <= mem_acc &&  A[15:12] == 4'hc && !mcu_en;
+    mcu_cs  <= mem_acc &&  A[15:12] == 4'hc &&  mcu_en;
+    ram_cs  <= mem_acc && (A[15:12] == 4'hd || A[15:12] == 4'he);
+    dial_cs <= mem_acc &&  A[15:12] == 4'hf;
+    pal_cs  <= mem_acc &&  A[15:12] == 4'hf && (A[11] ^ kabuki_mod) && !A[10] && kabuki;
+end
+
+always @(posedge clk, negedge comb_rstn) begin
+    if( !comb_rstn ) begin
+        bank     <= 0;
+        mcu_rstn <= 1;
+        dial_rst <= 0;
+    end else begin
+        if( bank_cs ) begin
+            bank     <= dout[1:0];
+            dial_rst <= dout[3:2];
+            mcu_rstn <= dout[4];
+`ifdef SIMULATION
+            if( !mcu_rstn && dout[4] ) $display("MCU reset released");
+            if( mcu_rstn && !dout[4] ) $display("MCU reset");
+`endif
+        end
+    end
+end
+
+wire [7:0] kabuki_dipsw = A[0] ? dipsw[15:8] : dipsw[7:0];
+
+always @(posedge clk) begin
+    if( !dip_pause )
+        cab_dout <= 8'hff; // do not let inputs disturb the pause
+    else begin
+        case( A[2:0] )
+            0: cab_dout <= { cab_1p[0], joystick1 };
+            1: cab_dout <= { cab_1p[1], joystick2 };
+            2: cab_dout <= (kabuki | kageki) ?
+                { 2'h3, coin[1], coin[0], 2'h3, tilt, service } :
+                { 4'hf, coin[0], coin[1],       tilt, service };
+            // 3: cab_dout <= { 7'h7f, ~coin[0] };
+            // 4: cab_dout <= { 7'h7f, ~coin[1] };
+            default: cab_dout <= 8'h00;
+        endcase
+    end
+    din <= rom_cs ? rom_data :
+           ram_cs ? ram_dout :
+           fm_cs  ? fm_dout  :
+           mcu_cs ? mcu_dout :
+           cab_cs ? cab_dout :
+           pal_cs ? pal_dout :
+           (kabuki_dipsnd & !A[2]) ? kabuki_dipsw :
+           dial_cs ? dial_dout :
+           8'h00;
+end
+
+always @(posedge clk) begin
+    case( p2_dout[2:0] )
+        3'h4: p1_din <= { cab_1p[0], joystick1 };
+        3'h5: p1_din <= { cab_1p[1], joystick2 };
+        3'h2: p1_din <= { 6'h3f, tilt, service };
+        default: p1_din <= 8'hff;
+    endcase
+end
+
+// Kageki's PCM
+reg  [7:0] pcm_lsb, pcm_re;
+wire [7:0] pcm_dcrm;
+reg  [1:0] pcm_st;
+reg  [2:0] pcm_cnt;
+reg        pcm_cen, sample_l, pb7l;
+
+always @(posedge clk, negedge comb_rstn) begin
+    if( !comb_rstn ) begin
+        pcm_cnt  <= 1;
+        pcm_cen  <= 0;
+        sample_l <= 0;
+    end else begin
+        sample_l <= sample;
+        pcm_cen  <= 0;
+        if( sample && !sample_l ) begin
+            pcm_cnt <= { pcm_cnt[1:0], pcm_cnt[2] };
+            pcm_cen <= pcm_cnt[2];
+        end
+    end
+end
+
+always @(posedge clk) begin
+    case( st_addr[5:4] )
+        0: st_dout <= { 3'd0, mcu_en, 3'd0, mcu_comb_rst };
+        1: st_dout <= mcu_st;
+        2: case( st_addr[1:0])
+            0: st_dout <= { pcm_st, portb_dout[5:0] };
+            1: st_dout <= pcm_addr[15:8];
+            2: st_dout <= pcm_re;
+            default: st_dout <= 0;
+        endcase
+        3: case( st_addr[1:0] )
+            0: st_dout <= p1_din;
+            1: st_dout <= p2_din;
+            3: st_dout <= p2_dout;
+            default: st_dout <= 0;
+        endcase
+    endcase
+end
+
+always @(posedge clk, negedge comb_rstn) begin
+    if( !comb_rstn ) begin
+        pcm_st   <= 0;
+        pcm_addr <= 0;
+        pcm_re   <= 8'h80;
+        pb7l     <= 0;
+    end else begin
+        pb7l <= portb_dout[7];
+        if( pcm_cen && pcm_ok ) begin
+            case( pcm_st )
+                default:;
+                1: begin
+                    pcm_lsb     <= pcm_data;
+                    pcm_addr[0] <= 1;
+                    pcm_st      <= 2;
+                end
+                2: begin
+                    pcm_addr <= { pcm_data, pcm_lsb };
+                    pcm_st   <= 3;
+                end
+                3: begin
+                    if( pcm_data == 0 || (&pcm_addr) ) begin
+                        pcm_st <= 0;
+                        pcm_re <= 8'h80;
+                    end else begin
+                        // the 0 value is not part of the sample.
+                        // pcm_re will keep the last valid value
+                        // this prevents noise at the start and end of samples
+                        pcm_re   <= pcm_data;
+                    end
+                    pcm_addr <= pcm_addr + 1'd1;
+                end
+            endcase
+        end
+        if( portb_dout[7] && !pb7l ) begin
+            pcm_st   <= 1;
+            pcm_addr <= { 9'd0, portb_dout[5:0], 1'b0 } + 16'h90;
+        end
+    end
+end
+
+`ifdef SIMULATION
+    integer line_cnt=1;
+
+    always @(negedge ram_cs, posedge rst) begin
+        if( rst )
+            line_cnt <= 1;
+        else
+            line_cnt <= line_cnt+1;
+    end
+`endif
+
+jtframe_ff u_irq(
+    .clk    ( clk       ),
+    .rst    ( ~comb_rstn),
+    .cen    ( 1'b1      ),
+    .din    ( 1'b1      ),
+    .q      (           ),
+    .qn     ( int_n     ),
+    .set    ( 1'b0      ),
+    .clr    ( irq_ack   ),
+    .sigedge( ~LVBL     )
+);
+
+jtframe_z80_devwait #(.RECOVERY(0)) u_gamecpu(
+    .rst_n    ( comb_rstn      ),
+    .clk      ( clk            ),
+    .cen      ( cen6           ),
+    .cpu_cen  ( cpu_cen        ),
+`ifdef NOINT
+    .int_n    ( 1'b1           ),
+    .nmi_n    ( 1'b1           ),
+`else
+    .int_n    ( int_n          ),
+    .nmi_n    ( kabuki | fmint_n ),
+`endif
+    .busrq_n  ( 1'b1           ),
+    .m1_n     ( m1_n           ),
+    .mreq_n   ( mreq_n         ),
+    .iorq_n   ( iorq_n         ),
+    .rd_n     ( rd_n           ),
+    .wr_n     ( wr_n           ),
+    .rfsh_n   ( rfsh_n         ),
+    .halt_n   (                ),
+    .busak_n  (                ),
+    .A        ( A              ),
+    .din      ( din            ),
+    .dout     ( dout           ),
+    .rom_cs   ( rom_cs         ),
+    .rom_ok   ( 1'b1           ),
+    .dev_busy ( dev_busy       )
+);
+
+`ifndef NOMCU
+// `ifdef SIMULATION
+//     reg mcu_rdl, mcu_wel;
+
+//     always @(posedge clk ) begin
+//         mcu_rdl <= |mcu_rd;
+//         mcu_wel <= |mcu_we;
+//         if( mcu_we==0 && mcu_wel ) $display("Wr %X to   %X", dout, A);
+//         if( mcu_rd==0 && mcu_rdl ) $display("Rd %X from %X",din, A);
+//     end
+// `endif
+
+jtframe_i8742 #(
+    .SIMFILE("../../firmware/arknoid2.bin")
+) u_mcu(
+    .rst        ( mcu_comb_rst ),
+    .clk        ( clk        ),
+    .cen        ( cen6       ),
+
+    // CPU communication
+    .a0         ( A[0]       ),
+    .cs_n       ( ~mcu_cs    ),
+    .cpu_rdn    ( rd_n       ),
+    .cpu_wrn    ( wr_n       ),
+    .din        ( dout       ),
+    .dout       ( mcu_dout   ),
+
+    // Ports
+    .p1_din     ( p1_din     ),
+    .p2_din     ( p2_din     ),
+    .p1_dout    ( p1_dout    ),
+    .p2_dout    ( p2_dout    ),
+
+    // Test pins (used in the assembler TEST instruction)
+    .t0_din     (~coin[0]),
+    .t1_din     (~coin[1]),
+
+    .prog_addr  ( prog_addr  ),
+    .prog_data  ( prog_data  ),
+    .prom_we    ( prom_we    ),
+
+    // Debug
+    .st_addr    ( st_addr    ),
+    .st_dout    ( mcu_st     )
+);
+`else
+    assign p2_dout  = 0;
+    assign mcu_dout = 8'hff;
+`endif
+
+always @(posedge clk) begin
+    if( kageki ) begin
+        case( portb_dout[1:0] )
+            0: porta_din <= { 4'd0, dipsw[4+8], dipsw[0+8], dipsw[4], dipsw[0] };
+            2: porta_din <= { 4'd0, dipsw[5+8], dipsw[1+8], dipsw[5], dipsw[1] };
+            1: porta_din <= { 4'd0, dipsw[6+8], dipsw[2+8], dipsw[6], dipsw[2] };
+            3: porta_din <= { 4'd0, dipsw[7+8], dipsw[3+8], dipsw[7], dipsw[3] };
+        endcase
+    end else porta_din <= dipsw[7:0];
+end
+
+// Kabuki sound CPU
+wire        snd_mreq_n, snd_m1_n, snd_iorq_n, snd_rd_n, snd_wr_n, snd_rfsh_n, snd_cpu_cen;
+reg         snd_int_n;
+reg  [ 7:0] snd_latch;
+wire [ 7:0] snd_dout, snd_ram_dout;
+wire [15:0] snd_A;
+wire  [2:0] snd_bank = porta_dout[2:0];
+reg         snd_rom_cs, snd_ram_cs, snd_bank_cs, snd_fm_cs, snd_latch_cs;
+assign      audiocpu_cs = snd_rom_cs | snd_bank_cs;
+assign      audiocpu_addr = {snd_bank_cs ? snd_bank[2:0] : {2'd0, snd_A[14]}, snd_A[13:0]};
+
+always @(posedge clk) begin
+    snd_rom_cs  <= ~snd_mreq_n && snd_rfsh_n && !snd_A[15];
+    snd_ram_cs  <= ~snd_mreq_n && snd_rfsh_n &&  snd_A[15:14] == 2'b11 && (snd_A[13] ^ kabuki_mod); // E000-FFFF or C000-DFFF
+    snd_bank_cs <= ~snd_mreq_n && snd_rfsh_n &&  snd_A[15:14] == 2'b10 && !kabuki_mod;  // 8000-BFFF
+    snd_fm_cs   <= ~snd_iorq_n && snd_m1_n && !snd_A[1];
+    snd_latch_cs<= ~snd_iorq_n && snd_m1_n &&  snd_A[1];
+
+    if (kabuki_dipsnd && !A[1]) begin
+        snd_int_n <= 0;
+        snd_latch <= dout;
+    end
+    if (snd_latch_cs) snd_int_n <= 1;
+end
+
+wire [7:0] snd_din =
+    (snd_rom_cs | snd_bank_cs) ? audiocpu_data :
+    snd_ram_cs ? snd_ram_dout :
+    snd_fm_cs  ? fm_dout :
+    snd_latch_cs ? snd_latch : 8'hFF;
+
+jtframe_z80_devwait #(.RECOVERY(0)) u_sndcpu(
+    .rst_n    ( comb_rstn & kabuki ),
+    .clk      ( clk            ),
+    .cen      ( cen6           ),
+    .cpu_cen  ( snd_cpu_cen    ),
+`ifdef NOINT
+    .int_n    ( 1'b1           ),
+    .nmi_n    ( 1'b1           ),
+`else
+    .int_n    ( snd_int_n      ),
+    .nmi_n    ( fmint_n        ),
+`endif
+    .busrq_n  ( 1'b1           ),
+    .m1_n     ( snd_m1_n       ),
+    .mreq_n   ( snd_mreq_n     ),
+    .iorq_n   ( snd_iorq_n     ),
+    .rd_n     ( snd_rd_n       ),
+    .wr_n     ( snd_wr_n       ),
+    .rfsh_n   ( snd_rfsh_n     ),
+    .halt_n   (                ),
+    .busak_n  (                ),
+    .A        ( snd_A          ),
+    .din      ( snd_din        ),
+    .dout     ( snd_dout       ),
+    .rom_cs   ( audiocpu_cs    ),
+    .rom_ok   ( audiocpu_ok    ),
+    .dev_busy ( dev_busy       )
+);
+
+jtframe_ram #(.AW(13)) u_sndram(
+    .clk    ( clk          ),
+    .cen    ( 1'b1         ),
+    // Main CPU
+    .addr   ( snd_A[12:0]  ),
+    .data   ( snd_dout     ),
+    .we     ( snd_ram_cs & ~snd_wr_n ),
+    .q      ( snd_ram_dout )
+);
+
+// only used by Arkanoid 2
+jt4701 u_dial(
+    .rst    ( rst       ),
+    .clk    ( clk       ),
+    .x_in   ( dial_x    ),
+    .y_in   ( dial_y    ),
+    .rightn ( service   ),
+    .leftn  (coin[0]),
+    .middlen(coin[1]),
+    .x_rst  (dial_rst[0]),
+    .y_rst  (dial_rst[1]),
+    .csn    ( ~dial_cs  ),
+    .uln    ( A[0]      ),
+    .xn_y   ( A[1]      ),
+    .cfn    (           ),
+    .sfn    (           ),
+    .dout   ( dial_dout ),
+    .dir    (           )
+);
+
+`ifndef VERILATOR_KEEP_JT03
+/* verilator tracing_off */
+`endif
+reg fm_cen;
+
+always @(negedge clk) fm_cen <= fast_fm ? cen3 : cen1p5;
+
+jt03 #(.YM2203_LUMPED(1)) u_2203(
+    .rst        ( ~comb_rstn ),
+    .clk        ( clk        ),
+    .cen        ( fm_cen     ),
+    .din        ( kabuki ? snd_dout : dout ),
+    .dout       ( fm_dout    ),
+    .addr       ( kabuki ? snd_A[0] : A[0] ),
+    .cs_n       ( ~fm_cs & ~snd_fm_cs ),
+    .wr_n       ( kabuki ? snd_wr_n : wr_n ),
+    .psg_snd    ( psg        ),
+    .fm_snd     ( fm         ),
+    .snd_sample ( sample     ),
+    .irq_n      ( fmint_n    ),
+    // IO ports
+    .IOA_in     ( porta_din  ),
+    .IOB_in     ( dipsw[15:8]),
+    .IOA_oe     (            ),
+    .IOA_out    ( porta_dout ),
+    .IOB_out    ( portb_dout ),
+    .IOB_oe     (            ),
+    // unused outputs
+    .psg_A      (            ),
+    .psg_B      (            ),
+    .psg_C      (            ),
+    .snd        (            ),
+    .debug_view (            )
+);
+`else
+    initial begin
+        rom_addr = 0;
+        rom_cs   = 0;
+        $display("WARNING: without the sound CPU, the main CPU won't work correctly");
+    end
+    assign ram_addr = 0;
+    assign ram_din  = 0;
+    initial ram_cs  = 0;
+    assign cpu_rnw  = 1;
+    assign snd      = 0;
+    assign sample   = 0;
+`endif
+endmodule

snapshots/jotego_jtcores_pr1111/cores/kiwi/hdl/jtkiwi_tilemap.v

@@ -0,0 +1,180 @@
+/*  This file is part of JTCORES.
+    JTCORES program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    JTCORES program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with JTCORES.  If not, see <http://www.gnu.org/licenses/>.
+
+    Author: Jose Tejada Gomez. Twitter: @topapate
+    Version: 1.0
+    Date: 7-11-2022 */
+
+// This is tile map section of the SETA chip
+// This one uses an independent line buffer
+// from that of the sprites
+
+module jtkiwi_tilemap(
+    input               rst,
+    input               clk,
+    input               pxl_cen,
+    input               tm_cen,
+
+    input               hs,
+    input               flip,
+    input               page,
+    input      [15:0]   col_xmsb,
+    input      [ 3:0]   col_cfg,
+    input      [ 1:0]   col0,
+
+    output     [11:0]   tm_addr,
+    input      [15:0]   tm_data,
+
+    // Column scroll
+    output     [ 7:0]   col_addr,
+    input      [ 7:0]   col_data,
+
+    output     [20:2]   rom_addr,
+    output              rom_cs,
+    input               rom_ok,
+    input      [31:0]   rom_data,
+
+    input      [ 8:0]   vrender,
+    input      [ 8:0]   hdump,
+    output     [ 8:0]   pxl,
+
+    input      [ 7:0]   debug_bus
+);
+
+reg         line, done, hsl, video_en;
+reg  [ 4:0] col_cnt, dr_pal;
+reg  [ 3:0] dr_ysub, col_end;
+reg  [ 8:0] eff_h, eff_v, dr_xpos;
+reg  [ 7:0] yscr;
+reg  [ 8:0] xscr;
+wire [ 8:0] vf, raw_pxl;
+reg  [ 1:0] st;
+reg         dr_draw, dr_hflip, dr_vflip, hflip, vflip;
+reg  [13:0] dr_code, code;
+wire        dr_busy;
+wire [ 8:0] buf_din, buf_addr;
+wire        buf_we;
+
+assign tm_addr  = { page, 1'b1, st[0], eff_h[8:5], eff_v[7:4], eff_h[4] }; // 1 + 1 + 1 + 4 + 5 = 12
+assign col_addr = { col_cnt[4:1], 1'd0, st[0], 2'd0 };
+assign vf       = {9{~flip}} ^ vrender;
+assign pxl      = video_en ? raw_pxl : 9'd0;
+
+always @* begin
+    eff_v = vf + { 1'b0, yscr };
+    eff_h = { col_cnt + {col0,3'd0}, 4'b0 };
+end
+
+// Columns are 32-pixel wide
+always @(posedge clk, posedge rst) begin
+    if( rst ) begin
+        col_cnt  <= 0;
+        line     <= 0;
+        hsl      <= 0;
+        dr_code  <= 0;
+        dr_hflip <= 0;
+        dr_vflip <= 0;
+        dr_xpos  <= 0;
+        dr_ysub  <= 0;
+        video_en <= 0;
+    end else begin
+        hsl <= hs;
+        dr_draw <= 0;
+        if ( hs & ~hsl ) line <= ~line;
+        if( hs || (vrender>9'hf0 && vrender<8) || col_cfg==0 ) begin
+            col_cnt  <= 0;
+            done     <= col_cfg==0; // don't do anything for col_cfg==0
+            video_en <= col_cfg!=0;
+            st       <= 0;
+            dr_draw  <= 0;
+            col_end  <= col_cfg==1 ? 4'hf : col_cfg-4'd1;
+        end else if( !done && tm_cen ) begin
+            st <= st + 1'd1;
+            case( st )
+                0: yscr <= col_data;
+                1: begin
+                    xscr <= { col_xmsb[col_cnt[4:1]], col_data };
+                end
+                2: begin
+                    { hflip, vflip } <= tm_data[15:14];
+                    code <= tm_data[13:0];
+                end
+                3: begin
+                    if( !dr_busy )  begin
+                        dr_draw  <= 1;
+                        dr_code  <= code;
+                        dr_hflip <= hflip^flip;
+                        dr_vflip <= vflip;
+                        dr_pal   <= tm_data[11+:5]; //{1'b1, tm_data[12:9] }; // some games seem to use the fifth bit too. This is probably some config setting unexplored by MAME
+                        dr_xpos  <= { 4'd0, col_cnt[0], 4'd0 } + xscr;
+                        dr_ysub  <= eff_v[3:0];
+                        col_cnt  <=  col_cnt + 1'd1;
+                        done     <= col_cnt[4:1]==col_end && col_cnt[0];
+                    end else begin
+                        st <= st;
+                    end
+                end
+            endcase
+        end
+    end
+end
+
+jtkiwi_draw #(.SWAP_HALVES(1'b1)) u_draw(
+    .rst        ( rst           ),
+    .clk        ( clk           ),
+
+    .draw       ( dr_draw       ),
+    .busy       ( dr_busy       ),
+    .code       ( dr_code       ),
+    .pal        ( dr_pal        ),
+    .hflip      ( dr_hflip      ),
+    .vflip      ( dr_vflip      ),
+    .xpos       ( dr_xpos       ),
+    .ysub       ( dr_ysub       ),
+    .flip       ( flip          ),
+
+    .rom_addr   ( rom_addr      ),
+    .rom_cs     ( rom_cs        ),
+    .rom_ok     ( rom_ok        ),
+    .rom_data   ( rom_data      ),
+
+    .buf_addr   ( buf_addr      ),
+    .buf_we     ( buf_we        ),
+    .buf_din    ( buf_din       ),
+    .debug_bus  ( 8'd0          )
+    //.debug_bus  ( debug_bus     )
+);
+
+// The tilemap is made of transparent tiles
+// that can be drawn on top of other ones. That's
+// how the sky in TNZS intro scene is drawn
+
+jtframe_obj_buffer #(
+    .DW   ( 9 ),
+    .ALPHA( 0 )
+) u_linebuf(
+    .clk    ( clk       ),
+    .flip   ( 1'b0      ),
+    .LHBL   ( ~hs       ),
+    // New line writting
+    .we     ( buf_we    ),
+    .wr_data( buf_din   ),
+    .wr_addr( buf_addr  ),
+    // Previous line reading
+    .rd     ( pxl_cen   ),
+    .rd_addr( hdump     ),
+    .rd_data( raw_pxl   )
+);
+
+endmodule

snapshots/jotego_jtcores_pr1111/cores/kiwi/hdl/jtkiwi_video.v

@@ -0,0 +1,187 @@
+/*  This file is part of JTCORES.
+    JTCORES program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    JTCORES program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with JTCORES.  If not, see <http://www.gnu.org/licenses/>.
+
+    Author: Jose Tejada Gomez. Twitter: @topapate
+    Version: 1.0
+    Date: 18-09-2022 */
+
+module jtkiwi_video(
+    input               rst,
+    input               clk,
+    input               clk_cpu,
+    input               pxl2_cen,
+    input               pxl_cen,
+    input               hb_dly,
+
+    output              LHBL,
+    output              LVBL,
+    output              HS,
+    output              VS,
+    output              flip,
+    output     [ 8:0]   hdump,
+    // PROMs
+    input      [ 9:0]   prog_addr,
+    input      [ 7:0]   prog_data,
+    input               prom_we,
+    input               colprom_en,
+    // CPU      interface
+    input               pal_cs,
+    output     [ 7:0]   pal_dout,
+    input               cpu_rnw,
+    input      [12:0]   cpu_addr,
+    input      [ 7:0]   cpu_dout,
+    input               vram_cs,
+    input               vctrl_cs,
+    input               vflag_cs,
+    output     [ 7:0]   vram_dout,
+    // Sub-CPU interface
+    input               pal2_cs,
+    input      [ 7:0]   cpu2_dout,
+    input               cpu2_rnw,
+    input      [ 9:0]   cpu2_addr,
+    // SDRAM interface
+    output     [20:2]   scr_addr,
+    input      [31:0]   scr_data,
+    input               scr_ok,
+    output              scr_cs,
+
+    output     [20:2]   obj_addr,
+    input      [31:0]   obj_data,
+    input               obj_ok,
+    output              obj_cs,
+    // Colours
+    output     [ 4:0]   red,
+    output     [ 4:0]   green,
+    output     [ 4:0]   blue,
+    // Test
+    input      [ 3:0]   gfx_en,
+    input      [ 7:0]   debug_bus,
+    output     [ 7:0]   st_dout
+);
+
+wire [ 8:0] vrender, vrender1, vdump;
+wire [ 8:0] scr_pxl, obj_pxl;
+reg  [ 7:0] LHBL_l;
+wire        preLHBL;
+
+assign LHBL = hb_dly ? LHBL_l[4] : preLHBL; // used by JTKIWI
+
+always @(posedge clk) begin
+    LHBL_l <= LHBL_l<<1;
+    LHBL_l[0] <= preLHBL;
+end
+
+jtframe_vtimer #(
+    .HB_START( 9'd256 ),
+    .HS_START( 9'd297 ),
+    .HCNT_END( 9'd383 ),
+    .HB_END  ( 9'd0   ),
+    .V_START ( 9'd008 ),
+    .VS_START( 9'd254 ),
+    .VB_START( 9'd239 ),
+    .VCNT_END( 9'd271 ),
+    .VB_END  ( 9'd015 )
+) u_timer(
+    .clk        ( clk        ),
+    .pxl_cen    ( pxl_cen    ),
+    .vdump      ( vdump      ),
+    .vrender    ( vrender    ),
+    .vrender1   ( vrender1   ),
+    .H          ( hdump      ),
+    .Hinit      (            ),
+    .Vinit      (            ),
+    .LHBL       ( preLHBL    ),
+    .LVBL       ( LVBL       ),
+    .HS         ( HS         ),
+    .VS         ( VS         )
+);
+
+jtkiwi_gfx u_gfx(
+    .rst        ( rst            ),
+    .clk        ( clk            ),
+    .clk_cpu    ( clk_cpu        ),
+    .pxl_cen    ( pxl_cen        ),
+    .pxl2_cen   ( pxl2_cen       ),
+    // PROMs
+    // .prog_addr  ( prog_addr      ),
+    // .prog_data  ( prog_data      ),
+    // .prom_we    ( prom_we        ),
+    // Screen
+    .flip       ( flip           ),
+    .LHBL       ( LHBL           ),
+    .LVBL       ( LVBL           ),
+    .vs         ( VS             ),
+    .hs         ( HS             ),
+    .vdump      ( vdump          ),
+    .vrender    ( vrender        ),
+    .hdump      ( hdump          ),
+    // CPU interface
+    .vram_cs    ( vram_cs        ),
+    .vctrl_cs   ( vctrl_cs       ),
+    .vflag_cs   ( vflag_cs       ),
+    .cpu_din    ( vram_dout      ),
+    .cpu_addr   ( cpu_addr       ),
+    .cpu_rnw    ( cpu_rnw        ),
+    .cpu_dout   ( cpu_dout       ),
+    // SDRAM
+    .scr_addr   ( scr_addr       ),
+    .scr_data   ( scr_data       ),
+    .scr_ok     ( scr_ok         ),
+    .scr_cs     ( scr_cs         ),
+
+    .obj_addr   ( obj_addr       ),
+    .obj_data   ( obj_data       ),
+    .obj_ok     ( obj_ok         ),
+    .obj_cs     ( obj_cs         ),
+    // Color address to palette
+    .scr_pxl    ( scr_pxl        ),
+    .obj_pxl    ( obj_pxl        ),
+    .debug_bus  ( debug_bus      ),
+    .st_dout    ( st_dout        )
+);
+
+jtkiwi_colmix u_colmix(
+    .clk        ( clk            ),
+    .clk_cpu    ( clk_cpu        ),
+    .pxl_cen    ( pxl_cen        ),
+    // Screen
+    .LHBL       ( LHBL           ),
+    .LVBL       ( LVBL           ),
+    // CPU interface
+    .cpu_addr   ( cpu_addr[9:0]  ),
+    .cpu_rnw    ( cpu_rnw        ),
+    .cpu_dout   ( cpu_dout       ),
+    .cpu_din    ( pal_dout       ),
+    .pal_cs     ( pal_cs         ),
+    // Sub-CPU interface
+    .pal2_cs    ( pal2_cs        ),
+    .cpu2_addr  ( cpu2_addr[9:0] ),
+    .cpu2_rnw   ( cpu2_rnw       ),
+    .cpu2_dout  ( cpu2_dout      ),
+    // PROMs
+    .prog_addr  ( prog_addr      ),
+    .prog_data  ( prog_data      ),
+    .prom_we    ( prom_we        ),
+    .colprom_en ( colprom_en     ),
+    // Colour output
+    .scr_pxl    ( scr_pxl        ),
+    .obj_pxl    ( obj_pxl        ),
+    .red        ( red            ),
+    .green      ( green          ),
+    .blue       ( blue           ),
+    .gfx_en     ( gfx_en         ),
+    .debug_bus  ( debug_bus      )
+);
+
+endmodule

snapshots/jotego_jtcores_pr1111/cores/kiwi/ver/extrm/sim.sh

@@ -0,0 +1,34 @@
+#!/bin/bash
+
+# The MCU gets out of reset at frame 19
+
+# Use cpsnap.sh to copy MAME scenes to a new folder
+
+ARG=
+SCENE=
+
+touch seta_cfg.hex
+
+while [ $# -gt 0 ]; do
+    case $1 in
+        -s) shift
+            SCENE=$1
+            ARG="$ARG -d NOMAIN -d NOMCU -nosnd -video 2"
+            ;;
+        *) ARG="$ARG $1";;
+    esac
+    shift
+done
+
+if [ ! -z "$SCENE" ]; then
+    if [ ! -d "$SCENE" ]; then
+        echo "Requested scene $SCENE cannot be found"
+        exit 1
+    fi
+    cp $SCENE/* .
+fi
+
+
+if [ ! -e rom.bin ]; then ln -sf $ROM/extrmatn.rom rom.bin; fi
+
+jtsim -sysname kiwi -d JTFRAME_SIM_ROMRQ_NOCHECK $ARG