Add files using upload-large-folder tool

snapshots/jotego_jtcores_pr960/cores/aliens/ver/crimfght/obj.gtkw

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+[*]
+[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
+[*] Sat Jun 24 14:10:34 2023
+[*]
+[dumpfile] "/home/jtejada/jtcores/cores/aliens/ver/crime/test.fst"
+[dumpfile_mtime] "Sat Jun 24 14:01:27 2023"
+[dumpfile_size] 993307
+[savefile] "/home/jtejada/jtcores/cores/aliens/ver/crime/obj.gtkw"
+[timestart] 12217370000
+[size] 1264 1013
+[pos] -1 -1
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snapshots/jotego_jtcores_pr960/cores/aliens/ver/crimfght/scene.sh

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+#!/bin/bash
+
+# Video simulation
+
+SCENE=SCONTRA.RAM
+OTHER=
+
+while [ $# -gt 0 ]; do
+    case $1 in
+        -s|-scene)
+            shift
+            SCENE=$1;;
+        *)
+            OTHER="$OTHER $1";;
+    esac
+    shift
+done
+
+if [ ! -e $SCENE ]; then
+    echo "Generate $SCENE on MiST by saving the NVRAM"
+    echo "And copying SCONTRA.RAM from MiST's SD card to here"
+    exit 0
+fi
+
+NULLDD="dd status=none if=$SCENE"
+
+# 16 kB Tilemap VRAM
+$NULLDD of=scr1.bin count=16
+$NULLDD of=scr0.bin count=16 skip=16
+# 2 kB PAL
+$NULLDD of=pal.bin count=4 skip=32
+# 1 kB Sprite LUT
+$NULLDD of=obj.bin count=2 skip=36
+# 8 bytes for tilemap MMR
+$NULLDD of=scr_mmr.bin count=1 skip=2432 ibs=8
+# 8 bytes for object MMR
+$NULLDD of=obj_mmr.bin count=1 skip=2433 ibs=8
+# Priority config
+$NULLDD of=prio.bin count=1 skip=19471 ibs=1
+
+jtsim -sysname aliens -nosnd -d NOMAIN -video 1 -zoom $OTHER

snapshots/jotego_jtcores_pr960/cores/aliens/ver/crimfght/sim.sh

@@ -0,0 +1,3 @@
+#!/bin/bash
+
+jtsim -sysname aliens $*

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snapshots/jotego_jtcores_pr960/cores/aliens/ver/game/misc.gtkw

@@ -0,0 +1,149 @@
+[*]
+[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
+[*] Sun Jun  4 16:59:31 2023
+[*]
+[dumpfile] "/home/jtejada/jtcores/cores/aliens/ver/game/test.fst"
+[dumpfile_mtime] "Sun Jun  4 16:59:19 2023"
+[dumpfile_size] 251057994
+[savefile] "/home/jtejada/jtcores/cores/aliens/ver/game/misc.gtkw"
+[timestart] 1025450000
+[size] 1262 1024
+[pos] -1 -1
+*-20.882450 1028736240 471087942192 1028736240 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] TOP.
+[treeopen] TOP.game_test.
+[treeopen] TOP.game_test.u_game.
+[treeopen] TOP.game_test.u_game.u_game.
+[treeopen] TOP.game_test.u_game.u_game.u_main.
+[treeopen] TOP.game_test.u_game.u_game.u_main.u_cpu.
+[treeopen] TOP.game_test.u_game.u_game.u_main.u_cpu.u_alu.
+[treeopen] TOP.game_test.u_game.u_game.u_main.u_cpu.u_ctrl.
+[treeopen] TOP.game_test.u_game.u_game.u_video.
+[treeopen] TOP.game_test.u_game.u_game.u_video.u_scroll.
+[treeopen] TOP.game_test.u_game.u_game.u_video.u_scroll.u_tilemap.
+[sst_width] 223
+[signals_width] 275
+[sst_expanded] 1
+[sst_vpaned_height] 364
+@24
+TOP.game_test.frame_cnt[31:0]
+@28
+TOP.game_test.u_game.u_game.u_main.rst8
+@200
+-
+@22
+TOP.game_test.u_game.u_game.u_main.u_cpu.u_ctrl.pc[15:0]
+@2022
+^1 /home/jtejada/jtcores/modules/jtkcpu/cfg/op.gtkwave
+TOP.game_test.u_game.u_game.u_main.u_cpu.u_ctrl.op[7:0]
+@20000
+-
+@c00022
+TOP.game_test.u_game.u_game.u_main.u_cpu.u_regs.cc[7:0]
+@28
+(0)TOP.game_test.u_game.u_game.u_main.u_cpu.u_regs.cc[7:0]
+(1)TOP.game_test.u_game.u_game.u_main.u_cpu.u_regs.cc[7:0]
+(2)TOP.game_test.u_game.u_game.u_main.u_cpu.u_regs.cc[7:0]
+(3)TOP.game_test.u_game.u_game.u_main.u_cpu.u_regs.cc[7:0]
+(4)TOP.game_test.u_game.u_game.u_main.u_cpu.u_regs.cc[7:0]
+(5)TOP.game_test.u_game.u_game.u_main.u_cpu.u_regs.cc[7:0]
+(6)TOP.game_test.u_game.u_game.u_main.u_cpu.u_regs.cc[7:0]
+(7)TOP.game_test.u_game.u_game.u_main.u_cpu.u_regs.cc[7:0]
+@1401200
+-group_end
+@22
+TOP.game_test.u_game.u_game.u_main.u_cpu.u_regs.a[7:0]
+TOP.game_test.u_game.u_game.u_main.u_cpu.u_regs.b[7:0]
+TOP.game_test.u_game.u_game.u_main.u_cpu.u_regs.dp[7:0]
+@200
+-
+@22
+TOP.game_test.u_game.u_game.u_main.u_cpu.u_regs.x[15:0]
+TOP.game_test.u_game.u_game.u_main.u_cpu.u_regs.y[15:0]
+[color] 2
+TOP.game_test.u_game.u_game.u_main.u_cpu.u_regs.u[15:0]
+TOP.game_test.u_game.u_game.u_main.u_cpu.u_regs.s[15:0]
+@200
+-
+@c00022
+TOP.game_test.u_game.u_game.u_main.u_cpu.addr[23:0]
+@28
+(0)TOP.game_test.u_game.u_game.u_main.u_cpu.addr[23:0]
+(1)TOP.game_test.u_game.u_game.u_main.u_cpu.addr[23:0]
+(2)TOP.game_test.u_game.u_game.u_main.u_cpu.addr[23:0]
+(3)TOP.game_test.u_game.u_game.u_main.u_cpu.addr[23:0]
+(4)TOP.game_test.u_game.u_game.u_main.u_cpu.addr[23:0]
+(5)TOP.game_test.u_game.u_game.u_main.u_cpu.addr[23:0]
+(6)TOP.game_test.u_game.u_game.u_main.u_cpu.addr[23:0]
+(7)TOP.game_test.u_game.u_game.u_main.u_cpu.addr[23:0]
+(8)TOP.game_test.u_game.u_game.u_main.u_cpu.addr[23:0]
+(9)TOP.game_test.u_game.u_game.u_main.u_cpu.addr[23:0]
+(10)TOP.game_test.u_game.u_game.u_main.u_cpu.addr[23:0]
+(11)TOP.game_test.u_game.u_game.u_main.u_cpu.addr[23:0]
+(12)TOP.game_test.u_game.u_game.u_main.u_cpu.addr[23:0]
+(13)TOP.game_test.u_game.u_game.u_main.u_cpu.addr[23:0]
+[color] 1
+(14)TOP.game_test.u_game.u_game.u_main.u_cpu.addr[23:0]
+[color] 1
+(15)TOP.game_test.u_game.u_game.u_main.u_cpu.addr[23:0]
+[color] 1
+(16)TOP.game_test.u_game.u_game.u_main.u_cpu.addr[23:0]
+(17)TOP.game_test.u_game.u_game.u_main.u_cpu.addr[23:0]
+(18)TOP.game_test.u_game.u_game.u_main.u_cpu.addr[23:0]
+(19)TOP.game_test.u_game.u_game.u_main.u_cpu.addr[23:0]
+(20)TOP.game_test.u_game.u_game.u_main.u_cpu.addr[23:0]
+(21)TOP.game_test.u_game.u_game.u_main.u_cpu.addr[23:0]
+(22)TOP.game_test.u_game.u_game.u_main.u_cpu.addr[23:0]
+(23)TOP.game_test.u_game.u_game.u_main.u_cpu.addr[23:0]
+@1401200
+-group_end
+@28
+TOP.game_test.u_game.u_game.u_main.init
+@200
+-
+@22
+TOP.game_test.u_game.u_game.u_main.u_cpu.u_alu.opnd0[15:0]
+TOP.game_test.u_game.u_game.u_main.u_cpu.u_alu.opnd1[15:0]
+TOP.game_test.u_game.u_game.u_main.u_cpu.u_alu.rslt[15:0]
+@200
+-
+@28
+TOP.game_test.u_game.u_game.u_main.banked_cs
+TOP.game_test.u_game.u_game.u_main.pal_cs
+TOP.game_test.u_game.u_game.u_main.ram_cs
+TOP.game_test.u_game.u_game.u_main.io_cs
+TOP.game_test.u_game.u_game.u_main.objsys_cs
+TOP.game_test.u_game.u_game.u_main.rom_cs
+TOP.game_test.u_game.u_game.u_main.tilesys_cs
+@29
+TOP.game_test.u_game.u_game.u_main.incs
+@200
+-
+@28
+TOP.game_test.u_game.u_game.u_main.cpu_we
+@22
+[color] 2
+TOP.game_test.u_game.u_game.u_main.cpu_dout[7:0]
+TOP.game_test.u_game.u_game.u_main.cpu_din[7:0]
+TOP.game_test.u_game.u_game.u_main.tilesys_dout[7:0]
+@28
+TOP.game_test.u_game.u_game.u_video.u_scroll.u_tilemap.cs[2:0]
+TOP.game_test.u_game.u_game.u_video.u_scroll.u_tilemap.gfx_cs
+[color] 1
+TOP.game_test.u_game.u_game.u_video.u_scroll.u_tilemap.reg_we
+@200
+-
+@22
+TOP.game_test.u_game.u_game.u_main.bank[3:0]
+@28
+TOP.game_test.u_game.u_game.u_main.work
+TOP.game_test.u_game.u_game.u_main.init
+TOP.game_test.u_game.u_game.u_main.rmrd
+TOP.game_test.u_game.u_game.u_main.bad_cs
+@22
+TOP.game_test.u_game.u_game.u_video.u_scroll.u_tilemap.range0[3:0]
+TOP.game_test.u_game.u_game.u_video.u_scroll.u_tilemap.range1[3:0]
+TOP.game_test.u_game.u_game.u_video.u_scroll.u_tilemap.range2[3:0]
+TOP.game_test.u_game.u_game.u_video.u_scroll.u_tilemap.cfg[7:0]
+[pattern_trace] 1
+[pattern_trace] 0

snapshots/jotego_jtcores_pr960/cores/aliens/ver/game/objram.mame

@@ -0,0 +1,3 @@
+wpset 7C00,400,w,1,{printf "%04X=%02X", wpaddr, wpdata; go}
+wpset 0000,400,w,1,{printf "%04X=%02X", wpaddr, wpdata; go}
+go

snapshots/jotego_jtcores_pr960/cores/aliens/ver/game/objram.sh

@@ -0,0 +1,4 @@
+#!/bin/bash
+mame aliens -debug -debuglog -debugscript objram.mame -cheat
+jtutil log2bin -a 0x7c00 -s 0x400 -o obj.bin
+jtutil log2bin -a 0x0000 -s 0x400 -o pal.bin

snapshots/jotego_jtcores_pr960/cores/aliens/ver/game/pcm.gtkw

@@ -0,0 +1,60 @@
+[*]
+[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
+[*] Sat May 13 06:55:06 2023
+[*]
+[dumpfile] "/home/jtejada/jtcores/cores/aliens/ver/game/test.fst"
+[dumpfile_mtime] "Sat May 13 06:54:47 2023"
+[dumpfile_size] 2111132
+[savefile] "/home/jtejada/jtcores/cores/aliens/ver/game/pcm.gtkw"
+[timestart] 4326200000000
+[size] 1278 996
+[pos] -1 -1
+*-29.352118 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] TOP.
+[treeopen] TOP.game_test.
+[treeopen] TOP.game_test.u_game.
+[treeopen] TOP.game_test.u_game.u_game.
+[treeopen] TOP.game_test.u_game.u_game.u_sound.
+[treeopen] TOP.game_test.u_game.u_game.u_sound.u_pcm.
+[sst_width] 223
+[signals_width] 220
+[sst_expanded] 1
+[sst_vpaned_height] 292
+@24
+TOP.game_test.frame_cnt[31:0]
+@22
+TOP.game_test.u_game.u_game.u_sound.u_pcm.roma_addr[16:0]
+@28
+TOP.game_test.u_game.u_game.u_sound.u_pcm.u_cha.play
+@200
+-
+@22
+TOP.game_test.u_game.u_game.u_sound.u_pcm.romb_addr[16:0]
+@28
+TOP.game_test.u_game.u_game.u_sound.u_pcm.u_chb.loop
+TOP.game_test.u_game.u_game.u_sound.u_pcm.u_chb.play
+@8420
+TOP.game_test.u_game.u_game.u_sound.u_pcm.snda[7:0]
+@20000
+-
+@8420
+TOP.game_test.u_game.u_game.u_sound.u_pcm.sndb[7:0]
+@20000
+-
+@8420
+TOP.game_test.u_game.u_game.u_sound.u_pcm.snd[11:0]
+@20000
+-
+@22
+TOP.game_test.u_game.u_game.u_sound.u_pcm.cha_gain[4:0]
+TOP.game_test.u_game.u_game.u_sound.u_pcm.chb_gain[4:0]
+@28
+TOP.game_test.u_game.u_game.u_sound.dac_cs
+@10420
+TOP.game_test.u_game.u_game.u_sound.fm_left[15:0]
+@28
+TOP.game_test.u_game.u_game.u_sound.cfg
+TOP.game_test.u_game.u_game.u_sound.ct[1:0]
+TOP.game_test.u_game.u_game.u_sound.fm_cs
+[pattern_trace] 1
+[pattern_trace] 0

snapshots/jotego_jtcores_pr960/cores/aliens/ver/game/sim.sh

@@ -0,0 +1,8 @@
+#!/bin/bash
+
+if [ -e aliens.bin ]; then
+    dd if=aliens.bin of=scr0.bin count=16
+    dd if=aliens.bin of=scr1.bin count=16 skip=16
+fi
+
+jtsim $*

snapshots/jotego_jtcores_pr960/cores/aliens/ver/game/trace.mame

@@ -0,0 +1,6 @@
+trace off
+trace debug.trace,maincpu,noloop,{tracelog "PC=%X,cc=%X,dp=%x,a=%x,b=%x,x=%x,y=%x,u=%x,s=%x,frame_cnt=%x* ",pc,cc,dp,a,b,x,y,u,s,frame}
+// simulate x ms seconds
+gtime 3652
+traceflush
+

snapshots/verilator_verilator_pr6630/test_regress/t/t_array_method_map.py

@@ -0,0 +1,19 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile(fails=test.vlt_all, expect_filename=test.golden_filename)
+
+if not test.vlt_all:
+    test.execute()
+
+test.passes()

snapshots/verilator_verilator_pr6630/test_regress/t/t_class1.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute(expect_filename=test.golden_filename)
+
+test.passes()

snapshots/verilator_verilator_pr6630/test_regress/t/t_class_override_bad.py

@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('linter')
+
+test.lint(fails=True, expect_filename=test.golden_filename)
+
+test.passes()

snapshots/verilator_verilator_pr6630/test_regress/t/t_constraint_assoc_arr_bad.out

@@ -0,0 +1,16 @@
+%Warning-CONSTRAINTIGN: t/t_constraint_assoc_arr_bad.v:12:20: Unsupported: Constrained randomization of associative array keys of 144bits, limit is 128 bits
+   12 |         string_arr["a_very_long_string"] == 65;
+      |                    ^~~~~~~~~~~~~~~~~~~~
+                        ... For warning description see https://verilator.org/warn/CONSTRAINTIGN?v=latest
+                        ... Use "/* verilator lint_off CONSTRAINTIGN */" and lint_on around source to disable this message.
+%Error: t/t_constraint_assoc_arr_bad.v:30:26: Illegal non-integral expression or subexpression in random constraint. (IEEE 1800-2023 18.3)
+   30 |     constraint c1 { data[cl] > 0;}  
+      |                          ^~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
+%Error: t/t_constraint_assoc_arr_bad.v:44:44: Illegal non-integral expression or subexpression in random constraint. (IEEE 1800-2023 18.3)
+   44 |     constraint c2 { foreach (data[i]) data[i] < 100; }  
+      |                                            ^
+%Error: t/t_constraint_assoc_arr_bad.v:58:44: Illegal non-integral expression or subexpression in random constraint. (IEEE 1800-2023 18.3)
+   58 |     constraint c3 { foreach (data[i]) data[i] > 0; }
+      |                                            ^
+%Error: Exiting due to

snapshots/verilator_verilator_pr6630/test_regress/t/t_export_packed_struct.v

@@ -0,0 +1,133 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2024 by Kefa Chen.
+// SPDX-License-Identifier: CC0-1.0
+
+typedef logic [5:0] udata6_t;
+
+typedef union soft packed {
+    udata6_t      a;
+    logic [2 : 0] b;
+} sub_t;
+
+typedef struct packed {
+  logic [40:0]   a;
+  udata6_t [3:0] nullptr;  // name confict test
+  sub_t          get;      // name confict test
+} in_t  /*verilator public*/;
+
+typedef struct packed {
+  udata6_t [3:0] nullptr;
+  sub_t          get;
+  logic [40:0]   a;
+} out_t  /*verilator public*/;
+
+// struct in1_t should cover parts of VL_ASSIGNSEL_II functions
+typedef struct packed {
+  logic [3:0]  a;
+  logic [11:0] b;
+} in1_t  /*verilator public*/;  // 4 + 12 = 16
+
+typedef struct packed {
+  logic [11:0] b;
+  logic [3:0]  a;
+} out1_t  /*verilator public*/;
+
+// struct in2_t should cover all VL_ASSIGNSEL_II functions
+typedef struct packed {
+  logic [2:0]  a;
+  logic [8:0]  b;
+  logic [18:0] c;
+} in2_t  /*verilator public*/;  // 3 + 9 + 19 = 31
+
+typedef struct packed {
+  logic [8:0]  b;
+  logic [18:0] c;
+  logic [2:0]  a;
+} out2_t  /*verilator public*/;
+
+// struct in3_t should cover all VL_ASSIGNSEL_XQ functions
+typedef struct packed {
+  logic [1:0]  a;
+  logic [8:0]  b;
+  logic [16:0] c;
+  logic [32:0] d;
+} in3_t  /*verilator public*/;  // 33 + 17 + 9 + 2 = 61
+
+typedef struct packed {
+  logic [8:0]  b;
+  logic [1:0]  a;
+  logic [32:0] d;
+  logic [16:0] c;
+} out3_t  /*verilator public*/;
+
+// struct in4_t should cover all VL_ASSIGNSEL_XW functions
+typedef struct packed {
+  logic [4:0]  a;
+  logic [12:0] b;
+  logic [24:0] c;
+  logic [48:0] d;
+  logic [80:0] e;
+} in4_t  /*verilator public*/;  // 5 + 13 + 25 + 49 + 81 = 173
+
+typedef struct packed {
+  logic [24:0] c;
+  logic [48:0] d;
+  logic [80:0] e;
+  logic [4:0]  a;
+  logic [12:0] b;
+} out4_t  /*verilator public*/;
+
+module add (
+  input  in_t   op1,
+  input  in_t   op2,
+  output out_t  out,
+  // Add some extra ports to test all VL_ASSIGNSEL_XX functions
+  input  in1_t  op1a,
+  input  in1_t  op1b,
+  output out1_t out1,
+  // Add some extra ports to test all VL_ASSIGNSEL_XX functions
+  input  in2_t  op2a,
+  input  in2_t  op2b,
+  output out2_t out2,
+  // Add some extra ports to test all VL_ASSIGNSEL_XX functions
+  input  in3_t  op3a,
+  input  in3_t  op3b,
+  output out3_t out3,
+  // Add some extra ports to test all VL_ASSIGNSEL_XX functions
+  input  in4_t  op4a,
+  input  in4_t  op4b,
+  output out4_t out4
+);
+  assign out.a = op1.a + op2.a;
+  generate
+    for (genvar i = 0; i < 4; ++i) begin
+      assign out.nullptr[i] = op1.nullptr[i] + op2.nullptr[i];
+    end
+  endgenerate
+  assign out.get.a = op1.get.a + op2.get.a;
+
+  // out1
+  assign out1.a    = op1a.a + op1b.a;
+  assign out1.b    = op1a.b + op1b.b;
+
+  // out2
+  assign out2.a    = op2a.a + op2b.a;
+  assign out2.b    = op2a.b + op2b.b;
+  assign out2.c    = op2a.c + op2b.c;
+
+  // out3
+  assign out3.a    = op3a.a + op3b.a;
+  assign out3.b    = op3a.b + op3b.b;
+  assign out3.c    = op3a.c + op3b.c;
+  assign out3.d    = op3a.d + op3b.d;
+
+  // out4
+  assign out4.a    = op4a.a + op4b.a;
+  assign out4.b    = op4a.b + op4b.b;
+  assign out4.c    = op4a.c + op4b.c;
+  assign out4.d    = op4a.d + op4b.d;
+  assign out4.e    = op4a.e + op4b.e;
+
+endmodule

snapshots/verilator_verilator_pr6630/test_regress/t/t_fork_dynscope_unsup.v

@@ -0,0 +1,24 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2024 by Antmicro.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+  bit p = 0, q = 0;
+
+  initial begin
+    t1(p);
+    t2(q);
+  end
+
+  task t1(inout p);
+    fork
+      p = #1 1;
+    join_none
+  endtask
+
+  task t2(output q);
+    q <= #1 1;
+  endtask
+endmodule

snapshots/verilator_verilator_pr6630/test_regress/t/t_func_link.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()

snapshots/verilator_verilator_pr6630/test_regress/t/t_sys_rand.v

@@ -0,0 +1,37 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2008 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+
+   reg [31:0] lastrand;
+   reg [31:0] thisrand;
+
+   integer    same = 0;
+   integer    i;
+
+`define TRIES 20
+
+   initial begin
+      // There's a 1^32 chance of the numbers being the same twice,
+      // so we'll allow one failure
+      lastrand = $random;
+      for (i=0; i<`TRIES; i=i+1) begin
+         thisrand = $random;
+`ifdef TEST_VERBOSE
+         $write("Random = %x\n", thisrand);
+`endif
+         if (thisrand == lastrand) same=same+1;
+         lastrand = thisrand;
+      end
+      if (same > 1) begin
+         $write("%%Error: Too many similar numbers: %d\n", same);
+         $stop;
+      end
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule

snapshots/verilator_verilator_pr6630/test_regress/t/t_var_xref_gen.py

@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.compile(verilator_flags2=["--debug-check"])
+
+test.passes()

snapshots/verilator_verilator_pr6630/test_regress/t/t_vpi_public_params.py

@@ -0,0 +1,26 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.pli_filename = "t/t_vpi_param.cpp"
+
+# same vpi script should work with --public-params instead of inline publics
+
+test.compile(make_top_shell=False,
+             make_main=False,
+             make_pli=True,
+             iv_flags2=["-g2005-sv -D USE_VPI_NOT_DPI"],
+             v_flags2=["+define+USE_VPI_NOT_DPI"],
+             verilator_flags2=["--exe --vpi --no-l2name", test.pli_filename, "--public-params"])
+
+test.execute(use_libvpi=True)
+
+test.passes()