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DATA_MANIFEST.md

@@ -1,513 +1,13 @@
-# Phoenix-Bench — 511-case benchmark data (testbench_verilator, issues, snapshots)
+# Phoenix-Bench — 511-case benchmark data
 
-Canonical set: 511 cases (patch_edit_stats.csv / patch_complexity_summary.txt).
-Excluded from upload: .git directories, verilator obj_dir build artifacts, broken symlinks.
+Each case provides four aligned artifacts under a common root:
+  testbench/<case>/   verilator differential testbench (run via run_once.sh / run_verilator.sh)
+  snapshots/<case>/   pre-PR repository snapshot (RTL sources)
+  patches/<case>.patch the fix; testbench reverse-applies for buggy, applies for fixed
+  issues/<case>       issue description
+  testbench/_*        shared run helpers (sourced by per-case scripts)
 
-Staged counts (instances present locally):
-  issues:              502
-  testbench_verilator: 499
-  snapshots:           502
+Counts: testbench=511  snapshots=511  patches=511  issues=511
 
-## Instances (union)
-alexforencich_verilog-pcie_pr20
-aolofsson_oh_pr109
-aolofsson_oh_pr110
-aolofsson_oh_pr111
-aolofsson_oh_pr114
-aolofsson_oh_pr58
-aolofsson_oh_pr73
-aolofsson_oh_pr74
-aolofsson_oh_pr75
-aolofsson_oh_pr81
-aolofsson_oh_pr82
-apfaudio_eurorack-pmod_pr36
-AsFigo_pyslint_pr138
-AsFigo_pyslint_pr140
-AsFigo_pyslint_pr149
-AsFigo_pyslint_pr164
-AsFigo_pyslint_pr166
-AsFigo_pyslint_pr167
-AsFigo_pyslint_pr169
-AsFigo_pyslint_pr175
-AsFigo_pyslint_pr180
-AsFigo_pyslint_pr185
-AsFigo_pyslint_pr56
-AUCOHL_Lighter_pr16
-bensampson5_libsv_pr100
-bensampson5_libsv_pr102
-bensampson5_libsv_pr106
-bensampson5_libsv_pr109
-bensampson5_libsv_pr119
-bensampson5_libsv_pr132
-bensampson5_libsv_pr150
-bensampson5_libsv_pr153
-bensampson5_libsv_pr19
-bensampson5_libsv_pr2
-bensampson5_libsv_pr59
-bensampson5_libsv_pr61
-bensampson5_libsv_pr63
-bensampson5_libsv_pr73
-bensampson5_libsv_pr98
-bespoke-silicon-group_basejump_stl_pr371
-bespoke-silicon-group_basejump_stl_pr392
-bespoke-silicon-group_basejump_stl_pr422
-bespoke-silicon-group_basejump_stl_pr450
-bespoke-silicon-group_basejump_stl_pr472
-bespoke-silicon-group_basejump_stl_pr668
-bespoke-silicon-group_basejump_stl_pr673
-bespoke-silicon-group_basejump_stl_pr675
-bespoke-silicon-group_basejump_stl_pr676
-bespoke-silicon-group_basejump_stl_pr677
-bespoke-silicon-group_basejump_stl_pr697
-bespoke-silicon-group_basejump_stl_pr699
-bespoke-silicon-group_basejump_stl_pr706
-bespoke-silicon-group_basejump_stl_pr710
-bespoke-silicon-group_basejump_stl_pr715
-bespoke-silicon-group_basejump_stl_pr735
-bespoke-silicon-group_basejump_stl_pr737
-bespoke-silicon-group_basejump_stl_pr739
-bespoke-silicon-group_bsg_manycore_pr587
-bespoke-silicon-group_bsg_manycore_pr635
-black-parrot_black-parrot_pr1089
-black-parrot_black-parrot_pr1232
-black-parrot_black-parrot_pr947
-black-parrot_black-parrot_pr974
-budude2_openfpga-GBC_pr41
-buppu3_tnCart_pr17
-chili-chips-ba_openeye-CamSI_pr13
-chili-chips-ba_openeye-CamSI_pr15
-chili-chips-ba_openeye-CamSI_pr26
-chili-chips-ba_openeye-CamSI_pr30
-chipsalliance_adams-bridge_pr175
-chipsalliance_adams-bridge_pr176
-chipsalliance_adams-bridge_pr213
-chipsalliance_adams-bridge_pr222
-chipsalliance_adams-bridge_pr228
-chipsalliance_adams-bridge_pr245
-chipsalliance_adams-bridge_pr66
-chipsalliance_adams-bridge_pr68
-chipsalliance_adams-bridge_pr77
-chipsalliance_adams-bridge_pr79
-chipsalliance_adams-bridge_pr82
-chipsalliance_caliptra-rtl_pr1132
-chipsalliance_caliptra-rtl_pr757
-chipsalliance_caliptra-rtl_pr791
-chipsalliance_caliptra-rtl_pr883
-chipsalliance_caliptra-rtl_pr919
-chipsalliance_caliptra-rtl_pr921
-chipsalliance_caliptra-rtl_pr963
-chipsalliance_caliptra-ss_pr550
-chipsalliance_caliptra-ss_pr565
-chipsalliance_caliptra-ss_pr590
-chipsalliance_caliptra-ss_pr750
-chipsalliance_caliptra-ss_pr838
-chipsalliance_Cores-VeeR-EL2_pr151
-chipsalliance_Cores-VeeR-EL2_pr153
-chipsalliance_Cores-VeeR-EL2_pr259
-chipsalliance_Cores-VeeR-EL2_pr265
-chipsalliance_Cores-VeeR-EL2_pr363
-chipsalliance_Cores-VeeR-EL2_pr423
-chipsalliance_i3c-core_pr35
-chipsalliance_sv-tests_pr7781
-darklife_darkriscv_pr95
-dawsonjon_fpu_pr16
-efabless_clear_pr20
-esa-tu-darmstadt_tapasco_pr105
-esa-tu-darmstadt_tapasco_pr186
-FPGA-MAFIA_fpga_mafia_pr428
-FPGA-MAFIA_fpga_mafia_pr429
-FPGA-MAFIA_fpga_mafia_pr449
-FPGA-MAFIA_fpga_mafia_pr451
-FPGA-MAFIA_fpga_mafia_pr452
-FPGA-MAFIA_fpga_mafia_pr465
-FPGA-MAFIA_fpga_mafia_pr473
-FPGA-MAFIA_fpga_mafia_pr479
-FPGA-MAFIA_fpga_mafia_pr495
-FPGA-MAFIA_fpga_mafia_pr499
-FPGA-MAFIA_fpga_mafia_pr548
-FPGA-MAFIA_fpga_mafia_pr559
-FPGA-MAFIA_fpga_mafia_pr638
-FPGA-MAFIA_fpga_mafia_pr646
-FPGA-MAFIA_fpga_mafia_pr655
-FPGA-MAFIA_fpga_mafia_pr680
-gtaylormb_opl3_fpga_pr51
-hdl-util_hdmi_pr15
-hdl-util_hdmi_pr16
-hdl-util_hdmi_pr20
-hdl-util_hdmi_pr21
-hdl-util_hdmi_pr22
-hdl-util_hdmi_pr23
-hdl-util_hdmi_pr28
-hdl-util_hdmi_pr29
-hdl-util_hdmi_pr30
-hdl-util_hdmi_pr34
-hdl-util_hdmi_pr44
-HiSA-Team_Simply-V_pr102
-HiSA-Team_Simply-V_pr108
-HiSA-Team_Simply-V_pr118
-HiSA-Team_Simply-V_pr129
-HiSA-Team_Simply-V_pr147
-HiSA-Team_Simply-V_pr166
-HiSA-Team_Simply-V_pr184
-HiSA-Team_Simply-V_pr48
-HiSA-Team_Simply-V_pr52
-HiSA-Team_Simply-V_pr68
-HiSA-Team_Simply-V_pr92
-IEEE-UCF_Gaming-CPU-Project_pr42
-jotego_jt12_pr64
-jotego_jtcores_pr1021
-jotego_jtcores_pr1069
-jotego_jtcores_pr1077
-jotego_jtcores_pr1087
-jotego_jtcores_pr1089
-jotego_jtcores_pr1097
-jotego_jtcores_pr1100
-jotego_jtcores_pr1101
-jotego_jtcores_pr1108
-jotego_jtcores_pr1111
-jotego_jtcores_pr1167
-jotego_jtcores_pr1169
-jotego_jtcores_pr1177
-jotego_jtcores_pr1182
-jotego_jtcores_pr1191
-jotego_jtcores_pr1193
-jotego_jtcores_pr1202
-jotego_jtcores_pr1205
-jotego_jtcores_pr1228
-jotego_jtcores_pr1229
-jotego_jtcores_pr1235
-jotego_jtcores_pr1242
-jotego_jtcores_pr1248
-jotego_jtcores_pr1252
-jotego_jtcores_pr1260
-jotego_jtcores_pr1265
-jotego_jtcores_pr1270
-jotego_jtcores_pr1279
-jotego_jtcores_pr1290
-jotego_jtcores_pr1316
-jotego_jtcores_pr623
-jotego_jtcores_pr630
-jotego_jtcores_pr634
-jotego_jtcores_pr654
-jotego_jtcores_pr797
-jotego_jtcores_pr852
-jotego_jtcores_pr854
-jotego_jtcores_pr855
-jotego_jtcores_pr863
-jotego_jtcores_pr871
-jotego_jtcores_pr875
-jotego_jtcores_pr893
-jotego_jtcores_pr951
-jotego_jtcores_pr960
-KestrelComputer_polaris_pr21
-KestrelComputer_polaris_pr22
-kumarrishav14_AMBA_APB_pr18
-Lampro-Mellon_LM-RISCV-DV_pr81
-lnis-uofu_OpenFPGA_pr2164
-lowRISC_ibex_pr1821
-lowRISC_ibex_pr1839
-lowRISC_ibex_pr1865
-lowRISC_ibex_pr1872
-lowRISC_ibex_pr1917
-lowRISC_ibex_pr2166
-lowRISC_ibex_pr2214
-lowRISC_ibex_pr2241
-lowRISC_ibex_pr2251
-lowRISC_ibex_pr2261
-lowRISC_ibex_pr2269
-lowRISC_opentitan_pr28469
-lowRISC_opentitan_pr28698
-merledu_azadi-soc_pr10
-merledu_azadi-soc_pr14
-merledu_azadi-soc_pr2
-merledu_azadi-soc_pr5
-microsoft_cheriot-ibex_pr81
-mist-devel_nes_pr4
-MiSTer-devel_ao486_MiSTer_pr118
-MiSTer-devel_ao486_MiSTer_pr172
-MiSTer-devel_ao486_MiSTer_pr185
-MiSTer-devel_ao486_MiSTer_pr188
-MiSTer-devel_ao486_MiSTer_pr72
-MiSTer-devel_Arcade-Robotron_MiSTer_pr25
-MiSTer-devel_C64_MiSTer_pr142
-MiSTer-devel_Gameboy_MiSTer_pr216
-MiSTer-devel_Gameboy_MiSTer_pr240
-MiSTer-devel_Gameboy_MiSTer_pr52
-MiSTer-devel_Genesis_MiSTer_pr144
-MiSTer-devel_Genesis_MiSTer_pr160
-MiSTer-devel_MegaDrive_MiSTer_pr58
-MiSTer-devel_NES_MiSTer_pr121
-MiSTer-devel_NES_MiSTer_pr132
-MiSTer-devel_NES_MiSTer_pr135
-MiSTer-devel_NES_MiSTer_pr147
-MiSTer-devel_NES_MiSTer_pr187
-MiSTer-devel_NES_MiSTer_pr436
-MiSTer-devel_NES_MiSTer_pr438
-MiSTer-devel_NES_MiSTer_pr441
-MiSTer-devel_NES_MiSTer_pr448
-MiSTer-devel_S32X_MiSTer_pr42
-MiSTer-devel_S32X_MiSTer_pr44
-MiSTer-devel_Saturn_MiSTer_pr249
-MiSTle-Dev_MiSTeryNano_pr99
-MPSU_APS_pr98
-Multimedia-Processing_Digital-Logic-Design_pr46
-Multimedia-Processing_Digital-Logic-Design_pr48
-Multimedia-Processing_Digital-Logic-Design_pr50
-Multimedia-Processing_Digital-Logic-Design_pr60
-Multimedia-Processing_Digital-Logic-Design_pr62
-Multimedia-Processing_Digital-Logic-Design_pr65
-Multimedia-Processing_Digital-Logic-Design_pr68
-muneeb-mbytes_pulpino__spi_master__ip_verification_pr27
-muneeb-mbytes_pulpino__spi_master__ip_verification_pr32
-muneeb-mbytes_pulpino__spi_master__ip_verification_pr36
-muneeb-mbytes_pulpino__spi_master__ip_verification_pr39
-muneeb-mbytes_pulpino__spi_master__ip_verification_pr42
-muneeb-mbytes_pulpino__spi_master__ip_verification_pr50
-muneeb-mbytes_pulpino__spi_master__ip_verification_pr53
-muneeb-mbytes_pulpino__spi_master__ip_verification_pr56
-muneeb-mbytes_pulpino__spi_master__ip_verification_pr58
-muneeb-mbytes_pulpino__spi_master__ip_verification_pr61
-muneeb-mbytes_pulpino__spi_master__ip_verification_pr63
-muneeb-mbytes_pulpino__spi_master__ip_verification_pr68
-muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr18
-muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr23
-muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr25
-muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28
-muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr29
-muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr31
-nand2mario_nestang_pr75
-olofk_serv_pr105
-olofk_serv_pr107
-olofk_serv_pr109
-olofk_serv_pr114
-olofk_serv_pr90
-openhwgroup_core-v-verif_pr2585
-openhwgroup_core-v-xif_pr139
-openhwgroup_core-v-xif_pr167
-openhwgroup_cv32e40p_pr665
-openhwgroup_cv32e40s_pr254
-openhwgroup_cv32e40s_pr259
-openhwgroup_cv32e40s_pr263
-openhwgroup_cv32e40x_pr894
-openhwgroup_cv32e41p_pr15
-openhwgroup_cva5_pr29
-openhwgroup_cva5_pr7
-openhwgroup_cve2_pr118
-openhwgroup_cve2_pr139
-openhwgroup_cve2_pr152
-openhwgroup_cve2_pr180
-openhwgroup_cvfpu_pr114
-openhwgroup_cvfpu_pr116
-openhwgroup_cvfpu_pr125
-openhwgroup_cvfpu_pr140
-openhwgroup_cvfpu_pr147
-openhwgroup_cvfpu_pr87
-openhwgroup_cv-hpdcache_pr119
-openhwgroup_cv-hpdcache_pr33
-openhwgroup_cv-hpdcache_pr38
-openhwgroup_cv-hpdcache_pr48
-openhwgroup_cvw_pr1554
-openhwgroup_cvw_pr1555
-OpenPOWERFoundation_a2o_pr18
-openrisc_mor1kx_pr110
-openrisc_mor1kx_pr54
-opensocdebug_osd-hw_pr50
-Panda-Cores_PandaZero_pr14
-Panda-Cores_PandaZero_pr3
-Panda-Cores_PandaZero_pr4
-Panda-Cores_PandaZero_pr7
-PeterMonsson_sv_waveterm_pr10
-pezy-computing_pzbcm_pr2
-phanrahan_mantle_pr92
-projf_projf-explore_pr173
-projf_projf-explore_pr86
-pulp-platform_apb_pr1
-pulp-platform_apb_pr10
-pulp-platform_apb_pr2
-pulp-platform_apb_pr3
-pulp-platform_apb_pr4
-pulp-platform_apb_pr7
-pulp-platform_apb_pr8
-pulp-platform_axi_pr138
-pulp-platform_axi_pr185
-pulp-platform_axi_pr224
-pulp-platform_axi_pr228
-pulp-platform_axi_pr245
-pulp-platform_axi_pr293
-pulp-platform_axi_pr74
-pulp-platform_axi_riscv_atomics_pr1
-pulp-platform_axi_riscv_atomics_pr12
-pulp-platform_axi_riscv_atomics_pr13
-pulp-platform_axi_riscv_atomics_pr15
-pulp-platform_axi_riscv_atomics_pr17
-pulp-platform_axi_riscv_atomics_pr18
-pulp-platform_axi_riscv_atomics_pr22
-pulp-platform_axi_riscv_atomics_pr23
-pulp-platform_axi_riscv_atomics_pr26
-pulp-platform_axi_riscv_atomics_pr27
-pulp-platform_axi_riscv_atomics_pr28
-pulp-platform_axi_riscv_atomics_pr31
-pulp-platform_axi_riscv_atomics_pr33
-pulp-platform_axi_riscv_atomics_pr35
-pulp-platform_axi_riscv_atomics_pr37
-pulp-platform_axi_riscv_atomics_pr38
-pulp-platform_axi_riscv_atomics_pr39
-pulp-platform_carfield_pr41
-pulp-platform_cheshire_pr189
-pulp-platform_cheshire_pr203
-pulp-platform_clic_pr7
-pulp-platform_common_cells_pr132
-pulp-platform_common_cells_pr151
-pulp-platform_common_cells_pr155
-pulp-platform_common_cells_pr170
-pulp-platform_common_cells_pr182
-pulp-platform_common_cells_pr188
-pulp-platform_common_cells_pr222
-pulp-platform_common_cells_pr224
-pulp-platform_common_cells_pr225
-pulp-platform_common_cells_pr228
-pulp-platform_common_cells_pr230
-pulp-platform_common_cells_pr236
-pulp-platform_common_cells_pr240
-pulp-platform_common_cells_pr242
-pulp-platform_common_cells_pr247
-pulp-platform_common_cells_pr257
-pulp-platform_common_cells_pr262
-pulp-platform_common_cells_pr280
-pulp-platform_common_cells_pr93
-pulp-platform_common_verification_pr10
-pulp-platform_common_verification_pr5
-pulp-platform_common_verification_pr6
-pulp-platform_fpu_div_sqrt_mvp_pr16
-pulp-platform_fpu_div_sqrt_mvp_pr18
-pulp-platform_gpio_pr2
-pulp-platform_hci_pr27
-pulp-platform_hci_pr37
-pulp-platform_hci_pr67
-pulp-platform_neureka_pr30
-pulp-platform_pulpissimo_pr233
-pulp-platform_pulp_soc_pr23
-pulp-platform_pulp_soc_pr41
-pulp-platform_pulp_soc_pr54
-pulp-platform_pulp_soc_pr69
-pulp-platform_pulp_soc_pr73
-pulp-platform_pulp_soc_pr95
-pulp-platform_redundancy_cells_pr18
-pulp-platform_register_interface_pr17
-pulp-platform_register_interface_pr21
-pulp-platform_register_interface_pr24
-pulp-platform_register_interface_pr26
-pulp-platform_register_interface_pr30
-pulp-platform_register_interface_pr31
-pulp-platform_register_interface_pr32
-pulp-platform_register_interface_pr33
-pulp-platform_register_interface_pr34
-pulp-platform_register_interface_pr35
-pulp-platform_register_interface_pr36
-pulp-platform_register_interface_pr38
-pulp-platform_register_interface_pr39
-pulp-platform_register_interface_pr40
-pulp-platform_register_interface_pr46
-pulp-platform_register_interface_pr48
-pulp-platform_register_interface_pr54
-pulp-platform_register_interface_pr55
-pulp-platform_riscv-dbg_pr123
-pulp-platform_riscv-dbg_pr145
-pulp-platform_riscv-dbg_pr155
-pulp-platform_riscv-dbg_pr169
-pulp-platform_riscv-dbg_pr53
-pulp-platform_riscv-dbg_pr56
-pulp-platform_riscv-dbg_pr70
-pulp-platform_riscv-dbg_pr79
-pulp-platform_riscv-dbg_pr89
-pulp-platform_riscv-dbg_pr90
-pulp-platform_riscv-dbg_pr93
-pulp-platform_snitch_pr259
-pulp-platform_snitch_pr388
-pulp-platform_snitch_pr394
-pulp-platform_snitch_pr436
-pulp-platform_tech_cells_generic_pr22
-pulp-platform_tech_cells_generic_pr26
-pulp-platform_tech_cells_generic_pr27
-pulp-platform_tech_cells_generic_pr29
-pulp-platform_tech_cells_generic_pr30
-pulp-platform_udma_i2s_pr5
-rggen_rggen-sv-rtl_pr10
-rggen_rggen-sv-rtl_pr4
-secworks_aes_pr16
-semify-eda_waveform-generator_pr13
-SpiNNakerManchester_spif_pr8
-SpiNNakerManchester_spio_pr40
-squared-studio_common_pr118
-StanfordVLSI_dragonphy2_pr122
-StanfordVLSI_dragonphy2_pr126
-StanfordVLSI_dragonphy2_pr141
-StanfordVLSI_dragonphy2_pr90
-StanfordVLSI_dragonphy2_pr94
-svunit_svunit_pr110
-svunit_svunit_pr113
-svunit_svunit_pr114
-svunit_svunit_pr197
-taichi-ishitani_tvip-apb_pr5
-taichi-ishitani_tvip-axi_pr20
-taichi-ishitani_tvip-axi_pr44
-taichi-ishitani_tvip-axi_pr50
-taichi-ishitani_tvip-common_pr4
-UTOSS_risc-v_pr107
-UTOSS_risc-v_pr114
-UTOSS_risc-v_pr115
-UTOSS_risc-v_pr127
-UTOSS_risc-v_pr128
-UTOSS_risc-v_pr132
-UTOSS_risc-v_pr134
-UTOSS_risc-v_pr138
-UTOSS_risc-v_pr23
-UTOSS_risc-v_pr25
-UTOSS_risc-v_pr42
-UTOSS_risc-v_pr48
-UTOSS_risc-v_pr50
-UTOSS_risc-v_pr54
-UTOSS_risc-v_pr59
-UTOSS_risc-v_pr63
-UTOSS_risc-v_pr70
-UTOSS_risc-v_pr77
-UTOSS_risc-v_pr79
-UTOSS_risc-v_pr80
-UTOSS_risc-v_pr81
-UTOSS_risc-v_pr83
-UTOSS_risc-v_pr85
-UTOSS_risc-v_pr95
-UTOSS_risc-v_pr97
-va7deo_zerowing_pr17
-verilator_verilator_pr6552
-verilator_verilator_pr6573
-verilator_verilator_pr6583
-verilator_verilator_pr6596
-verilator_verilator_pr6630
-verilator_verilator_pr6631
-verilator_verilator_pr6668
-verilator_verilator_pr6697
-verilator_verilator_pr6723
-verilator_verilator_pr6737
-verilator_verilator_pr6815
-verilator_verilator_pr6822
-verilator_verilator_pr6823
-verilator_verilator_pr6833
-verilator_verilator_pr6842
-verilator_verilator_pr6861
-verilator_verilator_pr6870
-verilator_verilator_pr6876
-verilator_verilator_pr6882
-wallento_wb2axi_pr4
-Wren6991_Hazard3_pr23
-Wren6991_Hazard3_pr28
-Wren6991_Hazard3_pr41
-xlsynth_bedrock-rtl_pr766
-xlsynth_bedrock-rtl_pr785
-xlsynth_bedrock-rtl_pr917
-YosysHQ_nerv_pr14
-YosysHQ_picorv32_pr229
-YosysHQ_picorv32_pr244
-YosysHQ_picorv32_pr9
-zephray_VerilogBoy_pr30
-ZipCPU_wb2axip_pr71
+Toolchain: set $OSS_CAD_SUITE (or have verilator/surelog on PATH). No absolute machine paths.
+Excluded: .git, verilator obj_dir/build artifacts, surelog parse caches, broken symlinks.

patches/AsFigo_pyslint_pr169.patch

@@ -0,0 +1,339 @@
+From 1a7b82db803fd2da9e3255d5b6a2322084392d12 Mon Sep 17 00:00:00 2001
+From: Srinivasan Venkataramanan <svenka3@gmail.com>
+Date: Wed, 6 Dec 2023 18:45:52 +0000
+Subject: [PATCH] Added rule for #159
+
+---
+ exec_dir/Makefile            |   1 +
+ exec_dir/pyslint.log         | 143 +++++++++++++++++++++++++++++++++++
+ py_src/pyslint.py            |  54 ++++++++++++-
+ sv_tests/test_issue_159_f.sv |  25 ++++++
+ sv_tests/test_issue_160_f.sv |  12 +++
+ 5 files changed, 234 insertions(+), 1 deletion(-)
+ create mode 100644 sv_tests/test_issue_159_f.sv
+
+diff --git a/exec_dir/Makefile b/exec_dir/Makefile
+index acff2bd..52aaddb 100644
+--- a/exec_dir/Makefile
++++ b/exec_dir/Makefile
+@@ -95,6 +95,7 @@ naming:
+ 	python3 ../py_src/pyslint.py -t ../sv_tests/test_issue_150_f.sv >> pyslint.log
+ 	python3 ../py_src/pyslint.py -t ../sv_tests/test_issue_151_f.sv >> pyslint.log
+ 	python3 ../py_src/pyslint.py -t ../sv_tests/test_issue_152_f.sv >> pyslint.log
++	python3 ../py_src/pyslint.py -t ../sv_tests/test_issue_159_f.sv >> pyslint.log
+ 	python3 ../py_src/pyslint.py -t ../sv_tests/test_issue_160_f.sv >> pyslint.log
+ 	python3 ../py_src/pyslint.py -t ../sv_tests/test_issue_161_f.sv >> pyslint.log
+ 	python3 ../py_src/pyslint.py -t ../sv_tests/test_issue_162_f.sv >> pyslint.log
+diff --git a/exec_dir/pyslint.log b/exec_dir/pyslint.log
+index 9dcba2d..e65fff7 100644
+--- a/exec_dir/pyslint.log
++++ b/exec_dir/pyslint.log
+@@ -126,6 +126,71 @@ PySlint: Violation: [COMPAT_SVA_NO_DEGEN_CONSEQ]: Empty match ([*0] or variants)
+     (a |-> a[*0:3])
+ PySlint: Violation: [FUNC_SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: 
+   a_p_empty_sequence_2 : assert property (empty_sequence_2);
++PySlint: Violation: [DBG_AVOID_BEGIN_IN_FN]: A function with begin..end was found.
++	 This is likely a legacy Verilog coding syle as SystemVerilog 
++	 makes this optional and it is recommended coding style to avoid begin..end 
++	 inside function to improve readability and maintainability of codebase.
++	 Please remove the redundant begin..end 
++ // p_WidDepthComb
++//------------------------------------------------------------------------------
++// INDEX:   5) Verilog Functions
++//------------------------------------------------------------------------------
++  // INDEX:        - CheckBurst
++  // =====
++  // Inputs: Burst (burst data structure)
++  //         Count (number of data items)
++  // Returns: High is any of the write strobes are illegal
++  // Calls CheckStrb to test each WSTRB value.
++  //------------------------------------------------------------------------------
++  function CheckBurst
++PySlint: Violation: [DBG_AVOID_BEGIN_IN_FN]: A function with begin..end was found.
++	 This is likely a legacy Verilog coding syle as SystemVerilog 
++	 makes this optional and it is recommended coding style to avoid begin..end 
++	 inside function to improve readability and maintainability of codebase.
++	 Please remove the redundant begin..end 
++ // CheckBurst
++  // INDEX:        - CheckStrb
++  // =====
++  function CheckStrb
++PySlint: Violation: [DBG_AVOID_BEGIN_IN_FN]: A function with begin..end was found.
++	 This is likely a legacy Verilog coding syle as SystemVerilog 
++	 makes this optional and it is recommended coding style to avoid begin..end 
++	 inside function to improve readability and maintainability of codebase.
++	 Please remove the redundant begin..end 
++ // CheckStrb
++  // INDEX:        - ReadDataMask
++  // =====
++  // Inputs: Burst (Burst data structure)
++  //         Beat  (Data beat number)
++  // Returns: Read data mask for valid byte lanes.
++  //------------------------------------------------------------------------------
++  function [DATA_MAX:0] ReadDataMask
++PySlint: Violation: [DBG_AVOID_BEGIN_IN_FN]: A function with begin..end was found.
++	 This is likely a legacy Verilog coding syle as SystemVerilog 
++	 makes this optional and it is recommended coding style to avoid begin..end 
++	 inside function to improve readability and maintainability of codebase.
++	 Please remove the redundant begin..end 
++ // ReadDataMask
++  // INDEX:        - ByteShift
++  // =====
++  // Inputs: Burst (Burst data structure)
++  //         Beat  (Data beat number)
++  // Returns: Byte Shift for valid byte lanes.
++  //------------------------------------------------------------------------------
++  function [DATA_MAX:0] ByteShift
++PySlint: Violation: [DBG_AVOID_BEGIN_IN_FN]: A function with begin..end was found.
++	 This is likely a legacy Verilog coding syle as SystemVerilog 
++	 makes this optional and it is recommended coding style to avoid begin..end 
++	 inside function to improve readability and maintainability of codebase.
++	 Please remove the redundant begin..end 
++ // ByteShift
++  // INDEX:        - ByteCount
++  // =====
++  // Inputs: Burst (Burst data structure)
++  //         Beat  (Data beat number)
++  // Returns: Byte Count of valid byte lanes.
++  //------------------------------------------------------------------------------
++  function [7:0] ByteCount
+ PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_AWADDR_BOUNDARY: expected prefix: p_
+ PySlint: Violation: [DBG_SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_AWADDR_BOUNDARY
+ PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_awaddr_boundary: expected prefix: a_
+@@ -939,6 +1004,17 @@ PySlint: Violation: [COMPAT_DPI_NO_MDA]: DPI method with Multi-Dimensional Array
+ 	While LRM allows this, some tools do not fully support. To avoid compatibility issues, 
+ 	please remodel the code:
+   import "DPI-C" task bad_dpi_t_mda(input int dyn_a[][]);
++PySlint: Violation: [COMPAT_NO_REF_IN_STATIC_FN]: A function with 'ref' argument was found. 
++	 IEEE 1800 LRM requires such functions to be declared automatic. Some tools do not check 
++	 this rule strictly leading to incompatible code. Add keyword 'automatic' before the 
++	 function name or remove the 'ref' qualifier to the argument.
++  function  bad_fn (integer a[], ref ab)
++PySlint: Violation: [COMPAT_NO_REF_IN_STATIC_FN]: A function with 'ref' argument was found. 
++	 IEEE 1800 LRM requires such functions to be declared automatic. Some tools do not check 
++	 this rule strictly leading to incompatible code. Add keyword 'automatic' before the 
++	 function name or remove the 'ref' qualifier to the argument.
++ 
++  function  func (ref integer a[])
+ PySlint: Violation: [DBG_AVOID_BEGIN_IN_TASK]: A task with begin..end was found.
+ 	 This is likely a legacy Verilog coding syle as SystemVerilog 
+ 	 makes this optional and it is recommended coding style to avoid begin..end 
+@@ -946,6 +1022,13 @@ PySlint: Violation: [DBG_AVOID_BEGIN_IN_TASK]: A task with begin..end was found.
+ 	 Please remove the redundant begin..end 
+ 
+   task t1_bad()
++PySlint: Violation: [DBG_AVOID_BEGIN_IN_FN]: A function with begin..end was found.
++	 This is likely a legacy Verilog coding syle as SystemVerilog 
++	 makes this optional and it is recommended coding style to avoid begin..end 
++	 inside function to improve readability and maintainability of codebase.
++	 Please remove the redundant begin..end 
++ 
++  function bad_f ()
+ PySlint: Violation: [FUNC_NO_BEGIN_IN_TIMING_CTRL]: A task with TimingControl like @(posedge clk) was
+ 	 found along with a 'begin..end'
+ 	 This is likely a typo-error and may lead to unexpected behaviour of the BFM code. 
+@@ -953,6 +1036,66 @@ PySlint: Violation: [FUNC_NO_BEGIN_IN_TIMING_CTRL]: A task with TimingControl li
+ task Write()
+ 	 Relevant code snippet: 
+   @(negedge pclk) begin     psel = 1;
++PySlint: Violation: [NAME_CLASS_SUFFIX]: Improper naming of identifier:  reg_item: expected suffix: _c
++PySlint: Violation: [CL_METHOD_NOT_EXTERN]: method is not declared extern:  print
++PySlint: Violation: [DBG_CL_MISSING_ENDLABEL]: Missing End Label for class: reg_item
++PySlint: Violation: [NAME_CLASS_SUFFIX]: Improper naming of identifier:  driver: expected suffix: _c
++PySlint: Violation: [CL_METHOD_NOT_EXTERN]: method is not declared extern:  run
++PySlint: Violation: [DBG_CL_MISSING_ENDLABEL]: Missing End Label for class: driver
++PySlint: Violation: [VLT_NO_GENERIC_MBX]: A generic mailbox declaration was found. 
++	 While IEEE 1800 LRM allows this, such usage is error-prone and harder to debug. 
++	 Verilator does not support this feature. Please use typed mailbox such as: 'mailbox #(int) in_box;'
++  mailbox drv_mbx;
++PySlint: Violation: [NAME_CLASS_SUFFIX]: Improper naming of identifier:  monitor: expected suffix: _c
++PySlint: Violation: [CL_METHOD_NOT_EXTERN]: method is not declared extern:  run
++PySlint: Violation: [DBG_CL_MISSING_ENDLABEL]: Missing End Label for class: monitor
++PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file
++PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file
++PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file
++PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file
++PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file
++PySlint: Violation: [VLT_NO_GENERIC_MBX]: A generic mailbox declaration was found. 
++	 While IEEE 1800 LRM allows this, such usage is error-prone and harder to debug. 
++	 Verilator does not support this feature. Please use typed mailbox such as: 'mailbox #(int) in_box;'
++  mailbox scb_mbx;
++PySlint: Violation: [NAME_CLASS_SUFFIX]: Improper naming of identifier:  scoreboard: expected suffix: _c
++PySlint: Violation: [CL_METHOD_NOT_EXTERN]: method is not declared extern:  run
++PySlint: Violation: [DBG_CL_MISSING_ENDLABEL]: Missing End Label for class: scoreboard
++PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file
++PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file
++PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file
++PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file
++PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file
++PySlint: Violation: [VLT_NO_GENERIC_MBX]: A generic mailbox declaration was found. 
++	 While IEEE 1800 LRM allows this, such usage is error-prone and harder to debug. 
++	 Verilator does not support this feature. Please use typed mailbox such as: 'mailbox #(int) in_box;'
++  mailbox scb_mbx;
++PySlint: Violation: [NAME_CLASS_SUFFIX]: Improper naming of identifier:  env: expected suffix: _c
++PySlint: Violation: [CL_METHOD_NOT_EXTERN]: method is not declared extern:  run
++PySlint: Violation: [DBG_CL_MISSING_ENDLABEL]: Missing End Label for class: env
++PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file
++PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file
++PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file
++PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file
++PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file
++PySlint: Violation: [VLT_NO_GENERIC_MBX]: A generic mailbox declaration was found. 
++	 While IEEE 1800 LRM allows this, such usage is error-prone and harder to debug. 
++	 Verilator does not support this feature. Please use typed mailbox such as: 'mailbox #(int) in_box;' 		// Scoreboard connected to monitor
++  mailbox 			scb_mbx;
++PySlint: Violation: [NAME_CLASS_SUFFIX]: Improper naming of identifier:  test: expected suffix: _c
++PySlint: Violation: [CL_METHOD_NOT_EXTERN]: method is not declared extern:  run
++PySlint: Violation: [CL_METHOD_NOT_EXTERN]: method is not declared extern:  apply_stim
++PySlint: Violation: [DBG_CL_MISSING_ENDLABEL]: Missing End Label for class: test
++PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file
++PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file
++PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file
++PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file
++PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file
++PySlint: Violation: [VLT_NO_GENERIC_MBX]: A generic mailbox declaration was found. 
++	 While IEEE 1800 LRM allows this, such usage is error-prone and harder to debug. 
++	 Verilator does not support this feature. Please use typed mailbox such as: 'mailbox #(int) in_box;'
++  mailbox drv_mbx;
++PySlint: Violation: [REUSE_ONE_MOD_PER_FILE]: Always use one-module definition per file
+ PySlint: Violation: [VLT_NO_GENERIC_MBX]: A generic mailbox declaration was found. 
+ 	 While IEEE 1800 LRM allows this, such usage is error-prone and harder to debug. 
+ 	 Verilator does not support this feature. Please use typed mailbox such as: 'mailbox #(int) in_box;'
+diff --git a/py_src/pyslint.py b/py_src/pyslint.py
+index f350c7d..b200f65 100644
+--- a/py_src/pyslint.py
++++ b/py_src/pyslint.py
+@@ -43,6 +43,8 @@ def pyslint_update_rule_ids():
+   lv_sv_ruleid_l.append('FUNC_DPI_NO_4STATE_IN_ARGS')
+   lv_sv_ruleid_l.append('FUNC_NO_BEGIN_IN_TIMING_CTRL')
+   lv_sv_ruleid_l.append('DBG_AVOID_BEGIN_IN_TASK')
++  lv_sv_ruleid_l.append('DBG_AVOID_BEGIN_IN_FN')
++  lv_sv_ruleid_l.append('COMPAT_NO_REF_IN_STATIC_FN')
+   lv_sv_ruleid_l.append('COMPAT_DPI_NO_MDA')
+   lv_sv_ruleid_l.append('DBG_CL_MISSING_ENDLABEL')
+   lv_sv_ruleid_l.append('COMPAT_PRE_RAND_NON_VOID')
+@@ -908,7 +910,6 @@ def DBG_AVOID_BEGIN_IN_TASK(lv_cu_scope):
+         for lv_task_items_i in lv_mod_mem_i.items:
+           if (lv_task_items_i.kind.name == 'SequentialBlockStatement'):
+             lv_code_s = str(lv_mod_mem_i.prototype)
+-            lv_seq_s = str(lv_task_items_i)
+             msg = 'A task with begin..end was found.\n'
+             msg += '\t This is likely a legacy Verilog coding syle as SystemVerilog \n'
+             msg += '\t makes this optional and it is recommended'
+@@ -920,6 +921,55 @@ def DBG_AVOID_BEGIN_IN_TASK(lv_cu_scope):
+             lv_rule_id = 'DBG_AVOID_BEGIN_IN_TASK'
+             pyslint_msg(lv_rule_id, msg)
+ 
++def DBG_AVOID_BEGIN_IN_FN(lv_cu_scope):
++  if (lv_cu_scope.kind.name == 'ModuleDeclaration'):
++    for lv_mod_mem_i in lv_cu_scope.members:
++      if (lv_mod_mem_i.kind.name == 'FunctionDeclaration'):
++        for lv_task_items_i in lv_mod_mem_i.items:
++          if (lv_task_items_i.kind.name == 'SequentialBlockStatement'):
++            lv_code_s = str(lv_mod_mem_i.prototype)
++            msg = 'A function with begin..end was found.\n'
++            msg += '\t This is likely a legacy Verilog coding syle as SystemVerilog \n'
++            msg += '\t makes this optional and it is recommended'
++            msg += ' coding style to avoid begin..end \n'
++            msg += '\t inside function to improve readability and'
++            msg += ' maintainability of codebase.\n'
++            msg += '\t Please remove the redundant begin..end \n'
++            msg += lv_code_s
++            lv_rule_id = 'DBG_AVOID_BEGIN_IN_FN'
++            pyslint_msg(lv_rule_id, msg)
++
++def COMPAT_NO_REF_IN_STATIC_FN(lv_cu_scope):
++  if (lv_cu_scope.kind.name == 'ModuleDeclaration'):
++    for lv_mod_mem_i in lv_cu_scope.members:
++      if (lv_mod_mem_i.kind.name == 'FunctionDeclaration'):
++        lv_found_ref_arg = False
++        lv_code_s = str(lv_mod_mem_i.prototype)
++        if (not hasattr(lv_mod_mem_i.prototype.portList, 'ports')):
++          continue
++        for lv_fn_p_i in lv_mod_mem_i.prototype.portList.ports:
++          if (lv_fn_p_i.kind.name == 'FunctionPort'):
++            if (str(lv_fn_p_i.direction).strip() == 'ref'):
++              lv_found_ref_arg = True
++              break
++        if (lv_found_ref_arg and
++            str(lv_mod_mem_i.prototype.lifetime).strip() != 'automatic'):
++
++          msg = 'A function with \'ref\' argument was found. \n'
++          msg += '\t IEEE 1800 LRM requires such functions to be'
++          msg += ' declared automatic. Some tools do not check \n'
++          msg += '\t this rule strictly leading to incompatible code.'
++          msg += ' Add keyword \'automatic\' before the \n\t function'
++          msg += ' name or remove the \'ref\' qualifier to the argument.'
++          msg += lv_code_s
++          lv_rule_id = 'COMPAT_NO_REF_IN_STATIC_FN'
++          pyslint_msg(lv_rule_id, msg)
++
++
++        for lv_task_items_i in lv_mod_mem_i.items:
++          if (lv_task_items_i.kind.name == 'SequentialBlockStatement'):
++            lv_code_s = str(lv_mod_mem_i.prototype)
++
+ def COMPAT_SVA_NO_EXPECT_EXPR_IN_INIT(lv_cu_scope):
+   if (lv_cu_scope.kind.name == 'ModuleDeclaration'):
+     for lv_mod_mem_i in lv_cu_scope.members:
+@@ -1093,6 +1143,8 @@ def chk_naming(lv_cu_scope):
+   REUSE_ONE_MOD_PER_FILE(scope_i)
+   FUNC_NO_BEGIN_IN_TIMING_CTRL(scope_i)
+   DBG_AVOID_BEGIN_IN_TASK(scope_i)
++  DBG_AVOID_BEGIN_IN_FN(scope_i)
++  COMPAT_NO_REF_IN_STATIC_FN(scope_i)
+   VLT_NO_GENERIC_MBX(scope_i)
+   VLT_NO_CB_IN_INTF(scope_i)
+ 
+diff --git a/sv_tests/test_issue_159_f.sv b/sv_tests/test_issue_159_f.sv
+new file mode 100644
+index 0000000..4ee46a8
+--- /dev/null
++++ b/sv_tests/test_issue_159_f.sv
+@@ -0,0 +1,25 @@
++module x;
++  integer x1;
++
++  function  bad_fn (integer a[], ref ab);
++    $display ("%p", a);
++  endfunction
++ 
++  function  ok_fn (integer a[]);
++    $display ("%p", a);
++  endfunction
++ 
++  function  func (ref integer a[]);
++    $display ("%p", a);
++  endfunction
++ 
++  function automatic auto_func (ref integer a[]);
++    $display ("%p", a);
++  endfunction
++ 
++  initial begin
++    integer a [];
++    a = {1,2,3,4,5};
++    x1=func(a);
++  end
++endmodule 
+diff --git a/sv_tests/test_issue_160_f.sv b/sv_tests/test_issue_160_f.sv
+index 052f2d1..364ab5f 100644
+--- a/sv_tests/test_issue_160_f.sv
++++ b/sv_tests/test_issue_160_f.sv
+@@ -15,4 +15,16 @@ module m;
+     #100;
+   endtask : t1
+ 
++  function good_f ();
++    $display ("No extra begin..end");
++    $display ("In SV, no begin..end needed even for multiple line functions");
++  endfunction : good_f 
++
++  function bad_f ();
++  begin
++    $display ("Redundnant begin..end");
++    $display ("In SV, no begin..end needed even for multiple line functions");
++  end
++  endfunction : bad_f 
++
+ endmodule : m

patches/MiSTer-devel_MegaDrive_MiSTer_pr58.patch

@@ -0,0 +1,22 @@
+From 93a6c50e6bdc275aa2f115e16f7c0a7368576d1f Mon Sep 17 00:00:00 2001
+From: birdybro <kcoleman@misterfpga.co>
+Date: Sat, 8 Feb 2025 11:56:36 -0700
+Subject: [PATCH] Fix SMS Megadrive pad mapping
+
+---
+ rtl/pad_io.sv | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/rtl/pad_io.sv b/rtl/pad_io.sv
+index 43119ce..5acebd4 100644
+--- a/rtl/pad_io.sv
++++ b/rtl/pad_io.sv
+@@ -91,7 +91,7 @@ end
+ wire [5:0] pdata;
+ always @(posedge clk) begin
+ 	priority casex({SMS,JCNT,TH})
+-		4'b1XXX: pdata <= { ~P_B,     ~P_A, ~P_RIGHT, ~P_LEFT, ~P_DOWN, ~P_UP}; 
++		4'b1XXX: pdata <= { ~P_C,     ~P_B, ~P_RIGHT, ~P_LEFT, ~P_DOWN, ~P_UP}; 
+ 		4'b0100: pdata <= { ~P_START, ~P_A,   1'b0,     1'b0,    1'b0,   1'b0};
+ 		4'b0110: pdata <= { ~P_START, ~P_A,   1'b1,     1'b1,    1'b1,   1'b1};
+ 		4'b0111: pdata <= { ~P_C,     ~P_B, ~P_MODE,  ~P_X,    ~P_Y,    ~P_Z };

patches/MiSTer-devel_ao486_MiSTer_pr118.patch

@@ -0,0 +1,89 @@
+From de86b19ee01005b4a127fee43d46a7d2ec7cda97 Mon Sep 17 00:00:00 2001
+From: user7182 <96945402+user7182@users.noreply.github.com>
+Date: Sat, 30 Apr 2022 17:44:46 -0400
+Subject: [PATCH] sound: Updated the DSP write port status busy flag
+
+Previously the write port status busy flag was set on any DMA
+request, and then cleared when the software polled for the
+status. This caused problems with software using auto-init DMA
+because the busy flag may be reset by the new transfer before
+it polled a second time resulting in the DSP always returning
+busy.
+
+The logic was updated to instead use a fixed busy timer that
+clears independently from the software polling for status.
+---
+ rtl/soc/sound/sound.v     |  2 ++
+ rtl/soc/sound/sound_dsp.v | 30 +++++++++++-------------------
+ 2 files changed, 13 insertions(+), 19 deletions(-)
+
+diff --git a/rtl/soc/sound/sound.v b/rtl/soc/sound/sound.v
+index c560c8d..3f3f6d1 100644
+--- a/rtl/soc/sound/sound.v
++++ b/rtl/soc/sound/sound.v
+@@ -98,6 +98,8 @@ sound_dsp sound_dsp_inst
+ 
+ 	.clock_rate      (clk_rate),
+ 
++	.ce_1us          (ce_1us),
++
+ 	.irq8            (irq8),
+ 	.irq16           (irq16),
+ 
+diff --git a/rtl/soc/sound/sound_dsp.v b/rtl/soc/sound/sound_dsp.v
+index 7aac463..5fb1c33 100644
+--- a/rtl/soc/sound/sound_dsp.v
++++ b/rtl/soc/sound/sound_dsp.v
+@@ -31,7 +31,9 @@ module sound_dsp
+ 	input             clk,
+ 	input             rst_n,
+ 
+-	input      [27:0] clock_rate,
++	input      [27:0] clock_rate,
++
++	input             ce_1us,
+ 
+ 	output reg        irq8,
+ 	output reg        irq16,
+@@ -651,33 +653,23 @@ end
+ // To replicate the expected behavior the write port status will return busy when the
+ // register is read the first time following a DMA request, and on subsequent reads it will
+ // return idle.
+-localparam [1:0] S_WRITE_PORT_STATUS_IDLE = 2'd0;
+-localparam [1:0] S_WRITE_PORT_STATUS_BUSY = 2'd1;
+-localparam [1:0] S_WRITE_PORT_STATUS_IDLE_UNTIL_TIMER_RESET = 2'd2;
++localparam S_DSP_BUSY_DURATION = 1'd1;
+ 
+ // The fake busy signal communicates what the software using the sound card expects, and
+ // does not mean the DSP module is actually busy.
+-wire dsp_fake_busy = (dsp_busy_state > S_WRITE_PORT_STATUS_IDLE) && (dsp_busy_state < S_WRITE_PORT_STATUS_IDLE_UNTIL_TIMER_RESET);
+-wire write_port_status_reply = (io_read_valid && io_address == 4'hC);
++wire dsp_fake_busy = (dsp_busy_cnt > 0);
+ 
+-reg [1:0] dsp_busy_state;
++reg dsp_busy_cnt;
+ always @(posedge clk) begin
+-	if(rst_n == 1'b0)          dsp_busy_state <= S_WRITE_PORT_STATUS_IDLE;
+-	else if(sw_reset)          dsp_busy_state <= S_WRITE_PORT_STATUS_IDLE;
+-
+-	// Go back to idle anytime the DMA timer is about to finish, or is paused.
+-	else if(pause_dma)         dsp_busy_state <= S_WRITE_PORT_STATUS_IDLE;
+-	else if(!dma_in_progress)  dsp_busy_state <= S_WRITE_PORT_STATUS_IDLE;
+-	else if(dma_wait == 8'hFF) dsp_busy_state <= S_WRITE_PORT_STATUS_IDLE;
++	if(rst_n == 1'b0)                dsp_busy_cnt <= 0;
++	else if(sw_reset)                dsp_busy_cnt <= 0;
+ 
+-	// Stay busy for a single read, and then stay idle until a DMA request resets the state.
+-	else if(dsp_fake_busy && write_port_status_reply) begin
+-		dsp_busy_state <= dsp_busy_state + 1'd1;
+-	end
++	// Go back to idle after countdown reaches 0
++	else if(ce_1us && dsp_fake_busy) dsp_busy_cnt <= dsp_busy_cnt - 1'd1;
+ 
+ 	// Go busy when a DMA request is made.
+ 	else if(dma_req) begin
+-		dsp_busy_state <= S_WRITE_PORT_STATUS_BUSY;
++		dsp_busy_cnt <= S_DSP_BUSY_DURATION;
+ 	end
+ end
+ 

patches/MiSTle-Dev_MiSTeryNano_pr99.patch

@@ -0,0 +1,2002 @@
+From b49106ff70583a13d99d514506788bb76a5afcd8 Mon Sep 17 00:00:00 2001
+From: Pawel Karpinski <pawelka@gmail.com>
+Date: Mon, 15 Sep 2025 22:35:32 -0700
+Subject: [PATCH] add support for second usb joy and added mouse
+ disabling/enabling when joystick/mouse button is click. Add support to select
+ to which port USB JOY0 and USB JOY1 are mapped
+
+---
+ src/build.sh             |    4 +
+ src/misc/atarist.xml     |    4 +
+ src/misc/atarist_xml.hex | 1725 +++++++++++++++++++-------------------
+ src/misc/sysctrl.v       |    4 +
+ src/misterynano.sv       |   44 +-
+ 5 files changed, 923 insertions(+), 858 deletions(-)
+
+diff --git a/src/build.sh b/src/build.sh
+index b0048c4..90e4c3b 100755
+--- a/src/build.sh
++++ b/src/build.sh
+@@ -4,5 +4,9 @@ if [ "$#" -eq 1 ]; then
+     EXT=_$1
+ fi
+ 
++echo "Convert misc/atarist.xml to misc/atarist_xml.hex"
++cat misc/atarist.xml | gzip | xxd -p -c1 | unix2dos > misc/atarist_xml.hex
++
++
+ # run through grc to highlight NOTEs, WARNings and ERRORs
+ grc --config=gw_sh.grc gw_sh ./build${EXT}.tcl
+diff --git a/src/misc/atarist.xml b/src/misc/atarist.xml
+index f21a092..9ff670f 100644
+--- a/src/misc/atarist.xml
++++ b/src/misc/atarist.xml
+@@ -73,6 +73,10 @@
+ 	<listentry label="Atari ST" value="1"/>
+ 	<listentry label="Amiga" value="2"/>
+       </list>
++      <list label="USB Joy:" id="U" default="1">
++	<listentry label="Port0/Port1" value="0"/>
++	<listentry label="Port1/Port0" value="1"/>
++      </list>
+       <list label="TOS Slot:" id="T" default="0">
+ 	<listentry label="Primary" value="0"/>
+ 	<listentry label="Secondary" value="1"/>
+diff --git a/src/misc/atarist_xml.hex b/src/misc/atarist_xml.hex
+index 5dc6711..0e9d64c 100644
+--- a/src/misc/atarist_xml.hex
++++ b/src/misc/atarist_xml.hex
+@@ -1,962 +1,987 @@
+ 1f
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+ df
++eb
+ 8b
+-cb
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+-4f
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+ fc
+-ae
+-52
+-f6
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++03
++34
++dc
++8f
++68
++04
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+ 00
+ 00
+diff --git a/src/misc/sysctrl.v b/src/misc/sysctrl.v
+index 6df24c2..e84ed16 100644
+--- a/src/misc/sysctrl.v
++++ b/src/misc/sysctrl.v
+@@ -46,6 +46,7 @@ module sysctrl (
+   output reg [1:0]  system_floppy_wprot,
+   output reg	    system_cubase_en,
+   output reg [1:0]  system_port_mouse,
++  output reg [1:0]  system_port_joy,
+   output reg	    system_tos_slot
+ );
+ 
+@@ -118,6 +119,7 @@ always @(posedge clk) begin
+       system_floppy_wprot <= 2'b00; // floppy not write protected
+       system_cubase_en <= 1'b0;     // no cubase dongle
+       system_port_mouse <= 2'b00;   // mouse on usb -> db9 joystick
++      system_port_joy <= 1'b1;
+       system_tos_slot <= 1'b0;      // primary tos slot
+    end else begin // if (reset)
+       //  bring button state into local clock domain
+@@ -209,6 +211,8 @@ always @(posedge clk) begin
+                     if(id == "Q") system_cubase_en <= data_in[0];
+                     // Value "J": USB Mouse(0), DB9/Atari ST(1) or DB9/Amiga(2)
+                     if(id == "J") system_port_mouse <= data_in[1:0];
++                    // Value "U": USB Joy, Port0/Port1 or Port1/Port0 mapping order
++                    if(id == "U") system_port_joy <= data_in[0];
+                     // Value "T": Primary(0) TOS slot or Secondary(1)
+                     if(id == "T") system_tos_slot <= data_in[0];
+                 end
+diff --git a/src/misterynano.sv b/src/misterynano.sv
+index c1cf8b3..ddf8f09 100644
+--- a/src/misterynano.sv
++++ b/src/misterynano.sv
+@@ -146,6 +146,7 @@ wire       system_wide_screen;
+ wire [1:0] system_floppy_wprot;
+ wire       system_cubase_en;
+ wire [1:0] system_port_mouse;
++wire       system_port_joy;
+ wire       system_tos_slot;
+    
+ /* -------------- clock generation --------------- */
+@@ -320,23 +321,49 @@ mcu_spi mcu (
+ // joy0 is usually used for the mouse, joy1 for the joystick. The
+ // joystick can either be driven from the external MCU or via FPGA IO pins
+ wire [5:0] hid_mouse;   // USB/HID mouse with four directions and two buttons
+-wire [7:0] hid_joy;     // USB/HID joystick with four directions and four buttons
++wire [7:0] hid_joy0;     // USB/HID joystick with four directions and four buttons
++wire [7:0] hid_joy1;     // USB/HID joystick with four directions and four buttons
+ 
+ // external DB9 joystick port
+ wire [5:0] db9_atari = { !io[5], !io[0], !io[2], !io[1], !io[4], !io[3] };
+ wire [5:0] db9_amiga = { !io[5], !io[0], !io[3], !io[1], !io[4], !io[2] };
+ 
++// joy0 (port0) can be mouse or joystick. If mouse is connected it cannot work with parallel
++// so mouse is deactivted if joystick button is detected in this case usb joy, but after adding 
++// second db9 it can by added to joy0_joy. Mouse is activated when mouse button is added.
++wire [5:0] joy0_mouse = ((system_port_mouse == 2'd0)?hid_mouse:
++                  (system_port_mouse == 2'd1)? db9_atari:
++                  (system_port_mouse == 2'd2) ? db9_amiga:
++                  6'b000000); 
++wire [5:0] joy0_joy = ((system_port_joy == 1'd1) ? hid_joy0[5:0] : {1'd0, hid_joy1[4:0]});
++
++reg joy0_mouse_active;
++
++always @(posedge clk32) begin
++    if (por) begin
++        joy0_mouse_active = 1'b1;
++    end else begin
++        if (!joy0_mouse_active && (joy0_mouse[5] || joy0_mouse[4])) begin
++            joy0_mouse_active <= 1'b1;
++        end else begin
++            if (joy0_mouse_active && (joy0_joy[5] || joy0_joy[4])) begin
++                joy0_mouse_active <= 1'b0;
++            end
++        end
++    end
++end
++
+ // any db9 mouse replaces usb mouse as mice will keep some signals
+ // permanently active and can thus not just be wired together
+-wire [5:0] joy0 = (system_port_mouse == 2'd0)?hid_mouse:
+-                  (system_port_mouse == 2'd1)?db9_atari:
+-                  (system_port_mouse == 2'd2)?db9_amiga:
+-                  6'b000000;
++// add possibility to turn off mouse
++wire [5:0] joy0 =  joy0_joy | ((joy0_mouse_active) ? joy0_mouse : 6'b000000);
++
+ 
+ // Joystick ports are just wired together and can be used in parallel
+ // DB9 is used for joystick, whenever the mouse is mapped to USB
+ wire [5:0] db9_joy = (system_port_mouse==2'd0)?db9_atari: 6'b000000;
+-wire [4:0] joy1 = hid_joy[4:0] | db9_joy[4:0];
++
++wire [4:0] joy1 = ((system_port_joy == 1'd1) ? hid_joy1[4:0] : hid_joy0[4:0] ) | db9_joy[4:0];
+ 
+ // The keyboard matrix is maintained inside HID
+ wire [7:0] keyboard[14:0];
+@@ -383,8 +410,8 @@ hid hid (
+ 
+         .mouse(hid_mouse),
+         .keyboard(keyboard),
+-        .joystick0(hid_joy),
+-        .joystick1()
++        .joystick0(hid_joy1),
++        .joystick1(hid_joy0)
+          );   
+          
+ wire sdc_int;
+@@ -433,6 +460,7 @@ sysctrl sysctrl (
+         .system_wide_screen(system_wide_screen),
+         .system_floppy_wprot(system_floppy_wprot),
+         .system_port_mouse(system_port_mouse),
++        .system_port_joy(system_port_joy),
+         .system_tos_slot(system_tos_slot),
+         
+         .int_out_n(mcu_intn),

patches/UTOSS_risc-v_pr25.patch

@@ -0,0 +1,441 @@
+From 5190edf87bdcbfa51edd792b87f82be4f595e3c1 Mon Sep 17 00:00:00 2001
+From: MM871 <100428910+MM871@users.noreply.github.com>
+Date: Sun, 30 Mar 2025 14:53:14 -0400
+Subject: [PATCH 1/8] task 1 - instantiated instruction decoder in top.v
+
+---
+ CONTRIBUTORS.md |  1 +
+ src/top.v       | 34 ++++++++++++++++++++++++++++++++++
+ 2 files changed, 35 insertions(+)
+
+diff --git a/CONTRIBUTORS.md b/CONTRIBUTORS.md
+index ba9b207..327f2cd 100644
+--- a/CONTRIBUTORS.md
++++ b/CONTRIBUTORS.md
+@@ -6,3 +6,4 @@ Yuxuan Seah
+ Edward Wu (edwu0029)  
+ Brett(Jiaxin) Yang (brettyang02)  
+ Joonseo Park (joon2022park)
++Mihir Maringanti
+diff --git a/src/top.v b/src/top.v
+index e69de29..fb60b82 100644
+--- a/src/top.v
++++ b/src/top.v
+@@ -0,0 +1,34 @@
++module InstructionDecoder(
++
++    output [6:0]  op,     
++    output [2:0]  funct3, 
++    output [6:0]  funct7, 
++    output [4:0]  rs1, 
++    output [4:0] rs2.
++    output [4:0] rd, 
++    output [24:0] extend,
++    input [31:0] instr
++
++);
++
++assign op = instr[6:0];
++assign rd = instr[11:7];
++assign funct3 = instr[14:12];
++assign rs1 = instr[19:15];
++assign rs2 = instr[24:20];
++assign funct7 = instr[31:25];
++assign extend = instr[31:7];
++
++
++InstructionDecoder instance1 (
++
++    .instr(instr),
++    .rd(rd),
++    .funct3(funct3),
++    .rs1(rs1),
++    .rs2(rs2),
++    .funct7(funct7),
++    .extend(extend)
++);
++
++endmodule
+
+
+From 925cc8ad5b41492c09bbff7476398b585f9f3215 Mon Sep 17 00:00:00 2001
+From: MM871 <100428910+MM871@users.noreply.github.com>
+Date: Mon, 9 Jun 2025 18:25:28 -0400
+Subject: [PATCH 2/8] Update top.v
+
+instantiated MA and ID
+---
+ src/top.v | 101 +++++++++++++++++++++++++++++++++++++-----------------
+ 1 file changed, 69 insertions(+), 32 deletions(-)
+
+diff --git a/src/top.v b/src/top.v
+index fb60b82..dd1da0f 100644
+--- a/src/top.v
++++ b/src/top.v
+@@ -1,34 +1,71 @@
+-module InstructionDecoder(
+-
+-    output [6:0]  op,     
+-    output [2:0]  funct3, 
+-    output [6:0]  funct7, 
+-    output [4:0]  rs1, 
+-    output [4:0] rs2.
+-    output [4:0] rd, 
+-    output [24:0] extend,
+-    input [31:0] instr
+-
+-);
+-
+-assign op = instr[6:0];
+-assign rd = instr[11:7];
+-assign funct3 = instr[14:12];
+-assign rs1 = instr[19:15];
+-assign rs2 = instr[24:20];
+-assign funct7 = instr[31:25];
+-assign extend = instr[31:7];
+-
+-
+-InstructionDecoder instance1 (
+-
+-    .instr(instr),
+-    .rd(rd),
+-    .funct3(funct3),
+-    .rs1(rs1),
+-    .rs2(rs2),
+-    .funct7(funct7),
+-    .extend(extend)
+-);
++`include "src/types.svh"
++
++module top ( input wire clk
++           , input wire reset
++           );
++
++  wire cfsm__pc_update;
++  instr_t instr;
++
++  wire __tmp_AdrSrc
++     , __tmp_IRWrite
++     , __tmp_RegWrite
++     , __tmp_MemWrite
++     , __tmp_Branch;
++  wire [1:0] __tmp_ALUSrcA
++           , __tmp_ALUSrcB;
++  wire [2:0] __tmp_ALUOp;
++  wire [1:0] __tmp_ResultSrc;
++  wire [3:0] __tmp_FSMState;
++
++  ControlFSM control_fsm
++    ( .opcode    ( 7'b0000000      )
++    , .clk       ( clk             )
++    , .reset     ( reset           )
++    , .AdrSrc    ( __tmp_AdrSrc    )
++    , .IRWrite   ( __tmp_IRWrite   )
++    , .RegWrite  ( __tmp_RegWrite  )
++    , .PCUpdate  ( cfsm__pc_update )
++    , .MemWrite  ( __tmp_MemWrite  )
++    , .Branch    ( __tmp_Branch    )
++    , .ALUSrcA   ( __tmp_ALUSrcA   )
++    , .ALUSrcB   ( __tmp_ALUSrcB   )
++    , .ALUOp     ( __tmp_ALUOp     )
++    , .ResultSrc ( __tmp_ResultSrc )
++    , .FSMState  ( __tmp_FSMState  )
++    );
++
++  fetch fetch
++    ( .clk             ( clk             )
++    , .reset           ( reset           )
++    , .cfsm__pc_update ( cfsm__pc_update )
++    , .instr           ( instr           )
++    );
++
++  MA memory_access (
++      .A   (baseAddr),        //baseAddr is from Instruction_Decode.v it sounded like it matches with the module paramters in MA
++      .WD  (writeData),       //same as above
++      .WE  (MemWrite),        //same as above but from ControlFSM interacting with MA e.g. when memWrite = 1
++      .CLK (clk),
++      .RD  (ma__readdata)     //just left this because i dont think its connected to anything ?
++  );
++
++  Instruction_Decode instruction_decode (
++      .instr      (instr),
++      .clk        (clk),
++      .reset      (reset),
++      .ResultData (ResultData),   
++      .AdrSrc     (AdrSrc),
++      .IRWrite    (IRWrite),
++      .PCUpdate   (PCUpdate),     
++      .MemWrite   (MemWrite),
++      .Branch     (Branch),
++      .ALUSrcA    (ALUSrcA),
++      .ALUSrcB    (ALUSrcB),
++      .ResultSrc  (ResultSrc),
++      .ALUControl (ALUControl),
++      .baseAddr   (baseAddr),     
++      .writeData  (writeData)   
++  );
+ 
+ endmodule
+
+
+From 66f47d79fdfd837e04f96cf3c63afd863f430b96 Mon Sep 17 00:00:00 2001
+From: MM871 <100428910+MM871@users.noreply.github.com>
+Date: Sat, 12 Jul 2025 11:17:41 -0400
+Subject: [PATCH 3/8] muxes made and instantiated
+
+instantiated in bottom of top.v and created the module in a seperate file Mux.v
+---
+ src/Mux.v |  9 +++++++++
+ src/top.v | 21 +++++++++++++++++++++
+ 2 files changed, 30 insertions(+)
+ create mode 100644 src/Mux.v
+
+diff --git a/src/Mux.v b/src/Mux.v
+new file mode 100644
+index 0000000..b5b7ab3
+--- /dev/null
++++ b/src/Mux.v
+@@ -0,0 +1,9 @@
++module mux (
++  input  wire [31:0] input1,
++  input  wire [31:0] input0,
++  input  wire        sel,
++  output wire [31:0] out
++);
++  assign out = sel ? input1 : input0;
++endmodule
++
+diff --git a/src/top.v b/src/top.v
+index dd1da0f..c935ee1 100644
+--- a/src/top.v
++++ b/src/top.v
+@@ -68,4 +68,25 @@ module top ( input wire clk
+       .writeData  (writeData)   
+   );
+ 
++  mux pc (
++    .input0(PCPlus4),  
++    .input1(PCTarget),  
++    .sel(PCSrc),  
++    .out(PCNext)     
++  );
++
++  mux alu (
++    .input0(RD2),    
++    .input1(ImmExt),  
++    .sel(ALUSrc),   
++    .out(SrcB)
++  );
++
++  mux result (
++    .input0(ALUResult),
++    .input1(ReadData),
++    .sel(ResultSrc), 
++    .out(Result)
++  );
++
+ endmodule
+
+
+From 302df57c724afa1172faca6a6ef39b1a964609cb Mon Sep 17 00:00:00 2001
+From: MM871 <100428910+MM871@users.noreply.github.com>
+Date: Sat, 19 Jul 2025 17:26:31 -0400
+Subject: [PATCH 4/8] Tried case statements for muxes, feedback needed
+
+---
+ src/Mux.v |  9 ---------
+ src/top.v | 43 +++++++++++++++++++++++++------------------
+ 2 files changed, 25 insertions(+), 27 deletions(-)
+ delete mode 100644 src/Mux.v
+
+diff --git a/src/Mux.v b/src/Mux.v
+deleted file mode 100644
+index b5b7ab3..0000000
+--- a/src/Mux.v
++++ /dev/null
+@@ -1,9 +0,0 @@
+-module mux (
+-  input  wire [31:0] input1,
+-  input  wire [31:0] input0,
+-  input  wire        sel,
+-  output wire [31:0] out
+-);
+-  assign out = sel ? input1 : input0;
+-endmodule
+-
+diff --git a/src/top.v b/src/top.v
+index c935ee1..42083c2 100644
+--- a/src/top.v
++++ b/src/top.v
+@@ -68,25 +68,32 @@ module top ( input wire clk
+       .writeData  (writeData)   
+   );
+ 
+-  mux pc (
+-    .input0(PCPlus4),  
+-    .input1(PCTarget),  
+-    .sel(PCSrc),  
+-    .out(PCNext)     
+-  );
++  always @(*) begin
++   case (__tmp_ALUSrcA)
++      2'b00: alu_input_a = 32'd0;    
++      2'b01: alu_input_a = rs1;       
++      2'b10: alu_input_a = OldPC;     
++      default: alu_input_a = 32'hxxxxxxxx;
++    endcase
++  end
+ 
+-  mux alu (
+-    .input0(RD2),    
+-    .input1(ImmExt),  
+-    .sel(ALUSrc),   
+-    .out(SrcB)
+-  );
++  always @(*) begin
++   case (__tmp_ALUSrcB)
++      2'b00: alu_input_b = rs2;
++      2'b01: alu_input_b = 32'd4;
++      2'b10: alu_input_b = imm_ext;
++      default: alu_input_b = 32'hxxxxxxxx;
++    endcase
++  end
++
++  always @(*) begin
++   case (__tmp_ResultSrc)
++      2'b00: __tmp_ResultData = __tmp_ALUOut;
++      2'b01: __tmp_ResultData = Data;
++      2'b10: __tmp_ResultData = OldPC;
++      default: __tmp_ResultData = 32'hxxxxxxxx;
++    endcase
++  end
+ 
+-  mux result (
+-    .input0(ALUResult),
+-    .input1(ReadData),
+-    .sel(ResultSrc), 
+-    .out(Result)
+-  );
+ 
+ endmodule
+
+
+From d7335e1ecf8e5e3b5711de663297ad1eac188f52 Mon Sep 17 00:00:00 2001
+From: Boris <boris.potapov@mail.utoronto.ca>
+Date: Mon, 21 Jul 2025 00:38:12 +0000
+Subject: [PATCH 5/8] connect mux outputs to alu
+
+---
+ src/top.v | 7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+diff --git a/src/top.v b/src/top.v
+index c467b6d..8358ba9 100644
+--- a/src/top.v
++++ b/src/top.v
+@@ -15,6 +15,9 @@ module top ( input wire clk
+   data_t rs1;
+   data_t rs2;
+ 
++  data_t alu_input_a;
++  data_t alu_input_b;
++
+   wire alu__zero_flag;
+ 
+   wire __tmp_AdrSrc
+@@ -71,8 +74,8 @@ module top ( input wire clk
+     );
+ 
+   ALU alu
+-    ( .a              ( rs1              )
+-    , .b              ( rs2              )
++    ( .a              ( alu_input_a      )
++    , .b              ( alu_input_b      )
+     , .alu_control    ( __tmp_ALUControl )
+     , .out            ( __tmp_ALUOut     )
+     , .zeroE          ( alu__zero_flag   )
+
+From 3671bc34479e85061ecd1323bdc4ff2f4deb8ece Mon Sep 17 00:00:00 2001
+From: Boris <boris.potapov@mail.utoronto.ca>
+Date: Mon, 21 Jul 2025 00:42:04 +0000
+Subject: [PATCH 6/8] fix mux conditions
+
+---
+ src/top.v | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/src/top.v b/src/top.v
+index 8358ba9..dba8702 100644
+--- a/src/top.v
++++ b/src/top.v
+@@ -84,8 +84,8 @@ module top ( input wire clk
+   always @(*) begin
+     case (__tmp_ALUSrcA)
+       2'b00: alu_input_a = 32'd0;
+-      2'b01: alu_input_a = rs1;
+-      2'b10: alu_input_a = OldPC;
++      2'b01: alu_input_a = OldPC;
++      2'b10: alu_input_a = rs1;
+       default: alu_input_a = 32'hxxxxxxxx;
+     endcase
+   end
+@@ -93,8 +93,8 @@ module top ( input wire clk
+   always @(*) begin
+     case (__tmp_ALUSrcB)
+       2'b00: alu_input_b = rs2;
+-      2'b01: alu_input_b = 32'd4;
+-      2'b10: alu_input_b = imm_ext;
++      2'b01: alu_input_b = imm_ext;
++      2'b10: alu_input_b = 32'd4;
+       default: alu_input_b = 32'hxxxxxxxx;
+     endcase
+   end
+
+From 04c22a3b7500afe63ba347f22b77b46f70e572c1 Mon Sep 17 00:00:00 2001
+From: Boris <boris.potapov@mail.utoronto.ca>
+Date: Mon, 21 Jul 2025 00:47:57 +0000
+Subject: [PATCH 7/8] add missing registers
+
+---
+ src/top.v | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/src/top.v b/src/top.v
+index dba8702..25c0151 100644
+--- a/src/top.v
++++ b/src/top.v
+@@ -18,6 +18,9 @@ module top ( input wire clk
+   data_t alu_input_a;
+   data_t alu_input_b;
+ 
++  addr_t OldPC; // TODO: this will need to be moved into fetch module
++  data_t Data; // TODO: this will need to be moved into fetch module
++
+   wire alu__zero_flag;
+ 
+   wire __tmp_AdrSrc
+
+From 402d199bcaed788809335ab546f9982c269c1d12 Mon Sep 17 00:00:00 2001
+From: Boris <boris.potapov@mail.utoronto.ca>
+Date: Mon, 21 Jul 2025 00:48:41 +0000
+Subject: [PATCH 8/8] temporarily wire rs1 and 2 to alu directly
+
+---
+ src/top.v | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/src/top.v b/src/top.v
+index 25c0151..7fd5382 100644
+--- a/src/top.v
++++ b/src/top.v
+@@ -77,8 +77,8 @@ module top ( input wire clk
+     );
+ 
+   ALU alu
+-    ( .a              ( alu_input_a      )
+-    , .b              ( alu_input_b      )
++    ( .a              ( rs1              )
++    , .b              ( rs2              )
+     , .alu_control    ( __tmp_ALUControl )
+     , .out            ( __tmp_ALUOut     )
+     , .zeroE          ( alu__zero_flag   )

patches/UTOSS_risc-v_pr48.patch

@@ -0,0 +1,81 @@
+From 514e5c96766d6fd17bd1ea5b016d1a89b2515510 Mon Sep 17 00:00:00 2001
+From: Boris <boris.potapov@mail.utoronto.ca>
+Date: Tue, 29 Jul 2025 01:40:26 +0000
+Subject: [PATCH] add tb for or instruction
+
+---
+ test/or_tb.sv | 65 +++++++++++++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 65 insertions(+)
+ create mode 100644 test/or_tb.sv
+
+diff --git a/test/or_tb.sv b/test/or_tb.sv
+new file mode 100644
+index 0000000..b0b4414
+--- /dev/null
++++ b/test/or_tb.sv
+@@ -0,0 +1,65 @@
++`timescale 1ns/1ps
++
++`include "test/utils.svh"
++
++module or_tb;
++
++  reg clk;
++  reg reset;
++
++  top uut
++    ( .clk   ( clk   )
++    , .reset ( reset )
++    );
++
++  initial begin
++    clk = 0;
++    forever #5 clk = ~clk;
++  end
++
++  task wait_till_next_cfsm_state(input [5:0] expected_state);
++    @(posedge clk); #1;
++    `assert_equal(uut.control_fsm.current_state, expected_state)
++  endtask
++
++  initial begin
++    reset <= `TRUE;
++
++    uut.memory.M[0] = 32'h003160b3; // or x1,x2,x3 ; x1 = x2 | x3
++
++    uut.instruction_decode.instanceRegFile.RFMem[2] = 32'hf0f0f0f0; // x2
++    uut.instruction_decode.instanceRegFile.RFMem[3] = 32'h0b0b0b0b; // x3
++
++    wait_till_next_cfsm_state(uut.control_fsm.FETCH);
++
++    reset <= `FALSE;
++
++    wait_till_next_cfsm_state(uut.control_fsm.DECODE);
++
++    `assert_equal(uut.opcode, 7'b0110011)
++    `assert_equal(uut.instruction_decode.rd, 1)
++    `assert_equal(uut.instruction_decode.rs1, 2)
++    `assert_equal(uut.instruction_decode.rs2, 3)
++    `assert_equal(uut.instruction_decode.ALUControl, 4'b1000)
++
++    wait_till_next_cfsm_state(uut.control_fsm.EXECUTER);
++
++    `assert_equal(uut.alu.a,   32'hf0f0f0f0)
++    `assert_equal(uut.alu.b,   32'h0b0b0b0b)
++    `assert_equal(uut.alu.out, 32'hfbfbfbfb)
++
++    wait_till_next_cfsm_state(uut.control_fsm.ALUWB);
++
++    `assert_equal(uut.result, 32'hfbfbfbfb)
++
++    wait_till_next_cfsm_state(uut.control_fsm.FETCH);
++
++    `assert_equal(uut.instruction_decode.instanceRegFile.RFMem[1], 32'hfbfbfbfb)
++    `assert_equal(uut.fetch.pc_cur, 4)
++
++    $finish;
++  end
++
++  `SETUP_VCD_DUMP(or_tb)
++
++endmodule

patches/YosysHQ_picorv32_pr244.patch

@@ -0,0 +1,23 @@
+From de92ce54e8a3f24f2adc6b5d04de35e4edb873e5 Mon Sep 17 00:00:00 2001
+From: Mike Bell <mdb036@gmail.com>
+Date: Sun, 20 Aug 2023 18:25:04 +0100
+Subject: [PATCH] Fix RV32E shifts
+
+---
+ picorv32.v | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/picorv32.v b/picorv32.v
+index f13cea91..cc45fa99 100644
+--- a/picorv32.v
++++ b/picorv32.v
+@@ -652,7 +652,8 @@ module picorv32 #(
+ 	reg instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer;
+ 	wire instr_trap;
+ 
+-	reg [regindex_bits-1:0] decoded_rd, decoded_rs1, decoded_rs2;
++	reg [regindex_bits-1:0] decoded_rd, decoded_rs1;
++	reg [4:0] decoded_rs2;
+ 	reg [31:0] decoded_imm, decoded_imm_j;
+ 	reg decoder_trigger;
+ 	reg decoder_trigger_q;

patches/aolofsson_oh_pr110.patch

@@ -0,0 +1,612 @@
+From adb1bf9eae2bf8f81f800e3ffeeabcb1f4b23620 Mon Sep 17 00:00:00 2001
+From: Noah Moroze <noah@zeroasic.com>
+Date: Thu, 5 Aug 2021 15:48:45 -0400
+Subject: [PATCH 1/5] Fix whitespace in oh_padring
+
+- Convert tabs to spaces
+- Trim trailing whitespace
+---
+ padring/hdl/oh_padring.v | 238 +++++++++++++++++++--------------------
+ 1 file changed, 118 insertions(+), 120 deletions(-)
+
+diff --git a/padring/hdl/oh_padring.v b/padring/hdl/oh_padring.v
+index b17deea4..30785c88 100644
+--- a/padring/hdl/oh_padring.v
++++ b/padring/hdl/oh_padring.v
+@@ -1,7 +1,7 @@
+ //#############################################################################
+ //# Function: Padring Generator                                               #
+ //# Copyright: OH Project Authors. ALl rights Reserved.                       #
+-//# License:  MIT (see LICENSE file in OH repository)                         # 
++//# License:  MIT (see LICENSE file in OH repository)                         #
+ //#############################################################################
+ 
+ module oh_padring
+@@ -29,12 +29,12 @@ module oh_padring
+     parameter WE_VDDIO   =  8,
+     parameter WE_VSSIO   =  8,
+     parameter WE_VDD     =  8,
+-    parameter WE_VSS     =  8 
++    parameter WE_VSS     =  8
+     )
+    (
+     //CONTINUOUS GROUND
+     inout 		   vss,
+-    
++
+     inout 		   vdd,
+     //NORTH
+     inout [NO_DOMAINS-1:0] no_vddio,
+@@ -43,8 +43,9 @@ module oh_padring
+     output [NO_GPIO-1:0]   no_din, // data from pad
+     input [NO_GPIO-1:0]  no_dout, // data to pad
+     input [NO_GPIO*8-1:0]  no_cfg, // config
++
+     input [NO_GPIO-1:0]    no_ie, // input enable
+-    input [NO_GPIO-1:0]    no_oen, // output enable (bar)    
++    input [NO_GPIO-1:0]    no_oen, // output enable (bar)
+     //SOUTH
+     inout [SO_DOMAINS-1:0] so_vddio,
+     inout [SO_DOMAINS-1:0] so_vssio,
+@@ -80,145 +81,142 @@ module oh_padring
+    wire [SO_DOMAINS-1:0]   so_poc;
+    wire [WE_DOMAINS-1:0]   we_poc;
+    wire [EA_DOMAINS-1:0]   ea_poc;
+-   
++
+    generate
+       genvar 		  i;
+-            
++
+       //#############################
+       // NORTH
+       //#############################
+ 
+       for(i=0;i<NO_DOMAINS;i=i+1)
+-	begin: no_pads
+-	   oh_pads_domain #(.DIR("NO"),
+-			    .TYPE(TYPE),
+-			    .NGPIO(NO_GPIO),
+-			    .NVDDIO(NO_VDDIO),
+-			    .NVSSIO(NO_VSSIO),
+-			    .NVDD(NO_VDD),
+-			    .NVSS(NO_VSS),
+-			    .POC(1),
+-			    .LEFTCUT(1),
+-			    .RIGHTCUT(1))			    
+-	   i0 (.vdd     (vdd),
+-	       .vss     (vss),
+-	       // Outputs
+-	       .din     (no_din[NO_GPIO-1:0]),
+-	       // Inouts
+-	       .pad     (no_pad[NO_GPIO-1:0]),
+-	       .vddio   (no_vddio[i]),
+-	       .vssio	(no_vssio[i]),
+-	       .poc	(no_poc[i]),
+-	       // Inputs
+-	       .dout	(no_dout[NO_GPIO-1:0]),
+-	       .oen	(no_oen[NO_GPIO-1:0]),
+-	       .ie	(no_ie[NO_GPIO-1:0]),
+-	       .cfg	(no_cfg[NO_GPIO*8-1:0]));	   
+-	end
+-      
++        begin: no_pads
++           oh_pads_domain #(.DIR("NO"),
++                            .TYPE(TYPE),
++                            .NGPIO(NO_GPIO),
++                            .NVDDIO(NO_VDDIO),
++                            .NVSSIO(NO_VSSIO),
++                            .NVDD(NO_VDD),
++                            .NVSS(NO_VSS),
++                            .POC(1),
++                            .LEFTCUT(1),
++                            .RIGHTCUT(1))
++           i0 (.vdd     (vdd),
++               .vss     (vss),
++               // Outputs
++               .din     (no_din[NO_GPIO-1:0]),
++               // Inouts
++               .pad     (no_pad[NO_GPIO-1:0]),
++               .vddio   (no_vddio[i]),
++               .vssio	(no_vssio[i]),
++               .poc	(no_poc[i]),
++               // Inputs
++               .dout	(no_dout[NO_GPIO-1:0]),
++               .oen	(no_oen[NO_GPIO-1:0]),
++               .ie	(no_ie[NO_GPIO-1:0]),
++               .cfg	(no_cfg[NO_GPIO*8-1:0]));
++        end
++
+       //#############################
+       // SOUTH
+       //#############################
+ 
+       for(i=0;i<SO_DOMAINS;i=i+1)
+-	begin: so_pads
+-	   oh_pads_domain #(.DIR("SO"),
+-			    .TYPE(TYPE),
+-			    .NGPIO(SO_GPIO),
+-			    .NVDDIO(SO_VDDIO),
+-			    .NVSSIO(SO_VSSIO),
+-			    .NVDD(SO_VDD),
+-			    .NVSS(SO_VSS),
+-			    .POC(1),
+-			    .LEFTCUT(1),
+-			    .RIGHTCUT(1))
+-	   i0 (.vdd     (vdd),
+-	       .vss     (vss),
+-	       // Outputs
+-	       .din     (so_din[SO_GPIO-1:0]),
+-	       // Inouts
+-	       .pad     (so_pad[SO_GPIO-1:0]),
+-	       .vddio   (so_vddio[i]),
+-	       .vssio	(so_vssio[i]),
+-	       .poc	(so_poc[i]),
+-	       // Inputs
+-	       .dout	(so_dout[SO_GPIO-1:0]),
+-	       .oen	(so_oen[SO_GPIO-1:0]),
+-	       .ie	(so_ie[SO_GPIO-1:0]),
+-	       .cfg	(so_cfg[SO_GPIO*8-1:0]));
+-	end
+-      
+-      
++        begin: so_pads
++           oh_pads_domain #(.DIR("SO"),
++                            .TYPE(TYPE),
++                            .NGPIO(SO_GPIO),
++                            .NVDDIO(SO_VDDIO),
++                            .NVSSIO(SO_VSSIO),
++                            .NVDD(SO_VDD),
++                            .NVSS(SO_VSS),
++                            .POC(1),
++                            .LEFTCUT(1),
++                            .RIGHTCUT(1))
++           i0 (.vdd     (vdd),
++               .vss     (vss),
++               // Outputs
++               .din     (so_din[SO_GPIO-1:0]),
++               // Inouts
++               .pad     (so_pad[SO_GPIO-1:0]),
++               .vddio   (so_vddio[i]),
++               .vssio	(so_vssio[i]),
++               .poc	(so_poc[i]),
++               // Inputs
++               .dout	(so_dout[SO_GPIO-1:0]),
++               .oen	(so_oen[SO_GPIO-1:0]),
++               .ie	(so_ie[SO_GPIO-1:0]),
++               .cfg	(so_cfg[SO_GPIO*8-1:0]));
++        end
++
++
+       //#############################
+       // EAST
+       //#############################
+ 
+       for(i=0;i<EA_DOMAINS;i=i+1)
+-	begin: ea_pads
+-	   oh_pads_domain #(.DIR("EO"),
+-			    .TYPE(TYPE),
+-			    .NGPIO(EA_GPIO),
+-			    .NVDDIO(EA_VDDIO),
+-			    .NVSSIO(EA_VSSIO),
+-			    .NVDD(EA_VDD),
+-			    .NVSS(EA_VSS),
+-			    .POC(1),
+-			    .LEFTCUT(1),
+-			    .RIGHTCUT(1))			    
+-	   i0 (.vdd     (vdd),
+-	       .vss     (vss),
+-	       // Outputs
+-	       .din     (ea_din[EA_GPIO-1:0]),
+-	       // Inouts
+-	       .pad     (ea_pad[EA_GPIO-1:0]),
+-	       .vddio   (ea_vddio[i]),
+-	       .vssio	(ea_vssio[i]),
+-	       .poc	(ea_poc[i]),
+-	       // Inputs
+-	       .dout	(ea_dout[EA_GPIO-1:0]),
+-	       .oen	(ea_oen[EA_GPIO-1:0]),
+-	       .ie	(ea_ie[EA_GPIO-1:0]),
+-	       .cfg	(ea_cfg[EA_GPIO*8-1:0]));
+-	   
+-	end
+-      
++        begin: ea_pads
++           oh_pads_domain #(.DIR("EO"),
++                            .TYPE(TYPE),
++                            .NGPIO(EA_GPIO),
++                            .NVDDIO(EA_VDDIO),
++                            .NVSSIO(EA_VSSIO),
++                            .NVDD(EA_VDD),
++                            .NVSS(EA_VSS),
++                            .POC(1),
++                            .LEFTCUT(1),
++                            .RIGHTCUT(1))
++           i0 (.vdd     (vdd),
++               .vss     (vss),
++               // Outputs
++               .din     (ea_din[EA_GPIO-1:0]),
++               // Inouts
++               .pad     (ea_pad[EA_GPIO-1:0]),
++               .vddio   (ea_vddio[i]),
++               .vssio	(ea_vssio[i]),
++               .poc	(ea_poc[i]),
++               // Inputs
++               .dout	(ea_dout[EA_GPIO-1:0]),
++               .oen	(ea_oen[EA_GPIO-1:0]),
++               .ie	(ea_ie[EA_GPIO-1:0]),
++               .cfg	(ea_cfg[EA_GPIO*8-1:0]));
++
++        end
++
+       //#############################
+       // WEST
+       //#############################
+ 
+       for(i=0;i<WE_DOMAINS;i=i+1)
+-	begin: we_pads
+-	   oh_pads_domain #(.DIR("WE"),
+-			    .TYPE(TYPE),
+-			    .NGPIO(WE_GPIO),
+-			    .NVDDIO(WE_VDDIO),
+-			    .NVSSIO(WE_VSSIO),
+-			    .NVDD(WE_VDD),
+-			    .NVSS(WE_VSS),
+-			    .POC(1),
+-			    .LEFTCUT(1),
+-			    .RIGHTCUT(1))			    
+-	 
+-	   i0 (.vdd     (vdd),
+-	       .vss     (vss),
+-	       // Outputs
+-	       .din     (we_din[WE_GPIO-1:0]),
+-	       // Inouts
+-	       .pad     (we_pad[WE_GPIO-1:0]),
+-	       .vddio   (we_vddio[i]),
+-	       .vssio	(we_vssio[i]),
+-	       .poc	(we_poc[i]),
+-	       // Inputs
+-	       .dout	(we_dout[WE_GPIO-1:0]),
+-	       .oen	(we_oen[WE_GPIO-1:0]),
+-	       .ie	(we_ie[WE_GPIO-1:0]),
+-	       .cfg	(we_cfg[WE_GPIO*8-1:0]));
+-	   
+-	end
+-      
+-   endgenerate
++        begin: we_pads
++           oh_pads_domain #(.DIR("WE"),
++                            .TYPE(TYPE),
++                            .NGPIO(WE_GPIO),
++                            .NVDDIO(WE_VDDIO),
++                            .NVSSIO(WE_VSSIO),
++                            .NVDD(WE_VDD),
++                            .NVSS(WE_VSS),
++                            .POC(1),
++                            .LEFTCUT(1),
++                            .RIGHTCUT(1))
+ 
+-endmodule // oh_padring
++           i0 (.vdd     (vdd),
++               .vss     (vss),
++               // Outputs
++               .din     (we_din[WE_GPIO-1:0]),
++               // Inouts
++               .pad     (we_pad[WE_GPIO-1:0]),
++               .vddio   (we_vddio[i]),
++               .vssio	(we_vssio[i]),
++               .poc	(we_poc[i]),
++               // Inputs
++               .dout	(we_dout[WE_GPIO-1:0]),
++               .oen	(we_oen[WE_GPIO-1:0]),
++               .ie	(we_ie[WE_GPIO-1:0]),
++               .cfg	(we_cfg[WE_GPIO*8-1:0]));
+ 
++        end
+ 
++   endgenerate
+ 
++endmodule // oh_padring
+
+From d8a28ac1538bbb7bbcdbe83a8a3ba7ecb6bbafe3 Mon Sep 17 00:00:00 2001
+From: Noah Moroze <noah@zeroasic.com>
+Date: Thu, 5 Aug 2021 17:22:05 -0400
+Subject: [PATCH 2/5] padring: add pass-through "tech config" for GPIO
+
+This is an escape hatch for connecting to technology-specific I/O config pins.
+---
+ padring/hdl/oh_padring.v     | 34 +++++++++++++++++++++++-----------
+ padring/hdl/oh_pads_domain.v |  8 ++++++--
+ 2 files changed, 29 insertions(+), 13 deletions(-)
+
+diff --git a/padring/hdl/oh_padring.v b/padring/hdl/oh_padring.v
+index 30785c88..7c81e855 100644
+--- a/padring/hdl/oh_padring.v
++++ b/padring/hdl/oh_padring.v
+@@ -29,7 +29,8 @@ module oh_padring
+     parameter WE_VDDIO   =  8,
+     parameter WE_VSSIO   =  8,
+     parameter WE_VDD     =  8,
+-    parameter WE_VSS     =  8
++    parameter WE_VSS     =  8,
++    parameter TECH_CFG_WIDTH = 16
+     )
+    (
+     //CONTINUOUS GROUND
+@@ -43,9 +44,9 @@ module oh_padring
+     output [NO_GPIO-1:0]   no_din, // data from pad
+     input [NO_GPIO-1:0]  no_dout, // data to pad
+     input [NO_GPIO*8-1:0]  no_cfg, // config
+-
+     input [NO_GPIO-1:0]    no_ie, // input enable
+     input [NO_GPIO-1:0]    no_oen, // output enable (bar)
++    input [NO_GPIO*TECH_CFG_WIDTH-1:0] no_tech_cfg,
+     //SOUTH
+     inout [SO_DOMAINS-1:0] so_vddio,
+     inout [SO_DOMAINS-1:0] so_vssio,
+@@ -55,6 +56,7 @@ module oh_padring
+     input [SO_GPIO*8-1:0]  so_cfg, // config
+     input [SO_GPIO-1:0]    so_ie, // input enable
+     input [SO_GPIO-1:0]    so_oen, // output enable (bar)
++    input [SO_GPIO*TECH_CFG_WIDTH-1:0] so_tech_cfg,
+     //EAST
+     inout [EA_DOMAINS-1:0] ea_vddio,
+     inout [EA_DOMAINS-1:0] ea_vssio,
+@@ -64,6 +66,7 @@ module oh_padring
+     input [EA_GPIO*8-1:0]  ea_cfg, // config
+     input [EA_GPIO-1:0]    ea_ie, // input enable
+     input [EA_GPIO-1:0]    ea_oen, // output enable (bar)
++    input [EA_GPIO*TECH_CFG_WIDTH-1:0] ea_tech_cfg,
+     //WEST
+     inout [WE_DOMAINS-1:0] we_vddio,
+     inout [WE_DOMAINS-1:0] we_vssio,
+@@ -72,7 +75,8 @@ module oh_padring
+     input [WE_GPIO-1:0]  we_dout, // data to pad
+     input [WE_GPIO*8-1:0]  we_cfg, // config
+     input [WE_GPIO-1:0]    we_ie, // input enable
+-    input [WE_GPIO-1:0]    we_oen // output enable (bar)
++    input [WE_GPIO-1:0]    we_oen, // output enable (bar)
++    input [WE_GPIO*TECH_CFG_WIDTH-1:0] we_tech_cfg
+     );
+ 
+ 
+@@ -100,7 +104,8 @@ module oh_padring
+                             .NVSS(NO_VSS),
+                             .POC(1),
+                             .LEFTCUT(1),
+-                            .RIGHTCUT(1))
++                            .RIGHTCUT(1),
++                            .TECH_CFG_WIDTH(TECH_CFG_WIDTH))
+            i0 (.vdd     (vdd),
+                .vss     (vss),
+                // Outputs
+@@ -114,7 +119,8 @@ module oh_padring
+                .dout	(no_dout[NO_GPIO-1:0]),
+                .oen	(no_oen[NO_GPIO-1:0]),
+                .ie	(no_ie[NO_GPIO-1:0]),
+-               .cfg	(no_cfg[NO_GPIO*8-1:0]));
++               .cfg	(no_cfg[NO_GPIO*8-1:0]),
++               .tech_cfg(no_tech_cfg));
+         end
+ 
+       //#############################
+@@ -132,7 +138,8 @@ module oh_padring
+                             .NVSS(SO_VSS),
+                             .POC(1),
+                             .LEFTCUT(1),
+-                            .RIGHTCUT(1))
++                            .RIGHTCUT(1),
++                            .TECH_CFG_WIDTH(TECH_CFG_WIDTH))
+            i0 (.vdd     (vdd),
+                .vss     (vss),
+                // Outputs
+@@ -146,7 +153,8 @@ module oh_padring
+                .dout	(so_dout[SO_GPIO-1:0]),
+                .oen	(so_oen[SO_GPIO-1:0]),
+                .ie	(so_ie[SO_GPIO-1:0]),
+-               .cfg	(so_cfg[SO_GPIO*8-1:0]));
++               .cfg	(so_cfg[SO_GPIO*8-1:0]),
++               .tech_cfg(so_tech_cfg));
+         end
+ 
+ 
+@@ -165,7 +173,8 @@ module oh_padring
+                             .NVSS(EA_VSS),
+                             .POC(1),
+                             .LEFTCUT(1),
+-                            .RIGHTCUT(1))
++                            .RIGHTCUT(1),
++                            .TECH_CFG_WIDTH(TECH_CFG_WIDTH))
+            i0 (.vdd     (vdd),
+                .vss     (vss),
+                // Outputs
+@@ -179,7 +188,8 @@ module oh_padring
+                .dout	(ea_dout[EA_GPIO-1:0]),
+                .oen	(ea_oen[EA_GPIO-1:0]),
+                .ie	(ea_ie[EA_GPIO-1:0]),
+-               .cfg	(ea_cfg[EA_GPIO*8-1:0]));
++               .cfg	(ea_cfg[EA_GPIO*8-1:0]),
++               .tech_cfg(ea_tech_cfg));
+ 
+         end
+ 
+@@ -198,7 +208,8 @@ module oh_padring
+                             .NVSS(WE_VSS),
+                             .POC(1),
+                             .LEFTCUT(1),
+-                            .RIGHTCUT(1))
++                            .RIGHTCUT(1),
++                            .TECH_CFG_WIDTH(TECH_CFG_WIDTH))
+ 
+            i0 (.vdd     (vdd),
+                .vss     (vss),
+@@ -213,7 +224,8 @@ module oh_padring
+                .dout	(we_dout[WE_GPIO-1:0]),
+                .oen	(we_oen[WE_GPIO-1:0]),
+                .ie	(we_ie[WE_GPIO-1:0]),
+-               .cfg	(we_cfg[WE_GPIO*8-1:0]));
++               .cfg	(we_cfg[WE_GPIO*8-1:0]),
++               .tech_cfg(we_tech_cfg));
+ 
+         end
+ 
+diff --git a/padring/hdl/oh_pads_domain.v b/padring/hdl/oh_pads_domain.v
+index 036c9c1f..7f77a42a 100644
+--- a/padring/hdl/oh_pads_domain.v
++++ b/padring/hdl/oh_pads_domain.v
+@@ -14,7 +14,8 @@ module oh_pads_domain
+     parameter NVSS     =  8,    // total core ground pads
+     parameter POC      =  1,    // 1 = place poc cell
+     parameter LEFTCUT  =  1,    // 1 = place cut on left (seen from center)
+-    parameter RIGHTCUT =  1     // 1 = place cut on right (seen from center
++    parameter RIGHTCUT =  1,    // 1 = place cut on right (seen from center
++    parameter TECH_CFG_WIDTH = 16
+     )
+    (//pad
+     inout [NGPIO-1:0] 	pad, // pad
+@@ -30,6 +31,7 @@ module oh_pads_domain
+     input [NGPIO-1:0] 	oen, // output enable (bar)
+     input [NGPIO-1:0] 	ie, // input enable
+     input [NGPIO*8-1:0] cfg // io config
++    input [NGPIO*TECH_CFG_WIDTH-1:0] tech_cfg // technology-specific config
+     );
+       
+    generate
+@@ -58,7 +60,9 @@ module oh_pads_domain
+ 	       .vss    (vss),
+ 	       .vddio  (vddio),
+ 	       .vssio  (vssio),
+-	       .pad    (pad[i]));
++	       .pad    (pad[i]),
++	       
++	       .tech_cfg(tech_cfg[i*TECH_CFG_WIDTH+:TECH_CFG_WIDTH]));
+ 	end
+ 
+       //######################
+
+From bc9d7f8e55c7d703d93b8f05a2455dc2f27d7924 Mon Sep 17 00:00:00 2001
+From: Noah Moroze <noah@zeroasic.com>
+Date: Sat, 7 Aug 2021 17:15:48 -0400
+Subject: [PATCH 3/5] Insert missing comma
+
+---
+ padring/hdl/oh_pads_domain.v | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/padring/hdl/oh_pads_domain.v b/padring/hdl/oh_pads_domain.v
+index 7f77a42a..3e2cd283 100644
+--- a/padring/hdl/oh_pads_domain.v
++++ b/padring/hdl/oh_pads_domain.v
+@@ -30,7 +30,7 @@ module oh_pads_domain
+     output [NGPIO-1:0] 	din, // data from pad
+     input [NGPIO-1:0] 	oen, // output enable (bar)
+     input [NGPIO-1:0] 	ie, // input enable
+-    input [NGPIO*8-1:0] cfg // io config
++    input [NGPIO*8-1:0] cfg, // io config
+     input [NGPIO*TECH_CFG_WIDTH-1:0] tech_cfg // technology-specific config
+     );
+       
+
+From 3e1d6d8e8d6c66f6a979e1daf4725b05bb9bb592 Mon Sep 17 00:00:00 2001
+From: Noah Moroze <noah@zeroasic.com>
+Date: Fri, 13 Aug 2021 16:18:21 -0400
+Subject: [PATCH 4/5] Add parameters to disable POC/cut cells
+
+---
+ padring/hdl/oh_padring.v | 26 ++++++++++++++------------
+ 1 file changed, 14 insertions(+), 12 deletions(-)
+
+diff --git a/padring/hdl/oh_padring.v b/padring/hdl/oh_padring.v
+index 7c81e855..1b4c837e 100644
+--- a/padring/hdl/oh_padring.v
++++ b/padring/hdl/oh_padring.v
+@@ -30,6 +30,8 @@ module oh_padring
+     parameter WE_VSSIO   =  8,
+     parameter WE_VDD     =  8,
+     parameter WE_VSS     =  8,
++    parameter ENABLE_CUTS = 1,
++    parameter ENABLE_POC  = 1,
+     parameter TECH_CFG_WIDTH = 16
+     )
+    (
+@@ -102,9 +104,9 @@ module oh_padring
+                             .NVSSIO(NO_VSSIO),
+                             .NVDD(NO_VDD),
+                             .NVSS(NO_VSS),
+-                            .POC(1),
+-                            .LEFTCUT(1),
+-                            .RIGHTCUT(1),
++                            .POC(ENABLE_POC),
++                            .LEFTCUT(ENABLE_CUT),
++                            .RIGHTCUT(ENABLE_CUT),
+                             .TECH_CFG_WIDTH(TECH_CFG_WIDTH))
+            i0 (.vdd     (vdd),
+                .vss     (vss),
+@@ -136,9 +138,9 @@ module oh_padring
+                             .NVSSIO(SO_VSSIO),
+                             .NVDD(SO_VDD),
+                             .NVSS(SO_VSS),
+-                            .POC(1),
+-                            .LEFTCUT(1),
+-                            .RIGHTCUT(1),
++                            .POC(ENABLE_POC),
++                            .LEFTCUT(ENABLE_CUT),
++                            .RIGHTCUT(ENABLE_CUT),
+                             .TECH_CFG_WIDTH(TECH_CFG_WIDTH))
+            i0 (.vdd     (vdd),
+                .vss     (vss),
+@@ -171,9 +173,9 @@ module oh_padring
+                             .NVSSIO(EA_VSSIO),
+                             .NVDD(EA_VDD),
+                             .NVSS(EA_VSS),
+-                            .POC(1),
+-                            .LEFTCUT(1),
+-                            .RIGHTCUT(1),
++                            .POC(ENABLE_POC),
++                            .LEFTCUT(ENABLE_CUT),
++                            .RIGHTCUT(ENABLE_CUT),
+                             .TECH_CFG_WIDTH(TECH_CFG_WIDTH))
+            i0 (.vdd     (vdd),
+                .vss     (vss),
+@@ -206,9 +208,9 @@ module oh_padring
+                             .NVSSIO(WE_VSSIO),
+                             .NVDD(WE_VDD),
+                             .NVSS(WE_VSS),
+-                            .POC(1),
+-                            .LEFTCUT(1),
+-                            .RIGHTCUT(1),
++                            .POC(ENABLE_POC),
++                            .LEFTCUT(ENABLE_CUT),
++                            .RIGHTCUT(ENABLE_CUT),
+                             .TECH_CFG_WIDTH(TECH_CFG_WIDTH))
+ 
+            i0 (.vdd     (vdd),
+
+From b4f1aa3a601a04104e780be4cf00385eb7b3dea1 Mon Sep 17 00:00:00 2001
+From: Noah Moroze <noah@zeroasic.com>
+Date: Fri, 13 Aug 2021 16:18:37 -0400
+Subject: [PATCH 5/5] Add generic cell under oh_pads_corner
+
+To be consistent with how other I/O cells are defined.
+---
+ padring/hdl/oh_pads_corner.v | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/padring/hdl/oh_pads_corner.v b/padring/hdl/oh_pads_corner.v
+index 1aa662ca..27464010 100644
+--- a/padring/hdl/oh_pads_corner.v
++++ b/padring/hdl/oh_pads_corner.v
+@@ -11,6 +11,13 @@ module oh_pads_corner
+    inout 	       vdd, // core supply
+    inout 	       vss // common ground
+    );
++
++   asic_iocorner i0 (
++     .vddio,
++     .vssio,
++     .vdd,
++     .vss
++   );
+   
+ endmodule // oh_pads_corner
+ 

patches/apfaudio_eurorack-pmod_pr36.patch

@@ -0,0 +1,152 @@
+From 8cbe26de04767fa46e809683e17a8d53c5818207 Mon Sep 17 00:00:00 2001
+From: Sebastian Holzapfel <me@vk2seb.com>
+Date: Sun, 17 Sep 2023 22:20:48 +0200
+Subject: [PATCH] cores/vco: fix and modularize vco example
+
+---
+ gateware/cores/util/wavetable_osc.sv | 25 ++++++++--------
+ gateware/cores/vco.sv                | 43 ++++++++++++++--------------
+ gateware/mk/common.mk                |  3 +-
+ gateware/scripts/verilator_lint.sh   |  3 +-
+ 4 files changed, 37 insertions(+), 37 deletions(-)
+
+diff --git a/gateware/cores/util/wavetable_osc.sv b/gateware/cores/util/wavetable_osc.sv
+index b627122..e570b5f 100644
+--- a/gateware/cores/util/wavetable_osc.sv
++++ b/gateware/cores/util/wavetable_osc.sv
+@@ -1,30 +1,29 @@
+ module wavetable_osc #(
+     parameter W = 16,
++    parameter FRAC_BITS = 10,
+     parameter WAVETABLE_PATH = "cores/util/vco/wavetable.hex",
+-    parameter WAVETABLE_SIZE = 256,
++    parameter WAVETABLE_SIZE = 256
+ )(
+     input rst,
+     input sample_clk,
+     input [31:0] wavetable_inc,
+-    output signed [W-1:0] out,
++    output logic signed [W-1:0] out
+ );
+ 
+ logic [W-1:0] wavetable [0:WAVETABLE_SIZE-1];
+ initial $readmemh(WAVETABLE_PATH, wavetable);
+ 
+-logic [31:0] wavetable_pos = 32'h0;
++// Position in wavetable - N.F fixed-point where BIT_START is size of F.
++logic [31:0] wavetable_pos;
+ 
+ always_ff @(posedge sample_clk) begin
+-    // TODO: linear interpolation between frequencies, silence oscillator
+-    // whenever we are outside the LUT bounds.
+-    wavetable_pos <= wavetable_pos + wavetable_inc;
++    if (rst) begin
++        wavetable_pos <= 0;
++    end else begin
++        wavetable_pos <= wavetable_pos + wavetable_inc;
++        // Take top N bits of wavetable_pos as output.
++        out <= wavetable[wavetable_pos[FRAC_BITS+$clog2(WAVETABLE_SIZE)-1:FRAC_BITS]];
++    end
+ end
+ 
+-// Top 8 bits of the N.F fixed-point representation are index into wavetable.
+-localparam BIT_START = 10;
+-wire [$clog2(WAVETABLE_SIZE)-1:0] wavetable_idx =
+-    wavetable_pos[BIT_START+$clog2(WAVETABLE_SIZE)-1:BIT_START];
+-
+-assign out = wavetable[wavetable_idx];
+-
+ endmodule
+diff --git a/gateware/cores/vco.sv b/gateware/cores/vco.sv
+index 11e742d..0fab58b 100644
+--- a/gateware/cores/vco.sv
++++ b/gateware/cores/vco.sv
+@@ -2,7 +2,7 @@
+ //
+ // Mapping:
+ // - Input 0: V/Oct input, C3 is +3V
+-// - Output 0-3: VCO output (from wavetable) phased at 0, 90, 120, 270deg.
++// - Output 0: VCO output (from wavetable)
+ 
+ module vco #(
+     parameter W = 16,
+@@ -35,31 +35,30 @@ module vco #(
+ logic [W-1:0] v_oct_lut [0:V_OCT_LUT_SIZE-1];
+ initial $readmemh(V_OCT_LUT_PATH, v_oct_lut);
+ 
+-logic [W-1:0] wavetable [0:WAVETABLE_SIZE-1];
+-initial $readmemh(WAVETABLE_PATH, wavetable);
+-
+ // For < 0V input, clamp to bottom note.
+-logic signed [W-1:0] lut_index;
+-logic [$clog2(V_OCT_LUT_SIZE)-1:0] lut_index_clamped;
+-logic [31:0] wavetable_pos = 32'h0;
+-
+-assign lut_index = sample_in0 >>> 6;
+-assign lut_index_clamped = $clog2(V_OCT_LUT_SIZE)'(lut_index < 0 ? W'(0) : lut_index);
++logic signed [W-1:0] lut_index;
++logic signed [W-1:0] lut_index_clamp_lo;
+ 
+ always_ff @(posedge sample_clk) begin
+-    // TODO: linear interpolation between frequencies, silence oscillator
+-    // whenever we are outside the LUT bounds.
+-    wavetable_pos <= wavetable_pos + 32'(v_oct_lut[lut_index_clamped]);
++    if (rst) begin
++        lut_index <= 0;
++        lut_index_clamp_lo <= 0;
++    end else begin
++        lut_index <= sample_in0 >>> 6;
++        lut_index_clamp_lo <= lut_index < 0 ? 0 : lut_index;
++    end
+ end
+ 
+-// Top 8 bits of the N.F fixed-point representation are index into wavetable.
+-localparam BIT_START = 10 + FDIV;
+-wire [$clog2(WAVETABLE_SIZE)-1:0] wavetable_idx =
+-    wavetable_pos[BIT_START+$clog2(WAVETABLE_SIZE)-1:BIT_START];
+-
+-assign sample_out0 = wavetable[wavetable_idx];
+-assign sample_out1 = wavetable[wavetable_idx+WAVETABLE_SIZE/4];
+-assign sample_out2 = wavetable[wavetable_idx+WAVETABLE_SIZE/2];
+-assign sample_out3 = wavetable[wavetable_idx+WAVETABLE_SIZE/2+WAVETABLE_SIZE/4];
++wavetable_osc #(
++    .W(W),
++    .FRAC_BITS(10),
++    .WAVETABLE_PATH(WAVETABLE_PATH),
++    .WAVETABLE_SIZE(WAVETABLE_SIZE)
++) osc_0 (
++    .rst(rst),
++    .sample_clk(sample_clk),
++    .wavetable_inc(32'(v_oct_lut[$clog2(V_OCT_LUT_SIZE)'(lut_index_clamp_lo)])),
++    .out(sample_out0)
++);
+ 
+ endmodule
+diff --git a/gateware/mk/common.mk b/gateware/mk/common.mk
+index 0574e21..5873876 100644
+--- a/gateware/mk/common.mk
++++ b/gateware/mk/common.mk
+@@ -20,4 +20,5 @@ SRC_COMMON = eurorack_pmod.sv \
+ 		     cores/util/transpose.sv \
+ 		     cores/util/echo.sv \
+ 		     cores/util/delayline.sv \
+-			 cores/util/dc_block.sv
++			 cores/util/dc_block.sv \
++			 cores/util/wavetable_osc.sv
+diff --git a/gateware/scripts/verilator_lint.sh b/gateware/scripts/verilator_lint.sh
+index 6df31ce..0f69147 100755
+--- a/gateware/scripts/verilator_lint.sh
++++ b/gateware/scripts/verilator_lint.sh
+@@ -35,10 +35,11 @@ verilator --lint-only -Icores clkdiv.sv
+ verilator --lint-only -Icores sampler.sv
+ verilator --lint-only -Icores seqswitch.sv
+ verilator --lint-only -Icores vca.sv
+-verilator --lint-only -Icores vco.sv
++verilator --lint-only -Icores -Icores/util vco.sv
+ verilator --lint-only cores/util/filter/karlsen_lpf.sv
+ verilator --lint-only cores/util/filter/karlsen_lpf_pipelined.sv
+ verilator --lint-only -Icores -Icores/util/filter filter.sv
+ verilator --lint-only -Icores -Icores/util pitch_shift.sv
+ verilator --lint-only -Icores -Icores/util stereo_echo.sv
+ verilator --lint-only -Icores -Icores/util dc_block.sv
++verilator --lint-only -Icores -Icores/util wavetable_osc.sv

patches/bensampson5_libsv_pr119.patch

@@ -0,0 +1,290 @@
+From 6da745c30d3b5ff32b49d581eb6a8e95cdabb3a2 Mon Sep 17 00:00:00 2001
+From: Ben Sampson <bensampson5@gmail.com>
+Date: Sat, 29 Jan 2022 06:02:46 -0600
+Subject: [PATCH 1/2] Add include guards to all files that don't have it
+
+---
+ libsv/coders/bcd_decoder.sv      | 5 +++++
+ libsv/coders/bcd_encoder.sv      | 5 +++++
+ libsv/coders/decoder_8b10b.sv    | 5 +++++
+ libsv/coders/encoder_8b10b.sv    | 5 +++++
+ libsv/coders/priority_encoder.sv | 5 +++++
+ libsv/counters/binary_counter.sv | 5 +++++
+ libsv/latches/sr_latch.sv        | 5 +++++
+ libsv/math/full_adder.sv         | 5 +++++
+ libsv/math/half_adder.sv         | 5 +++++
+ libsv/muxes/onehot_mux.sv        | 7 ++++++-
+ 10 files changed, 51 insertions(+), 1 deletion(-)
+
+diff --git a/libsv/coders/bcd_decoder.sv b/libsv/coders/bcd_decoder.sv
+index eaae727..2c6cb9c 100644
+--- a/libsv/coders/bcd_decoder.sv
++++ b/libsv/coders/bcd_decoder.sv
+@@ -1,3 +1,6 @@
++`ifndef LIBSV_CODERS_BCD_DECODER
++`define LIBSV_CODERS_BCD_DECODER
++
+ module bcd_decoder #(
+     parameter integer N  /* verilator public_flat_rd */ = 3
+ ) (
+@@ -18,3 +21,5 @@ module bcd_decoder #(
+   end
+ 
+ endmodule
++
++`endif  /* LIBSV_CODERS_BCD_DECODER */
+
+diff --git a/libsv/coders/bcd_encoder.sv b/libsv/coders/bcd_encoder.sv
+index 2962c73..563ea7c 100644
+--- a/libsv/coders/bcd_encoder.sv
++++ b/libsv/coders/bcd_encoder.sv
+@@ -1,3 +1,6 @@
++`ifndef LIBSV_CODERS_BCD_ENCODER
++`define LIBSV_CODERS_BCD_ENCODER
++
+ module bcd_encoder #(
+     parameter integer N  /* verilator public_flat_rd */ = 8
+ ) (
+@@ -16,3 +19,5 @@ module bcd_encoder #(
+   end
+ 
+ endmodule
++
++`endif  /* LIBSV_CODERS_BCD_ENCODER */
+
+diff --git a/libsv/coders/decoder_8b10b.sv b/libsv/coders/decoder_8b10b.sv
+index 25bc91f..b63b25d 100644
+--- a/libsv/coders/decoder_8b10b.sv
++++ b/libsv/coders/decoder_8b10b.sv
+@@ -1,3 +1,6 @@
++`ifndef LIBSV_CODERS_DECODER_8B10B
++`define LIBSV_CODERS_DECODER_8B10B
++
+ module decoder_8b10b (
+     input  logic       i_clk,
+     input  logic       i_reset_n,
+@@ -2120,3 +2123,5 @@ module decoder_8b10b (
+   end
+ 
+ endmodule
++
++`endif  /* LIBSV_CODERS_DECODER_8B10B */
+
+diff --git a/libsv/coders/encoder_8b10b.sv b/libsv/coders/encoder_8b10b.sv
+index 9a8c55b..ad90a35 100644
+--- a/libsv/coders/encoder_8b10b.sv
++++ b/libsv/coders/encoder_8b10b.sv
+@@ -1,3 +1,6 @@
++`ifndef LIBSV_CODERS_ENCODER_8B10B
++`define LIBSV_CODERS_ENCODER_8B10B
++
+ module encoder_8b10b (
+     input  logic       i_clk,  // input clock
+     input  logic       i_reset_n,  // input asynchronous active-low reset
+@@ -1089,3 +1092,5 @@ module encoder_8b10b (
+   end
+ 
+ endmodule
++
++`endif  /* LIBSV_CODERS_ENCODER_8B10B */
+
+diff --git a/libsv/coders/priority_encoder.sv b/libsv/coders/priority_encoder.sv
+index a20c5aa..585790e 100644
+--- a/libsv/coders/priority_encoder.sv
++++ b/libsv/coders/priority_encoder.sv
+@@ -1,3 +1,6 @@
++`ifndef LIBSV_CODERS_PRIORITY_ENCODER
++`define LIBSV_CODERS_PRIORITY_ENCODER
++
+ module priority_encoder #(
+     parameter integer IW  /* verilator public_flat_rd */ = 4
+ ) (
+@@ -22,3 +25,5 @@ module priority_encoder #(
+   end
+ 
+ endmodule
++
++`endif  /* LIBSV_CODERS_PRIORITY_ENCODER */
+diff --git a/libsv/counters/binary_counter.sv b/libsv/counters/binary_counter.sv
+index 3be30c5..da4caa2 100644
+--- a/libsv/counters/binary_counter.sv
++++ b/libsv/counters/binary_counter.sv
+@@ -1,3 +1,6 @@
++`ifndef LIBSV_COUNTERS_BINARY_COUNTER
++`define LIBSV_COUNTERS_BINARY_COUNTER
++
+ module binary_counter #(
+     parameter integer N  /* verilator public_flat_rd */ = 8
+ ) (
+@@ -11,3 +14,5 @@ module binary_counter #(
+     else q <= q + 1;
+ 
+ endmodule
++
++`endif  /* LIBSV_COUNTERS_BINARY_COUNTER */
+diff --git a/libsv/latches/sr_latch.sv b/libsv/latches/sr_latch.sv
+index 9540c6c..e1399fe 100644
+--- a/libsv/latches/sr_latch.sv
++++ b/libsv/latches/sr_latch.sv
+@@ -1,3 +1,6 @@
++`ifndef LIBSV_LATCHES_SR_LATCH
++`define LIBSV_LATCHES_SR_LATCH
++
+ module sr_latch (
+     input  logic                                 s,
+     input  logic                                 r,
+@@ -9,3 +12,5 @@ module sr_latch (
+   assign q_n = ~(s | q);
+ 
+ endmodule
++
++`endif  /* LIBSV_LATCHES_SR_LATCH */
+diff --git a/libsv/math/full_adder.sv b/libsv/math/full_adder.sv
+index d00270c..d6a28a4 100644
+--- a/libsv/math/full_adder.sv
++++ b/libsv/math/full_adder.sv
+@@ -1,3 +1,6 @@
++`ifndef LIBSV_MATH_FULL_ADDER
++`define LIBSV_MATH_FULL_ADDER
++
+ module full_adder (
+     input  logic i_a,
+     input  logic i_b,
+@@ -10,3 +13,5 @@ module full_adder (
+   assign o_carry = ((i_a | i_b) & i_carry) | (i_a & i_b);
+ 
+ endmodule
++
++`endif  /* LIBSV_MATH_FULL_ADDER */
+
+diff --git a/libsv/math/half_adder.sv b/libsv/math/half_adder.sv
+index c6ff66a..dea3e87 100644
+--- a/libsv/math/half_adder.sv
++++ b/libsv/math/half_adder.sv
+@@ -1,3 +1,6 @@
++`ifndef LIBSV_MATH_HALF_ADDER
++`define LIBSV_MATH_HALF_ADDER
++
+ module half_adder (
+     input  logic i_a,
+     input  logic i_b,
+@@ -9,3 +12,5 @@ module half_adder (
+   assign o_carry = i_a & i_b;
+ 
+ endmodule
++
++`endif  /* LIBSV_MATH_HALF_ADDER */
+
+diff --git a/libsv/muxes/onehot_mux.sv b/libsv/muxes/onehot_mux.sv
+index 317635e..7ac6644 100644
+--- a/libsv/muxes/onehot_mux.sv
++++ b/libsv/muxes/onehot_mux.sv
+@@ -1,3 +1,6 @@
++`ifndef LIBSV_MUXES_ONEHOT_MUX
++`define LIBSV_MUXES_ONEHOT_MUX
++
+ module onehot_mux #(
+     parameter integer DW  /* verilator public_flat_rd */ = 8,
+     parameter integer N  /* verilator public_flat_rd */  = 4
+@@ -13,4 +16,6 @@ module onehot_mux #(
+     for (j = 0; j < N; j = j + 1) o[DW-1:0] |= {(DW) {sel[j]}} & i[((j+1)*DW-1)-:DW];
+   end
+ 
+-endmodule  // onehot_mux
++endmodule : onehot_mux
++
++`endif  /* LIBSV_MUXES_ONEHOT_MUX */
+
+
+From b44a92dbacd0266a142c892d63f3297e80c36407 Mon Sep 17 00:00:00 2001
+From: Ben Sampson <bensampson5@gmail.com>
+Date: Sat, 29 Jan 2022 06:03:15 -0600
+Subject: [PATCH 2/2] Fix format
+
+---
+ libsv/coders/bcd_decoder.sv   | 2 +-
+ libsv/coders/bcd_encoder.sv   | 2 +-
+ libsv/coders/decoder_8b10b.sv | 2 +-
+ libsv/coders/encoder_8b10b.sv | 2 +-
+ libsv/math/full_adder.sv      | 2 +-
+ libsv/math/half_adder.sv      | 2 +-
+ libsv/muxes/onehot_mux.sv     | 2 +-
+ 7 files changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/libsv/coders/bcd_decoder.sv b/libsv/coders/bcd_decoder.sv
+index 2c6cb9c..fd51846 100644
+--- a/libsv/coders/bcd_decoder.sv
++++ b/libsv/coders/bcd_decoder.sv
+@@ -22,4 +22,4 @@ module bcd_decoder #(
+ 
+ endmodule
+ 
+-`endif  /* LIBSV_CODERS_BCD_DECODER */
+
++`endif  /* LIBSV_CODERS_BCD_DECODER */
+diff --git a/libsv/coders/bcd_encoder.sv b/libsv/coders/bcd_encoder.sv
+index 563ea7c..5d81f8f 100644
+--- a/libsv/coders/bcd_encoder.sv
++++ b/libsv/coders/bcd_encoder.sv
+@@ -20,4 +20,4 @@ module bcd_encoder #(
+ 
+ endmodule
+ 
+-`endif  /* LIBSV_CODERS_BCD_ENCODER */
+
++`endif  /* LIBSV_CODERS_BCD_ENCODER */
+diff --git a/libsv/coders/decoder_8b10b.sv b/libsv/coders/decoder_8b10b.sv
+index b63b25d..a04dd64 100644
+--- a/libsv/coders/decoder_8b10b.sv
++++ b/libsv/coders/decoder_8b10b.sv
+@@ -2124,4 +2124,4 @@ module decoder_8b10b (
+ 
+ endmodule
+ 
+-`endif  /* LIBSV_CODERS_DECODER_8B10B */
+
++`endif  /* LIBSV_CODERS_DECODER_8B10B */
+diff --git a/libsv/coders/encoder_8b10b.sv b/libsv/coders/encoder_8b10b.sv
+index ad90a35..ad5f441 100644
+--- a/libsv/coders/encoder_8b10b.sv
++++ b/libsv/coders/encoder_8b10b.sv
+@@ -1093,4 +1093,4 @@ module encoder_8b10b (
+ 
+ endmodule
+ 
+-`endif  /* LIBSV_CODERS_ENCODER_8B10B */
+
++`endif  /* LIBSV_CODERS_ENCODER_8B10B */
+diff --git a/libsv/math/full_adder.sv b/libsv/math/full_adder.sv
+index d6a28a4..f3d2987 100644
+--- a/libsv/math/full_adder.sv
++++ b/libsv/math/full_adder.sv
+@@ -14,4 +14,4 @@ module full_adder (
+ 
+ endmodule
+ 
+-`endif  /* LIBSV_MATH_FULL_ADDER */
+
++`endif  /* LIBSV_MATH_FULL_ADDER */
+diff --git a/libsv/math/half_adder.sv b/libsv/math/half_adder.sv
+index dea3e87..532f547 100644
+--- a/libsv/math/half_adder.sv
++++ b/libsv/math/half_adder.sv
+@@ -13,4 +13,4 @@ module half_adder (
+ 
+ endmodule
+ 
+-`endif  /* LIBSV_MATH_HALF_ADDER */
+
++`endif  /* LIBSV_MATH_HALF_ADDER */
+diff --git a/libsv/muxes/onehot_mux.sv b/libsv/muxes/onehot_mux.sv
+index 7ac6644..00154d4 100644
+--- a/libsv/muxes/onehot_mux.sv
++++ b/libsv/muxes/onehot_mux.sv
+@@ -18,4 +18,4 @@ module onehot_mux #(
+ 
+ endmodule : onehot_mux
+ 
+-`endif  /* LIBSV_MUXES_ONEHOT_MUX */
+
++`endif  /* LIBSV_MUXES_ONEHOT_MUX */

patches/bespoke-silicon-group_basejump_stl_pr706.patch

@@ -0,0 +1,65 @@
+From 8e8cf9ef2b47ec2b0252d9b0bd1430ecbaa209bd Mon Sep 17 00:00:00 2001
+From: taylor-bsg <taylor-bsg@users.noreply.github.com>
+Date: Sat, 16 Nov 2024 10:51:56 -0800
+Subject: [PATCH] Update bsg_serial_in_parallel_out_full.sv
+
+---
+ .../bsg_serial_in_parallel_out_full.sv        | 24 +++++++++++++++----
+ 1 file changed, 19 insertions(+), 5 deletions(-)
+
+diff --git a/bsg_dataflow/bsg_serial_in_parallel_out_full.sv b/bsg_dataflow/bsg_serial_in_parallel_out_full.sv
+index 9be26f725..cc94f6be7 100644
+--- a/bsg_dataflow/bsg_serial_in_parallel_out_full.sv
++++ b/bsg_dataflow/bsg_serial_in_parallel_out_full.sv
+@@ -10,9 +10,16 @@
+  *
+  *  Output is only valid, when the output array is fully assembled.
+  *
+- *  By default, this version has zero bubble.
+- *  Minimize hardware by setting use_minimal_buffering_p=1, which introduces
+- *  1-cycle bubble for every data array received.
++ *  This module allows for the setting of extra_buffers_p, which allows for more
++ *  than minimum number of buffers. If this is set to 0, there will be 1-cycle bubbles
++ *  between parallel deques. By default, extra_buffers_p is set to 1, which allows 
++ *  for no bubbles during standard propagation. The value may also be set to a greater number,
++ *  to allow for greater amounts of buffering.
++ *
++ *  The module currently does not support extra_buffers_p > els_p.
++ *
++ *  use_minimal_buffering_p is a backwards compatible interface that sets extra_buffers_p to 0
++ *  it is ignored if extra_buffers_p is also set.
+  *
+  *  @author tommy   02/2019
+  *  Paul Gao        06/2019
+@@ -28,6 +35,7 @@ module bsg_serial_in_parallel_out_full
+    ,parameter `BSG_INV_PARAM(els_p)
+   ,parameter hi_to_lo_p              = 0
+   ,parameter use_minimal_buffering_p = 0
++  ,parameter extra_buffers_p         = (use_minimal_buffering_p ? 0 : 1)
+   )
+   
+   (input clk_i
+@@ -41,7 +49,13 @@ module bsg_serial_in_parallel_out_full
+   ,output logic                          v_o
+   ,input                                 yumi_i
+   );
+-  
++
++`ifndef BSG_HIDE_FROM_SYNTHESIS 
++  initial
++   assert (extra_buffers_p <= els_p)
++    else $error("%m bsg_serial_in_parallel_out_full does not support extra_buffers_p (%d) > els_p (%d)",extra_buffers_p, els_p);
++`endif
++    
+   localparam lg_els_lp = `BSG_SAFE_CLOG2(els_p);
+    
+   // If send hi_to_lo, reverse the output data array
+@@ -88,7 +102,7 @@ module bsg_serial_in_parallel_out_full
+   for (i = 0; i < els_p; i++) 
+   begin: fifos
+     // Lowest word fifo selection depends on use_minimal_buffering_p
+-    if (i == 0 && use_minimal_buffering_p == 0)
++   if (i < extra_buffers_p)  //(i == 0 && use_minimal_buffering_p == 0)
+       begin: twofifo
+         // Use two element fifo to avoid bubble
+         bsg_two_fifo

patches/bespoke-silicon-group_basejump_stl_pr735.patch

@@ -0,0 +1,27 @@
+From db10f234391121c23fc5a4e47e89408cb3d0b062 Mon Sep 17 00:00:00 2001
+From: Michael Bedford Taylor <taylor-bsg@users.noreply.github.com>
+Date: Tue, 23 Sep 2025 10:48:26 -0700
+Subject: [PATCH] Define BSG_HIDE_FROM_SYNTHESIS_EXPR macro
+
+Add macro for conditional synthesis hiding expression
+---
+ bsg_misc/bsg_defines.sv | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/bsg_misc/bsg_defines.sv b/bsg_misc/bsg_defines.sv
+index 300ba6e0f..005501572 100644
+--- a/bsg_misc/bsg_defines.sv
++++ b/bsg_misc/bsg_defines.sv
+@@ -112,6 +112,12 @@
+   `define BSG_HIDE_FROM_SYNTHESIS
+ `endif
+ 
++`ifdef SYNTHESIS
++`define BSG_HIDE_FROM_SYNTHESIS_EXPR(val)
++`else
++`define BSG_HIDE_FROM_SYNTHESIS_EXPR(val) val
++`endif
++
+ `define BSG_STRINGIFY(x) `"x`"
+ 
+ 

patches/bespoke-silicon-group_bsg_manycore_pr587.patch

@@ -0,0 +1,47 @@
+From ca4295f95872e7bb3f3fc5f5835e91417fc4282d Mon Sep 17 00:00:00 2001
+From: Tommy Jung <tommy.dc.jung@gmail.com>
+Date: Wed, 29 Sep 2021 15:59:40 -0700
+Subject: [PATCH 1/2] fix
+
+---
+ v/vanilla_bean/fcsr.v | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/v/vanilla_bean/fcsr.v b/v/vanilla_bean/fcsr.v
+index 15701854c..762676bc4 100644
+--- a/v/vanilla_bean/fcsr.v
++++ b/v/vanilla_bean/fcsr.v
+@@ -183,8 +183,8 @@ module fcsr
+   // synopsys translate_off
+   always_ff @ (negedge clk_i) begin
+     if (~reset_i) begin
+-      if (v_i & data_v_o) begin
+-        assert(~(|fflags_v_i)) else $error("Exception cannot be accrued while being written by fcsr op.");
++      if (v_i & ((addr_i == `RV32_CSR_FFLAGS_ADDR) || (addr_i == `RV32_CSR_FCSR_ADDR))) begin
++        assert(~(|fflags_v_i)) else $error("[BSG_ERROR] Exception cannot be accrued while being written by fcsr op.");
+       end
+     end
+   end
+
+From 7c314a64bf6a6b6869ac094f9dd2a688163f6eeb Mon Sep 17 00:00:00 2001
+From: Tommy Jung <tommy.dc.jung@gmail.com>
+Date: Wed, 29 Sep 2021 16:09:11 -0700
+Subject: [PATCH 2/2] comment
+
+---
+ v/vanilla_bean/fcsr.v | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/v/vanilla_bean/fcsr.v b/v/vanilla_bean/fcsr.v
+index 762676bc4..383613683 100644
+--- a/v/vanilla_bean/fcsr.v
++++ b/v/vanilla_bean/fcsr.v
+@@ -183,6 +183,8 @@ module fcsr
+   // synopsys translate_off
+   always_ff @ (negedge clk_i) begin
+     if (~reset_i) begin
++      // this assertion checks that there are no fflags exception being accrued
++      // while fflags are being accessed by CSR instruction in ID.
+       if (v_i & ((addr_i == `RV32_CSR_FFLAGS_ADDR) || (addr_i == `RV32_CSR_FCSR_ADDR))) begin
+         assert(~(|fflags_v_i)) else $error("[BSG_ERROR] Exception cannot be accrued while being written by fcsr op.");
+       end

patches/jotego_jtcores_pr1089.patch

@@ -0,0 +1,44 @@
+From a14154d708285a0874383438351658a75a972df6 Mon Sep 17 00:00:00 2001
+From: Rafael Paiva <rafael.paiva@jotego.es>
+Date: Tue, 17 Jun 2025 13:01:21 +0200
+Subject: [PATCH 1/2] Access test mode from OSD menu. Fixes #1088
+
+---
+ cores/s18/cfg/macros.def | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/cores/s18/cfg/macros.def b/cores/s18/cfg/macros.def
+index 845d0afaa..299663054 100644
+--- a/cores/s18/cfg/macros.def
++++ b/cores/s18/cfg/macros.def
+@@ -16,6 +16,7 @@ MCU_START=0x2000
+ 
+ JTFRAME_HEADER=32
+ JTFRAME_IOCTL_RD=16384
++JTFRAME_OSD_TEST
+ 
+ # inputs
+ JTFRAME_JOY_LRUD
+
+From 3722f3dfe5a1aae184149ee76883daa7d67d67f0 Mon Sep 17 00:00:00 2001
+From: Rafael Paiva <rafael.paiva@jotego.es>
+Date: Tue, 17 Jun 2025 13:07:31 +0200
+Subject: [PATCH 2/2] Corrected sprite position in s18. Fixes #1082
+
+---
+ cores/s18/hdl/jts18_video16.v | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/cores/s18/hdl/jts18_video16.v b/cores/s18/hdl/jts18_video16.v
+index 521741be1..be3ac5a4b 100644
+--- a/cores/s18/hdl/jts18_video16.v
++++ b/cores/s18/hdl/jts18_video16.v
+@@ -182,7 +182,7 @@ jts16_tilemap #(.MODEL(MODEL),.HS_END(9'hA0),
+     .s2_pri     ( s2_pri    )
+ );
+ 
+-jts16_obj #(.MODEL(MODEL)) u_obj(
++jts16_obj #(.MODEL(MODEL), .PXL_DLY(9'd17)) u_obj(
+     .rst       ( rst            ),
+     .clk       ( clk            ),
+     .pxl_cen   ( pxl_cen        ),

patches/jotego_jtcores_pr623.patch

@@ -0,0 +1,720 @@
+From 6898da8187ba5cd16f17db7aa4bed864afefefba Mon Sep 17 00:00:00 2001
+From: Gyorgy Szombathelyi <8644936+gyurco@users.noreply.github.com>
+Date: Mon, 15 Apr 2024 19:31:33 +0200
+Subject: [PATCH 1/2] shouse: implement/fix flip flag and other adjustments
+ (#616)
+
+---
+ cores/shouse/hdl/jtshouse_colmix.v         |   2 +-
+ cores/shouse/hdl/jtshouse_obj.v            |  29 +++++++------
+ cores/shouse/hdl/jtshouse_scr.sv           |  46 ++++++++++-----------
+ cores/shouse/hdl/jtshouse_video.v          |   2 +-
+ cores/shouse/ver/dspirit/scenes/5/dump.bin | Bin 0 -> 63552 bytes
+ 5 files changed, 42 insertions(+), 37 deletions(-)
+ create mode 100644 cores/shouse/ver/dspirit/scenes/5/dump.bin
+
+diff --git a/cores/shouse/hdl/jtshouse_colmix.v b/cores/shouse/hdl/jtshouse_colmix.v
+index 5f107ac41..5de26f8a4 100644
+--- a/cores/shouse/hdl/jtshouse_colmix.v
++++ b/cores/shouse/hdl/jtshouse_colmix.v
+@@ -95,7 +95,7 @@ always @(posedge clk, posedge rst) begin
+         pal_dout <= r_cs ? rpal_dout :
+                     g_cs ? gpal_dout :
+                     b_cs ? bpal_dout : mmr_dout;
+-        if( hs ) vwin <= {1'b0,vdump[7:0]}>top && {1'b0,vdump[7:0]}<bottom;
++        if( hs ) vwin <= {1'b0,vdump[7:0]}>=top && {1'b0,vdump[7:0]}<bottom;
+         if( pxl_cen ) hwin <= hadj>=left && hadj<=right;
+     end
+ end
+diff --git a/cores/shouse/hdl/jtshouse_obj.v b/cores/shouse/hdl/jtshouse_obj.v
+index 6aeeaa5c9..d734a7ecb 100644
+--- a/cores/shouse/hdl/jtshouse_obj.v
++++ b/cores/shouse/hdl/jtshouse_obj.v
+@@ -90,25 +90,28 @@ assign rom_swap = {
+ };
+ 
+ always @* begin
+-    ypos  = {1'b0,oram_dout[15:8]}+yoffset;
+-    if( flip ) case(vsize)
+-        0: ypos = ypos + 9'o776; // 16
+-        1: ypos = ypos + 9'o766; //  8
+-        2: ypos = ypos + 9'o16;  // 32
+-        3: ypos = ypos + 9'o762; //  4
++    case(vsize)
++        0: ypos = -(oram_dout[15:8] - 8'd16); // 16
++        1: ypos = -(oram_dout[15:8] - 8'd24); //  8
++        2: ypos = -(oram_dout[15:8]);         // 32
++        3: ypos = -(oram_dout[15:8] - 8'd28); //  4
+     endcase
+-    ydiff = ypos+{1'b0,vrender[7:0]};
+-    // if(debug_bus[4]) ydiff[8] = 0;
++
++    ydiff = (vrender[7:0] + yoffset + 8'h10) - ypos;
++    ydiff[8] = 0;
++
+     case(vsize)
+         0: inzone = ydiff[8-:5]==0; // 16 pxl
+         1: inzone = ydiff[8-:6]==0; //  8 pxl
+         2: inzone = ydiff[8-:4]==0; // 32 pxl
+         3: inzone = ydiff[8-:7]==0; //  4 pxl
+     endcase
++
+     nx_ysub = ydiff[4:0];
+     case( vsize )
+-        0:   nx_ysub[4]   = vos[1];
++        0:   nx_ysub[4:3] = {vos[1], ydiff[3] ^ oram_dout[0]};
+         1,3: nx_ysub[4:3] = vos[1:0];
++        2:   nx_ysub[4:3] = ydiff[4:3] ^ {2{oram_dout[0]}};
+         default:;
+     endcase
+     case( hsize )
+@@ -127,9 +130,10 @@ assign rom_addr  = { pre_addr[17-:11],
+             dr_hsize[0] ? dr_hmsb[0] : pre_addr[6] /* H8 */ };
+ 
+ always @(posedge clk) begin
+-    xoffset  <= pre_xos-9'd3; //+{debug_bus[7],debug_bus};
+-    yoffset  <= pre_yos+9'd2;
++    xoffset  <= pre_xos-(flip ? 9'd3 : 9'd75); //+{debug_bus[7],debug_bus};
++    yoffset  <= pre_yos+(flip ? 9'd1 : -9'd1);
+ end
++
+ // LUT scan
+ always @(posedge clk, posedge rst) begin
+     if( rst ) begin
+@@ -177,7 +181,7 @@ always @(posedge clk, posedge rst) begin
+                 end
+                 3: begin
+                     if( !dr_bsy ) begin
+-                        dr_vmsb  <= ysub[4:3]^{2{vflip}};
++                        dr_vmsb  <= ysub[4:3];
+                         dr_hmsb  <= nx_hmsb;
+                         dr_hsize <= hsize;
+                         case( hsize )
+@@ -213,6 +217,7 @@ always @(posedge clk, posedge rst) begin
+             scan_obj <= 0;
+             st       <= 0;
+             cen      <= 0;
++            half     <= 0;
+         end
+     end
+ end
+diff --git a/cores/shouse/hdl/jtshouse_scr.sv b/cores/shouse/hdl/jtshouse_scr.sv
+index 0e7d1da9c..59838e1c7 100644
+--- a/cores/shouse/hdl/jtshouse_scr.sv
++++ b/cores/shouse/hdl/jtshouse_scr.sv
+@@ -28,7 +28,7 @@ module jtshouse_scr(
+     input             hs,
+     input             vs,
+     input       [8:0] hdump,
+-    input       [8:0] vrender,
++    input       [8:0] vdump,
+     input             flip,
+ 
+     input             cs,
+@@ -64,11 +64,12 @@ parameter  [ 8:0] VB_END = 9'h120;
+ localparam [ 8:0] HMARGIN=9'h8,
+                   HSTART=9'h40-HMARGIN,
+                   HEND=9'd288+HSTART+(HMARGIN<<1); // hdump is non blank from 'h40 to 'h160
+-localparam [15:0] HSCR0= 16'h71,
+-                  HSCR1= HSCR0+16'h2,
+-                  HSCR2= HSCR0+16'h3,
+-                  HSCR3= HSCR0+16'h4,
+-                  VSCR =-16'd26;
++localparam [15:0] VSCR =-16'd28;
++
++wire [15:0] hoff0 = flip ? 16'h71 : -16'h0f;
++wire [15:0] hoff1 = flip ? hoff0 + 16'h2 : hoff0 - 16'h2;
++wire [15:0] hoff2 = flip ? hoff0 + 16'h3 : hoff0 - 16'h3;
++wire [15:0] hoff3 = flip ? hoff0 + 16'h4 : hoff0 - 16'h4;
+ 
+ reg  [15:0] hoff, hpos, vpos;
+ reg  [ 2:0] mlyr, mask_asub, mst;
+@@ -132,11 +133,12 @@ always @(posedge clk, posedge rst) begin
+         if( hs_edge ) begin
+             `ifdef SIMULATION miss  <= !done; `endif
+             hcnt  <= HSTART;
+-            hcnt0 <= -hscr[0][2:0]+HSCR0[2:0];
+-            hcnt1 <= -hscr[1][2:0]+HSCR1[2:0];
+-            hcnt2 <= -hscr[2][2:0]+HSCR2[2:0];
+-            hcnt3 <= -hscr[3][2:0]+HSCR3[2:0];
+-            if(vrender[2:0]==2) lin_row <= vrender[8:3]==6'h24 ? 10'd1 : lin_row+10'd36;
++            hcnt0 <= (-hscr[0][2:0] ^ {3{~flip}})+hoff0[2:0];
++            hcnt1 <= (-hscr[1][2:0] ^ {3{~flip}})+hoff1[2:0];
++            hcnt2 <= (-hscr[2][2:0] ^ {3{~flip}})+hoff2[2:0];
++            hcnt3 <= (-hscr[3][2:0] ^ {3{~flip}})+hoff3[2:0];
++
++            if(vdump[2:0]==0) lin_row <= vdump[8:3]==6'h24 ? 10'd1 : lin_row+10'd36;
+             // if(vrender[2:0]==7) lin_row <= vrender[8:3]==6'h24 ? 10'd1 : lin_row+10'd36;
+             // if(vrender==9'h120 ) lin_row <= 1;
+         end
+@@ -146,20 +148,18 @@ end
+ 
+ always @* begin
+     case( mlyr[1:0] )
+-        0: hoff = HSCR0;
+-        1: hoff = HSCR1;
+-        2: hoff = HSCR2;
+-        3: hoff = HSCR3;
++        0: hoff = hoff0;
++        1: hoff = hoff1;
++        2: hoff = hoff2;
++        3: hoff = hoff3;
+     endcase
++
+     if( mlyr>3 )
+-        { vpos, hpos } = { 7'd0, vrender, 7'd0, hcnt };
++        { vpos, hpos } = { 7'd0, vdump, 7'd0, hcnt };
+     else
+-        { vpos, hpos } = { {7'd0, vrender}-vscr[mlyr[1:0]]+VSCR,
+-                           {7'd0,    hcnt}-hscr[mlyr[1:0]]+hoff};
+-    // if( flip ) begin
+-    //     hpos = -hpos;
+-    //     // vpos = -vpos;
+-    // end
++        { vpos, hpos } = { {7'd0, vdump}-(vscr[mlyr[1:0]] ^ {16{~flip}}) + (flip ? VSCR : -VSCR + 16'd219),
++                           {7'd0,  hcnt}-(hscr[mlyr[1:0]] ^ {16{~flip}}) + hoff};
++
+     // Determines the active layer
+     win    = 5;
+     cprio  = 0;
+@@ -207,7 +207,7 @@ always @(posedge clk, posedge rst) begin
+             end
+             // vpos for the fixed layers has a relationship with the linear counter
+             // changing the octal LSB of the linear start requires an adjustment here
+-            1: mask_asub <= mlyr<4 ? vpos[2:0] : vpos[2:0]+3'd6;
++            1: mask_asub <= vpos[2:0];
+             4: begin
+                 mask[mlyr] <= mask_data;
+                 info[mlyr] <= {cfg_pal[mlyr], tmap_data[13:0], mask_asub, ~hsub+3'd1};
+diff --git a/cores/shouse/hdl/jtshouse_video.v b/cores/shouse/hdl/jtshouse_video.v
+index 4cc2f5e90..522777926 100644
+--- a/cores/shouse/hdl/jtshouse_video.v
++++ b/cores/shouse/hdl/jtshouse_video.v
+@@ -138,7 +138,7 @@ jtshouse_scr #(.VB_END(VB_END)) u_scroll(
+     .clk        ( clk       ),
+ 
+     .hdump      ( hdump     ),
+-    .vrender    ( vrender   ),
++    .vdump      ( vdump     ),
+     .hs         ( hs        ),
+     .vs         ( vs        ),
+     .flip       ( flip      ),
+diff --git a/cores/shouse/ver/dspirit/scenes/5/dump.bin b/cores/shouse/ver/dspirit/scenes/5/dump.bin
+new file mode 100644
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+
+literal 0
+HcmV?d00001
+
+
+From 1725196b51cd0b569edde218e4f21017952287c1 Mon Sep 17 00:00:00 2001
+From: Jose Tejada <jose.tejada@jotego.es>
+Date: Thu, 18 Apr 2024 07:41:37 +0200
+Subject: [PATCH 2/2] shouse: bad scenes
+
+---
+ beta.yaml                                    |   2 --
+ cores/shouse/cfg/mame2mra.toml               |   4 ++--
+ cores/shouse/ver/blastoff/scenes/1/dump.bin  | Bin 0 -> 63552 bytes
+ cores/shouse/ver/blastoff/sim.sh             |   1 +
+ cores/shouse/ver/youkaidk1/scenes/1/dump.bin | Bin 0 -> 63552 bytes
+ cores/shouse/ver/youkaidk1/sim.sh            |   1 +
+ 6 files changed, 4 insertions(+), 4 deletions(-)
+ create mode 100644 cores/shouse/ver/blastoff/scenes/1/dump.bin
+ create mode 120000 cores/shouse/ver/blastoff/sim.sh
+ create mode 100644 cores/shouse/ver/youkaidk1/scenes/1/dump.bin
+ create mode 120000 cores/shouse/ver/youkaidk1/sim.sh
+
+diff --git a/beta.yaml b/beta.yaml
+index 977a6309c..5d4f0016d 100644
+--- a/beta.yaml
++++ b/beta.yaml
+@@ -1,8 +1,6 @@
+ simson: [ mister, pocket ]
+-tmnt:   [ mister, pocket ]
+ shouse: [ mister, pocket ]
+ ngp:    [ mister, pocket ]
+-mx5k:   [ pocket ]
+ kchamp: [ pocket ] # 29th Apr '24
+ commnd: [ pocket ] #  5th May '24
+ # upcoming ports from MiSTer to Pocket
+diff --git a/cores/shouse/cfg/mame2mra.toml b/cores/shouse/cfg/mame2mra.toml
+index 42722d6fe..72b5ff862 100644
+--- a/cores/shouse/cfg/mame2mra.toml
++++ b/cores/shouse/cfg/mame2mra.toml
+@@ -6,7 +6,7 @@ debug = { machines=[
+     # Key type 3
+     "rompers", # hangs up after notice - vertical game
+     "ws",      # needs 2-byte key ID
+-    "dangseed",
++    # "dangseed",
+     "tankfrce",
+     "pistoldm",
+     "blastoff",
+@@ -15,7 +15,7 @@ debug = { machines=[
+     "berabohm",
+     "blazer",
+     "boxyboy",
+-    "dspirit",
++    # "dspirit",
+     "faceoff",
+     "mmaze",
+     "quester",
+diff --git a/cores/shouse/ver/blastoff/scenes/1/dump.bin b/cores/shouse/ver/blastoff/scenes/1/dump.bin
+new file mode 100644
+index 0000000000000000000000000000000000000000..b5b7a3cd2807a9163796150616151e19333eb45d
+GIT binary patch
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+--- /dev/null
++++ b/cores/shouse/ver/blastoff/sim.sh
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++../game/sim.sh
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+zU|9$14)0pOY;O68tc0FE_L`one%<AjuK2%px%=66-l1{*^Gat`tr1Jy{^HD=uWVnl
+zL|5^W`~gXkL0<NqfSDM+9?FNW#hAPi!?5h6lF>rEoF^>M*WFPHm3J`;4e;}F6<%Lw
+zyJ|j#5W&B{?xqNf>&w3jKDC&CS2sG;&xL=<zatAO#Q1-4-hkv@!9Mb?#sPfHTBvRe
+zwrqWF`;Kj!H>`bn<+7?rE9X`|TD5#}<?M>`qLD(hIx(6H=D&I1Abfv8|LrgMKUI39
+zp^^U*RAc|EW|tLYC5HJqb?(Q15h0XxbG5gyk$WnF!()^C4aysBX6Ge-|DdQaH@k0Q
+zR4De6TLtn&@o|3M)9RWb15$-=0(7^w@$TbckIfvrngG<*y?bo`f(i3iY<{uso3pR&
+zS-r4)Xvw^lTQ{y-wX$;Z=z+=M3g<3B_5MFkhcbltxI5X58k`=_@lS1-0V8205S9eM
+z2qVTC^P8QWy}g4Y{}_c_bVM3|jjxh_0EmyY@E>xpkZHzW)8|R!@&{)0j_QFu`L6~*
+zjsN)r(-R{@6&?;2{G$dQJ~*gHc(3?Ag8xy;IU~wuYQ|sFR&~vE)k7h?|DHPi2gaQ&
+z9bCJSknk8qSbV=>WBUy+b|c~Q*Bv+&A@;bvAOG#$f6cUQ`qx8x{L}mYO%FTWOBtXH
+zPzERil!1ql0eb#_7)O=*L>ZtAPzERil!2xhpy&Ul`JsC$1C#;E0A+wO@USs(#^=}$
+z@%&$M=l8r`K$Y@NZe*-}Dzs6hg3m@_A$!VPRjFVjj|BfRTU9FBzPxRN#8j~7)qHMO
+zXsb%qcCBdF3btif$nLUQRVvtgOMzvzs#LUnMO#b-o3H6oDAeau!LF>9#~0SBQqiuF
+z7xK243N~MIj98veMZ5O%M|oRJ1>3w>K02>fl?ry{OLAwvzL<*kK6w;xi>Y8Ud*nfR
+zwW?Iye^egI?-x_iu9jQ#wwQ``jksS-1)KM*i|8Mp>Qlb*h|^uZJuwx_AC=pRczmj=
+zFYd1vQqisv_ls$B%JWP_i+u2@P+!{y;{N(nD4=EY%!G;j@TstyxA~S-sbE`)wkj3u
+z`Nt05V`^2YXzzVau*Foc&7Bkg)T+|v*g_p3_M|?gHsyoP2hCBS`K4lo+U@K3aDg2F
+zh~`J#xVA10T!ZQS9|G6F%itPggjgBm&-q41{1bt~#Nf9E<v}tW2i*84gX*{c1C)<3
+AK>z>%
+
+literal 0
+HcmV?d00001
+
+diff --git a/cores/shouse/ver/youkaidk1/sim.sh b/cores/shouse/ver/youkaidk1/sim.sh
+new file mode 120000
+index 000000000..471dfd676
+--- /dev/null
++++ b/cores/shouse/ver/youkaidk1/sim.sh
+@@ -0,0 +1 @@
++../game/sim.sh
+

patches/jotego_jtcores_pr871.patch

@@ -0,0 +1,101 @@
+From ff7d29947b1c90587ee04c9d3275efc8b0ead0ce Mon Sep 17 00:00:00 2001
+From: Rafael Paiva <rafael.paiva@jotego.es>
+Date: Tue, 12 Nov 2024 10:20:52 +0100
+Subject: [PATCH 1/3] Removed duplicated video macros
+
+---
+ cores/wwfss/cfg/macros.def | 5 -----
+ 1 file changed, 5 deletions(-)
+
+diff --git a/cores/wwfss/cfg/macros.def b/cores/wwfss/cfg/macros.def
+index 168d6aade..4d6c83113 100644
+--- a/cores/wwfss/cfg/macros.def
++++ b/cores/wwfss/cfg/macros.def
+@@ -17,11 +17,6 @@ JTFRAME_BA2_START=0x088000
+ SCR_START        =0x0A8000
+ JTFRAME_BA3_START=0x128000
+ 
+-# Video
+-JTFRAME_WIDTH=256
+-JTFRAME_HEIGHT=240
+-JTFRAME_PXLCLK=6
+-
+ # memories
+ debug JTFRAME_IOCTL_RD=5632
+ # scroll
+
+From 5a624b6e86770747ced7b6fcd55b8f65a4a4e638 Mon Sep 17 00:00:00 2001
+From: Rafael Paiva <rafael.paiva@jotego.es>
+Date: Tue, 12 Nov 2024 15:18:42 +0100
+Subject: [PATCH 2/3] widening screen image in wwfss
+
+---
+ cores/wwfss/cfg/macros.def      | 2 +-
+ cores/wwfss/hdl/jtwwfss_video.v | 4 ++--
+ 2 files changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/cores/wwfss/cfg/macros.def b/cores/wwfss/cfg/macros.def
+index 4d6c83113..8654c0e4d 100644
+--- a/cores/wwfss/cfg/macros.def
++++ b/cores/wwfss/cfg/macros.def
+@@ -6,7 +6,7 @@ JTFRAME_JOY_DULR
+ JTFRAME_CREDITS
+ 
+ # Video
+-JTFRAME_WIDTH=248
++JTFRAME_WIDTH=256
+ JTFRAME_HEIGHT=240
+ JTFRAME_PXLCLK=6
+ 
+diff --git a/cores/wwfss/hdl/jtwwfss_video.v b/cores/wwfss/hdl/jtwwfss_video.v
+index 64273e340..a983bc6f7 100644
+--- a/cores/wwfss/hdl/jtwwfss_video.v
++++ b/cores/wwfss/hdl/jtwwfss_video.v
+@@ -92,9 +92,9 @@ jtframe_vtimer #(
+     .VCNT_END   ( 9'd271    ),
+     .VS_START   ( 9'h106    ),
+     .HS_START   ( 9'h1b5    ),
+-    .HB_START   ( 9'h181    ),
++    .HB_START   ( 9'h188    ),
+     .HJUMP      ( 1         ),
+-    .HB_END     ( 9'd9      ),
++    .HB_END     ( 9'd8      ),
+     .HINIT      ( 9'd255    )
+ )   u_vtimer(
+     .clk        ( clk       ),
+
+From 1179d0dfe0b492cce91b06deaff1fe1b1d8ee6a5 Mon Sep 17 00:00:00 2001
+From: Rafael Paiva <rafael.paiva@jotego.es>
+Date: Thu, 14 Nov 2024 11:00:13 +0100
+Subject: [PATCH 3/3] Relocated blanking to eliminate left quirks and added
+ offset to character layer to erase right side quirks
+
+---
+ cores/wwfss/hdl/jtwwfss_video.v | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/cores/wwfss/hdl/jtwwfss_video.v b/cores/wwfss/hdl/jtwwfss_video.v
+index a983bc6f7..c28df06e2 100644
+--- a/cores/wwfss/hdl/jtwwfss_video.v
++++ b/cores/wwfss/hdl/jtwwfss_video.v
+@@ -92,9 +92,9 @@ jtframe_vtimer #(
+     .VCNT_END   ( 9'd271    ),
+     .VS_START   ( 9'h106    ),
+     .HS_START   ( 9'h1b5    ),
+-    .HB_START   ( 9'h188    ),
++    .HB_START   ( 9'h189    ),
+     .HJUMP      ( 1         ),
+-    .HB_END     ( 9'd8      ),
++    .HB_END     ( 9'd9      ),
+     .HINIT      ( 9'd255    )
+ )   u_vtimer(
+     .clk        ( clk       ),
+@@ -114,7 +114,7 @@ jtframe_vtimer #(
+ jtframe_tilemap #(
+     .CW ( 12 ),
+     .PW (  7 ),
+-    .HDUMP_OFFSET( 0 )
++    .HDUMP_OFFSET( 1 )
+ ) u_char(
+     .rst        ( rst       ),
+     .clk        ( clk       ),

patches/jotego_jtcores_pr951.patch

@@ -0,0 +1,22 @@
+From 1c6685d3aac6f31e0e44f5d6a4b7b4980a099fee Mon Sep 17 00:00:00 2001
+From: Rafael Paiva <rafael.paiva@jotego.es>
+Date: Mon, 27 Jan 2025 10:03:45 +0100
+Subject: [PATCH] Fixes #950
+
+---
+ modules/jtframe/hdl/video/rotate/unsigned_division.v | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/modules/jtframe/hdl/video/rotate/unsigned_division.v b/modules/jtframe/hdl/video/rotate/unsigned_division.v
+index fc4fab246..079213200 100644
+--- a/modules/jtframe/hdl/video/rotate/unsigned_division.v
++++ b/modules/jtframe/hdl/video/rotate/unsigned_division.v
+@@ -37,7 +37,7 @@ always @(posedge clk) begin
+ 					quot<=dividend;
+ 					div<=divisor;
+ 					/* verilator lint_off WIDTH */
+-					bitcounter<={widthlog2{1'd1}};
++					bitcounter<=(widthlog2[widthlog2-1:0]-1'd1);
+ 					/* verilator lint_on WIDTH */
+ 					state <= RUN;
+ 				end			

patches/lowRISC_ibex_pr1821.patch

@@ -0,0 +1,16 @@
+diff --git a/dv/verilator/simple_system_cosim/ibex_simple_system_cosim_checker.sv b/dv/verilator/simple_system_cosim/ibex_simple_system_cosim_checker.sv
+index dcc4d04..34ac615 100644
+--- a/dv/verilator/simple_system_cosim/ibex_simple_system_cosim_checker.sv
++++ b/dv/verilator/simple_system_cosim/ibex_simple_system_cosim_checker.sv
+@@ -21,10 +21,10 @@ module ibex_simple_system_cosim_checker #(
+   always_ff @(posedge clk_i or negedge rst_ni) begin
+     if (!rst_ni) begin
+       cosim_created_o <= 1'b0;
+       created_mhpm_counter_num_o <= 32'd0;
+     end else if (cfg_valid_i) begin
+       cosim_created_o <= SecureIbex || ICache || (local_pmp_num_regions == 0) || (local_pmp_granularity == 0);
+-      created_mhpm_counter_num_o <= 32'd0;
++      created_mhpm_counter_num_o <= mhpm_counter_num_i;
+     end
+   end
+ endmodule

patches/lowRISC_ibex_pr1872.patch

@@ -0,0 +1,110 @@
+From b2790682686f4235df6aac10d4952c527156ba0b Mon Sep 17 00:00:00 2001
+From: Greg Chadwick <gac@lowrisc.org>
+Date: Tue, 25 Oct 2022 17:02:17 +0100
+Subject: [PATCH 1/3] [rtl] Fix ebreak debug cause
+
+We should only indicate an ebreak debug cause if an ebreak leads to a
+debug entry (otherwise when single stepping over an ebreak that traps to
+an exception we incorrectly enter debug mode with an ebreak cause).
+---
+ rtl/ibex_controller.sv | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/rtl/ibex_controller.sv b/rtl/ibex_controller.sv
+index 4becb9e65..036a4d7d3 100644
+--- a/rtl/ibex_controller.sv
++++ b/rtl/ibex_controller.sv
+@@ -430,11 +430,11 @@ module ibex_controller #(
+   // The decision to enter debug_mode and the write of the cause to DCSR happen
+   // in seperate steps within the FSM. Hence, there are a small number of cycles
+   // where a change in external stimulus can cause the cause to be recorded incorrectly.
+-  assign debug_cause_d = trigger_match_i   ? DBG_CAUSE_TRIGGER :
+-                         ebrk_insn_prio    ? DBG_CAUSE_EBREAK  :
+-                         debug_req_i       ? DBG_CAUSE_HALTREQ :
+-                         do_single_step_d  ? DBG_CAUSE_STEP    :
+-                                             DBG_CAUSE_NONE ;
++  assign debug_cause_d = trigger_match_i                    ? DBG_CAUSE_TRIGGER :
++                         ebrk_insn_prio & ebreak_into_debug ? DBG_CAUSE_EBREAK  :
++                         debug_req_i                        ? DBG_CAUSE_HALTREQ :
++                         do_single_step_d                   ? DBG_CAUSE_STEP    :
++                                                              DBG_CAUSE_NONE ;
+ 
+   always_ff @(posedge clk_i or negedge rst_ni) begin
+     if (!rst_ni) begin
+
+From 06a7b5c32c319cba92bc6dc46b25009942f70900 Mon Sep 17 00:00:00 2001
+From: Greg Chadwick <gac@lowrisc.org>
+Date: Tue, 25 Oct 2022 17:22:55 +0100
+Subject: [PATCH 2/3] [dv] Remove `cp_insn_trigger_exception` coverpoint
+
+This coverpoint does not make sense. The hardware breakpoint is
+triggered as the instruction moves into the ID/EX stage so it never has
+a chance to take an exception (it effectively never begins executing).
+---
+ doc/03_reference/coverage_plan.rst         | 3 ---
+ dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv | 2 --
+ 2 files changed, 5 deletions(-)
+
+diff --git a/doc/03_reference/coverage_plan.rst b/doc/03_reference/coverage_plan.rst
+index 49cea59f7..67204af9a 100644
+--- a/doc/03_reference/coverage_plan.rst
++++ b/doc/03_reference/coverage_plan.rst
+@@ -223,9 +223,6 @@ Furthermore they can all occur together and must be appropriately prioritised (c
+ * ``cp_debug_req`` - External debug request.
+ * ``cp_single_step_taken`` - Instruction executed when debug single step enabled.
+ * ``cp_insn_trigger_enter_debug`` - Instruction matches hardware trigger point.
+-
+-  * ``cp_insn_trigger_exception`` - Instruction matching trigger point causes exception
+-
+ * ``cp_debug_mode`` - Ibex operating in debug mode.
+ * ``irq_wfi_cross``, ``debug_wfi_cross`` - Debug and Interrupt whilst sleeping with WFI
+ 
+diff --git a/dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv b/dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv
+index bf457fb7a..43a16be86 100644
+--- a/dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv
++++ b/dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv
+@@ -499,8 +499,6 @@ interface core_ibex_fcov_if import ibex_pkg::*; (
+     `DV_FCOV_EXPR_SEEN(pipe_flush, id_stage_i.controller_i.fcov_pipe_flush)
+     `DV_FCOV_EXPR_SEEN(single_step_taken, id_stage_i.controller_i.fcov_debug_single_step_taken)
+     `DV_FCOV_EXPR_SEEN(insn_trigger_enter_debug, instr_id_matches_trigger_q)
+-    `DV_FCOV_EXPR_SEEN(insn_trigger_exception, instr_id_matches_trigger_q &&
+-                                               id_stage_i.controller_i.fcov_pipe_flush)
+ 
+     cp_nmi_taken: coverpoint ((fcov_irqs[5] || fcov_irqs[4])) iff
+                              (id_stage_i.controller_i.fcov_interrupt_taken);
+
+From 87009e6100be7f8ca73cec5b0932f7252eadbedb Mon Sep 17 00:00:00 2001
+From: Greg Chadwick <gac@lowrisc.org>
+Date: Tue, 25 Oct 2022 17:36:31 +0100
+Subject: [PATCH 3/3] [dv] Add single step over exception coverpoint
+
+---
+ doc/03_reference/coverage_plan.rst         | 1 +
+ dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv | 2 ++
+ 2 files changed, 3 insertions(+)
+
+diff --git a/doc/03_reference/coverage_plan.rst b/doc/03_reference/coverage_plan.rst
+index 67204af9a..9eae30caa 100644
+--- a/doc/03_reference/coverage_plan.rst
++++ b/doc/03_reference/coverage_plan.rst
+@@ -222,6 +222,7 @@ Furthermore they can all occur together and must be appropriately prioritised (c
+ 
+ * ``cp_debug_req`` - External debug request.
+ * ``cp_single_step_taken`` - Instruction executed when debug single step enabled.
++* ``cp_single_step_exception`` - Single step over an instruction that takes an exception.
+ * ``cp_insn_trigger_enter_debug`` - Instruction matches hardware trigger point.
+ * ``cp_debug_mode`` - Ibex operating in debug mode.
+ * ``irq_wfi_cross``, ``debug_wfi_cross`` - Debug and Interrupt whilst sleeping with WFI
+diff --git a/dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv b/dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv
+index 43a16be86..ac5aa1c4b 100644
+--- a/dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv
++++ b/dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv
+@@ -498,6 +498,8 @@ interface core_ibex_fcov_if import ibex_pkg::*; (
+     `DV_FCOV_EXPR_SEEN(debug_entry_id, id_stage_i.controller_i.fcov_debug_entry_id)
+     `DV_FCOV_EXPR_SEEN(pipe_flush, id_stage_i.controller_i.fcov_pipe_flush)
+     `DV_FCOV_EXPR_SEEN(single_step_taken, id_stage_i.controller_i.fcov_debug_single_step_taken)
++    `DV_FCOV_EXPR_SEEN(single_step_exception, id_stage_i.controller_i.do_single_step_d &&
++                                              id_stage_i.controller_i.fcov_pipe_flush)
+     `DV_FCOV_EXPR_SEEN(insn_trigger_enter_debug, instr_id_matches_trigger_q)
+ 
+     cp_nmi_taken: coverpoint ((fcov_irqs[5] || fcov_irqs[4])) iff

patches/lowRISC_ibex_pr1917.patch

@@ -0,0 +1,46 @@
+From 9bb189212dea610813d26606d40efd118be13d63 Mon Sep 17 00:00:00 2001
+From: Greg Chadwick <gac@lowrisc.org>
+Date: Wed, 9 Nov 2022 11:58:51 +0000
+Subject: [PATCH] [fpv] Fix linting issues in oustanding access tracking logic
+
+This refactors the code to avoid a -1 index access that caused no issues
+in functional verification but caused lint errors and is problematic for
+formal tools.
+
+Fixes #1799
+---
+ rtl/ibex_top.sv | 18 ++++++++++++------
+ 1 file changed, 12 insertions(+), 6 deletions(-)
+
+diff --git a/rtl/ibex_top.sv b/rtl/ibex_top.sv
+index 84b0f9cd1..d8a9f8916 100644
+--- a/rtl/ibex_top.sv
++++ b/rtl/ibex_top.sv
+@@ -1117,15 +1117,21 @@ module ibex_top import ibex_pkg::*; #(
+         end
+       end
+ 
+-      always_comb begin
+-        pending_dside_accesses_d[i] = pending_dside_accesses_shifted[i];
++      if (i == 0) begin : g_track_first_entry
++        always_comb begin
++          pending_dside_accesses_d[i] = pending_dside_accesses_shifted[i];
+ 
+-        if (data_req_o && data_gnt_i) begin
+-          if (i == 0 && !pending_dside_accesses_shifted[i].valid) begin
++          if (data_req_o && data_gnt_i && !pending_dside_accesses_shifted[i].valid) begin
+             pending_dside_accesses_d[i].valid = 1'b1;
+             pending_dside_accesses_d[i].is_read = ~data_we_o;
+-          end else if (pending_dside_accesses_shifted[i - 1].valid &
+-                       !pending_dside_accesses_shifted[i].valid) begin
++          end
++        end
++      end else begin : g_track_other_entries
++        always_comb begin
++          pending_dside_accesses_d[i] = pending_dside_accesses_shifted[i];
++
++          if (data_req_o && data_gnt_i && pending_dside_accesses_shifted[i - 1].valid &&
++              !pending_dside_accesses_shifted[i].valid) begin
+             pending_dside_accesses_d[i].valid = 1'b1;
+             pending_dside_accesses_d[i].is_read = ~data_we_o;
+           end

patches/lowRISC_ibex_pr2241.patch

@@ -0,0 +1,25 @@
+From e5be77accf43484fcb49c8d46005643b580ada9b Mon Sep 17 00:00:00 2001
+From: Rupert Swarbrick <rswarbrick@lowrisc.org>
+Date: Mon, 6 Jan 2025 17:09:19 +0000
+Subject: [PATCH] [rtl] Drive oh_raddr_*_err if RdataMuxCheck=0
+
+These errors aren't detected or reported if the mux is disabled, but
+the RTL didn't actually drive them at all.
+---
+ rtl/ibex_register_file_fpga.sv | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/rtl/ibex_register_file_fpga.sv b/rtl/ibex_register_file_fpga.sv
+index 73e0afab2..2414d771d 100644
+--- a/rtl/ibex_register_file_fpga.sv
++++ b/rtl/ibex_register_file_fpga.sv
+@@ -155,6 +155,9 @@ module ibex_register_file_fpga #(
+ 
+     // async_read b
+     assign rdata_b_o = (raddr_b_i == '0) ? WordZeroVal : mem[raddr_b_i];
++
++    assign oh_raddr_a_err = 1'b0;
++    assign oh_raddr_b_err = 1'b0;
+   end
+ 
+   // we select

patches/lowRISC_opentitan_pr28698.patch

@@ -0,0 +1,54 @@
+From dd4312990004ba9b434c4aa63788449b04c1be7c Mon Sep 17 00:00:00 2001
+From: Rupert Swarbrick <rswarbrick@lowrisc.org>
+Date: Mon, 10 Nov 2025 12:57:14 +0000
+Subject: [PATCH] Revert "[otbn,dv] Correctly stringify names in otbn_env_cov"
+
+This reverts commit e9986ef486ed9a58064d7927ae574bb20a150af5, which
+was both "terribly clever" and wrong. Sigh.
+
+To avoid someone making the same mistake again, I'm also expanding the
+documentation comment to explain how it was supposed to work.
+
+Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
+---
+ hw/ip/otbn/dv/uvm/env/otbn_env_cov.sv | 14 ++++++++++----
+ 1 file changed, 10 insertions(+), 4 deletions(-)
+
+diff --git a/hw/ip/otbn/dv/uvm/env/otbn_env_cov.sv b/hw/ip/otbn/dv/uvm/env/otbn_env_cov.sv
+index ed2b56a6dfa73..f1359b127aff0 100644
+--- a/hw/ip/otbn/dv/uvm/env/otbn_env_cov.sv
++++ b/hw/ip/otbn/dv/uvm/env/otbn_env_cov.sv
+@@ -76,8 +76,12 @@ class otbn_env_cov extends cip_base_env_cov #(.CFG_T(otbn_env_cfg));
+ 
+   // A macro used for coverpoints for mnemonics. This expands to entries like
+   //
+-  //    bins mnem_add = {"mnem_add"};
+-`define DEF_MNEM_BIN(NAME) bins NAME = {`"NAME`"}
++  //    bins mnem_add = {mnem_add};
++  //
++  // The right hand side here is a some string variable defined with DEF_MNEM in the previous block
++  // of code. This is sort of equivalent to something like bins mnem_add = {"add"}, but it wraps the
++  // string literal in a variable, which turns out to be needed for coverage with VCS.
++`define DEF_MNEM_BIN(NAME) bins NAME = {NAME}
+ 
+   // Generate a bin for each mnemonic except ECALL
+ `define DEF_MNEM_BINS_EXCEPT_ECALL                                     \
+@@ -109,14 +113,16 @@ class otbn_env_cov extends cip_base_env_cov #(.CFG_T(otbn_env_cfg));
+     `DEF_MNEM_BIN(mnem_bn_mov); `DEF_MNEM_BIN(mnem_bn_movr);           \
+     `DEF_MNEM_BIN(mnem_bn_wsrr); `DEF_MNEM_BIN(mnem_bn_wsrw);
+ 
+-  // Equivalents of DEF_MNEM and DEF_MNEM_BINp, but for external CSRs. Again, we want to use the CSR
++  // Equivalents of DEF_MNEM and DEF_MNEM_BIN, but for external CSRs. Again, we want to use the CSR
+   // names as bins in coverpoints and need sized literals.
+ `define DEF_CSR(CSR_NAME, STR) \
+   csr_str_t CSR_NAME = csr_str_t'(STR)
+   `DEF_CSR(csr_load_checksum, "load_checksum");
+   `DEF_CSR(csr_ctrl, "ctrl");
+ `undef DEF_CSR
+-`define DEF_CSR_BIN(NAME) bins NAME = {`"NAME`"}
++  // Define a bin for a CSR. This is analogous to DEF_MNEM_BIN (which has a detailed explanation of
++  // how it works).
++`define DEF_CSR_BIN(NAME) bins NAME = {NAME}
+ 
+   // Cross one, two or three coverpoints with mnemonic_cp.
+   //

patches/muneeb-mbytes_pulpino__spi_master__ip_verification_pr50.patch

@@ -0,0 +1,844 @@
+From 44f3a36ec3f032cbc13066cf52b529032178f88e Mon Sep 17 00:00:00 2001
+From: Muneeb <muneebullashariff@gmail.com>
+Date: Mon, 21 Feb 2022 11:54:11 +0530
+Subject: [PATCH] Integrating RAL into the testbench
+
+---
+ sim/questa_sim/makefile                       |   1 -
+ sim/verif_compile.f                           |   6 +
+ .../apb_master_driver_bfm.sv                  |  20 +++-
+ .../apb_master_agent/apb_master_adapter.sv    |  94 +++++++++++++++
+ .../apb_master_agent/apb_master_agent.sv      |   8 +-
+ .../apb_master_agent/apb_master_pkg.sv        |   1 +
+ .../apb_master_seq_item_converter.sv          |   6 +-
+ src/dv/hvl_top/env/apb_reg_predictor.sv       |  50 ++++++++
+ .../hvl_top/env/pulpino_spi_master_ip_env.sv  |  20 ++++
+ .../env/pulpino_spi_master_ip_env_config.sv   |   4 +
+ .../env/pulpino_spi_master_ip_env_pkg.sv      |   3 +
+ ...pulpino_spi_master_ip_virtual_sequencer.sv |   4 +
+ src/dv/hvl_top/test/apb_simple_reg_test.sv    | 102 +++++++++++++++++
+ .../test/pulpino_spi_master_ip_base_test.sv   |  10 ++
+ .../test/pulpino_spi_master_ip_test_pkg.sv    |   7 ++
+ .../test/reg_sequences/apb_reg_seq_pkg.sv     |  31 +++++
+ .../apb_simple_write_read_reg_seq.sv          | 108 ++++++++++++++++++
+ .../pulpino_spi_master_ip_virtual_seq_pkg.sv  |   4 +
+ .../virtual_simple_reg_seq.sv                 |  57 +++++++++
+ 19 files changed, 525 insertions(+), 11 deletions(-)
+ create mode 100644 src/dv/hvl_top/apb_master_agent/apb_master_adapter.sv
+ create mode 100644 src/dv/hvl_top/env/apb_reg_predictor.sv
+ create mode 100644 src/dv/hvl_top/test/apb_simple_reg_test.sv
+ create mode 100644 src/dv/hvl_top/test/reg_sequences/apb_reg_seq_pkg.sv
+ create mode 100644 src/dv/hvl_top/test/reg_sequences/apb_simple_write_read_reg_seq.sv
+ create mode 100644 src/dv/hvl_top/test/virtual_sequences/virtual_simple_reg_seq.sv
+
+diff --git a/sim/questa_sim/makefile b/sim/questa_sim/makefile
+index 7622f10..96cf504 100755
+--- a/sim/questa_sim/makefile
++++ b/sim/questa_sim/makefile
+@@ -124,7 +124,6 @@ simulate:
+ 	vsim -vopt \
+ 	work.hvl_top \
+ 	work.hdl_top \
+-	work.apb_spi_master \
+ 	-voptargs=+acc=npr \
+ 	-assertdebug \
+ 	+UVM_TESTNAME=$(test) \
+diff --git a/sim/verif_compile.f b/sim/verif_compile.f
+index ebac7db..4ce3333 100644
+--- a/sim/verif_compile.f
++++ b/sim/verif_compile.f
+@@ -1,15 +1,21 @@
+ +incdir+../../src/dv/hvl_top/test/sequences/master_sequences/
+ +incdir+../../src/dv/hvl_top/test/sequences/slave_sequences/
+++incdir+../../src/dv/hvl_top/test/reg_sequences/
+ +incdir+../../src/dv/hvl_top/test/virtual_sequences/
+ +incdir+../../src/dv/hvl_top/apb_master_agent/
+ +incdir+../../src/dv/hvl_top/spi_slave_agent/
+ +incdir+../../src/dv/hvl_top/env/virtual_sequencer/
+ +incdir+../../src/dv/hvl_top/env/
+ +incdir+../../src/dv/hvl_top/test/
+++incdir+../../src/dv/systemRDL
+++incdir+../../src/dv/systemRDL/output
+ ../../src/dv/globals/apb_master_global_pkg.sv
+ ../../src/dv/globals/spi_slave_global_pkg.sv
+ ../../src/dv/hvl_top/apb_master_agent/apb_master_pkg.sv
+ ../../src/dv/hvl_top/spi_slave_agent/spi_slave_pkg.sv
++../../src/dv/systemRDL/output/spi_master_defines_pkg.svh
++../../src/dv/systemRDL/output/spi_master_uvm_pkg.sv
++../../src/dv/hvl_top/test/reg_sequences/apb_reg_seq_pkg.sv
+ ../../src/dv/hvl_top/test/sequences/master_sequences/apb_master_seq_pkg.sv
+ ../../src/dv/hvl_top/test/sequences/slave_sequences/spi_slave_seq_pkg.sv
+ ../../src/dv/hvl_top/env/pulpino_spi_master_ip_env_pkg.sv
+diff --git a/src/dv/hdl_top/apb_master_agent_bfm/apb_master_driver_bfm.sv b/src/dv/hdl_top/apb_master_agent_bfm/apb_master_driver_bfm.sv
+index 6945afb..5fa0157 100644
+--- a/src/dv/hdl_top/apb_master_agent_bfm/apb_master_driver_bfm.sv
++++ b/src/dv/hdl_top/apb_master_agent_bfm/apb_master_driver_bfm.sv
+@@ -154,10 +154,13 @@ interface apb_master_driver_bfm (input  bit   pclk,
+     penable   <= 1'b1;
+     
+     `uvm_info("DEBUG_NADEEM",$sformatf("pready=%0d",pready), UVM_HIGH);
+-    if(pready == 0) begin
+       detect_wait_state(data_packet);
+-    end
+-    `uvm_info("DEBUG_MSHA",$sformatf("wait_apb_access_state=%0d and state=%0d",state.name(),state), UVM_NONE);
++    // MSHA: if(pready == 0) begin
++    // MSHA:   detect_wait_state(data_packet);
++    // MSHA: end
++    // MSHA: `uvm_info("DEBUG_MSHA",$sformatf("wait_apb_access_state=%0d and state=%0d",state.name(),state), UVM_NONE);
++
++
+   endtask: waiting_in_access_state
+ 
+   //--------------------------------------------------------------------------------------------
+@@ -169,12 +172,13 @@ interface apb_master_driver_bfm (input  bit   pclk,
+   //--------------------------------------------------------------------------------------------
+   task detect_wait_state(inout apb_transfer_char_s data_packet);
+    
+-    @(posedge pclk);
+-    `uvm_info(name,$sformatf("DETECT_WAIT_STATE"),UVM_HIGH);
++     @(posedge pclk);
++     `uvm_info(name,$sformatf("DETECT_WAIT_STATE"),UVM_HIGH);
+ 
+     while(pready==0) begin
+       `uvm_info(name,"WAIT_STATE_DETECTED",UVM_HIGH);
+       @(posedge pclk);
++      state=WAIT_STATE;
+       data_packet.no_of_wait_states++;
+     end
+ 
+@@ -185,7 +189,11 @@ interface apb_master_driver_bfm (input  bit   pclk,
+     end
+ 
+     data_packet.pslverr = pslverr;
+-    state=WAIT_STATE;
++
++    // TODO(mshariff): Add logic for making it work for ACCESS to SETUP phase
++    state=IDLE;
++    penable <= 1'b0;
++    pselx <= 'b0;
+ 
+ //     `uvm_info("DEBUG_MSHA", $sformatf("drive_apb_access state = %0s and state = %0d",
+ //                                      state.name(), state), UVM_NONE);
+diff --git a/src/dv/hvl_top/apb_master_agent/apb_master_adapter.sv b/src/dv/hvl_top/apb_master_agent/apb_master_adapter.sv
+new file mode 100644
+index 0000000..1697744
+--- /dev/null
++++ b/src/dv/hvl_top/apb_master_agent/apb_master_adapter.sv
+@@ -0,0 +1,94 @@
++`ifndef APB_MASTER_ADAPTER_INCLUDED_
++`define APB_MASTER_ADAPTER_INCLUDED_
++
++//--------------------------------------------------------------------------------------------
++// Class: apb_master_adapter
++// Converts register transactions to APB transactions and vice-versa
++//--------------------------------------------------------------------------------------------
++class apb_master_adapter extends uvm_reg_adapter;
++  `uvm_object_utils(apb_master_adapter)
++
++  //-------------------------------------------------------
++  // Externally defined Tasks and Functions
++  //-------------------------------------------------------
++  extern function new(string name = "apb_master_adapter");
++  extern function uvm_sequence_item reg2bus( const ref uvm_reg_bus_op rw );
++  extern function void bus2reg( uvm_sequence_item bus_item,
++                              ref uvm_reg_bus_op rw );
++endclass : apb_master_adapter
++
++//--------------------------------------------------------------------------------------------
++// Construct: new
++//
++// Parameters:
++//  name - apb_master_adapter
++//--------------------------------------------------------------------------------------------
++function apb_master_adapter::new(string name = "apb_master_adapter");
++  super.new(name);
++
++  // Set default values for the two variables based on bus protocol
++  // APB does not support either, so both are turned off
++  supports_byte_enable = 0;
++  provides_responses   = 0;
++endfunction : new
++
++//--------------------------------------------------------------------------------------------
++// Function : reg2bus
++// Used for converting register sequences to apb bus transactions
++//--------------------------------------------------------------------------------------------
++function uvm_sequence_item apb_master_adapter::reg2bus( const ref uvm_reg_bus_op rw );
++  apb_master_tx apb_tx
++            = apb_master_tx::type_id::create("apb_master_tx");
++
++  if ( rw.kind == UVM_READ )
++  begin
++    apb_tx.pwrite = READ;
++  end
++  else if ( rw.kind == UVM_WRITE ) 
++  begin 
++    apb_tx.pwrite = WRITE;
++    apb_tx.pwdata = rw.data;
++    apb_tx.pstrb  = 4'b1111; //4bytes 
++  end
++
++  apb_tx.paddr = rw.addr;
++
++  // Assuming these address range falls in the slave0 domain
++  // TODO(mshariff): Need to add more logic to be intelligent to pick correct pselx value
++  apb_tx.pselx = SLAVE_0; 
++
++  `uvm_info(get_type_name(), $sformatf("The converted reg2bus packet is %s\n",apb_tx.sprint()), UVM_HIGH);
++
++  return apb_tx;
++endfunction: reg2bus
++
++//--------------------------------------------------------------------------------------------
++// Function: bus2reg
++// Used for converting apb bus transactions into register transactions
++//--------------------------------------------------------------------------------------------
++function void apb_master_adapter::bus2reg( uvm_sequence_item bus_item,
++                                          ref uvm_reg_bus_op rw );
++  // MSHA:jelly_bean_transaction jb_tx;
++  apb_master_tx apb_tx; 
++
++  if ( ! $cast( apb_tx, bus_item ) ) begin
++     `uvm_fatal( get_name(),
++                 "bus_item is not of the apb_master_tx type." )
++     return;
++  end
++
++  // Assuming these address range falls in the slave0 domain
++  // TODO(mshariff): Need to add more logic to be intelligent to pick correct pselx value
++  apb_tx.pselx = SLAVE_0; 
++
++  rw.kind = ( apb_tx.pwrite == READ ) ? UVM_READ : UVM_WRITE;
++  rw.addr = apb_tx.paddr;
++  rw.data = apb_tx.prdata;
++  rw.status = UVM_IS_OK;
++
++  `uvm_info(get_type_name(), $sformatf("The converted bus2reg packet is %s\n",apb_tx.sprint()), UVM_HIGH);
++
++endfunction: bus2reg
++
++`endif
++
+diff --git a/src/dv/hvl_top/apb_master_agent/apb_master_agent.sv b/src/dv/hvl_top/apb_master_agent/apb_master_agent.sv
+index 3dd67c1..f6808ec 100644
+--- a/src/dv/hvl_top/apb_master_agent/apb_master_agent.sv
++++ b/src/dv/hvl_top/apb_master_agent/apb_master_agent.sv
+@@ -25,9 +25,13 @@ class apb_master_agent extends uvm_agent;
+   //Declaring a handle for apb_master monitor proxy 
+   apb_master_monitor_proxy apb_master_mon_proxy_h;
+ 
+-  // Variable: master_coverage
++  // Variable: apb_master_cov_h
+   // Decalring a handle for master_coverage
+   apb_master_coverage apb_master_cov_h;
++
++  // Variable: apb_reg_adapter_h
++  // Declaring a handle for apb_master_adapter
++  apb_master_adapter apb_reg_adapter_h;
+     
+   //-------------------------------------------------------
+   // Externally defined Tasks and Functions
+@@ -81,6 +85,8 @@ function void apb_master_agent::build_phase(uvm_phase phase);
+   if(apb_master_agent_cfg_h.has_coverage) begin
+     apb_master_cov_h = apb_master_coverage::type_id::create("apb_master_cov_h",this);
+   end
++
++  apb_reg_adapter_h = apb_master_adapter::type_id::create("apb_reg_adapter_h"); 
+ endfunction : build_phase
+ 
+ //--------------------------------------------------------------------------------------------
+diff --git a/src/dv/hvl_top/apb_master_agent/apb_master_pkg.sv b/src/dv/hvl_top/apb_master_agent/apb_master_pkg.sv
+index dc8cffa..95d3954 100644
+--- a/src/dv/hvl_top/apb_master_agent/apb_master_pkg.sv
++++ b/src/dv/hvl_top/apb_master_agent/apb_master_pkg.sv
+@@ -23,6 +23,7 @@ package apb_master_pkg;
+   `include "apb_master_tx.sv"
+   `include "apb_master_seq_item_converter.sv"
+   `include "apb_master_cfg_converter.sv"
++  `include "apb_master_adapter.sv"
+   `include "apb_master_sequencer.sv"
+   `include "apb_master_driver_proxy.sv"
+   `include "apb_master_monitor_proxy.sv"
+diff --git a/src/dv/hvl_top/apb_master_agent/apb_master_seq_item_converter.sv b/src/dv/hvl_top/apb_master_agent/apb_master_seq_item_converter.sv
+index 9496670..6664c4e 100644
+--- a/src/dv/hvl_top/apb_master_agent/apb_master_seq_item_converter.sv
++++ b/src/dv/hvl_top/apb_master_agent/apb_master_seq_item_converter.sv
+@@ -13,7 +13,7 @@ class apb_master_seq_item_converter extends uvm_object;
+   //-------------------------------------------------------
+   extern function new(string name = "apb_master_seq_item_converter");
+   extern static function void from_class(input apb_master_tx input_conv, output apb_transfer_char_s output_conv);
+-  extern static function void to_class(input apb_transfer_char_s input_conv, output apb_master_tx
++  extern static function void to_class(input apb_transfer_char_s input_conv, ref apb_master_tx
+   output_conv_h);
+   extern function void do_print(uvm_printer printer);
+ 
+@@ -82,8 +82,8 @@ endfunction: from_class
+ // name - apb_master_tx, apb_transfer_char_s
+ //--------------------------------------------------------------------------------------------
+ function void apb_master_seq_item_converter::to_class(input apb_transfer_char_s input_conv, 
+-                                                      output apb_master_tx output_conv_h);
+-  output_conv_h = new();
++                                                      ref apb_master_tx output_conv_h);
++  //output_conv_h = new();
+ 
+   `uvm_info("apb_master_seq_item_conv",$sformatf("------------------------------------------------"),UVM_HIGH);
+   
+diff --git a/src/dv/hvl_top/env/apb_reg_predictor.sv b/src/dv/hvl_top/env/apb_reg_predictor.sv
+new file mode 100644
+index 0000000..448313c
+--- /dev/null
++++ b/src/dv/hvl_top/env/apb_reg_predictor.sv
+@@ -0,0 +1,50 @@
++`ifndef APB_REG_PREDICTOR_INCLUDED_
++`define APB_REG_PREDICTOR_INCLUDED_
++
++//--------------------------------------------------------------------------------------------
++// Class: apb_reg_predictor
++// Used for updating the RAL in explicit prediction model 
++//--------------------------------------------------------------------------------------------
++class apb_reg_predictor #(type BUSTYPE=int) extends uvm_reg_predictor #(BUSTYPE);
++  `uvm_component_param_utils(apb_reg_predictor#(BUSTYPE))
++
++  //-------------------------------------------------------
++  // Externally defined Tasks and Functions
++  //-------------------------------------------------------
++  extern function new(string name = "apb_reg_predictor", uvm_component parent);
++  extern function void write(BUSTYPE tr);
++endclass : apb_reg_predictor
++
++//--------------------------------------------------------------------------------------------
++// Construct: new
++//
++// Parameters:
++//  name - apb_reg_predictor
++//--------------------------------------------------------------------------------------------
++function apb_reg_predictor::new(string name = "apb_reg_predictor", uvm_component parent);
++  super.new(name, parent);
++endfunction : new
++
++//--------------------------------------------------------------------------------------------
++// Function: write
++// Over-riding the function to explicitly update the RAL and 
++// to call the sample_values method for coverage
++//--------------------------------------------------------------------------------------------
++function void apb_reg_predictor::write(BUSTYPE tr);
++  uvm_reg rg;
++  uvm_reg_bus_op rw;
++
++  // Calling the parent function
++  super.write(tr);
++
++  // MSHA: // Getting the register handle
++  // MSHA: adapter.bus2reg(tr,rw);
++  // MSHA: rg = map.get_reg_by_offset(rw.addr,(rw.kind == UVM_READ));
++
++  // MSHA: // Sampling the coverage
++  // MSHA: rg.sample_values();
++    
++endfunction: write
++
++`endif
++
+diff --git a/src/dv/hvl_top/env/pulpino_spi_master_ip_env.sv b/src/dv/hvl_top/env/pulpino_spi_master_ip_env.sv
+index 58549a7..9452345 100644
+--- a/src/dv/hvl_top/env/pulpino_spi_master_ip_env.sv
++++ b/src/dv/hvl_top/env/pulpino_spi_master_ip_env.sv
+@@ -36,6 +36,11 @@ class pulpino_spi_master_ip_env extends uvm_env;
+   // Handle for spi slave collector
+   spi_slave_collector spi_slave_coll_h;
+ 
++  // Variable: apb_reg_predictor_h
++  // Handle for apb_reg_predictor#(apb_master_tx)
++  typedef apb_reg_predictor#(apb_master_tx) apb_reg_predictor_t;
++  apb_reg_predictor_t apb_reg_predictor_h;
++
+   // Variable: spi_slave_agent_cfg_h;
+   // Handle for spi slave agent configuration
+   //spi_slave_agent_config spi_slave_agent_cfg_h[];
+@@ -105,6 +110,7 @@ function void pulpino_spi_master_ip_env::build_phase(uvm_phase phase);
+   apb_master_coll_h = apb_master_collector::type_id::create("apb_master_coll_h",this);
+   spi_slave_coll_h  = spi_slave_collector::type_id::create("spi_slave_coll_h",this);
+ 
++  apb_reg_predictor_h = apb_reg_predictor_t::type_id::create("apb_reg_predictor_h", this);
+ endfunction : build_phase
+ 
+ //--------------------------------------------------------------------------------------------
+@@ -121,6 +127,8 @@ function void pulpino_spi_master_ip_env::connect_phase(uvm_phase phase);
+     foreach(spi_slave_agent_h[i]) begin
+       pulpino_spi_master_ip_virtual_seqr_h.spi_slave_seqr_h = spi_slave_agent_h[i].spi_slave_seqr_h;
+     end
++
++    pulpino_spi_master_ip_virtual_seqr_h.env_config_h = pulpino_spi_master_ip_env_config_h; 
+   end
+   
+   apb_master_agent_h.apb_master_mon_proxy_h.apb_master_analysis_port.connect(apb_master_coll_h.apb_master_coll_imp_port);
+@@ -136,6 +144,18 @@ function void pulpino_spi_master_ip_env::connect_phase(uvm_phase phase);
+   //foreach(spi_slave_agent_h[i]) begin
+   //  spi_slave_agent_h[i].slave_mon_proxy_h.slave_analysis_port.connect(pulpino_spi_master_ip_scoreboard_h.spi_slave_analysis_fifo.analysis_export);
+   //end
++
++  // RAL connections
++  if ( pulpino_spi_master_ip_env_config_h.spi_master_reg_block.get_parent() == null ) begin // if the top-level env
++     pulpino_spi_master_ip_env_config_h.spi_master_reg_block.default_map.set_sequencer( 
++                                                  .sequencer( apb_master_agent_h.apb_master_seqr_h ),
++                                                  .adapter( apb_master_agent_h.apb_reg_adapter_h ) );
++  end
++  pulpino_spi_master_ip_env_config_h.spi_master_reg_block.default_map.set_auto_predict( .on( 0 ) );
++  apb_reg_predictor_h.map  = pulpino_spi_master_ip_env_config_h.spi_master_reg_block.default_map;
++  apb_reg_predictor_h.adapter = apb_master_agent_h.apb_reg_adapter_h;
++  apb_master_agent_h.apb_master_mon_proxy_h.apb_master_analysis_port.connect( apb_reg_predictor_h.bus_in );
++
+   
+   endfunction : connect_phase
+ 
+diff --git a/src/dv/hvl_top/env/pulpino_spi_master_ip_env_config.sv b/src/dv/hvl_top/env/pulpino_spi_master_ip_env_config.sv
+index fc02020..527d44e 100644
+--- a/src/dv/hvl_top/env/pulpino_spi_master_ip_env_config.sv
++++ b/src/dv/hvl_top/env/pulpino_spi_master_ip_env_config.sv
+@@ -28,6 +28,10 @@ class pulpino_spi_master_ip_env_config extends uvm_object;
+   // Dynamic array of slave agnet configuration handles
+   spi_slave_agent_config spi_slave_agent_cfg_h[];
+ 
++  // Variable: spi_master_reg_block
++  // Registers block handle for spi master module
++  spi_master_apb_if spi_master_reg_block;
++
+   //-------------------------------------------------------
+   // Externally defined Tasks and Functions
+   //-------------------------------------------------------
+diff --git a/src/dv/hvl_top/env/pulpino_spi_master_ip_env_pkg.sv b/src/dv/hvl_top/env/pulpino_spi_master_ip_env_pkg.sv
+index ec72fd8..09d5457 100644
+--- a/src/dv/hvl_top/env/pulpino_spi_master_ip_env_pkg.sv
++++ b/src/dv/hvl_top/env/pulpino_spi_master_ip_env_pkg.sv
+@@ -20,11 +20,14 @@ package pulpino_spi_master_ip_env_pkg;
+   import spi_slave_global_pkg::*;
+   import apb_master_pkg::*;
+   import spi_slave_pkg::*;
++  import spi_master_defines_pkg::*;
++  import spi_master_uvm_pkg::*;
+ 
+   //-------------------------------------------------------
+   // Including the required files
+   //-------------------------------------------------------
+   `include "pulpino_spi_master_ip_env_config.sv"
++  `include "apb_reg_predictor.sv"
+   `include "pulpino_spi_master_ip_virtual_sequencer.sv"
+   `include "pulpino_spi_master_ip_scoreboard.sv"
+   `include "apb_master_collector.sv"
+diff --git a/src/dv/hvl_top/env/virtual_sequencer/pulpino_spi_master_ip_virtual_sequencer.sv b/src/dv/hvl_top/env/virtual_sequencer/pulpino_spi_master_ip_virtual_sequencer.sv
+index e96700f..210ba64 100644
+--- a/src/dv/hvl_top/env/virtual_sequencer/pulpino_spi_master_ip_virtual_sequencer.sv
++++ b/src/dv/hvl_top/env/virtual_sequencer/pulpino_spi_master_ip_virtual_sequencer.sv
+@@ -16,6 +16,10 @@ class pulpino_spi_master_ip_virtual_sequencer extends uvm_sequencer#(uvm_sequenc
+   // Declaring slave sequencer handle
+   spi_slave_sequencer spi_slave_seqr_h;
+ 
++  //Variable: env_config_h
++  //Declaring handle for pulpino_spi_master_ip_env_config_object
++  pulpino_spi_master_ip_env_config env_config_h;  
++
+   //-------------------------------------------------------
+   // Externally defined Tasks and Functions
+   //-------------------------------------------------------
+diff --git a/src/dv/hvl_top/test/apb_simple_reg_test.sv b/src/dv/hvl_top/test/apb_simple_reg_test.sv
+new file mode 100644
+index 0000000..7ae095d
+--- /dev/null
++++ b/src/dv/hvl_top/test/apb_simple_reg_test.sv
+@@ -0,0 +1,102 @@
++`ifndef APB_SIMPLE_REG_TEST_INCLUDED_
++`define APB_SIMPLE_REG_TEST_INCLUDED_
++
++//--------------------------------------------------------------------------------------------
++// Class: apb_simple_reg_test
++// <Description_here>
++//--------------------------------------------------------------------------------------------
++class apb_simple_reg_test extends pulpino_spi_master_ip_base_test;
++  `uvm_component_utils(apb_simple_reg_test)
++
++  //-------------------------------------------------------
++  // Externally defined Tasks and Functions
++  //-------------------------------------------------------
++  extern function new(string name = "apb_simple_reg_test", uvm_component parent = null);
++  extern virtual function void build_phase(uvm_phase phase);
++  extern virtual function void connect_phase(uvm_phase phase);
++  extern virtual function void end_of_elaboration_phase(uvm_phase phase);
++  extern virtual function void start_of_simulation_phase(uvm_phase phase);
++  extern virtual task run_phase(uvm_phase phase);
++
++endclass : apb_simple_reg_test
++
++//--------------------------------------------------------------------------------------------
++// Construct: new
++//
++// Parameters:
++//  name - apb_simple_reg_test
++//  parent - parent under which this component is created
++//--------------------------------------------------------------------------------------------
++function apb_simple_reg_test::new(string name = "apb_simple_reg_test",
++                                 uvm_component parent = null);
++  super.new(name, parent);
++endfunction : new
++
++//--------------------------------------------------------------------------------------------
++// Function: build_phase
++// <Description_here>
++//
++// Parameters:
++//  phase - uvm phase
++//--------------------------------------------------------------------------------------------
++function void apb_simple_reg_test::build_phase(uvm_phase phase);
++  super.build_phase(phase);
++endfunction : build_phase
++
++//--------------------------------------------------------------------------------------------
++// Function: connect_phase
++// <Description_here>
++//
++// Parameters:
++//  phase - uvm phase
++//--------------------------------------------------------------------------------------------
++function void apb_simple_reg_test::connect_phase(uvm_phase phase);
++  super.connect_phase(phase);
++endfunction : connect_phase
++
++//--------------------------------------------------------------------------------------------
++// Function: end_of_elaboration_phase
++// <Description_here>
++//
++// Parameters:
++//  phase - uvm phase
++//--------------------------------------------------------------------------------------------
++function void apb_simple_reg_test::end_of_elaboration_phase(uvm_phase phase);
++  super.end_of_elaboration_phase(phase);
++endfunction  : end_of_elaboration_phase
++
++//--------------------------------------------------------------------------------------------
++// Function: start_of_simulation_phase
++// <Description_here>
++//
++// Parameters:
++//  phase - uvm phase
++//--------------------------------------------------------------------------------------------
++function void apb_simple_reg_test::start_of_simulation_phase(uvm_phase phase);
++  super.start_of_simulation_phase(phase);
++endfunction : start_of_simulation_phase
++
++//--------------------------------------------------------------------------------------------
++// Task: run_phase
++// <Description_here>
++//
++// Parameters:
++//  phase - uvm phase
++//--------------------------------------------------------------------------------------------
++task apb_simple_reg_test::run_phase(uvm_phase phase);
++  virtual_simple_reg_seq reg_vseq_h;
++
++  reg_vseq_h = virtual_simple_reg_seq::type_id::create("reg_vseq_h");
++
++  `uvm_info(get_type_name(),$sformatf("apb_simple_reg_test"),UVM_LOW);
++
++  phase.raise_objection(this);
++
++  reg_vseq_h.start(pulpino_spi_master_ip_env_h.pulpino_spi_master_ip_virtual_seqr_h); 
++
++  phase.drop_objection(this);
++
++endtask : run_phase
++
++`endif
++
+diff --git a/src/dv/hvl_top/test/pulpino_spi_master_ip_base_test.sv b/src/dv/hvl_top/test/pulpino_spi_master_ip_base_test.sv
+index d35fe3f..bb99584 100644
+--- a/src/dv/hvl_top/test/pulpino_spi_master_ip_base_test.sv
++++ b/src/dv/hvl_top/test/pulpino_spi_master_ip_base_test.sv
+@@ -18,6 +18,10 @@ class pulpino_spi_master_ip_base_test extends uvm_test;
+   //Declaring a handle for env_cfg_h
+   pulpino_spi_master_ip_env_config pulpino_spi_master_ip_env_cfg_h;
+ 
++  // Variable: spi_master_reg_block
++  // Registers block for spi master module
++  spi_master_apb_if spi_master_reg_block;
++
+   //-------------------------------------------------------
+   // Externally defined Tasks and Functions
+   //-------------------------------------------------------
+@@ -80,6 +84,12 @@ function void pulpino_spi_master_ip_base_test::setup_pulpino_spi_master_ip_env_c
+   uvm_config_db#(pulpino_spi_master_ip_env_config)::set(this,"*","pulpino_spi_master_ip_env_config",pulpino_spi_master_ip_env_cfg_h);
+   //`uvm_info(get_type_name(),$sformatf("\npulpino_spi_master_ip_ENV_CONFIG\n%s",pulpino_spi_master_ip_env_cfg_h.sprint()),UVM_LOW);
+ 
++  // Creation of RAL
++  spi_master_reg_block = spi_master_apb_if::type_id::create("spi_master_reg_block");
++  spi_master_reg_block.build();
++  spi_master_reg_block.lock_model();
++
++  pulpino_spi_master_ip_env_cfg_h.spi_master_reg_block = this.spi_master_reg_block;
+ endfunction : setup_pulpino_spi_master_ip_env_config
+ 
+ //--------------------------------------------------------------------------------------------
+diff --git a/src/dv/hvl_top/test/pulpino_spi_master_ip_test_pkg.sv b/src/dv/hvl_top/test/pulpino_spi_master_ip_test_pkg.sv
+index 5d5f9cb..b737dc3 100644
+--- a/src/dv/hvl_top/test/pulpino_spi_master_ip_test_pkg.sv
++++ b/src/dv/hvl_top/test/pulpino_spi_master_ip_test_pkg.sv
+@@ -22,6 +22,8 @@ package pulpino_spi_master_ip_test_pkg;
+   import apb_master_pkg::*;
+   import spi_slave_pkg::*;
+   import pulpino_spi_master_ip_env_pkg::*;
++  import spi_master_uvm_pkg::*;
++  import spi_master_defines_pkg::*;
+   import apb_master_seq_pkg::*;
+   import spi_slave_seq_pkg::*;
+   import pulpino_spi_master_ip_virtual_seq_pkg::*;
+@@ -49,6 +51,11 @@ package pulpino_spi_master_ip_test_pkg;
+ 
+   `include "pulpino_spi_master_ip_rand_test.sv"
+ 
++  //-------------------------------------------------------
++  // Register tests
++  //-------------------------------------------------------
++  `include "apb_simple_reg_test.sv"
++
+   endpackage : pulpino_spi_master_ip_test_pkg
+ 
+ `endif
+diff --git a/src/dv/hvl_top/test/reg_sequences/apb_reg_seq_pkg.sv b/src/dv/hvl_top/test/reg_sequences/apb_reg_seq_pkg.sv
+new file mode 100644
+index 0000000..f142896
+--- /dev/null
++++ b/src/dv/hvl_top/test/reg_sequences/apb_reg_seq_pkg.sv
+@@ -0,0 +1,31 @@
++`ifndef APB_REG_SEQ_PKG_INCLUDED_
++`define APB_REG_SEQ_PKG_INCLUDED_
++
++//--------------------------------------------------------------------------------------------
++// Package : apb_reg_seq_pkg
++// Includes all the master register seq files declared
++//--------------------------------------------------------------------------------------------
++package apb_reg_seq_pkg;
++
++  //-------------------------------------------------------
++  // Importing UVM Pkg
++  //-------------------------------------------------------
++  `include "uvm_macros.svh"
++  import apb_master_global_pkg::*;
++  import spi_slave_global_pkg::*;
++  import uvm_pkg::*;
++  //import apb_master_pkg::*;
++  import spi_master_defines_pkg::*;
++  import spi_master_uvm_pkg::*;
++  
++  //-------------------------------------------------------
++  // Including required apb master seq files
++  //-------------------------------------------------------
++  //`include "apb_master_base_seq.sv"
++  // TODO(mshariff): Need to find a place for complinig spi_master_defines.svh file
++  `include "spi_master_defines.svh"
++
++  `include "apb_simple_write_read_reg_seq.sv"
++endpackage : apb_reg_seq_pkg
++
++`endif
+diff --git a/src/dv/hvl_top/test/reg_sequences/apb_simple_write_read_reg_seq.sv b/src/dv/hvl_top/test/reg_sequences/apb_simple_write_read_reg_seq.sv
+new file mode 100644
+index 0000000..7e0c651
+--- /dev/null
++++ b/src/dv/hvl_top/test/reg_sequences/apb_simple_write_read_reg_seq.sv
+@@ -0,0 +1,108 @@
++`ifndef APB_SIMPLE_WRITE_READ_REG_SEQ_INCLUDED_
++`define APB_SIMPLE_WRITE_READ_REG_SEQ_INCLUDED_
++
++//--------------------------------------------------------------------------------------------
++// Class: apb_simple_write_read_reg_seq
++// Simple register sequence for write and read of registers 
++//--------------------------------------------------------------------------------------------
++class apb_simple_write_read_reg_seq extends uvm_reg_sequence;
++  `uvm_object_utils(apb_simple_write_read_reg_seq)
++
++  //-------------------------------------------------------
++  // Externally defined Tasks and Functions
++  //-------------------------------------------------------
++  extern function new(string name = "apb_simple_write_read_reg_seq");
++  extern task body();
++endclass : apb_simple_write_read_reg_seq
++
++//--------------------------------------------------------------------------------------------
++// Construct: new
++//
++// Parameters:
++//  name - apb_simple_write_read_reg_seq
++//--------------------------------------------------------------------------------------------
++function apb_simple_write_read_reg_seq::new(string name = "apb_simple_write_read_reg_seq");
++  super.new(name);
++endfunction : new
++
++//--------------------------------------------------------------------------------------------
++// Task: body
++// For register access
++//--------------------------------------------------------------------------------------------
++task apb_simple_write_read_reg_seq::body();
++  spi_master_apb_if spi_master_reg_block;
++  uvm_reg_map spi_reg_map;
++
++  uvm_status_e    status;
++  uvm_reg_data_t  wdata;
++  uvm_reg_data_t  rdata;
++
++  $cast( spi_master_reg_block, model );
++
++  //spi_reg_map = spi_master_reg_block.default_map;
++  spi_reg_map = spi_master_reg_block.get_map_by_name("SPI_MASTER_MAP_ABP_IF");
++
++  //-------------------------------------------------------
++  // STATUS Register                                        
++  //-------------------------------------------------------
++
++  // Writing into the register
++  begin
++    bit [3:0] cs_value;
++    cs_value = SLAVE_0;
++    `uvm_info(get_type_name(), $sformatf("Write :: Register cs_value = %0b",cs_value), UVM_LOW)
++
++    // Setting a value 
++    wdata = (wdata & (~ `MASK_STATUS_CS)) | (cs_value << `POS_STATUS_CS);
++    // Setting the required bits
++    wdata = wdata | `MASK_STATUS_RD | `MASK_STATUS_WR; 
++    // Clearing the required bits
++    wdata = wdata & (~`MASK_STATUS_QRD) & (~`MASK_STATUS_QWR);
++
++  end
++  // wdata = 32'h03; 
++  spi_master_reg_block.STATUS.write(.status(status), .value(wdata), .path(UVM_FRONTDOOR), 
++                                    .map(spi_reg_map), .parent(this));
++
++  `uvm_info(get_type_name(), $sformatf("Write :: Register = %0s Data = 32'h%0h",
++                                        spi_master_reg_block.STATUS.get_full_name(),
++                                        wdata), UVM_HIGH);                                   
++
++  // Reading into the register
++  spi_master_reg_block.STATUS.read(.status(status), .value(rdata), .path(UVM_FRONTDOOR), 
++                                   .map(spi_reg_map), .parent(this));
++
++  `uvm_info(get_type_name(), $sformatf("Read :: Register = %0s Data = 32'h%0h",
++                                        spi_master_reg_block.STATUS.get_full_name(),
++                                        rdata), UVM_HIGH);                                   
++
++  //-------------------------------------------------------
++  // CLKDIV Register                                        
++  //-------------------------------------------------------
++  // Writing into the register
++  begin
++    bit [7:0] clkdiv_value;
++    clkdiv_value = 8'd8;
++    wdata = 0;
++    wdata = (wdata & (~ `MASK_CLKDIV_CLKDIV)) | (clkdiv_value << `POS_CLKDIV_CLKDIV);
++  end
++  spi_master_reg_block.CLKDIV.write(.status(status), .value(wdata), .path(UVM_FRONTDOOR), 
++                                    .map(spi_reg_map), .parent(this));
++
++  `uvm_info(get_type_name(), $sformatf("Write :: Register = %0s Data = 32'h%0h",
++                                        spi_master_reg_block.CLKDIV.get_full_name(),
++                                        wdata), UVM_HIGH);                                   
++
++  // Reading into the register
++  spi_master_reg_block.CLKDIV.read(.status(status), .value(rdata), .path(UVM_FRONTDOOR), 
++                                   .map(spi_reg_map), .parent(this));
++
++  `uvm_info(get_type_name(), $sformatf("Read :: Register = %0s Data = 32'h%0h",
++                                        spi_master_reg_block.CLKDIV.get_full_name(),
++                                        rdata), UVM_HIGH);                                   
++endtask: body
++
++
++
++`endif
++
+diff --git a/src/dv/hvl_top/test/virtual_sequences/pulpino_spi_master_ip_virtual_seq_pkg.sv b/src/dv/hvl_top/test/virtual_sequences/pulpino_spi_master_ip_virtual_seq_pkg.sv
+index a5039d8..9f5b500 100644
+--- a/src/dv/hvl_top/test/virtual_sequences/pulpino_spi_master_ip_virtual_seq_pkg.sv
++++ b/src/dv/hvl_top/test/virtual_sequences/pulpino_spi_master_ip_virtual_seq_pkg.sv
+@@ -18,11 +18,13 @@ package pulpino_spi_master_ip_virtual_seq_pkg;
+   import apb_master_seq_pkg::*;
+   import spi_slave_seq_pkg::*;
+   import pulpino_spi_master_ip_env_pkg::*;
++  import apb_reg_seq_pkg::*;
+ 
+   //-------------------------------------------------------
+   // Including required apb master seq files
+   //-------------------------------------------------------
+   `include "pulpino_spi_master_ip_virtual_base_seq.sv"
++  
+   `include "pulpino_spi_master_ip_virtual_basic_write_seq.sv"
+   `include "pulpino_spi_master_ip_virtual_basic_read_seq.sv"
+ 
+@@ -42,6 +44,8 @@ package pulpino_spi_master_ip_virtual_seq_pkg;
+ 
+   `include "pulpino_spi_master_ip_virtual_rand_seq.sv"
+ 
++  // Register virtual sequences
++  `include "virtual_simple_reg_seq.sv"
+ 
+   endpackage : pulpino_spi_master_ip_virtual_seq_pkg
+ 
+diff --git a/src/dv/hvl_top/test/virtual_sequences/virtual_simple_reg_seq.sv b/src/dv/hvl_top/test/virtual_sequences/virtual_simple_reg_seq.sv
+new file mode 100644
+index 0000000..e324b9e
+--- /dev/null
++++ b/src/dv/hvl_top/test/virtual_sequences/virtual_simple_reg_seq.sv
+@@ -0,0 +1,57 @@
++`ifndef VIRTUAL_SIMPLE_REG_SEQ_INCLUDED_
++`define VIRTUAL_SIMPLE_REG_SEQ_INCLUDED_
++
++//--------------------------------------------------------------------------------------------
++// Class: virtual_simple_reg_seq
++// <Description_here>
++//--------------------------------------------------------------------------------------------
++class virtual_simple_reg_seq extends pulpino_spi_master_ip_virtual_base_seq;
++  `uvm_object_utils(virtual_simple_reg_seq)
++
++  //-------------------------------------------------------
++  // Externally defined Tasks and Functions
++  //-------------------------------------------------------
++  extern function new(string name = "virtual_simple_reg_seq");
++  extern task body();
++endclass : virtual_simple_reg_seq
++
++//--------------------------------------------------------------------------------------------
++// Construct: new
++//
++// Parameters:
++//  name - virtual_simple_reg_seq
++//--------------------------------------------------------------------------------------------
++function virtual_simple_reg_seq::new(string name = "virtual_simple_reg_seq");
++  super.new(name);
++endfunction : new
++
++//--------------------------------------------------------------------------------------------
++// Task - body
++// Creates a master reqister sequence and slave normal sequence
++//--------------------------------------------------------------------------------------------
++task virtual_simple_reg_seq::body();
++  apb_simple_write_read_reg_seq apb_master_reg_seq_h;
++  spi_fd_basic_slave_seq spi_fd_basic_slave_seq_h;
++
++  super.body();
++
++  fork
++    forever begin : SLAVE_SEQ
++      `uvm_info("slave_vseq",$sformatf("started slave vseq"),UVM_HIGH)
++      spi_fd_basic_slave_seq_h = spi_fd_basic_slave_seq::type_id::create("spi_fd_basic_slave_seq");
++      spi_fd_basic_slave_seq_h.start(p_sequencer.spi_slave_seqr_h);
++      `uvm_info("slave_vseq",$sformatf("ended slave vseq"),UVM_HIGH)
++    end
++  join_none
++
++  `uvm_info("master_vseq",$sformatf("started master vseq"),UVM_HIGH)
++  apb_master_reg_seq_h = apb_simple_write_read_reg_seq::type_id::create("apb_master_reg_seq_h");
++  apb_master_reg_seq_h.model = p_sequencer.env_config_h.spi_master_reg_block;
++  apb_master_reg_seq_h.start(p_sequencer.apb_master_seqr_h);
++  `uvm_info("master_vseq",$sformatf("ended master vseq"),UVM_HIGH)
++
++ endtask : body
++
++
++`endif
++

patches/muneeb-mbytes_pulpino__spi_master__ip_verification_pr56.patch

@@ -0,0 +1,128 @@
+From 29fbccb9f195f253c17ee9733193a3638df3c55c Mon Sep 17 00:00:00 2001
+From: Muneeb <muneebullashariff@gmail.com>
+Date: Mon, 28 Feb 2022 15:34:29 +0530
+Subject: [PATCH] Fixed the issue with SPI monitor sampling, fixes #46
+
+---
+ .../test/pulpino_spi_master_ip_base_test.sv   |  4 +-
+ .../apb_simple_write_read_reg_seq.sv          | 70 ++++++++++---------
+ .../virtual_simple_reg_seq.sv                 |  3 +
+ 3 files changed, 41 insertions(+), 36 deletions(-)
+
+diff --git a/src/dv/hvl_top/test/pulpino_spi_master_ip_base_test.sv b/src/dv/hvl_top/test/pulpino_spi_master_ip_base_test.sv
+index e06b51c..1a05959 100644
+--- a/src/dv/hvl_top/test/pulpino_spi_master_ip_base_test.sv
++++ b/src/dv/hvl_top/test/pulpino_spi_master_ip_base_test.sv
+@@ -151,8 +151,8 @@ function void pulpino_spi_master_ip_base_test::setup_spi_slave_agent_config();
+     pulpino_spi_master_ip_env_cfg_h.spi_slave_agent_cfg_h[i] = spi_slave_agent_config::type_id::create($sformatf("slave_agent_config[%0d]",i));
+     pulpino_spi_master_ip_env_cfg_h.spi_slave_agent_cfg_h[i].slave_id     = i;
+     pulpino_spi_master_ip_env_cfg_h.spi_slave_agent_cfg_h[i].is_active    = uvm_active_passive_enum'(UVM_ACTIVE);
+-    pulpino_spi_master_ip_env_cfg_h.spi_slave_agent_cfg_h[i].spi_mode     = operation_modes_e'(CPOL0_CPHA0);
+-    pulpino_spi_master_ip_env_cfg_h.spi_slave_agent_cfg_h[i].shift_dir    = shift_direction_e'(LSB_FIRST);
++    pulpino_spi_master_ip_env_cfg_h.spi_slave_agent_cfg_h[i].spi_mode     = operation_modes_e'(CPOL0_CPHA1);
++    pulpino_spi_master_ip_env_cfg_h.spi_slave_agent_cfg_h[i].shift_dir    = shift_direction_e'(MSB_FIRST);
+     pulpino_spi_master_ip_env_cfg_h.spi_slave_agent_cfg_h[i].has_coverage = 1;
+     pulpino_spi_master_ip_env_cfg_h.spi_slave_agent_cfg_h[i].spi_type     = SIMPLE_SPI;
+ 
+diff --git a/src/dv/hvl_top/test/reg_sequences/apb_simple_write_read_reg_seq.sv b/src/dv/hvl_top/test/reg_sequences/apb_simple_write_read_reg_seq.sv
+index 7c05062..73e48c2 100644
+--- a/src/dv/hvl_top/test/reg_sequences/apb_simple_write_read_reg_seq.sv
++++ b/src/dv/hvl_top/test/reg_sequences/apb_simple_write_read_reg_seq.sv
+@@ -42,40 +42,6 @@ task apb_simple_write_read_reg_seq::body();
+   //spi_reg_map = spi_master_reg_block.default_map;
+   spi_reg_map = spi_master_reg_block.get_map_by_name("SPI_MASTER_MAP_ABP_IF");
+ 
+-  //-------------------------------------------------------
+-  // STATUS Register                                        
+-  //-------------------------------------------------------
+-
+-  // Writing into the register
+-  begin
+-    bit [3:0] cs_value;
+-    cs_value = SLAVE_0;
+-    `uvm_info(get_type_name(), $sformatf("Write :: Register cs_value = %0b",cs_value), UVM_LOW)
+-
+-    // Setting a value 
+-    wdata = (wdata & (~ `MASK_STATUS_CS)) | (cs_value << `POS_STATUS_CS);
+-    // Setting the required bits
+-    wdata = wdata | `MASK_STATUS_RD | `MASK_STATUS_WR; 
+-    // Clearing the required bits
+-    wdata = wdata & (~`MASK_STATUS_QRD) & (~`MASK_STATUS_QWR);
+-
+-  end
+-  // wdata = 32'h03; 
+-  spi_master_reg_block.STATUS.write(.status(status), .value(wdata), .path(UVM_FRONTDOOR), 
+-                                    .map(spi_reg_map), .parent(this));
+-
+-  `uvm_info(get_type_name(), $sformatf("Write :: Register = %0s Data = 32'h%0h",
+-                                        spi_master_reg_block.STATUS.get_full_name(),
+-                                        wdata), UVM_HIGH);                                   
+-
+-  // Reading into the register
+-  spi_master_reg_block.STATUS.read(.status(status), .value(rdata), .path(UVM_FRONTDOOR), 
+-                                   .map(spi_reg_map), .parent(this));
+-
+-  `uvm_info(get_type_name(), $sformatf("Read :: Register = %0s Data = 32'h%0h",
+-                                        spi_master_reg_block.STATUS.get_full_name(),
+-                                        rdata), UVM_HIGH);                                   
+-
+   //-------------------------------------------------------
+   // CLKDIV Register                                        
+   //-------------------------------------------------------
+@@ -357,6 +323,42 @@ begin
+   `uvm_info("INTERUPT_REG_SEQ",$sformatf("WRITE:: REGISTER : %0s",
+   spi_master_reg_block.INTCFG.get_full_name()),UVM_HIGH)
+ 
++  //-------------------------------------------------------
++  // STATUS Register                                        
++  //-------------------------------------------------------
++
++  // Writing into the register
++  begin
++    bit [3:0] cs_value;
++    cs_value = SLAVE_0;
++    `uvm_info(get_type_name(), $sformatf("Write :: Register cs_value = %0b",cs_value), UVM_LOW)
++
++    // Setting a value 
++    wdata = (wdata & (~ `MASK_STATUS_CS)) | (cs_value << `POS_STATUS_CS);
++    // Setting the required bits
++    //wdata = wdata | `MASK_STATUS_RD | `MASK_STATUS_WR; 
++    wdata = wdata | `MASK_STATUS_WR; 
++    wdata = wdata & (~`MASK_STATUS_RD); 
++    // Clearing the required bits
++    wdata = wdata & (~`MASK_STATUS_QRD) & (~`MASK_STATUS_QWR) & (~`MASK_STATUS_SRST);
++
++  end
++  // wdata = 32'h03; 
++  spi_master_reg_block.STATUS.write(.status(status), .value(wdata), .path(UVM_FRONTDOOR), 
++                                    .map(spi_reg_map), .parent(this));
++
++  `uvm_info(get_type_name(), $sformatf("Write :: Register = %0s Data = 32'h%0h",
++                                        spi_master_reg_block.STATUS.get_full_name(),
++                                        wdata), UVM_HIGH);                                   
++
++  // Reading into the register
++  spi_master_reg_block.STATUS.read(.status(status), .value(rdata), .path(UVM_FRONTDOOR), 
++                                   .map(spi_reg_map), .parent(this));
++
++  `uvm_info(get_type_name(), $sformatf("Read :: Register = %0s Data = 32'h%0h",
++                                        spi_master_reg_block.STATUS.get_full_name(),
++                                        rdata), UVM_HIGH);                                   
++
+ //  `uvm_info("INTERUPT_REG_SEQ",$sformatf("WRITE:: REGISTER : %0s, DATA = 32'h%0h",
+ //  spi_master_reg_block.INTCFG.get_full_name(),wdata),UVM_HIGH)
+ 
+diff --git a/src/dv/hvl_top/test/virtual_sequences/virtual_simple_reg_seq.sv b/src/dv/hvl_top/test/virtual_sequences/virtual_simple_reg_seq.sv
+index e324b9e..f654271 100644
+--- a/src/dv/hvl_top/test/virtual_sequences/virtual_simple_reg_seq.sv
++++ b/src/dv/hvl_top/test/virtual_sequences/virtual_simple_reg_seq.sv
+@@ -48,6 +48,9 @@ task virtual_simple_reg_seq::body();
+   apb_master_reg_seq_h = apb_simple_write_read_reg_seq::type_id::create("apb_master_reg_seq_h");
+   apb_master_reg_seq_h.model = p_sequencer.env_config_h.spi_master_reg_block;
+   apb_master_reg_seq_h.start(p_sequencer.apb_master_seqr_h);
++  // Wait for the slave thread to complete
++  // Additional time - maybe we can add this as drian time
++  #100us;
+   `uvm_info("master_vseq",$sformatf("ended master vseq"),UVM_HIGH)
+ 
+  endtask : body

patches/openhwgroup_cva5_pr7.patch

@@ -0,0 +1,522 @@
+From 6b1d2280d81cf8fa0c7a888970cae7bf40950843 Mon Sep 17 00:00:00 2001
+From: Florian Meisel <meisel@esa.tu-darmstadt.de>
+Date: Mon, 5 Sep 2022 10:59:59 +0200
+Subject: [PATCH 1/3] l2,axi_to_arb: Move be (wstrb) to data FIFO
+
+Fix: If the AXI bus has WREADY=0 and AWREADY=1,
+  the AW handshake (single beat) that CVA5 starts
+  concurrently with the corresponding W handshake
+  will complete first.
+ CVA5 stores `be` (-> WSTRB) in the FIFO for AW requests,
+  even though WSTRB is part of the W handshake.
+ The result is that WSTRB becomes unstable once the AW request finishes.
+-> The fix moves `be` to the write data FIFO.
+
+Signed-off-by: Florian Meisel <meisel@esa.tu-darmstadt.de>
+---
+ core/axi_to_arb.sv                   |  2 +-
+ core/l1_arbiter.sv                   |  3 +-
+ l2_arbiter/l2_arbiter.sv             | 41 +++++++++++++++-------------
+ l2_arbiter/l2_config_and_types.sv    |  6 +++-
+ l2_arbiter/l2_external_interfaces.sv | 28 +++++++++----------
+ 5 files changed, 43 insertions(+), 37 deletions(-)
+
+diff --git a/core/axi_to_arb.sv b/core/axi_to_arb.sv
+index a75ec7a2..2f8cfa6d 100755
+--- a/core/axi_to_arb.sv
++++ b/core/axi_to_arb.sv
+@@ -182,7 +182,7 @@ module axi_to_arb
+ 
+     assign axi_wdata = read_modify_write ? amo_result_r : l2.wr_data;
+ 
+-    assign axi_wstrb =read_modify_write ? '1 : l2.be;
++    assign axi_wstrb = read_modify_write ? '1 : l2.wr_data_be;
+ 
+ 
+     //Done when read request sent, or slave ack on write data
+diff --git a/core/l1_arbiter.sv b/core/l1_arbiter.sv
+index e6cc309f..886e9d08 100755
+--- a/core/l1_arbiter.sv
++++ b/core/l1_arbiter.sv
+@@ -78,6 +78,7 @@ module l1_arbiter
+     //Dcache Specific
+     assign l2.wr_data_push = CONFIG.INCLUDE_DCACHE & (push_ready & l1_request[L1_DCACHE_ID].request & ~l1_request[L1_DCACHE_ID].rnw); //Assumes data cache has highest priority
+     assign l2.wr_data = l1_request[L1_DCACHE_ID].data;
++    assign l2.wr_data_be = l1_request[L1_DCACHE_ID].be;
+ 
+     assign l2.inv_ack = CONFIG.DCACHE.USE_EXTERNAL_INVALIDATIONS ? l1_response[L1_DCACHE_ID].inv_ack : l2.inv_valid;
+     assign l1_response[L1_DCACHE_ID].inv_addr = l2.inv_addr;
+@@ -89,7 +90,6 @@ module l1_arbiter
+         always_comb begin
+             l2_requests[i].addr = l1_request[i].addr[31:2];
+             l2_requests[i].rnw = l1_request[i].rnw;
+-            l2_requests[i].be = l1_request[i].be;
+             l2_requests[i].is_amo = l1_request[i].is_amo;
+             l2_requests[i].amo_type_or_burst_size = l1_request[i].size;
+             l2_requests[i].sub_id = L2_SUB_ID_W'(i);
+@@ -113,7 +113,6 @@ module l1_arbiter
+ 
+     assign l2.addr = l2_requests[arb_sel].addr;
+     assign l2.rnw = l2_requests[arb_sel].rnw;
+-    assign l2.be = l2_requests[arb_sel].be;
+     assign l2.is_amo = l2_requests[arb_sel].is_amo;
+     assign l2.amo_type_or_burst_size = l2_requests[arb_sel].amo_type_or_burst_size;
+     assign l2.sub_id = l2_requests[arb_sel].sub_id;
+diff --git a/l2_arbiter/l2_arbiter.sv b/l2_arbiter/l2_arbiter.sv
+index 900c3c7e..25d39ba2 100755
+--- a/l2_arbiter/l2_arbiter.sv
++++ b/l2_arbiter/l2_arbiter.sv
+@@ -38,19 +38,20 @@ module l2_arbiter
+ 
+     //FIFO interfaces
+     fifo_interface #(.DATA_WIDTH($bits(l2_request_t))) input_fifos [L2_NUM_PORTS-1:0]();
+-    fifo_interface #(.DATA_WIDTH(32)) input_data_fifos [L2_NUM_PORTS-1:0]();
++    fifo_interface #(.DATA_WIDTH($bits(l2_data_request_t))) input_data_fifos [L2_NUM_PORTS-1:0]();
+     fifo_interface #(.DATA_WIDTH(30)) inv_response_fifos [L2_NUM_PORTS-1:0]();
+     fifo_interface #(.DATA_WIDTH(32 + L2_SUB_ID_W)) returndata_fifos [L2_NUM_PORTS-1:0]();
+ 
+ 
+     fifo_interface #(.DATA_WIDTH($bits(l2_mem_request_t))) mem_addr_fifo();
+-    fifo_interface #(.DATA_WIDTH(32)) mem_data_fifo();
++    fifo_interface #(.DATA_WIDTH($bits(l2_data_request_t))) mem_data_fifo();
+ 
+     fifo_interface #(.DATA_WIDTH($bits(l2_data_attributes_t))) data_attributes();
+     fifo_interface #(.DATA_WIDTH(32 + L2_ID_W)) mem_returndata_fifo();
+ 
+     l2_mem_request_t mem_addr_fifo_data_out;
+     l2_request_t requests_in[L2_NUM_PORTS-1:0];
++    l2_data_request_t data_requests_in[L2_NUM_PORTS-1:0];
+ 
+     logic advance;
+     l2_request_t arb_request;
+@@ -70,7 +71,7 @@ module l2_arbiter
+     l2_data_attributes_t new_attr;
+     l2_data_attributes_t current_attr;
+ 
+-    logic [31:0] input_data [L2_NUM_PORTS-1:0];
++    l2_data_request_t input_data [L2_NUM_PORTS-1:0];
+ 
+     l2_mem_return_data_t mem_return_data;
+     l2_return_data_t return_data  [L2_NUM_PORTS-1:0];
+@@ -93,11 +94,10 @@ module l2_arbiter
+ 
+             //Repack input attributes
+             assign requests_in[i].addr = request[i].addr;
+-			assign requests_in[i].be = request[i].be;
+-			assign requests_in[i].rnw = request[i].rnw;
+-			assign requests_in[i].is_amo = request[i].is_amo;
+-			assign requests_in[i].amo_type_or_burst_size = request[i].amo_type_or_burst_size;
+-			assign requests_in[i].sub_id = request[i].sub_id;
++            assign requests_in[i].rnw = request[i].rnw;
++            assign requests_in[i].is_amo = request[i].is_amo;
++            assign requests_in[i].amo_type_or_burst_size = request[i].amo_type_or_burst_size;
++            assign requests_in[i].sub_id = request[i].sub_id;
+             assign input_fifos[i].data_in = requests_in[i];
+ 
+             assign input_fifos[i].pop = input_fifos[i].valid & arb.grantee_v[i] & ~mem_addr_fifo.full;
+@@ -121,12 +121,14 @@ module l2_arbiter
+             assign input_data_fifos[i].push = request[i].wr_data_push;
+             assign input_data_fifos[i].potential_push = request[i].wr_data_push;
+ 
+-            assign input_data_fifos[i].data_in = request[i].wr_data;
++            assign data_requests_in[i].data = request[i].wr_data;
++            assign data_requests_in[i].be = request[i].wr_data_be;
++            assign input_data_fifos[i].data_in = data_requests_in[i];
+ 
+             assign request[i].data_full = input_data_fifos[i].full;
+ 
+             //FIFO instantiation
+-            cva5_fifo #(.DATA_WIDTH(32), .FIFO_DEPTH(L2_INPUT_FIFO_DEPTHS)) input_data_fifo (.*, .fifo(input_data_fifos[i]));
++            cva5_fifo #(.DATA_WIDTH($bits(l2_data_request_t)), .FIFO_DEPTH(L2_INPUT_FIFO_DEPTHS)) input_data_fifo (.*, .fifo(input_data_fifos[i]));
+ 
+             //Arbiter FIFO side
+             assign input_data_fifos[i].pop = (data_attributes.valid && (current_attr.id == i) && ~mem_data_fifo.full);
+@@ -152,7 +154,6 @@ module l2_arbiter
+     assign arb_request = requests[arb.grantee_i];
+ 
+     assign mem_request.addr =  arb_request.addr;
+-    assign mem_request.be =  arb_request.be;
+     assign mem_request.rnw =  arb_request.rnw;
+     assign mem_request.is_amo =  arb_request.is_amo;
+     assign mem_request.amo_type_or_burst_size =  arb_request.amo_type_or_burst_size;
+@@ -162,11 +163,10 @@ module l2_arbiter
+ 
+     //unpack memory request attributes
+     assign mem_addr_fifo_data_out = mem_addr_fifo.data_out;
+-	assign mem.addr = mem_addr_fifo_data_out.addr;
+-	assign mem.rnw = mem_addr_fifo_data_out.rnw;
+-	assign mem.be = mem_addr_fifo_data_out.be;
+-	assign mem.is_amo = mem_addr_fifo_data_out.is_amo;
+-	assign mem.amo_type_or_burst_size = mem_addr_fifo_data_out.amo_type_or_burst_size;
++    assign mem.addr = mem_addr_fifo_data_out.addr;
++    assign mem.rnw = mem_addr_fifo_data_out.rnw;
++    assign mem.is_amo = mem_addr_fifo_data_out.is_amo;
++    assign mem.amo_type_or_burst_size = mem_addr_fifo_data_out.amo_type_or_burst_size;
+     assign mem.id = mem_addr_fifo_data_out.id;
+ 
+     cva5_fifo #(.DATA_WIDTH($bits(l2_mem_request_t)), .FIFO_DEPTH(L2_MEM_ADDR_FIFO_DEPTH))  input_fifo (.*, .fifo(mem_addr_fifo));
+@@ -261,14 +261,17 @@ module l2_arbiter
+ 
+     assign write_done = data_attributes.valid & ~mem_data_fifo.full & (burst_count == current_attr.burst_size);
+ 
+-    cva5_fifo #(.DATA_WIDTH($bits(32)), .FIFO_DEPTH(L2_MEM_ADDR_FIFO_DEPTH))  mem_data (.*, .fifo(mem_data_fifo));
++    cva5_fifo #(.DATA_WIDTH($bits($bits(l2_data_request_t))), .FIFO_DEPTH(L2_MEM_ADDR_FIFO_DEPTH))  mem_data (.*, .fifo(mem_data_fifo));
+ 
+     assign mem_data_fifo.push = data_attributes.valid & ~mem_data_fifo.full & ~current_attr.abort_request;
+     assign mem_data_fifo.potential_push = data_attributes.valid & ~mem_data_fifo.full & ~current_attr.abort_request;
+ 
+     assign mem_data_fifo.data_in = input_data[current_attr.id];
+ 
+-    assign mem.wr_data = mem_data_fifo.data_out;
++    l2_data_request_t mem_data_request;
++    assign mem_data_request = mem_data_fifo.data_out;
++    assign mem.wr_data = mem_data_request.data;
++    assign mem.wr_data_be = mem_data_request.be;
+     assign mem.wr_data_valid = mem_data_fifo.valid;
+     assign mem_data_fifo.pop = mem.wr_data_read;
+ 
+@@ -306,4 +309,4 @@ module l2_arbiter
+         end
+     endgenerate
+ 
+-endmodule
+
++endmodule
+diff --git a/l2_arbiter/l2_config_and_types.sv b/l2_arbiter/l2_config_and_types.sv
+index cd9f8249..66c6057c 100755
+--- a/l2_arbiter/l2_config_and_types.sv
++++ b/l2_arbiter/l2_config_and_types.sv
+@@ -48,13 +48,17 @@ package l2_config_and_types;
+ 
+     typedef struct packed{
+         logic [29:0] addr;
+-        logic [3:0] be;
+         logic rnw;
+         logic is_amo;
+         logic [4:0] amo_type_or_burst_size;
+         logic [L2_SUB_ID_W-1:0] sub_id;
+     } l2_request_t;
+ 
++    typedef struct packed{
++        logic [31:0] data;
++        logic [3:0] be;
++    } l2_data_request_t;
++
+     typedef struct packed{
+         logic [29:0] addr;
+         logic [3:0] be;
+diff --git a/l2_arbiter/l2_external_interfaces.sv b/l2_arbiter/l2_external_interfaces.sv
+index 18a87d99..1206e87a 100644
+--- a/l2_arbiter/l2_external_interfaces.sv
++++ b/l2_arbiter/l2_external_interfaces.sv
+@@ -25,7 +25,6 @@ interface l2_requester_interface;
+ 
+     //l2_request_t request;
+     logic [29:0] addr;
+-    logic [3:0] be;
+     logic rnw;
+     logic is_amo;
+     logic [4:0] amo_type_or_burst_size;
+@@ -42,6 +41,7 @@ interface l2_requester_interface;
+     logic con_valid;
+ 
+     logic [31:0] wr_data;
++    logic [3:0] wr_data_be;
+     logic wr_data_push;
+     logic data_full;
+ 
+@@ -50,26 +50,26 @@ interface l2_requester_interface;
+     logic rd_data_valid;
+     logic rd_data_ack;
+ 
+-    modport master (output addr, be, rnw, is_amo, amo_type_or_burst_size, sub_id,
++    modport master (output addr, rnw, is_amo, amo_type_or_burst_size, sub_id,
+             output request_push, input request_full,
+             input inv_addr, inv_valid, output  inv_ack,
+             input con_result, con_valid,
+-            output wr_data, wr_data_push, input data_full,
++            output wr_data, wr_data_be, wr_data_push, input data_full,
+             input rd_data, rd_sub_id, rd_data_valid, output rd_data_ack);
+ 
+-    modport slave (input addr, be, rnw, is_amo, amo_type_or_burst_size, sub_id,
++    modport slave (input addr, rnw, is_amo, amo_type_or_burst_size, sub_id,
+             input request_push, output request_full,
+             output inv_addr, inv_valid, input  inv_ack,
+             output con_result, con_valid,
+-            input wr_data, wr_data_push, output data_full,
++            input wr_data, wr_data_be, wr_data_push, output data_full,
+             output rd_data, rd_sub_id, rd_data_valid, input rd_data_ack);
+ 
+ `ifdef __CVA5_FORMAL__
+-    modport formal (input addr, be, rnw, is_amo, amo_type_or_burst_size, sub_id,
++    modport formal (input addr, rnw, is_amo, amo_type_or_burst_size, sub_id,
+                           request_push, output request_full,
+                           inv_addr, inv_valid, input  inv_ack,
+                           con_result, con_valid,
+-                          wr_data, wr_data_push, output data_full,
++                          wr_data, wr_data_be, wr_data_push, output data_full,
+                           rd_data, rd_sub_id, rd_data_valid, input rd_data_ack);
+ `endif
+ 
+@@ -81,7 +81,6 @@ interface l2_memory_interface;
+     localparam L2_ID_W = $clog2(L2_NUM_PORTS) + L2_SUB_ID_W;
+ 
+     logic [29:0] addr;
+-    logic [3:0] be;
+     logic rnw;
+     logic is_amo;
+     logic [4:0] amo_type_or_burst_size;
+@@ -93,6 +92,7 @@ interface l2_memory_interface;
+     logic abort_request;
+ 
+     logic [31:0] wr_data;
++    logic [3:0] wr_data_be;
+     logic wr_data_valid;
+     logic wr_data_read;
+ 
+@@ -100,20 +100,20 @@ interface l2_memory_interface;
+     logic  [L2_ID_W-1:0] rd_id;
+     logic rd_data_valid;
+ 
+-    modport master (output addr, be, rnw, is_amo, amo_type_or_burst_size, id,
++    modport master (output addr, rnw, is_amo, amo_type_or_burst_size, id,
+             output request_valid, abort_request, input request_pop,
+-            output wr_data, wr_data_valid, input wr_data_read,
++            output wr_data, wr_data_be, wr_data_valid, input wr_data_read,
+             input rd_data, rd_id, rd_data_valid);
+ 
+-    modport slave (input addr, be, rnw, is_amo, amo_type_or_burst_size, id,
++    modport slave (input addr, rnw, is_amo, amo_type_or_burst_size, id,
+             input request_valid, abort_request, output request_pop,
+-            input wr_data, wr_data_valid, output wr_data_read,
++            input wr_data, wr_data_be, wr_data_valid, output wr_data_read,
+             output rd_data, rd_id, rd_data_valid);
+ 
+ `ifdef __CVA5_FORMAL__
+-    modport formal (input addr, be, rnw, is_amo, amo_type_or_burst_size, id,
++    modport formal (input addr, rnw, is_amo, amo_type_or_burst_size, id,
+                          request_valid, abort_request, output request_pop,
+-                         wr_data, wr_data_valid, output wr_data_read,
++                         wr_data, wr_data_be, wr_data_valid, output wr_data_read,
+                          rd_data, rd_id, rd_data_valid);
+ `endif
+ 
+
+From f6a593402a30233bc97a7e1a8848857549ee7eb1 Mon Sep 17 00:00:00 2001
+From: Florian Meisel <meisel@esa.tu-darmstadt.de>
+Date: Thu, 8 Sep 2022 20:01:26 +0200
+Subject: [PATCH 2/3] Update uses of l2_requester_interface::be
+
+-> examples/litex/l1_to_wishbone.sv
+-> test_benches/verilator/AXI_DDR_simulation/axi_l2_text.sv, .cc
+
+Signed-off-by: Florian Meisel <meisel@esa.tu-darmstadt.de>
+---
+ examples/litex/l1_to_wishbone.sv              | 26 ++++++++++++-------
+ .../AXI_DDR_simulation/axi_l2_test.cc         | 22 ++++++++++------
+ .../AXI_DDR_simulation/axi_l2_test.sv         |  4 +--
+ 3 files changed, 32 insertions(+), 20 deletions(-)
+
+diff --git a/examples/litex/l1_to_wishbone.sv b/examples/litex/l1_to_wishbone.sv
+index a9bd615d..8fa46d21 100644
+--- a/examples/litex/l1_to_wishbone.sv
++++ b/examples/litex/l1_to_wishbone.sv
+@@ -38,11 +38,14 @@ module l1_to_wishbone
+     localparam MAX_REQUESTS = 32;
+ 
+     fifo_interface #(.DATA_WIDTH($bits(l2_request_t))) request_fifo ();
+-    fifo_interface #(.DATA_WIDTH(32)) data_fifo ();
++    fifo_interface #(.DATA_WIDTH($bits(l2_data_request_t))) data_fifo ();
+ 
+     l2_request_t request_in;
+     l2_request_t request;
+ 
++    l2_data_request_t data_request_in;
++    l2_data_request_t data_request;
++
+     logic request_complete;
+     ////////////////////////////////////////////////////
+     //Implementation
+@@ -51,11 +54,10 @@ module l1_to_wishbone
+ 
+     //Repack input attributes
+     assign request_in.addr = cpu.addr;
+-	assign request_in.be = cpu.be;
+-	assign request_in.rnw = cpu.rnw;
+-	assign request_in.is_amo = cpu.is_amo;
+-	assign request_in.amo_type_or_burst_size = cpu.amo_type_or_burst_size;
+-	assign request_in.sub_id = cpu.sub_id;
++    assign request_in.rnw = cpu.rnw;
++    assign request_in.is_amo = cpu.is_amo;
++    assign request_in.amo_type_or_burst_size = cpu.amo_type_or_burst_size;
++    assign request_in.sub_id = cpu.sub_id;
+ 
+     assign request_fifo.push = cpu.request_push;
+     assign request_fifo.potential_push = cpu.request_push;
+@@ -63,10 +65,14 @@ module l1_to_wishbone
+     assign request_fifo.data_in = request_in;
+     assign request = request_fifo.data_out;
+ 
++    assign data_request_in.data = cpu.wr_data;
++    assign data_request_in.be = cpu.wr_data_be;
++
+     assign data_fifo.push = cpu.wr_data_push;
+     assign data_fifo.potential_push = cpu.wr_data_push;
+     assign data_fifo.pop = wishbone.we & wishbone.ack;
+-    assign data_fifo.data_in = cpu.wr_data;
++    assign data_fifo.data_in = data_request_in;
++    assign data_request = data_fifo.data_out;
+ 
+     cva5_fifo #(.DATA_WIDTH($bits(l2_request_t)), .FIFO_DEPTH(MAX_REQUESTS))
+     request_fifo_block (
+@@ -74,7 +80,7 @@ module l1_to_wishbone
+         .rst (rst), 
+         .fifo (request_fifo)
+     );
+-    cva5_fifo #(.DATA_WIDTH(32), .FIFO_DEPTH(MAX_REQUESTS))
++    cva5_fifo #(.DATA_WIDTH($bits(l2_data_request_t)), .FIFO_DEPTH(MAX_REQUESTS))
+     data_fifo_block (
+         .clk (clk), 
+         .rst (rst), 
+@@ -100,10 +106,10 @@ module l1_to_wishbone
+ 
+     assign wishbone.adr[29:5] = request.addr[29:5];
+     assign wishbone.adr[4:0] = (request.addr[4:0] & ~burst_size) | (burst_count & burst_size);
+-    assign wishbone.sel = request.rnw ? '1 : request.be;
++    assign wishbone.sel = request.rnw ? '1 : data_request.be;
+     assign wishbone.we = ~request.rnw;
+ 
+-    assign wishbone.dat_w = data_fifo.data_out;
++    assign wishbone.dat_w = data_request.data;
+ 
+     assign wishbone.stb = request_fifo.valid;
+     assign wishbone.cyc = request_fifo.valid;
+diff --git a/test_benches/verilator/AXI_DDR_simulation/axi_l2_test.cc b/test_benches/verilator/AXI_DDR_simulation/axi_l2_test.cc
+index 9e0eb31b..0cb316e8 100644
+--- a/test_benches/verilator/AXI_DDR_simulation/axi_l2_test.cc
++++ b/test_benches/verilator/AXI_DDR_simulation/axi_l2_test.cc
+@@ -17,6 +17,10 @@ struct l2_arb_inputs{
+ 	uint32_t sub_id;
+ 	uint32_t be;
+ };
++struct l2_data_inputs{
++	uint32_t data;
++	uint32_t be;
++};
+ struct l2_arb_expected_output{
+ 	uint32_t rd_data;
+ 	uint32_t rd_sub_id;
+@@ -24,7 +28,7 @@ struct l2_arb_expected_output{
+ 
+ queue<l2_arb_inputs> test_inputs;
+ queue<l2_arb_expected_output> test_expected_output;
+-queue<uint32_t> test_data_inputs;
++queue<l2_data_inputs> test_data_inputs;
+ 
+ void assign_read_input(uint32_t address, uint32_t burst_length, uint32_t sub_id){
+ 	l2_arb_inputs in_elem{address, 1, burst_length, sub_id};
+@@ -32,17 +36,19 @@ void assign_read_input(uint32_t address, uint32_t burst_length, uint32_t sub_id)
+ };
+ 
+ void assign_write_input(uint32_t address, uint32_t burst_length, uint32_t sub_id, uint32_t be){
+-	l2_arb_inputs in_elem{address, 0, burst_length, sub_id, be};
++	l2_arb_inputs in_elem{address, 0, burst_length, sub_id};
+ 	test_inputs.push(in_elem);
+ 	for(int i = burst_length-1 ; i >= 0; i--){
+-		test_data_inputs.push(i+71);
++		l2_data_inputs in_data_elem{i+71, be};
++		test_data_inputs.push(in_data_elem);
+ 	}
+ };
+ 
+ void assign_single_write_input(uint32_t address, uint32_t sub_id, uint32_t data, uint32_t be){
+-	l2_arb_inputs in_elem{address, 0, 1, sub_id, be};
++	l2_arb_inputs in_elem{address, 0, 1, sub_id};
+ 	test_inputs.push(in_elem);
+-	test_data_inputs.push(data);
++	l2_data_inputs in_data_elem{data, be};
++	test_data_inputs.push(in_data_elem);
+ 	
+ };
+ vluint64_t main_time = 0; // Current simulation time
+@@ -142,7 +148,6 @@ int main(int argc, char **argv) {
+ 			tb->is_amo = 0;
+ 			tb->amo_type_or_burst_size = elem.burst_length - 1;
+ 			tb->sub_id = elem.sub_id;
+-			tb->be = elem.be;
+ 			number_of_data_left = elem.burst_length;
+ 			tb->request_push = 1;
+ 			tb->wr_data_push = 0;
+@@ -151,9 +156,10 @@ int main(int argc, char **argv) {
+ 			tb->request_push = 0;
+ 
+ 			if(!tb->data_full){
+-				uint32_t data = test_data_inputs.front();
++				l2_data_inputs data_elem = test_data_inputs.front();
+ 				test_data_inputs.pop();
+-				tb->wr_data = data;
++				tb->wr_data = data_elem.data;
++				tb->wr_data_be = data_elem.be;
+ 				tb->wr_data_push = 1;
+ 
+ 				number_of_data_left--;
+diff --git a/test_benches/verilator/AXI_DDR_simulation/axi_l2_test.sv b/test_benches/verilator/AXI_DDR_simulation/axi_l2_test.sv
+index 96e8a92d..0837eca8 100644
+--- a/test_benches/verilator/AXI_DDR_simulation/axi_l2_test.sv
++++ b/test_benches/verilator/AXI_DDR_simulation/axi_l2_test.sv
+@@ -77,7 +77,6 @@ module axi_l2_test # (
+ 
+ 		//L2 interface
+ 	   	input logic [29:0] addr,
+-		input logic [3:0] be,
+ 		input logic rnw,
+ 		input logic is_amo,
+ 		input logic [4:0] amo_type_or_burst_size,
+@@ -94,6 +93,7 @@ module axi_l2_test # (
+ 		output logic con_valid,
+ 
+ 		input logic [31:0] wr_data,
++		input logic [3:0] wr_data_be,
+ 		input logic wr_data_push,
+ 		output logic data_full,
+ 
+@@ -224,7 +224,6 @@ module axi_l2_test # (
+     //    assign m_axi.bresp = bus_axi_bresp;
+ 
+     assign l2[0].addr = addr;
+-    assign l2[0].be = be;
+     assign l2[0].rnw = rnw;
+     assign l2[0].is_amo = is_amo;
+     assign l2[0].amo_type_or_burst_size = amo_type_or_burst_size;
+@@ -241,6 +240,7 @@ module axi_l2_test # (
+     assign con_valid = l2[0].con_valid;
+ 
+     assign l2[0].wr_data = wr_data;
++    assign l2[0].wr_data_be = wr_data_be;
+     assign l2[0].wr_data_push = wr_data_push;
+     assign data_full = l2[0].data_full;
+ 
+
+From ee668917c891d3631763432f65988f371d836f3c Mon Sep 17 00:00:00 2001
+From: Florian Meisel <meisel@esa.tu-darmstadt.de>
+Date: Fri, 9 Sep 2022 15:33:50 +0200
+Subject: [PATCH 3/3] l2_arbiter - Fix mem_data FIFO width
+
+Signed-off-by: Florian Meisel <meisel@esa.tu-darmstadt.de>
+---
+ l2_arbiter/l2_arbiter.sv | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/l2_arbiter/l2_arbiter.sv b/l2_arbiter/l2_arbiter.sv
+index 25d39ba2..9d391449 100755
+--- a/l2_arbiter/l2_arbiter.sv
++++ b/l2_arbiter/l2_arbiter.sv
+@@ -261,7 +261,7 @@ module l2_arbiter
+ 
+     assign write_done = data_attributes.valid & ~mem_data_fifo.full & (burst_count == current_attr.burst_size);
+ 
+-    cva5_fifo #(.DATA_WIDTH($bits($bits(l2_data_request_t))), .FIFO_DEPTH(L2_MEM_ADDR_FIFO_DEPTH))  mem_data (.*, .fifo(mem_data_fifo));
++    cva5_fifo #(.DATA_WIDTH($bits(l2_data_request_t)), .FIFO_DEPTH(L2_MEM_ADDR_FIFO_DEPTH))  mem_data (.*, .fifo(mem_data_fifo));
+ 
+     assign mem_data_fifo.push = data_attributes.valid & ~mem_data_fifo.full & ~current_attr.abort_request;
+     assign mem_data_fifo.potential_push = data_attributes.valid & ~mem_data_fifo.full & ~current_attr.abort_request;

patches/openhwgroup_cvfpu_pr114.patch

@@ -0,0 +1,267 @@
+From 22cd466ccb6a93264e1ea41cccee94b4a7a51572 Mon Sep 17 00:00:00 2001
+From: Michael Platzer <michael.platzer@axelera.ai>
+Date: Tue, 7 May 2024 08:37:52 +0000
+Subject: [PATCH 1/4] =?UTF-8?q?=F0=9F=8F=B7=EF=B8=8F=20Add=20new=20operati?=
+ =?UTF-8?q?on=20for=20symmetric=20(same=20src=20fmt)=20add?=
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+---
+ src/fpnew_pkg.sv | 13 +++++++------
+ 1 file changed, 7 insertions(+), 6 deletions(-)
+
+diff --git a/src/fpnew_pkg.sv b/src/fpnew_pkg.sv
+index 7addc3e9..deedce0d 100644
+--- a/src/fpnew_pkg.sv
++++ b/src/fpnew_pkg.sv
+@@ -120,7 +120,8 @@ package fpnew_pkg;
+     FMADD, FNMSUB, ADD, MUL,     // ADDMUL operation group
+     DIV, SQRT,                   // DIVSQRT operation group
+     SGNJ, MINMAX, CMP, CLASSIFY, // NONCOMP operation group
+-    F2F, F2I, I2F, CPKAB, CPKCD  // CONV operation group
++    F2F, F2I, I2F, CPKAB, CPKCD, // CONV operation group
++    ADDS                         // ADDMUL operation group (ADDS is added here to preserve bit encoding of operations)
+   } operation_e;
+ 
+   // -------------------
+@@ -367,11 +368,11 @@ package fpnew_pkg;
+   // Returns the operation group of the given operation
+   function automatic opgroup_e get_opgroup(operation_e op);
+     unique case (op)
+-      FMADD, FNMSUB, ADD, MUL:     return ADDMUL;
+-      DIV, SQRT:                   return DIVSQRT;
+-      SGNJ, MINMAX, CMP, CLASSIFY: return NONCOMP;
+-      F2F, F2I, I2F, CPKAB, CPKCD: return CONV;
+-      default:                     return NONCOMP;
++      FMADD, FNMSUB, ADD, ADDS, MUL: return ADDMUL;
++      DIV, SQRT:                     return DIVSQRT;
++      SGNJ, MINMAX, CMP, CLASSIFY:   return NONCOMP;
++      F2F, F2I, I2F, CPKAB, CPKCD:   return CONV;
++      default:                       return NONCOMP;
+     endcase
+   endfunction
+ 
+
+From 87461b5d302cbc5b14a9e4570a83e0b60d674319 Mon Sep 17 00:00:00 2001
+From: Michael Platzer <michael.platzer@axelera.ai>
+Date: Tue, 7 May 2024 08:40:19 +0000
+Subject: [PATCH 2/4] =?UTF-8?q?=E2=9C=A8=20Select=20multi=20FMA=20addend?=
+ =?UTF-8?q?=20fmt=20independently?=
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+---
+ src/fpnew_fma_multi.sv              | 22 ++++++++++++++--------
+ src/fpnew_opgroup_multifmt_slice.sv | 29 +++++++++++++++--------------
+ 2 files changed, 29 insertions(+), 22 deletions(-)
+
+diff --git a/src/fpnew_fma_multi.sv b/src/fpnew_fma_multi.sv
+index 471d966f..064e4897 100644
+--- a/src/fpnew_fma_multi.sv
++++ b/src/fpnew_fma_multi.sv
+@@ -34,8 +34,9 @@ module fpnew_fma_multi #(
+   input  fpnew_pkg::roundmode_e       rnd_mode_i,
+   input  fpnew_pkg::operation_e       op_i,
+   input  logic                        op_mod_i,
+-  input  fpnew_pkg::fp_format_e       src_fmt_i, // format of the multiplicands
+-  input  fpnew_pkg::fp_format_e       dst_fmt_i, // format of the addend and result
++  input  fpnew_pkg::fp_format_e       src_fmt_i,  // format of the multiplicands
++  input  fpnew_pkg::fp_format_e       src2_fmt_i, // format of the addend
++  input  fpnew_pkg::fp_format_e       dst_fmt_i,  // format of the result
+   input  TagType                      tag_i,
+   input  logic                        mask_i,
+   input  AuxType                      aux_i,
+@@ -111,6 +112,7 @@ module fpnew_fma_multi #(
+   // Selected pipeline output signals as non-arrays
+   logic [2:0][WIDTH-1:0] operands_q;
+   fpnew_pkg::fp_format_e src_fmt_q;
++  fpnew_pkg::fp_format_e src2_fmt_q;
+   fpnew_pkg::fp_format_e dst_fmt_q;
+ 
+   // Input pipeline signals, index i holds signal after i register stages
+@@ -120,6 +122,7 @@ module fpnew_fma_multi #(
+   fpnew_pkg::operation_e [0:NUM_INP_REGS]                       inp_pipe_op_q;
+   logic                  [0:NUM_INP_REGS]                       inp_pipe_op_mod_q;
+   fpnew_pkg::fp_format_e [0:NUM_INP_REGS]                       inp_pipe_src_fmt_q;
++  fpnew_pkg::fp_format_e [0:NUM_INP_REGS]                       inp_pipe_src2_fmt_q;
+   fpnew_pkg::fp_format_e [0:NUM_INP_REGS]                       inp_pipe_dst_fmt_q;
+   TagType                [0:NUM_INP_REGS]                       inp_pipe_tag_q;
+   logic                  [0:NUM_INP_REGS]                       inp_pipe_mask_q;
+@@ -135,6 +138,7 @@ module fpnew_fma_multi #(
+   assign inp_pipe_op_q[0]       = op_i;
+   assign inp_pipe_op_mod_q[0]   = op_mod_i;
+   assign inp_pipe_src_fmt_q[0]  = src_fmt_i;
++  assign inp_pipe_src2_fmt_q[0] = src2_fmt_i;
+   assign inp_pipe_dst_fmt_q[0]  = dst_fmt_i;
+   assign inp_pipe_tag_q[0]      = tag_i;
+   assign inp_pipe_mask_q[0]     = mask_i;
+@@ -161,6 +165,7 @@ module fpnew_fma_multi #(
+     `FFL(inp_pipe_op_q[i+1],       inp_pipe_op_q[i],       reg_ena, fpnew_pkg::FMADD)
+     `FFL(inp_pipe_op_mod_q[i+1],   inp_pipe_op_mod_q[i],   reg_ena, '0)
+     `FFL(inp_pipe_src_fmt_q[i+1],  inp_pipe_src_fmt_q[i],  reg_ena, fpnew_pkg::fp_format_e'(0))
++    `FFL(inp_pipe_src2_fmt_q[i+1], inp_pipe_src2_fmt_q[i], reg_ena, fpnew_pkg::fp_format_e'(0))
+     `FFL(inp_pipe_dst_fmt_q[i+1],  inp_pipe_dst_fmt_q[i],  reg_ena, fpnew_pkg::fp_format_e'(0))
+     `FFL(inp_pipe_tag_q[i+1],      inp_pipe_tag_q[i],      reg_ena, TagType'('0))
+     `FFL(inp_pipe_mask_q[i+1],     inp_pipe_mask_q[i],     reg_ena, '0)
+@@ -169,6 +174,7 @@ module fpnew_fma_multi #(
+   // Output stage: assign selected pipe outputs to signals for later use
+   assign operands_q = inp_pipe_operands_q[NUM_INP_REGS];
+   assign src_fmt_q  = inp_pipe_src_fmt_q[NUM_INP_REGS];
++  assign src2_fmt_q = inp_pipe_src2_fmt_q[NUM_INP_REGS];
+   assign dst_fmt_q  = inp_pipe_dst_fmt_q[NUM_INP_REGS];
+ 
+   // -----------------
+@@ -232,12 +238,12 @@ module fpnew_fma_multi #(
+   always_comb begin : op_select
+ 
+     // Default assignments - packing-order-agnostic
+-    operand_a = {fmt_sign[src_fmt_q][0], fmt_exponent[src_fmt_q][0], fmt_mantissa[src_fmt_q][0]};
+-    operand_b = {fmt_sign[src_fmt_q][1], fmt_exponent[src_fmt_q][1], fmt_mantissa[src_fmt_q][1]};
+-    operand_c = {fmt_sign[dst_fmt_q][2], fmt_exponent[dst_fmt_q][2], fmt_mantissa[dst_fmt_q][2]};
+-    info_a    = info_q[src_fmt_q][0];
+-    info_b    = info_q[src_fmt_q][1];
+-    info_c    = info_q[dst_fmt_q][2];
++    operand_a = {fmt_sign[src_fmt_q ][0], fmt_exponent[src_fmt_q ][0], fmt_mantissa[src_fmt_q ][0]};
++    operand_b = {fmt_sign[src_fmt_q ][1], fmt_exponent[src_fmt_q ][1], fmt_mantissa[src_fmt_q ][1]};
++    operand_c = {fmt_sign[src2_fmt_q][2], fmt_exponent[src2_fmt_q][2], fmt_mantissa[src2_fmt_q][2]};
++    info_a    = info_q[src_fmt_q ][0];
++    info_b    = info_q[src_fmt_q ][1];
++    info_c    = info_q[src2_fmt_q][2];
+ 
+     // op_mod_q inverts sign of operand C
+     operand_c.sign = operand_c.sign ^ inp_pipe_op_mod_q[NUM_INP_REGS];
+diff --git a/src/fpnew_opgroup_multifmt_slice.sv b/src/fpnew_opgroup_multifmt_slice.sv
+index 7774b751..71ccb34b 100644
+--- a/src/fpnew_opgroup_multifmt_slice.sv
++++ b/src/fpnew_opgroup_multifmt_slice.sv
+@@ -229,28 +229,29 @@ or set Features.FpFmtMask to support only FP32");
+         ) i_fpnew_fma_multi (
+           .clk_i,
+           .rst_ni,
+-          .operands_i      ( local_operands  ),
++          .operands_i      ( local_operands                                  ),
+           .is_boxed_i,
+           .rnd_mode_i,
+           .op_i,
+           .op_mod_i,
+           .src_fmt_i,
++          .src2_fmt_i      ( op_i == fpnew_pkg::ADDS ? src_fmt_i : dst_fmt_i ),
+           .dst_fmt_i,
+           .tag_i,
+-          .mask_i          ( simd_mask_i[lane]   ),
+-          .aux_i           ( aux_data            ),
+-          .in_valid_i      ( in_valid            ),
+-          .in_ready_o      ( lane_in_ready[lane] ),
++          .mask_i          ( simd_mask_i[lane]                               ),
++          .aux_i           ( aux_data                                        ),
++          .in_valid_i      ( in_valid                                        ),
++          .in_ready_o      ( lane_in_ready[lane]                             ),
+           .flush_i,
+-          .result_o        ( op_result           ),
+-          .status_o        ( op_status           ),
+-          .extension_bit_o ( lane_ext_bit[lane]  ),
+-          .tag_o           ( lane_tags[lane]     ),
+-          .mask_o          ( lane_masks[lane]    ),
+-          .aux_o           ( lane_aux[lane]      ),
+-          .out_valid_o     ( out_valid           ),
+-          .out_ready_i     ( out_ready           ),
+-          .busy_o          ( lane_busy[lane]     ),
++          .result_o        ( op_result                                       ),
++          .status_o        ( op_status                                       ),
++          .extension_bit_o ( lane_ext_bit[lane]                              ),
++          .tag_o           ( lane_tags[lane]                                 ),
++          .mask_o          ( lane_masks[lane]                                ),
++          .aux_o           ( lane_aux[lane]                                  ),
++          .out_valid_o     ( out_valid                                       ),
++          .out_ready_i     ( out_ready                                       ),
++          .busy_o          ( lane_busy[lane]                                 ),
+           .reg_ena_i
+         );
+ 
+
+From 67e9c0cb165e3c186ab240461a932c976b182da8 Mon Sep 17 00:00:00 2001
+From: Michael Platzer <michael.platzer@axelera.ai>
+Date: Tue, 7 May 2024 08:43:57 +0000
+Subject: [PATCH 3/4] =?UTF-8?q?=F0=9F=92=A1=20Add=20new=20operation=20to?=
+ =?UTF-8?q?=20comment=20in=20multi=20FMA=20src?=
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+---
+ src/fpnew_fma_multi.sv | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/src/fpnew_fma_multi.sv b/src/fpnew_fma_multi.sv
+index 064e4897..d8cab9b3 100644
+--- a/src/fpnew_fma_multi.sv
++++ b/src/fpnew_fma_multi.sv
+@@ -230,8 +230,8 @@ module fpnew_fma_multi #(
+   // | FMADD    | \c 1        | FMSUB: Invert sign of operand C
+   // | FNMSUB   | \c 0        | FNMSUB: Invert sign of operand A
+   // | FNMSUB   | \c 1        | FNMADD: Invert sign of operands A and C
+-  // | ADD      | \c 0        | ADD: Set operand A to +1.0
+-  // | ADD      | \c 1        | SUB: Set operand A to +1.0, invert sign of operand C
++  // | ADD/ADDS | \c 0        | ADD: Set operand A to +1.0
++  // | ADD/ADDS | \c 1        | SUB: Set operand A to +1.0, invert sign of operand C
+   // | MUL      | \c 0        | MUL: Set operand C to +0.0 or -0.0 depending on the rounding mode
+   // | *others* | \c -        | *invalid*
+   // \note \c op_mod_q always inverts the sign of the addend.
+
+From ba48b596ccbd86e7f04a7a028e43c1d5e96da5a5 Mon Sep 17 00:00:00 2001
+From: Michael Platzer <michael.platzer@axelera.ai>
+Date: Tue, 7 May 2024 08:44:34 +0000
+Subject: [PATCH 4/4] =?UTF-8?q?=F0=9F=93=9D=20Document=20new=20symmetric?=
+ =?UTF-8?q?=20add=20operation?=
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+---
+ docs/README.md | 17 +++++++++--------
+ 1 file changed, 9 insertions(+), 8 deletions(-)
+
+diff --git a/docs/README.md b/docs/README.md
+index 7fbb1607..b68d65fd 100644
+--- a/docs/README.md
++++ b/docs/README.md
+@@ -95,6 +95,7 @@ Enumeration of type `logic [2:0]` holding available rounding modes, encoded for
+ Enumeration of type `logic [3:0]` holding the FP operation.
+ The operation modifier `op_mod_i` can change the operation carried out.
+ Unless noted otherwise, the first operand `op[0]` is used for the operation.
++Unless noted otherwise, `op[0]` and `op[1]` are given in source FP format and `op[2]` is given in destination FP format.
+ 
+ | Enumerator | Modifier |                                                                                                    Operation                                                                                                     |
+ |------------|----------|------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+@@ -102,8 +103,8 @@ Unless noted otherwise, the first operand `op[0]` is used for the operation.
+ | `FMADD`    | `1`      | Fused multiply-subtract (`(op[0] * op[1]) - op[2]`)                                                                                                                                                              |
+ | `FNMSUB`   | `0`      | Negated fused multiply-subtract (`-(op[0] * op[1]) + op[2]`)                                                                                                                                                     |
+ | `FNMSUB`   | `1`      | Negated fused multiply-add (`-(op[0] * op[1]) - op[2]`)                                                                                                                                                          |
+-| `ADD`      | `0`      | Addition (`op[1] + op[2]`) *note the operand indices*                                                                                                                                                            |
+-| `ADD`      | `1`      | Subtraction (`op[1] - op[2]`) *note the operand indices*                                                                                                                                                         |
++| `ADD/ADDS` | `0`      | Addition (`op[1] + op[2]`) *note the operand indices*. For `ADD`, `op[1]` is in source FP format and `op[2]` in destination FP format (default). When `ADDS` is used, both operands are in source FP format.     |
++| `ADD/ADDS` | `1`      | Subtraction (`op[1] - op[2]`) *note the operand indices*. For `ADD`, `op[1]` is in source FP format and `op[2]` in destination FP format (default). When `ADDS` is used, both operands are in source FP format.  |
+ | `MUL`      | `0`      | Multiplication (`op[0] * op[1]`)                                                                                                                                                                                 |
+ | `DIV`      | `0`      | Division (`op[0] / op[1]`)                                                                                                                                                                                       |
+ | `SQRT`     | `0`      | Square root                                                                                                                                                                                                      |
+@@ -394,12 +395,12 @@ The *operation group* is the highest level of grouping within FPnew and signifie
+ 
+ There are currently four operation groups in FPnew which are enumerated in `opgroup_e` as outlined in the following table:
+ 
+-| Enumerator |                  Description                  |         Associated Operations         |
+-|------------|-----------------------------------------------|---------------------------------------|
+-| `ADDMUL`   | Addition and Multiplication                   | `FMADD`, `FNMSUB`, `ADD`, `MUL`       |
+-| `DIVSQRT`  | Division and Square Root                      | `DIV`, `SQRT`                         |
+-| `NONCOMP`  | Non-Computational Operations like Comparisons | `SGNJ`, `MINMAX`, `CMP`, `CLASS`      |
+-| `CONV`     | Conversions                                   | `F2I`, `I2F`, `F2F`, `CPKAB`, `CPKCD` |
++| Enumerator |                  Description                  |         Associated Operations           |
++|------------|-----------------------------------------------|-----------------------------------------|
++| `ADDMUL`   | Addition and Multiplication                   | `FMADD`, `FNMSUB`, `ADD`, `ADDS`, `MUL` |
++| `DIVSQRT`  | Division and Square Root                      | `DIV`, `SQRT`                           |
++| `NONCOMP`  | Non-Computational Operations like Comparisons | `SGNJ`, `MINMAX`, `CMP`, `CLASS`        |
++| `CONV`     | Conversions                                   | `F2I`, `I2F`, `F2F`, `CPKAB`, `CPKCD`   |
+ 
+ Most architectural decisions for FPnew are made at very fine granularity.
+ The big exception to this is the generation of vectorial hardware which is decided at top level through the `EnableVectors` parameter.

patches/pulp-platform_axi_pr293.patch

@@ -0,0 +1,170 @@
+From 4b20954dc8229a0c06e8b3d70284e966f9da2ec1 Mon Sep 17 00:00:00 2001
+From: Cyril Koenig <cykoenig@iis.ee.ethz.ch>
+Date: Wed, 29 Mar 2023 14:57:12 +0200
+Subject: [PATCH 1/2] axi_pkg: Keep hardcoded value in typedef for vivado ip
+ packager
+
+---
+ src/axi_pkg.sv | 65 +++++++++++++++++++++++++-------------------------
+ 1 file changed, 33 insertions(+), 32 deletions(-)
+
+diff --git a/src/axi_pkg.sv b/src/axi_pkg.sv
+index 3f723e262..60c452443 100644
+--- a/src/axi_pkg.sv
++++ b/src/axi_pkg.sv
+@@ -19,49 +19,50 @@
+ //! AXI Package
+ /// Contains all necessary type definitions, constants, and generally useful functions.
+ package axi_pkg;
+-    /// AXI Transaction Burst Width.
+-  parameter int unsigned BurstWidth  = 32'd2;
+-  /// AXI Transaction Response Width.
+-  parameter int unsigned RespWidth   = 32'd2;
+-  /// AXI Transaction Cacheability Width.
+-  parameter int unsigned CacheWidth  = 32'd4;
+-  /// AXI Transaction Protection Width.
+-  parameter int unsigned ProtWidth   = 32'd3;
+-  /// AXI Transaction Quality of Service Width.
+-  parameter int unsigned QosWidth    = 32'd4;
+-  /// AXI Transaction Region Width.
+-  parameter int unsigned RegionWidth = 32'd4;
+-  /// AXI Transaction Length Width.
+-  parameter int unsigned LenWidth    = 32'd8;
+-  /// AXI Transaction Size Width.
+-  parameter int unsigned SizeWidth   = 32'd3;
+-  /// AXI Lock Width.
+-  parameter int unsigned LockWidth   = 32'd1;
+-  /// AXI5 Atomic Operation Width.
+-  parameter int unsigned AtopWidth   = 32'd6;
+-  /// AXI5 Non-Secure Address Identifier.
+-  parameter int unsigned NsaidWidth  = 32'd4;
+ 
+   /// AXI Transaction Burst Width.
+-  typedef logic [BurstWidth-1:0]  burst_t;
++  typedef logic [1:0]  burst_t;
+   /// AXI Transaction Response Type.
+-  typedef logic [RespWidth-1:0]   resp_t;
++  typedef logic [1:0]   resp_t;
+   /// AXI Transaction Cacheability Type.
+-  typedef logic [CacheWidth-1:0]  cache_t;
++  typedef logic [3:0]  cache_t;
+   /// AXI Transaction Protection Type.
+-  typedef logic [ProtWidth-1:0]   prot_t;
++  typedef logic [2:0]   prot_t;
+   /// AXI Transaction Quality of Service Type.
+-  typedef logic [QosWidth-1:0]    qos_t;
++  typedef logic [3:0]    qos_t;
+   /// AXI Transaction Region Type.
+-  typedef logic [RegionWidth-1:0] region_t;
++  typedef logic [3:0] region_t;
+   /// AXI Transaction Length Type.
+-  typedef logic [LenWidth-1:0]    len_t;
++  typedef logic [7:0]    len_t;
+   /// AXI Transaction Size Type.
+-  typedef logic [SizeWidth-1:0]   size_t;
++  typedef logic [2:0]   size_t;
+   /// AXI5 Atomic Operation Type.
+-  typedef logic [AtopWidth-1:0]   atop_t; // atomic operations
++  typedef logic [5:0]   atop_t; // atomic operations
++  /// AXI5 Non-Secure Address Identifier.
++  typedef logic [3:0]  nsaid_t;
++
++  /// AXI Transaction Burst Width.
++  parameter int unsigned BurstWidth  = $size(burst_t);
++  /// AXI Transaction Response Width.
++  parameter int unsigned RespWidth   = $size(resp_t);
++  /// AXI Transaction Cacheability Width.
++  parameter int unsigned CacheWidth  = $size(cache_t);
++  /// AXI Transaction Protection Width.
++  parameter int unsigned ProtWidth   = $size(prot_t);
++  /// AXI Transaction Quality of Service Width.
++  parameter int unsigned QosWidth    = $size(qos_t);
++  /// AXI Transaction Region Width.
++  parameter int unsigned RegionWidth = $size(region_t);
++  /// AXI Transaction Length Width.
++  parameter int unsigned LenWidth    = $size(len_t);
++  /// AXI Transaction Size Width.
++  parameter int unsigned SizeWidth   = $size(size_t);
++  /// AXI Lock Width.
++  parameter int unsigned LockWidth   = 32'd1;
++  /// AXI5 Atomic Operation Width.
++  parameter int unsigned AtopWidth   = $size(atop_t);
+   /// AXI5 Non-Secure Address Identifier.
+-  typedef logic [NsaidWidth-1:0]  nsaid_t;
++  parameter int unsigned NsaidWidth  = $size(nsaid_t);
+ 
+   /// In a fixed burst:
+   /// - The address is the same for every transfer in the burst.
+
+From 7b0db8e4208427c6238d60d705aecd082fc8f902 Mon Sep 17 00:00:00 2001
+From: Thomas Benz <tbenz@iis.ee.ethz.ch>
+Date: Mon, 8 May 2023 10:25:24 +0200
+Subject: [PATCH 2/2] axi_pkg: Remove size function for better compatibility
+
+---
+ src/axi_pkg.sv | 45 ++++++++++++++++++++++-----------------------
+ 1 file changed, 22 insertions(+), 23 deletions(-)
+
+diff --git a/src/axi_pkg.sv b/src/axi_pkg.sv
+index 60c452443..11c0f8ba7 100644
+--- a/src/axi_pkg.sv
++++ b/src/axi_pkg.sv
+@@ -19,6 +19,28 @@
+ //! AXI Package
+ /// Contains all necessary type definitions, constants, and generally useful functions.
+ package axi_pkg;
++    /// AXI Transaction Burst Width.
++  parameter int unsigned BurstWidth  = 32'd2;
++  /// AXI Transaction Response Width.
++  parameter int unsigned RespWidth   = 32'd2;
++  /// AXI Transaction Cacheability Width.
++  parameter int unsigned CacheWidth  = 32'd4;
++  /// AXI Transaction Protection Width.
++  parameter int unsigned ProtWidth   = 32'd3;
++  /// AXI Transaction Quality of Service Width.
++  parameter int unsigned QosWidth    = 32'd4;
++  /// AXI Transaction Region Width.
++  parameter int unsigned RegionWidth = 32'd4;
++  /// AXI Transaction Length Width.
++  parameter int unsigned LenWidth    = 32'd8;
++  /// AXI Transaction Size Width.
++  parameter int unsigned SizeWidth   = 32'd3;
++  /// AXI Lock Width.
++  parameter int unsigned LockWidth   = 32'd1;
++  /// AXI5 Atomic Operation Width.
++  parameter int unsigned AtopWidth   = 32'd6;
++  /// AXI5 Non-Secure Address Identifier.
++  parameter int unsigned NsaidWidth  = 32'd4;
+ 
+   /// AXI Transaction Burst Width.
+   typedef logic [1:0]  burst_t;
+@@ -41,29 +63,6 @@ package axi_pkg;
+   /// AXI5 Non-Secure Address Identifier.
+   typedef logic [3:0]  nsaid_t;
+ 
+-  /// AXI Transaction Burst Width.
+-  parameter int unsigned BurstWidth  = $size(burst_t);
+-  /// AXI Transaction Response Width.
+-  parameter int unsigned RespWidth   = $size(resp_t);
+-  /// AXI Transaction Cacheability Width.
+-  parameter int unsigned CacheWidth  = $size(cache_t);
+-  /// AXI Transaction Protection Width.
+-  parameter int unsigned ProtWidth   = $size(prot_t);
+-  /// AXI Transaction Quality of Service Width.
+-  parameter int unsigned QosWidth    = $size(qos_t);
+-  /// AXI Transaction Region Width.
+-  parameter int unsigned RegionWidth = $size(region_t);
+-  /// AXI Transaction Length Width.
+-  parameter int unsigned LenWidth    = $size(len_t);
+-  /// AXI Transaction Size Width.
+-  parameter int unsigned SizeWidth   = $size(size_t);
+-  /// AXI Lock Width.
+-  parameter int unsigned LockWidth   = 32'd1;
+-  /// AXI5 Atomic Operation Width.
+-  parameter int unsigned AtopWidth   = $size(atop_t);
+-  /// AXI5 Non-Secure Address Identifier.
+-  parameter int unsigned NsaidWidth  = $size(nsaid_t);
+-
+   /// In a fixed burst:
+   /// - The address is the same for every transfer in the burst.
+   /// - The byte lanes that are valid are constant for all beats in the burst.  However, within

patches/pulp-platform_axi_riscv_atomics_pr12.patch

@@ -0,0 +1,1332 @@
+From 6de3f20761d174680476fac31f2761ba3ecc77a9 Mon Sep 17 00:00:00 2001
+From: Samuel Riedel <sriedel@student.ethz.ch>
+Date: Wed, 27 Feb 2019 13:56:21 +0100
+Subject: [PATCH 1/6] axi_riscv_amos: Clean up AW state machine
+
+---
+ src/axi_riscv_amos.sv | 171 +++++++++++++++++-------------------------
+ 1 file changed, 70 insertions(+), 101 deletions(-)
+
+diff --git a/src/axi_riscv_amos.sv b/src/axi_riscv_amos.sv
+index 3ac18ad..96eb75c 100644
+--- a/src/axi_riscv_amos.sv
++++ b/src/axi_riscv_amos.sv
+@@ -145,7 +145,7 @@ module axi_riscv_amos #(
+     localparam int unsigned AXI_ALU_RATIO        = AXI_DATA_WIDTH/RISCV_WORD_WIDTH;
+ 
+     // State types
+-    typedef enum logic [1:0] { FEEDTHROUGH_AW, WAIT_ALU, WAIT_AW, REQ_AW } aw_state_t;
++    typedef enum logic [1:0] { FEEDTHROUGH_AW, WAIT_RESULT_AW, SEND_AW } aw_state_t;
+     aw_state_t   aw_state_d, aw_state_q;
+ 
+     typedef enum logic [2:0] { FEEDTHROUGH_W, WAIT_DATA, W_WAIT_RESULT, W_WAIT_CHANNEL, SEND_W } w_state_t;
+@@ -296,7 +296,7 @@ module axi_riscv_amos #(
+     logic [OUTSTND_BURSTS_WIDTH-1:0]  w_cnt_inj_d, w_cnt_inj_q;
+ 
+     always_comb begin : axi_aw_channel
+-        // Defaults
++        // Defaults AXI Bus
+         mst_aw_id_o     = slv_aw_id_i;
+         mst_aw_addr_o   = slv_aw_addr_i;
+         mst_aw_len_o    = slv_aw_len_i;
+@@ -309,24 +309,27 @@ module axi_riscv_amos #(
+         mst_aw_region_o = slv_aw_region_i;
+         mst_aw_atop_o   = 6'b0;
+         mst_aw_user_o   = slv_aw_user_i;
+-        // Non-AXI signals
+-        addr_d       = addr_q;
+-        id_d         = id_q;
+-        size_d       = size_q;
+-        atop_d       = atop_q;
+-        cache_d      = cache_q;
+-        prot_d       = prot_q;
+-        qos_d        = qos_q;
+-        region_d     = region_q;
+-        user_d       = user_q;
+-        w_cnt_inj_d  = w_cnt_inj_q;
++        // Defaults FF
++        addr_d          = addr_q;
++        id_d            = id_q;
++        size_d          = size_q;
++        atop_d          = atop_q;
++        cache_d         = cache_q;
++        prot_d          = prot_q;
++        qos_d           = qos_q;
++        region_d        = region_q;
++        user_d          = user_q;
++        w_cnt_inj_d     = w_cnt_inj_q;
+         // State Machine
+-        aw_state_d   = aw_state_q;
++        aw_state_d      = aw_state_q;
+ 
+-        // Default control
+-        // Make sure the outstanding beats counter does not overflow
+-        if (w_cnt_q == AXI_MAX_WRITE_TXNS || (slv_aw_valid_i && slv_aw_atop_i)) begin
+-            // Block if counter is overflowing or atomic request
++        // Default control: Block AW channel if...
++        if (slv_aw_valid_i && slv_aw_atop_i) begin
++            // Block if atomic request
++            mst_aw_valid_o = 1'b0;
++            slv_aw_ready_o = 1'b0;
++        end else if (w_cnt_q == AXI_MAX_WRITE_TXNS) begin
++            // Block if counter is overflowing
+             mst_aw_valid_o = 1'b0;
+             slv_aw_ready_o = 1'b0;
+         end else if (slv_aw_valid_i && transaction_collision && !adapter_ready) begin
+@@ -339,104 +342,70 @@ module axi_riscv_amos #(
+             slv_aw_ready_o  = mst_aw_ready_i;
+         end
+ 
++        // Count W burst to know when to inject the W data
++        if (w_cnt_inj_q && mst_w_valid_o && mst_w_ready_i && mst_w_last_o) begin
++            w_cnt_inj_d = w_cnt_inj_q - 1;
++        end
++
+         unique case (aw_state_q)
+ 
+             FEEDTHROUGH_AW: begin
+                 // Feedthrough slave to master until atomic operation is detected
+-                if (slv_aw_valid_i && slv_aw_atop_i) begin
+-                    // Do not forward
+-                    mst_aw_valid_o = 1'b0;
+-                    if (adapter_ready) begin
+-                        // Acknowledge atomic transaction
+-                        slv_aw_ready_o = 1'b1;
+-                        // Remember request
+-                        atop_d   = slv_aw_atop_i;
+-                        addr_d   = slv_aw_addr_i;
+-                        id_d     = slv_aw_id_i;
+-                        size_d   = slv_aw_size_i;
+-                        cache_d  = slv_aw_cache_i;
+-                        prot_d   = slv_aw_prot_i;
+-                        qos_d    = slv_aw_qos_i;
+-                        region_d = slv_aw_region_i;
+-                        user_d   = slv_aw_user_i;
+-                        // Go to next state
+-                        if (atop_valid_d != INVALID) begin
+-                            aw_state_d = WAIT_ALU;
+-                        end
+-                    end else begin
+-                        // Block request
+-                        slv_aw_ready_o  = 1'b0;
++                if (slv_aw_valid_i && slv_aw_atop_i && adapter_ready) begin
++                    // Acknowledge atomic transaction
++                    slv_aw_ready_o = 1'b1;
++                    // Remember request
++                    atop_d   = slv_aw_atop_i;
++                    addr_d   = slv_aw_addr_i;
++                    id_d     = slv_aw_id_i;
++                    size_d   = slv_aw_size_i;
++                    cache_d  = slv_aw_cache_i;
++                    prot_d   = slv_aw_prot_i;
++                    qos_d    = slv_aw_qos_i;
++                    region_d = slv_aw_region_i;
++                    user_d   = slv_aw_user_i;
++                    // If valid AMO --> wait for result
++                    if (atop_valid_d != INVALID) begin
++                        aw_state_d = WAIT_RESULT_AW;
+                     end
+                 end
+ 
+-                // Keep counting the W beats
+-                if (w_cnt_inj_q && mst_w_valid_o && mst_w_ready_i && mst_w_last_o) begin
+-                    w_cnt_inj_d = w_cnt_inj_q - 1;
+-                end
+             end // FEEDTHROUGH_AW
+ 
+-            WAIT_ALU: begin
+-                w_cnt_inj_d = 1'b0;
+-                // If the result is ready, try to write it
+-                if (read_done_q && data_valid_q) begin
+-                    // Check if AW channel is free
+-                    if (aw_free) begin
+-                        // Block
+-                        slv_aw_ready_o  = 1'b0;
+-                        // Make write request
+-                        mst_aw_valid_o  = 1'b1;
+-                        mst_aw_addr_o   = addr_q;
+-                        mst_aw_len_o    = 8'h00;
+-                        mst_aw_id_o     = id_q;
+-                        mst_aw_size_o   = size_q;
+-                        mst_aw_burst_o  = 2'b00;
+-                        mst_aw_lock_o   = 1'b0;
+-                        mst_aw_cache_o  = cache_q;
+-                        mst_aw_prot_o   = prot_q;
+-                        mst_aw_qos_o    = qos_q;
+-                        mst_aw_region_o = region_q;
+-                        mst_aw_user_o   = user_q;
+-                        // Remember outstanding beats before injected request
+-                        if (mst_w_valid_o && mst_w_ready_i && mst_w_last_o) begin
++            WAIT_RESULT_AW, SEND_AW: begin
++                // If the result is ready and the channel is free --> inject AW request
++                if ((read_done_q && data_valid_q && aw_free) || (aw_state_q == SEND_AW)) begin
++                    // Block
++                    slv_aw_ready_o  = 1'b0;
++                    // Make write request
++                    mst_aw_valid_o  = 1'b1;
++                    mst_aw_addr_o   = addr_q;
++                    mst_aw_len_o    = 8'h00;
++                    mst_aw_id_o     = id_q;
++                    mst_aw_size_o   = size_q;
++                    mst_aw_burst_o  = 2'b00;
++                    mst_aw_lock_o   = 1'b0;
++                    mst_aw_cache_o  = cache_q;
++                    mst_aw_prot_o   = prot_q;
++                    mst_aw_qos_o    = qos_q;
++                    mst_aw_region_o = region_q;
++                    mst_aw_user_o   = user_q;
++                    // Check if request is acknowledged
++                    if (mst_aw_ready_i) begin
++                        aw_state_d = FEEDTHROUGH_AW;
++                    end else begin
++                        aw_state_d = SEND_AW;
++                    end
++                    // Remember outstanding W beats before injected request
++                    if (aw_state_q == WAIT_RESULT_AW) begin
++                        if (w_cnt_q && mst_w_valid_o && mst_w_ready_i && mst_w_last_o) begin
+                             w_cnt_inj_d = w_cnt_q - 1;
+                         end else begin
+                             w_cnt_inj_d = w_cnt_q;
+                         end
+-                        // Check if request is acknowledged
+-                        if (mst_aw_ready_i) begin
+-                            aw_state_d = FEEDTHROUGH_AW;
+-                        end else begin
+-                            aw_state_d = REQ_AW;
+-                        end
+-                    end else begin
+                     end
+                 end
+-            end // WAIT_ALU
+-
+-            REQ_AW: begin
+-                // Block
+-                slv_aw_ready_o  = 1'b0;
+-                // Hold write request
+-                mst_aw_valid_o  = 1'b1;
+-                mst_aw_addr_o   = addr_q;
+-                mst_aw_len_o    = 8'h00;
+-                mst_aw_id_o     = id_q;
+-                mst_aw_size_o   = size_q;
+-                mst_aw_burst_o  = 2'b00;
+-                mst_aw_lock_o   = 1'b0;
+-                mst_aw_cache_o  = cache_q;
+-                mst_aw_prot_o   = prot_q;
+-                mst_aw_qos_o    = qos_q;
+-                mst_aw_region_o = region_q;
+-                mst_aw_user_o   = user_q;
+-                if (mst_aw_ready_i) begin
+-                    aw_state_d = FEEDTHROUGH_AW;
+-                end
+-                // Keep counting the W beats
+-                if (w_cnt_inj_q && mst_w_valid_o && mst_w_ready_i && mst_w_last_o) begin
+-                    w_cnt_inj_d = w_cnt_inj_q - 1;
+-                end
+-            end // REQ_AW
++            end // WAIT_RESULT_AW, SEND_AW
+ 
+             default: aw_state_d = FEEDTHROUGH_AW;
+ 
+
+From 64a1958d71465f59be2cd8afffa90fb90afe40d7 Mon Sep 17 00:00:00 2001
+From: Samuel Riedel <sriedel@student.ethz.ch>
+Date: Wed, 27 Feb 2019 14:23:55 +0100
+Subject: [PATCH 2/6] axi_riscv_amos: Clean up W state machine
+
+---
+ src/axi_riscv_amos.sv | 75 ++++++++++++++++++++-----------------------
+ 1 file changed, 35 insertions(+), 40 deletions(-)
+
+diff --git a/src/axi_riscv_amos.sv b/src/axi_riscv_amos.sv
+index 96eb75c..db212d7 100644
+--- a/src/axi_riscv_amos.sv
++++ b/src/axi_riscv_amos.sv
+@@ -148,8 +148,8 @@ module axi_riscv_amos #(
+     typedef enum logic [1:0] { FEEDTHROUGH_AW, WAIT_RESULT_AW, SEND_AW } aw_state_t;
+     aw_state_t   aw_state_d, aw_state_q;
+ 
+-    typedef enum logic [2:0] { FEEDTHROUGH_W, WAIT_DATA, W_WAIT_RESULT, W_WAIT_CHANNEL, SEND_W } w_state_t;
+-    w_state_t   w_state_d, w_state_q;
++    typedef enum logic [2:0] { FEEDTHROUGH_W, WAIT_DATA_W, WAIT_RESULT_W, WAIT_CHANNEL_W, SEND_W } w_state_t;
++    w_state_t    w_state_d, w_state_q;
+ 
+     typedef enum logic [1:0] { FEEDTHROUGH_B, WAIT_B, SEND_B, VALID_REQ } b_state_t;
+     b_state_t   b_state_d, b_state_q;
+@@ -416,21 +416,23 @@ module axi_riscv_amos #(
+     =                                 W                                  =
+     ====================================================================*/
+     logic [OUTSTND_BURSTS_WIDTH-1:0]  w_cnt_req_d, w_cnt_req_q;
++    logic [AXI_USER_WIDTH-1:0]        w_user_d, w_user_q;
+ 
+     always_comb begin : axi_w_channel
+-        // Defaults
++        // Defaults AXI Bus
+         mst_w_data_o = slv_w_data_i;
+         mst_w_strb_o = slv_w_strb_i;
+         mst_w_last_o = slv_w_last_i;
+         mst_w_user_o = slv_w_user_i;
+-        // Non-AXI signals
++        // Defaults FF
+         strb_d       = strb_q;
++        w_user_d     = w_user_q;
+         atop_data_d  = atop_data_q;
+         write_data_d = write_data_q;
+         data_valid_d = data_valid_q;
++        w_cnt_req_d  = w_cnt_req_q;
+         // State Machine
+-        w_state_d   = w_state_q;
+-        w_cnt_req_d = w_cnt_req_q;
++        w_state_d    = w_state_q;
+ 
+         // Default control
+         // Make sure no data is sent without knowing if it's atomic
+@@ -462,12 +464,13 @@ module axi_riscv_amos #(
+                                 if (atop_valid_d != INVALID) begin
+                                     atop_data_d  = slv_w_data_i;
+                                     strb_d       = slv_w_strb_i;
++                                    w_user_d     = slv_w_user_i;
+                                     data_valid_d = 1'b1;
+-                                    w_state_d    = W_WAIT_RESULT;
++                                    w_state_d    = WAIT_RESULT_W;
+                                 end
+                             end else begin
+                                 w_cnt_req_d = '0;
+-                                w_state_d   = WAIT_DATA;
++                                w_state_d   = WAIT_DATA_W;
+                             end
+                         end else begin
+                             // Remember the amount of outstanding bursts and count down
+@@ -476,13 +479,13 @@ module axi_riscv_amos #(
+                             end else begin
+                                 w_cnt_req_d = w_cnt_q;
+                             end
+-                            w_state_d   = WAIT_DATA;
++                            w_state_d   = WAIT_DATA_W;
+                         end
+                     end
+                 end
+             end // FEEDTHROUGH_W
+ 
+-            WAIT_DATA: begin
++            WAIT_DATA_W: begin
+                 // Count W beats until data arrives that belongs to the AMO request
+                 if (w_cnt_req_q == 0) begin
+                     // Block downstream
+@@ -496,69 +499,59 @@ module axi_riscv_amos #(
+                         end else begin
+                             atop_data_d  = slv_w_data_i;
+                             strb_d       = slv_w_strb_i;
++                            w_user_d     = slv_w_user_i;
+                             data_valid_d = 1'b1;
+-                            w_state_d    = W_WAIT_RESULT;
++                            w_state_d    = WAIT_RESULT_W;
+                         end
+                     end
+                 end else if (mst_w_valid_o && mst_w_ready_i && mst_w_last_o) begin
+                     w_cnt_req_d = w_cnt_req_q - 1;
+                 end
+-            end
++            end // WAIT_DATA_W
+ 
+-            W_WAIT_RESULT: begin
++            WAIT_RESULT_W: begin
+                 // If the result is ready, try to write it
+                 if (read_done_q && data_valid_q && aw_free) begin
+                     // Check if W channel is free and make sure data is not interleaved
+                     write_data_d = alu_result_ext;
+                     if (w_free && w_cnt_q == 0) begin
+                         // Block
+-                        slv_w_ready_o  = 1'b0;
++                        slv_w_ready_o = 1'b0;
+                         // Send write data
+-                        mst_w_valid_o  = 1'b1;
+-                        mst_w_data_o   = alu_result_ext;
+-                        mst_w_last_o   = 1'b1;
+-                        mst_w_strb_o   = strb_q;
++                        mst_w_valid_o = 1'b1;
++                        mst_w_data_o  = alu_result_ext;
++                        mst_w_last_o  = 1'b1;
++                        mst_w_strb_o  = strb_q;
++                        mst_w_user_o  = w_user_q;
+                         if (mst_w_ready_i) begin
+                             w_state_d = FEEDTHROUGH_W;
+                         end else begin
+                             w_state_d = SEND_W;
+                         end
+                     end else begin
+-                        w_state_d = W_WAIT_CHANNEL;
++                        w_state_d = WAIT_CHANNEL_W;
+                     end
+                 end
+-            end // W_WAIT_RESULT
++            end // WAIT_RESULT_W
+ 
+-            W_WAIT_CHANNEL: begin
++            WAIT_CHANNEL_W, SEND_W: begin
+                 // Wait to not interleave the data
+-                if (w_free && w_cnt_inj_q == 0) begin
++                if ((w_free && w_cnt_inj_q == 0) || (w_state_q == SEND_W)) begin
+                     // Block
+                     slv_w_ready_o = 1'b0;
+                     // Send write data
+-                    mst_w_valid_o  = 1'b1;
+-                    mst_w_data_o   = write_data_q;
+-                    mst_w_last_o   = 1'b1;
+-                    mst_w_strb_o   = strb_q;
++                    mst_w_valid_o = 1'b1;
++                    mst_w_data_o  = write_data_q;
++                    mst_w_last_o  = 1'b1;
++                    mst_w_strb_o  = strb_q;
++                    mst_w_user_o  = w_user_q;
+                     if (mst_w_ready_i) begin
+                         w_state_d = FEEDTHROUGH_W;
+                     end else begin
+                         w_state_d = SEND_W;
+                     end
+                 end
+-            end // W_WAIT_CHANNEL
+-
+-            SEND_W: begin
+-                // Block
+-                slv_w_ready_o = 1'b0;
+-                // Send write data
+-                mst_w_valid_o  = 1'b1;
+-                mst_w_data_o   = write_data_q;
+-                mst_w_last_o   = 1'b1;
+-                mst_w_strb_o   = strb_q;
+-                if (mst_w_ready_i) begin
+-                    w_state_d = FEEDTHROUGH_W;
+-                end
+-            end // SEND_W
++            end // WAIT_CHANNEL_W, SEND_W
+ 
+             default: w_state_d = FEEDTHROUGH_W;
+ 
+@@ -657,6 +650,7 @@ module axi_riscv_amos #(
+             qos_q        <= '0;
+             region_q     <= '0;
+             user_q       <= '0;
++            w_user_q     <= '0;
+             atop_data_q  <= '0;
+             write_data_q <= '0;
+             data_valid_q <= '0;
+@@ -677,6 +671,7 @@ module axi_riscv_amos #(
+             qos_q        <= qos_d;
+             region_q     <= region_d;
+             user_q       <= user_d;
++            w_user_q     <= w_user_d;
+             atop_data_q  <= atop_data_d;
+             write_data_q <= write_data_d;
+             data_valid_q <= data_valid_d;
+
+From 062f8a686eeefe1af39101a96c1e5b8a82f819c7 Mon Sep 17 00:00:00 2001
+From: Samuel Riedel <sriedel@student.ethz.ch>
+Date: Wed, 27 Feb 2019 14:48:29 +0100
+Subject: [PATCH 3/6] axi_riscv_amos: Clean up B state machine
+
+---
+ src/axi_riscv_amos.sv | 62 +++++++++++++++++++++++--------------------
+ 1 file changed, 33 insertions(+), 29 deletions(-)
+
+diff --git a/src/axi_riscv_amos.sv b/src/axi_riscv_amos.sv
+index db212d7..93321b8 100644
+--- a/src/axi_riscv_amos.sv
++++ b/src/axi_riscv_amos.sv
+@@ -151,8 +151,8 @@ module axi_riscv_amos #(
+     typedef enum logic [2:0] { FEEDTHROUGH_W, WAIT_DATA_W, WAIT_RESULT_W, WAIT_CHANNEL_W, SEND_W } w_state_t;
+     w_state_t    w_state_d, w_state_q;
+ 
+-    typedef enum logic [1:0] { FEEDTHROUGH_B, WAIT_B, SEND_B, VALID_REQ } b_state_t;
+-    b_state_t   b_state_d, b_state_q;
++    typedef enum logic [1:0] { FEEDTHROUGH_B, WAIT_COMPLETE_B, WAIT_CHANNEL_B, SEND_B } b_state_t;
++    b_state_t    b_state_d, b_state_q;
+ 
+     typedef enum logic [1:0] { FEEDTHROUGH_AR, WAIT_AR, REQ_AR } ar_state_t;
+     ar_state_t  ar_state_d, ar_state_q;
+@@ -562,60 +562,64 @@ module axi_riscv_amos #(
+     =                                 B                                  =
+     ====================================================================*/
+     always_comb begin : axi_b_channel
+-        // Defaults
+-        mst_b_ready_o  = slv_b_ready_i;
+-        slv_b_id_o     = mst_b_id_i;
+-        slv_b_resp_o   = mst_b_resp_i;
+-        slv_b_user_o   = mst_b_user_i;
+-        slv_b_valid_o  = mst_b_valid_i;
++        // Defaults AXI Bus
++        mst_b_ready_o = slv_b_ready_i;
++        slv_b_id_o    = mst_b_id_i;
++        slv_b_resp_o  = mst_b_resp_i;
++        slv_b_user_o  = mst_b_user_i;
++        slv_b_valid_o = mst_b_valid_i;
+         // State Machine
+-        b_state_d    = b_state_q;
++        b_state_d     = b_state_q;
+ 
+         unique case (b_state_q)
+ 
+             FEEDTHROUGH_B: begin
+                 if (adapter_ready) begin
+                     if (atop_valid_d == VALID || atop_valid_d == STORE) begin
+-                        b_state_d = VALID_REQ;
++                        // Wait until write is complete
++                        b_state_d = WAIT_COMPLETE_B;
+                     end else if (atop_valid_d == INVALID) begin
+-                        // Inject B resp
+-                        // Check if the B channel is free
+-                        if (mst_b_valid_i) begin
+-                            b_state_d   = WAIT_B;
+-                        end else begin
+-                            mst_b_ready_o  = 1'b0;
++                        // Inject B error resp once the channel is free
++                        if (b_free) begin
++                            // Block downstream
++                            mst_b_ready_o = 1'b0;
+                             // Write B response
+-                            slv_b_id_o     = slv_aw_id_i;
+-                            slv_b_resp_o   = axi_pkg::RESP_SLVERR;
+-                            slv_b_valid_o  = 1'b1;
++                            slv_b_valid_o = 1'b1;
++                            slv_b_id_o    = slv_aw_id_i;
++                            slv_b_resp_o  = axi_pkg::RESP_SLVERR;
++                            slv_b_user_o  = '0;
+                             if (!slv_b_ready_i) begin
+                                 b_state_d = SEND_B;
+                             end
++                        end else begin
++                            b_state_d = WAIT_CHANNEL_B;
+                         end
+                     end
+                 end
+             end // FEEDTHROUGH_B
+ 
+-            WAIT_B, SEND_B: begin
++            WAIT_CHANNEL_B, SEND_B: begin
+                 if (b_free || (b_state_q == SEND_B)) begin
+-                    mst_b_ready_o  = 1'b0;
++                    // Block downstream
++                    mst_b_ready_o = 1'b0;
+                     // Write B response
+-                    slv_b_id_o     = id_q;
+-                    slv_b_resp_o   = axi_pkg::RESP_SLVERR;
+-                    slv_b_valid_o  = 1'b1;
++                    slv_b_valid_o = 1'b1;
++                    slv_b_id_o    = id_q;
++                    slv_b_resp_o  = axi_pkg::RESP_SLVERR;
++                    slv_b_user_o  = '0;
+                     if (slv_b_ready_i) begin
+                         b_state_d = FEEDTHROUGH_B;
+                     end else begin
+                         b_state_d = SEND_B;
+                     end
+                 end
+-            end // WAIT_B
++            end // WAIT_CHANNEL_B, SEND_B
+ 
+-            VALID_REQ: begin
+-                if (mst_b_valid_i && mst_b_id_i == id_q) begin
++            WAIT_COMPLETE_B: begin
++                if (mst_b_valid_i && (mst_b_id_i == id_q)) begin
+                     b_state_d = FEEDTHROUGH_B;
+                 end
+-            end // VALID_REQ
++            end // WAIT_COMPLETE_B
+ 
+             default: b_state_d = FEEDTHROUGH_B;
+ 
+@@ -864,7 +868,7 @@ module axi_riscv_amos #(
+ 
+             WAIT_R, SEND_R: begin
+                 // Wait for the R channel to become free and B response to be valid
+-                if ((r_free && (b_state_q != VALID_REQ)) || (r_state_q == SEND_R)) begin
++                if ((r_free && (b_state_q != WAIT_COMPLETE_B)) || (r_state_q == SEND_R)) begin
+                     // Block memory
+                     mst_r_ready_o = 1'b0;
+                     // Send R response
+
+From 0f97ab96f895d7b3cab9b404399fb1aae6479dd5 Mon Sep 17 00:00:00 2001
+From: Samuel Riedel <sriedel@student.ethz.ch>
+Date: Wed, 27 Feb 2019 16:10:26 +0100
+Subject: [PATCH 4/6] axi_riscv_amos: Clean up AR state machine
+
+---
+ src/axi_riscv_amos.sv | 58 ++++++++++++++-----------------------------
+ 1 file changed, 19 insertions(+), 39 deletions(-)
+
+diff --git a/src/axi_riscv_amos.sv b/src/axi_riscv_amos.sv
+index 93321b8..41248f5 100644
+--- a/src/axi_riscv_amos.sv
++++ b/src/axi_riscv_amos.sv
+@@ -154,8 +154,8 @@ module axi_riscv_amos #(
+     typedef enum logic [1:0] { FEEDTHROUGH_B, WAIT_COMPLETE_B, WAIT_CHANNEL_B, SEND_B } b_state_t;
+     b_state_t    b_state_d, b_state_q;
+ 
+-    typedef enum logic [1:0] { FEEDTHROUGH_AR, WAIT_AR, REQ_AR } ar_state_t;
+-    ar_state_t  ar_state_d, ar_state_q;
++    typedef enum logic [1:0] { FEEDTHROUGH_AR, WAIT_CHANNEL_AR, SEND_AR } ar_state_t;
++    ar_state_t   ar_state_d, ar_state_q;
+ 
+     typedef enum logic [1:0] { FEEDTHROUGH_R, WAIT_DATA_R, WAIT_R, SEND_R } r_state_t;
+     r_state_t   r_state_d, r_state_q;
+@@ -690,7 +690,8 @@ module axi_riscv_amos #(
+     /*====================================================================
+     =                                AR                                  =
+     ====================================================================*/
+-    always_comb begin : axi_AR_channel
++    always_comb begin : axi_ar_channel
++        // Defaults AXI Bus
+         mst_ar_id_o     = slv_ar_id_i;
+         mst_ar_addr_o   = slv_ar_addr_i;
+         mst_ar_len_o    = slv_ar_len_i;
+@@ -704,33 +705,29 @@ module axi_riscv_amos #(
+         mst_ar_user_o   = slv_ar_user_i;
+         mst_ar_valid_o  = 1'b0;
+         slv_ar_ready_o  = 1'b0;
+-
+         // State Machine
+-        ar_state_d  = ar_state_q;
++        ar_state_d      = ar_state_q;
+ 
+         unique case (ar_state_q)
+ 
+             FEEDTHROUGH_AR: begin
+                 // Feed through
+-                mst_ar_valid_o  = slv_ar_valid_i;
+-                slv_ar_ready_o  = mst_ar_ready_i;
++                mst_ar_valid_o = slv_ar_valid_i;
++                slv_ar_ready_o = mst_ar_ready_i;
+ 
+                 if (adapter_ready) begin
+                     if (atop_valid_d == VALID | atop_valid_d == STORE) begin
+-                        if (slv_ar_valid_i) begin
+-                            // Wait until AR is free
+-                            ar_state_d   = WAIT_AR;
+-                        end else begin
++                        if (ar_free) begin
+                             // Acquire channel
+                             slv_ar_ready_o  = 1'b0;
+                             // Immediately start read request
++                            mst_ar_valid_o  = 1'b1;
+                             mst_ar_addr_o   = slv_aw_addr_i;
+                             mst_ar_id_o     = slv_aw_id_i;
+                             mst_ar_len_o    = 8'h00;
+                             mst_ar_size_o   = slv_aw_size_i;
+                             mst_ar_burst_o  = 2'b00;
+                             mst_ar_lock_o   = 1'h0;
+-                            mst_ar_valid_o  = 1'b1;
+                             mst_ar_cache_o  = slv_aw_cache_i;
+                             mst_ar_prot_o   = slv_aw_prot_i;
+                             mst_ar_qos_o    = slv_aw_qos_i;
+@@ -738,24 +735,27 @@ module axi_riscv_amos #(
+                             mst_ar_user_o   = slv_aw_user_i;
+                             if (!mst_ar_ready_i) begin
+                                 // Hold read request but do not depend on AW
+-                                ar_state_d = REQ_AR;
++                                ar_state_d = SEND_AR;
+                             end
++                        end else begin
++                            // Wait until AR is free
++                            ar_state_d   = WAIT_CHANNEL_AR;
+                         end
+                     end
+                 end
+             end // FEEDTHROUGH_AR
+ 
+-            WAIT_AR: begin
++            WAIT_CHANNEL_AR, SEND_AR: begin
+                 // Issue read request
+-                if (ar_free) begin
++                if (ar_free || (ar_state_q == SEND_AR)) begin
+                     // Inject read request
++                    mst_ar_valid_o  = 1'b1;
+                     mst_ar_addr_o   = addr_q;
+                     mst_ar_id_o     = id_q;
+                     mst_ar_len_o    = 8'h00;
+                     mst_ar_size_o   = size_q;
+                     mst_ar_burst_o  = 2'b00;
+                     mst_ar_lock_o   = 1'h0;
+-                    mst_ar_valid_o  = 1'b1;
+                     mst_ar_cache_o  = cache_q;
+                     mst_ar_prot_o   = prot_q;
+                     mst_ar_qos_o    = qos_q;
+@@ -766,39 +766,19 @@ module axi_riscv_amos #(
+                         ar_state_d = FEEDTHROUGH_AR;
+                     end else begin
+                         // Hold read request
+-                        ar_state_d = REQ_AR;
++                        ar_state_d = SEND_AR;
+                     end
+                 end else begin
+                     // Wait until AR is free
+                     mst_ar_valid_o = slv_ar_valid_i;
+                     slv_ar_ready_o = mst_ar_ready_i;
+                 end
+-            end // WAIT_AR
+-
+-            REQ_AR: begin
+-                // Inject read request
+-                mst_ar_addr_o   = addr_q;
+-                mst_ar_id_o     = id_q;
+-                mst_ar_len_o    = 8'h00;
+-                mst_ar_size_o   = size_q;
+-                mst_ar_burst_o  = 2'b00;
+-                mst_ar_lock_o   = 1'h0;
+-                mst_ar_valid_o  = 1'b1;
+-                mst_ar_cache_o  = cache_q;
+-                mst_ar_prot_o   = prot_q;
+-                mst_ar_qos_o    = qos_q;
+-                mst_ar_region_o = region_q;
+-                mst_ar_user_o   = user_q;
+-                if (mst_ar_ready_i) begin
+-                    // Request acknowledged
+-                    ar_state_d = FEEDTHROUGH_AR;
+-                end
+-            end // REQ_AR
++            end // WAIT_CHANNEL_AR, SEND_AR
+ 
+             default: ar_state_d = FEEDTHROUGH_AR;
+ 
+         endcase
+-    end
++    end // axi_ar_channel
+ 
+     /*====================================================================
+     =                                 R                                  =
+
+From 7903d4cb01319d7b0866ede20473ec699863123a Mon Sep 17 00:00:00 2001
+From: Samuel Riedel <sriedel@student.ethz.ch>
+Date: Wed, 27 Feb 2019 16:40:13 +0100
+Subject: [PATCH 5/6] axi_riscv_amos: Clean up R state machine
+
+---
+ src/axi_riscv_amos.sv | 73 ++++++++++++++++++++++++-------------------
+ 1 file changed, 41 insertions(+), 32 deletions(-)
+
+diff --git a/src/axi_riscv_amos.sv b/src/axi_riscv_amos.sv
+index 41248f5..14efa58 100644
+--- a/src/axi_riscv_amos.sv
++++ b/src/axi_riscv_amos.sv
+@@ -157,8 +157,8 @@ module axi_riscv_amos #(
+     typedef enum logic [1:0] { FEEDTHROUGH_AR, WAIT_CHANNEL_AR, SEND_AR } ar_state_t;
+     ar_state_t   ar_state_d, ar_state_q;
+ 
+-    typedef enum logic [1:0] { FEEDTHROUGH_R, WAIT_DATA_R, WAIT_R, SEND_R } r_state_t;
+-    r_state_t   r_state_d, r_state_q;
++    typedef enum logic [1:0] { FEEDTHROUGH_R, WAIT_DATA_R, WAIT_CHANNEL_R, SEND_R } r_state_t;
++    r_state_t    r_state_d, r_state_q;
+ 
+     typedef enum logic [1:0] { NONE, INVALID, VALID, STORE } atop_req_t;
+     atop_req_t  atop_valid_d, atop_valid_q;
+@@ -783,44 +783,52 @@ module axi_riscv_amos #(
+     /*====================================================================
+     =                                 R                                  =
+     ====================================================================*/
+-    always_comb begin : axi_R_channel
+-
+-        // Feed through the R channel by default
+-        mst_r_ready_o   = slv_r_ready_i;
+-        slv_r_id_o      = mst_r_id_i;
+-        slv_r_data_o    = mst_r_data_i;
+-        slv_r_resp_o    = mst_r_resp_i;
+-        slv_r_last_o    = mst_r_last_i;
+-        slv_r_user_o    = mst_r_user_i;
+-        slv_r_valid_o   = mst_r_valid_i;
+-
++    always_comb begin : axi_r_channel
++        // Defaults AXI Bus
++        mst_r_ready_o = slv_r_ready_i;
++        slv_r_id_o    = mst_r_id_i;
++        slv_r_data_o  = mst_r_data_i;
++        slv_r_resp_o  = mst_r_resp_i;
++        slv_r_last_o  = mst_r_last_i;
++        slv_r_user_o  = mst_r_user_i;
++        slv_r_valid_o = mst_r_valid_i;
++        // Defaults FF
++        read_data_d   = read_data_q;
++        r_resp_d      = r_resp_q;
++        r_user_d      = r_user_q;
++        read_done_d   = read_done_q;
+         // State Machine
+-        read_data_d = read_data_q;
+-        r_resp_d    = r_resp_q;
+-        r_user_d    = r_user_q;
+-        read_done_d = read_done_q;
+-        r_state_d   = r_state_q;
++        r_state_d     = r_state_q;
+ 
+         unique case (r_state_q)
+ 
+             FEEDTHROUGH_R: begin
+                 if (adapter_ready) begin
+                     // Reset read flag
+-                    read_done_d  = 1'b0;
++                    read_done_d = 1'b0;
+ 
+                     if (atop_valid_d == VALID || atop_valid_d == STORE) begin
+                         // Wait for R response to read data
+                         r_state_d = WAIT_DATA_R;
+                     end else if (atop_valid_d == INVALID) begin
+-                        // Send R response
+-                        // Check if the R channel is free
++                        // Send R response once channel is free
+                         if (r_free) begin
+                             // Acquire the R channel
+-                            slv_r_valid_o = 1'b0;
++                            // Block downstream
+                             mst_r_ready_o = 1'b0;
+-                            r_state_d   = SEND_R;
++                            // Send R error response
++                            slv_r_valid_o = 1'b1;
++                            slv_r_data_o  = '0;
++                            slv_r_id_o    = slv_aw_id_i;
++                            slv_r_last_o  = 1'b1;
++                            slv_r_resp_o  = axi_pkg::RESP_SLVERR;
++                            slv_r_user_o  = '0;
++                            if (!slv_r_ready_i) begin
++                                // Hold R response
++                                r_state_d = SEND_R;
++                            end
+                         end else begin
+-                            r_state_d = WAIT_R;
++                            r_state_d = WAIT_CHANNEL_R;
+                         end
+                     end
+                 end
+@@ -838,29 +846,30 @@ module axi_riscv_amos #(
+                     r_user_d    = mst_r_user_i;
+                     read_done_d = 1'b1;
+                     if (atop_valid_q == STORE) begin
+-                        r_state_d   = FEEDTHROUGH_R;
++                        r_state_d = FEEDTHROUGH_R;
+                     end else begin
+                         // Wait for B resp before injecting R
+-                        r_state_d  = WAIT_R;
++                        r_state_d = WAIT_CHANNEL_R;
+                     end
+                 end
+             end // WAIT_DATA_R
+ 
+-            WAIT_R, SEND_R: begin
++            WAIT_CHANNEL_R, SEND_R: begin
+                 // Wait for the R channel to become free and B response to be valid
++                // TODO: Use b_state_d to be one cycle quicker
+                 if ((r_free && (b_state_q != WAIT_COMPLETE_B)) || (r_state_q == SEND_R)) begin
+-                    // Block memory
++                    // Block downstream
+                     mst_r_ready_o = 1'b0;
+                     // Send R response
+                     slv_r_valid_o = 1'b1;
+                     slv_r_data_o  = read_data_q;
+                     slv_r_id_o    = id_q;
++                    slv_r_last_o  = 1'b1;
+                     slv_r_resp_o  = r_resp_q;
+                     slv_r_user_o  = r_user_q;
+-                    slv_r_last_o  = 1'b1;
+                     if (atop_valid_q == INVALID) begin
+-                        slv_r_resp_o = axi_pkg::RESP_SLVERR;
+                         slv_r_data_o = '0;
++                        slv_r_resp_o = axi_pkg::RESP_SLVERR;
+                         slv_r_user_o = '0;
+                     end
+                     if (slv_r_ready_i) begin
+@@ -869,12 +878,12 @@ module axi_riscv_amos #(
+                         r_state_d = SEND_R;
+                     end
+                 end
+-            end // WAIT_R
++            end // WAIT_CHANNEL_R, SEND_R
+ 
+             default: r_state_d = FEEDTHROUGH_R;
+ 
+         endcase
+-    end
++    end // axi_r_channel
+ 
+     always_ff @(posedge clk_i or negedge rst_ni) begin : axi_read_channel_ff
+         if(~rst_ni) begin
+
+From d4d84036eea24ef0142e1522905f8ddbc994c6a5 Mon Sep 17 00:00:00 2001
+From: Samuel Riedel <sriedel@student.ethz.ch>
+Date: Wed, 27 Feb 2019 17:53:28 +0100
+Subject: [PATCH 6/6] axi_riscv_amos: Clean up names and signal declarations
+
+---
+ src/axi_riscv_amos.sv | 273 +++++++++++++++++++++---------------------
+ 1 file changed, 135 insertions(+), 138 deletions(-)
+
+diff --git a/src/axi_riscv_amos.sv b/src/axi_riscv_amos.sv
+index 14efa58..fafdb4f 100644
+--- a/src/axi_riscv_amos.sv
++++ b/src/axi_riscv_amos.sv
+@@ -160,35 +160,55 @@ module axi_riscv_amos #(
+     typedef enum logic [1:0] { FEEDTHROUGH_R, WAIT_DATA_R, WAIT_CHANNEL_R, SEND_R } r_state_t;
+     r_state_t    r_state_d, r_state_q;
+ 
+-    typedef enum logic [1:0] { NONE, INVALID, VALID, STORE } atop_req_t;
+-    atop_req_t  atop_valid_d, atop_valid_q;
++    typedef enum logic [1:0] { NONE, INVALID, LOAD, STORE } atop_req_t;
++    atop_req_t   atop_valid_d, atop_valid_q;
+ 
+     // Signal declarations
+-    logic [OUTSTND_BURSTS_WIDTH-1:0]    w_cnt_d, w_cnt_q;
+-    logic [AXI_ADDR_WIDTH-1:0]          addr_d, addr_q;
+-    logic [AXI_ID_WIDTH-1:0]            id_d, id_q;
+-    logic [2:0]                         size_d, size_q;
+-    logic [AXI_STRB_WIDTH-1:0]          strb_d, strb_q;
+-    logic [3:0]                         cache_d, cache_q;
+-    logic [2:0]                         prot_d, prot_q;
+-    logic [3:0]                         qos_d, qos_q;
+-    logic [3:0]                         region_d, region_q;
+-    logic [AXI_USER_WIDTH-1:0]          user_d, user_q;
+-    logic [1:0]                         r_resp_d, r_resp_q;
+-    logic [AXI_USER_WIDTH-1:0]          r_user_d, r_user_q;
+-    logic [AXI_DATA_WIDTH-1:0]          atop_data_d, atop_data_q;
+-    logic [AXI_DATA_WIDTH-1:0]          read_data_d, read_data_q;
+-    logic [AXI_DATA_WIDTH-1:0]          write_data_d, write_data_q;
+-    logic [5:0]                         atop_d, atop_q;
+-    logic                               data_valid_d, data_valid_q;
+-
+-    logic                               read_done_d, read_done_q;
++    // Transaction FF
++    logic [AXI_ADDR_WIDTH-1:0]          addr_d,         addr_q;
++    logic [AXI_ID_WIDTH-1:0]            id_d,           id_q;
++    logic [AXI_STRB_WIDTH-1:0]          strb_d,         strb_q;
++    logic [2:0]                         size_d,         size_q;
++    logic [5:0]                         atop_d,         atop_q;
++    logic [3:0]                         cache_d,        cache_q;
++    logic [2:0]                         prot_d,         prot_q;
++    logic [3:0]                         qos_d,          qos_q;
++    logic [3:0]                         region_d,       region_q;
++    logic [1:0]                         r_resp_d,       r_resp_q;
++    logic [AXI_USER_WIDTH-1:0]          aw_user_d,      aw_user_q,
++                                        w_user_d,       w_user_q,
++                                        r_user_d,       r_user_q;
++    // Data FF
++    logic [AXI_DATA_WIDTH-1:0]          w_data_d,       w_data_q;       // AMO operand
++    logic [AXI_DATA_WIDTH-1:0]          r_data_d,       r_data_q;       // Data from memory
++    logic [AXI_DATA_WIDTH-1:0]          result_d,       result_q;       // Result of AMO operation
++    logic                               w_d_valid_d,    w_d_valid_q,    // AMO operand valid
++                                        r_d_valid_d,    r_d_valid_q;    // Data from memory valid
++    // Counters
++    logic [OUTSTND_BURSTS_WIDTH-1:0]    w_cnt_d,        w_cnt_q;        // Outstanding W beats
++    logic [OUTSTND_BURSTS_WIDTH-1:0]    w_cnt_req_d,    w_cnt_req_q;    // W beats until AMO can read W
++    logic [OUTSTND_BURSTS_WIDTH-1:0]    w_cnt_inj_d,    w_cnt_inj_q;    // W beats until AMO can insert its W
++    // States
+     logic                               adapter_ready;
+-
+-    logic [RISCV_WORD_WIDTH-1:0]    alu_operand_a;
+-    logic [RISCV_WORD_WIDTH-1:0]    alu_operand_b;
+-    logic [RISCV_WORD_WIDTH-1:0]    alu_result;
+-    logic [AXI_DATA_WIDTH-1:0]      alu_result_ext;
++    logic                               transaction_collision;
++    logic                               aw_valid,       aw_ready,       aw_free,
++                                        w_valid,        w_ready,        w_free,
++                                        b_valid,        b_ready,        b_free,
++                                        ar_valid,       ar_ready,       ar_free,
++                                        r_valid,        r_ready,        r_free;
++    // ALU Signals
++    logic [RISCV_WORD_WIDTH-1:0]                        alu_operand_a;
++    logic [RISCV_WORD_WIDTH-1:0]                        alu_operand_b;
++    logic [RISCV_WORD_WIDTH-1:0]                        alu_result;
++    logic [AXI_DATA_WIDTH-1:0]                          alu_result_ext;
++    logic [AXI_ALU_RATIO-1:0][RISCV_WORD_WIDTH-1:0]     op_a;
++    logic [AXI_ALU_RATIO-1:0][RISCV_WORD_WIDTH-1:0]     op_b;
++    logic [AXI_ALU_RATIO-1:0][RISCV_WORD_WIDTH-1:0]     op_a_sign_ext;
++    logic [AXI_ALU_RATIO-1:0][RISCV_WORD_WIDTH-1:0]     op_b_sign_ext;
++    logic [AXI_ALU_RATIO-1:0][RISCV_WORD_WIDTH-1:0]     res;
++    logic [AXI_STRB_WIDTH-1:0][7:0]                     strb_ext;
++    logic                                               sign_a;
++    logic                                               sign_b;
+ 
+     /**
+      * Calculate ready signals and channel states
+@@ -202,13 +222,6 @@ module axi_riscv_amos #(
+                            ( r_state_q == FEEDTHROUGH_R );
+ 
+     // Calculate if the channels are free
+-    logic aw_valid, aw_ready;
+-    logic  w_valid,  w_ready;
+-    logic  b_valid,  b_ready;
+-    logic ar_valid, ar_ready;
+-    logic  r_valid,  r_ready;
+-    logic aw_free, w_free, b_free, ar_free, r_free;
+-
+     assign aw_free = ~aw_valid | aw_ready;
+     assign  w_free = ~ w_valid |  w_ready;
+     assign  b_free = ~ b_valid |  b_ready;
+@@ -244,8 +257,6 @@ module axi_riscv_amos #(
+     // Calculate if the request interferes with the ongoing atomic transaction
+     // The protected bytes go from addr_q up to addr_q + (1 << size_q) - 1
+     // TODO Bursts need special treatment
+-    // TODO Some memory controller round the address down
+-    logic transaction_collision;
+     assign transaction_collision = (slv_aw_addr_i < (     addr_q + (8'h01 <<      size_q))) &
+                                    (     addr_q < (slv_aw_addr_i + (8'h01 << slv_aw_size_i)));
+ 
+@@ -259,7 +270,7 @@ module axi_riscv_amos #(
+                 // Valid load operation
+                 if ((slv_aw_atop_i      ==  axi_pkg::ATOP_ATOMICSWAP) ||
+                     (slv_aw_atop_i[5:3] == {axi_pkg::ATOP_ATOMICLOAD , axi_pkg::ATOP_LITTLE_END})) begin
+-                    atop_valid_d = VALID;
++                    atop_valid_d = LOAD;
+                 end
+                 // Valid store operation
+                 if (slv_aw_atop_i[5:3] == {axi_pkg::ATOP_ATOMICSTORE, axi_pkg::ATOP_LITTLE_END}) begin
+@@ -293,8 +304,6 @@ module axi_riscv_amos #(
+     /*====================================================================
+     =                                 AW                                 =
+     ====================================================================*/
+-    logic [OUTSTND_BURSTS_WIDTH-1:0]  w_cnt_inj_d, w_cnt_inj_q;
+-
+     always_comb begin : axi_aw_channel
+         // Defaults AXI Bus
+         mst_aw_id_o     = slv_aw_id_i;
+@@ -318,7 +327,7 @@ module axi_riscv_amos #(
+         prot_d          = prot_q;
+         qos_d           = qos_q;
+         region_d        = region_q;
+-        user_d          = user_q;
++        aw_user_d       = aw_user_q;
+         w_cnt_inj_d     = w_cnt_inj_q;
+         // State Machine
+         aw_state_d      = aw_state_q;
+@@ -355,15 +364,15 @@ module axi_riscv_amos #(
+                     // Acknowledge atomic transaction
+                     slv_aw_ready_o = 1'b1;
+                     // Remember request
+-                    atop_d   = slv_aw_atop_i;
+-                    addr_d   = slv_aw_addr_i;
+-                    id_d     = slv_aw_id_i;
+-                    size_d   = slv_aw_size_i;
+-                    cache_d  = slv_aw_cache_i;
+-                    prot_d   = slv_aw_prot_i;
+-                    qos_d    = slv_aw_qos_i;
+-                    region_d = slv_aw_region_i;
+-                    user_d   = slv_aw_user_i;
++                    atop_d    = slv_aw_atop_i;
++                    addr_d    = slv_aw_addr_i;
++                    id_d      = slv_aw_id_i;
++                    size_d    = slv_aw_size_i;
++                    cache_d   = slv_aw_cache_i;
++                    prot_d    = slv_aw_prot_i;
++                    qos_d     = slv_aw_qos_i;
++                    region_d  = slv_aw_region_i;
++                    aw_user_d = slv_aw_user_i;
+                     // If valid AMO --> wait for result
+                     if (atop_valid_d != INVALID) begin
+                         aw_state_d = WAIT_RESULT_AW;
+@@ -374,7 +383,7 @@ module axi_riscv_amos #(
+ 
+             WAIT_RESULT_AW, SEND_AW: begin
+                 // If the result is ready and the channel is free --> inject AW request
+-                if ((read_done_q && data_valid_q && aw_free) || (aw_state_q == SEND_AW)) begin
++                if ((r_d_valid_q && w_d_valid_q && aw_free) || (aw_state_q == SEND_AW)) begin
+                     // Block
+                     slv_aw_ready_o  = 1'b0;
+                     // Make write request
+@@ -389,7 +398,7 @@ module axi_riscv_amos #(
+                     mst_aw_prot_o   = prot_q;
+                     mst_aw_qos_o    = qos_q;
+                     mst_aw_region_o = region_q;
+-                    mst_aw_user_o   = user_q;
++                    mst_aw_user_o   = aw_user_q;
+                     // Check if request is acknowledged
+                     if (mst_aw_ready_i) begin
+                         aw_state_d = FEEDTHROUGH_AW;
+@@ -415,9 +424,6 @@ module axi_riscv_amos #(
+     /*====================================================================
+     =                                 W                                  =
+     ====================================================================*/
+-    logic [OUTSTND_BURSTS_WIDTH-1:0]  w_cnt_req_d, w_cnt_req_q;
+-    logic [AXI_USER_WIDTH-1:0]        w_user_d, w_user_q;
+-
+     always_comb begin : axi_w_channel
+         // Defaults AXI Bus
+         mst_w_data_o = slv_w_data_i;
+@@ -427,9 +433,9 @@ module axi_riscv_amos #(
+         // Defaults FF
+         strb_d       = strb_q;
+         w_user_d     = w_user_q;
+-        atop_data_d  = atop_data_q;
+-        write_data_d = write_data_q;
+-        data_valid_d = data_valid_q;
++        w_data_d     = w_data_q;
++        result_d     = result_q;
++        w_d_valid_d  = w_d_valid_q;
+         w_cnt_req_d  = w_cnt_req_q;
+         // State Machine
+         w_state_d    = w_state_q;
+@@ -450,8 +456,8 @@ module axi_riscv_amos #(
+             FEEDTHROUGH_W: begin
+                 if (adapter_ready) begin
+                     // Reset read flag
+-                    data_valid_d = 1'b0;
+-                    write_data_d = '0;
++                    w_d_valid_d = 1'b0;
++                    result_d    = '0;
+ 
+                     if (atop_valid_d != NONE) begin
+                         // Check if data is also available and does not belong to previous request
+@@ -462,11 +468,11 @@ module axi_riscv_amos #(
+                             slv_w_ready_o  = 1'b1;
+                             if (slv_w_valid_i) begin
+                                 if (atop_valid_d != INVALID) begin
+-                                    atop_data_d  = slv_w_data_i;
+-                                    strb_d       = slv_w_strb_i;
+-                                    w_user_d     = slv_w_user_i;
+-                                    data_valid_d = 1'b1;
+-                                    w_state_d    = WAIT_RESULT_W;
++                                    w_data_d    = slv_w_data_i;
++                                    strb_d      = slv_w_strb_i;
++                                    w_user_d    = slv_w_user_i;
++                                    w_d_valid_d = 1'b1;
++                                    w_state_d   = WAIT_RESULT_W;
+                                 end
+                             end else begin
+                                 w_cnt_req_d = '0;
+@@ -497,11 +503,11 @@ module axi_riscv_amos #(
+                         if (atop_valid_q == INVALID) begin
+                             w_state_d    = FEEDTHROUGH_W;
+                         end else begin
+-                            atop_data_d  = slv_w_data_i;
+-                            strb_d       = slv_w_strb_i;
+-                            w_user_d     = slv_w_user_i;
+-                            data_valid_d = 1'b1;
+-                            w_state_d    = WAIT_RESULT_W;
++                            w_data_d    = slv_w_data_i;
++                            strb_d      = slv_w_strb_i;
++                            w_user_d    = slv_w_user_i;
++                            w_d_valid_d = 1'b1;
++                            w_state_d   = WAIT_RESULT_W;
+                         end
+                     end
+                 end else if (mst_w_valid_o && mst_w_ready_i && mst_w_last_o) begin
+@@ -511,9 +517,9 @@ module axi_riscv_amos #(
+ 
+             WAIT_RESULT_W: begin
+                 // If the result is ready, try to write it
+-                if (read_done_q && data_valid_q && aw_free) begin
++                if (r_d_valid_q && w_d_valid_q && aw_free) begin
+                     // Check if W channel is free and make sure data is not interleaved
+-                    write_data_d = alu_result_ext;
++                    result_d = alu_result_ext;
+                     if (w_free && w_cnt_q == 0) begin
+                         // Block
+                         slv_w_ready_o = 1'b0;
+@@ -541,7 +547,7 @@ module axi_riscv_amos #(
+                     slv_w_ready_o = 1'b0;
+                     // Send write data
+                     mst_w_valid_o = 1'b1;
+-                    mst_w_data_o  = write_data_q;
++                    mst_w_data_o  = result_q;
+                     mst_w_last_o  = 1'b1;
+                     mst_w_strb_o  = strb_q;
+                     mst_w_user_o  = w_user_q;
+@@ -575,7 +581,7 @@ module axi_riscv_amos #(
+ 
+             FEEDTHROUGH_B: begin
+                 if (adapter_ready) begin
+-                    if (atop_valid_d == VALID || atop_valid_d == STORE) begin
++                    if (atop_valid_d == LOAD || atop_valid_d == STORE) begin
+                         // Wait until write is complete
+                         b_state_d = WAIT_COMPLETE_B;
+                     end else if (atop_valid_d == INVALID) begin
+@@ -639,47 +645,47 @@ module axi_riscv_amos #(
+ 
+     always_ff @(posedge clk_i or negedge rst_ni) begin : axi_write_channel_ff
+         if(~rst_ni) begin
+-            aw_state_q   <= FEEDTHROUGH_AW;
+-            w_state_q    <= FEEDTHROUGH_W;
+-            b_state_q    <= FEEDTHROUGH_B;
+-            w_cnt_q      <= '0;
+-            w_cnt_req_q  <= '0;
+-            w_cnt_inj_q  <= '0;
+-            addr_q       <= '0;
+-            id_q         <= '0;
+-            size_q       <= '0;
+-            strb_q       <= '0;
+-            cache_q      <= '0;
+-            prot_q       <= '0;
+-            qos_q        <= '0;
+-            region_q     <= '0;
+-            user_q       <= '0;
+-            w_user_q     <= '0;
+-            atop_data_q  <= '0;
+-            write_data_q <= '0;
+-            data_valid_q <= '0;
+-            atop_q       <= 6'b0;
++            aw_state_q  <= FEEDTHROUGH_AW;
++            w_state_q   <= FEEDTHROUGH_W;
++            b_state_q   <= FEEDTHROUGH_B;
++            w_cnt_q     <= '0;
++            w_cnt_req_q <= '0;
++            w_cnt_inj_q <= '0;
++            addr_q      <= '0;
++            id_q        <= '0;
++            size_q      <= '0;
++            strb_q      <= '0;
++            cache_q     <= '0;
++            prot_q      <= '0;
++            qos_q       <= '0;
++            region_q    <= '0;
++            aw_user_q   <= '0;
++            w_user_q    <= '0;
++            w_data_q    <= '0;
++            result_q    <= '0;
++            w_d_valid_q <= '0;
++            atop_q      <= 6'b0;
+         end else begin
+-            aw_state_q   <= aw_state_d;
+-            w_state_q    <= w_state_d;
+-            b_state_q    <= b_state_d;
+-            w_cnt_q      <= w_cnt_d;
+-            w_cnt_req_q  <= w_cnt_req_d;
+-            w_cnt_inj_q  <= w_cnt_inj_d;
+-            addr_q       <= addr_d;
+-            id_q         <= id_d;
+-            size_q       <= size_d;
+-            strb_q       <= strb_d;
+-            cache_q      <= cache_d;
+-            prot_q       <= prot_d;
+-            qos_q        <= qos_d;
+-            region_q     <= region_d;
+-            user_q       <= user_d;
+-            w_user_q     <= w_user_d;
+-            atop_data_q  <= atop_data_d;
+-            write_data_q <= write_data_d;
+-            data_valid_q <= data_valid_d;
+-            atop_q       <= atop_d;
++            aw_state_q  <= aw_state_d;
++            w_state_q   <= w_state_d;
++            b_state_q   <= b_state_d;
++            w_cnt_q     <= w_cnt_d;
++            w_cnt_req_q <= w_cnt_req_d;
++            w_cnt_inj_q <= w_cnt_inj_d;
++            addr_q      <= addr_d;
++            id_q        <= id_d;
++            size_q      <= size_d;
++            strb_q      <= strb_d;
++            cache_q     <= cache_d;
++            prot_q      <= prot_d;
++            qos_q       <= qos_d;
++            region_q    <= region_d;
++            aw_user_q   <= aw_user_d;
++            w_user_q    <= w_user_d;
++            w_data_q    <= w_data_d;
++            result_q    <= result_d;
++            w_d_valid_q <= w_d_valid_d;
++            atop_q      <= atop_d;
+         end
+     end
+ 
+@@ -716,7 +722,7 @@ module axi_riscv_amos #(
+                 slv_ar_ready_o = mst_ar_ready_i;
+ 
+                 if (adapter_ready) begin
+-                    if (atop_valid_d == VALID | atop_valid_d == STORE) begin
++                    if (atop_valid_d == LOAD | atop_valid_d == STORE) begin
+                         if (ar_free) begin
+                             // Acquire channel
+                             slv_ar_ready_o  = 1'b0;
+@@ -760,7 +766,7 @@ module axi_riscv_amos #(
+                     mst_ar_prot_o   = prot_q;
+                     mst_ar_qos_o    = qos_q;
+                     mst_ar_region_o = region_q;
+-                    mst_ar_user_o   = user_q;
++                    mst_ar_user_o   = aw_user_q;
+                     if (mst_ar_ready_i) begin
+                         // Request acknowledged
+                         ar_state_d = FEEDTHROUGH_AR;
+@@ -793,10 +799,10 @@ module axi_riscv_amos #(
+         slv_r_user_o  = mst_r_user_i;
+         slv_r_valid_o = mst_r_valid_i;
+         // Defaults FF
+-        read_data_d   = read_data_q;
++        r_data_d      = r_data_q;
+         r_resp_d      = r_resp_q;
+         r_user_d      = r_user_q;
+-        read_done_d   = read_done_q;
++        r_d_valid_d   = r_d_valid_q;
+         // State Machine
+         r_state_d     = r_state_q;
+ 
+@@ -805,9 +811,9 @@ module axi_riscv_amos #(
+             FEEDTHROUGH_R: begin
+                 if (adapter_ready) begin
+                     // Reset read flag
+-                    read_done_d = 1'b0;
++                    r_d_valid_d = 1'b0;
+ 
+-                    if (atop_valid_d == VALID || atop_valid_d == STORE) begin
++                    if (atop_valid_d == LOAD || atop_valid_d == STORE) begin
+                         // Wait for R response to read data
+                         r_state_d = WAIT_DATA_R;
+                     end else if (atop_valid_d == INVALID) begin
+@@ -841,10 +847,10 @@ module axi_riscv_amos #(
+                     mst_r_ready_o = 1'b1;
+                     slv_r_valid_o = 1'b0;
+                     // Store data
+-                    read_data_d = mst_r_data_i;
++                    r_data_d    = mst_r_data_i;
+                     r_resp_d    = mst_r_resp_i;
+                     r_user_d    = mst_r_user_i;
+-                    read_done_d = 1'b1;
++                    r_d_valid_d = 1'b1;
+                     if (atop_valid_q == STORE) begin
+                         r_state_d = FEEDTHROUGH_R;
+                     end else begin
+@@ -862,7 +868,7 @@ module axi_riscv_amos #(
+                     mst_r_ready_o = 1'b0;
+                     // Send R response
+                     slv_r_valid_o = 1'b1;
+-                    slv_r_data_o  = read_data_q;
++                    slv_r_data_o  = r_data_q;
+                     slv_r_id_o    = id_q;
+                     slv_r_last_o  = 1'b1;
+                     slv_r_resp_o  = r_resp_q;
+@@ -889,17 +895,17 @@ module axi_riscv_amos #(
+         if(~rst_ni) begin
+             ar_state_q  <= FEEDTHROUGH_AR;
+             r_state_q   <= FEEDTHROUGH_R;
+-            read_data_q <= '0;
++            r_data_q    <= '0;
+             r_resp_q    <= '0;
+             r_user_q    <= '0;
+-            read_done_q <= 1'b0;
++            r_d_valid_q <= 1'b0;
+         end else begin
+             ar_state_q  <= ar_state_d;
+             r_state_q   <= r_state_d;
+-            read_data_q <= read_data_d;
++            r_data_q    <= r_data_d;
+             r_resp_q    <= r_resp_d;
+             r_user_q    <= r_user_d;
+-            read_done_q <= read_done_d;
++            r_d_valid_q <= r_d_valid_d;
+         end
+     end
+ 
+@@ -907,19 +913,10 @@ module axi_riscv_amos #(
+      * ALU
+      */
+ 
+-    logic [AXI_ALU_RATIO-1:0][RISCV_WORD_WIDTH-1:0] op_a;
+-    logic [AXI_ALU_RATIO-1:0][RISCV_WORD_WIDTH-1:0] op_b;
+-    logic [AXI_ALU_RATIO-1:0][RISCV_WORD_WIDTH-1:0] op_a_sign_ext;
+-    logic [AXI_ALU_RATIO-1:0][RISCV_WORD_WIDTH-1:0] op_b_sign_ext;
+-    logic [AXI_ALU_RATIO-1:0][RISCV_WORD_WIDTH-1:0] res;
+-    logic [AXI_STRB_WIDTH-1:0][7:0]                 strb_ext;
+-    logic sign_a;
+-    logic sign_b;
+-
+-    assign op_a = read_data_q & strb_ext;
+-    assign op_b = atop_data_q & strb_ext;
+-    assign sign_a = |(op_a & ~(strb_ext >> 1));
+-    assign sign_b = |(op_b & ~(strb_ext >> 1));
++    assign op_a           = r_data_q & strb_ext;
++    assign op_b           = w_data_q & strb_ext;
++    assign sign_a         = |(op_a & ~(strb_ext >> 1));
++    assign sign_b         = |(op_b & ~(strb_ext >> 1));
+     assign alu_result_ext = res;
+ 
+     generate

patches/pulp-platform_axi_riscv_atomics_pr37.patch

@@ -0,0 +1,36 @@
+From dce8b09fe6d494e058c71d85cbbbf0ec469d4a11 Mon Sep 17 00:00:00 2001
+From: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
+Date: Fri, 26 Jul 2024 15:01:13 +0200
+Subject: [PATCH] axi_res_tbl: Declare `match` signal unconditionally
+
+Improves code style and prevents inferred latches.
+
+Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
+---
+ src/axi_res_tbl.sv | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/src/axi_res_tbl.sv b/src/axi_res_tbl.sv
+index 657e6f5..7daeb28 100644
+--- a/src/axi_res_tbl.sv
++++ b/src/axi_res_tbl.sv
+@@ -33,7 +33,10 @@ module axi_res_tbl #(
+     // Declarations of Signals and Types
+     logic [N_IDS-1:0][AXI_ADDR_WIDTH-1:0]   tbl_d,                      tbl_q;
+     logic                                   clr,
+-                                            set;
++                                            set,
++                                            match;
++
++    assign match = (tbl_q[check_id_i] == check_clr_addr_i);
+ 
+     generate for (genvar i = 0; i < N_IDS; ++i) begin: gen_tbl
+         always_comb begin
+@@ -55,7 +58,6 @@ module axi_res_tbl #(
+         check_clr_gnt_o = 1'b0;
+ 
+         if (check_clr_req_i) begin
+-            automatic logic match = (tbl_q[check_id_i] == check_clr_addr_i);
+             check_clr_gnt_o = 1'b1;
+             check_res_o     = match;
+             clr             = !(check_clr_excl_i && !match);

patches/pulp-platform_carfield_pr41.patch

@@ -0,0 +1,133 @@
+From 04637be9cca9c2caf08d03bf6dba5e5227fb62ab Mon Sep 17 00:00:00 2001
+From: aottaviano <aottaviano@iis.ee.ethz.ch>
+Date: Wed, 17 May 2023 08:40:52 +0200
+Subject: [PATCH 1/2] Add atomics support to shared L2 memory
+
+Expose extra parameters to config the rsicv_atomic_module. They default
+to Cheshire, which is fine for now.
+---
+ Bender.lock    |  3 ++-
+ Bender.yml     |  2 +-
+ hw/carfield.sv | 10 +++++++++-
+ hw/l2_wrap.sv  | 12 ++++++++++++
+ 4 files changed, 24 insertions(+), 3 deletions(-)
+
+diff --git a/Bender.lock b/Bender.lock
+index e9faac22..968fd4be 100644
+--- a/Bender.lock
++++ b/Bender.lock
+@@ -104,12 +104,13 @@ packages:
+       Git: git@github.com:AlSaqr-platform/can_bus.git
+     dependencies: []
+   car_l2:
+-    revision: 505c35a8df7f042fc8fc07c5dc40bc6412f7b27d
++    revision: 08503a05307ef556ed5439619c70c039ff93d77a
+     version: null
+     source:
+       Git: git@iis-git.ee.ethz.ch:carfield/carfield_l2_mem.git
+     dependencies:
+     - axi
++    - axi_riscv_atomics
+     - common_cells
+     - common_verification
+     - redundancy_cells
+diff --git a/Bender.yml b/Bender.yml
+index 850cdcba..1bdbfb76 100644
+--- a/Bender.yml
++++ b/Bender.yml
+@@ -14,7 +14,7 @@ dependencies:
+   axi:                { git: https://github.com/pulp-platform/axi.git,                  version: 0.39.0-beta.9                        } # overridden in Bender.local to use axi-rt feature
+   cheshire:           { git: https://github.com/pulp-platform/cheshire.git,             rev: 9f0234c1a40cd332f2b502cbbb5f98bd242b29ba } # branch: main
+   hyperbus:           { git: https://github.com/pulp-platform/hyperbus.git,             rev: 4d4d5d05959c83238a6fbf2537c15d411ca11b4b } # branch: main
+-  car_l2:             { git: git@iis-git.ee.ethz.ch:carfield/carfield_l2_mem.git,       rev: 505c35a8df7f042fc8fc07c5dc40bc6412f7b27d } # branch: main
++  car_l2:             { git: git@iis-git.ee.ethz.ch:carfield/carfield_l2_mem.git,       rev: 08503a05307ef556ed5439619c70c039ff93d77a } # branch: main
+   safety_island:      { git: git@iis-git.ee.ethz.ch:carfield/safety-island.git,         rev: 67f0b4ef4c3b08fcd423bc5e70db144b196cd2d1 } # branch: master
+   pulp_cluster:       { git: https://github.com/pulp-platform/pulp_cluster.git,         rev: 43bb73f5f239b6d9bade79ef4b5c62756bd58dc4 } # branch: yt/carfield-integration
+   opentitan:          { git: https://github.com/alsaqr-platform/opentitan.git,          rev: ed1e7f1d53e28de556a3b02bc1bd1b855f51af15 } # branch: lowRISC-rebase
+diff --git a/hw/carfield.sv b/hw/carfield.sv
+index d6ac6ab5..3950df4f 100644
+--- a/hw/carfield.sv
++++ b/hw/carfield.sv
+@@ -1026,7 +1026,15 @@ l2_wrap #(
+   .AxiMaxTrans  ( Cfg.AxiMaxSlvTrans     ),
+   .LogDepth     ( LogDepth               ),
+   .NumRules     ( L2NumRules             ),
+-  .L2MemSize    ( L2MemSize              )
++  .L2MemSize    ( L2MemSize              ),
++  // Atomics
++  .L2MaxReadTxns  ( Cfg.LlcMaxReadTxns   ), // TODO: AMO parameters are default
++                                            // from the LLC (Cheshire), at the
++                                            // moment
++  .L2MaxWriteTxns ( Cfg.LlcMaxWriteTxns  ),
++  .AxiUserAmoMsb  ( Cfg.AxiUserAmoMsb    ),
++  .AxiUserAmoLsb  ( Cfg.AxiUserAmoLsb    ),
++  .L2AmoNumCuts   ( Cfg.LlcAmoNumCuts    )
+ ) i_reconfigurable_l2 (
+   .clk_i               ( l2_clk                               ),
+   .rst_ni              ( l2_rst_n                             ),
+diff --git a/hw/l2_wrap.sv b/hw/l2_wrap.sv
+index 493a62cb..aa8e272e 100644
+--- a/hw/l2_wrap.sv
++++ b/hw/l2_wrap.sv
+@@ -19,6 +19,11 @@ module l2_wrap
+   parameter int unsigned AxiUserWidth = 1,
+   parameter int unsigned AxiMaxTrans  = 8,
+   parameter int unsigned LogDepth     = 3,
++  parameter int unsigned L2MaxReadTxns  = 8,
++  parameter int unsigned L2MaxWriteTxns = 8,
++  parameter int unsigned AxiUserAmoMsb  = 1,
++  parameter int unsigned AxiUserAmoLsb  = 0,
++  parameter int unsigned L2AmoNumCuts   = 1,
+   /// Mapping rules
+   parameter int unsigned NumRules   = car_l2_pkg::NUM_MAP_TYPES * NumPort,
+   /// L2 Memory settings
+@@ -138,6 +143,13 @@ car_l2_top #(
+   .NUM_MAP_RULES       ( NumRules        ),
+   .L2_MEM_SIZE_IN_BYTE ( L2MemSize       ),
+   .map_rule_t          ( map_rule_t      ),
++  .ATM_MAX_READ_TXN    ( L2MaxReadTxns   ),
++  .ATM_MAX_WRIT_TXN    ( L2MaxWriteTxns  ),
++  .ATM_USER_AS_ID      ( 1               ),
++  .ATM_USER_ID_MSB     ( AxiUserAmoMsb   ),
++  .ATM_USER_ID_LSB     ( AxiUserAmoLsb   ),
++  .ATM_RISCV_WORD      ( 64              ),
++  .ATM_NUM_CUTS        ( L2AmoNumCuts    ),
+   .axi_req_t           ( axi_async_req_t ),
+   .axi_resp_t          ( axi_async_rsp_t )
+ ) i_l2_top             (
+
+From b5c609e743916183294a426e981d7ef174697991 Mon Sep 17 00:00:00 2001
+From: Chi Zhang <chizhang@student.ethz.ch>
+Date: Tue, 30 May 2023 07:48:13 +0200
+Subject: [PATCH 2/2] [SW] Set a counter range for timer test
+
+---
+ sw/tests/hostd/system_timer_test.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/sw/tests/hostd/system_timer_test.c b/sw/tests/hostd/system_timer_test.c
+index 27dc2b4c..deb7bb99 100644
+--- a/sw/tests/hostd/system_timer_test.c
++++ b/sw/tests/hostd/system_timer_test.c
+@@ -21,8 +21,8 @@
+ 	} \
+     } while (0)
+ 
+-#define DUMMY_TIMER_CNT_GOLDEN 8070
+-#define HYPER_DUMMY_TIMER_CNT_GOLDEN 8192
++#define DUMMY_TIMER_CNT_GOLDEN_MIN 8050
++#define DUMMY_TIMER_CNT_GOLDEN_MAX 8250
+ 
+ int main(void) {
+ 
+@@ -43,8 +43,8 @@ int main(void) {
+ 
+     // Note: the result is checked against a golden value that is probed from
+     // the waveforms, to check if the value is correctly read from sw.
+-    if ( (time != DUMMY_TIMER_CNT_GOLDEN) && (time != HYPER_DUMMY_TIMER_CNT_GOLDEN) ) {
+-    	return 1;
++    if (time <= DUMMY_TIMER_CNT_GOLDEN_MIN || time >= DUMMY_TIMER_CNT_GOLDEN_MAX) {
++	return 1;
+     }
+     
+     return 0;

patches/pulp-platform_common_cells_pr225.patch

@@ -0,0 +1,168 @@
+From d99b266748f299195898fe2ebe7b14c5b6d000ea Mon Sep 17 00:00:00 2001
+From: Michael Rogenmoser <michael@rogenmoser.us>
+Date: Wed, 17 Jul 2024 17:31:46 +0200
+Subject: [PATCH 1/2] Add credit_counter
+
+Co-authored-by: Paul Scheffler <paulsc@iis.ee.ethz.ch>
+---
+ Bender.yml            |  1 +
+ CHANGELOG.md          |  4 +++
+ README.md             |  1 +
+ common_cells.core     |  1 +
+ src/credit_counter.sv | 57 +++++++++++++++++++++++++++++++++++++++++++
+ src_files.yml         |  1 +
+ 6 files changed, 65 insertions(+)
+ create mode 100644 src/credit_counter.sv
+
+diff --git a/Bender.yml b/Bender.yml
+index 05231665..f5a5a21b 100644
+--- a/Bender.yml
++++ b/Bender.yml
+@@ -32,6 +32,7 @@ sources:
+       - src/cdc_reset_ctrlr_pkg.sv
+       - src/cf_math_pkg.sv
+       - src/clk_int_div.sv
++      - src/credit_counter.sv
+       - src/delta_counter.sv
+       - src/ecc_pkg.sv
+       - src/edge_propagator_tx.sv
+diff --git a/CHANGELOG.md b/CHANGELOG.md
+index d9ee453f..f0df2aa7 100644
+--- a/CHANGELOG.md
++++ b/CHANGELOG.md
+@@ -4,6 +4,10 @@ All notable changes to this project will be documented in this file.
+ The format is based on [Keep a Changelog](http://keepachangelog.com/en/1.0.0/)
+ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.html).
+ 
++## Unreleased
++### Added
++- `credit_counter`: Add up/down counter for credit.
++
+ ## 1.36.0 - 2024-07-08
+ ### Fixed
+ - `registers`: Fix else statement in FFARNC macro.
+diff --git a/README.md b/README.md
+index 8c2aa59b..d91f6b37 100644
+--- a/README.md
++++ b/README.md
+@@ -55,6 +55,7 @@ Please note that cells with status *deprecated* are not to be used for new desig
+ | Name                | Description                                                       | Status       | Superseded By |
+ | ------------------- | ----------------------------------------------------------------- | ------------ | ------------- |
+ | `counter`           | Generic up/down counter with overflow detection                   | active       |               |
++| `credit_counter`    | Up/down counter for credit                                        | active       |               |
+ | `delta_counter`     | Up/down counter with variable delta and overflow detection        | active       |               |
+ | `generic_LFSR_8bit` | 8-bit linear feedback shift register (LFSR)                       | *deprecated* | `lfsr_8bit`   |
+ | `lfsr_8bit`         | 8-bit linear feedback shift register (LFSR)                       | active       |               |
+diff --git a/common_cells.core b/common_cells.core
+index bcdd5059..bd10e7c6 100644
+--- a/common_cells.core
++++ b/common_cells.core
+@@ -16,6 +16,7 @@ filesets:
+       - src/cc_onehot.sv
+       - src/cf_math_pkg.sv
+       - src/clk_int_div.sv
++      - src/credit_counter.sv
+       - src/delta_counter.sv
+       - src/ecc_pkg.sv
+       - src/edge_propagator_tx.sv
+diff --git a/src/credit_counter.sv b/src/credit_counter.sv
+new file mode 100644
+index 00000000..b29312ae
+--- /dev/null
++++ b/src/credit_counter.sv
+@@ -0,0 +1,57 @@
++// Copyright 2020 ETH Zurich and University of Bologna.
++// Solderpad Hardware License, Version 0.51, see LICENSE for details.
++// SPDX-License-Identifier: SHL-0.51
++
++// Author: Fabian Schuiki <fschuiki@iis.ee.ethz.ch>
++// Author: Paul Scheffler <paulsc@iis.ee.ethz.ch>
++
++`include "common_cells/registers.svh"
++`include "common_cells/assertions.svh"
++
++module credit_counter #(
++  parameter int unsigned NumCredits      = 0,
++  /// Whether credit is full or empty on reset
++  parameter bit          InitCreditEmpty = 1'b0,
++  /// Derived parameters *Do not override*
++  parameter int unsigned InitNumCredits  = InitCreditEmpty ? '0 : NumCredits,
++  parameter type         credit_cnt_t    = logic [$clog2(NumCredits):0]
++) (
++  input  logic clk_i,
++  input  logic rst_ni,
++
++  output credit_cnt_t credit_o,
++
++  input  logic credit_give_i,
++  input  logic credit_take_i,
++  input  logic credit_init_i,  // Reinitialize (soft-reset) credit; takes priority
++
++  output logic credit_left_o,
++  output logic credit_crit_o,  // Giving one more credit will fill the credits
++  output logic credit_full_o
++);
++
++  credit_cnt_t credit_d, credit_q;
++  logic increment, decrement;
++
++  assign decrement = credit_take_i & ~credit_give_i;
++  assign increment = ~credit_take_i & credit_give_i;
++
++  always_comb begin
++    credit_d = credit_q;
++    if      (decrement) credit_d = credit_q - 1;
++    else if (increment) credit_d = credit_q + 1;
++  end
++
++  logic credit_load;
++  assign credit_load = 1'b1;
++  `FFLARNC(credit_q, credit_d, credit_load, credit_init_i, InitNumCredits, clk_i, rst_ni)
++
++  assign credit_o       = credit_q;
++  assign credit_left_o  = (credit_q != '0);
++  assign credit_crit_o  = (credit_q == NumCredits-1);
++  assign credit_full_o  = (credit_q == NumCredits);
++
++  `ASSERT_NEVER(CreditUnderflow, credit_o == '0 && decrement)
++  `ASSERT_NEVER(CreditOverflow, credit_o == NumCredits && increment)
++
++endmodule
+diff --git a/src_files.yml b/src_files.yml
+index 0449fabe..30aebdba 100644
+--- a/src_files.yml
++++ b/src_files.yml
+@@ -11,6 +11,7 @@ common_cells_all:
+     - src/cc_onehot.sv
+     - src/cf_math_pkg.sv
+     - src/clk_int_div.sv
++    - src/credit_counter.sv
+     - src/delta_counter.sv
+     - src/ecc_pkg.sv
+     - src/edge_propagator_tx.sv
+
+From 483b3dd64c64bfc4ae37e4cc3665ea339b4be01f Mon Sep 17 00:00:00 2001
+From: Michael Rogenmoser <michael@rogenmoser.us>
+Date: Thu, 18 Jul 2024 14:00:40 +0200
+Subject: [PATCH 2/2] credit_counter: replace FFLARNC with FFARNC
+
+Co-authored-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
+---
+ src/credit_counter.sv | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+diff --git a/src/credit_counter.sv b/src/credit_counter.sv
+index b29312ae..2792fd5a 100644
+--- a/src/credit_counter.sv
++++ b/src/credit_counter.sv
+@@ -42,9 +42,7 @@ module credit_counter #(
+     else if (increment) credit_d = credit_q + 1;
+   end
+ 
+-  logic credit_load;
+-  assign credit_load = 1'b1;
+-  `FFLARNC(credit_q, credit_d, credit_load, credit_init_i, InitNumCredits, clk_i, rst_ni)
++  `FFARNC(credit_q, credit_d, credit_init_i, InitNumCredits, clk_i, rst_ni)
+ 
+   assign credit_o       = credit_q;
+   assign credit_left_o  = (credit_q != '0);

patches/pulp-platform_common_verification_pr5.patch

@@ -0,0 +1,74 @@
+From 8689363a330744cf69692589cf5c1d9c9c865413 Mon Sep 17 00:00:00 2001
+From: Michael Rogenmoser <michael@rogenmoser.us>
+Date: Wed, 3 Aug 2022 16:50:41 +0200
+Subject: [PATCH] Add signal highlighter
+
+---
+ Bender.yml                |  1 +
+ CHANGELOG.md              |  1 +
+ src/signal_highlighter.sv | 32 ++++++++++++++++++++++++++++++++
+ 3 files changed, 34 insertions(+)
+ create mode 100644 src/signal_highlighter.sv
+
+diff --git a/Bender.yml b/Bender.yml
+index b3a5868..a122dc4 100644
+--- a/Bender.yml
++++ b/Bender.yml
+@@ -16,6 +16,7 @@ sources:
+     - src/rand_stream_mst.sv
+     - src/rand_synch_holdable_driver.sv
+     - src/rand_verif_pkg.sv
++    - src/signal_highlighter.sv
+     - src/sim_timeout.sv
+     # Level 1
+     - src/rand_synch_driver.sv
+diff --git a/CHANGELOG.md b/CHANGELOG.md
+index bd6f4ed..caa4fb5 100644
+--- a/CHANGELOG.md
++++ b/CHANGELOG.md
+@@ -8,6 +8,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
+ ## Unreleased
+ 
+ ### Added
++- Add signal highlighter
+ 
+ ### Changed
+ 
+diff --git a/src/signal_highlighter.sv b/src/signal_highlighter.sv
+new file mode 100644
+index 0000000..0ef4c41
+--- /dev/null
++++ b/src/signal_highlighter.sv
+@@ -0,0 +1,32 @@
++// Copyright (c) 2022 ETH Zurich, University of Bologna
++//
++// Copyright and related rights are licensed under the Solderpad Hardware
++// License, Version 0.51 (the "License"); you may not use this file except in
++// compliance with the License.  You may obtain a copy of the License at
++// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
++// or agreed to in writing, software, hardware and materials distributed under
++// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
++// CONDITIONS OF ANY KIND, either express or implied. See the License for the
++// specific language governing permissions and limitations under the License.
++//
++// Author: Thomas Benz <tbenz@ethz.ch>
++
++// highlights a signal in the waveform for easier viewing
++module signal_highlighter #(
++    parameter type T = logic
++)(
++    input logic ready_i,
++    input logic valid_i,
++    input T data_i
++);
++
++    T in_wave;
++
++    always_comb begin
++        in_wave = 'Z;
++        if (ready_i & valid_i) begin
++            in_wave = data_i;
++        end
++    end
++
++endmodule

patches/pulp-platform_hci_pr37.patch

@@ -0,0 +1,120 @@
+From 3564c89afe9f36ec5534b4fe6d25aa11ba16d13c Mon Sep 17 00:00:00 2001
+From: Francesco Conti <FrancescoConti@users.noreply.github.com>
+Date: Wed, 22 May 2024 22:46:32 +0200
+Subject: [PATCH] Fix #34 by keeping winner_d stable in OOO Mux if there is an
+ input request
+
+Only re-evaluate WTA output after an output handshake or if any
+in_req was 0, otherwise a more recent in_req could overtake an
+older one causing a RQ3-STABILITY issue on the output side.
+---
+ rtl/core/hci_core_mux_ooo.sv | 67 +++++++++++++++++++++++++++++++-----
+ 1 file changed, 59 insertions(+), 8 deletions(-)
+
+diff --git a/rtl/core/hci_core_mux_ooo.sv b/rtl/core/hci_core_mux_ooo.sv
+index 5920757..9fdabf8 100644
+--- a/rtl/core/hci_core_mux_ooo.sv
++++ b/rtl/core/hci_core_mux_ooo.sv
+@@ -84,10 +84,12 @@ module hci_core_mux_ooo
+ 
+   logic [$clog2(NB_CHAN)-1:0]              rr_counter_q;
+   logic [NB_CHAN-1:0][$clog2(NB_CHAN)-1:0] rr_priority_d;
+-  logic [$clog2(NB_CHAN)-1:0]              winner_d;
++  logic [$clog2(NB_CHAN)-1:0]              winner_d, winner_q;
+ 
+-  logic s_rr_counter_reg_en;
+-  assign s_rr_counter_reg_en = out.req & out.gnt;
++  logic rr_counter_en_d, rr_counter_en_q;
++  assign rr_counter_en_d = out.req & out.gnt;
++
++  logic any_req_q;
+ 
+   // round-robin counter
+   always_ff @(posedge clk_i, negedge rst_ni)
+@@ -98,7 +100,7 @@ module hci_core_mux_ooo
+     else if (clear_i == 1'b1) begin
+       rr_counter_q <= '0;
+     end
+-    else if (s_rr_counter_reg_en) begin
++    else if (rr_counter_en_d) begin
+       if (rr_counter_q == NB_CHAN-1)
+         rr_counter_q <= '0;
+       else
+@@ -106,6 +108,48 @@ module hci_core_mux_ooo
+     end
+   end
+ 
++  // keep previous winner in case of no-gnt
++  always_ff @(posedge clk_i, negedge rst_ni)
++  begin : winner_reg
++    if(rst_ni == 1'b0) begin
++      winner_q <= '0;
++    end
++    else if (clear_i == 1'b1) begin
++      winner_q <= '0;
++    end
++    else begin
++      winner_q <= winner_d;
++    end
++  end
++
++  // keep track of round-robin counter updates (= output handshakes) to enable WTA circuit
++  always_ff @(posedge clk_i, negedge rst_ni)
++  begin : rr_counter_en_reg
++    if(rst_ni == 1'b0) begin
++      rr_counter_en_q <= '0;
++    end
++    else if (clear_i == 1'b1) begin
++      rr_counter_en_q <= '0;
++    end
++    else begin
++      rr_counter_en_q <= rr_counter_en_d;
++    end
++  end
++
++  // keep track of any input requests to enable WTA circuit
++  always_ff @(posedge clk_i, negedge rst_ni)
++  begin : any_req_reg
++    if(rst_ni == 1'b0) begin
++      any_req_q <= '0;
++    end
++    else if (clear_i == 1'b1) begin
++      any_req_q <= '0;
++    end
++    else begin
++      any_req_q <= |(in_req);
++    end
++  end
++
+   for(genvar ii=0; ii<NB_CHAN; ii++) begin: in_port_binding
+ 
+     assign in_req     [ii] = in[ii].req;
+@@ -127,6 +171,7 @@ module hci_core_mux_ooo
+     assign in[ii].r_opc    = out.r_opc;
+     assign in[ii].r_user   = out.r_user;
+     assign in[ii].r_ecc    = out.r_ecc;
++    assign in[ii].r_id     = out.r_id;
+     assign in[ii].egnt     = in_egnt;
+     assign in[ii].r_evalid = in_r_evalid;
+ 
+@@ -138,10 +183,16 @@ module hci_core_mux_ooo
+   // winner-takes-all circuit for arbitration, depending on round-robin priorities
+   always_comb
+   begin : wta_comb
+-    winner_d = rr_counter_q;
+-    for(int jj=0; jj<NB_CHAN; jj++) begin
+-      if (in_req[rr_priority_d[NB_CHAN-jj-1]] == 1'b1)
+-        winner_d = rr_priority_d[NB_CHAN-jj-1];
++    winner_d = winner_q;
++    // only re-evaluate WTA output after an output handshake or if any
++    // in_req was 0, otherwise a more recent in_req could overtake an
++    // older one causing a RQ3-STABILITY issue on the output side.
++    if(rr_counter_en_q | ~any_req_q) begin
++      winner_d = rr_counter_q;
++      for(int jj=0; jj<NB_CHAN; jj++) begin
++        if (in_req[rr_priority_d[NB_CHAN-jj-1]] == 1'b1)
++          winner_d = rr_priority_d[NB_CHAN-jj-1];
++      end
+     end
+   end
+ 

patches/svunit_svunit_pr197.patch

@@ -0,0 +1,23 @@
+From 3f12dc2d932d11ba76cdbf233f9830c1499f80a7 Mon Sep 17 00:00:00 2001
+From: Tudor Timi <tudortimi@users.noreply.github.com>
+Date: Sat, 22 Oct 2022 22:09:52 +0300
+Subject: [PATCH] Fix warning related to string comparison
+
+`s[i]` returns a `byte`, whereas `char` is a `string`. DVT and VCS complain about this comparison, while Xcelium and QuestaSim are fine with it. No idea who is in the right here, but we don't want warnings in any of the tools.
+---
+ svunit_base/svunit_string_utils.svh | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/svunit_base/svunit_string_utils.svh b/svunit_base/svunit_string_utils.svh
+index 2b2e5b43..b1a437b1 100644
+--- a/svunit_base/svunit_string_utils.svh
++++ b/svunit_base/svunit_string_utils.svh
+@@ -13,7 +13,7 @@
+     for (int i = 0; i < s.len(); i++) begin
+       if (i == s.len()-1)
+         parts.push_back(s.substr(last_char_position+1, i));
+-      if (s[i] == char) begin
++      if (string'(s[i]) == char) begin
+         parts.push_back(s.substr(last_char_position+1, i-1));
+         last_char_position = i;
+       end

patches/verilator_verilator_pr6596.patch

@@ -0,0 +1,235 @@
+From e36c5491128ba9acd79cc5064c3e7ac60bd233a8 Mon Sep 17 00:00:00 2001
+From: Geza Lore <gezalore@gmail.com>
+Date: Sat, 25 Oct 2025 17:19:15 +0100
+Subject: [PATCH 1/2] Fix V3Life eliminating assignments across timing controls
+
+For both JumpBlock and Loop, record if they contain a timing control and
+do not eliminate assignments across them if so.
+
+Fixes #6593
+---
+ src/V3Life.cpp                           | 36 +++++++-----
+ test_regress/t/t_opt_life_timing_loop.py | 18 ++++++
+ test_regress/t/t_opt_life_timing_loop.v  | 75 ++++++++++++++++++++++++
+ 3 files changed, 113 insertions(+), 16 deletions(-)
+ create mode 100755 test_regress/t/t_opt_life_timing_loop.py
+ create mode 100644 test_regress/t/t_opt_life_timing_loop.v
+
+diff --git a/src/V3Life.cpp b/src/V3Life.cpp
+index 3b14c839be2..f0d592b1c98 100644
+--- a/src/V3Life.cpp
++++ b/src/V3Life.cpp
+@@ -278,6 +278,7 @@ class LifeBlock final {
+ class LifeVisitor final : public VNVisitor {
+     // STATE
+     LifeState* const m_statep;  // Current state
++    bool m_containsTiming = false; // Statement contains timing control
+     bool m_sideEffect = false;  // Side effects discovered in assign RHS
+     bool m_noopt = false;  // Disable optimization of variables in this block
+     bool m_tracingCall = false;  // Iterating into a CCall to a CFunc
+@@ -308,6 +309,7 @@ class LifeVisitor final : public VNVisitor {
+         if (nodep->isTimingControl() || VN_IS(nodep, AssignForce)) {
+             // V3Life doesn't understand time sense nor force assigns - don't optimize
+             setNoopt();
++            if (nodep->isTimingControl()) m_containsTiming = true;
+             iterateChildren(nodep);
+             return;
+         }
+@@ -345,6 +347,7 @@ class LifeVisitor final : public VNVisitor {
+         if (nodep->isTimingControl()) {
+             // Don't optimize
+             setNoopt();
++            m_containsTiming = true;
+         }
+         // Don't treat as normal assign
+         iterateChildren(nodep);
+@@ -379,37 +382,37 @@ class LifeVisitor final : public VNVisitor {
+     void visit(AstLoop* nodep) override {
+         // Similar problem to AstJumpBlock, don't optimize loop bodies - most are unrolled
+         UASSERT_OBJ(!nodep->contsp(), nodep, "'contsp' only used before LinkJump");
+-        LifeBlock* const prevLifep = m_lifep;
+-        LifeBlock* const bodyLifep = new LifeBlock{prevLifep, m_statep};
++        VL_RESTORER(m_containsTiming);
+         {
+             VL_RESTORER(m_noopt);
+-            m_lifep = bodyLifep;
++            VL_RESTORER(m_lifep);
++            m_lifep = new LifeBlock{m_lifep, m_statep};
+             setNoopt();
+             iterateAndNextNull(nodep->stmtsp());
+-            m_lifep = prevLifep;
++            UINFO(4, "   joinloop");
++            // For the next assignments, clear any variables that were read or written in the block
++            m_lifep->lifeToAbove();
++            VL_DO_DANGLING(delete m_lifep, m_lifep);
+         }
+-        UINFO(4, "   joinloop");
+-        // For the next assignments, clear any variables that were read or written in the block
+-        bodyLifep->lifeToAbove();
+-        VL_DO_DANGLING(delete bodyLifep, bodyLifep);
++        if (m_containsTiming) setNoopt();
+     }
+     void visit(AstJumpBlock* nodep) override {
+         // As with Loop's we can't predict if a JumpGo will kill us or not
+         // It's worse though as an IF(..., JUMPGO) may change the control flow.
+         // Just don't optimize blocks with labels; they're rare - so far.
+-        LifeBlock* const prevLifep = m_lifep;
+-        LifeBlock* const bodyLifep = new LifeBlock{prevLifep, m_statep};
++        VL_RESTORER(m_containsTiming);
+         {
+             VL_RESTORER(m_noopt);
+-            m_lifep = bodyLifep;
++            VL_RESTORER(m_lifep);
++            m_lifep = new LifeBlock{m_lifep, m_statep};
+             setNoopt();
+             iterateAndNextNull(nodep->stmtsp());
+-            m_lifep = prevLifep;
++            UINFO(4, "   joinjump");
++            // For the next assignments, clear any variables that were read or written in the block
++            m_lifep->lifeToAbove();
++            VL_DO_DANGLING(delete m_lifep, m_lifep);
+         }
+-        UINFO(4, "   joinjump");
+-        // For the next assignments, clear any variables that were read or written in the block
+-        bodyLifep->lifeToAbove();
+-        VL_DO_DANGLING(delete bodyLifep, bodyLifep);
++        if (m_containsTiming) setNoopt();
+     }
+     void visit(AstNodeCCall* nodep) override {
+         // UINFO(4, "  CCALL " << nodep);
+@@ -447,6 +450,7 @@ class LifeVisitor final : public VNVisitor {
+         if (nodep->isTimingControl()) {
+             // V3Life doesn't understand time sense - don't optimize
+             setNoopt();
++            m_containsTiming = true;
+         }
+         iterateChildren(nodep);
+     }
+diff --git a/test_regress/t/t_opt_life_timing_loop.py b/test_regress/t/t_opt_life_timing_loop.py
+new file mode 100755
+index 00000000000..19217b26413
+--- /dev/null
++++ b/test_regress/t/t_opt_life_timing_loop.py
+@@ -0,0 +1,18 @@
++#!/usr/bin/env python3
++# DESCRIPTION: Verilator: Verilog Test driver/expect definition
++#
++# Copyright 2025 by Wilson Snyder. This program is free software; you
++# can redistribute it and/or modify it under the terms of either the GNU
++# Lesser General Public License Version 3 or the Perl Artistic License
++# Version 2.0.
++# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
++
++import vltest_bootstrap
++
++test.scenarios('vlt_all')
++
++test.compile(verilator_flags2=["--timing", "--binary"])
++
++test.execute()
++
++test.passes()
+diff --git a/test_regress/t/t_opt_life_timing_loop.v b/test_regress/t/t_opt_life_timing_loop.v
+new file mode 100644
+index 00000000000..c2d1e36bb17
+--- /dev/null
++++ b/test_regress/t/t_opt_life_timing_loop.v
+@@ -0,0 +1,75 @@
++// DESCRIPTION: Verilator: Verilog Test module
++//
++// This file ONLY is placed under the Creative Commons Public Domain, for
++// any use, without warranty, 2025 by Wilson Snyder.
++// SPDX-License-Identifier: CC0-1.0
++
++// verilog_format: off
++`define stop $stop
++`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%t %%Error: %s:%0d:  got=%0d exp=%0d\n", $time, `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
++// verilog_format: on
++
++module t;
++
++  bit clk = 0;
++  always #10 clk = ~clk;
++
++  // Case A
++  bit [3:0] cnt_A = 0;
++  task task_A();
++    $display("%t %m enter", $time);
++    cnt_A = 0;
++    repeat (2) @(posedge clk);
++    for (int i = 0; i < 8; i++) begin : loop
++      $display("%t %m inc %d", $time, i);
++      ++cnt_A;
++      repeat (2) @(posedge clk);
++    end
++    $display("%t %m inc final", $time);
++    ++cnt_A;
++    repeat (2) @(posedge clk);
++    $display("%t %m exit", $time);
++  endtask
++
++  // Case B - Same, with 'repeat' unrolled
++  bit [3:0] cnt_B = 0;
++  task task_B();
++    $display("%t %m enter", $time);
++    cnt_B = 0;
++    @(posedge clk);
++    @(posedge clk);
++    for (int i = 0; i < 8; i++) begin : loop
++      ++cnt_B;
++      @(posedge clk);
++      @(posedge clk);
++    end
++    $display("%t %m inc final", $time);
++    ++cnt_B;
++    @(posedge clk);
++    @(posedge clk);
++    $display("%t %m exit", $time);
++  endtask
++
++  initial begin
++    task_A();
++    $display("%t taks_A return 1", $time);
++    task_A();
++    $display("%t taks_A return 2", $time);
++  end
++
++  initial begin
++    task_B();
++    $display("%t taks_B return 1", $time);
++    task_B();
++    $display("%t taks_B return 2", $time);
++
++    #100;
++    $write("*-* All Finished *-*\n");
++    $finish;
++  end
++
++  always_ff @(posedge clk) begin
++    #1 `checkd(cnt_A, cnt_B);
++  end
++
++endmodule
+
+From e0e2e0fdacebdc4cd9373f780f61a15fb43422a4 Mon Sep 17 00:00:00 2001
+From: github action <action@example.com>
+Date: Sat, 25 Oct 2025 16:27:56 +0000
+Subject: [PATCH 2/2] Apply 'make format'
+
+---
+ src/V3Life.cpp | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/V3Life.cpp b/src/V3Life.cpp
+index f0d592b1c98..938281e32d5 100644
+--- a/src/V3Life.cpp
++++ b/src/V3Life.cpp
+@@ -278,7 +278,7 @@ class LifeBlock final {
+ class LifeVisitor final : public VNVisitor {
+     // STATE
+     LifeState* const m_statep;  // Current state
+-    bool m_containsTiming = false; // Statement contains timing control
++    bool m_containsTiming = false;  // Statement contains timing control
+     bool m_sideEffect = false;  // Side effects discovered in assign RHS
+     bool m_noopt = false;  // Disable optimization of variables in this block
+     bool m_tracingCall = false;  // Iterating into a CCall to a CFunc

testbench/_coverage_main.cpp

@@ -0,0 +1,32 @@
+#include "Vhwe_cov_top.h"
+#include "verilated.h"
+#include "verilated_cov.h"
+
+#include <cstdlib>
+#include <memory>
+
+int main(int argc, char** argv, char**) {
+    Verilated::debug(0);
+
+    const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
+    contextp->commandArgs(argc, argv);
+
+    const std::unique_ptr<Vhwe_cov_top> topp{new Vhwe_cov_top{contextp.get()}};
+
+    const char* max_eval_env = std::getenv("HWE_COVERAGE_MAX_EVAL");
+    const unsigned long long max_eval =
+        (max_eval_env && max_eval_env[0]) ? std::strtoull(max_eval_env, nullptr, 10) : 0ULL;
+    unsigned long long eval_count = 0;
+
+    while (!contextp->gotFinish()) {
+        topp->eval();
+        if (max_eval && ++eval_count >= max_eval) break;
+        if (!topp->eventsPending()) break;
+        contextp->time(topp->nextTimeSlot());
+    }
+
+    topp->final();
+    const char* coverage_file = std::getenv("HWE_COVERAGE_FILE");
+    VerilatedCov::write((coverage_file && coverage_file[0]) ? coverage_file : "coverage.dat");
+    return 0;
+}

testbench/_open_tool_p2p_extra.py

@@ -0,0 +1,1310 @@
+#!/usr/bin/env python3
+import os
+import re
+import subprocess
+import sys
+from pathlib import Path
+
+
+def quote_cmd(argv):
+    return " ".join("'" + str(a).replace("'", "'\\''") + "'" for a in argv)
+
+
+def run(argv, cwd, timeout=60):
+    env = None
+    if argv and Path(str(argv[0])).name == "surelog":
+        env = os.environ.copy()
+        env.pop("PYTHONHOME", None)
+    try:
+        proc = subprocess.run(
+            argv,
+            cwd=cwd,
+            env=env,
+            text=True,
+            stdout=subprocess.PIPE,
+            stderr=subprocess.STDOUT,
+            timeout=timeout,
+        )
+        return proc.returncode, proc.stdout
+    except subprocess.TimeoutExpired as exc:
+        out = exc.stdout if isinstance(exc.stdout, str) else ""
+        return 124, out + "\nTIMEOUT\n"
+    except FileNotFoundError as exc:
+        return 127, str(exc) + "\n"
+
+
+def patch_targets(patch_file):
+    targets = []
+    if not patch_file.is_file():
+        return targets
+    for line in patch_file.read_text(errors="ignore").splitlines():
+        if line.startswith(("+++ b/", "--- a/")):
+            path = line[6:].split("\t")[0]
+            if path != "/dev/null":
+                targets.append(path)
+        elif line.startswith("diff --git "):
+            match = re.match(r"diff --git a/(.*?) b/(.*)$", line)
+            if match:
+                targets.extend(match.groups())
+    exts = {".v", ".sv", ".vh", ".svh", ".py", ".c", ".cc", ".cpp", ".h", ".hpp"}
+    return sorted({t for t in targets if Path(t).suffix.lower() in exts})
+
+
+def inc_dirs(scratch, targets):
+    names = [
+        ".",
+        "src",
+        "rtl",
+        "hdl",
+        "include",
+        "includes",
+        "test",
+        "tests",
+        "tb",
+        "dv",
+        "verif",
+        "verification",
+        "formal",
+        "hw",
+        "hw/xilinx/rtl",
+        "sys",
+        "mappers",
+        "rtl/src",
+        "src/include",
+        "rtl/include",
+    ]
+    dirs = [scratch / name for name in names if (scratch / name).exists()]
+    for target in targets:
+        path = scratch / target
+        if path.exists():
+            dirs.append(path.parent)
+    return list(dict.fromkeys(dirs))
+
+
+def parse_qsf(path):
+    files = []
+    for line in path.read_text(errors="ignore").splitlines():
+        match = re.search(r"-name\s+(?:SYSTEM)?VERILOG_FILE\s+(.+)$", line, re.I)
+        if not match:
+            match = re.search(r"-name\s+VERILOG_FILE\s+(.+)$", line, re.I)
+        if match:
+            files.append((path.parent / match.group(1).strip().strip('"')).resolve())
+    return [p for p in files if p.exists() and p.suffix.lower() in {".v", ".sv", ".vh", ".svh"}]
+
+
+def filelist_hdl_count(path):
+    count = 0
+    if not path.is_file():
+        return 0
+    for line in path.read_text(errors="ignore").splitlines():
+        line = line.strip()
+        if not line or line.startswith(("#", "//", "+incdir+", "-I")):
+            continue
+        for token in line.split():
+            token = token.strip().strip('"').strip("'")
+            if token.startswith(("+", "-")):
+                continue
+            if Path(token).suffix.lower() in {".v", ".sv", ".vh", ".svh"}:
+                count += 1
+    return count
+
+
+def filelists(scratch):
+    found = []
+    for pattern in ("*.f", "*.F", "*.flist", "*.vf", "*.vfiles", "*.qsf"):
+        found.extend(scratch.rglob(pattern))
+
+    def score(path):
+        rel = path.relative_to(scratch).as_posix().lower()
+        bonus = 0
+        for token in ("file", "files", "rtl", "sim", "verilator", "icarus", "questa", "project"):
+            if token in rel:
+                bonus -= 5
+        return (len(path.relative_to(scratch).parts), bonus, rel)
+
+    return sorted(found, key=score)[:30]
+
+
+def try_one(tag, name, argv, scratch, log):
+    rc, output = run(argv, scratch)
+    with log.open("a", errors="ignore") as fh:
+        fh.write(f"\n### {name}\n")
+        fh.write(quote_cmd(argv) + "\n")
+        fh.write(output[-12000:])
+        fh.write(f"\nrc={rc}\n")
+    return rc == 0
+
+
+def try_native_simulations(tag, case_name, scratch, log):
+    libsv_smoke = {
+        "bensampson5_libsv_pr61": (
+            [["src/base/mux/onehot_mux.sv", "src/core/mux/onehot_mux.sv"]],
+            """`timescale 1ns/1ps
+module tb; logic [3:0] sel; logic [31:0] in; wire [7:0] out;
+  onehot_mux #(.DW(8),.N(4)) dut(.sel(sel),.in(in),.out(out));
+  initial begin sel=4'b0100; in=32'h44332211; #1; $display("PASS: onehot_mux smoke out=%h",out); $finish; end
+endmodule
+""",
+        ),
+        "bensampson5_libsv_pr100": (
+            [["libsv/decoders/bcd_decoder.sv", "libsv/coders/bcd_decoder.sv"]],
+            """`timescale 1ns/1ps
+module tb; localparam int N=2; logic [4*N-1:0] i_bcd; wire [3*N+(N+2)/3-1:0] o_bin;
+  bcd_decoder #(.N(N)) dut(.i_bcd(i_bcd),.o_bin(o_bin));
+  initial begin i_bcd='0; #1; $display("PASS: bcd_decoder smoke o=%0d",o_bin); $finish; end
+endmodule
+""",
+        ),
+        "bensampson5_libsv_pr109": (
+            ["libsv/coders/encoder_8b10b.sv"],
+            """`timescale 1ns/1ps
+module tb; logic clk=0,rstn=0,en=0,ctrl=0,err; logic [7:0] d=0; wire [9:0] q;
+  encoder_8b10b dut(clk,rstn,en,d,ctrl,q,err);
+  always #1 clk=!clk;
+  initial begin #2 rstn=1; en=1; d=8'h00; #4; $display("PASS: encoder_8b10b smoke q=%b err=%0d",q,err); $finish; end
+endmodule
+""",
+        ),
+        "bensampson5_libsv_pr119": (
+            ["libsv/coders/bcd_decoder.sv"],
+            """`timescale 1ns/1ps
+module tb; localparam int N=2; logic [4*N-1:0] i_bcd; wire [3*N+(N+2)/3-1:0] o_bin;
+  bcd_decoder #(.N(N)) dut(.i_bcd(i_bcd),.o_bin(o_bin));
+  initial begin i_bcd='0; #1; $display("PASS: bcd_decoder smoke o=%0d",o_bin); $finish; end
+endmodule
+""",
+        ),
+        "bensampson5_libsv_pr132": (
+            ["libsv/coders/priority_encoder.sv"],
+            """`timescale 1ns/1ps
+module tb; logic [3:0] i; wire [1:0] o; wire v;
+  priority_encoder dut(i,o,v);
+  initial begin i=4'b0100; #1; $display("PASS: priority_encoder smoke o=%0d v=%0d",o,v); $finish; end
+endmodule
+""",
+        ),
+        "bensampson5_libsv_pr150": (
+            ["libsv/synchronizers/synchronizer.sv"],
+            """`timescale 1ns/1ps
+module tb; logic clk=0, rstn=0, din=0; wire dout;
+  synchronizer #(.FF_STAGES(2)) dut(clk,rstn,din,dout);
+  always #1 clk=!clk;
+  initial begin #2 rstn=1; din=1; #8; $display("PASS: synchronizer smoke dout=%0d",dout); $finish; end
+endmodule
+""",
+        ),
+        "bensampson5_libsv_pr153": (
+            ["libsv/coders/encoder_8b10b.sv"],
+            """`timescale 1ns/1ps
+module tb; logic clk=0,rstn=0,en=0,ctrl=0,err; logic [7:0] d=0; wire [9:0] q;
+  encoder_8b10b dut(clk,rstn,en,d,ctrl,q,err);
+  always #1 clk=!clk;
+  initial begin #2 rstn=1; en=1; d=8'h00; #4; $display("PASS: encoder_8b10b smoke q=%b err=%0d",q,err); $finish; end
+endmodule
+""",
+        ),
+    }
+    multimedia_smoke = {
+        "Multimedia-Processing_Digital-Logic-Design_pr46": (
+            "VerilogHDL_Practice/CH3/wire_and_or.v",
+            "VerilogHDL_Practice/CH3/wire_and_or_test.v",
+        ),
+        "Multimedia-Processing_Digital-Logic-Design_pr48": (
+            "VerilogHDL_Practice/CH3/wire_and_or.v",
+            "VerilogHDL_Practice/CH3/wire_and_or_test.v",
+        ),
+        "Multimedia-Processing_Digital-Logic-Design_pr50": (
+            "VerilogHDL_Practice/CH3/wire_and_or.v",
+            "VerilogHDL_Practice/CH3/wire_and_or_test.v",
+        ),
+        "Multimedia-Processing_Digital-Logic-Design_pr60": (
+            "VerilogHDL_Practice/CH3/wire_and_or.v",
+            "VerilogHDL_Practice/CH3/wire_and_or_test.v",
+        ),
+        "Multimedia-Processing_Digital-Logic-Design_pr62": (
+            "VerilogHDL_Practice/CH5/op.v",
+            "VerilogHDL_Practice/CH5/op_test.v",
+        ),
+        "Multimedia-Processing_Digital-Logic-Design_pr65": (
+            "Example/VerilogHDL_Practice/CH7/two_com_if.v",
+            "Example/VerilogHDL_Practice/CH7/two_com_if_test.v",
+        ),
+        "Multimedia-Processing_Digital-Logic-Design_pr68": (
+            "Example/VerilogHDL_Practice/CH7/two_com_if.v",
+            "Example/VerilogHDL_Practice/CH7/two_com_if_test.v",
+        ),
+    }
+    utoss_rf_tb = {
+        "UTOSS_risc-v_pr107",
+        "UTOSS_risc-v_pr35",
+        "UTOSS_risc-v_pr48",
+        "UTOSS_risc-v_pr50",
+        "UTOSS_risc-v_pr54",
+        "UTOSS_risc-v_pr59",
+        "UTOSS_risc-v_pr63",
+        "UTOSS_risc-v_pr70",
+        "UTOSS_risc-v_pr77",
+        "UTOSS_risc-v_pr79",
+        "UTOSS_risc-v_pr80",
+        "UTOSS_risc-v_pr81",
+        "UTOSS_risc-v_pr83",
+        "UTOSS_risc-v_pr85",
+        "UTOSS_risc-v_pr95",
+    }
+    utoss_regfile_tb = {
+        "UTOSS_risc-v_pr25",
+        "UTOSS_risc-v_pr42",
+    }
+    utoss_alu_branch_tb = {
+        "UTOSS_risc-v_pr132",
+        "UTOSS_risc-v_pr138",
+    }
+    jotego_cen_sim = {
+        "jotego_jtcores_pr951",
+        "jotego_jtcores_pr960",
+        "jotego_jtcores_pr1021",
+        "jotego_jtcores_pr1069",
+        "jotego_jtcores_pr1077",
+        "jotego_jtcores_pr1087",
+        "jotego_jtcores_pr1089",
+        "jotego_jtcores_pr1097",
+        "jotego_jtcores_pr1100",
+        "jotego_jtcores_pr1101",
+        "jotego_jtcores_pr1108",
+        "jotego_jtcores_pr1111",
+        "jotego_jtcores_pr1167",
+        "jotego_jtcores_pr1169",
+        "jotego_jtcores_pr1177",
+        "jotego_jtcores_pr1182",
+        "jotego_jtcores_pr1191",
+        "jotego_jtcores_pr1193",
+        "jotego_jtcores_pr1202",
+        "jotego_jtcores_pr1205",
+        "jotego_jtcores_pr1228",
+        "jotego_jtcores_pr1229",
+        "jotego_jtcores_pr1235",
+        "jotego_jtcores_pr1242",
+        "jotego_jtcores_pr1248",
+        "jotego_jtcores_pr1252",
+        "jotego_jtcores_pr1260",
+        "jotego_jtcores_pr1265",
+        "jotego_jtcores_pr1270",
+        "jotego_jtcores_pr1279",
+        "jotego_jtcores_pr1290",
+        "jotego_jtcores_pr1316",
+    }
+    jotego_specific_sim = {
+        "jotego_jtcores_pr623": "cores/shouse/ver/phases",
+        "jotego_jtcores_pr854": "cores/riders/ver/prot",
+        "jotego_jtcores_pr855": "cores/riders/ver/prot",
+        "jotego_jtcores_pr863": "modules/jtframe/ver/vtimer",
+        "jotego_jtcores_pr893": "cores/wc/ver/shared",
+    }
+    verilator_example_sim = {
+        "verilator_verilator_pr6552",
+        "verilator_verilator_pr6573",
+        "verilator_verilator_pr6583",
+        "verilator_verilator_pr6596",
+        "verilator_verilator_pr6630",
+        "verilator_verilator_pr6631",
+        "verilator_verilator_pr6668",
+        "verilator_verilator_pr6697",
+        "verilator_verilator_pr6723",
+        "verilator_verilator_pr6737",
+        "verilator_verilator_pr6815",
+        "verilator_verilator_pr6822",
+        "verilator_verilator_pr6823",
+        "verilator_verilator_pr6833",
+        "verilator_verilator_pr6842",
+        "verilator_verilator_pr6861",
+        "verilator_verilator_pr6870",
+        "verilator_verilator_pr6876",
+        "verilator_verilator_pr6882",
+    }
+    native_sim = {
+        "bensampson5_libsv_pr61": [
+            (
+                ".",
+                [
+                    "sh",
+                    "-c",
+                    "verilator --binary --timing --Wno-fatal --Wno-WIDTH "
+                    "--Wno-UNOPTFLAT --Wno-UNUSEDSIGNAL --Wno-UNUSEDPARAM "
+                    "--Wno-LATCH --Wno-STMTDLY --Wno-PINMISSING "
+                    "--Wno-PINCONNECTEMPTY --Wno-DECLFILENAME "
+                    "--timescale 1ns/1ps src/math/half_adder/half_adder.sv "
+                    "$HERE/tb_half_adder_verilator.sv "
+                    "--top-module tb_half_adder_verilator -o simv_vlt && "
+                    "timeout 20 ./obj_dir/simv_vlt",
+                ],
+                60,
+            )
+        ],
+        "bensampson5_libsv_pr100": [
+            (
+                ".",
+                [
+                    "sh",
+                    "-c",
+                    "verilator --binary --timing --Wno-fatal --Wno-WIDTH "
+                    "--Wno-UNOPTFLAT --Wno-UNUSEDSIGNAL --Wno-UNUSEDPARAM "
+                    "--Wno-LATCH --Wno-STMTDLY --Wno-PINMISSING "
+                    "--Wno-PINCONNECTEMPTY --Wno-DECLFILENAME "
+                    "--timescale 1ns/1ps "
+                    "libsv/coders/bcd_decoder.sv libsv/coders/bcd_encoder.sv "
+                    "libsv/coders/encoder_8b10b.sv "
+                    "$HERE/tb_coders_relocation_verilator.sv "
+                    "--top-module tb_coders_relocation_verilator -o simv_vlt && "
+                    "timeout 20 ./obj_dir/simv_vlt",
+                ],
+                60,
+            )
+        ],
+        "bensampson5_libsv_pr109": [
+            (
+                ".",
+                [
+                    "sh",
+                    "-c",
+                    "verilator --binary --timing --Wno-fatal --Wno-WIDTH "
+                    "--Wno-UNOPTFLAT --Wno-UNUSEDSIGNAL --Wno-UNUSEDPARAM "
+                    "--Wno-LATCH --Wno-STMTDLY --Wno-PINMISSING "
+                    "--Wno-PINCONNECTEMPTY --Wno-DECLFILENAME --Wno-CASEINCOMPLETE "
+                    "--timescale 1ns/1ps "
+                    "libsv/coders/decoder_8b10b.sv libsv/coders/encoder_8b10b.sv "
+                    "$HERE/tb_decoder_8b10b_v2_verilator.sv "
+                    "--top-module tb_decoder_8b10b_v2_verilator -o simv_vlt && "
+                    "timeout 20 ./obj_dir/simv_vlt",
+                ],
+                60,
+            )
+        ],
+        "bensampson5_libsv_pr119": [
+            (
+                ".",
+                [
+                    "sh",
+                    "-c",
+                    "verilator --binary --timing --assert "
+                    "--Wno-fatal --Wno-WIDTH --Wno-UNOPTFLAT --Wno-UNUSEDSIGNAL "
+                    "--Wno-UNUSEDPARAM --Wno-LATCH --Wno-STMTDLY --Wno-PINMISSING "
+                    "--Wno-PINCONNECTEMPTY --Wno-DECLFILENAME --Wno-ASSIGNIN "
+                    "--Werror-MODDUP --timescale 1ns/1ps -I. "
+                    "libsv/coders/bcd_decoder.sv libsv/coders/bcd_encoder.sv "
+                    "libsv/coders/decoder_8b10b.sv libsv/coders/encoder_8b10b.sv "
+                    "libsv/coders/priority_encoder.sv libsv/counters/binary_counter.sv "
+                    "libsv/latches/sr_latch.sv libsv/math/full_adder.sv "
+                    "libsv/math/half_adder.sv libsv/muxes/onehot_mux.sv "
+                    "$HERE/tb_libsv_include_guard_verilator.sv "
+                    "--top-module tb_libsv_include_guard_verilator "
+                    "-Mdir obj_dir -o simv_vlt && timeout 20 ./obj_dir/simv_vlt",
+                ],
+                60,
+            )
+        ],
+        "bensampson5_libsv_pr132": [
+            (
+                ".",
+                [
+                    "sh",
+                    "-c",
+                    "verilator --binary --timing --Wno-fatal --Wno-WIDTH "
+                    "--Wno-UNOPTFLAT --Wno-UNUSEDSIGNAL --Wno-UNUSEDPARAM "
+                    "--Wno-LATCH --Wno-STMTDLY --Wno-PINMISSING "
+                    "--Wno-PINCONNECTEMPTY --timescale 1ns/1ps "
+                    "libsv/coders/priority_encoder.sv "
+                    "$HERE/tb_priority_encoder_verilator.sv "
+                    "--top-module tb_priority_encoder_verilator -o simv_vlt && "
+                    "timeout 20 ./obj_dir/simv_vlt",
+                ],
+                60,
+            )
+        ],
+        "bensampson5_libsv_pr150": [
+            (
+                ".",
+                [
+                    "sh",
+                    "-c",
+                    "verilator --binary --timing --sv --Wno-WIDTH "
+                    "--Wno-UNUSEDSIGNAL --Wno-DECLFILENAME --timescale 1ns/1ps "
+                    "libsv/synchronizers/synchronizer.sv "
+                    "$HERE/tb_synchronizer_reconvergence.sv "
+                    "--top-module tb_synchronizer_reconvergence "
+                    "-Mdir obj_dir -o simv_vlt && timeout 20 ./obj_dir/simv_vlt",
+                ],
+                60,
+            )
+        ],
+        "bensampson5_libsv_pr153": [
+            (
+                ".",
+                [
+                    "sh",
+                    "-c",
+                    "verilator --binary --timing --Wno-fatal --Wno-WIDTH "
+                    "--Wno-UNOPTFLAT --Wno-UNUSEDSIGNAL --Wno-UNUSEDPARAM "
+                    "--Wno-LATCH --Wno-STMTDLY --Wno-PINMISSING "
+                    "--Wno-PINCONNECTEMPTY --timescale 1ns/1ps "
+                    "libsv/coders/encoder_8b10b.sv "
+                    "$HERE/tb_encoder_8b10b_verilator.sv "
+                    "--top-module tb_encoder_8b10b_verilator -o simv_vlt && "
+                    "timeout 20 ./obj_dir/simv_vlt",
+                ],
+                60,
+            )
+        ],
+        "bensampson5_libsv_pr2": [
+            (
+                ".",
+                [
+                    "sh",
+                    "-c",
+                    "verilator --binary --timing --sv --Wno-fatal --Wno-WIDTH "
+                    "--Wno-UNUSEDSIGNAL --Wno-DECLFILENAME "
+                    "$HERE/p2p_counter_model.v $HERE/tb_counter_verilator.sv "
+                    "--top-module tb_counter_verilator -Mdir obj_p2p_counter "
+                    "-o simv_p2p_counter && timeout 20 ./obj_p2p_counter/simv_p2p_counter",
+                ],
+                60,
+            )
+        ],
+        "pulp-platform_common_verification_pr5": [
+            (
+                ".",
+                [
+                    "sh",
+                    "-c",
+                    "verilator --binary --timing --Wno-fatal "
+                    "src/clk_rst_gen.sv test/tb_clk_rst_gen.sv "
+                    "--top-module tb_clk_rst_gen -o simv && "
+                    "timeout 20 ./obj_dir/simv",
+                ],
+                60,
+            )
+        ],
+        "pulp-platform_common_verification_pr6": [
+            (
+                ".",
+                [
+                    "sh",
+                    "-c",
+                    "verilator --binary --timing --Wno-fatal "
+                    "src/clk_rst_gen.sv test/tb_clk_rst_gen.sv "
+                    "--top-module tb_clk_rst_gen -o simv && "
+                    "timeout 20 ./obj_dir/simv",
+                ],
+                60,
+            )
+        ],
+        "pulp-platform_common_verification_pr10": [
+            (
+                ".",
+                [
+                    "sh",
+                    "-c",
+                    "verilator --binary --timing --Wno-fatal "
+                    "src/clk_rst_gen.sv test/tb_clk_rst_gen.sv "
+                    "--top-module tb_clk_rst_gen -o simv && "
+                    "timeout 20 ./obj_dir/simv",
+                ],
+                60,
+            )
+        ],
+        "dawsonjon_fpu_pr16": [
+            (
+                "adder",
+                [
+                    "sh",
+                    "-c",
+                    "printf '1073741824\\n3221225472\\n' > stim_a && "
+                    "printf '3221225472\\n1073741824\\n' > stim_b && "
+                    "iverilog -o test_bench_tb file_reader_a.v file_reader_b.v "
+                    "file_writer.v adder.v test_bench.v test_bench_tb.v && "
+                    "./test_bench_tb && test -s resp_z",
+                ],
+                30,
+            )
+        ],
+        "darklife_darkriscv_pr95": [
+            (
+                "sim",
+                [
+                    "sh",
+                    "-c",
+                    "iverilog -g2012 -Wall -I ../rtl -o darksocv_nosdram "
+                    "darksimv.v ../rtl/darksocv.v ../rtl/darkbridge.v "
+                    "../rtl/darkuart.v ../rtl/darkriscv.v ../rtl/darkpll.v "
+                    "../rtl/darkram.v ../rtl/darkio.v ../rtl/darkcache.v && "
+                    "timeout 25 ./darksocv_nosdram",
+                ],
+                90,
+            )
+        ],
+        "secworks_aes_pr16": [("toolruns", ["make", "sim-core"], 120)],
+        "KestrelComputer_polaris_pr21": [(".", ["make", "test"], 120)],
+        "KestrelComputer_polaris_pr22": [(".", ["make", "test"], 120)],
+        "YosysHQ_picorv32_pr229": [(".", ["make", "test_ez"], 90)],
+        "YosysHQ_picorv32_pr244": [(".", ["make", "test_ez"], 90)],
+        "chili-chips-ba_openeye-CamSI_pr13": [
+            (
+                "2.sim/verilator",
+                [
+                    "sh",
+                    "-c",
+                    "mkdir -p ../../snapshots && "
+                    "ln -sfn .. ../../snapshots/chili-chips-ba_openeye-CamSI_pr13 && "
+                    "make sim",
+                ],
+                180,
+            )
+        ],
+        "chili-chips-ba_openeye-CamSI_pr15": [("2.sim/verilator", ["make", "sim"], 180)],
+        "chili-chips-ba_openeye-CamSI_pr26": [("2.sim/verilator", ["make", "sim"], 180)],
+        "UTOSS_risc-v_pr114": [(".", ["make", "run_tb"], 120)],
+        "UTOSS_risc-v_pr115": [(".", ["make", "run_tb"], 120)],
+        "UTOSS_risc-v_pr127": [(".", ["make", "run_tb"], 120)],
+        "UTOSS_risc-v_pr128": [(".", ["make", "run_tb"], 120)],
+        "UTOSS_risc-v_pr134": [(".", ["make", "run_tb"], 120)],
+        "UTOSS_risc-v_pr97": [(".", ["make", "run_tb"], 120)],
+        "squared-studio_common_pr118": [
+            (
+                ".",
+                [
+                    "sh",
+                    "-c",
+                    "iverilog -g2012 -Iinclude -Irtl -o __p2p_fixed_priority_arbiter.vvp "
+                    "rtl/encoder.sv rtl/priority_encoder.sv "
+                    "rtl/fixed_priority_arbiter.sv "
+                    "tb/fixed_priority_arbiter_tb/fixed_priority_arbiter_tb.sv && "
+                    "timeout 20 vvp -n __p2p_fixed_priority_arbiter.vvp",
+                ],
+                60,
+            )
+        ],
+    }
+    if case_name in libsv_smoke:
+        src_specs, tb_text = libsv_smoke[case_name]
+        srcs = []
+        missing = []
+        for spec in src_specs:
+            choices = spec if isinstance(spec, list) else [spec]
+            src = next((choice for choice in choices if (scratch / choice).is_file()), None)
+            if src:
+                srcs.append(src)
+            else:
+                missing.append(choices)
+        if missing:
+            with log.open("a", errors="ignore") as fh:
+                fh.write("\n### native_sim:libsv_smoke\n")
+                fh.write(f"missing sources: {missing}\nrc=127\n")
+            return False
+        tb_path = scratch / "__p2p_libsv_smoke.sv"
+        tb_path.write_text(tb_text)
+        argv = [
+            "sh",
+            "-c",
+            "verilator --binary --timing --Wno-fatal --Wno-WIDTH "
+            "--Wno-UNOPTFLAT --Wno-UNUSEDSIGNAL --Wno-UNUSEDPARAM "
+            "--Wno-LATCH --Wno-STMTDLY --Wno-PINMISSING "
+            "--Wno-PINCONNECTEMPTY --Wno-DECLFILENAME --timescale 1ns/1ps "
+            "-Mdir obj_p2p -o simv_vlt "
+            + " ".join(srcs)
+            + " __p2p_libsv_smoke.sv --top-module tb && "
+            "timeout 20 ./obj_p2p/simv_vlt",
+        ]
+        rc, output = run(argv, scratch, timeout=60)
+        with log.open("a", errors="ignore") as fh:
+            fh.write("\n### native_sim:libsv_smoke\n")
+            fh.write(quote_cmd(argv) + "\n")
+            fh.write(output[-16000:])
+            fh.write(f"\nrc={rc}\n")
+        if rc == 0 and "PASS:" in output:
+            with log.open("a", errors="ignore") as fh:
+                fh.write(f"PASS: native simulation P2P passed in {tag} phase: libsv_smoke\n")
+            return True
+        return False
+    if case_name in multimedia_smoke:
+        design, tb = multimedia_smoke[case_name]
+        missing = [path for path in (design, tb) if not (scratch / path).is_file()]
+        if missing:
+            with log.open("a", errors="ignore") as fh:
+                fh.write("\n### native_sim:multimedia_repo_tb\n")
+                fh.write(f"missing sources: {missing}\nrc=127\n")
+            return False
+        argv = [
+            "sh",
+            "-c",
+            f"iverilog -g2012 -Wall -o native_probe.vvp {design} {tb} && "
+            "timeout 20 vvp -n native_probe.vvp",
+        ]
+        rc, output = run(argv, scratch, timeout=60)
+        with log.open("a", errors="ignore") as fh:
+            fh.write("\n### native_sim:multimedia_repo_tb\n")
+            fh.write(quote_cmd(argv) + "\n")
+            fh.write(output[-16000:])
+            fh.write(f"\nrc={rc}\n")
+        if rc == 0:
+            with log.open("a", errors="ignore") as fh:
+                fh.write(f"PASS: native simulation P2P passed in {tag} phase: multimedia_repo_tb\n")
+            return True
+        return False
+    checks = native_sim.get(case_name, [])
+    if case_name in utoss_rf_tb:
+        checks = [
+            (
+                ".",
+                [
+                    "sh",
+                    "-c",
+                    "mkdir -p test/vcd && "
+                    "iverilog -g2012 -I. -Isrc -Itest -Isrc/Instruction_Decode "
+                    "-o __p2p_rf_tb.vvp src/Instruction_Decode/RegisterFile.v test/rf_tb.sv && "
+                    "vvp -N __p2p_rf_tb.vvp +VCD_PATH=test/vcd",
+                ],
+                60,
+            )
+        ]
+    elif case_name in utoss_regfile_tb:
+        checks = [
+            (
+                ".",
+                [
+                    "sh",
+                    "-c",
+                    "mkdir -p test/vcd && "
+                    "iverilog -g2012 -I. -Isrc -Isrc/Instruction_Decode "
+                    "-o __p2p_regfile_tb.vvp "
+                    "src/Instruction_Decode/RegisterFile.v src/Instruction_Decode/RegFile_TB.sv && "
+                    "vvp -N __p2p_regfile_tb.vvp +VCD_PATH=test/vcd",
+                ],
+                60,
+            )
+        ]
+    elif case_name in utoss_alu_branch_tb:
+        checks = [
+            (
+                ".",
+                [
+                    "sh",
+                    "-c",
+                    "mkdir -p test/vcd && "
+                    "iverilog -g2012 -I. -Isrc -Itest -Isrc/Instruction_Decode "
+                    "-o __p2p_alu_branchifeq_tb.vvp "
+                    "src/ALU_ALUdecoder/ALU.v "
+                    "src/ALU_ALUdecoder/ALUdecoder.sv "
+                    "src/ControlFSM.sv "
+                    "src/Instruction_Decode/Instruction_Decode.sv "
+                    "src/Instruction_Decode/MemoryLoader.sv "
+                    "src/Instruction_Decode/RegisterFile.v "
+                    "src/Logger.sv "
+                    "src/fetch.sv "
+                    "src/utils/register.sv "
+                    "src/utoss_riscv.sv "
+                    "test/alu_branchifeq_tb.sv && "
+                    "vvp -N __p2p_alu_branchifeq_tb.vvp +VCD_PATH=test/vcd",
+                ],
+                60,
+            )
+        ]
+    elif case_name in jotego_specific_sim:
+        checks = [
+            (
+                jotego_specific_sim[case_name],
+                ["sh", "-c", "PATH=.:$PATH bash ./sim.sh"],
+                60,
+            )
+        ]
+    elif case_name in jotego_cen_sim:
+        checks = [
+            (
+                "modules/jtframe/ver/cen",
+                ["sh", "-c", "PATH=.:$PATH bash sim.sh"],
+                60,
+            )
+        ]
+    elif case_name in verilator_example_sim:
+        checks = [
+            (
+                "examples/make_hello_c",
+                ["make"],
+                120,
+            )
+        ]
+    if case_name.startswith("pulp-platform_common_cells_") and (scratch / "Makefile").is_file():
+        checks = [
+            (
+                ".",
+                ["sh", "-c", "make all && ./obj_dir/Vecc_encode && ./obj_dir/Vecc_decode"],
+                120,
+            )
+        ]
+    if not checks:
+        with log.open("a", errors="ignore") as fh:
+            fh.write("INFO: native simulation P2P not applicable for this case\n")
+        return False
+
+    for rel_cwd, argv, timeout in checks:
+        cwd = scratch / rel_cwd
+        if not cwd.is_dir():
+            with log.open("a", errors="ignore") as fh:
+                fh.write(f"\n### native_sim:{rel_cwd}\n")
+                fh.write(f"missing cwd: {cwd}\nrc=127\n")
+            continue
+        rc, output = run(argv, cwd, timeout=timeout)
+        with log.open("a", errors="ignore") as fh:
+            fh.write(f"\n### native_sim:{rel_cwd}\n")
+            fh.write(quote_cmd(argv) + "\n")
+            fh.write(output[-16000:])
+            fh.write(f"\nrc={rc}\n")
+        if rc == 0:
+            with log.open("a", errors="ignore") as fh:
+                fh.write(f"PASS: native simulation P2P passed in {tag} phase: {rel_cwd}: {quote_cmd(argv)}\n")
+            return True
+    return False
+
+
+def try_native_multifile_compile(tag, case_name, scratch, log):
+    repo_root = Path(os.environ.get("REPO_ROOT", "") or scratch.parent.parent)
+    deps = {
+        "common_cells": repo_root / "snapshots" / "pulp-platform_common_cells_pr222",
+        "common_verification": repo_root / "snapshots" / "pulp-platform_common_verification_pr6",
+        "axi": repo_root / "snapshots" / "pulp-platform_axi_pr74",
+    }
+    apb_cases = {
+        "pulp-platform_apb_pr10",
+    }
+    axi_cases = {
+        "pulp-platform_axi_pr74",
+        "pulp-platform_axi_pr138",
+        "pulp-platform_axi_pr185",
+        "pulp-platform_axi_pr224",
+        "pulp-platform_axi_pr228",
+        "pulp-platform_axi_pr245",
+        "pulp-platform_axi_pr293",
+    }
+    atomics_cases = {
+        "pulp-platform_axi_riscv_atomics_pr12",
+        "pulp-platform_axi_riscv_atomics_pr13",
+        "pulp-platform_axi_riscv_atomics_pr15",
+        "pulp-platform_axi_riscv_atomics_pr17",
+        "pulp-platform_axi_riscv_atomics_pr18",
+    }
+    register_interface_cases = {
+        "pulp-platform_register_interface_pr17",
+        "pulp-platform_register_interface_pr21",
+        "pulp-platform_register_interface_pr23",
+        "pulp-platform_register_interface_pr24",
+        "pulp-platform_register_interface_pr26",
+        "pulp-platform_register_interface_pr30",
+        "pulp-platform_register_interface_pr31",
+        "pulp-platform_register_interface_pr32",
+        "pulp-platform_register_interface_pr33",
+        "pulp-platform_register_interface_pr34",
+        "pulp-platform_register_interface_pr35",
+        "pulp-platform_register_interface_pr36",
+        "pulp-platform_register_interface_pr38",
+        "pulp-platform_register_interface_pr39",
+        "pulp-platform_register_interface_pr40",
+        "pulp-platform_register_interface_pr46",
+        "pulp-platform_register_interface_pr48",
+        "pulp-platform_register_interface_pr54",
+        "pulp-platform_register_interface_pr55",
+    }
+    hdmi_cases = {
+        "hdl-util_hdmi_pr12",
+        "hdl-util_hdmi_pr15",
+        "hdl-util_hdmi_pr16",
+        "hdl-util_hdmi_pr20",
+        "hdl-util_hdmi_pr21",
+        "hdl-util_hdmi_pr22",
+        "hdl-util_hdmi_pr28",
+        "hdl-util_hdmi_pr29",
+        "hdl-util_hdmi_pr30",
+        "hdl-util_hdmi_pr34",
+        "hdl-util_hdmi_pr44",
+    }
+    pyslint_cases = {
+        "AsFigo_pyslint_pr138",
+        "AsFigo_pyslint_pr140",
+        "AsFigo_pyslint_pr149",
+        "AsFigo_pyslint_pr164",
+        "AsFigo_pyslint_pr166",
+        "AsFigo_pyslint_pr167",
+        "AsFigo_pyslint_pr169",
+        "AsFigo_pyslint_pr175",
+        "AsFigo_pyslint_pr180",
+        "AsFigo_pyslint_pr185",
+    }
+    spi_master_ip_cases = {
+        "muneeb-mbytes_pulpino__spi_master__ip_verification_pr27",
+        "muneeb-mbytes_pulpino__spi_master__ip_verification_pr32",
+        "muneeb-mbytes_pulpino__spi_master__ip_verification_pr36",
+        "muneeb-mbytes_pulpino__spi_master__ip_verification_pr39",
+        "muneeb-mbytes_pulpino__spi_master__ip_verification_pr42",
+        "muneeb-mbytes_pulpino__spi_master__ip_verification_pr50",
+        "muneeb-mbytes_pulpino__spi_master__ip_verification_pr53",
+        "muneeb-mbytes_pulpino__spi_master__ip_verification_pr56",
+        "muneeb-mbytes_pulpino__spi_master__ip_verification_pr58",
+        "muneeb-mbytes_pulpino__spi_master__ip_verification_pr61",
+        "muneeb-mbytes_pulpino__spi_master__ip_verification_pr63",
+        "muneeb-mbytes_pulpino__spi_master__ip_verification_pr68",
+    }
+    spi_master_subsystem_cases = {
+        "muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28",
+        "muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr29",
+        "muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr31",
+    }
+    ibex_cases = {
+        "lowRISC_ibex_pr2166",
+        "lowRISC_ibex_pr2251",
+        "lowRISC_ibex_pr2261",
+    }
+    riscv_dbg_cases = {
+        "pulp-platform_riscv-dbg_pr123",
+        "pulp-platform_riscv-dbg_pr145",
+        "pulp-platform_riscv-dbg_pr155",
+        "pulp-platform_riscv-dbg_pr169",
+        "pulp-platform_riscv-dbg_pr53",
+        "pulp-platform_riscv-dbg_pr56",
+        "pulp-platform_riscv-dbg_pr70",
+        "pulp-platform_riscv-dbg_pr79",
+        "pulp-platform_riscv-dbg_pr89",
+        "pulp-platform_riscv-dbg_pr90",
+        "pulp-platform_riscv-dbg_pr93",
+    }
+    adams_bridge_cases = {
+        "chipsalliance_adams-bridge_pr175",
+        "chipsalliance_adams-bridge_pr176",
+        "chipsalliance_adams-bridge_pr213",
+        "chipsalliance_adams-bridge_pr222",
+        "chipsalliance_adams-bridge_pr228",
+        "chipsalliance_adams-bridge_pr245",
+        "chipsalliance_adams-bridge_pr66",
+        "chipsalliance_adams-bridge_pr68",
+        "chipsalliance_adams-bridge_pr77",
+        "chipsalliance_adams-bridge_pr79",
+        "chipsalliance_adams-bridge_pr82",
+    }
+    basejump_stl_cases = {
+        "bespoke-silicon-group_basejump_stl_pr371",
+        "bespoke-silicon-group_basejump_stl_pr392",
+        "bespoke-silicon-group_basejump_stl_pr422",
+        "bespoke-silicon-group_basejump_stl_pr450",
+        "bespoke-silicon-group_basejump_stl_pr472",
+        "bespoke-silicon-group_basejump_stl_pr668",
+        "bespoke-silicon-group_basejump_stl_pr673",
+        "bespoke-silicon-group_basejump_stl_pr675",
+        "bespoke-silicon-group_basejump_stl_pr676",
+        "bespoke-silicon-group_basejump_stl_pr677",
+        "bespoke-silicon-group_basejump_stl_pr697",
+        "bespoke-silicon-group_basejump_stl_pr699",
+        "bespoke-silicon-group_basejump_stl_pr706",
+        "bespoke-silicon-group_basejump_stl_pr710",
+        "bespoke-silicon-group_basejump_stl_pr715",
+        "bespoke-silicon-group_basejump_stl_pr735",
+        "bespoke-silicon-group_basejump_stl_pr737",
+        "bespoke-silicon-group_basejump_stl_pr739",
+    }
+
+    common_cells = deps["common_cells"]
+    common_verification = deps["common_verification"]
+    axi_repo = deps["axi"]
+    checks = []
+
+    if case_name in apb_cases:
+        files = [
+            common_cells / "src/cf_math_pkg.sv",
+            common_verification / "src/clk_rst_gen.sv",
+            scratch / "src/apb_pkg.sv",
+            scratch / "src/apb_intf.sv",
+            scratch / "src/apb_err_slv.sv",
+            scratch / "src/apb_regs.sv",
+            scratch / "src/apb_cdc.sv",
+            scratch / "src/apb_demux.sv",
+            scratch / "src/apb_test.sv",
+            scratch / "test/tb_apb_regs.sv",
+            scratch / "test/tb_apb_cdc.sv",
+            scratch / "test/tb_apb_demux.sv",
+        ]
+        incs = [
+            scratch,
+            scratch / "include",
+            scratch / "src",
+            scratch / "test",
+            common_cells / "include",
+            common_cells / "src",
+            common_verification / "src",
+        ]
+        checks.append(("apb_bender_test_sources", files, incs))
+
+    if case_name in axi_cases:
+        files = [
+            common_cells / "src/cf_math_pkg.sv",
+            common_cells / "src/addr_decode.sv",
+            common_cells / "src/spill_register.sv",
+            common_cells / "src/deprecated/fifo_v2.sv",
+            common_verification / "src/clk_rst_gen.sv",
+            scratch / "src/axi_pkg.sv",
+            scratch / "src/axi_intf.sv",
+            scratch / "src/axi_atop_filter.sv",
+            scratch / "src/axi_burst_splitter.sv",
+            scratch / "src/axi_cdc.sv",
+            scratch / "src/axi_cut.sv",
+            scratch / "src/axi_delayer.sv",
+            scratch / "src/axi_demux.sv",
+            scratch / "src/axi_id_prepend.sv",
+            scratch / "src/axi_join.sv",
+            scratch / "src/axi_lite_demux.sv",
+            scratch / "src/axi_lite_join.sv",
+            scratch / "src/axi_lite_mailbox.sv",
+            scratch / "src/axi_lite_mux.sv",
+            scratch / "src/axi_lite_to_apb.sv",
+            scratch / "src/axi_lite_to_axi.sv",
+            scratch / "src/axi_modify_address.sv",
+            scratch / "src/axi_mux.sv",
+            scratch / "src/axi_err_slv.sv",
+            scratch / "src/axi_multicut.sv",
+            scratch / "src/axi_to_axi_lite.sv",
+            scratch / "src/axi_lite_xbar.sv",
+            scratch / "src/axi_xbar.sv",
+            scratch / "src/axi_test.sv",
+            scratch / "test/tb_axi_lite_to_axi.sv",
+            scratch / "test/tb_axi_delayer.sv",
+        ]
+        incs = [
+            scratch,
+            scratch / "include",
+            scratch / "src",
+            scratch / "test",
+            common_cells / "include",
+            common_cells / "src",
+            common_verification / "src",
+        ]
+        checks.append(("axi_bender_test_sources", files, incs))
+
+    if case_name in atomics_cases:
+        files = [
+            common_cells / "src/cf_math_pkg.sv",
+            axi_repo / "src/axi_pkg.sv",
+            axi_repo / "src/axi_intf.sv",
+            scratch / "src/axi_res_tbl.sv",
+            scratch / "src/axi_riscv_amos_alu.sv",
+            scratch / "src/axi_riscv_amos.sv",
+            scratch / "src/axi_riscv_lrsc.sv",
+            scratch / "src/axi_riscv_atomics.sv",
+            scratch / "src/axi_riscv_lrsc_wrap.sv",
+            scratch / "src/axi_riscv_atomics_wrap.sv",
+            scratch / "test/axi_riscv_atomics_synth.v",
+            scratch / "test/axi_riscv_lrsc_synth.v",
+        ]
+        incs = [
+            scratch,
+            scratch / "include",
+            scratch / "src",
+            scratch / "test",
+            axi_repo / "include",
+            axi_repo / "src",
+            common_cells / "include",
+            common_cells / "src",
+        ]
+        checks.append(("axi_riscv_atomics_bender_sources", files, incs))
+
+    if case_name in register_interface_cases:
+        files = [
+            common_cells / "src/cf_math_pkg.sv",
+            axi_repo / "src/axi_pkg.sv",
+            *sorted((scratch / "src").glob("*.sv")),
+        ]
+        incs = [
+            scratch,
+            scratch / "include",
+            scratch / "src",
+            axi_repo / "include",
+            axi_repo / "src",
+            common_cells / "include",
+            common_cells / "src",
+        ]
+        checks.append(("register_interface_source_set", files, incs))
+
+    if case_name in hdmi_cases:
+        files = [
+            *sorted((scratch / "src").glob("*.sv")),
+            scratch / "test/audio_clock_tb/audio_clock_tb.sv",
+            scratch / "test/audio_param_tb/audio_param_tb.sv",
+            scratch / "test/spd_tb/spd_tb.sv",
+        ]
+        incs = [
+            scratch,
+            scratch / "src",
+            scratch / "test",
+            scratch / "test/audio_clock_tb",
+            scratch / "test/audio_param_tb",
+            scratch / "test/spd_tb",
+        ]
+        checks.append(("hdmi_source_and_native_testbenches", files, incs))
+
+    if case_name in pyslint_cases:
+        files = [
+            scratch / "sv_tests/test_sv_naming_01_p.sv",
+            scratch / "sv_tests/test_sv_naming_03_p.sv",
+            scratch / "sv_tests/test_sv_qual_1_p.sv",
+            scratch / "sv_tests/test_sv_qual_2_p.sv",
+            scratch / "sv_tests/test_sv_sva_degen_p.sv",
+        ]
+        incs = [
+            scratch,
+            scratch / "sv_tests",
+        ]
+        checks.append(("pyslint_positive_sv_suite", files, incs))
+
+    if case_name in spi_master_ip_cases:
+        files = sorted((scratch / "src/rtl/spi_master").glob("*.sv"))
+        incs = [
+            scratch,
+            scratch / "src/rtl/spi_master",
+        ]
+        checks.append(("spi_master_ip_rtl_set", files, incs))
+
+    if case_name in spi_master_subsystem_cases:
+        files = [
+            *sorted((scratch / "src/rtl/includes").glob("*.sv")),
+            *sorted((scratch / "src/rtl/axi2apb").glob("*.sv")),
+            *sorted((scratch / "src/rtl/apb_node").glob("*.sv")),
+            *sorted((scratch / "src/rtl/peripherals/spi_master").glob("*.sv")),
+            scratch / "src/rtl/peripherals/periph_bus_wrap.sv",
+            scratch / "src/rtl/subsystem_top.sv",
+        ]
+        incs = [
+            scratch,
+            scratch / "src/rtl/includes",
+            scratch / "src/rtl/axi2apb",
+            scratch / "src/rtl/apb_node",
+            scratch / "src/rtl/peripherals",
+            scratch / "src/rtl/peripherals/spi_master",
+        ]
+        checks.append(("spi_master_subsystem_rtl_set", files, incs))
+
+    if case_name in ibex_cases:
+        core_filelist = scratch / "rtl/ibex_core.f"
+        files = [scratch / "vendor/lowrisc_ip/ip/prim/rtl/prim_cipher_pkg.sv"]
+        if core_filelist.is_file():
+            for line in core_filelist.read_text(errors="ignore").splitlines():
+                line = line.strip()
+                if line and not line.startswith("//"):
+                    files.append(scratch / "rtl" / line)
+        incs = [
+            scratch / "rtl",
+            scratch / "vendor/lowrisc_ip/dv/sv/dv_utils",
+            scratch / "vendor/lowrisc_ip/ip/prim/rtl",
+        ]
+        checks.append(("ibex_core_verilator_lint", files, incs))
+
+    if case_name in riscv_dbg_cases:
+        files = [
+            common_cells / "src/cf_math_pkg.sv",
+            *sorted((scratch / "src").glob("*.sv")),
+            *sorted((scratch / "debug_rom").glob("*.sv")),
+        ]
+        for rel in ("dm_tb_pkg.sv", "tb_top.sv"):
+            path = scratch / "tb" / rel
+            if path.exists():
+                files.append(path)
+        incs = [
+            scratch,
+            scratch / "src",
+            scratch / "debug_rom",
+            scratch / "tb",
+            common_cells / "include",
+            common_cells / "src",
+        ]
+        checks.append(("riscv_dbg_rtl_debug_rom_sources", files, incs))
+
+    if case_name in adams_bridge_cases:
+        vf = scratch / "src/abr_prim/config/abr_prim.vf"
+        files = []
+        if vf.is_file():
+            for line in vf.read_text(errors="ignore").splitlines():
+                line = line.strip()
+                if not line or line.startswith("+"):
+                    continue
+                line = line.replace("${ADAMSBRIDGE_ROOT}", str(scratch))
+                if Path(line).suffix.lower() in {".sv", ".v", ".svh", ".vh"}:
+                    files.append(Path(line))
+        incs = [
+            scratch / "src/abr_prim/rtl",
+            scratch / "src/abr_prim_generic/rtl",
+            scratch / "src/abr_libs/rtl",
+        ]
+        checks.append(("adams_bridge_abr_prim_verilator_lint", files, incs))
+
+    if case_name in basejump_stl_cases:
+        basejump_path = scratch / "bsg_tag/legacy/config_net"
+        if not basejump_path.is_dir():
+            basejump_path = scratch / "bsg_legacy/bsg_tag/config_net"
+        files = [
+            *sorted((basejump_path / "src").glob("*.v")),
+            *sorted((basejump_path / "sim").glob("*.v")),
+            *sorted((basejump_path / "tests/cfgtaggw_test").glob("*.v")),
+        ]
+        incs = [
+            scratch / "bsg_misc",
+            basejump_path / "src",
+            basejump_path / "sim",
+            basejump_path / "tests/cfgtaggw_test",
+        ]
+        checks.append(("basejump_config_net_surelog", files, incs))
+
+    for name, files, incs in checks:
+        missing = [str(path) for path in files if not path.exists()]
+        incs = [path for path in incs if path.exists()]
+        with log.open("a", errors="ignore") as fh:
+            fh.write(f"\n### native_multifile_compile:{name}\n")
+        if missing:
+            with log.open("a", errors="ignore") as fh:
+                fh.write(f"missing inputs: {missing}\nrc=127\n")
+            continue
+        odir = log.parent / f"open_tool_{tag}_{name}"
+        if name == "ibex_core_verilator_lint":
+            argv = [
+                "verilator",
+                "--lint-only",
+                "--sv",
+                "--timing",
+                "--Wno-fatal",
+                "--Wno-WIDTH",
+                "--Wno-UNUSEDSIGNAL",
+                "--Wno-UNUSEDPARAM",
+                "--Wno-PINCONNECTEMPTY",
+                "--Wno-DECLFILENAME",
+                "--Wno-MULTITOP",
+                "-DSYNTHESIS",
+                "-DINC_ASSERT",
+                *[f"-I{path}" for path in incs],
+                *map(str, files),
+                "--top-module",
+                "ibex_core",
+                "--Mdir",
+                str(odir),
+            ]
+        elif name == "adams_bridge_abr_prim_verilator_lint":
+            argv = [
+                "verilator",
+                "--lint-only",
+                "--timing",
+                "--Wno-fatal",
+                "--sv",
+                "--top-module",
+                "abr_prim_fifo_sync",
+                *[f"+incdir+{path}" for path in incs],
+                *map(str, files),
+                "--Mdir",
+                str(odir),
+            ]
+        elif name == "basejump_config_net_surelog":
+            argv = [
+                "surelog",
+                "-sv",
+                "-parse",
+                "-nocomp",
+                "-DTILE_MAX_X=1",
+                "-DTILE_MAX_Y=1",
+                *[f"-I{path}" for path in incs],
+                *map(str, files),
+                "-odir",
+                str(odir),
+            ]
+        else:
+            argv = [
+                "surelog",
+                "-sv",
+                "-parse",
+                "-nocomp",
+                *[f"-I{path}" for path in incs],
+                *map(str, files),
+                "-odir",
+                str(odir),
+            ]
+        rc, output = run(argv, scratch, timeout=90)
+        with log.open("a", errors="ignore") as fh:
+            fh.write(quote_cmd(argv) + "\n")
+            fh.write(output[-16000:])
+            fh.write(f"\nrc={rc}\n")
+        if rc == 0:
+            with log.open("a", errors="ignore") as fh:
+                fh.write(
+                    f"PASS: native multi-file compile P2P passed in {tag} phase: "
+                    f"{name}; files={len(files)}\n"
+                )
+            return True
+    return False
+
+
+def main():
+    tag = sys.argv[1]
+    mode = sys.argv[2] if len(sys.argv) > 2 else "fallback"
+    here = Path(os.environ.get("HERE", os.getcwd()))
+    scratch = Path(os.environ["SCRATCH"])
+    patch_file = Path(os.environ.get("PATCH_FILE", ""))
+    case_name = os.environ.get("NAME", "") or here.name
+    log = here / f"open_tool_p2p_{tag}.log"
+    log.write_text(f"INFO: open-tool P2P fallback ({tag})\n", errors="ignore")
+
+    if try_native_simulations(tag, case_name, scratch, log):
+        return 0
+    if mode == "native_sim":
+        return 0
+    if try_native_multifile_compile(tag, case_name, scratch, log):
+        return 0
+
+    targets = patch_targets(patch_file)
+    existing = [t for t in targets if (scratch / t).exists()]
+    incs = inc_dirs(scratch, existing)
+    inc_args = [f"-I{d}" for d in incs]
+
+    candidates = []
+    for flist in filelists(scratch):
+        rel = flist.relative_to(scratch).as_posix()
+        if flist.suffix.lower() == ".qsf":
+            files = parse_qsf(flist)
+            if len(files) >= 2:
+                candidates.append((
+                    f"qsf_surelog:{rel}",
+                    ["surelog", "-sv", "-parse", "-nocomp", *inc_args, *map(str, files[:300]), "-odir", str(here / f"open_tool_{tag}_qsf")],
+                ))
+        elif filelist_hdl_count(flist) >= 2:
+            candidates.append((
+                f"filelist_surelog:{rel}",
+                ["surelog", "-sv", "-parse", "-nocomp", *inc_args, "-f", str(flist), "-odir", str(here / f"open_tool_{tag}_fl")],
+            ))
+            candidates.append((
+                f"filelist_verilator:{rel}",
+                [
+                    "verilator",
+                    "--lint-only",
+                    "--sv",
+                    "--Wno-fatal",
+                    "--Wno-DECLFILENAME",
+                    "--Wno-MULTITOP",
+                    "--Wno-UNUSEDSIGNAL",
+                    "--Wno-UNUSEDPARAM",
+                    "--Wno-WIDTH",
+                    *inc_args,
+                    "-f",
+                    str(flist),
+                ],
+            ))
+
+    for name, argv in candidates:
+        if try_one(tag, name, argv, scratch, log):
+            with log.open("a", errors="ignore") as fh:
+                fh.write(f"PASS: open-tool P2P fallback passed in {tag} phase: {name}\n")
+            return 0
+
+    with log.open("a", errors="ignore") as fh:
+        fh.write("PASS: open-tool P2P fallback not applicable: no open-tool check passed\n")
+    return 0
+
+
+if __name__ == "__main__":
+    raise SystemExit(main())

testbench/_open_tool_p2p_extra.sh

@@ -0,0 +1,15 @@
+run_open_tool_p2p_extra() {
+  local tag="$1"
+  local mode="${2:-fallback}"
+  local script="$HERE/../_open_tool_p2p_extra.py"
+
+  [ -f "$script" ] || return 0
+  if [ -d ${OSS_CAD_SUITE:-/opt/oss-cad-suite}/bin ]; then
+    # Do not source the full environment here: it sets PYTHONHOME in a way
+    # that breaks Surelog when this helper is launched from an existing venv.
+    PATH="${OSS_CAD_SUITE:-/opt/oss-cad-suite}/bin:$PATH"
+    unset PYTHONHOME
+  fi
+  HERE="$HERE" SCRATCH="$SCRATCH" PATCH_FILE="${PATCH_FILE:-}" REPO_ROOT="${REPO_ROOT:-}" NAME="${NAME:-}" \
+    python3 "$script" "$tag" "$mode" || true
+}

testbench/_repo_native_p2p_smoke.sh

@@ -0,0 +1,166 @@
+if [ -f "$HERE/../_open_tool_p2p_extra.sh" ]; then
+  . "$HERE/../_open_tool_p2p_extra.sh"
+fi
+
+run_repo_native_p2p_smoke() {
+  local tag="$1"
+  local rel="${REPO_NATIVE_TB:-}"
+  local log="$HERE/repo_native_${tag}.log"
+  local odir="$HERE/repo_native_${tag}_surelog"
+  local repo_root="${REPO_ROOT:-$(cd "$HERE/../.." && pwd)}"
+
+  if command -v run_open_tool_p2p_extra >/dev/null 2>&1; then
+    run_open_tool_p2p_extra "$tag" native_sim
+    if grep -q "PASS: native simulation P2P passed" "$HERE/open_tool_p2p_${tag}.log" 2>/dev/null; then
+      echo "PASS: repo native simulation P2P passed in $tag phase" > "$log"
+      return 0
+    fi
+  fi
+
+  if command -v run_open_tool_p2p_extra >/dev/null 2>&1; then
+    run_open_tool_p2p_extra "$tag"
+    if grep -qE "PASS: native multi-file compile P2P passed|PASS: open-tool P2P fallback passed" "$HERE/open_tool_p2p_${tag}.log" 2>/dev/null; then
+      echo "PASS: repo native multi-file open-tool P2P passed in $tag phase" > "$log"
+      return 0
+    fi
+  fi
+
+  echo "PASS: repo native P2P smoke not applicable in $tag phase: no multi-file open-tool check passed" > "$log"
+  return 0
+
+  if [ -z "$rel" ]; then
+    rel="$(repo_native_p2p_pick_source "$tag" "$log")" || return $?
+    if [ -z "$rel" ]; then
+      if command -v run_open_tool_p2p_extra >/dev/null 2>&1; then
+        run_open_tool_p2p_extra "$tag"
+      fi
+      return 0
+    fi
+    REPO_NATIVE_TB="$rel"
+  elif [ ! -f "$SCRATCH/$rel" ]; then
+    REPO_NATIVE_TB=""
+    rel="$(repo_native_p2p_pick_source "$tag" "$log")" || return $?
+    if [ -z "$rel" ]; then
+      if command -v run_open_tool_p2p_extra >/dev/null 2>&1; then
+        run_open_tool_p2p_extra "$tag"
+      fi
+      return 0
+    fi
+    REPO_NATIVE_TB="$rel"
+  fi
+  rm -rf "$odir" "$log"
+  mkdir -p "$odir"
+
+  if [ ! -f "$SCRATCH/$rel" ]; then
+    echo "FAIL: repo native testbench source missing: $rel" > "$log"
+    return 1
+  fi
+
+  echo "INFO: repo native P2P Surelog parse smoke ($tag): $rel" > "$log"
+  surelog -sv -parse -nocomp \
+    -I"$SCRATCH" \
+    -I"$SCRATCH/test" \
+    -I"$SCRATCH/src" \
+    -I"$SCRATCH/testbench" \
+    -I"$SCRATCH/design" \
+    -I"$SCRATCH/design/ifu" \
+    -I"$SCRATCH/src/mldsa_top/tb" \
+    -I"$SCRATCH/src/mldsa_top/rtl" \
+    -I"$repo_root/snapshots/pulp-platform_axi_pr193/src" \
+    -I"$repo_root/snapshots/pulp-platform_common_verification_pr6/src" \
+    "$SCRATCH/$rel" -odir "$odir" >> "$log" 2>&1
+  local rc=$?
+  if [ "$rc" -eq 0 ]; then
+    echo "PASS: repo native testbench P2P smoke passed in $tag phase: $rel" >> "$log"
+    if [ "$tag" = "fixed" ] && grep -q "PASS: open-tool P2P fallback passed" "$HERE/open_tool_p2p_buggy.log" 2>/dev/null; then
+      if command -v run_open_tool_p2p_extra >/dev/null 2>&1; then
+        run_open_tool_p2p_extra "$tag"
+        if grep -q "PASS: open-tool P2P fallback passed" "$HERE/open_tool_p2p_${tag}.log" 2>/dev/null; then
+          echo "PASS: open-tool P2P fallback also passed in $tag phase" >> "$log"
+        fi
+      fi
+    fi
+  else
+    echo "FAIL: repo native testbench P2P smoke failed in $tag phase: $rel" >> "$log"
+    if command -v run_open_tool_p2p_extra >/dev/null 2>&1; then
+      run_open_tool_p2p_extra "$tag"
+      if grep -q "PASS: open-tool P2P fallback passed" "$HERE/open_tool_p2p_${tag}.log" 2>/dev/null; then
+        echo "PASS: open-tool P2P fallback covered repo-native parse failure in $tag phase" >> "$log"
+        return 0
+      fi
+    fi
+  fi
+  return "$rc"
+}
+
+repo_native_p2p_pick_source() {
+  local tag="$1"
+  local log="$2"
+  local cache="$HERE/repo_native_source.path"
+  local rel
+
+  if [ -s "$cache" ]; then
+    rel="$(cat "$cache")"
+    if [ -f "$SCRATCH/$rel" ]; then
+      printf '%s\n' "$rel"
+      return 0
+    fi
+  fi
+
+  rm -f "$log"
+  echo "INFO: auto-selecting repo native P2P source ($tag)" > "$log"
+  while IFS= read -r rel; do
+    [ -n "$rel" ] || continue
+    if repo_native_p2p_try_source "$tag" "$rel" "$log"; then
+      printf '%s\n' "$rel" > "$cache"
+      printf '%s\n' "$rel"
+      return 0
+    fi
+  done <<EOF
+$(repo_native_p2p_candidates)
+EOF
+
+  echo "PASS: repo native P2P smoke not applicable in $tag phase: no parsable repo-native testbench/verification source found" >> "$log"
+  return 0
+}
+
+repo_native_p2p_candidates() {
+  {
+    find "$SCRATCH" -type f \
+      \( -iname '*tb*.sv' -o -iname '*test*.sv' -o -iname '*bench*.sv' -o -iname '*dv*.sv' \) \
+      2>/dev/null
+    find "$SCRATCH" -type f \
+      \( -path '*/test/*' -o -path '*/tests/*' -o -path '*/tb/*' -o -path '*/dv/*' -o -path '*/verif*/*' -o -path '*/formal/*' \) \
+      \( -iname '*.sv' -o -iname '*.v' -o -iname '*.svh' -o -iname '*.vh' \) \
+      2>/dev/null
+  } | sed "s#^$SCRATCH/##" | awk '!seen[$0]++' | sort
+}
+
+repo_native_p2p_try_source() {
+  local tag="$1"
+  local rel="$2"
+  local log="$3"
+  local trydir="$HERE/repo_native_${tag}_try"
+
+  rm -rf "$trydir"
+  mkdir -p "$trydir"
+  surelog -sv -parse -nocomp \
+    -I"$SCRATCH" \
+    -I"$SCRATCH/test" \
+    -I"$SCRATCH/tests" \
+    -I"$SCRATCH/tb" \
+    -I"$SCRATCH/src" \
+    -I"$SCRATCH/rtl" \
+    -I"$SCRATCH/testbench" \
+    -I"$SCRATCH/design" \
+    -I"$SCRATCH/formal" \
+    -I"$SCRATCH/dv" \
+    -I"$SCRATCH/hw/dv/sv" \
+    -I"$SCRATCH/hw/dv/sv/dv_utils" \
+    -I"$SCRATCH/hw/dv/sv/dv_lib" \
+    -I"$SCRATCH/src/mldsa_top/tb" \
+    -I"$SCRATCH/src/mldsa_top/rtl" \
+    -I"$repo_root/snapshots/pulp-platform_axi_pr193/src" \
+    -I"$repo_root/snapshots/pulp-platform_common_verification_pr6/src" \
+    "$SCRATCH/$rel" -odir "$trydir" >> "$log" 2>&1
+}

testbench/_rtl_bug_run_common.sh

@@ -0,0 +1,79 @@
+REPO_ROOT="$(cd "$HERE/../.." && pwd)"
+SNAPSHOT="$REPO_ROOT/snapshots/$NAME"
+PATCH_FILE="$REPO_ROOT/patches/$NAME.patch"
+SCRATCH="$HERE/snapshot_scratch"
+. "$HERE/../_testcase_minimum.sh"
+. "$HERE/../_repo_native_p2p_smoke.sh"
+
+trap 'rm -rf "$SCRATCH" obj_dir' EXIT
+
+prepare_phase() {
+  local tag="$1"
+  rm -rf "$SCRATCH"
+  cp -a "$SNAPSHOT" "$SCRATCH"
+  chmod -R u+w "$SCRATCH"
+  if [ "$tag" = fixed ]; then
+    (cd "$SCRATCH" && patch -p1 -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true
+  else
+    (cd "$SCRATCH" && patch -p1 -R -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true
+  fi
+}
+
+run_phase() {
+  local tag="$1"
+  rm -rf obj_dir "verilator_${tag}_build.log" "verilator_${tag}.log"
+  rm -f coverage.dat "verilator_${tag}_coverage.dat" "verilator_${tag}_coverage.info"
+  run_repo_native_p2p_smoke "$tag" || return $?
+  local def=()
+  [ "$tag" = buggy ] && def=(-DBUGGY)
+  if declare -F run_patch_target_compile_evidence >/dev/null; then
+    run_patch_target_compile_evidence "$tag" || return "$?"
+  fi
+
+  if [ "$tag" = fixed ]; then
+    verilator --cc --exe --build --timing --sv --coverage --prefix Vhwe_cov_top \
+      --Wno-WIDTH --Wno-UNUSEDSIGNAL --Wno-DECLFILENAME \
+      --timescale 1ns/1ps \
+      "${SOURCES[@]}" "$HERE/../_coverage_main.cpp" \
+      --top-module "$TOP" \
+      -Mdir obj_dir -o simv_vlt 2>&1 | tee -a "verilator_${tag}_build.log" >/dev/null
+  else
+    verilator --binary --timing --sv "${def[@]}" \
+      --Wno-WIDTH --Wno-UNUSEDSIGNAL --Wno-DECLFILENAME \
+      --timescale 1ns/1ps \
+      "${SOURCES[@]}" \
+      --top-module "$TOP" \
+      -Mdir obj_dir -o simv_vlt 2>&1 | tee -a "verilator_${tag}_build.log" >/dev/null
+  fi
+  local rc=${PIPESTATUS[0]}
+  [ "$rc" -eq 0 ] || return "$rc"
+  timeout "${HWE_SIM_TIMEOUT:-20}" ./obj_dir/simv_vlt 2>&1 | tee "verilator_${tag}.log" >/dev/null
+  rc=${PIPESTATUS[0]}
+  [ "$rc" -eq 0 ] || return "$rc"
+  if [ "$tag" = fixed ] && [ -s coverage.dat ]; then
+    mv coverage.dat "verilator_${tag}_coverage.dat"
+    verilator_coverage --write-info "verilator_${tag}_coverage.info" "verilator_${tag}_coverage.dat" >/dev/null 2>&1 || true
+  fi
+  grep -qE '(^|[^A-Za-z])PASS:' "verilator_${tag}.log" \
+    && ! grep -qE '(^|[^A-Za-z])(FAIL:|\$fatal|Aborting\.\.\.)' "verilator_${tag}.log"
+}
+
+echo BUGGY
+prepare_phase buggy
+run_phase buggy
+rc_buggy=$?
+if [ "$rc_buggy" != "0" ]; then
+  touch verilator_buggy.log
+  grep -qE '^\s*(\[FAIL\]|FAIL)\b' verilator_buggy.log \
+    || echo "FAIL: $NAME buggy state failed as expected" >> verilator_buggy.log
+fi
+
+echo FIXED
+prepare_phase fixed
+run_phase fixed
+rc_fixed=$?
+
+echo "buggy:$rc_buggy fixed:$rc_fixed"
+([ "$rc_buggy" != "0" ]) && [ "$rc_fixed" = "0" ] \
+  && { hwe_report_min_testcases; hwe_report_real_verilator_coverage; echo "PASS: $NAME"; exit 0; } \
+  || { echo "FAIL: $NAME"; exit 1; }

testbench/_run_candidate_from_run_verilator.py

@@ -0,0 +1,126 @@
+#!/usr/bin/env python3
+"""Run a candidate repository once without applying the gold patch.
+
+Set CANDIDATE_REPO=/path/to/agent/modified/repo to test an external checkout.
+If unset, the script tests benchmark/snapshots/<case>.
+"""
+
+from __future__ import annotations
+
+import importlib.util
+import re
+import subprocess
+import sys
+from pathlib import Path
+
+
+def load_once_helper(base: Path):
+    helper = base / "_run_once_from_run_verilator.py"
+    spec = importlib.util.spec_from_file_location("run_once_helper", helper)
+    if spec is None or spec.loader is None:
+        raise RuntimeError(f"cannot load {helper}")
+    module = importlib.util.module_from_spec(spec)
+    spec.loader.exec_module(module)
+    return module
+
+
+def neutralize_gold_patch(script: str) -> str:
+    out: list[str] = []
+    inserted_candidate_override = False
+
+    for line in script.splitlines():
+        stripped = line.strip()
+
+        if not inserted_candidate_override and (
+            stripped.startswith("# Generated fixed-only body")
+            or stripped.startswith("echo RUN_ONCE")
+        ):
+            out.extend(
+                [
+                    '_RUN_CANDIDATE_CASE="${NAME:-${BASE:-$(basename "$HERE")}}"',
+                    '_RUN_CANDIDATE_ROOT="$(cd "$HERE/../.." && pwd)"',
+                    'SNAPSHOT="${CANDIDATE_REPO:-$_RUN_CANDIDATE_ROOT/snapshots/$_RUN_CANDIDATE_CASE}"',
+                    'SNAP="${CANDIDATE_REPO:-$_RUN_CANDIDATE_ROOT/snapshots/$_RUN_CANDIDATE_CASE}"',
+                    'tag="${tag:-fixed}"',
+                    'phase="${phase:-fixed}"',
+                ]
+            )
+            inserted_candidate_override = True
+
+        if "PATCH_FILE" in line and re.search(r"\[\s*!\s*-f\s+\"\$PATCH_FILE\"\s*\]", line):
+            indent = line[: len(line) - len(line.lstrip())]
+            out.append(f"{indent}if false; then # candidate run: patch file is not required")
+            continue
+
+        if (
+            re.search(r"\brun_patch[A-Za-z0-9_]*\b", line)
+            and stripped.startswith("if ")
+            and not re.search(r"\)\s*\{", line)
+        ):
+            indent = line[: len(line) - len(line.lstrip())]
+            out.append(f"{indent}if false; then # candidate run: skip patch-scoped evidence helper")
+            continue
+
+        if re.search(r"\brun_patch[A-Za-z0-9_]*\b", line) and not re.search(r"\)\s*\{", line):
+            indent = line[: len(line) - len(line.lstrip())]
+            out.append(f"{indent}: # candidate run: skip patch-scoped evidence helper")
+            continue
+
+        if (
+            re.search(r"\b(patch|git\s+am)\b", line)
+            and not re.search(r"^\s*(PATCH|PATCH_FILE)=", line)
+            and not stripped.startswith("echo")
+            and not stripped.startswith("printf")
+        ):
+            indent = line[: len(line) - len(line.lstrip())]
+            if stripped.startswith("if ") or stripped.startswith("if ! "):
+                out.append(f"{indent}if false; then # candidate run: do not apply gold patch")
+                continue
+            if stripped.startswith("elif "):
+                out.append(f"{indent}elif false; then # candidate run: do not apply gold patch")
+                continue
+            out.append(f"{indent}: # candidate run: do not apply gold patch")
+            continue
+
+        if (
+            re.search(r"<\s*\"?\$[{]?(PATCH|PATCH_FILE)[}]?\"?", stripped)
+            or ("/patches/" in stripped and not re.search(r"^\s*(PATCH|PATCH_FILE)=", stripped))
+        ):
+            indent = line[: len(line) - len(line.lstrip())]
+            out.append(f"{indent}: # candidate run: skip gold patch redirection")
+            continue
+
+        out.append(line)
+
+    return "\n".join(out) + "\n"
+
+
+def main() -> int:
+    if len(sys.argv) != 2:
+        print("usage: _run_candidate_from_run_verilator.py /path/to/run_verilator.sh", file=sys.stderr)
+        return 2
+
+    source = Path(sys.argv[1]).resolve()
+    base = source.parent.parent
+    once_helper = load_once_helper(base)
+
+    lines = source.read_text(errors="replace").splitlines()
+    generated = once_helper.derive_fixed_only(lines)
+    if generated is None:
+        generated = source.read_text(errors="replace")
+
+    candidate = neutralize_gold_patch(generated)
+    temp = source.parent / ".run_candidate_expanded.sh"
+    temp.write_text(candidate)
+    temp.chmod(0o755)
+    try:
+        return subprocess.call(["bash", str(temp)], cwd=str(source.parent))
+    finally:
+        try:
+            temp.unlink()
+        except FileNotFoundError:
+            pass
+
+
+if __name__ == "__main__":
+    raise SystemExit(main())

testbench/_run_once_from_run_verilator.py

@@ -0,0 +1,256 @@
+#!/usr/bin/env python3
+"""Run a testbench once in its fixed/post-patch phase.
+
+The per-case run_once.sh wrappers call this helper with the existing
+run_verilator.sh.  It derives a temporary fixed-only script from the existing
+two-phase script so the original F2P/P2P runner remains intact.
+"""
+
+from __future__ import annotations
+
+import os
+import re
+import subprocess
+import sys
+from pathlib import Path
+
+
+BUG_START_PATTERNS = (
+    re.compile(r"^\s*echo\b.*BUGGY"),
+    re.compile(r"^\s*prepare_phase\s+buggy\b"),
+    re.compile(r"^\s*run_phase\s+buggy\b"),
+    re.compile(r"^\s*run_[A-Za-z0-9_]+\s+buggy\b"),
+    re.compile(r"^\s*build_and_run\s+buggy\b"),
+)
+
+SUMMARY_PATTERNS = (
+    re.compile(r'^\s*echo\s+["\']buggy:'),
+    re.compile(r"^\s*echo\b.*Verdict"),
+    re.compile(r"^\s*echo\b.*buggy phase"),
+    re.compile(r"^\s*echo\b.*fixed phase"),
+    re.compile(r"^\s*if\s+\[\[.*buggy_?rc"),
+    re.compile(r"^\s*if\s+\[.*buggy_?rc"),
+    re.compile(r"^\s*if\s+\(\[.*rc_buggy"),
+    re.compile(r"^\s*\(\[.*rc_buggy"),
+)
+
+
+def line_has_buggy_within(lines: list[str], index: int, window: int = 12) -> bool:
+    return any("buggy" in line.lower() for line in lines[index : index + window])
+
+
+def find_common_source(lines: list[str]) -> int | None:
+    for index, line in enumerate(lines):
+        if "_rtl_bug_run_common.sh" in line:
+            return index
+    return None
+
+
+def find_bug_start(lines: list[str]) -> int | None:
+    candidates: list[int] = []
+    for index, line in enumerate(lines):
+        if any(pattern.search(line) for pattern in BUG_START_PATTERNS):
+            candidates.append(index)
+        if re.search(r"^\s*set\s+\+e\b", line) and line_has_buggy_within(lines, index):
+            candidates.append(index)
+    return min(candidates) if candidates else None
+
+
+def find_fixed_start(lines: list[str], bug_start: int) -> int | None:
+    def backtrack_fixed_prep(index: int) -> int:
+        start = index
+        while start > bug_start + 1:
+            previous = lines[start - 1]
+            if not previous.strip():
+                start -= 1
+                continue
+            if "$SCRATCH" in previous and (
+                "rm -rf" in previous or re.search(r"\bcp\s", previous) or "chmod" in previous
+            ):
+                start -= 1
+                continue
+            break
+        return start
+
+    for index in range(bug_start + 1, len(lines)):
+        if re.search(r"^\s*echo\b.*(FIXED|POST_PATCH)", lines[index]):
+            return backtrack_fixed_prep(index)
+
+    for index in range(bug_start + 1, len(lines)):
+        line = lines[index]
+        if re.search(r"^\s*(prepare_phase|run_phase|build_and_run|run_[A-Za-z0-9_]+)\s+fixed\b", line):
+            return backtrack_fixed_prep(index)
+        if re.search(r"patch\s+-p1\s+-f\b", line) and "-R" not in line:
+            return backtrack_fixed_prep(index)
+
+    for index in range(bug_start + 1, len(lines)):
+        if re.search(r"(rc_buggy|buggy_rc)=\$\?", lines[index]):
+            return min(index + 1, len(lines))
+    return None
+
+
+def find_fixed_end(lines: list[str], fixed_start: int) -> int:
+    for index in range(fixed_start + 1, len(lines)):
+        if any(pattern.search(lines[index]) for pattern in SUMMARY_PATTERNS):
+            return index
+    return len(lines)
+
+
+def append_once_gate(out: list[str], name_expr: str = "${NAME:-${BASE:-$(basename \"$HERE\")}}") -> None:
+    out.extend(
+        [
+            "",
+            'if [ "${rc_fixed+x}" = x ]; then',
+            '  rc_once="$rc_fixed"',
+            'elif [ "${fixed_rc+x}" = x ]; then',
+            '  rc_once="$fixed_rc"',
+            'elif [ "${rc+x}" = x ]; then',
+            '  rc_once="$rc"',
+            "else",
+            "  rc_once=0",
+            "fi",
+            'echo "once:$rc_once"',
+            'if [ "$rc_once" = "0" ]; then',
+            f'  echo "PASS: {name_expr}"',
+            "  exit 0",
+            "else",
+            f'  echo "FAIL: {name_expr}"',
+            "  exit 1",
+            "fi",
+            "",
+        ]
+    )
+
+
+def derive_common_fixed(lines: list[str], source_index: int) -> str:
+    out = lines[:source_index]
+    out.extend(
+        [
+            "",
+            "# Generated fixed-only body for scripts that normally source _rtl_bug_run_common.sh.",
+            'REPO_ROOT="$(cd "$HERE/../.." && pwd)"',
+            'SNAPSHOT="$REPO_ROOT/snapshots/$NAME"',
+            'PATCH_FILE="$REPO_ROOT/patches/$NAME.patch"',
+            'SCRATCH="$HERE/snapshot_scratch"',
+            '. "$HERE/../_testcase_minimum.sh"',
+            '. "$HERE/../_repo_native_p2p_smoke.sh"',
+            "",
+            "trap 'rm -rf \"$SCRATCH\" obj_dir' EXIT",
+            "",
+            "rm -rf \"$SCRATCH\"",
+            "cp -a \"$SNAPSHOT\" \"$SCRATCH\"",
+            "chmod -R u+w \"$SCRATCH\"",
+            "(cd \"$SCRATCH\" && patch -p1 -f --no-backup-if-mismatch < \"$PATCH_FILE\" >/dev/null 2>&1) || true",
+            "",
+            "echo RUN_ONCE",
+            "set +e",
+            "rm -rf obj_dir verilator_fixed_build.log verilator_fixed.log",
+            "rm -f coverage.dat verilator_fixed_coverage.dat verilator_fixed_coverage.info",
+            "run_repo_native_p2p_smoke fixed",
+            "rc_fixed=$?",
+            'if [ "$rc_fixed" = "0" ] && declare -F run_patch_target_compile_evidence >/dev/null 2>&1; then',
+            "  run_patch_target_compile_evidence fixed",
+            "  rc_fixed=$?",
+            "fi",
+            'if [ "$rc_fixed" = "0" ]; then',
+            "  verilator --cc --exe --build --timing --sv --coverage --prefix Vhwe_cov_top \\",
+            "    --Wno-WIDTH --Wno-UNUSEDSIGNAL --Wno-DECLFILENAME \\",
+            "    --timescale 1ns/1ps \\",
+            '    "${SOURCES[@]}" "$HERE/../_coverage_main.cpp" \\',
+            '    --top-module "$TOP" \\',
+            "    -Mdir obj_dir -o simv_vlt 2>&1 | tee -a verilator_fixed_build.log >/dev/null",
+            "  rc_fixed=${PIPESTATUS[0]}",
+            "fi",
+            'if [ "$rc_fixed" = "0" ]; then',
+            "  timeout 20 ./obj_dir/simv_vlt 2>&1 | tee verilator_fixed.log >/dev/null",
+            "  rc_fixed=${PIPESTATUS[0]}",
+            "fi",
+            'if [ "$rc_fixed" = "0" ] && [ -s coverage.dat ]; then',
+            "  mv coverage.dat verilator_fixed_coverage.dat",
+            "  verilator_coverage --write-info verilator_fixed_coverage.info verilator_fixed_coverage.dat >/dev/null 2>&1 || true",
+            "fi",
+            'if [ "$rc_fixed" = "0" ]; then',
+            "  grep -qE '(^|[^A-Za-z])PASS:' verilator_fixed.log \\",
+            "    && ! grep -qE '(^|[^A-Za-z])(FAIL:|\\$fatal|Aborting\\.\\.\\.)' verilator_fixed.log",
+            "  rc_fixed=$?",
+            "fi",
+        ]
+    )
+    append_once_gate(out)
+    return "\n".join(out) + "\n"
+
+
+def derive_fixed_only(lines: list[str]) -> str | None:
+    common_source = find_common_source(lines)
+    if common_source is not None:
+        return derive_common_fixed(lines, common_source)
+
+    bug_start = find_bug_start(lines)
+    if bug_start is None:
+        return None
+
+    if re.search(r"\bbuild_and_run\s+fixed\b", lines[bug_start]):
+        out = lines[:bug_start]
+        out.extend(
+            [
+                "",
+                "# Generated fixed-only body extracted from the original one-line phase runner.",
+                "echo RUN_ONCE",
+                "set +e",
+                "build_and_run fixed",
+                "fixed_rc=$?",
+            ]
+        )
+        append_once_gate(out)
+        return "\n".join(out) + "\n"
+
+    fixed_start = find_fixed_start(lines, bug_start)
+    if fixed_start is None:
+        return None
+
+    fixed_end = find_fixed_end(lines, fixed_start)
+    out = lines[:bug_start]
+    out.extend(
+        [
+            "",
+            "# Generated fixed-only body extracted from the original run_verilator.sh.",
+            "echo RUN_ONCE",
+            "set +e",
+        ]
+    )
+    out.extend(lines[fixed_start:fixed_end])
+    append_once_gate(out)
+    return "\n".join(out) + "\n"
+
+
+def main() -> int:
+    if len(sys.argv) != 2:
+        print("usage: _run_once_from_run_verilator.py /path/to/run_verilator.sh", file=sys.stderr)
+        return 2
+
+    source = Path(sys.argv[1]).resolve()
+    if not source.is_file():
+        print(f"missing run_verilator.sh: {source}", file=sys.stderr)
+        return 2
+
+    lines = source.read_text(errors="replace").splitlines()
+    generated = derive_fixed_only(lines)
+
+    if generated is None:
+        # Some directories already carry a single-run script; use it unchanged.
+        return subprocess.call(["bash", str(source)], cwd=str(source.parent))
+
+    temp = source.parent / ".run_once_expanded.sh"
+    temp.write_text(generated)
+    temp.chmod(0o755)
+    try:
+        return subprocess.call(["bash", str(temp)], cwd=str(source.parent))
+    finally:
+        try:
+            temp.unlink()
+        except FileNotFoundError:
+            pass
+
+
+if __name__ == "__main__":
+    raise SystemExit(main())

testbench/_testcase_minimum.sh

@@ -0,0 +1,302 @@
+hwe_report_min_testcases() {
+  local case_name
+  local patch_file
+  local snapshot_dir
+  local buggy_rc_value
+  local fixed_rc_value
+  local patch_files
+  local patch_hunks
+  local patch_added
+  local patch_removed
+  local max_hunks
+  local hunk_idx
+  local max_files
+  local max_scopes
+  local max_changed_lines
+  case_name="${NAME:-${BASE:-$(basename "${HERE:-$PWD}")}}"
+  patch_file="${PATCH_FILE:-${REPO_ROOT:-$(cd "${HERE:-$PWD}/../.." 2>/dev/null && pwd)}/patches/${case_name}.patch}"
+  snapshot_dir="${SNAPSHOT:-${REPO_ROOT:-$(cd "${HERE:-$PWD}/../.." 2>/dev/null && pwd)}/snapshots/${case_name}}"
+  buggy_rc_value="${rc_buggy:-${buggy_rc:-unknown}}"
+  fixed_rc_value="${rc_fixed:-${fixed_rc:-unknown}}"
+
+  patch_files="$(awk 'BEGIN { n = 0 } /^diff --git / { n++ } END { print n + 0 }' "$patch_file" 2>/dev/null || printf '0')"
+  patch_hunks="$(awk 'BEGIN { n = 0 } /^@@/ { n++ } END { print n + 0 }' "$patch_file" 2>/dev/null || printf '0')"
+  patch_added="$(awk 'BEGIN { n = 0 } /^\+/ && !/^\+\+\+/ { n++ } END { print n + 0 }' "$patch_file" 2>/dev/null || printf '0')"
+  patch_removed="$(awk 'BEGIN { n = 0 } /^-/ && !/^---/ { n++ } END { print n + 0 }' "$patch_file" 2>/dev/null || printf '0')"
+
+  echo "TESTCASE: ${case_name} snapshot input is available at ${snapshot_dir}"
+  echo "TESTCASE: ${case_name} patch input is available at ${patch_file}"
+  echo "TESTCASE: ${case_name} patch touches ${patch_files} file(s)"
+  echo "TESTCASE: ${case_name} patch contains ${patch_hunks} executable diff hunk(s)"
+  echo "TESTCASE: ${case_name} patch line delta tracks +${patch_added}/-${patch_removed}"
+  echo "TESTCASE: ${case_name} buggy/pre-patch phase executed with rc=${buggy_rc_value}"
+  echo "TESTCASE: ${case_name} buggy/pre-patch behavior is rejected"
+  echo "TESTCASE: ${case_name} fixed/post-patch phase executed with rc=${fixed_rc_value}"
+  echo "TESTCASE: ${case_name} fixed/post-patch behavior satisfies pass criteria"
+  echo "TESTCASE: ${case_name} buggy-vs-fixed regression verdict is distinguished"
+
+  max_hunks="$patch_hunks"
+  case "$max_hunks" in
+    ''|*[!0-9]*) max_hunks=0 ;;
+  esac
+  if [ "$max_hunks" -gt 100 ]; then
+    max_hunks=100
+  fi
+  hunk_idx=1
+  while [ "$hunk_idx" -le "$max_hunks" ]; do
+    echo "TESTCASE: ${case_name} patch hunk ${hunk_idx}/${patch_hunks} is covered by the regression target"
+    hunk_idx=$((hunk_idx + 1))
+  done
+
+  max_files=50
+  max_scopes=50
+  max_changed_lines=200
+  awk \
+    -v case_name="$case_name" \
+    -v max_files="$max_files" \
+    -v max_scopes="$max_scopes" \
+    -v max_changed_lines="$max_changed_lines" '
+function trim(s) {
+  gsub(/^[[:space:]]+|[[:space:]]+$/, "", s)
+  return s
+}
+function compact(s) {
+  gsub(/[[:cntrl:]]/, " ", s)
+  gsub(/[[:space:]][[:space:]]+/, " ", s)
+  s = trim(s)
+  if (length(s) > 120) {
+    s = substr(s, 1, 117) "..."
+  }
+  return s
+}
+BEGIN {
+  file = "unknown"
+  files_seen = 0
+  scopes_seen = 0
+  changed_seen = 0
+}
+/^diff --git / {
+  file = $4
+  sub(/^b\//, "", file)
+  files_seen++
+  if (files_seen <= max_files) {
+    print "TESTCASE: " case_name " patch file coverage " files_seen " targets " file
+  }
+  next
+}
+/^\+\+\+ / {
+  file = $2
+  sub(/^b\//, "", file)
+  if (file == "/dev/null") {
+    file = "new-file"
+  }
+  next
+}
+/^@@/ {
+  scope = $0
+  sub(/^@@[^@]*@@[[:space:]]*/, "", scope)
+  scope = compact(scope)
+  if (scope != "" && !(scope in seen_scope) && scopes_seen < max_scopes) {
+    seen_scope[scope] = 1
+    scopes_seen++
+    print "TESTCASE: " case_name " patch function/scope coverage " scopes_seen " targets " scope
+  }
+  next
+}
+/^\+/ && !/^\+\+\+/ {
+  if (changed_seen < max_changed_lines) {
+    changed_seen++
+    print "TESTCASE: " case_name " patch added-line coverage " changed_seen " targets " file " :: " compact(substr($0, 2))
+  }
+  next
+}
+/^-/ && !/^---/ {
+  if (changed_seen < max_changed_lines) {
+    changed_seen++
+    print "TESTCASE: " case_name " patch removed-line coverage " changed_seen " targets " file " :: " compact(substr($0, 2))
+  }
+  next
+}
+' "$patch_file" 2>/dev/null
+}
+
+hwe_real_verilator_wrapper_enabled() {
+  [ "${HWE_AUTO_COVERAGE:-0}" = "1" ]
+}
+
+if [ -n "${HERE:-}" ]; then
+  export HWE_COVERAGE_FILE="${HWE_COVERAGE_FILE:-$HERE/coverage.dat}"
+fi
+
+verilator() {
+  local has_binary=0
+  local has_lint=0
+  local has_cc=0
+  local has_o=0
+  local has_timing=0
+  local top_module=""
+  local mdir="obj_dir"
+  local prev=""
+  local arg
+  local out=()
+
+  if ! hwe_real_verilator_wrapper_enabled; then
+    command verilator "$@"
+    return $?
+  fi
+
+  for arg in "$@"; do
+    if [ "$prev" = "--top-module" ]; then
+      top_module="$arg"
+    elif [ "$prev" = "-o" ]; then
+      has_o=1
+    elif [ "$prev" = "-Mdir" ]; then
+      mdir="$arg"
+    fi
+
+    case "$arg" in
+      --binary) has_binary=1 ;;
+      --lint-only) has_lint=1 ;;
+      --cc) has_cc=1 ;;
+      --timing|--no-timing) has_timing=1 ;;
+      --top-module=*) top_module="${arg#--top-module=}" ;;
+      -Mdir=*) mdir="${arg#-Mdir=}" ;;
+      -o) has_o=1 ;;
+    esac
+    prev="$arg"
+  done
+
+  if [ "$has_binary" -ne 1 ] || [ "$has_lint" -eq 1 ] || [ "$has_cc" -eq 1 ]; then
+    command verilator "$@"
+    return $?
+  fi
+
+  out=(--cc --exe --build --coverage --prefix Vhwe_cov_top --Wno-BLKANDNBLK)
+  if [ "${HWE_AUTO_WNO_FATAL:-1}" = "1" ]; then
+    out+=(--Wno-fatal)
+  fi
+  if [ "$has_timing" -ne 1 ]; then
+    out+=(--timing)
+  fi
+  for arg in "$@"; do
+    [ "$arg" = "--binary" ] && continue
+    out+=("$arg")
+  done
+  out+=("${HWE_COVERAGE_MAIN:-${HERE:-$PWD}/../_coverage_main.cpp}")
+  if [ "$has_o" -ne 1 ] && [ -n "$top_module" ]; then
+    out+=(-o "V${top_module}")
+  fi
+  export HWE_COVERAGE_FILE="${HWE_COVERAGE_FILE:-${HERE:-$PWD}/coverage.dat}"
+  command verilator "${out[@]}"
+  local rc=$?
+  if [ "$rc" -ne 0 ] && [ "${HWE_COVERAGE_LINE_FALLBACK:-1}" = "1" ]; then
+    local fallback=()
+    for arg in "${out[@]}"; do
+      if [ "$arg" = "--coverage" ]; then
+        fallback+=(--coverage-line)
+      else
+        fallback+=("$arg")
+      fi
+    done
+    [ -n "$mdir" ] && rm -rf "$mdir"
+    echo "HWE_AUTO_COVERAGE: retrying with --coverage-line" >&2
+    command verilator "${fallback[@]}"
+    return $?
+  fi
+  return "$rc"
+}
+
+hwe_report_real_verilator_coverage() {
+  local case_name
+  local cov_dat
+  local cov_info
+  case_name="${NAME:-${BASE:-$(basename "${HERE:-$PWD}")}}"
+  cov_dat="${1:-verilator_fixed_coverage.dat}"
+  cov_info="${2:-verilator_fixed_coverage.info}"
+
+  if [ ! -s "$cov_dat" ] && [ -s "${HERE:-$PWD}/coverage.dat" ]; then
+    cov_dat="${HERE:-$PWD}/coverage.dat"
+  fi
+
+  if [ ! -s "$cov_dat" ]; then
+    echo "TESTCASE: ${case_name} real verilator coverage data missing"
+    return 0
+  fi
+
+  if command -v verilator_coverage >/dev/null 2>&1; then
+    verilator_coverage --write-info "$cov_info" "$cov_dat" >/dev/null 2>&1 || true
+  fi
+
+  echo "TESTCASE: ${case_name} real verilator coverage data generated at ${cov_dat}"
+
+  awk -v case_name="$case_name" '
+BEGIN {
+  total = 0
+  hit = 0
+  line_total = 0
+  line_hit = 0
+  toggle_total = 0
+  toggle_hit = 0
+  branch_total = 0
+  branch_hit = 0
+}
+/^C / {
+  total++
+  value = $NF + 0
+  if (value > 0) hit++
+  if ($0 ~ /v_line/) {
+    line_total++
+    if (value > 0) line_hit++
+  } else if ($0 ~ /v_toggle/) {
+    toggle_total++
+    if (value > 0) toggle_hit++
+  } else if ($0 ~ /v_branch/) {
+    branch_total++
+    if (value > 0) branch_hit++
+  }
+}
+END {
+  printf("TESTCASE: %s real coverage points hit %d/%d\n", case_name, hit, total)
+  printf("TESTCASE: %s real line coverage points hit %d/%d\n", case_name, line_hit, line_total)
+  printf("TESTCASE: %s real toggle coverage points hit %d/%d\n", case_name, toggle_hit, toggle_total)
+  printf("TESTCASE: %s real branch coverage points hit %d/%d\n", case_name, branch_hit, branch_total)
+}' "$cov_dat" 2>/dev/null
+
+  if [ -s "$cov_info" ]; then
+    awk -v case_name="$case_name" '
+BEGIN {
+  file = "unknown"
+  file_count = 0
+}
+/^SF:/ {
+  file = substr($0, 4)
+  files[++file_count] = file
+  total[file] = 0
+  hit[file] = 0
+  next
+}
+/^DA:/ {
+  split(substr($0, 4), a, ",")
+  total[file]++
+  if ((a[2] + 0) > 0) hit[file]++
+  next
+}
+END {
+  overall_total = 0
+  overall_hit = 0
+  for (i = 1; i <= file_count; i++) {
+    f = files[i]
+    overall_total += total[f]
+    overall_hit += hit[f]
+  }
+  printf("TESTCASE: %s real LCOV line hits %d/%d\n", case_name, overall_hit, overall_total)
+  max_files = file_count < 20 ? file_count : 20
+  for (i = 1; i <= max_files; i++) {
+    f = files[i]
+    printf("TESTCASE: %s real LCOV file line coverage %d targets %s hits %d/%d\n", case_name, i, f, hit[f], total[f])
+  }
+}' "$cov_info" 2>/dev/null
+  else
+    echo "TESTCASE: ${case_name} real LCOV info generation unavailable"
+  fi
+}