repo stringlengths 7 90 | file_url stringlengths 81 315 | file_path stringlengths 4 228 | content stringlengths 0 32.8k | language stringclasses 1
value | license stringclasses 7
values | commit_sha stringlengths 40 40 | retrieved_at stringdate 2026-01-04 14:38:15 2026-01-05 02:33:18 | truncated bool 2
classes |
|---|---|---|---|---|---|---|---|---|
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/tools/extract_tilegrid.py | tools/extract_tilegrid.py | #!/usr/bin/env python3
"""
This script reads the output from Lattice's bstool in "test" mode, which should be invoked thus:
```
bstool -t bitstream.bit > bitstream.test
```
and from it obtains a list of tiles with the following information:
- Tile name (with position encoded in the name)
- Tile type
- Fra... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/tools/fixup_io_tilegrid.py | tools/fixup_io_tilegrid.py | import database
import tiles
import json
from os import path
"""
Despite Lattice assigning them the same tile type; "odd" and "even" top/left/right IO
locations have slightly different routing - swapped output tristate and data
This script fixes this by patching tile names
"""
for f, d in [("LIFCL", "LIFCL-40"), ("L... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/tools/html_tilebits.py | tools/html_tilebits.py | #!/usr/bin/env python3
"""
Convert the tile grid for a given family and device to HTML format
"""
import sys, re
import argparse
import database
import libpyprjoxide
from os import path
parser = argparse.ArgumentParser(description=__doc__)
parser.add_argument('family', type=str,
help="FPGA family (... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LFCPNX/021-cmux/fuzzer.py | fuzzers/LFCPNX/021-cmux/fuzzer.py | from fuzzconfig import FuzzConfig
from interconnect import fuzz_interconnect
import re
cfg = FuzzConfig(job="CMUXROUTE", device="LFCPNX-100", sv="../shared/route_100.v",
tiles=["CIB_R38C73:CMUX_0", "CIB_R38C74:CMUX_1_GSR",
"CIB_R47C73:CMUX_2_TRUNK_LL", "CIB_R47C74:CMUX_3_TRUNK_LR",
"CIB_R29C73:CMUX_4_TRUNK... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LFCPNX/020-plc_tap/fuzzer.py | fuzzers/LFCPNX/020-plc_tap/fuzzer.py | from fuzzconfig import FuzzConfig
from interconnect import fuzz_interconnect
import re
configs = [
([(11, 7), (11, 19)], [], FuzzConfig(job="TAPROUTE", device="LFCPNX-100", sv="../shared/route_100.v", tiles=["TAP_PLC_R11C14:TAP_PLC"])),
([(10, 7), (10, 19)], [], FuzzConfig(job="TAPROUTECIB", device="LFCPNX-100... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LFCPNX/012-plc-modes/fuzzer.py | fuzzers/LFCPNX/012-plc-modes/fuzzer.py | from fuzzconfig import FuzzConfig
import nonrouting
import fuzzloops
import re
cfg = FuzzConfig(job="SLICEMODE", device="LFCPNX-100", sv="../shared/empty_100.v", tiles=["R2C2:PLC"])
def main():
cfg.setup()
empty = cfg.build_design(cfg.sv, {})
cfg.sv = "slice.v"
def per_slice(slicen):
def get_... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LFCPNX/001-plc-routing/fuzzer.py | fuzzers/LFCPNX/001-plc-routing/fuzzer.py | from fuzzconfig import FuzzConfig
from interconnect import fuzz_interconnect
import re
cfg = FuzzConfig(job="PLCROUTE", device="LFCPNX-100", sv="../shared/route_100.v", tiles=["R16C22:PLC"])
def main():
cfg.setup()
r = 16
c = 22
nodes = ["R{}C{}_J*".format(r, c)]
extra_sources = []
extra_sourc... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LFCPNX/011-reg-config/fuzzer.py | fuzzers/LFCPNX/011-reg-config/fuzzer.py | from fuzzconfig import FuzzConfig
import nonrouting
import fuzzloops
import re
cfg = FuzzConfig(job="REGCFG", device="LFCPNX-100", sv="../shared/empty_100.v", tiles=["R2C2:PLC"])
def main():
cfg.setup()
empty = cfg.build_design(cfg.sv, {})
cfg.sv = "ff.v"
def per_slice(slicen):
for r in range... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LFCPNX/030-io_route/fuzzer.py | fuzzers/LFCPNX/030-io_route/fuzzer.py | from fuzzconfig import FuzzConfig
from interconnect import fuzz_interconnect
import re
configs = [
{
"cfg": FuzzConfig(job="IOROUTE5", device="LFCPNX-100", sv="../shared/route_100.v", tiles=["CIB_R74C10:SYSIO_B5_0", "CIB_R74C11:SYSIO_B5_1"]),
"rc": (74, 10),
},
{
"cfg": FuzzConfig(j... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LFCPNX/002-cib-routing/fuzzer.py | fuzzers/LFCPNX/002-cib-routing/fuzzer.py | from fuzzconfig import FuzzConfig
from interconnect import fuzz_interconnect
import re
configs = [
((1, 18), FuzzConfig(job="CIBTROUTE", device="LFCPNX-100", sv="../shared/route_100.v", tiles=["CIB_R1C18:CIB_T"]), set(["TAP_CIBT_R1C14:TAP_CIBT"])),
((18, 1), FuzzConfig(job="CIBLRROUTE", device="LFCPNX-100", sv... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LFCPNX/023-trunk-spine/fuzzer.py | fuzzers/LFCPNX/023-trunk-spine/fuzzer.py | from fuzzconfig import FuzzConfig
from interconnect import fuzz_interconnect
import re
spine_cfgs = {
("CIB_R29C13:SPINE_UL2", "R19C13"),
("CIB_R29C37:SPINE_UL1", "R19C37"),
("CIB_R29C61:SPINE_UL0", "R19C61"),
("CIB_R29C86:SPINE_UR0", "R19C85"),
("CIB_R29C110:SPINE_UR1", "R19C109"),
("CIB_R29C1... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LFCPNX/110-global-structure/fuzzer.py | fuzzers/LFCPNX/110-global-structure/fuzzer.py | import database
import lapie
import json
from fuzzconfig import FuzzConfig
from tiles import pos_from_name
from os import path
# name max_row max_col
configs = [
("LFCPNX-100", 74, 159, "../shared/empty_100.v"),
]
def main():
for name, max_row, max_col, sv in configs:
cfg = FuzzConfig(job="GLOBAL_{}".... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LFCPNX/010-lut-init/fuzzer.py | fuzzers/LFCPNX/010-lut-init/fuzzer.py | from fuzzconfig import FuzzConfig
import nonrouting
import fuzzloops
import re
cfg = FuzzConfig(job="PLCINIT", device="LFCPNX-100", sv="../shared/empty_100.v", tiles=["R2C2:PLC"])
def get_lut_function(init_bits):
sop_terms = []
lut_inputs = ["A", "B", "C", "D"]
for i in range(16):
if init_bits[i]:... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LFCPNX/022-midmux/fuzzer.py | fuzzers/LFCPNX/022-midmux/fuzzer.py | from fuzzconfig import FuzzConfig
from interconnect import fuzz_interconnect
cr, cc = (37, 73)
configs = [
("HPFE", (37, 0), 12, "L",
FuzzConfig(job="LMIDROUTE", device="LFCPNX-100", sv="../shared/route_100.v", tiles=["CIB_R37C0:LMID"])),
("HPFW", (37, 158), 12, "R",
FuzzConfig(job="RMIDROUTE"... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/071-iodelay/fuzzer.py | fuzzers/LIFCL/071-iodelay/fuzzer.py | from fuzzconfig import FuzzConfig
import nonrouting
import fuzzloops
import re
configs = [
("IOL_B8A", "IOLOGICA", FuzzConfig(job="IOL5AMODE", device="LIFCL-40", sv="../shared/empty_40.v", tiles=["CIB_R56C8:SYSIO_B5_0", "CIB_R56C9:SYSIO_B5_1"])),
("IOL_B8B", "IOLOGICB", FuzzConfig(job="IOL5BMODE", device="LIFC... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/035-bankref/fuzzer.py | fuzzers/LIFCL/035-bankref/fuzzer.py | from fuzzconfig import FuzzConfig
import nonrouting
import fuzzloops
import re
configs = [
(1, "F16",
FuzzConfig(job="IO1A_17", device="LIFCL-17", sv="../shared/empty_17.v", tiles=["CIB_R2C75:BK1_15K"])),
(0, "E15",
FuzzConfig(job="IO0A_17", device="LIFCL-17", sv="../shared/empty_17.v", tiles=[... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/140-bram-init/fuzzer.py | fuzzers/LIFCL/140-bram-init/fuzzer.py | from fuzzconfig import FuzzConfig
import nonrouting
import fuzzloops
import re
cfg = FuzzConfig(job="EBRINIT", device="LIFCL-40", sv="../shared/empty_40.v", tiles=["EBR_WID0:EBR_INIT"])
def bin2dec(bits):
x = 0
for i, b in enumerate(bits):
if b:
x |= (1 << i)
return x
def main():
... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/021-cmux/fuzzer.py | fuzzers/LIFCL/021-cmux/fuzzer.py | from fuzzconfig import FuzzConfig
from interconnect import fuzz_interconnect
import re
cfg = FuzzConfig(job="CMUXROUTE", device="LIFCL-40", sv="../shared/route_40.v", tiles=["CIB_R29C49:CMUX_0", "CIB_R29C50:CMUX_1", "CIB_R38C49:CMUX_2", "CIB_R38C50:CMUX_3"])
def main():
cfg.setup()
nodes = ["R28C49_JHPRX{}_CM... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/090-sysconfig/fuzzer.py | fuzzers/LIFCL/090-sysconfig/fuzzer.py | from fuzzconfig import FuzzConfig
import nonrouting
import fuzzloops
import re
cfgs = [
FuzzConfig(job="SYSCONFIG40", device="LIFCL-40", sv="../shared/empty_40.v",
tiles=["CIB_R0C75:EFB_0", "CIB_R0C72:BANKREF0", "CIB_R0C77:EFB_1_OSC", "CIB_R0C79:EFB_2",
"CIB_R0C81:I2C_EFB_3", "CIB_R0C85:PMU", "CIB_... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/020-plc_tap/fuzzer.py | fuzzers/LIFCL/020-plc_tap/fuzzer.py | from fuzzconfig import FuzzConfig
from interconnect import fuzz_interconnect
import re
configs = [
([(11, 7), (11, 19)], [], FuzzConfig(job="TAPROUTE", device="LIFCL-40", sv="../shared/route_40.v", tiles=["TAP_PLC_R11C14:TAP_PLC"])),
([(10, 7), (10, 19)], [], FuzzConfig(job="TAPROUTECIB", device="LIFCL-40", sv... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/012-plc-modes/fuzzer.py | fuzzers/LIFCL/012-plc-modes/fuzzer.py | from fuzzconfig import FuzzConfig
import nonrouting
import fuzzloops
import re
cfg = FuzzConfig(job="SLICEMODE", device="LIFCL-40", sv="../shared/empty_40.v", tiles=["R2C2:PLC"])
def main():
cfg.setup()
empty = cfg.build_design(cfg.sv, {})
cfg.sv = "slice.v"
def per_slice(slicen):
def get_sub... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/063-lram-routing/fuzzer.py | fuzzers/LIFCL/063-lram-routing/fuzzer.py | from fuzzconfig import FuzzConfig
from interconnect import fuzz_interconnect
import re
configs = [
{
"cfg": FuzzConfig(job="LRAMROUTE0", device="LIFCL-40", sv="../shared/route_40.v", tiles=["CIB_R23C87:LRAM_0"]),
"rc": (18, 86),
},
{
"cfg": FuzzConfig(job="LRAMROUTE1", device="LIFCL... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/152-dqsroute/fuzzer.py | fuzzers/LIFCL/152-dqsroute/fuzzer.py | from fuzzconfig import FuzzConfig
from interconnect import fuzz_interconnect
import re
configs = [
{
"cfg": FuzzConfig(job="DQS3", device="LIFCL-40", sv="../shared/route_40.v",
tiles=["CIB_R56C75:SYSIO_B3_1_DQS0", "CIB_R56C76:SYSIO_B3_0_DQS1", "CIB_R56C77:SYSIO_B3_1_DQS2", "CIB_R56C78:SYSIO_B3_... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/060-ebr-config/fuzzer.py | fuzzers/LIFCL/060-ebr-config/fuzzer.py | from fuzzconfig import FuzzConfig
import nonrouting
import fuzzloops
import re
configs = [
("EBR_CORE_R28C26", "EBR0", FuzzConfig(job="EBRMODE0", device="LIFCL-40", sv="../shared/empty_40.v", tiles=["CIB_R29C26:MIB_EBR", "CIB_R29C27:EBR_1", "CIB_R29C28:EBR_2"])),
("EBR_CORE_R28C29", "EBR1", FuzzConfig(job="EBR... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/100-ip-base/fuzzer.py | fuzzers/LIFCL/100-ip-base/fuzzer.py | import fuzzconfig
import nonrouting
import fuzzloops
import database
from os import path
import libpyprjoxide
import json
cfgs = [
# (fuzzconfig.FuzzConfig(job="IPADDR", device="LIFCL-40", sv="ip.v", tiles=[]),
# [
# ("TDPHY_CORE2", "DPHY_CORE"),
# ("TDPHY_CORE26", "DPHY_CORE"),
... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/162-pcie-ipconfig/fuzzer.py | fuzzers/LIFCL/162-pcie-ipconfig/fuzzer.py | from fuzzconfig import FuzzConfig
import nonrouting
import fuzzloops
import re
import os
import get_params
cfg = FuzzConfig(job="PCIEIP", device="LIFCL-40", sv="../shared/empty_40.v", tiles=["TPCIE_CORE57:PCIE_CORE"])
def bin2bin(bits):
return "0b{}".format("".join(["1" if b else "0" for b in reversed(bits)]))
... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/001-plc-routing/fuzzer.py | fuzzers/LIFCL/001-plc-routing/fuzzer.py | from fuzzconfig import FuzzConfig
from interconnect import fuzz_interconnect
import re
cfg = FuzzConfig(job="PLCROUTE", device="LIFCL-40", sv="../shared/route_40.v", tiles=["R16C22:PLC"])
def main():
cfg.setup()
r = 16
c = 22
nodes = ["R{}C{}_J*".format(r, c)]
extra_sources = []
extra_sources ... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/011-reg-config/fuzzer.py | fuzzers/LIFCL/011-reg-config/fuzzer.py | from fuzzconfig import FuzzConfig
import nonrouting
import fuzzloops
import re
cfg = FuzzConfig(job="REGCFG", device="LIFCL-40", sv="../shared/empty_40.v", tiles=["R2C2:PLC"])
def main():
cfg.setup()
empty = cfg.build_design(cfg.sv, {})
cfg.sv = "ff.v"
def per_slice(slicen):
for r in range(2)... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/120-pll-routing/fuzzer.py | fuzzers/LIFCL/120-pll-routing/fuzzer.py | from fuzzconfig import FuzzConfig
from interconnect import fuzz_interconnect
import re
configs = [
{
"cfg": FuzzConfig(job="PLLULC", device="LIFCL-40", sv="../shared/route_40.v", tiles=["CIB_R0C1:GPLL_ULC"]),
"rc": (1, 1),
},
{
"cfg": FuzzConfig(job="PLLLLC", device="LIFCL-40", sv="... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/030-io_route/fuzzer.py | fuzzers/LIFCL/030-io_route/fuzzer.py | from fuzzconfig import FuzzConfig
from interconnect import fuzz_interconnect
import re
configs = [
{
"cfg": FuzzConfig(job="IOROUTE0_17K", device="LIFCL-17", sv="../shared/route_17.v", tiles=["CIB_R0C59:SYSIO_B0_0_15K"]),
"rc": (0, 59),
},
{
"cfg": FuzzConfig(job="IOROUTE1_17K", dev... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/067-copy-ebr/fuzzer.py | fuzzers/LIFCL/067-copy-ebr/fuzzer.py | import database
import libpyprjoxide
def main():
db = libpyprjoxide.Database(database.get_db_root())
libpyprjoxide.copy_db(db, "LIFCL", "EBR_10", ["TRUNK_L_EBR_10", ], "PEWC", "")
if __name__ == '__main__':
main()
| python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/153-dqsbuf/fuzzer.py | fuzzers/LIFCL/153-dqsbuf/fuzzer.py | from fuzzconfig import FuzzConfig
import nonrouting
import fuzzloops
import re
configs = [
{
"cfg": FuzzConfig(job="DQS3", device="LIFCL-40", sv="../shared/route_40.v",
tiles=["CIB_R56C75:SYSIO_B3_1_DQS0", "CIB_R56C76:SYSIO_B3_0_DQS1", "CIB_R56C77:SYSIO_B3_1_DQS2", "CIB_R56C78:SYSIO_B3_0_DQS3",... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/154-ddrll/fuzzer.py | fuzzers/LIFCL/154-ddrll/fuzzer.py | from fuzzconfig import FuzzConfig
from interconnect import fuzz_interconnect
import nonrouting
import re
configs = [
{
"cfg": FuzzConfig(job="DDRDLLL", device="LIFCL-40", sv="../shared/route_40.v",
tiles=["CIB_R56C2:DOSCL_P18_V18"]),
"rc": (55, 2),
},
{
"cfg": FuzzConfig... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/039-copy-io/fuzzer.py | fuzzers/LIFCL/039-copy-io/fuzzer.py | import database
import libpyprjoxide
def main():
db = libpyprjoxide.Database(database.get_db_root())
libpyprjoxide.copy_db(db, "LIFCL", "SYSIO_B5_1", ["SYSIO_B5_1_V18", "SYSIO_B5_1_15K_DQS51", "SYSIO_B5_1_15K_DQS50", "SYSIO_B5_1_15K_ECLK_L_V52"], "PEWC", "")
libpyprjoxide.copy_db(db, "LIFCL", "SYSIO_B5_0",... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/061-ebr-routing/fuzzer.py | fuzzers/LIFCL/061-ebr-routing/fuzzer.py | from fuzzconfig import FuzzConfig
from interconnect import fuzz_interconnect
import re
configs = [
{
"cfg": FuzzConfig(job="EBRROUTE0", device="LIFCL-40", sv="../shared/route_40.v", tiles=["CIB_R29C15:EBR_1", "CIB_R29C16:EBR_2", "CIB_R29C14:MIB_EBR"]),
"rc": (28, 14),
},
{
"cfg": Fu... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/900-always-on/fuzzer.py | fuzzers/LIFCL/900-always-on/fuzzer.py | from fuzzconfig import FuzzConfig
import nonrouting
import fuzzloops
import re
import libpyprjoxide
import fuzzconfig
cfgs = [
FuzzConfig(job="EMPTY", device="LIFCL-40", sv="../shared/empty_40.v", tiles=[]),
FuzzConfig(job="EMPTY", device="LIFCL-17", sv="../shared/empty_17.v", tiles=[]),
]
def main():
for cfg in c... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/040-speed/fuzzer.py | fuzzers/LIFCL/040-speed/fuzzer.py | from fuzzconfig import FuzzConfig
import nonrouting
import fuzzloops
import re
import database
speed_map = {
"FAST_1V0": "7_High-Performance_1.0V",
"SLOW_1V0": "7_Low-Power_1.0V",
}
all_tiles_40 = set(database.get_tilegrid("LIFCL", "LIFCL-40")["tiles"].keys())
cfg = FuzzConfig(job="SPEED", device="LIFCL-40", sv=".... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/050-cib-special/fuzzer.py | fuzzers/LIFCL/050-cib-special/fuzzer.py | from fuzzconfig import FuzzConfig
import nonrouting
from interconnect import fuzz_interconnect
import lapie
import re
import fuzzloops
configs = [
((46, 6), FuzzConfig(job="CIBENABLE", device="LIFCL-40", sv="../shared/route_40.v", tiles=["CIB_R46C6:CIB"])),
((1, 18), FuzzConfig(job="CIBTENABLE", device="LIFCL-... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/092-gsr/fuzzer.py | fuzzers/LIFCL/092-gsr/fuzzer.py | from fuzzconfig import FuzzConfig
import nonrouting
import fuzzloops
import re
from interconnect import fuzz_interconnect
cfg = FuzzConfig(job="GSR", device="LIFCL-40", sv="../shared/empty_40.v", tiles=["CIB_R29C49:CMUX_0", "CIB_R29C50:CMUX_1"])
def main():
cfg.setup()
empty = cfg.build_design(cfg.sv, {})
... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/151-eclkprim/fuzzer.py | fuzzers/LIFCL/151-eclkprim/fuzzer.py | from fuzzconfig import FuzzConfig
import nonrouting
import fuzzloops
import re
configs = [
{
"cfg": FuzzConfig(job="ECLK0", device="LIFCL-40", sv="../shared/empty_40.v", tiles=["CIB_R56C48:ECLK_0", "CIB_R56C49:BMID_0_ECLK_1", "CIB_R56C50:BMID_1_ECLK_2", "CIB_R56C51:ECLK_3"]),
"rc": (55, 48),
... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/122-pll-config/fuzzer.py | fuzzers/LIFCL/122-pll-config/fuzzer.py | from fuzzconfig import FuzzConfig
import nonrouting
import fuzzloops
import re
from interconnect import fuzz_interconnect
cfgs = [
("PLL_LLC",
FuzzConfig(job="PLL_LL", device="LIFCL-40", sv="../shared/empty_40.v", tiles=["CIB_R55C0:GPLL_LLC"]),
),
("PLL_ULC",
FuzzConfig(job="PLL_LL", device... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/002-cib-routing/fuzzer.py | fuzzers/LIFCL/002-cib-routing/fuzzer.py | from fuzzconfig import FuzzConfig
from interconnect import fuzz_interconnect
import re
configs = [
((1, 18), FuzzConfig(job="CIBTROUTE", device="LIFCL-40", sv="../shared/route_40.v", tiles=["CIB_R1C18:CIB_T"]), set(["TAP_CIBT_R1C14:TAP_CIBT"])),
((18, 1), FuzzConfig(job="CIBLRROUTE", device="LIFCL-40", sv="../... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/032-hsio_mode/fuzzer.py | fuzzers/LIFCL/032-hsio_mode/fuzzer.py | from fuzzconfig import FuzzConfig
import nonrouting
import fuzzloops
import re
configs = [
("A","V1", # PB6A
FuzzConfig(job="IO5A", device="LIFCL-40", sv="../shared/empty_40.v", tiles=["CIB_R56C6:SYSIO_B5_0", "CIB_R56C7:SYSIO_B5_1"])),
("B","W1", # PB6B
FuzzConfig(job="IO5B", device="LIFCL-40",... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/160-hard-ip-routing/fuzzer.py | fuzzers/LIFCL/160-hard-ip-routing/fuzzer.py | from fuzzconfig import FuzzConfig
from interconnect import fuzz_interconnect
import re
configs = [
{
"cfg": FuzzConfig(job="DPHYROUTE0", device="LIFCL-40", sv="../shared/route_40.v", tiles=["CIB_R0C4:MIPI_DPHY_0", "CIB_R0C2:DPHY_CLKMUX0"]),
"rc": (0, 2),
},
{
"cfg": FuzzConfig(job="... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/023-trunk-spine/fuzzer.py | fuzzers/LIFCL/023-trunk-spine/fuzzer.py | from fuzzconfig import FuzzConfig
from interconnect import fuzz_interconnect
import re
spine_cfgs = {
("CIB_R29C13:SPINE_L1", "R28C13"),
("CIB_R29C37:SPINE_L0", "R28C37"),
("CIB_R29C62:SPINE_R0", "R28C61"),
("CIB_R29C74:SPINE_R1", "R28C73"),
}
hrow_cfgs = {
("CIB_R29C37:SPINE_L0", "R28C31"),
(... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/024-dcc-dcs/fuzzer.py | fuzzers/LIFCL/024-dcc-dcs/fuzzer.py | from fuzzconfig import FuzzConfig
import nonrouting
import fuzzloops
import re
def main():
# 40k
dev = "LIFCL-40"
sv = "../shared/empty_40.v"
dcc_tiles = ["CIB_R28C0:LMID", "CIB_R28C87:RMID_DLY20", "CIB_R56C49:BMID_0_ECLK_1", "CIB_R56C50:BMID_1_ECLK_2",
"CIB_R0C49:TMID_0", "CIB_R0C50:TMID_1", "... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/091-osc/fuzzer.py | fuzzers/LIFCL/091-osc/fuzzer.py | from fuzzconfig import FuzzConfig
import nonrouting
import fuzzloops
import re
from interconnect import fuzz_interconnect
cfgs = [
FuzzConfig(job="OSCMODE17", device="LIFCL-17", sv="../shared/empty_17.v", tiles=["CIB_R0C71:OSC_15K"]),
FuzzConfig(job="OSCMODE40", device="LIFCL-40", sv="../shared/empty_40.v", ti... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/121-pll-ipconfig/fuzzer.py | fuzzers/LIFCL/121-pll-ipconfig/fuzzer.py | from fuzzconfig import FuzzConfig
import nonrouting
import fuzzloops
import re
cfg = FuzzConfig(job="PLLIP", device="LIFCL-40", sv="../shared/empty_40.v", tiles=["PLL_LLC:PLL_CORE"])
def bin2dec(bits):
x = 0
for i, b in enumerate(bits):
if b:
x |= (1 << i)
return x
def bin2bin(bits):
... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/161-dphy-ipconfig/fuzzer.py | fuzzers/LIFCL/161-dphy-ipconfig/fuzzer.py | from fuzzconfig import FuzzConfig
import nonrouting
import fuzzloops
import re
import os
import get_params
cfg = FuzzConfig(job="DPHYIP", device="LIFCL-40", sv="../shared/empty_40.v", tiles=["TDPHY_CORE2:DPHY_CORE"])
def bin2bin(bits):
return "0b{}".format("".join(["1" if b else "0" for b in reversed(bits)]))
... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/031-io_mode/fuzzer.py | fuzzers/LIFCL/031-io_mode/fuzzer.py | from fuzzconfig import FuzzConfig
import nonrouting
import fuzzloops
import re
configs = [
("B", "E11", # PR3A,
FuzzConfig(job="IO1D_17K", device="LIFCL-17", sv="../shared/empty_17.v", tiles=["CIB_R3C75:SYSIO_B1_DED_15K"])),
("A","F16", # PR13A
FuzzConfig(job="IO1A_17K", device="LIFCL-17", sv="... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/062-lram-config/fuzzer.py | fuzzers/LIFCL/062-lram-config/fuzzer.py | from fuzzconfig import FuzzConfig
import nonrouting
import fuzzloops
import re
configs = [
("LRAM_CORE_R18C86", "LRAM0", FuzzConfig(job="LRAM0", device="LIFCL-40", sv="../shared/empty_40.v", tiles=["CIB_R23C87:LRAM_0" ])),
("LRAM_CORE_R40C86", "LRAM1", FuzzConfig(job="LRAM1", device="LIFCL-40", sv="../shared/e... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/080-dsp-config/fuzzer.py | fuzzers/LIFCL/080-dsp-config/fuzzer.py | from fuzzconfig import FuzzConfig
import nonrouting
import fuzzloops
import re
configs = [
((37, 63), FuzzConfig(job="DSPMODER", device="LIFCL-40", sv="../shared/empty_40.v", tiles=[
"CIB_R38C62:MIB_EBR", "CIB_R38C63:DSP_R_1", "CIB_R38C64:DSP_R_2",
"CIB_R38C65:DSP_R_3", "CIB_R38C66:DSP_R_4", "CIB_R... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/110-global-structure/fuzzer.py | fuzzers/LIFCL/110-global-structure/fuzzer.py | import database
import lapie
import json
from fuzzconfig import FuzzConfig
from tiles import pos_from_name
from os import path
# name max_row max_col
configs = [
("LIFCL-40", 56, 87, "../shared/empty_40.v"),
("LIFCL-17", 29, 75, "../shared/empty_17.v"),
]
def main():
for name, max_row, max_col, sv in conf... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/130-config-ip-routing/fuzzer.py | fuzzers/LIFCL/130-config-ip-routing/fuzzer.py | from fuzzconfig import FuzzConfig
from interconnect import fuzz_interconnect
import re
configs = [
{
"cfg": FuzzConfig(job="CLKRST", device="LIFCL-40", sv="../shared/route_40.v", tiles=["CIB_R0C75:EFB_0", "CIB_R0C77:EFB_1_OSC", "CIB_R0C79:EFB_2", "CIB_R0C81:I2C_EFB_3"]),
"rc": (0, 73),
"key... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/010-lut-init/fuzzer.py | fuzzers/LIFCL/010-lut-init/fuzzer.py | from fuzzconfig import FuzzConfig
import nonrouting
import fuzzloops
import re
cfg = FuzzConfig(job="PLCINIT", device="LIFCL-40", sv="../shared/empty_40.v", tiles=["R2C2:PLC"])
def get_lut_function(init_bits):
sop_terms = []
lut_inputs = ["A", "B", "C", "D"]
for i in range(16):
if init_bits[i]:
... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/141-lram-init/fuzzer.py | fuzzers/LIFCL/141-lram-init/fuzzer.py | from fuzzconfig import FuzzConfig
import nonrouting
import fuzzloops
import re
cfg = FuzzConfig(job="LRAMINIT", device="LIFCL-40", sv="../shared/empty_40.v", tiles=["LRAM_CORE_R18C86:LRAM_INIT"])
def bin2dec(bits):
x = 0
for i, b in enumerate(bits):
if b:
x |= (1 << i)
return x
def ma... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/022-midmux/fuzzer.py | fuzzers/LIFCL/022-midmux/fuzzer.py | from fuzzconfig import FuzzConfig
from interconnect import fuzz_interconnect
configs = [
("HPFE", (28, 0), 12, "L",
FuzzConfig(job="LMIDROUTE", device="LIFCL-40", sv="../shared/route_40.v", tiles=["CIB_R28C0:LMID"])),
("HPFW", (28, 86), 12, "R",
FuzzConfig(job="RMIDROUTE", device="LIFCL-40", sv... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/155-dlldel/fuzzer.py | fuzzers/LIFCL/155-dlldel/fuzzer.py | from fuzzconfig import FuzzConfig
from interconnect import fuzz_interconnect
import nonrouting
import fuzzloops
import re
configs = [
{
"cfg": FuzzConfig(job="DLL70", device="LIFCL-40", sv="../shared/route_40.v",
tiles=["CIB_R21C0:PCLK_DLY_70_RBB_6"]),
"rc": (21, 1),
},
{
... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/070-iologic_mode/fuzzer.py | fuzzers/LIFCL/070-iologic_mode/fuzzer.py | from fuzzconfig import FuzzConfig
import nonrouting
import fuzzloops
import re
configs = [
# LIFCL-40 tiles
("IOL_B8A", "IOLOGICA", FuzzConfig(job="IOL5AMODE", device="LIFCL-40", sv="../shared/empty_40.v", tiles=["CIB_R56C8:SYSIO_B5_0", "CIB_R56C9:SYSIO_B5_1"])),
("IOL_B8B", "IOLOGICB", FuzzConfig(job="IO... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/081-dsp-routing/fuzzer.py | fuzzers/LIFCL/081-dsp-routing/fuzzer.py | from fuzzconfig import FuzzConfig
from interconnect import fuzz_interconnect
import re
configs = [
{
"cfg": FuzzConfig(job="DSPROUTE0", device="LIFCL-40", sv="../shared/route_40.v", tiles=[
"CIB_R38C63:DSP_R_1", "CIB_R38C62:MIB_EBR", "CIB_R38C64:DSP_R_2",
"CIB_R38C65:DSP_R_3... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/150-eclkroute/fuzzer.py | fuzzers/LIFCL/150-eclkroute/fuzzer.py | from fuzzconfig import FuzzConfig
from interconnect import fuzz_interconnect
import re
configs = [
{
"cfg": FuzzConfig(job="ECLK0", device="LIFCL-40", sv="../shared/route_40.v", tiles=["CIB_R56C48:ECLK_0", "CIB_R56C49:BMID_0_ECLK_1", "CIB_R56C50:BMID_1_ECLK_2", "CIB_R56C51:ECLK_3"]),
"rc": (55, 48)... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/fuzzers/LIFCL/131-config-ip/fuzzer.py | fuzzers/LIFCL/131-config-ip/fuzzer.py | from fuzzconfig import FuzzConfig
import nonrouting
import fuzzloops
import re
settings = {
"CONFIG_MULTIBOOT_CORE": [
("SOURCESEL", ["DIS", "EN"], "selects next address from input pins or fixed parameter")
],
"CONFIG_CLKRST_CORE": [
("MCJTAGGSRNDIS", ["DIS", "EN"], ""),
("MCLMMIGSR... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/timing/util/extract_route.py | timing/util/extract_route.py | import lapie
import pickle
import sys
def main():
udb = sys.argv[1]
# Get actual routed path using Tcl
nets = lapie.list_nets(udb)
routing = lapie.get_routing(udb, nets)
# (source, sink) -> pips
arc2pips = {}
# Keep track of fanout - we'll need this later!
wire_fanout = {}
for ne... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/timing/util/solve_interconnect.py | timing/util/solve_interconnect.py | import sys, pickle, math, json, os, glob
import lapie
from parse_sdf import parse_sdf_file
import database
import libpyprjoxide
import numpy as np
from scipy.sparse import csc_matrix
from scipy.sparse.linalg import lsqr
from os import path
from timing_config import *
def unescape_sdf_name(name):
e = ""
if ... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/timing/util/parse_sdf.py | timing/util/parse_sdf.py | """
Utilities for SDF file parsing to determine cell timings
"""
import sys, pickle
class SDFData:
def __init__(self):
self.cells = {}
class Delay:
def __init__(self, minv, typv, maxv):
self.minv = minv
self.typv = typv
self.maxv = maxv
class IOPath:
def __init__(self, f... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/timing/util/extract_cell_timings.py | timing/util/extract_cell_timings.py | from parse_sdf import IOPath, SetupHoldCheck
from os import path
import database
import sys, json, os, glob, pickle
def unescape_sdf_name(name):
e = ""
if name[0] == '"':
assert name[-1] == '"'
name = name[1:-1]
for c in name:
if c == '\\':
continue
e += c
re... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/timing/util/timing_config.py | timing/util/timing_config.py | # These pip classes always have zero delay
zero_delay_classes = {
"slice_internal",
"vcc_internal",
"s1:span1s -> a",
"jeclkdiv0_mid_entry",
"jeclkdiv0 -> jvpf_mid",
"f -> a",
"f -> b",
"f -> c",
"f -> d",
"q -> abcd",
"cibmuxo -> io18",
"clk -> clk_dff",
}
| python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/timing/tools/yosysify_verilog.py | timing/tools/yosysify_verilog.py | import sys
in_spec = False
with open(sys.argv[1], "r") as i:
with open(sys.argv[2], "w") as o:
for line in i:
if " specify" in line or in_spec:
if " endspecify" in line:
in_spec = False
else:
in_spec = True
continue # Yosys can't cope with the more complex features used
o.write(line)
| python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/timing/tools/pickle_sdf.py | timing/tools/pickle_sdf.py | import parse_sdf
import sys, pickle
def main():
parsed = parse_sdf.parse_sdf_file(sys.argv[1])
with open(sys.argv[2], "wb") as pickled:
pickle.dump(parsed, pickled)
if __name__ == '__main__':
main()
| python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/timing/fuzzers/LIFCL/01-dff/gen_dff.py | timing/fuzzers/LIFCL/01-dff/gen_dff.py | dffs = []
for clk in ("clk", "clkn"):
for lsr in ("lsr", "lsrn", "1'b0"):
for ce in ("ce", "cen", "1'b0"):
for d in ("d", "x ^ d"):
for prim, sr in [("FD1P3BX", "PD"), ("FD1P3DX", "CD"), ("FD1P3IX", "CD"), ("FD1P3JX", "PD")]:
i = len(dffs)
... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/timing/fuzzers/LIFCL/04-dsp/gen_dsp.py | timing/fuzzers/LIFCL/04-dsp/gen_dsp.py | import numpy as np
# (name, cost, a_width, b_with, c_width, z_width, extra_registers)
prims = [
("MULT18X18", 2, 18, 18, None, 36, ()),
("MULT18X36", 4, 18, 36, None, 54, ()),
("MULT36X36", 8, 36, 36, None, 72, ()),
("MULT9X9", 1, 9, 9, None... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/timing/fuzzers/LIFCL/06-carry/gen_carry.py | timing/fuzzers/LIFCL/06-carry/gen_carry.py | print("module top(input [1:0] A, B, C, D, output [5:0] S);")
print("wire [1:0] cy;")
for i in range(3):
print(" CCU2 #(.INIT0(\"0x1234\"), .INIT1(\"0x5678\")) SLICE_CCU_{} (".format(i))
if i > 0:
print(" .CIN(cy[{}]),".format(i-1))
print(" {},".format(", ".join([".{p}0({p}[0])".format(p=p) for p in "A... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/timing/fuzzers/LIFCL/02-ram/gen_ram.py | timing/fuzzers/LIFCL/02-ram/gen_ram.py | import random
print("module top(input [3:0] clk, ce, rst, input [7:0] d, output [7:0] q);")
data = ["d[{}]".format(i) for i in range(8)]
def data_bits(N):
return "{{{}}}".format(", ".join([random.choice(data) for i in range(N)]))
def clock_port(name):
print(" .{}(clk[{}]),".format(name, random.randint(... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/timing/fuzzers/LIFCL/05-clock/gen_clk.py | timing/fuzzers/LIFCL/05-clock/gen_clk.py | import random
# CABGA400
clk_pins = "J2 K2 K3 L5 L7 M2 V1 Y2 R5 Y5 R7 W7 T10 W10 W11 Y12 W14 T13 N19 M19 M17 L20 L16 L13 E13 E12".split(" ")
banks = "7 7 7 6 6 6 5 5 5 5 4 4 4 4 3 3 3 3 2 2 2 1 1 1 0 0".split(" ")
plls = ["PLL_LLC", "PLL_LRC", "PLL_ULC"]
pll_pins = ["CLKOP", "CLKOS", "CLKOS2", "CLKOS3", "CLKOS4", "CL... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/timing/fuzzers/LIFCL/08-io/gen_io.py | timing/fuzzers/LIFCL/08-io/gen_io.py | import random
# Some representative pins for each bank
bank_pins = {
0: ("E12", "E13", "D13", "D15", "D14", "D16"),
1: ("F13", "F16", "F18", "E20", "G14", "L13", "L16", "L20"),
2: ("N14", "M16", "N15", "M19", "N19", "P19", "P17", "R17", "U20"),
3: ("W18", "Y17", "V17", "U15", "Y15", "P13", "V14", "Y13... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/timing/fuzzers/LIFCL/03-picorv32/gen_picorv32.py | timing/fuzzers/LIFCL/03-picorv32/gen_picorv32.py | import random
print("`define SEED {}".format(random.randint(0, 0xFFFFFFFF)))
print("""
module top_large (
input clk, resetn,
output [4:0] trap,
output [4:0] mem_valid,
output [4:0] mem_instr,
input mem_ready,
output reg [7:0] mem_addr,
output [7:0] mem_wdata,
output [ 3:0] mem_wstrb,
input [31:0] ... | python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | true |
gatecat/prjoxide | https://github.com/gatecat/prjoxide/blob/30712ff988a3ea7700fa11b87ae2d77e55c7c468/timing/fuzzers/LIFCL/07-lutram/gen_lutram.py | timing/fuzzers/LIFCL/07-lutram/gen_lutram.py | print("""
module top(input clk, wre, input [3:0] wad, rad, wd, output [3:0] rd);
reg [3:0] mem[0:15];
always @(posedge clk) if(wre) mem[wad] <= wd;
assign rd = mem[rad];
endmodule
""")
| python | ISC | 30712ff988a3ea7700fa11b87ae2d77e55c7c468 | 2026-01-05T07:10:26.543741Z | false |
lyletang/Huawei_LiteOS | https://github.com/lyletang/Huawei_LiteOS/blob/87d4fb9ea485e43587e1618e31fead8a41a1ad38/client.py | client.py | # -*- coding:utf-8 -*-
import socket
BLOCK_SIZE = 1024
def send(s, filename):
print('Before Sending...')
with open(filename, 'rb') as f:
block = f.read(BLOCK_SIZE)
while block:
print('Sending...')
s.send(block)
block = f.read(BLOCK_SIZE)
print('Done Sen... | python | MIT | 87d4fb9ea485e43587e1618e31fead8a41a1ad38 | 2026-01-05T07:08:48.607958Z | false |
lyletang/Huawei_LiteOS | https://github.com/lyletang/Huawei_LiteOS/blob/87d4fb9ea485e43587e1618e31fead8a41a1ad38/server_tensorflow.py | server_tensorflow.py | # -*- coding:utf-8 -*-
import tensorflow as tf
import numpy as np
import os
import inception
import socket
import subprocess
MAX_ACCEPTED_PHOTOS = 10
bundler_command_line = 'C:/WinPython-64bit-2.7.10.3/python-2.7.10.amd64/python.exe F:/osm-bundler-pmvs2-cmvs-full-32-64/osm-bundler/osm-bundlerWin64/RunBundler.py --phot... | python | MIT | 87d4fb9ea485e43587e1618e31fead8a41a1ad38 | 2026-01-05T07:08:48.607958Z | false |
lyletang/Huawei_LiteOS | https://github.com/lyletang/Huawei_LiteOS/blob/87d4fb9ea485e43587e1618e31fead8a41a1ad38/inception.py | inception.py | ########################################################################
#
# The Inception Model v3 for TensorFlow.
#
# This is a pre-trained Deep Neural Network for classifying images.
# You provide an image or filename for a jpeg-file which will be
# loaded and input to the Inception model, which will then output
# a... | python | MIT | 87d4fb9ea485e43587e1618e31fead8a41a1ad38 | 2026-01-05T07:08:48.607958Z | false |
lyletang/Huawei_LiteOS | https://github.com/lyletang/Huawei_LiteOS/blob/87d4fb9ea485e43587e1618e31fead8a41a1ad38/inception5h.py | inception5h.py | ########################################################################
#
# The Inception Model 5h for TensorFlow.
#
# This variant of the Inception model is easier to use for DeepDream
# and other imaging techniques. This is because it allows the input
# image to be any size, and the optimized images are also prettie... | python | MIT | 87d4fb9ea485e43587e1618e31fead8a41a1ad38 | 2026-01-05T07:08:48.607958Z | false |
lyletang/Huawei_LiteOS | https://github.com/lyletang/Huawei_LiteOS/blob/87d4fb9ea485e43587e1618e31fead8a41a1ad38/translate_http_request.py | translate_http_request.py | # /usr/bin/env python
# coding=utf8
import http.client
import hashlib
import urllib.parse
import random
import json
appid = '20170107000035394'
secretKey = 'fm2Qmj34KveDrvTglZ0l'
httpClient = None
myurl = '/api/trans/vip/translate'
q = 'laptop'
fromLang = 'en'
toLang = 'zh'
salt = random.randint(32768, 65536)
sign ... | python | MIT | 87d4fb9ea485e43587e1618e31fead8a41a1ad38 | 2026-01-05T07:08:48.607958Z | false |
lyletang/Huawei_LiteOS | https://github.com/lyletang/Huawei_LiteOS/blob/87d4fb9ea485e43587e1618e31fead8a41a1ad38/dataset.py | dataset.py | ########################################################################
#
# Class for creating a data-set consisting of all files in a directory.
#
# Example usage is shown in the file knifey.py and Tutorial #09.
#
# Implemented in Python 3.5
#
########################################################################
#... | python | MIT | 87d4fb9ea485e43587e1618e31fead8a41a1ad38 | 2026-01-05T07:08:48.607958Z | false |
lyletang/Huawei_LiteOS | https://github.com/lyletang/Huawei_LiteOS/blob/87d4fb9ea485e43587e1618e31fead8a41a1ad38/labels_convert.py | labels_convert.py | # coding=utf8
import http.client
import hashlib
import urllib.parse
import random
import json
import codecs
appid, secretKey = '20170107000035394', 'fm2Qmj34KveDrvTglZ0l'
fromLang, toLang = 'en', 'zh'
translate_api_url = '/api/trans/vip/translate'
def translate_call(query_word):
httpClient = None
data = None... | python | MIT | 87d4fb9ea485e43587e1618e31fead8a41a1ad38 | 2026-01-05T07:08:48.607958Z | false |
lyletang/Huawei_LiteOS | https://github.com/lyletang/Huawei_LiteOS/blob/87d4fb9ea485e43587e1618e31fead8a41a1ad38/utils.py | utils.py | # coding=utf8
with open('inception/imagenet_synset_to_human_label_map.txt') as f:
lines = f.readlines()
for line in lines:
line = line.replace('\t', ' ')
l = line.split('\n')
l.pop()
ll = l[0].split(' ')
number = ll.pop(0)
label = ' '.join(ll)
label_list ... | python | MIT | 87d4fb9ea485e43587e1618e31fead8a41a1ad38 | 2026-01-05T07:08:48.607958Z | false |
lyletang/Huawei_LiteOS | https://github.com/lyletang/Huawei_LiteOS/blob/87d4fb9ea485e43587e1618e31fead8a41a1ad38/download.py | download.py | ########################################################################
#
# Functions for downloading and extracting data-files from the internet.
#
# Implemented in Python 3.5
#
########################################################################
#
# This file is part of the TensorFlow Tutorials available at:
#
#... | python | MIT | 87d4fb9ea485e43587e1618e31fead8a41a1ad38 | 2026-01-05T07:08:48.607958Z | false |
lyletang/Huawei_LiteOS | https://github.com/lyletang/Huawei_LiteOS/blob/87d4fb9ea485e43587e1618e31fead8a41a1ad38/server.py | server.py | # -*- coding:utf-8 -*-
import tensorflow as tf
import numpy as np
import os
import inception
import socket
def run_inference(model, image_path):
# Use the Inception model to classify the image.
pred = model.classify(image_path=image_path)
# Print the scores and names for the top-1 predictions.
model.... | python | MIT | 87d4fb9ea485e43587e1618e31fead8a41a1ad38 | 2026-01-05T07:08:48.607958Z | false |
lyletang/Huawei_LiteOS | https://github.com/lyletang/Huawei_LiteOS/blob/87d4fb9ea485e43587e1618e31fead8a41a1ad38/cache.py | cache.py | ########################################################################
#
# Cache-wrapper for a function or class.
#
# Save the result of calling a function or creating an object-instance
# to harddisk. This is used to persist the data so it can be reloaded
# very quickly and easily.
#
# Implemented in Python 3.5
#
##... | python | MIT | 87d4fb9ea485e43587e1618e31fead8a41a1ad38 | 2026-01-05T07:08:48.607958Z | false |
lyletang/Huawei_LiteOS | https://github.com/lyletang/Huawei_LiteOS/blob/87d4fb9ea485e43587e1618e31fead8a41a1ad38/osm-bundler/osm-bundlerWin64/RunCMVS.py | osm-bundler/osm-bundlerWin64/RunCMVS.py | import logging
import osmcmvs
logging.basicConfig(level=logging.INFO, format="%(message)s")
# initialize OsmCMVS manager class
manager = osmcmvs.OsmCmvs()
# initialize PMVS input from Bundler output
#manager.doBundle2PMVS()
# call PMVS
manager.doCMVS()
| python | MIT | 87d4fb9ea485e43587e1618e31fead8a41a1ad38 | 2026-01-05T07:08:48.607958Z | false |
lyletang/Huawei_LiteOS | https://github.com/lyletang/Huawei_LiteOS/blob/87d4fb9ea485e43587e1618e31fead8a41a1ad38/osm-bundler/osm-bundlerWin64/RunBundler.py | osm-bundler/osm-bundlerWin64/RunBundler.py | import logging
import osmbundler
logging.basicConfig(level=logging.INFO, format="%(message)s")
# initialize OsmBundler manager class
manager = osmbundler.OsmBundler()
manager.preparePhotos()
manager.matchFeatures()
manager.doBundleAdjustment()
# manager.openResult()
| python | MIT | 87d4fb9ea485e43587e1618e31fead8a41a1ad38 | 2026-01-05T07:08:48.607958Z | false |
lyletang/Huawei_LiteOS | https://github.com/lyletang/Huawei_LiteOS/blob/87d4fb9ea485e43587e1618e31fead8a41a1ad38/osm-bundler/osm-bundlerWin64/RunPMVS.py | osm-bundler/osm-bundlerWin64/RunPMVS.py | import logging
import osmpmvs
logging.basicConfig(level=logging.INFO, format="%(message)s")
# initialize OsmPMVS manager class
manager = osmpmvs.OsmPmvs()
# initialize PMVS input from Bundler output
manager.doBundle2PMVS()
# call PMVS
manager.doPMVS()
| python | MIT | 87d4fb9ea485e43587e1618e31fead8a41a1ad38 | 2026-01-05T07:08:48.607958Z | false |
lyletang/Huawei_LiteOS | https://github.com/lyletang/Huawei_LiteOS/blob/87d4fb9ea485e43587e1618e31fead8a41a1ad38/osm-bundler/osm-bundlerWin64/osmpmvs/__init__.py | osm-bundler/osm-bundlerWin64/osmpmvs/__init__.py | import logging
import sys, os, getopt, tempfile, subprocess, shutil
# service function: get path of an executable (.exe suffix is added if we are on Windows)
def getExecPath(dir, fileName):
if sys.platform == "win32": fileName = "%s.exe" % fileName
return os.path.join(dir, fileName)
distrPath = os.path.di... | python | MIT | 87d4fb9ea485e43587e1618e31fead8a41a1ad38 | 2026-01-05T07:08:48.607958Z | false |
lyletang/Huawei_LiteOS | https://github.com/lyletang/Huawei_LiteOS/blob/87d4fb9ea485e43587e1618e31fead8a41a1ad38/osm-bundler/osm-bundlerWin64/osmbundler/defaults.py | osm-bundler/osm-bundlerWin64/osmbundler/defaults.py |
maxPhotoDimension = 1200
matchingEngine = "bundler"
featureExtractor = "siftvlfeat"
bundlerOptions = (
"--match_table matches.init.txt\n",
"--output bundle.out\n",
"--output_all bundle_\n",
"--output_dir bundle\n",
"--variable_focal_length\n",
"--use_focal_estimate\n",
"--constrain_focal\n",
"--constrain_focal_weight... | python | MIT | 87d4fb9ea485e43587e1618e31fead8a41a1ad38 | 2026-01-05T07:08:48.607958Z | false |
lyletang/Huawei_LiteOS | https://github.com/lyletang/Huawei_LiteOS/blob/87d4fb9ea485e43587e1618e31fead8a41a1ad38/osm-bundler/osm-bundlerWin64/osmbundler/__init__.py | osm-bundler/osm-bundlerWin64/osmbundler/__init__.py | import logging
import sys, os, getopt, tempfile, subprocess
import sqlite3
from PIL import Image
from PIL.ExifTags import TAGS
import defaults
import matching
from matching import *
import features
from features import *
# a helper function to get list of photos from a directory
def getPhotosFromDirectory(photoDi... | python | MIT | 87d4fb9ea485e43587e1618e31fead8a41a1ad38 | 2026-01-05T07:08:48.607958Z | false |
lyletang/Huawei_LiteOS | https://github.com/lyletang/Huawei_LiteOS/blob/87d4fb9ea485e43587e1618e31fead8a41a1ad38/osm-bundler/osm-bundlerWin64/osmbundler/features/extractor.py | osm-bundler/osm-bundlerWin64/osmbundler/features/extractor.py |
class FeatureExtractor():
def __init__(self, distrDir):
pass
def extract(self, photo, photoInfo):
pass | python | MIT | 87d4fb9ea485e43587e1618e31fead8a41a1ad38 | 2026-01-05T07:08:48.607958Z | false |
lyletang/Huawei_LiteOS | https://github.com/lyletang/Huawei_LiteOS/blob/87d4fb9ea485e43587e1618e31fead8a41a1ad38/osm-bundler/osm-bundlerWin64/osmbundler/features/sift.py | osm-bundler/osm-bundlerWin64/osmbundler/features/sift.py | import sys, os, logging
from extractor import FeatureExtractor
class Sift(FeatureExtractor):
fileExtension = "key"
executable = ''
win32Executable = ''
linuxExecutable = ''
def __init__(self, distrDir):
if sys.platform == "win32":
self.executable = os.path.join(d... | python | MIT | 87d4fb9ea485e43587e1618e31fead8a41a1ad38 | 2026-01-05T07:08:48.607958Z | false |
lyletang/Huawei_LiteOS | https://github.com/lyletang/Huawei_LiteOS/blob/87d4fb9ea485e43587e1618e31fead8a41a1ad38/osm-bundler/osm-bundlerWin64/osmbundler/features/siftvlfeat.py | osm-bundler/osm-bundlerWin64/osmbundler/features/siftvlfeat.py | import os, subprocess, gzip, logging
from sift import Sift
className = "VlfeatSift"
class VlfeatSift(Sift):
win32Executable = "vlfeat/bin/w32/sift.exe"
linuxExecutable = "vlfeat/bin/glx/sift"
def __init__(self, distrDir):
Sift.__init__(self, distrDir)
def extract(self, photo, photoInfo)... | python | MIT | 87d4fb9ea485e43587e1618e31fead8a41a1ad38 | 2026-01-05T07:08:48.607958Z | false |
lyletang/Huawei_LiteOS | https://github.com/lyletang/Huawei_LiteOS/blob/87d4fb9ea485e43587e1618e31fead8a41a1ad38/osm-bundler/osm-bundlerWin64/osmbundler/features/__init__.py | osm-bundler/osm-bundlerWin64/osmbundler/features/__init__.py | __all__ = ["siftvlfeat", "siftlowe"] | python | MIT | 87d4fb9ea485e43587e1618e31fead8a41a1ad38 | 2026-01-05T07:08:48.607958Z | false |
lyletang/Huawei_LiteOS | https://github.com/lyletang/Huawei_LiteOS/blob/87d4fb9ea485e43587e1618e31fead8a41a1ad38/osm-bundler/osm-bundlerWin64/osmbundler/features/siftlowe.py | osm-bundler/osm-bundlerWin64/osmbundler/features/siftlowe.py | import os, subprocess, gzip
from sift import Sift
className = "LoweSift"
class LoweSift(Sift):
win32Executable = "sift-lowe/siftWin32.exe"
linuxExecutable = "sift-lowe/sift"
def __init__(self, distrDir):
Sift.__init__(self, distrDir)
def extract(self, photo, photoInfo):
phot... | python | MIT | 87d4fb9ea485e43587e1618e31fead8a41a1ad38 | 2026-01-05T07:08:48.607958Z | false |
lyletang/Huawei_LiteOS | https://github.com/lyletang/Huawei_LiteOS/blob/87d4fb9ea485e43587e1618e31fead8a41a1ad38/osm-bundler/osm-bundlerWin64/osmbundler/matching/bundler.py | osm-bundler/osm-bundlerWin64/osmbundler/matching/bundler.py | import sys,os,subprocess,logging
from engine import MatchingEngine
className = "BundlerMatching"
class BundlerMatching(MatchingEngine):
featuresListFileName = "list_features.txt"
executable = ''
def __init__(self, distrDir):
if sys.platform == "win32":
self.executable = os.path.jo... | python | MIT | 87d4fb9ea485e43587e1618e31fead8a41a1ad38 | 2026-01-05T07:08:48.607958Z | false |
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