repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ip/design_SWandHW_standalone_xbar_0/synth/design_SWandHW_standalone_xbar_0.v | 19,748 | module MODULE1 (
VAR132,
VAR39,
VAR95,
VAR113,
VAR40,
VAR44,
VAR3,
VAR98,
VAR33,
VAR117,
VAR74,
VAR55,
VAR23,
VAR28,
VAR42,
VAR89,
VAR54,
VAR69,
VAR104,
VAR101,
VAR66,
VAR105,
VAR47,
VAR29,
VAR125,
VAR123,
VAR122,
VAR67,
VAR45,
VAR38,
VAR108,
VAR14,
VAR6,
VAR17,
VAR103,
VAR12,
VAR49,
VAR88,
VAR92,
VAR27
);
input wire V... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_1.behavioral.pp.v | 2,030 | module MODULE1( VAR4, VAR7, VAR2, VAR3, VAR6, VAR1, VAR8 );
input VAR7, VAR3, VAR6, VAR4;
inout VAR1, VAR8;
output VAR2;
VAR10 VAR5(.VAR4(VAR4),.VAR7(VAR7),.VAR2(VAR2),.VAR3(VAR3),.VAR6(VAR6),.VAR1(VAR1),.VAR8(VAR8));
VAR10 VAR9(.VAR4(VAR4),.VAR7(VAR7),.VAR2(VAR2),.VAR3(VAR3),.VAR6(VAR6),.VAR1(VAR1),.VAR8(VAR8)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srsdfxtp/sky130_fd_sc_lp__srsdfxtp.symbol.v | 1,531 | module MODULE1 (
input VAR2 ,
output VAR11 ,
input VAR6 ,
input VAR5 ,
input VAR10 ,
input VAR9
);
supply1 VAR3;
supply1 VAR4 ;
supply0 VAR7 ;
supply1 VAR8 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
antmicro/yosys | techlibs/xilinx/xc7_brams_map.v | 8,476 | module \VAR33 (VAR64, VAR48, VAR50, VAR43, VAR6, VAR38, VAR34, VAR61);
parameter VAR37 = 1;
parameter VAR27 = 1;
parameter [36863:0] VAR31 = 36864'VAR10;
input VAR64;
input VAR48;
input [8:0] VAR50;
output [71:0] VAR43;
input VAR6;
input [8:0] VAR38;
input [71:0] VAR34;
input [7:0] VAR61;
wire [15:0] VAR4 = {1'b1, VAR5... | isc |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o311a/sky130_fd_sc_ms__o311a.symbol.v | 1,372 | module MODULE1 (
input VAR1,
input VAR2,
input VAR8,
input VAR7,
input VAR3,
output VAR10
);
supply1 VAR4;
supply0 VAR6;
supply1 VAR5 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
antmicro/yosys | techlibs/nexus/arith_map.v | 2,776 | module MODULE1(
module 80nexusalu (VAR28, VAR31, VAR8, VAR13, VAR29, VAR35, VAR2);
parameter VAR10 = 0;
parameter VAR26 = 0;
parameter VAR9 = 1;
parameter VAR19 = 1;
parameter VAR3 = 1;
input [VAR9-1:0] VAR28;
input [VAR19-1:0] VAR31;
output [VAR3-1:0] VAR29, VAR35;
input VAR8, VAR13;
output [VAR3-1:0] VAR2;
wire VAR32... | isc |
ShepardSiegel/ocpi | coregen/temac_axi_v5_2/example_design/pat_gen/address_swap.v | 15,676 | module MODULE1
(
input VAR14,
input VAR58,
input VAR42,
input [7:0] VAR7,
input VAR32,
input VAR33,
output VAR2,
output reg [7:0] VAR6,
output reg VAR65,
output VAR48,
input VAR61
);
parameter VAR64 = 3'b000,
VAR34 = 3'b001,
VAR39 = 3'b010,
VAR46 = 3'b011,
VAR44 = 3'b100,
VAR16 = 3'b101,
VAR27 = 3'b110;
parameter VAR10... | lgpl-3.0 |
peteg944/music-fpga | Enlightened Main Project/LowPassFilter.v | 5,117 | module MODULE1(clk, VAR4, VAR1, VAR7);
input clk;
input VAR4;
reg VAR3;
wire VAR10;
input [15:0] VAR1;
output [15:0] VAR7;
reg [2:0] state;
localparam VAR2 = 3'd0,
VAR5 = 3'd1,
VAR6 = 3'd2,
VAR9 = 3'd3,
VAR8 = 3'd4; | mit |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_33.v | 25,102 | module MODULE3 (
clk,
reset,
VAR44,
VAR1,
VAR12,
VAR93,
VAR77
);
parameter VAR208 = 18;
parameter VAR16 = 33;
parameter VAR169 = 17;
localparam VAR55 = 40;
input clk;
input reset;
input VAR44;
input VAR1;
input [VAR208-1:0] VAR12; output VAR93;
output [VAR208-1:0] VAR77;
localparam VAR22 = 18; localparam VAR115 = 36; l... | mit |
kernelpanics/Grad | Expanded-Hyperbolic-CORDIC/Verilog/Fixed-to-Floating-Point-Convertion/Barrel_shifter.v | 1,518 | module MODULE1
input wire clk,
input wire rst,
input wire VAR1,
input wire [VAR11-1:0] VAR19,
input wire [VAR13-1:0] VAR8,
input wire VAR14,
input wire VAR5,
output wire [VAR13-1:0] VAR12
);
wire [VAR13-1:0] VAR6;
VAR20 #(.VAR13(VAR13),.VAR11(VAR11)) VAR20(
.clk(clk),
.rst(rst),
.VAR1(VAR1),
.VAR2(VAR8),
.VAR9(VAR14),
... | gpl-3.0 |
8l/beri | cherilibs/trunk/AsymmetricBRAM/AsymmetricBRAM.v | 3,931 | module MODULE1(
VAR30,
VAR17,
VAR38,
VAR43,
VAR53,
VAR37,
VAR47
);
parameter VAR18 = 'VAR68 0;
parameter VAR31 = 'VAR68 0;
parameter VAR57 = 'VAR68 0;
parameter VAR39 = 'VAR68 0;
parameter VAR7 = 'VAR68 0;
parameter VAR2 = 'VAR68 0;
parameter VAR12 = 'VAR68 1;
parameter VAR21 = (VAR18 == 0) ? "VAR48":"VAR27";
input VAR... | apache-2.0 |
bluespec/Flute | builds/RV64ACIMU_Flute_verilator/Verilog_RTL/mkTop_HW_Side.v | 13,196 | module MODULE1(VAR71,
VAR80);
input VAR71;
input VAR80;
reg VAR30;
wire VAR7, VAR6;
reg [11 : 0] VAR35;
wire [11 : 0] VAR72;
wire VAR67;
wire [352 : 0] VAR22;
wire [255 : 0] VAR15;
wire VAR61,
VAR119,
VAR14,
VAR78;
wire [352 : 0] VAR85;
wire [255 : 0] VAR38;
wire [63 : 0] VAR36,
VAR87,
VAR122;
wire [7 : 0] VAR108,
VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfsbp/sky130_fd_sc_hvl__dfsbp.functional.pp.v | 2,376 | module MODULE1 (
VAR2 ,
VAR4 ,
VAR13 ,
VAR20 ,
VAR7,
VAR16 ,
VAR10 ,
VAR11 ,
VAR19
);
output VAR2 ;
output VAR4 ;
input VAR13 ;
input VAR20 ;
input VAR7;
input VAR16 ;
input VAR10 ;
input VAR11 ;
input VAR19 ;
wire VAR17 ;
wire VAR9 ;
wire VAR15 ;
wire VAR6;
not VAR3 (VAR9 , VAR7 );
VAR14 VAR5 VAR21 (VAR17 , VAR20, VAR... | apache-2.0 |
hydai/Verilog-Practice | template/Moore.v | 1,078 | module MODULE1 #(
parameter VAR2 = 2)(
output [VAR2-1:0] out,
input [VAR2-1:0] in,
input clk,
input VAR1
);
parameter VAR4 = 2'b00;
parameter VAR6 = 2'b01;
parameter VAR3 = 2'b10;
parameter VAR5 = 2'b11;
reg [VAR2-1:0] state, VAR7;
always @(posedge clk, negedge VAR1) begin
if (!VAR1) begin
state <= VAR4;
end else begin... | mit |
nanamake/my6502 | rtl/my6502mc.v | 62,790 | module MODULE1 (
input [7:0] VAR156, input [2:0] VAR119,
output reg [55:0] VAR104, output reg [7:0] VAR65,
output VAR30, output VAR187, output VAR135, output VAR120, output VAR241, output VAR168, output VAR80, output VAR23, output VAR81, output VAR176, output VAR111, output VAR101, output VAR42,
output VAR132, output V... | mit |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/afi_mux_ddrx.v | 8,373 | module MODULE1 (
clk,
VAR40,
VAR22,
VAR56,
VAR19,
VAR80,
VAR52,
VAR55,
VAR32,
VAR44,
VAR72,
VAR41,
VAR29,
VAR47,
VAR77,
VAR25,
VAR10,
VAR53,
VAR59,
VAR76,
VAR54,
VAR58,
VAR42,
VAR74,
VAR46,
VAR15,
VAR64,
VAR39,
VAR16,
VAR49,
VAR9,
VAR27,
VAR65,
VAR3,
VAR51,
VAR85,
VAR20,
VAR50,
VAR30,
VAR79,
VAR5,
VAR31,
VAR73,
VAR11,
... | gpl-3.0 |
eda-globetrotter/PicenoDecoders | andy/design/pmsm.v | 2,783 | module MODULE1 (VAR1, VAR5, VAR7, VAR10, VAR11, VAR13, VAR4, VAR8, clk, reset);
output [3:0] VAR11, VAR13, VAR4, VAR8;
input clk, reset;
input [3:0] VAR1, VAR5, VAR7, VAR10;
reg [3:0] VAR11, VAR13, VAR4, VAR8;
reg [3:0] VAR3, VAR2, VAR6, VAR9;
parameter VAR12 = 4'd15;
always @ (VAR1 or VAR5 or VAR7 or VAR10)
begin
if (... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fahcin/sky130_fd_sc_ms__fahcin.functional.pp.v | 2,782 | module MODULE1 (
VAR18,
VAR16 ,
VAR23 ,
VAR21 ,
VAR9 ,
VAR6,
VAR15,
VAR28 ,
VAR17
);
output VAR18;
output VAR16 ;
input VAR23 ;
input VAR21 ;
input VAR9 ;
input VAR6;
input VAR15;
input VAR28 ;
input VAR17 ;
wire VAR5 ;
wire VAR12 ;
wire VAR7 ;
wire VAR3 ;
wire VAR4 ;
wire VAR19 ;
wire VAR10 ;
wire VAR27;
not VAR14 (VA... | apache-2.0 |
cynngah/virtualsynthesizer | project.v | 1,953 | module MODULE1(VAR56, VAR4, VAR40,
VAR41, VAR8, VAR27, VAR50, VAR55, VAR19, VAR35, VAR20, VAR38, VAR25, VAR6, VAR9, VAR28, VAR44, VAR18, VAR33, VAR5 );
input VAR40;
input [3:0] VAR56;
input [3:0] VAR4;
output VAR41;
output VAR8;
output VAR27;
output VAR50;
output VAR55;
output [9:0] VAR19;
output [9:0] VAR35;
output [9... | mit |
PulseRain/PulseRain_rtl_lib | SRAM/M23XX1024/23xx1024/23LC1024.v | 33,782 | module MODULE1 (VAR26, VAR29, VAR13, VAR6, VAR19, VAR31, VAR7);
inout VAR26; input VAR13;
input VAR6;
inout VAR19;
inout VAR31;
input VAR7;
inout VAR29;
reg [07:00] VAR28; reg [07:00] VAR11; reg [31:00] VAR4; reg [07:00] VAR24; reg [16:00] VAR14;
wire VAR25; wire VAR17; wire VAR33; wire VAR20; wire VAR9; wire VAR12; wi... | gpl-3.0 |
SymbiFlow/yosys | techlibs/ecp5/arith_map.v | 2,589 | module MODULE1(
module 80ecp5alu (VAR36, VAR28, VAR8, VAR23, VAR4, VAR10, VAR46);
parameter VAR44 = 0;
parameter VAR12 = 0;
parameter VAR2 = 1;
parameter VAR45 = 1;
parameter VAR11 = 1;
input [VAR2-1:0] VAR36;
input [VAR45-1:0] VAR28;
output [VAR11-1:0] VAR4, VAR10;
input VAR8, VAR23;
output [VAR11-1:0] VAR46;
wire VAR... | isc |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfxbp/sky130_fd_sc_lp__sdfxbp.behavioral.pp.v | 2,509 | module MODULE1 (
VAR3 ,
VAR23 ,
VAR11 ,
VAR12 ,
VAR16 ,
VAR2 ,
VAR18,
VAR9,
VAR17 ,
VAR26
);
output VAR3 ;
output VAR23 ;
input VAR11 ;
input VAR12 ;
input VAR16 ;
input VAR2 ;
input VAR18;
input VAR9;
input VAR17 ;
input VAR26 ;
wire VAR21 ;
wire VAR24 ;
reg VAR14 ;
wire VAR8 ;
wire VAR1;
wire VAR6;
wire VAR13;
wire V... | apache-2.0 |
kDaniu/miaow | src/verilog/rtl/sgpr/sgpr_3to1_rd_port_mux.v | 1,054 | module MODULE1 (
VAR8,
VAR7,
VAR4,
VAR9,
VAR6,
VAR2,
VAR3,
VAR5,
VAR1
);
input VAR8;
input [8:0] VAR7;
input VAR4;
input [8:0] VAR9;
input VAR6;
input [8:0] VAR2;
input [127:0] VAR1;
output [127:0] VAR3;
output [8:0] VAR5;
reg [8:0] VAR5;
assign VAR3 = VAR1;
always @ (
VAR8 or
VAR4 or
VAR6 or
VAR7 or
VAR9 or
VAR2
) beg... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand3b/sky130_fd_sc_hs__nand3b.pp.blackbox.v | 1,267 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR4 ,
VAR3 ,
VAR6,
VAR2
);
output VAR5 ;
input VAR1 ;
input VAR4 ;
input VAR3 ;
input VAR6;
input VAR2;
endmodule | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_hdmi_tx_v1_00_a/hdl/verilog/axi_hdmi_tx_core.v | 18,723 | module MODULE1 (
VAR49,
VAR107,
VAR42,
VAR114,
VAR111,
VAR7,
VAR142,
VAR102,
VAR52,
VAR134,
VAR34,
VAR125,
VAR146,
VAR77,
VAR103,
VAR62,
VAR59,
VAR35,
VAR92,
VAR21,
VAR83,
VAR2,
VAR43,
VAR8,
VAR139,
VAR86,
VAR16,
VAR140,
VAR5,
VAR72,
VAR20,
VAR65,
VAR30,
VAR66,
VAR121,
VAR137,
VAR110,
VAR73,
VAR40);
parameter VAR106 = ... | mit |
olofk/oh | xilibs/ip/fifo_async_104x32/fifo_async_104x32_stub.v | 1,564 | module MODULE1(VAR10, VAR4, VAR7, VAR1, din, VAR2, VAR3, dout, VAR9, VAR5, VAR8, valid, VAR6)
;
input VAR10;
input VAR4;
input VAR7;
input VAR1;
input [103:0]din;
input VAR2;
input VAR3;
output [103:0]dout;
output VAR9;
output VAR5;
output VAR8;
output valid;
output VAR6;
endmodule | gpl-3.0 |
ElegantLin/My-CPU | project_4/project_4.srcs/sources_1/imports/Chapter11/ex_mem.v | 6,211 | module MODULE1(
input wire clk,
input wire rst,
input wire[5:0] VAR43,
input wire VAR2,
input wire[VAR4] VAR21,
input wire VAR31,
input wire[VAR33] VAR11,
input wire[VAR33] VAR20,
input wire[VAR33] VAR18,
input wire VAR13,
input wire[VAR37] VAR41,
input wire[VAR33] VAR29,
input wire[VAR33] VAR15,
input wire[VAR42] VAR2... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkbuf/sky130_fd_sc_ls__clkbuf_2.v | 2,034 | module MODULE1 (
VAR1 ,
VAR8 ,
VAR4,
VAR3,
VAR6 ,
VAR7
);
output VAR1 ;
input VAR8 ;
input VAR4;
input VAR3;
input VAR6 ;
input VAR7 ;
VAR5 VAR2 (
.VAR1(VAR1),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR1,
VAR8
);
output VAR1;
input VAR8;
supply1 VAR4;
supply0 VAR3;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o31ai/sky130_fd_sc_lp__o31ai_0.v | 2,335 | module MODULE1 (
VAR5 ,
VAR10 ,
VAR9 ,
VAR3 ,
VAR1 ,
VAR7,
VAR4,
VAR6 ,
VAR2
);
output VAR5 ;
input VAR10 ;
input VAR9 ;
input VAR3 ;
input VAR1 ;
input VAR7;
input VAR4;
input VAR6 ;
input VAR2 ;
VAR8 VAR11 (
.VAR5(VAR5),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR... | apache-2.0 |
ankitshah009/High-Radix-Adaptive-CORDIC | HCORDIC_Verilog/FSM.v | 2,807 | module MODULE1(
input [31:0] VAR9,
input [31:0] VAR46,
input [31:0] VAR39,
input [31:0] VAR26,
input reset,
input VAR34,
input [1:0] VAR18,
input VAR44,
input VAR6,
input [7:0] VAR31,
output [1:0] VAR2,
output VAR19,
output VAR37,
output [31:0] VAR16,
output [31:0] VAR29,
output [31:0] VAR45,
output [31:0] VAR40,
outpu... | apache-2.0 |
jameshegarty/rigel | platform/camera1x/vsrc/fifo_64w_64r_512d.v | 13,839 | module MODULE1(
rst,
VAR170,
VAR320,
din,
VAR19,
VAR32,
dout,
VAR418,
VAR219,
VAR426,
VAR164
);
input rst;
input VAR170;
input VAR320;
input [63 : 0] din;
input VAR19;
input VAR32;
output [63 : 0] dout;
output VAR418;
output VAR219;
output [8 : 0] VAR426;
output [8 : 0] VAR164;
VAR21 #(
.VAR318(0),
.VAR311(0),
.VAR114(... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh.symbol.v | 1,424 | module MODULE1 (
input VAR3,
output VAR5
);
supply1 VAR2 ;
supply0 VAR1 ;
supply1 VAR7;
supply1 VAR6 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
olajep/oh | src/mio/hdl/mrx_fifo.v | 5,523 | module MODULE1 # ( parameter VAR33 = 104, parameter VAR47 = 32, parameter VAR37 = 16, parameter VAR46 = "VAR59" )
( input clk, input VAR50, input VAR25, input [4:0] VAR8, input VAR15, input [VAR47-1:0] VAR18, input [1:0] VAR10, input VAR2, input [7:0] VAR24, input [63:0] VAR38, output VAR40,
input VAR36,
output VAR52, ... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffnrnq/gf180mcu_fd_sc_mcu9t5v0__dffnrnq_2.behavioral.pp.v | 3,755 | module MODULE1( VAR5, VAR8, VAR20, VAR19, VAR30, VAR29 );
input VAR5, VAR8, VAR20;
inout VAR30, VAR29;
output VAR19;
reg VAR7;
VAR17 VAR26(.VAR5(VAR5),.VAR8(VAR8),.VAR20(VAR20),.VAR19(VAR19),.VAR30(VAR30),.VAR29(VAR29),.VAR7(VAR7));
VAR17 VAR28(.VAR5(VAR5),.VAR8(VAR8),.VAR20(VAR20),.VAR19(VAR19),.VAR30(VAR30),.VAR29(VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor2b/sky130_fd_sc_hd__nor2b_2.v | 2,173 | module MODULE2 (
VAR6 ,
VAR2 ,
VAR9 ,
VAR3,
VAR7,
VAR1 ,
VAR5
);
output VAR6 ;
input VAR2 ;
input VAR9 ;
input VAR3;
input VAR7;
input VAR1 ;
input VAR5 ;
VAR8 VAR4 (
.VAR6(VAR6),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR6 ,
VAR2 ,
VAR9
);
output VAR6... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o311a/sky130_fd_sc_ls__o311a.pp.blackbox.v | 1,406 | module MODULE1 (
VAR2 ,
VAR7 ,
VAR8 ,
VAR9 ,
VAR10 ,
VAR6 ,
VAR1,
VAR4,
VAR3 ,
VAR5
);
output VAR2 ;
input VAR7 ;
input VAR8 ;
input VAR9 ;
input VAR10 ;
input VAR6 ;
input VAR1;
input VAR4;
input VAR3 ;
input VAR5 ;
endmodule | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/db/GDA_St_N8_M8_P1_syn.v | 1,696 | module MODULE1 ( VAR50, VAR46, VAR26 );
input [7:0] VAR50;
input [7:0] VAR46;
output [8:0] VAR26;
wire VAR16, VAR57, VAR42, VAR47, VAR11, VAR29, VAR54, VAR5, VAR12, VAR15, VAR6, VAR56, VAR30;
VAR18 VAR48 ( .VAR13(VAR46[6]), .VAR39(VAR50[6]), .VAR23(VAR30) );
VAR53 VAR8 ( .VAR33(VAR50[2]), .VAR36(VAR46[2]), .VAR2(VAR5),... | gpl-3.0 |
yansyaf/cmake-verilog-vhdl-fpga-template | src/model/fifo.v | 2,785 | module MODULE1 (
clk,
VAR10,
din,
VAR8,
VAR6,
dout,
VAR2,
VAR9);
input clk;
input VAR10;
input [31:0] din;
input VAR6;
input VAR8;
output [31:0] dout;
output VAR2;
output VAR9;
parameter VAR1 = 1024; parameter VAR5 = 10'b1111111111;
reg VAR2;
reg VAR9;
reg [31:0] dout;
reg [(VAR1-1):0] VAR4;
reg [(VAR1-1):0] head;
reg ... | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_23.v | 17,021 | module MODULE3 (
clk,
reset,
VAR3,
VAR43,
VAR68,
VAR98,
VAR87
);
parameter VAR47 = 18;
parameter VAR122 = 23;
parameter VAR112 = 12;
localparam VAR26 = 24;
input clk;
input reset;
input VAR3;
input VAR43;
input [VAR47-1:0] VAR68; output VAR98;
output [VAR47-1:0] VAR87;
localparam VAR2 = 18; localparam VAR69 = 36; local... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or4/sky130_fd_sc_ms__or4.behavioral.pp.v | 1,828 | module MODULE1 (
VAR12 ,
VAR10 ,
VAR7 ,
VAR5 ,
VAR6 ,
VAR15,
VAR2,
VAR1 ,
VAR8
);
output VAR12 ;
input VAR10 ;
input VAR7 ;
input VAR5 ;
input VAR6 ;
input VAR15;
input VAR2;
input VAR1 ;
input VAR8 ;
wire VAR13 ;
wire VAR4;
or VAR14 (VAR13 , VAR6, VAR5, VAR7, VAR10 );
VAR3 VAR9 (VAR4, VAR13, VAR15, VAR2);
buf VAR11 (V... | apache-2.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_dc_tag.v | 5,373 | module MODULE1(
clk, rst,
VAR1, VAR10, VAR8,
addr, en, VAR15, VAR19, VAR16, VAR3
);
parameter VAR2 = VAR5;
parameter VAR9 = VAR13;
input clk;
input rst;
input [VAR9-1:0] addr;
input en;
input VAR15;
input [VAR2-1:0] VAR19;
output VAR16;
output [VAR2-2:0] VAR3;
input VAR1;
input [VAR17 - 1:0] VAR8;
output VAR10;
assign ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or4bb/sky130_fd_sc_ms__or4bb_1.v | 2,314 | module MODULE2 (
VAR3 ,
VAR1 ,
VAR11 ,
VAR10 ,
VAR9 ,
VAR5,
VAR6,
VAR8 ,
VAR2
);
output VAR3 ;
input VAR1 ;
input VAR11 ;
input VAR10 ;
input VAR9 ;
input VAR5;
input VAR6;
input VAR8 ;
input VAR2 ;
VAR4 VAR7 (
.VAR3(VAR3),
.VAR1(VAR1),
.VAR11(VAR11),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR8(VAR8),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and3b/sky130_fd_sc_ls__and3b.behavioral.v | 1,477 | module MODULE1 (
VAR8 ,
VAR12,
VAR4 ,
VAR3
);
output VAR8 ;
input VAR12;
input VAR4 ;
input VAR3 ;
supply1 VAR11;
supply0 VAR1;
supply1 VAR9 ;
supply0 VAR6 ;
wire VAR13 ;
wire VAR10;
not VAR7 (VAR13 , VAR12 );
and VAR2 (VAR10, VAR3, VAR13, VAR4 );
buf VAR5 (VAR8 , VAR10 );
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/pll.v | 4,224 | module MODULE1 (
address,
VAR2,
clk,
read,
VAR8,
write,
VAR16,
VAR10,
VAR6,
VAR7,
VAR13
)
;
output VAR10;
output VAR6;
output [ 15: 0] VAR7;
output VAR13;
input [ 2: 0] address;
input VAR2;
input clk;
input read;
input VAR8;
input write;
input [ 15: 0] VAR16;
wire VAR15;
wire VAR14;
wire VAR10;
wire VAR6;
wire VAR18;
w... | mit |
FPGA1988/udp_ip_stack | Network/udp_ip_core/trunk/ic/digital/rtl/eth_tri_mode/TECH/xilinx/CLK_SWITCH.v | 3,664 | module MODULE1 (
input VAR8,
input VAR1,
input VAR9 ,
output VAR3
);
VAR2 VAR10 (
.VAR7 (VAR3 ),
.VAR4 (VAR8 ),
.VAR5 (VAR1 ),
.VAR6 (VAR9 ));
endmodule | apache-2.0 |
AmeerAbdelhadi/2D-Binary-Content-Addressable-Memory-BCAM | mwram_m20k.v | 9,117 | module MODULE1
localparam VAR25 = 14-VAR48(VAR52); localparam VAR5 = 14-VAR48(VAR13);
VAR27 #( .VAR28 ("VAR12" ),
.VAR44 ("VAR6" ),
.VAR59 ("VAR47" ),
.VAR24 ("VAR47" ),
.VAR40 ("VAR47" ),
.VAR49 ("VAR36 VAR50" ),
.VAR4 ("VAR27" ),
.VAR31 (2**VAR25 ),
.VAR11 (2**VAR5 ),
.VAR1 ("VAR42" ),
.VAR22 ("VAR12" ),
.VAR32 ("VAR... | bsd-3-clause |
Digilent/vivado-library | ip/Pmods/PmodSF3_v1_0/src/PmodSF3.v | 10,915 | module MODULE1
(VAR11,
VAR83,
VAR36,
VAR158,
VAR123,
VAR170,
VAR54,
VAR152,
VAR192,
VAR81,
VAR194,
VAR68,
VAR166,
VAR97,
VAR175,
VAR5,
VAR111,
VAR16,
VAR67,
VAR4,
VAR73,
VAR102,
VAR105,
VAR141,
VAR144,
VAR188,
VAR193,
VAR136,
VAR157,
VAR96,
VAR165,
VAR51,
VAR82,
VAR69,
VAR30,
VAR86,
VAR138,
VAR119,
VAR75,
VAR18,
VAR13,... | mit |
scalable-networks/ext | uhd/fpga/usrp2/models/gpmc_model_async.v | 3,080 | module MODULE1
(output VAR8, inout [15:0] VAR10, output reg [10:1] VAR2, output reg [1:0] VAR4,
output reg VAR5, output reg VAR1, output reg VAR7,
output reg VAR3, output reg VAR9 );
assign VAR8 = 0;
reg [15:0] VAR6;
assign VAR10 = VAR6;
begin
begin
end
begin
end
begin | gpl-2.0 |
bluespec/Flute | src_SSITH_P2/Verilog_RTL/mkTV_Xactor.v | 3,905 | module MODULE1(VAR11,
VAR31,
VAR21,
VAR18,
VAR24,
VAR12,
VAR7,
VAR29,
VAR20,
VAR5,
VAR9);
input VAR11;
input VAR31;
input [607 : 0] VAR21;
input VAR18;
output VAR24;
output VAR12;
output [607 : 0] VAR7;
output [75 : 0] VAR29;
output [75 : 0] VAR20;
output VAR5;
input VAR9;
wire [607 : 0] VAR7;
wire [75 : 0] VAR20, VAR2... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nor3/gf180mcu_fd_sc_mcu9t5v0__nor3_1.functional.pp.v | 1,235 | module MODULE1( VAR3, VAR8, VAR12, VAR4, VAR9, VAR6 );
input VAR4, VAR12, VAR3;
inout VAR9, VAR6;
output VAR8;
wire VAR11;
not VAR7( VAR11, VAR4 );
wire VAR5;
not VAR1( VAR5, VAR12 );
wire VAR2;
not VAR13( VAR2, VAR3 );
and VAR10( VAR8, VAR11, VAR5, VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o21ba/sky130_fd_sc_ms__o21ba.pp.blackbox.v | 1,390 | module MODULE1 (
VAR7 ,
VAR5 ,
VAR4 ,
VAR1,
VAR8,
VAR6,
VAR2 ,
VAR3
);
output VAR7 ;
input VAR5 ;
input VAR4 ;
input VAR1;
input VAR8;
input VAR6;
input VAR2 ;
input VAR3 ;
endmodule | apache-2.0 |
m-labs/milkymist | cores/monitor/rtl/monitor.v | 1,917 | module MODULE1(
input VAR6,
input VAR8,
input VAR3,
input [31:0] VAR2,
output reg [31:0] VAR12,
input [31:0] VAR5,
input [3:0] VAR10,
input VAR7,
input VAR1,
output reg VAR11,
input VAR9
);
reg [31:0] VAR4[0:2047]; | lgpl-3.0 |
hydai/Verilog-Practice | HardwareLab/Upload/101062124_戴宏穎_Lab8/Lab8.v | 1,274 | module MODULE1(VAR41, VAR37, VAR8, VAR38, VAR7, VAR4, VAR45, VAR24, clk, VAR20, VAR31, VAR22, VAR2);
input clk, VAR24;
output [3:0] VAR20;
output [8:0] VAR31;
output [3:0] VAR22;
input [3:0] VAR2;
output VAR41, VAR37, VAR8, VAR38, VAR7, VAR4;
output [7:0] VAR45;
wire VAR40, VAR34, VAR32, VAR43, VAR14;
wire [15:0] VAR30... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/bufinv/sky130_fd_sc_ms__bufinv.pp.symbol.v | 1,272 | module MODULE1 (
input VAR2 ,
output VAR1 ,
input VAR6 ,
input VAR5,
input VAR3,
input VAR4
);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_2.behavioral.pp.v | 3,700 | module MODULE1( VAR15, VAR5, VAR24, VAR25, VAR27, VAR19 );
input VAR15, VAR5, VAR24;
inout VAR27, VAR19;
output VAR25;
reg VAR12;
VAR33 VAR3(.VAR15(VAR15),.VAR5(VAR5),.VAR24(VAR24),.VAR25(VAR25),.VAR27(VAR27),.VAR19(VAR19),.VAR12(VAR12));
VAR33 VAR7(.VAR15(VAR15),.VAR5(VAR5),.VAR24(VAR24),.VAR25(VAR25),.VAR27(VAR27),.V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/mux2/sky130_fd_sc_hs__mux2_1.v | 2,060 | module MODULE1 (
VAR8 ,
VAR1 ,
VAR5 ,
VAR7 ,
VAR6,
VAR3
);
output VAR8 ;
input VAR1 ;
input VAR5 ;
input VAR7 ;
input VAR6;
input VAR3;
VAR2 VAR4 (
.VAR8(VAR8),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR8 ,
VAR1,
VAR5,
VAR7
);
output VAR8 ;
input VAR1;
input VAR5;
... | apache-2.0 |
GSejas/Karatsuba_FPU | Resultados/FPSUB/FPADDFPSUB_Pipelined/FPADDFPSUB_Pipelined.srcs/sources_1/imports/Karatsuba_FPU/Pipeline_FPADD_sourcefiles/FSM_input_enable.v | 3,019 | module MODULE1(
input wire clk,
input wire rst,
input wire VAR11,
output reg VAR7,
output wire VAR13,
output reg VAR5
);
parameter [3:0] VAR9 = 3'd0,
VAR8 = 3'd1,
VAR12 = 3'd2,
VAR14 = 3'd3,
VAR4 = 3'd4,
VAR3= 3'd5,
VAR2 = 3'd6,
VAR10 = 3'd7;
reg [2:0] VAR6, VAR1;
always @(posedge clk, posedge rst)
if(rst)
VAR6 <= VAR9... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/bw_io_ddr_rptr_c.v | 6,235 | module MODULE1(VAR86 ,VAR27 ,VAR80 ,VAR13 ,VAR79 ,VAR39 ,VAR50
,VAR93 ,VAR46 ,VAR84 ,VAR98 ,VAR56 ,VAR4 ,VAR36 ,VAR76 ,VAR90 ,VAR24 ,
VAR30 ,VAR88 ,VAR6 ,VAR61 ,VAR64 ,VAR21 ,VAR29 ,VAR52 ,VAR87 ,VAR16 ,VAR41 ,
VAR89 ,VAR23 ,VAR26 ,VAR74 ,VAR5 ,VAR19 ,VAR55 ,VAR8 ,VAR42 ,VAR20 ,VAR3
,VAR25 ,VAR57 ,VAR54 ,VAR58 ,VAR15 ,... | gpl-2.0 |
AnAtomInTheUniverse/578_project_col_panic | final_verilog/src/vcr_vc_alloc_wf.v | 14,086 | module MODULE1
(clk, reset, VAR63, VAR52, VAR28, VAR78,
VAR43, VAR92, VAR71, VAR76, VAR55,
VAR56);
parameter VAR21 = 2;
parameter VAR46 = 2;
localparam VAR19 = VAR21 * VAR46;
parameter VAR6 = 1;
localparam VAR10 = VAR19 * VAR6;
parameter VAR74 = 5;
parameter VAR15 = VAR61;
parameter VAR47 = VAR51;
input clk;
input rese... | gpl-2.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_amphy/alt_mem_ddrx_timing_param.v | 59,342 | module MODULE1 #
( parameter
VAR154 = 2,
VAR114 = "VAR54",
VAR49 = 3,
VAR38 = 5,
VAR26 = 4, VAR32 = 3, VAR22 = 4, VAR50 = 4, VAR100 = 6, VAR146 = 8, VAR156 = 13, VAR107 = 4, VAR33 = 4, VAR17 = 4, VAR61 = 4, VAR105 = 4, VAR64 = 5, VAR48 = 6, VAR131 = 3, VAR165 = 3, VAR30 = 10, VAR63 = 4, VAR124 = 16,
VAR144 = 4,
VAR73 =... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o32ai/sky130_fd_sc_hs__o32ai.functional.pp.v | 2,092 | module MODULE1 (
VAR3,
VAR14,
VAR16 ,
VAR8 ,
VAR18 ,
VAR9 ,
VAR12 ,
VAR10
);
input VAR3;
input VAR14;
output VAR16 ;
input VAR8 ;
input VAR18 ;
input VAR9 ;
input VAR12 ;
input VAR10 ;
wire VAR12 VAR7 ;
wire VAR12 VAR15 ;
wire VAR13 ;
wire VAR11;
nor VAR4 (VAR7 , VAR9, VAR8, VAR18 );
nor VAR1 (VAR15 , VAR12, VAR10 );
o... | apache-2.0 |
efabless/openlane | designs/des/src/3des.v | 65,728 | module MODULE9(VAR106, VAR88, VAR26, VAR71, clk);
output [63:0] VAR106;
input [63:0] VAR88;
input [55:0] VAR26;
input VAR71;
input clk;
wire [1:64] VAR7, VAR24;
reg [63:0] VAR111;
reg [55:0] VAR14;
reg [63:0] VAR106;
reg [1:32] VAR51, VAR48, VAR8, VAR108, VAR94, VAR38, VAR28, VAR114, VAR85, VAR89, VAR78, VAR118, VAR2, ... | apache-2.0 |
hhuang25/uwaterloo_ece224 | Lab1Good/pio_response.v | 2,101 | module MODULE1 (
address,
VAR4,
clk,
VAR6,
VAR2,
VAR1,
VAR9,
VAR5
)
;
output VAR9;
output VAR5;
input [ 1: 0] address;
input VAR4;
input clk;
input VAR6;
input VAR2;
input VAR1;
wire VAR8;
reg VAR7;
wire VAR9;
wire VAR3;
wire VAR5;
assign VAR8 = 1;
assign VAR3 = {1 {(address == 0)}} & VAR7;
always @(posedge clk or nege... | mit |
toyoshim/tvcl | SerialTransmitter.v | 3,662 | module MODULE1(
VAR10,
VAR16,
VAR9,
VAR18,
VAR23,
VAR22,
VAR8);
input VAR10;
input VAR16;
input [7:0] VAR9;
input VAR18;
output VAR23;
output VAR22;
output VAR8;
reg VAR14;
reg [1:0] VAR12;
reg [3:0] VAR4;
reg [7:0] VAR3;
wire VAR24;
wire VAR1;
localparam VAR13 = 4'b0000;
localparam VAR6 = 4'b0001;
localparam VAR20 = 4... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/einvp/sky130_fd_sc_hdll__einvp_2.v | 2,146 | module MODULE2 (
VAR6 ,
VAR9 ,
VAR1 ,
VAR8,
VAR3,
VAR7 ,
VAR5
);
output VAR6 ;
input VAR9 ;
input VAR1 ;
input VAR8;
input VAR3;
input VAR7 ;
input VAR5 ;
VAR2 VAR4 (
.VAR6(VAR6),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR6 ,
VAR9 ,
VAR1
);
output VAR6... | apache-2.0 |
HackerFoo/poprc | vlgen/primitives.v | 8,512 | module MODULE6 #( \
parameter VAR36 = VAR44, \
parameter VAR19 = VAR42 \
)( \
input(VAR21, VAR36, 0), \
output(VAR21, VAR19, 0) \
); \
assign VAR1 = VAR48 VAR46; \
endmodule
module MODULE6 #( \
parameter VAR36 = VAR44, \
parameter VAR12 = VAR44, \
parameter VAR19 = VAR42 \
)( \
input(VAR21, VAR36, 0), \
input(VAR21, VA... | gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_KOA_2_cycles/integracion_fisica/front_end/source/subRecursiveKOA_1c.v | 4,987 | module MODULE1
(
input wire [VAR1-1:0] VAR32,
input wire [VAR1-1:0] VAR8,
output wire [2*VAR1-1:0] VAR20
);
localparam integer VAR31 = VAR31;
generate
if (VAR1 <= VAR31) begin : VAR27
VAR29 #(.VAR1(VAR1))
VAR13 (
.VAR32(VAR32),
.VAR8(VAR8),
.VAR20(VAR20)
);
end else begin : VAR11
reg [2*VAR1-1:0] VAR9;
wire [1:0] VAR16... | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/ad_dds_sine.v | 6,899 | module MODULE1 (
clk,
VAR15,
VAR11,
VAR1,
VAR31);
parameter VAR17 = 16;
localparam VAR35 = VAR17 - 1;
input clk;
input [ 15:0] VAR15;
output [ 15:0] VAR11;
input [ VAR35:0] VAR1;
output [ VAR35:0] VAR31;
reg [ 33:0] VAR3 = 'd0;
reg [ 33:0] VAR16 = 'd0;
reg [ 15:0] VAR33 = 'd0;
reg [ VAR35:0] VAR5 = 'd0;
reg [ 18:0] VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and4b/sky130_fd_sc_hd__and4b_1.v | 2,300 | module MODULE2 (
VAR9 ,
VAR1 ,
VAR11 ,
VAR5 ,
VAR2 ,
VAR7,
VAR10,
VAR8 ,
VAR3
);
output VAR9 ;
input VAR1 ;
input VAR11 ;
input VAR5 ;
input VAR2 ;
input VAR7;
input VAR10;
input VAR8 ;
input VAR3 ;
VAR6 VAR4 (
.VAR9(VAR9),
.VAR1(VAR1),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR8(VAR8),
.... | apache-2.0 |
Gilberto-Lopez/Arquitectura-Computadoras | CUnit.v | 5,059 | module MODULE1(
input wire clk,
input wire reset,
output reg VAR11,
output reg [31:0] VAR31,
input wire [31:0] VAR2,
output reg VAR8,
output reg [9:0] VAR12,
input wire VAR29,
input wire VAR10,
input wire VAR34,
input wire [31:0] VAR33,
output reg [31:0] VAR3,
output reg [31:0] VAR14,
output reg [3:0] VAR22
);
localpar... | lgpl-3.0 |
eda-globetrotter/MarcheProcessor | processor/spare/build2/sipo.v | 5,795 | module MODULE1(VAR1, VAR7, VAR3, VAR13, VAR2, clk);
output [7:0] VAR1;
output VAR7;
input VAR3;
input clk;
input VAR2;
input VAR13;
reg VAR7; reg [7:0] VAR1; reg [7:0] VAR12; reg VAR6; reg VAR9; reg VAR4; reg VAR10; reg VAR8; reg VAR14; reg VAR5; reg VAR11;
always @(~VAR2)
begin
VAR7<=1'd0;
VAR1<=8'd0;
VAR12<=8'd0;
VAR... | mit |
silent-observer/RCPU | CPU/source/rcpu.v | 7,840 | module MODULE1 ( input wire rst, input wire clk, input wire irq, output wire VAR110, input wire VAR113, input wire[VAR43-1:0] VAR130, input wire[VAR86-1:0] VAR109, input wire[VAR86-1:0] VAR15, output reg[VAR43-1:0] VAR34, input wire[VAR86-1:0] VAR122, output reg[VAR86-1:0] VAR20, output wire VAR69, output wire VAR6, ou... | mit |
smithe0/GestureControlInterface | DE2Component_FLASH/niosII_system/synthesis/submodules/niosII_system_green_leds.v | 2,262 | module MODULE1 (
address,
VAR7,
clk,
VAR5,
VAR4,
VAR3,
VAR2,
VAR8
)
;
output [ 7: 0] VAR2;
output [ 31: 0] VAR8;
input [ 1: 0] address;
input VAR7;
input clk;
input VAR5;
input VAR4;
input [ 31: 0] VAR3;
wire VAR1;
reg [ 7: 0] VAR6;
wire [ 7: 0] VAR2;
wire [ 7: 0] VAR9;
wire [ 31: 0] VAR8;
assign VAR1 = 1;
assign VAR9 ... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/FPU_Interface/fpaddsub_arch2/RegisterAdd.v | 1,098 | module MODULE1
(
input wire clk, input wire rst, input wire VAR4, input wire [VAR3-1:0] VAR2, output reg [VAR3-1:0] VAR1 );
always @(posedge clk, posedge rst)
if(rst)
VAR1 <= 0;
else if(VAR4)
VAR1 <= VAR2;
else
VAR1 <= VAR1;
endmodule
module MODULE2
(
input wire clk, input wire rst, input wire [VAR3-1:0] VAR2, output r... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdlclkp/sky130_fd_sc_ls__sdlclkp.symbol.v | 1,338 | module MODULE1 (
input VAR2 ,
input VAR8 ,
input VAR3,
output VAR4
);
supply1 VAR6;
supply0 VAR1;
supply1 VAR5 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
karatekid/ultrasonic-fountain | hardware/src/message_rom.v | 1,193 | module MODULE1 (
input clk,
input [3:0] addr,
output [7:0] VAR2
);
wire [7:0] VAR12 [13:0];
assign VAR12[0] = "VAR1";
assign VAR12[1] = "VAR3";
assign VAR12[2] = "VAR7";
assign VAR12[3] = "VAR7";
assign VAR12[4] = "VAR4";
assign VAR12[5] = " ";
assign VAR12[6] = "VAR11";
assign VAR12[7] = "VAR4";
assign VAR12[8] = "VAR... | gpl-3.0 |
kernelpanics/Grad | CORDIC-Exponential-Function/Verilog/Multiplier/Adder_Round.v | 1,306 | module MODULE1
input wire clk,
input wire rst,
input wire VAR9,
input wire [VAR10-1:0] VAR6,
input wire [VAR10-1:0] VAR17,
output wire [VAR10-1:0] VAR5,
output wire VAR3
);
wire [VAR10:0] VAR1;
VAR11 #(.VAR7(VAR10)) VAR8 (
.VAR6(VAR6),
.VAR17(VAR17),
.VAR12(VAR1)
);
VAR2 #(.VAR7(VAR10)) VAR4(
.clk (clk),
.rst (rst),
.V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o2bb2a/sky130_fd_sc_hd__o2bb2a_1.v | 2,398 | module MODULE2 (
VAR11 ,
VAR3,
VAR1,
VAR6 ,
VAR9 ,
VAR5,
VAR2,
VAR8 ,
VAR7
);
output VAR11 ;
input VAR3;
input VAR1;
input VAR6 ;
input VAR9 ;
input VAR5;
input VAR2;
input VAR8 ;
input VAR7 ;
VAR10 VAR4 (
.VAR11(VAR11),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR7(VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fahcon/sky130_fd_sc_ms__fahcon.functional.pp.v | 2,730 | module MODULE1 (
VAR2,
VAR20 ,
VAR9 ,
VAR19 ,
VAR24 ,
VAR13 ,
VAR1 ,
VAR10 ,
VAR14
);
output VAR2;
output VAR20 ;
input VAR9 ;
input VAR19 ;
input VAR24 ;
input VAR13 ;
input VAR1 ;
input VAR10 ;
input VAR14 ;
wire VAR11 ;
wire VAR23 ;
wire VAR17 ;
wire VAR25 ;
wire VAR5 ;
wire VAR12 ;
wire VAR26;
xor VAR6 (VAR11 , VAR... | apache-2.0 |
alexforencich/xfcp | lib/eth/rtl/arp_eth_rx.v | 11,539 | module MODULE1 #
(
parameter VAR31 = 8,
parameter VAR9 = (VAR31>8),
parameter VAR21 = (VAR31/8)
)
(
input wire clk,
input wire rst,
input wire VAR8,
output wire VAR25,
input wire [47:0] VAR24,
input wire [47:0] VAR26,
input wire [15:0] VAR18,
input wire [VAR31-1:0] VAR14,
input wire [VAR21-1:0] VAR33,
input wire VAR34,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand3b/sky130_fd_sc_ls__nand3b_2.v | 2,229 | module MODULE2 (
VAR2 ,
VAR9 ,
VAR6 ,
VAR1 ,
VAR4,
VAR10,
VAR7 ,
VAR3
);
output VAR2 ;
input VAR9 ;
input VAR6 ;
input VAR1 ;
input VAR4;
input VAR10;
input VAR7 ;
input VAR3 ;
VAR8 VAR5 (
.VAR2(VAR2),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR3(VAR3)
);
endmodule
module MODULE... | apache-2.0 |
ptracton/vscale_soc | library/memory/ram/ram_axi4_lite.v | 1,667 | module MODULE1 ( ) ;
input wire VAR6;
input wire VAR11; input wire [14:0] VAR12;
input wire VAR9;
input wire [3:0] VAR8;
input wire [1:0] VAR13;
input wire [31:0] VAR4;
input wire VAR2;
output reg [31:0] VAR10;
output reg VAR3;
output reg VAR7;
reg [31:0] memory [0:4095];
reg [14:0] addr;
reg VAR1;
always @(posedge VAR... | mit |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_fpaddsub_arch2/integracion_fisica/front_end/db/SINGLE/LZD_syn.v | 5,816 | module MODULE3 ( VAR52, VAR80 );
input [25:0] VAR52;
output [4:0] VAR80;
wire VAR23, VAR138, VAR115, VAR68, VAR14, VAR46, VAR31, VAR122, VAR158, VAR137, VAR142, VAR149, VAR118, VAR156, VAR25, VAR128,
VAR157, VAR47, VAR96, VAR104, VAR43, VAR148, VAR51, VAR74, VAR44, VAR22, VAR160, VAR54, VAR66, VAR85,
VAR40, VAR106, VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv.functional.pp.v | 1,873 | module MODULE1 (
VAR12 ,
VAR11 ,
VAR6 ,
VAR8 ,
VAR13,
VAR9 ,
VAR3
);
output VAR12 ;
input VAR11 ;
input VAR6 ;
input VAR8 ;
input VAR13;
input VAR9 ;
input VAR3 ;
wire VAR7;
wire VAR1 ;
VAR10 VAR5 (VAR7, VAR11, VAR6, VAR8 );
buf VAR4 (VAR1 , VAR7 );
VAR10 VAR2 (VAR12 , VAR1, VAR13, VAR8);
endmodule | apache-2.0 |
SymbiFlow/nextpnr | ice40/benchmark/spimemio.v | 13,474 | module MODULE1 (
input clk, VAR69,
input valid,
output ready,
input [23:0] addr,
output reg [31:0] VAR1,
output VAR29,
output VAR87,
output VAR45,
output VAR37,
output VAR13,
output VAR46,
output VAR32,
output VAR83,
output VAR50,
output VAR20,
input VAR8,
input VAR56,
input VAR6,
input VAR31,
input [3:0] VAR85,
input ... | isc |
hoangt/NOCulator | hring/hw/buffered/src/vcr_routing_logic.v | 8,175 | module MODULE1
(clk, reset, VAR35, VAR34, VAR38, VAR31, VAR36);
parameter VAR14 = 2;
parameter VAR28 = 4;
localparam VAR24 = VAR1(VAR28);
parameter VAR23 = 2;
localparam VAR13 = VAR23 * VAR24;
parameter VAR12 = 1;
localparam VAR19 = VAR1(VAR12);
localparam VAR37 = VAR13 + VAR19;
parameter VAR4 = VAR6;
localparam VAR11
... | mit |
xuwenyihust/MapReduce_NoC | RTL/sram.v | 6,234 | module MODULE1(clk, rst, address, VAR10, VAR1, VAR3);
parameter VAR9 = 36;
parameter VAR8 = 128;
input clk;
input rst;
input [31:0] address;
input VAR1;
output VAR3;
assign VAR3 = VAR1;
wire [5:0] VAR6;
assign VAR6 = address[9:4];
output [VAR9-1:0] VAR10;
reg [VAR9-1:0] VAR2;
reg VAR4;
assign VAR10 = (VAR1)?VAR2:36'VAR... | mit |
kielfriedt/ece472 | lab2/add16_LA.v | 1,300 | module MODULE1(VAR4, VAR13, VAR3, sum, VAR5, VAR17, VAR11);
input [15:0] VAR4, VAR13;
input VAR3;
output [15:0] sum;
output VAR5;
output VAR17, VAR11;
wire [2:0] VAR14;
wire [3:0] VAR15, VAR6;
wire [3:0] VAR2;
VAR7 VAR10(VAR4[3:0], VAR13[3:0], VAR3, sum[3:0], VAR2[0], VAR15[0], VAR6[0]);
VAR7 VAR9(VAR4[7:4], VAR13[7:4]... | gpl-3.0 |
zaqwes8811/hdl-fpga | ip-cores/rtl_vlog/mem_lib.v | 1,407 | module MODULE1(clk, VAR1, VAR2, VAR5);
parameter VAR4 = 8;
parameter VAR3 = 8;
input clk, VAR1;
input [VAR3-1:0] VAR2;
output reg [VAR4-1:0] VAR5;
reg [VAR4-1:0] VAR6[2**VAR3-1:0];
begin
begin | mit |
monotone-RK/FACE | IEICE-Trans/data_compression/16-way_2-tree/src/ip_pcie/PCIeGen2x8If128_stub.v | 7,254 | module MODULE1(VAR48, VAR49, VAR71, VAR18, VAR7, VAR76, VAR38, VAR41, VAR63, VAR57, VAR83, VAR23, VAR26, VAR39, VAR69, VAR17, VAR15, VAR13, VAR22, VAR14, VAR86, VAR45, VAR9, VAR75, VAR36, VAR24, VAR47, VAR32, VAR82, VAR59, VAR8, VAR81, VAR29, VAR68, VAR43, VAR27, VAR78, VAR12, VAR4, VAR55, VAR19, VAR84, VAR16, VAR33, V... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9625/axi_ad9625_pnmon.v | 27,849 | module MODULE1 (
VAR9,
VAR2,
VAR7,
VAR13,
VAR15);
input VAR9;
input [191:0] VAR2;
output VAR7;
output VAR13;
input [ 3:0] VAR15;
reg [191:0] VAR12 = 'd0;
reg [191:0] VAR6 = 'd0;
wire [191:0] VAR11;
function [191:0] VAR5;
input [191:0] din;
reg [191:0] dout;
begin
dout[191] = din[22] ^ din[17];
dout[190] = din[21] ^ din... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfstp/sky130_fd_sc_hs__sdfstp.pp.symbol.v | 1,462 | module MODULE1 (
input VAR5 ,
output VAR6 ,
input VAR8,
input VAR7 ,
input VAR2 ,
input VAR1 ,
input VAR4 ,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sedfxbp/sky130_fd_sc_ls__sedfxbp.symbol.v | 1,517 | module MODULE1 (
input VAR8 ,
output VAR7 ,
output VAR10,
input VAR2 ,
input VAR6,
input VAR3,
input VAR1
);
supply1 VAR5;
supply0 VAR11;
supply1 VAR4 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a31oi/sky130_fd_sc_hs__a31oi_2.v | 2,223 | module MODULE2 (
VAR9 ,
VAR3 ,
VAR5 ,
VAR8 ,
VAR7 ,
VAR6,
VAR4
);
output VAR9 ;
input VAR3 ;
input VAR5 ;
input VAR8 ;
input VAR7 ;
input VAR6;
input VAR4;
VAR2 VAR1 (
.VAR9(VAR9),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR9 ,
VAR3,
VAR5,
VAR8,
VAR7
);... | apache-2.0 |
FPGA1988/udp_ip_stack | Network/udp_ip_core/trunk/ic/digital/rtl/eth_tri_mode/TECH/altera/CLK_SWITCH.v | 3,532 | module MODULE1 (
input VAR1,
input VAR2,
input VAR4 ,
output VAR3
);
assign VAR3=VAR4?VAR2:VAR1;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfrbp/sky130_fd_sc_ls__dfrbp.symbol.v | 1,423 | module MODULE1 (
input VAR3 ,
output VAR2 ,
output VAR4 ,
input VAR7,
input VAR5
);
supply1 VAR8;
supply0 VAR6;
supply1 VAR1 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor3/sky130_fd_sc_hdll__nor3_1.v | 2,214 | module MODULE2 (
VAR2 ,
VAR5 ,
VAR10 ,
VAR6 ,
VAR4,
VAR1,
VAR7 ,
VAR9
);
output VAR2 ;
input VAR5 ;
input VAR10 ;
input VAR6 ;
input VAR4;
input VAR1;
input VAR7 ;
input VAR9 ;
VAR8 VAR3 (
.VAR2(VAR2),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR9(VAR9)
);
endmodule
module MODULE... | apache-2.0 |
UCR-CS179-SUMMER2014/NES_FPGA | source/NES_FPGA/nios_system/synthesis/submodules/nios_system_CPU_jtag_debug_module_sysclk.v | 6,900 | module MODULE1 (
clk,
VAR11,
VAR26,
VAR4,
VAR23,
VAR32,
VAR24,
VAR27,
VAR25,
VAR28,
VAR2,
VAR30,
VAR8,
VAR29,
VAR14,
VAR19,
VAR31,
VAR12,
VAR15
)
;
output [ 37: 0] VAR32;
output VAR24;
output VAR27;
output VAR25;
output VAR28;
output VAR2;
output VAR30;
output VAR8;
output VAR29;
output VAR14;
output VAR19;
output VAR3... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.v | 2,246 | module MODULE1 (
VAR6 ,
VAR3 ,
VAR5 ,
VAR1 ,
VAR7,
VAR9 ,
VAR4
);
input VAR6 ;
input VAR3 ;
output VAR5 ;
output VAR1 ;
input VAR7;
input VAR9 ;
input VAR4 ;
VAR8 VAR2 (
.VAR6(VAR6),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR6 ,
VAR3 ,
VAR5 ,
VAR1 ,
VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlymetal6s2s/sky130_fd_sc_ls__dlymetal6s2s.symbol.v | 1,355 | module MODULE1 (
input VAR1,
output VAR3
);
supply1 VAR4;
supply0 VAR5;
supply1 VAR2 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
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