repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfstp/sky130_fd_sc_hs__dfstp.functional.pp.v | 1,729 | module MODULE1 (
VAR5 ,
VAR10 ,
VAR13 ,
VAR12 ,
VAR4 ,
VAR2
);
input VAR5 ;
input VAR10 ;
output VAR13 ;
input VAR12 ;
input VAR4 ;
input VAR2;
wire VAR9;
wire VAR8 ;
not VAR11 (VAR8 , VAR2 );
VAR1 VAR6 VAR3 (VAR9 , VAR4, VAR12, VAR8, VAR5, VAR10);
buf VAR7 (VAR13 , VAR9 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or2b/sky130_fd_sc_hd__or2b_4.v | 2,127 | module MODULE1 (
VAR3 ,
VAR4 ,
VAR7 ,
VAR8,
VAR6,
VAR9 ,
VAR5
);
output VAR3 ;
input VAR4 ;
input VAR7 ;
input VAR8;
input VAR6;
input VAR9 ;
input VAR5 ;
VAR2 VAR1 (
.VAR3(VAR3),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR3 ,
VAR4 ,
VAR7
);
output VAR3... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfrtp/sky130_fd_sc_hd__sdfrtp.pp.symbol.v | 1,517 | module MODULE1 (
input VAR3 ,
output VAR4 ,
input VAR7,
input VAR8 ,
input VAR1 ,
input VAR5 ,
input VAR6 ,
input VAR2 ,
input VAR9 ,
input VAR10
);
endmodule | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/ac97/rtl/ac97_asfifo.v | 4,301 | module MODULE1
VAR10 = 4,
VAR13 = (1 << VAR10))
(output wire [VAR1-1:0] VAR11,
output reg VAR14,
input wire VAR4,
input wire VAR19,
input wire [VAR1-1:0] VAR22,
output reg VAR25,
input wire VAR2,
input wire VAR3,
input wire VAR20);
reg [VAR1-1:0] VAR16 [VAR13-1:0];
wire [VAR10-1:0] VAR18, VAR27;
wire VAR8;
wire VAR6, V... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | models/udp_dff_ps/sky130_fd_sc_ls__udp_dff_ps.blackbox.v | 1,233 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR3,
VAR2
);
output VAR1 ;
input VAR4 ;
input VAR3;
input VAR2;
endmodule | apache-2.0 |
Jesus89/open-fpga-verilog-tutorial | tutorial/ICESTICK/T16-countsec/countsec.v | 1,191 | module MODULE1(input wire clk, output wire [3:0] VAR4);
parameter VAR1 = VAR5;
wire VAR7;
reg [3:0] counter = 0;
VAR8 #(VAR1)
VAR3 (
.VAR6(clk),
.VAR2(VAR7)
);
always @(posedge VAR7)
counter <= counter + 1;
assign VAR4 = counter;
endmodule | gpl-2.0 |
ptracton/vscale_soc | rtl/bus_matrix/bus_matrix.v | 11,366 | module MODULE1
(input VAR151,
input VAR44,
input [31:0] VAR133,
input [31:0] VAR124,
input [3:0] VAR134,
input VAR77,
input VAR19,
input VAR164,
input [2:0] VAR81,
input [1:0] VAR47,
output [31:0] VAR140,
output VAR15,
output VAR78,
output VAR93,
input [31:0] VAR99,
input [31:0] VAR128,
input [3:0] VAR61,
input VAR166,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/lsbufiso0p/sky130_fd_sc_lp__lsbufiso0p.blackbox.v | 1,330 | module MODULE1 (
VAR9 ,
VAR3,
VAR8
);
output VAR9 ;
input VAR3;
input VAR8 ;
supply1 VAR7;
supply1 VAR4 ;
supply0 VAR6 ;
supply1 VAR2;
supply1 VAR1 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
AngelTerrones/Antares | Hardware/verilog/antares_core.v | 47,472 | module MODULE1 #(parameter VAR192 = 1,
parameter VAR58 = 1,
parameter VAR119 = 1
)(
input clk,
input rst,
output VAR46, input [4:0] VAR171, input VAR273, input [31:0] VAR126, input VAR25, input VAR45, output [31:0] VAR160, output [3:0] VAR92, output VAR130, input [31:0] VAR53, input VAR141, input VAR144, output [31:0] ... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai31/gf180mcu_fd_sc_mcu9t5v0__oai31_1.functional.v | 1,436 | module MODULE1( VAR9, VAR8, VAR16, VAR2, VAR10 );
input VAR16, VAR2, VAR10, VAR9;
output VAR8;
wire VAR4;
not VAR5( VAR4, VAR16 );
wire VAR3;
not VAR14( VAR3, VAR2 );
wire VAR11;
not VAR12( VAR11, VAR10 );
wire VAR7;
and VAR15( VAR7, VAR4, VAR3, VAR11 );
wire VAR13;
not VAR1( VAR13, VAR9 );
or VAR6( VAR8, VAR7, VAR13 )... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_1.v | 2,466 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR3 ,
VAR5 ,
VAR7 ,
VAR6 ,
VAR8,
VAR10,
VAR2 ,
VAR12
);
output VAR4 ;
input VAR1 ;
input VAR3 ;
input VAR5 ;
input VAR7 ;
input VAR6 ;
input VAR8;
input VAR10;
input VAR2 ;
input VAR12 ;
VAR11 VAR9 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR8(VAR8... | apache-2.0 |
peteg944/music-fpga | Enlightened Main Project/Claps.v | 2,318 | module MODULE1(
input VAR1,
input rst,
input [9:0] VAR3,
output reg VAR2, output [3:0] VAR4
);
reg [2:0] state, VAR10;
reg [2:0] VAR17, VAR12;
reg [31:0] delay, VAR14;
reg VAR5;
localparam VAR11 = 10'd770; localparam VAR13 = 32'h4;
localparam VAR8 = 32'hB71B00; localparam VAR6 = 32'h5B8D800;
localparam VAR7 = 3'd0,
VAR... | mit |
diegovalverde/papiGB | rtl/sound_controller_modules/SoundControllerOSC2.v | 1,675 | module MODULE1
(
input wire VAR4,
input wire VAR2,
output wire VAR1,
output wire VAR5
);
reg [4:0] VAR3;
always @ (posedge VAR4) begin
if (VAR2) begin
VAR3 <= 0;
end
else begin
VAR3 <= VAR3+1;
end
end
assign VAR1 = VAR3[4];
assign VAR5 = VAR3[3];
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfbbp/sky130_fd_sc_hd__dfbbp.symbol.v | 1,467 | module MODULE1 (
input VAR8 ,
output VAR3 ,
output VAR5 ,
input VAR6,
input VAR4 ,
input VAR2
);
supply1 VAR10;
supply0 VAR1;
supply1 VAR7 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/buf/sky130_fd_sc_lp__buf_0.v | 1,993 | module MODULE2 (
VAR5 ,
VAR1 ,
VAR4,
VAR6,
VAR8 ,
VAR2
);
output VAR5 ;
input VAR1 ;
input VAR4;
input VAR6;
input VAR8 ;
input VAR2 ;
VAR7 VAR3 (
.VAR5(VAR5),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR5,
VAR1
);
output VAR5;
input VAR1;
supply1 VAR4;
supply0 VAR6;... | apache-2.0 |
8l/kestrel | 2/nexys2/uxa/ps2io/T_uxa_ps2_fifo.v | 7,228 | module MODULE1;
reg [7:0] VAR2;
reg VAR3;
reg VAR5;
reg VAR7;
reg VAR6;
reg VAR10;
wire [7:0] VAR8;
wire VAR11;
wire VAR4;
VAR1 VAR9 (
.VAR2(VAR2),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR10(VAR10)
);
always begin
VAR6 <= ~VAR6;
end | apache-2.0 |
kernelpanics/Grad | CORDIC-Natural-Logarithm/Verilog/Natural-Logarithm/LUT_Z.v | 3,004 | module MODULE1#(parameter VAR4 = 32, parameter VAR1 = 5) (
input wire VAR6,
input wire VAR3,
input wire [VAR1-1:0] VAR2,
output reg [VAR4-1:0] VAR5
);
always @(posedge VAR6)
if (VAR3)
case (VAR2)
5'b00000: VAR5 <= 32'b10111111100011001001111101010100;
5'b00001: VAR5 <= 32'b10111111000000101100010101111000;
5'b00010: VA... | gpl-3.0 |
nyaxt/dmix | spi_trx_t.v | 1,557 | module MODULE1;
reg clk;
parameter VAR6 = 20;
VAR12 clk = 0;
always #(VAR6/2) clk = ~clk;
reg VAR8;
parameter VAR4 = 55;
reg VAR5;
reg VAR3;
reg [7:0] VAR1;
reg VAR2;
VAR11 VAR10(
.clk(clk),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR2(VAR2));
task VAR7;
input wire [7:0] VAR9;
begin
VAR5 = VAR9[7];
VAR8 = ... | mit |
sam-falvo/polaris | ramcon/rtl/verilog/ramcon.v | 3,381 | module MODULE1(
input VAR4,
input VAR47,
output [22:0] VAR17,
inout [15:0] VAR43,
output VAR15,
output VAR20,
output VAR28,
output VAR5,
output VAR39,
output VAR21,
output VAR16,
output VAR49,
input VAR1,
output VAR50,
output [15:0] VAR42,
input [15:0] VAR18,
input [23:1] VAR46,
input [1:0] VAR40,
input VAR27,
input VA... | mpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlrtn/sky130_fd_sc_ls__dlrtn_1.v | 2,358 | module MODULE1 (
VAR7 ,
VAR8,
VAR10 ,
VAR4 ,
VAR5 ,
VAR6 ,
VAR3 ,
VAR2
);
output VAR7 ;
input VAR8;
input VAR10 ;
input VAR4 ;
input VAR5 ;
input VAR6 ;
input VAR3 ;
input VAR2 ;
VAR1 VAR9 (
.VAR7(VAR7),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR2(VAR2)
);
endmodule
module MODU... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21boi/sky130_fd_sc_ms__a21boi_2.v | 2,332 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR3 ,
VAR9,
VAR1,
VAR5,
VAR8 ,
VAR10
);
output VAR4 ;
input VAR2 ;
input VAR3 ;
input VAR9;
input VAR1;
input VAR5;
input VAR8 ;
input VAR10 ;
VAR7 VAR6 (
.VAR4(VAR4),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR10(VAR10)
);
endmodule
module MODULE1 ... | apache-2.0 |
mrehkopf/sd2snes | verilog/sd2snes_gsu/gsu_fmult.v | 4,652 | module MODULE1 (
VAR11,
VAR19,
VAR5,
VAR16);
input VAR11;
input [15:0] VAR19;
input [15:0] VAR5;
output [31:0] VAR16;
wire [31:0] VAR18;
wire [31:0] VAR16 = VAR18[31:0];
VAR10 VAR2 (
.VAR11 (VAR11),
.VAR19 (VAR19),
.VAR5 (VAR5),
.VAR16 (VAR18),
.VAR20 (1'b0),
.VAR14 (1'b1),
.VAR9 (1'b0),
.sum (1'b0));
VAR2.VAR1 = "VAR... | gpl-2.0 |
mrehkopf/sd2snes | verilog/sd2snes_dsp/upd77c25.v | 19,785 | module MODULE1(
input [7:0] VAR46,
output [7:0] VAR51,
input VAR39,
input enable,
input VAR59,
input VAR28,
input VAR32,
input VAR21,
input VAR115,
input VAR76,
input [23:0] VAR91,
input [10:0] VAR97,
input VAR80,
input [15:0] VAR83,
input [10:0] VAR54,
input VAR64,
input [10:0] VAR29,
input [15:0] VAR48,
output [15:0]... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or3/sky130_fd_sc_ls__or3_2.v | 2,153 | module MODULE2 (
VAR10 ,
VAR2 ,
VAR8 ,
VAR4 ,
VAR1,
VAR9,
VAR5 ,
VAR7
);
output VAR10 ;
input VAR2 ;
input VAR8 ;
input VAR4 ;
input VAR1;
input VAR9;
input VAR5 ;
input VAR7 ;
VAR6 VAR3 (
.VAR10(VAR10),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR7(VAR7)
);
endmodule
module MODULE... | apache-2.0 |
cagiurumescu/pmod_oled_s3e | src/oled_init.v | 7,509 | module MODULE1 (
input clk,
input reset,
input VAR32,
output reg VAR17,
output VAR25,
output VAR8,
output VAR4,
output VAR19, output reg VAR27,
output reg VAR9,
output reg VAR36
);
assign VAR19 = 1'b0;
localparam VAR24 = 12;
localparam VAR14 = 1;
localparam VAR35 = 100;
localparam VAR34 = VAR30'h00;
localparam VAR1 = V... | gpl-2.0 |
tmatsuya/milkymist-ml401 | cores/ac97/rtl/ac97_ctlif.v | 4,554 | module MODULE1 #(
parameter VAR29 = 4'h0
) (
input VAR2,
input VAR23,
input [13:0] VAR8,
input VAR6,
input [31:0] VAR24,
output reg [31:0] VAR30,
output reg VAR3,
output reg VAR15,
output reg VAR14,
output reg VAR1,
input VAR32,
input VAR18,
output reg VAR12,
output reg [19:0] VAR10,
output reg VAR37,
output reg [19:0]... | lgpl-3.0 |
paraschas/MIPS_CPU | library.v | 20,135 | module MODULE3 #(
parameter VAR42 = 32
) (
input wire [3:0] VAR70,
input wire [VAR42 - 1:0] VAR34,
input wire [VAR42 - 1:0] VAR84,
output reg [VAR42 - 1:0] out,
output wire VAR69
);
always @(VAR70, VAR34, VAR84) begin
case(VAR70)
0 : out = VAR34 & VAR84;
1 : out = VAR34 | VAR84;
2 : out = VAR34 + VAR84;
6 : out = VAR34... | mit |
freecores/orsoc_graphics_accelerator | rtl/verilog/gfx/gfx_rasterizer.v | 14,710 | module MODULE1(VAR4, VAR26,
VAR24, VAR22, VAR15,
VAR54, VAR3, VAR78, VAR46, VAR9,
VAR27, VAR18, VAR47, VAR21,
VAR41, VAR85,
VAR58, VAR84,
VAR71, VAR35,
VAR30,
VAR76, VAR11, VAR38, VAR17,
VAR70, VAR51,
VAR45, VAR7, VAR20,VAR57,
VAR66, VAR19,
VAR60, VAR31, VAR12
);
parameter VAR1 = 16;
parameter VAR50 = 16;
parameter VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv5sd1/sky130_fd_sc_ms__clkdlyinv5sd1.symbol.v | 1,357 | module MODULE1 (
input VAR6,
output VAR3
);
supply1 VAR2;
supply0 VAR1;
supply1 VAR5 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_qspi_1cs_top.v | 8,068 | module MODULE1(
input clk,
input VAR49,
input VAR46,
output VAR15,
input [32-1:0] VAR61,
input VAR14,
input [32-1:0] VAR38,
output VAR4,
input VAR33,
output [32-1:0] VAR29,
output VAR9,
input VAR19,
output VAR28,
output VAR21,
input VAR37,
output VAR67,
output VAR1,
input VAR17,
output VAR40,
output VAR35,
input VAR62,... | apache-2.0 |
sorgelig/Apogee_MIST | bios86.v | 6,496 | module MODULE1 (
address,
VAR17,
VAR39);
input [10:0] address;
input VAR17;
output [7:0] VAR39;
tri1 VAR17;
wire [7:0] VAR6;
wire [7:0] VAR39 = VAR6[7:0];
VAR16 VAR47 (
.VAR27 (address),
.VAR37 (VAR17),
.VAR24 (VAR6),
.VAR8 (1'b0),
.VAR26 (1'b0),
.VAR25 (1'b1),
.VAR14 (1'b0),
.VAR12 (1'b0),
.VAR43 (1'b1),
.VAR18 (1'b1)... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o21ba/sky130_fd_sc_hd__o21ba.pp.blackbox.v | 1,390 | module MODULE1 (
VAR2 ,
VAR7 ,
VAR5 ,
VAR1,
VAR6,
VAR3,
VAR4 ,
VAR8
);
output VAR2 ;
input VAR7 ;
input VAR5 ;
input VAR1;
input VAR6;
input VAR3;
input VAR4 ;
input VAR8 ;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/clk_ibuf.v | 4,263 | module MODULE1 #
(
parameter VAR14 = "VAR2" )
(
input VAR11, input VAR7,
input VAR20,
output VAR13
);
wire VAR12;
generate
if (VAR14 == "VAR2") begin: VAR9
VAR1 #
(
.VAR19 ("VAR3"),
.VAR8 ("VAR17")
)
VAR10
(
.VAR4 (VAR11),
.VAR18 (VAR7),
.VAR16 (VAR12)
);
end else if (VAR14 == "VAR5") begin: VAR15
VAR6 #
(
.VAR8 ("VAR1... | lgpl-3.0 |
m-labs/fjmem-m1 | fjmem/rtl/spartan6/fjmem_jtag.v | 1,060 | module MODULE1 (
output VAR5,
output VAR9,
output VAR14,
output VAR16,
output VAR3,
input VAR12
);
VAR4 #(
.VAR19(1)
) VAR2 (
.VAR18(),
.VAR1(VAR5),
.VAR8(VAR9),
.VAR15(),
.VAR11(),
.VAR17(VAR16),
.VAR7(),
.VAR13(VAR3),
.VAR6(),
.VAR10(VAR14),
.VAR20(VAR12)
);
endmodule | gpl-3.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/08ULTRASONIDO/Version_02/02 verilog/PorPruebas/BloquePruebaManual/visualizacion.v | 1,814 | module MODULE1 (
input clk,
input VAR19,
input VAR18,
output VAR4,
output [3:0] VAR21,
output [6:0] VAR12
);
wire [7:0] VAR14;
wire [7:0] VAR16;
wire [1:0] VAR8;
wire [3:0] VAR11;
wire [3:0] VAR21;
wire [6:0] VAR12;
wire [3:0] VAR3;
wire [3:0] VAR5;
wire [3:0] VAR1;
VAR23 VAR20 (
.clk ( clk ),
.VAR24 ( VAR24 )
);
VAR25... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/xor2/sky130_fd_sc_lp__xor2.behavioral.pp.v | 1,814 | module MODULE1 (
VAR6 ,
VAR13 ,
VAR12 ,
VAR7,
VAR8,
VAR9 ,
VAR10
);
output VAR6 ;
input VAR13 ;
input VAR12 ;
input VAR7;
input VAR8;
input VAR9 ;
input VAR10 ;
wire VAR2 ;
wire VAR5;
xor VAR4 (VAR2 , VAR12, VAR13 );
VAR11 VAR1 (VAR5, VAR2, VAR7, VAR8);
buf VAR3 (VAR6 , VAR5 );
endmodule | apache-2.0 |
SI-RISCV/e200_opensource | rtl/e203/core/e203_exu_excp.v | 26,983 | module MODULE1(
output VAR40,
output VAR43,
output VAR136,
output VAR102,
input VAR128,
input VAR67,
input VAR76,
output VAR109,
input VAR64 ,
input VAR58 ,
input VAR39 ,
input VAR140 ,
input VAR114 ,
input VAR74 ,
input VAR28 ,
input VAR9 ,
input VAR90 ,
input VAR107 ,
input VAR119 ,
input [VAR52-1:0] VAR87,
input [VA... | apache-2.0 |
wendlers/lattice-logic-sniffer | logic/lib/pll.v | 5,160 | module MODULE1 (VAR8, VAR4, VAR7, VAR5, VAR3)
;
assign VAR3 = VAR6;
assign VAR5 = VAR2;
assign VAR7 = VAR9;
assign VAR4 = VAR1;
endmodule | mit |
fbalakirev/red-pitaya-notes | cores/axi_sts_register_v1_0/axi_sts_register.v | 3,981 | module MODULE1 #
(
parameter integer VAR10 = 1024,
parameter integer VAR5 = 32,
parameter integer VAR2 = 16
)
(
input wire VAR26,
input wire VAR9,
input wire [VAR10-1:0] VAR11,
input wire [VAR2-1:0] VAR3, input wire VAR16, output wire VAR8, input wire [VAR5-1:0] VAR40, input wire VAR28, output wire VAR32, output wire [... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/invkapwr/sky130_fd_sc_lp__invkapwr.behavioral.v | 1,394 | module MODULE1 (
VAR4,
VAR1
);
output VAR4;
input VAR1;
supply1 VAR2 ;
supply0 VAR5 ;
supply1 VAR3;
supply1 VAR6 ;
supply0 VAR8 ;
wire VAR10;
not VAR7 (VAR10, VAR1 );
buf VAR9 (VAR4 , VAR10 );
endmodule | apache-2.0 |
idgaf/Verilog_codes | Ex10/main.v | 1,685 | module MODULE1(VAR29,VAR22,VAR21,VAR27,VAR3,VAR10,VAR24,VAR19,VAR2,VAR18,VAR9,VAR32,VAR16,VAR4,VAR13,VAR26,VAR8);
input wire [3:0]VAR18;
input wire [17:0]VAR2;
input wire VAR32;
input wire VAR4;
input wire VAR26;
output wire [6:0]VAR29;
output wire [6:0]VAR22;
output wire [6:0]VAR21;
output wire [6:0]VAR27;
output wire... | mit |
csail-csg/riscy-OOO | procs/asic/bluespec_verilog/RWire0.v | 1,397 | module MODULE1(VAR1, VAR2);
input VAR2;
output VAR1;
assign VAR1 = VAR2;
endmodule | mit |
drichmond/tinker | skels/16.0/de5net/top.v | 6,492 | module MODULE1
(
input VAR44,
input VAR121,
input VAR50,
input VAR43,
input VAR10,
input VAR16,
input VAR6,
input VAR86,
input VAR113,
input VAR1, input VAR48,
input VAR55,
input VAR107,
input VAR67,
input VAR122,
input VAR106,
input VAR104,
input VAR46,
output VAR60,
output VAR59,
output VAR114,
output VAR53,
output V... | bsd-3-clause |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_NVMeHostController_0_0/src/pcie_7x_0_core_top/source/pcie_7x_0_core_top_qpll_reset.v | 14,678 | module MODULE1 #
(
parameter VAR40 = "VAR34", parameter VAR27 = "VAR14", parameter VAR25 = 1, parameter VAR5 = 1
)
(
input VAR47,
input VAR21,
input VAR1,
input [VAR25-1:0] VAR9,
input [(VAR25-1)>>2:0]VAR6,
input [(VAR25-1)>>2:0]VAR38,
input [ 1:0] VAR45,
input [VAR25-1:0] VAR3,
input [VAR25-1:0] VAR7,
output VAR33,
ou... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or4/sky130_fd_sc_lp__or4_m.v | 2,228 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR8 ,
VAR1 ,
VAR10 ,
VAR5,
VAR7,
VAR11 ,
VAR9
);
output VAR4 ;
input VAR2 ;
input VAR8 ;
input VAR1 ;
input VAR10 ;
input VAR5;
input VAR7;
input VAR11 ;
input VAR9 ;
VAR3 VAR6 (
.VAR4(VAR4),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR11(VAR11),
.... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/addf/gf180mcu_fd_sc_mcu9t5v0__addf_1.behavioral.pp.v | 3,162 | module MODULE1( VAR4, VAR6, VAR9, VAR8, VAR1, VAR10, VAR3 );
input VAR6, VAR8, VAR9;
inout VAR10, VAR3;
output VAR1, VAR4;
VAR5 VAR2(.VAR4(VAR4),.VAR6(VAR6),.VAR9(VAR9),.VAR8(VAR8),.VAR1(VAR1),.VAR10(VAR10),.VAR3(VAR3));
VAR5 VAR7(.VAR4(VAR4),.VAR6(VAR6),.VAR9(VAR9),.VAR8(VAR8),.VAR1(VAR1),.VAR10(VAR10),.VAR3(VAR3)); | apache-2.0 |
SiLab-Bonn/MCA | firmware/src/qmca.v | 8,616 | module MODULE1 (
input wire VAR22,
inout wire [7:0] VAR76,
input wire [15:0] VAR127,
input wire VAR21,
input wire VAR83,
inout wire [7:0] VAR102,
input wire VAR90,
input wire VAR61,
input wire VAR5,
output wire [19:0] VAR143,
inout wire [15:0] VAR68,
output wire VAR59,
output wire VAR46,
output wire VAR32,
output wire ... | gpl-2.0 |
zaqwes8811/hdl-fpga | ip-cores/spi_host_ram_host/easy_avalon_mm.v | 1,028 | module MODULE2(
clk,
write,
address, VAR4,
VAR1
);
input clk, write;
input [VAR5-1:0] address;
input [7:0] VAR4;
output reg [7:0] VAR1;
reg [7:0] VAR3 [127:0];
always @(posedge clk) begin
if (write)
VAR3[address] <= VAR4;
VAR1 <= VAR3[address];
end
endmodule
module MODULE1(VAR6, VAR2, VAR7, VAR8, clk);
output reg [7:0]... | mit |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ip/zc702_s01_regslice_0/synth/zc702_s01_regslice_0.v | 14,866 | module MODULE1 (
VAR45,
VAR5,
VAR12,
VAR104,
VAR109,
VAR77,
VAR3,
VAR71,
VAR68,
VAR99,
VAR30,
VAR83,
VAR9,
VAR95,
VAR87,
VAR58,
VAR43,
VAR48,
VAR39,
VAR14,
VAR100,
VAR86,
VAR72,
VAR63,
VAR70,
VAR56,
VAR23,
VAR65,
VAR60,
VAR67,
VAR32,
VAR66,
VAR78,
VAR103,
VAR10,
VAR21,
VAR94,
VAR97,
VAR53,
VAR24,
VAR27,
VAR79,
VAR88,
V... | mit |
hoglet67/opc | copro/src/Tube/ph_fifo.v | 1,465 | module MODULE1 (
input VAR26,
input VAR4,
input VAR3,
input VAR24,
input [7:0] VAR17,
input VAR8,
input VAR12,
input VAR20,
output [7:0] VAR15,
output VAR13,
output VAR2
);
wire VAR25;
wire VAR18;
wire VAR6;
wire [7:0] VAR7;
wire VAR11;
wire VAR27;
wire [7:0] VAR22;
wire VAR19;
wire VAR16;
VAR29 VAR23 (
VAR10 VAR23 (
.... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/tapvgnd2/sky130_fd_sc_lp__tapvgnd2.symbol.v | 1,276 | module MODULE1 ();
supply1 VAR3;
supply0 VAR1;
supply1 VAR2 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a2111o/sky130_fd_sc_ms__a2111o.pp.symbol.v | 1,400 | module MODULE1 (
input VAR3 ,
input VAR10 ,
input VAR4 ,
input VAR6 ,
input VAR9 ,
output VAR1 ,
input VAR7 ,
input VAR2,
input VAR5,
input VAR8
);
endmodule | apache-2.0 |
egyp7/mor1kx | rtl/verilog/mor1kx_pic.v | 4,246 | module MODULE1
(
VAR15, VAR20, VAR1, VAR4,
clk, rst, VAR24, VAR32, VAR18, VAR9, VAR22
);
parameter VAR23="VAR17";
parameter VAR29 = 0;
input clk;
input rst;
input [31:0] VAR24;
output [31:0] VAR15;
output [31:0] VAR20;
input VAR32;
input VAR18;
input [15:0] VAR9;
input [31:0] VAR22;
output VAR1;
output [31:0] VAR4;
reg... | mpl-2.0 |
grantae/uart | src/uart_tx.v | 2,688 | module MODULE1 (
input VAR3,
input reset,
input VAR9,
input [7:0] VAR4,
input VAR6, output ready,
output reg VAR20
);
localparam [3:0] VAR2=0, VAR8=1, VAR15=2, VAR10=3, VAR16=4, VAR19=5,
VAR11=6, VAR13=7, VAR5=8, VAR12=9, VAR14=10;
reg [3:0] VAR17 = VAR2;
reg [7:0] VAR7 = 8'h00;
assign ready = (VAR17 == VAR2) || (VAR17... | mit |
bbrown1867/ObjectTracking | hw/common/Sdram_Control_4Port/Sdram_Control_4Port.v | 14,266 | module MODULE1(
VAR11,
VAR32,
VAR34,
VAR93,
VAR82,
VAR125,
VAR132,
VAR43,
VAR65,
VAR85,
VAR52,
VAR42,
VAR81,
VAR41,
VAR61,
VAR33,
VAR140,
VAR78,
VAR76,
VAR94,
VAR4,
VAR101,
VAR17,
VAR106,
VAR6,
VAR147,
VAR144,
VAR100,
VAR21,
VAR36,
VAR115,
VAR99,
VAR79,
VAR63,
VAR142,
VAR25,
VAR91,
VAR35,
VAR19,
VAR22,
VAR139,
VAR1,
VA... | mit |
SiLab-Bonn/basil | basil/firmware/modules/pulse_gen/pulse_gen.v | 1,451 | module MODULE1 #(
parameter VAR14 = 16'h0000,
parameter VAR15 = 16'h0000,
parameter VAR21 = 16
) (
input wire VAR8,
input wire VAR13,
input wire [VAR21-1:0] VAR19,
inout wire [7:0] VAR17,
input wire VAR20,
input wire VAR4,
input wire VAR12,
input wire VAR11,
output wire VAR3
);
wire VAR9, VAR18;
wire [VAR21-1:0] VAR2;
... | bsd-3-clause |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v6es_gtx_x4_250/example_design/PIO_64_TX_ENGINE.v | 9,515 | module MODULE1 (
clk,
VAR15,
VAR3,
VAR2,
VAR14,
VAR21,
VAR18,
VAR5,
VAR25,
VAR33,
VAR32,
VAR7,
VAR35,
VAR23,
VAR22,
VAR9,
VAR11,
VAR24,
VAR26,
VAR6,
VAR1,
VAR27,
VAR30,
VAR4,
VAR31,
VAR36
);
input clk;
input VAR15;
output [63:0] VAR3;
output [7:0] VAR2;
output VAR14;
output VAR21;
output VAR18;
output VAR5;
input VAR25... | lgpl-3.0 |
vipinkmenon/scas | hw/fpga/source/multiboot_ctrl/multiboot_ctrl.v | 3,334 | module MODULE1
(
input VAR16,
input VAR20,
input VAR2,
input [31:0] VAR1
);
localparam VAR9 = 'd0,
VAR26 = 'd1,
VAR22 = 'd2;
reg [1:0] state ;
reg VAR7;
reg [31:0] VAR24;
reg VAR15;
reg [3:0] counter;
reg VAR23;
reg VAR19;
wire [31:0] VAR18;
assign VAR18 = {2'b00,1'b1,VAR1[24],VAR1[25],3'b000,VAR1[16],VAR1[17],VAR1[18]... | mit |
plindstroem/oh | elink/hdl/etx_fifo.v | 5,523 | module MODULE1(
VAR30, VAR22, VAR5, VAR13, VAR3,
VAR7, VAR28, VAR2,
VAR35, VAR36, VAR40,
VAR4, VAR33, VAR43, VAR6, VAR1,
VAR29, VAR32, VAR17, VAR38, VAR44,
VAR10, VAR45, VAR19, VAR21
);
parameter VAR14 = 32;
parameter VAR37 = 32;
parameter VAR20 = 104;
parameter VAR9 = 6;
parameter VAR8 = 12'h000;
input VAR4;
input VAR... | gpl-3.0 |
cafe-alpha/wasca | v12/fpga_firmware/wasca/synthesis/submodules/altera_up_audio_in_deserializer.v | 7,476 | module MODULE1 (
clk,
reset,
VAR28,
VAR31,
VAR1,
VAR21,
VAR3,
VAR8,
VAR25,
VAR19,
VAR22,
VAR16,
VAR13,
VAR9
);
parameter VAR6 = 15;
parameter VAR12 = 5'h0F;
input clk;
input reset;
input VAR28;
input VAR31;
input VAR1;
input VAR21;
input VAR3;
input VAR8;
input VAR25;
input VAR19;
output reg [ 7: 0] VAR22;
output reg [... | gpl-2.0 |
ehab93/MIPS-Processor | RF/reg_32bits.v | 2,135 | module MODULE1 (
input [31:0] VAR21,
input VAR5, clk,
output [31:0] VAR36);
VAR18 VAR34 (.VAR36(VAR36[0 ]), .VAR21(VAR21[0 ]), .VAR5(VAR5), .clk(clk));
VAR18 VAR35 (.VAR36(VAR36[1 ]), .VAR21(VAR21[1 ]), .VAR5(VAR5), .clk(clk));
VAR18 VAR26 (.VAR36(VAR36[2 ]), .VAR21(VAR21[2 ]), .VAR5(VAR5), .clk(clk));
VAR18 VAR10 (.VA... | mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/system/synthesis/submodules/altera_avalon_mm_bridge.v | 11,339 | module MODULE1
parameter VAR40 = 32,
parameter VAR42 = 8,
parameter VAR39 = 10,
parameter VAR50 = 1,
parameter VAR32 = 1,
parameter VAR53 = 1,
parameter VAR36 = VAR40 / VAR42
)
(
input clk,
input reset,
output VAR24,
output [VAR40-1:0] VAR17,
output VAR25,
input [VAR50-1:0] VAR29,
input [VAR40-1:0] VAR27,
input [VAR39-... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_dff_nr_pp_pkg_sn/sky130_fd_sc_lp__udp_dff_nr_pp_pkg_sn.blackbox.v | 1,519 | module MODULE1 (
VAR5 ,
VAR4 ,
VAR8 ,
VAR2 ,
VAR7 ,
VAR3,
VAR9 ,
VAR6 ,
VAR1
);
output VAR5 ;
input VAR4 ;
input VAR8 ;
input VAR2 ;
input VAR7 ;
input VAR3;
input VAR9 ;
input VAR6 ;
input VAR1 ;
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/iobdg/common/rtl/iobdg_1r2w_vec.v | 4,871 | module MODULE1 (
dout, VAR18,
clk, VAR30, VAR19, VAR14, VAR39, VAR1, VAR35, VAR29, VAR4, VAR2
);
parameter VAR13 = 32;
parameter VAR23 = 5;
input clk;
input VAR30;
input VAR19;
input [VAR23-1:0] VAR14;
input [VAR23-1:0] VAR39;
input [VAR23-1:0] VAR1;
input VAR35;
input VAR29;
input VAR4;
input VAR2;
output dout;
output... | gpl-2.0 |
jameshegarty/rigel | platform/camera1x/vsrc/axi_master32_stub.v | 2,977 | module MODULE1(
output VAR19,
output VAR20,
input VAR16,
output [31:0] VAR22,
output [1:0] VAR25,
output [3:0] VAR2,
output [1:0] VAR18,
input VAR26,
output VAR9,
input VAR12,
input [31:0] VAR8,
input [1:0] VAR7,
output VAR5,
input VAR15,
output [31:0] VAR24,
output [1:0] VAR23,
output [3:0] VAR3,
output [1:0] VAR4,
ou... | mit |
peteasa/parallella-fpga | AdaptevaLib/src/ecfg/hdl/ecfg-ao.v | 13,218 | module MODULE1 (
VAR40, VAR64, VAR48, VAR51,
VAR28, VAR46, VAR16,
VAR27, VAR42, VAR45,
VAR37, VAR11, VAR44,
VAR14, VAR34, VAR57, VAR10,
VAR41,
VAR31, clk, VAR36, VAR12, VAR18, VAR65,
VAR63
);
parameter VAR8 = 12; parameter VAR1 = 32; parameter VAR50 = 32; parameter VAR6 = 12; parameter VAR49 = 5;
input [VAR6-1:0] VAR31... | lgpl-3.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_069.v | 1,463 | module MODULE2 (
VAR8,
VAR1
);
input [31:0] VAR8;
output [31:0]
VAR1;
wire [31:0]
VAR6,
VAR4,
VAR10,
VAR9,
VAR2,
VAR3,
VAR11;
assign VAR6 = VAR8;
assign VAR3 = VAR6 << 7;
assign VAR10 = VAR4 - VAR6;
assign VAR4 = VAR6 << 14;
assign VAR11 = VAR2 - VAR3;
assign VAR2 = VAR10 + VAR9;
assign VAR9 = VAR6 << 12;
assign VAR1 =... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_2.functional.v | 1,787 | module MODULE1( VAR8, VAR18, VAR3, VAR25, VAR12, VAR23, VAR21, VAR26 );
input VAR25, VAR3, VAR23, VAR8, VAR12, VAR18, VAR26;
output VAR21;
not VAR6( VAR19, VAR23 );
not VAR5( VAR20, VAR12 );
wire VAR1;
not VAR15( VAR1, VAR3 );
wire VAR28;
not VAR16( VAR28, VAR8 );
wire VAR11;
and VAR17( VAR11, VAR1, VAR28 );
wire VAR22... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_mout/rtl/jbi_mout.v | 27,545 | module MODULE1 (
VAR27, VAR65, VAR162, VAR136,
VAR43, VAR150, VAR8, VAR121,
VAR173, VAR10, VAR118, VAR138,
VAR119, VAR9, VAR255,
VAR64, VAR254, VAR101,
VAR156, VAR247, VAR183,
VAR34, VAR222, VAR193,
VAR184, VAR66, VAR49, VAR16,
VAR28, VAR181, VAR96, VAR123,
VAR214, VAR175, VAR185, VAR251,
VAR198, VAR157, VAR169,
VAR196... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/iobdg/c2i/rtl/c2i_fdp.v | 15,412 | module MODULE1 (
VAR79, VAR87, VAR39, VAR12,
VAR19, VAR97, VAR50,
VAR45, VAR104, VAR29,
VAR94, VAR28, VAR102,
VAR37, VAR52,
VAR51, VAR72, VAR5, VAR69, VAR77,
VAR73, VAR8,
VAR75, VAR66,
VAR82, VAR99, VAR41,
VAR81, VAR101,
VAR103, VAR111, VAR6,
VAR62, VAR93, VAR40,
VAR23, VAR31, VAR4,
VAR63
);
input VAR51;
input VAR72;
i... | gpl-2.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/ethmac/rtl/verilog/eth_crc.v | 7,096 | module MODULE1 (VAR2, VAR4, VAR5, VAR1, VAR6, VAR3, VAR8);
input VAR2;
input VAR4;
input [3:0] VAR5;
input VAR1;
input VAR6;
output [31:0] VAR3;
output VAR8;
reg [31:0] VAR3;
wire [31:0] VAR7;
assign VAR7[0] = VAR1 & (VAR5[0] ^ VAR3[28]);
assign VAR7[1] = VAR1 & (VAR5[1] ^ VAR5[0] ^ VAR3[28] ^ VAR3[29]);
assign VAR7[2]... | gpl-2.0 |
CospanDesign/nysa-verilog | verilog/generic/adapter_dpb_ppfifo.v | 7,896 | module MODULE1 #(
parameter VAR46 = 9,
parameter VAR47 = 32
)(
input clk,
input rst,
input VAR24,
input VAR42,
input VAR12,
output reg [31:0] VAR3,
output VAR45,
input VAR44,
input [VAR46 - 1: 0] VAR56,
input [VAR47 - 1: 0] VAR33,
output [VAR47 - 1: 0] VAR9,
output VAR54,
input VAR28,
input [1:0] VAR60,
output reg [1:0... | mit |
fbalakirev/red-pitaya-notes | cores/axi_axis_reader_v1_0/axi_axis_reader.v | 3,109 | module MODULE1 #
(
parameter integer VAR12 = 32,
parameter integer VAR14 = 16
)
(
input wire VAR18,
input wire VAR19,
input wire [VAR14-1:0] VAR16, input wire VAR6, output wire VAR3, input wire [VAR12-1:0] VAR29, input wire VAR15, output wire VAR28, output wire [1:0] VAR13, output wire VAR17, input wire VAR26, input wi... | mit |
csturton/wirepatch | system/hardware/cores/ethmac/xilinx_dist_ram_16x32.v | 7,413 | module MODULE1
(
VAR4,
VAR40,
VAR25,
VAR54,
VAR41,
VAR13
);
output [31:0] VAR4;
input VAR40, VAR13;
input [31:0] VAR25;
input [3:0] VAR41, VAR54;
wire [3:0] VAR53 = VAR41 ;
wire [3:0] VAR19 = VAR54 ;
VAR31 VAR8 (.VAR37(VAR4[0]), .VAR45(), .VAR36(VAR53[0]), .VAR21(VAR53[1]), .VAR44(VAR53[2]), .VAR51(VAR53[3]), .VAR3(VAR... | mit |
aquaxis/FPGAMAG18 | modules/uart_v1/src/fmrv32im_axis_uart.v | 28,243 | module MODULE3
parameter VAR178 = 8'd107
)
(
input VAR197,
input VAR149,
input [15:0] VAR23,
input [3:0] VAR172,
input [2:0] VAR39,
input VAR202,
output VAR137,
input [31:0] VAR145,
input [3:0] VAR134,
input VAR50,
output VAR78,
output VAR20,
input VAR43,
output [1:0] VAR168,
input [15:0] VAR58,
input [3:0] VAR130,
inp... | mit |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/pcieCore/source/pcieCore_axi_basic_rx.v | 8,243 | module MODULE1 #(
parameter VAR21 = 128, parameter VAR34 = "VAR19", parameter VAR6 = "VAR8", parameter VAR1 = "VAR8", parameter VAR18 = 1,
parameter VAR23 = (VAR21 == 128) ? 2 : 1, parameter VAR37 = VAR21 / 8 ) (
output [VAR21-1:0] VAR16, output VAR13, input VAR9, output [VAR37-1:0] VAR2, output VAR20, output [21:0] VA... | gpl-2.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/stream_encoder_ip_prj/stream_encoder_ip_prj.ip_user_files/ipstatic/axi_traffic_gen_v2_0_7/hdl/src/verilog/axi_traffic_gen_v2_0_cmdram.v | 7,295 | module MODULE1 #(
parameter VAR27 = "VAR25",
parameter VAR38 = "VAR39",
parameter VAR8 = "VAR39",
parameter VAR32 = "VAR39",
parameter VAR47 = "VAR39"
) (
input reset ,
input VAR22 ,
input VAR4 ,
input [15:0 ] VAR50 ,
input [15:0 ] VAR37 ,
input [15:0 ] VAR45 ,
input [127:0] VAR49 ,
output [127:0] VAR36 ,
input VAR5 ,
... | gpl-3.0 |
sam-falvo/remex | rtl/queue_8x9.v | 1,692 | module MODULE1(
input clk,
input reset,
input VAR6,
input VAR7,
input [7:0] VAR5,
input VAR8,
output VAR16,
output [8:0] VAR14,
output VAR21,
output VAR18,
output [7:0] VAR4, output [2:0] VAR13,
output [2:0] VAR3,
output VAR15
);
reg [8:0] VAR22[0:7];
reg [7:0] VAR20; reg [2:0] VAR9, VAR12; reg VAR1;
assign VAR16 = VAR... | mpl-2.0 |
gajjanag/6111_Project | src/Square.v | 1,071 | module MODULE1 #(parameter VAR3 = 27000000) (
input VAR1, reset,
output reg VAR6 = 0);
wire VAR2;
VAR5 #(.VAR3(VAR3)) VAR4 (
.VAR1(VAR1),
.reset(reset),
.VAR7(1'b0),
.VAR2(VAR2)
);
always @ (posedge VAR2) begin
VAR6 <= ~VAR6;
end
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o31ai/sky130_fd_sc_ms__o31ai.pp.symbol.v | 1,359 | module MODULE1 (
input VAR6 ,
input VAR3 ,
input VAR7 ,
input VAR8 ,
output VAR2 ,
input VAR9 ,
input VAR5,
input VAR1,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand3/sky130_fd_sc_ms__nand3.behavioral.pp.v | 1,819 | module MODULE1 (
VAR10 ,
VAR6 ,
VAR8 ,
VAR9 ,
VAR7,
VAR4,
VAR3 ,
VAR14
);
output VAR10 ;
input VAR6 ;
input VAR8 ;
input VAR9 ;
input VAR7;
input VAR4;
input VAR3 ;
input VAR14 ;
wire VAR13 ;
wire VAR1;
nand VAR5 (VAR13 , VAR8, VAR6, VAR9 );
VAR2 VAR11 (VAR1, VAR13, VAR7, VAR4);
buf VAR12 (VAR10 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/tapvgnd/sky130_fd_sc_lp__tapvgnd.behavioral.pp.v | 1,230 | module MODULE1 (
VAR2,
VAR3,
VAR4 ,
VAR1
);
input VAR2;
input VAR3;
input VAR4 ;
input VAR1 ;
endmodule | apache-2.0 |
joaocarlos/udlx-verilog | rtl/data_memory_controll/sdram_fsm.v | 8,483 | module MODULE1 (
input VAR31,
input VAR11,
input [31:0] VAR20,
input [31:0] addr,
output VAR20
output reg [ 1:0] VAR42,
output reg VAR25,
output reg VAR18,
output reg VAR29,
output reg VAR4,
output reg [11:0] VAR13,
output reg [ 1:0] VAR43,
output reg [ 3:0] VAR48,
input [31:0] VAR1,
output reg [31:0] VAR41,
output reg... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr.functional.pp.v | 1,940 | module MODULE1 (
VAR8 ,
VAR5 ,
VAR7 ,
VAR6 ,
VAR12,
VAR10 ,
VAR9
);
output VAR8 ;
input VAR5 ;
input VAR7 ;
input VAR6 ;
input VAR12;
input VAR10 ;
input VAR9 ;
wire VAR3 ;
wire VAR2;
buf VAR11 (VAR3 , VAR5 );
VAR13 VAR1 (VAR2, VAR3, VAR12, VAR6);
buf VAR4 (VAR8 , VAR2 );
endmodule | apache-2.0 |
ankitshah009/High-Radix-Adaptive-CORDIC | HCORDIC_Verilog/NormaliseSum.v | 5,813 | module MODULE1(
input [1:0] VAR22,
input [31:0] VAR17,
input [1:0] VAR11,
input VAR1,
input VAR12,
input [27:0] VAR18,
input [7:0] VAR2,
input VAR13,
output reg [1:0] VAR9,
output reg [31:0] VAR5,
output reg [1:0] VAR3,
output reg VAR14,
output reg VAR4,
output reg [27:0] VAR16,
output reg [7:0] VAR7
);
parameter VAR10... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai32/gf180mcu_fd_sc_mcu9t5v0__oai32_1.functional.pp.v | 1,692 | module MODULE1( VAR23, VAR15, VAR12, VAR1, VAR17, VAR5, VAR13, VAR7 );
input VAR12, VAR15, VAR23, VAR17, VAR5;
inout VAR13, VAR7;
output VAR1;
wire VAR6;
not VAR19( VAR6, VAR12 );
wire VAR16;
not VAR4( VAR16, VAR15 );
wire VAR14;
not VAR10( VAR14, VAR23 );
wire VAR21;
and VAR9( VAR21, VAR6, VAR16, VAR14 );
wire VAR3;
n... | apache-2.0 |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_sd_host/rtl/generic/sd_crc_16.v | 1,336 | module MODULE1(
input clk, input rst, input en,
input VAR1, output reg [15:0] VAR2 );
wire VAR3;
assign VAR3 = VAR1 ^ VAR2[15];
always @(posedge clk or posedge rst) begin
if (rst) begin
VAR2 = 0;
end
else begin
if (en==1) begin
VAR2[15] = VAR2[14];
VAR2[14] = VAR2[13];
VAR2[13] = VAR2[12];
VAR2[12] = VAR2[11] ^ VAR3;
V... | mit |
SiLab-Bonn/basil | basil/firmware/modules/utils/tcp_to_bus.v | 4,576 | module MODULE1 (
input wire VAR21,
input wire VAR19,
output reg [15:0] VAR17, input wire VAR10, input wire [7:0] VAR16,
input wire VAR23,
input wire [31:0] VAR24,
input wire [7:0] VAR5,
input wire VAR4,
input wire VAR14,
output reg VAR7,
output wire [7:0] VAR25,
output wire VAR3,
output wire VAR9,
output wire [31:0] VA... | bsd-3-clause |
samyk/proxmark3 | fpga/hi_reader.v | 10,643 | module MODULE1(
VAR41,
VAR1, VAR15, VAR31, VAR20, VAR21, VAR16,
VAR4, VAR28,
VAR44, VAR39, VAR17, VAR10,
VAR37,
VAR23, VAR42
);
input VAR41;
output VAR1, VAR15, VAR31, VAR20, VAR21, VAR16;
input [7:0] VAR4;
output VAR28;
input VAR17;
output VAR44, VAR39, VAR10;
output VAR37;
input [1:0] VAR23;
input [3:0] VAR42;
assign... | gpl-2.0 |
danidim13/labo-digitales | Experimento3/MiniAlu.v | 5,978 | module MODULE1
(
input wire VAR30,
input wire VAR18,
output wire [7:0] VAR43
);
wire [15:0] VAR1,VAR48,VAR25;
reg VAR31,VAR28,VAR44,VAR36;
wire [27:0] VAR51;
wire [3:0] VAR5;
reg [15:0] VAR17;
wire [7:0] VAR2,VAR16,VAR14, VAR34;
wire [15:0] VAR22,VAR55,VAR3,VAR26,VAR46,VAR27,VAR59,VAR24;
wire VAR57, VAR39, VAR52, VAR21... | gpl-3.0 |
campsandrew/ECE-474A-Program-1 | Modules/CIRCUIT5.v | 1,059 | module MODULE1(VAR7, VAR31, VAR19, VAR17, VAR18, VAR21, VAR16);
input VAR17, VAR18;
input [63:0] VAR7, VAR31, VAR19;
output [31:0] VAR21, VAR16;
wire [63:0] VAR1, VAR23, VAR24, VAR22, VAR15;
wire VAR4, VAR14;
wire [63:0] VAR9, VAR25;
reg [63:0] VAR30, VAR27;
VAR5 #(64) VAR29(VAR7, VAR31, VAR1);
VAR5 #(64) VAR36(VAR7, V... | gpl-3.0 |
wamgoo/FPGA-Imaging-Library | Generator/RowsGenerator/HDL/RowsGenerator.srcs/sources_1/new/RowsGenerator.v | 6,047 | module MODULE1(
clk,
VAR14,
VAR10,
VAR8,
VAR21,
VAR17
);
parameter[3 : 0] VAR24 = 3;
parameter VAR25 = 320;
parameter[3: 0] VAR12 = 8;
parameter[4 : 0] VAR2 = 9;
input clk;
input VAR14;
input VAR10;
input [VAR12 - 1 : 0] VAR8;
output VAR21;
output[VAR24 * VAR12 - 1 : 0] VAR17;
reg VAR9[0 : VAR24];
wire VAR18[0 : VAR24]... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi.pp.symbol.v | 1,465 | module MODULE1 (
input VAR1,
input VAR7,
input VAR2 ,
input VAR5 ,
output VAR6 ,
input VAR9 ,
input VAR8,
input VAR4,
input VAR3
);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_16.behavioral.pp.v | 1,164 | module MODULE1( VAR1, VAR5, VAR6, VAR7 );
input VAR1;
inout VAR6, VAR7;
output VAR5;
VAR4 VAR2(.VAR1(VAR1),.VAR5(VAR5),.VAR6(VAR6),.VAR7(VAR7));
VAR4 VAR3(.VAR1(VAR1),.VAR5(VAR5),.VAR6(VAR6),.VAR7(VAR7)); | apache-2.0 |
chriswynnyk/american-put-verilog | american_put_cyclone/src/addrgen.v | 4,413 | module MODULE1(
clk,
VAR9,
VAR15,
VAR24,
VAR4,
VAR8,
VAR18,
VAR2,
VAR11
);
input clk;
input VAR9;
input VAR15;
input VAR24;
input [15:0]VAR4;
output [9:0]VAR8;
output [9:0]VAR2;
output [12:0]VAR11;
output VAR18;
reg [15:0]VAR3;
reg [15:0]VAR17;
reg [15:0]VAR13;
reg [15:0]VAR21;
reg [15:0]VAR14;
reg [15:0]VAR1;
reg [15:... | apache-2.0 |
jairov4/accel-oil | solution_spartan3/impl/pcores/nfa_accept_samples_generic_hw_top_v1_00_a/synhdl/verilog/nfa_accept_samples_generic_hw_nfa_finals_buckets_if.v | 44,620 | module MODULE3
VAR134 = 1,
VAR103 = 32,
VAR147 = 32,
VAR158 = 1,
VAR38 = 1,
VAR46 = 1,
VAR26 = 1,
VAR136 = 1,
VAR115 = 32,
VAR141 = 32'h00000000,
VAR18 = 1'b0,
VAR56 = 3'b000,
VAR37 = 4'b0011
)(
input wire VAR151,
input wire VAR80,
output wire [VAR134-1:0] VAR67,
output wire [VAR103-1:0] VAR142,
output wire [7:0] VAR23... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/lsbuf/sky130_fd_sc_lp__lsbuf.behavioral.v | 1,630 | module MODULE1 (
VAR3,
VAR10
);
output VAR3;
input VAR10;
supply1 VAR8;
supply1 VAR11 ;
supply0 VAR6 ;
supply1 VAR2;
supply1 VAR12 ;
supply0 VAR7 ;
wire VAR1;
buf VAR9 (VAR1, VAR10 );
VAR4 VAR5 (VAR3 , VAR1, VAR8, VAR6);
endmodule | apache-2.0 |
UA3MQJ/fpga-synth | modules/note2dds_2st_gen.v | 1,608 | module MODULE1(VAR4, VAR1, VAR2);
input wire VAR4;
input wire [6:0] VAR1;
output reg [31:0] VAR2;
reg [31:0] VAR3 [12:0]; | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlrbp/sky130_fd_sc_lp__dlrbp.functional.pp.v | 2,072 | module MODULE1 (
VAR5 ,
VAR6 ,
VAR7,
VAR4 ,
VAR16 ,
VAR17 ,
VAR1 ,
VAR10 ,
VAR8
);
output VAR5 ;
output VAR6 ;
input VAR7;
input VAR4 ;
input VAR16 ;
input VAR17 ;
input VAR1 ;
input VAR10 ;
input VAR8 ;
wire VAR14;
wire VAR9;
not VAR11 (VAR14 , VAR7 );
VAR2 VAR3 VAR13 (VAR9 , VAR4, VAR16, VAR14, , VAR17, VAR1);
buf VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2111ai/sky130_fd_sc_lp__o2111ai_2.v | 2,461 | module MODULE2 (
VAR3 ,
VAR8 ,
VAR6 ,
VAR10 ,
VAR1 ,
VAR11 ,
VAR5,
VAR2,
VAR7 ,
VAR4
);
output VAR3 ;
input VAR8 ;
input VAR6 ;
input VAR10 ;
input VAR1 ;
input VAR11 ;
input VAR5;
input VAR2;
input VAR7 ;
input VAR4 ;
VAR12 VAR9 (
.VAR3(VAR3),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR11(VAR11),
.VAR5(... | apache-2.0 |
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