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arjun10g
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+# Compression Is Part of the Compute
+### Lecture 1a: why a quantized model is only as fast as the kernel that reads it
+*Approx. 45 minutes spoken. Written to be listened to: the numbers that matter are rounded and said in words, and the mechanisms are described rather than drawn. The one-line version: optimise the representation the hardware actually executes, not just the size of the file.*
+---
+## The obvious story
+Welcome back. Today's lecture starts with an idea so obvious that it barely seems worth a lecture, and then spends forty minutes showing why the obvious version is incomplete.
+Here is the obvious idea. A large language model is mostly weights. When the model generates a token, it has to read those weights from memory. Reading memory is slow. So if we store each weight in fewer bits, we move fewer bytes, and the model runs faster. Sixteen bits down to four bits means a quarter of the bytes, which should mean something close to four times the speed. Three bits should be faster still. Two bits faster again.
+That story is not wrong. It is where the whole field of weight quantization for inference comes from, and the best systems really do get close to that four-times figure in the right conditions. But the story skips a step. Between the compressed bytes sitting in memory and the multiply-add that actually uses them, something has to unpack those bits into a number the arithmetic units understand. That unpacking is work. It happens on the same chip, in the same time budget, competing for the same resources as everything else. And depending on how the bits are laid out, it can be nearly free, or it can eat the entire benefit of compression, or it can make the compressed model slower than the uncompressed one.
+So the thesis of this lecture is a single sentence. A compressed model is only fast if the processor can consume that compressed representation efficiently. Compression is part of the compute.
+To make that sentence mean something, we need to build up some machinery. We will start with where the time actually goes when a model generates text. Then we will look at what fewer bits buy on paper, and what the hidden decoding step costs. Then we will go down into how a graphics processor physically reads memory, how its matrix units want their data arranged, and why lookup tables are awkward. Only then will we arrive at FLUTE, a kernel for lookup-table quantized models, and take it apart piece by piece. After that we will look at the same idea appearing in other systems, at real cases where a smaller format ran slower, at hardware that is starting to speak these formats natively, and finally at a design rule for anyone building their own hardware or kernels.
+## Where the time goes
+Let's start with the physics of generating one token.
+A transformer layer is dominated by a few large matrix multiplications: the attention projections and the feed-forward network. When the model is generating text for a single user, one token at a time, each of those multiplications takes a single activation vector and multiplies it by a large weight matrix. That is a matrix-vector product, and it has a very particular shape of cost.
+Think about what a matrix-vector product does per weight. It reads the weight, multiplies it by one element of the input vector, and adds the result into a running sum. Two floating-point operations, a multiply and an add. And the weight, in half precision, is two bytes. So the arithmetic intensity, the number of operations per byte fetched from memory, is about one. One operation per byte.
+Now compare that to what the hardware can do. A modern data-centre graphics processor like the H100 can perform nearly a thousand trillion half-precision operations per second on its tensor cores, and it can read a little over three trillion bytes per second from its high-bandwidth memory. Divide one by the other and you get the processor's balance point: about three hundred operations per byte. On the older A100, it is about a hundred and fifty.
+This is the roofline model, and it is worth holding onto because the rest of the lecture hangs from it. The roofline says the speed of any computation is capped by the lower of two ceilings: the processor's peak arithmetic rate, or its memory bandwidth multiplied by the computation's arithmetic intensity. If your work does fewer operations per byte than the balance point, you are memory bound: the arithmetic units sit idle, waiting for data. If it does more, you are compute bound.
+Single-user decoding sits at about one operation per byte, against a balance point of about three hundred. It is not a little memory bound. It is memory bound by more than two orders of magnitude. The tensor cores spend almost all their time waiting.
+That gives us a very simple way to estimate the speed limit of generation. Every token requires streaming essentially all the weights once. So the maximum tokens per second is roughly the memory bandwidth divided by the size of the model in bytes. An eight-billion-parameter model in half precision is about sixteen gigabytes. At a little over three terabytes per second, that is a ceiling of about two hundred tokens per second. Store the same model in four bits, around four gigabytes, and the ceiling rises to about eight hundred. Real systems reach perhaps half to two thirds of peak bandwidth, but the proportion holds: the bytes are the budget.
+There is an energy version of the same argument. Fetching a word from off-chip memory costs hundreds of times more energy than a floating-point addition. Arithmetic is cheap. Moving data is expensive. So in this regime, bytes are the currency, and quantization is a way of spending fewer of them.
+That is the obvious story, stated carefully. Now let's see what it hides.
+## What fewer bits buy on paper
+The first thing the obvious story hides is that a four-bit model is rarely four bits.
+To store weights in four bits, you have to map real-valued weights onto sixteen possible codes. The standard way is group-wise quantization: take a small group of consecutive weights, say a hundred and twenty-eight of them, find a scale for that group, and store each weight as a small integer that gets multiplied by the scale to reconstruct it. Often there is also a zero point, an offset. The scale and zero point are stored in higher precision, typically sixteen bits each.
+That metadata is not free. A sixteen-bit scale shared across a hundred and twenty-eight weights adds an eighth of a bit per weight. Add a zero point and it is a quarter of a bit. Use smaller groups for better accuracy and the overhead grows. The popular format for bits-and-bytes normal-float four-bit, with a scale for every sixty-four weights, comes to four and a half bits per weight, unless you also quantize the scales themselves, which brings it back to just over four point one. The widely used block formats in the llama dot c-p-p ecosystem tell the same story in their names: their "four-bit" format is four and a half bits per weight, their "three-bit" is about three and a half, and their "two-bit" is about two and a half.
+Those overheads show up directly in speedups. The Marlin kernel, which we will meet properly later, is one of the best four-bit kernels ever written, and its authors point out that the ideal speedup over half precision is not four, but about three point nine, precisely because the group scales add an eighth of a bit to every weight. Metadata eats into the ceiling before a single instruction runs.
+And for exotic formats, the bookkeeping gets worse. Methods that keep a small fraction of outlier weights in full precision, stored as a sparse matrix, pay for the indices of those outliers. One such method, SqueezeLLM, moves from about three point zero two bits to about three point two four bits by keeping less than half a percent of weights as outliers, and adds around ten percent to latency for handling them. Methods based on codebooks pay for the codebooks. A so-called two-bit model can easily be closer to three bits per parameter once you count everything in the file.
+So the first correction to the obvious story is this: count every byte. The number that matters is bytes moved per weight, including scales, zero points, codebooks, outlier indices, and padding. Not the nominal bit width on the label.
+## The hidden step: someone has to decode
+The second thing the obvious story hides is the decoding step.
+Most weight-only quantization schemes work like this. The weights are stored compressed. The activations stay in sixteen-bit floating point. The matrix multiplication itself happens in sixteen-bit floating point on the tensor cores, because that is what the tensor cores are built to do. So somewhere between memory and the tensor core, each compressed weight has to be turned back into a sixteen-bit number. Unpack the bits, look up or compute the value, multiply by the group scale, maybe add the zero point.
+Where does that happen? The naive answer is: in a separate step. Launch one kernel that reads the compressed weights and writes out a full sixteen-bit copy, then launch an ordinary matrix multiplication on that copy. This is catastrophic for decoding, and it is worth seeing why. The separate step reads the compressed weights, which is the small read we wanted, but then writes the full sixteen-bit matrix back to memory and reads it again for the multiplication. You have made the traffic worse than not quantizing at all. One measurement of a four-bit implementation that dequantized in a separate kernel found it running at under a third of the speed of the plain half-precision baseline. An early version of a popular four-bit library only used a fused path for single tokens; for anything larger it expanded the whole weight to sixteen bits first.
+So the decode has to happen inside the matrix multiplication kernel: load compressed bytes from memory, unpack them in registers, feed them straight to the tensor cores, and never write the expanded weights anywhere. That is called a fused, or mixed-input, kernel.
+But fusing the decode does not make it free. It moves it onto a different part of the chip. The tensor cores do the matrix arithmetic. The unpacking, the shifts and masks and conversions and scale multiplications, happens on the ordinary arithmetic units, sometimes called the CUDA cores. And those are much, much slower. On an H100, the general-purpose floating-point throughput is about one fifteenth of the half-precision tensor core throughput. Look closer, at a single streaming multiprocessor per clock cycle, and the gap is starker. The tensor cores can do on the order of two thousand half-precision multiply-adds per cycle. The integer units can do sixty-four simple operations. And the native instruction that converts an integer into a floating-point number runs at just sixteen per cycle.
+Now put that next to the memory budget. If the kernel is streaming weights at full memory bandwidth, how many instructions can it afford to spend decoding each weight without becoming the bottleneck itself? The rough answer, on an H100 at batch size one, is about two integer operations per weight, and less than one of those native conversions. Two instructions. That is the whole decode budget. Anything that costs more than a couple of cheap operations per weight turns a memory-bound kernel into an instruction-bound one, and you lose the speedup you paid for with accuracy.
+This is why kernel writers treat the integer-to-float conversion with such care. The standard trick, which Marlin uses, avoids the slow conversion instruction entirely. You take the four-bit integer and, with a single logical instruction, drop it into the low bits of a sixteen-bit floating-point number whose exponent is pre-set so that the number represents one thousand and twenty-four plus your integer. Then you subtract one thousand and twenty-four, and you have your value as a half-precision float. A logical operation and a subtraction, done on two values at once because they are packed into one thirty-two-bit register. That kind of bit-level trick is not a curiosity. It is what makes four-bit decoding fit into the budget at all.
+So here is the second correction to the obvious story. The format is not just a storage decision. It determines the decode instruction sequence, and that sequence has a budget of roughly two cheap operations per weight. A format that needs more than that is not faster, no matter how few bits it uses.
+## How the processor actually reads memory
+The third thing the obvious story hides is that memory is not read one bit, or one byte, at a time. It is read in fixed-size, aligned chunks, and the shape of those chunks matters enormously.
+On NVIDIA graphics processors, global memory is accessed in thirty-two-byte sectors, grouped into hundred-and-twenty-eight-byte cache lines. A warp, which is a group of thirty-two threads that execute in lockstep, issues a memory instruction, and the hardware combines the addresses those threads asked for into the minimum number of thirty-two-byte transactions. If the thirty-two threads read thirty-two consecutive, aligned words, that collapses into a handful of transactions, and every byte fetched is used. That is called coalescing, and it is the first rule of fast kernels. If each thread reads from a scattered location, each request may cost a full sector, and you can end up using an eighth of the bandwidth you are paying for. Even a misaligned but otherwise sequential read can touch five sectors instead of four.
+There is a second rule. An individual load instruction moves one, two, four, eight, or sixteen bytes, and the address has to be naturally aligned to that size. The fastest kernels use the sixteen-byte loads, a hundred and twenty-eight bits at a time, so that each thread pulls in a meaningful chunk per instruction.
+Now think about what this means for bit widths.
+Eight bits: a byte. Perfect. Four bits: two per byte, eight per thirty-two-bit word, thirty-two per sixteen-byte load. Perfect. Two bits and one bit: also powers of two, also perfect.
+Three bits: awkward. Three does not divide eight. Pack three-bit values end to end, and some of them straddle byte boundaries, and some of them straddle word boundaries. Sixteen of them occupy forty-eight bits, which is six bytes, which is not a legal load size. To extract a particular value, a thread may need bits from two different words, which means extra loads, shifts, masks and ors, all of which come out of that two-instruction budget. The alternative, padding each three-bit value out to four bits so that everything aligns, wastes a quarter of the bandwidth you compressed to save.
+Six bits has the same problem. Sixteen six-bit values are twelve bytes, again not a legal load size. One team measured that naive six-bit reads wasted between sixty and eighty percent of the shared-memory bandwidth involved.
+So the third correction is this: the hardware has a native grain. Bit widths that align with it are cheap to load. Bit widths that don't are either expensive to unpack or wasteful to pad. The number three looks like it is between two and four. To a memory system, it is not between them at all. It is off to the side.
+## Registers and the shape the tensor core wants
+The fourth thing hidden in the obvious story is that getting the bytes onto the chip is not the end. They have to arrive in the right places.
+Tensor cores do not multiply arbitrary arrays. A tensor-core instruction multiplies small fixed-size tiles, for instance a sixteen by sixteen tile against a sixteen by eight tile, and it expects its operands to be spread across the registers of the thirty-two threads in a warp in a very specific pattern, called the fragment layout. Thread zero holds certain elements, thread one holds certain others, and so on, in an interleaved pattern that exists for the convenience of the hardware, not for the convenience of anyone storing a model.
+When you multiply ordinary sixteen-bit matrices, there are special instructions that load tiles from shared memory and scatter them into exactly this layout for you. But there is no such instruction for four-bit data, let alone three-bit data. So if your compressed weights are stored in the natural row-by-row order of the original matrix, every thread has to load bytes, unpack them, and then shuffle values between threads or registers to get them into the fragment layout. More instructions, from the same tiny budget.
+The answer, used by every serious mixed-input kernel, is to do that shuffle once, offline, when the model is prepared. You permute the compressed weights in memory so that when each thread performs its single sixteen-byte load, the bytes it receives contain exactly the weights it will need, in exactly the order the tensor core expects. Marlin does this: each thread's sixteen-byte load holds exactly its own eight weights, already arranged in the interleaved order its registers need, so decoding is a handful of bit operations per pair and nothing moves between threads. On newer Hopper processors, whose matrix instructions read one operand directly from shared memory rather than registers, a follow-on kernel called Machete had to derive an entirely new pre-packed layout from the new instruction's requirements, and swap which operand lives where, so that the dequantized weights could stay in registers.
+This is the first time we see the thesis in its full form. The on-disk order of the weights is not the model's natural order. It is an order chosen to match the memory transaction size, the thread count of a warp, and the fragment layout of a particular tensor-core instruction on a particular generation of hardware. The format, the layout, and the kernel are one design.
+## Non-uniform formats and the lookup problem
+So far we have talked about uniform quantization: codes are evenly spaced integers, and decoding is a scale and an offset. But evenly spaced levels are not the best use of a small number of bits. Neural network weights are roughly bell-shaped: most weights are near zero, a few are large. If you only get sixteen levels, you would rather spend more of them near zero where the weights are dense, and fewer out in the tails.
+That is the idea behind non-uniform formats. The best known is normal-float four-bit, introduced with QLoRA, whose sixteen levels are placed at quantiles of a normal distribution, so that each level covers an equal share of a bell-shaped weight distribution. Other methods go further and learn the levels, with clustering, or with codebooks that represent several weights at once.
+Non-uniform formats buy accuracy. But they change the decoding step. There is no longer a formula that turns a code into a value with one multiply-add. You need a lookup table: the four-bit code is an index, and the value lives in a sixteen-entry table. And lookups have their own physics.
+Where do you keep the table? It needs to be fast and shared by the threads that use it, so it goes in shared memory, the small on-chip scratchpad each streaming multiprocessor has. Shared memory is divided into thirty-two banks, each four bytes wide, and in one cycle each bank can serve one address. If several threads in a warp read the same word, the hardware broadcasts it for free. If several threads read different words that happen to live in the same bank, those reads are serialised, one after another. That is a bank conflict.
+Now think about a table lookup during decoding. Each thread's index depends on the data: whatever code the weight happened to have. So the addresses are effectively random. A small table of sixteen half-precision values fits in eight words, so conflicts there are limited. But the moment you make the table bigger, or make each entry wider to return more values at once, random indices from thirty-two threads will collide in the same banks, and the lookups serialise. And there is a throughput question even without conflicts: at full memory speed on an H100, a single shared-memory lookup per four-bit weight is already enough to use up roughly all of shared memory's throughput. The lookup is not a side detail. It sits right on the critical path.
+One more distinction before we get to FLUTE, because the phrase "lookup table kernel" is used for two opposite ideas. In the first, which is FLUTE's family, the table maps weight codes to weight values: it replaces the decoding formula, and the tensor cores still do the multiplying. In the second, used by systems such as LUT-GEMM on graphics processors and T-MAC on phones and laptops, the table stores pre-computed partial sums of the activations, and the table lookups replace the multiplications themselves. The second idea is elegant, and on processors without tensor cores it can be excellent. On graphics processors, though, it cannot use the tensor cores at all, and later measurements found it running roughly twice as slow as a well-built decode-then-multiply kernel. Remember that; we will come back to it when we talk about hardware.
+## FLUTE, piece by piece
+Now we have everything we need to understand FLUTE, which stands for a flexible lookup table engine. It is a matrix-multiplication kernel for exactly the case we have been building towards: weights stored in lookup-table formats, including non-uniform ones like normal-float, at four bits and at the awkward three bits, with sixteen-bit activations, for small batch sizes where decoding is memory bound.
+FLUTE's authors identify three obstacles, and each of its main ideas addresses one.
+The first obstacle is the one we met with the tensor-core layout and the awkward bit width. FLUTE's answer is offline restructuring of the weight matrix. Before the model is ever run, the quantized weights are permuted so that after they are loaded and looked up, the resulting values land directly in the register positions the tensor-core instruction expects. No shuffling at run time.
+And for three bits, FLUTE does something more interesting. Rather than packing three-bit codes end to end, where they straddle word boundaries, or padding them to four bits, where they waste bandwidth, it splits each three-bit code into two separate streams: a one-bit stream holding the top bit of every code, and a two-bit stream holding the bottom two bits. Each stream, on its own, has a power-of-two element size. So each stream can be loaded with ordinary, aligned, full-width, coalesced loads, exactly the kind the memory system is built for. Inside the kernel, in registers, a couple of bit operations stitch each code back together from its two pieces. The total bytes moved are exactly three bits per weight, with no padding, and the loads are as efficient as if the format had been two bits or four.
+Pause on how different that is from the obvious story. The obvious story asks how many bits per weight. FLUTE keeps the bit count fixed at three and changes the physical representation, the arrangement of bits in memory, so that the representation matches what the hardware can move efficiently. The model is the same. The file is the same size. The bytes are just in a different place.
+The second obstacle is the cost of the lookups themselves. FLUTE's answer is vectorised lookup. Instead of a table of sixteen single values, it builds a table indexed by pairs of codes. At four bits, sixteen possible codes means two hundred and fifty-six possible pairs, and each entry holds two half-precision values packed into one thirty-two-bit word. That table is a little over a kilobyte, still small enough for shared memory, and now one lookup returns two decoded weights at once. The number of lookups per weight halves, which matters a great deal when lookups were already sitting on the critical path.
+But that creates the third obstacle, which is bank conflicts. A two-hundred-and-fifty-six-entry table spreads across all thirty-two banks, and with data-dependent indices, threads collide. With a single copy of the table, FLUTE's authors describe up to eight-way conflicts at four bits. Their answer is duplication: keep several copies of the table, placed so that different threads tend to read from different banks. Shared memory is a scarce resource, so the number of copies is a tuned trade-off, not a fixed rule. You spend a little on-chip memory to buy back lookup throughput.
+There is one more piece, and it is about keeping the whole chip busy. At small batch sizes, and especially after compression shrinks the weight matrix, a matrix multiplication may not have enough independent output tiles to give every streaming multiprocessor its own work. Some of the chip sits idle. FLUTE uses a work decomposition called Stream-K, which splits the long inner dimension of the product across processors, so that several processors each compute part of one output tile and then combine their partial sums. The combining is done carefully: partial sums accumulate in thirty-two-bit precision in registers but are written out in sixteen-bit to save memory traffic. It is one more place where saving bytes shaped a decision.
+Finally, FLUTE pairs the kernel with a small refinement to the format. Its "learned normal-float" variant learns one scale factor per tensor on calibration data and folds it into the existing group scales, so the stored format and the kernel are completely unchanged. At four bits on an eight-billion-parameter Llama model, the perplexity it reports is within about a tenth of the unquantized model.
+So what does all this buy? At the level of the kernel, FLUTE reports speedups of two to four times over the existing kernels for lookup-table formats, at batch sizes below about thirty-two, sometimes approaching the four-times ceiling. End to end, generating with an eight-billion-parameter model at four bits and batch size one, it roughly doubled throughput on an A6000 workstation card. At three bits, the gain on that card reached about two and a half times.
+And then there is a result I want you to notice, because it foreshadows the rest of the lecture. On the A100, a card with much faster memory, the same four-bit model gained only about a third. Same kernel, same format, same model. Faster memory means each byte saved is worth less, and the decode costs, which do not shrink with the memory, become a larger share of the total. Compression and compute trade places depending on the hardware.
+FLUTE's authors are candid about the limits. The kernel was tuned for the Ampere generation, and the newer H100 was not yet optimised. Below a batch of sixteen, inputs have to be padded to fit the tensor-core tile shape. Performance falls off at larger batches. It was still behind the best uniform four-bit kernels on the A100. And its configurations were tuned per matrix shape. Most interestingly, the authors end by asking for hardware changes: support for multiplying mixed data types directly, and faster indexing of small tables. We will come back to that request.
+## The same move, elsewhere
+FLUTE is a clean example, but the move it makes, changing the physical representation to suit the hardware without changing what the model means, shows up again and again.
+Consider six-bit weights. A team at Microsoft built a kernel, called FP6-LLM, for six-bit floating-point weights, and ran into exactly the alignment wall we described: six bits do not divide the natural load sizes. Their solution was to split each six-bit weight ahead of time into a two-bit piece and a four-bit piece, stored in separate, aligned regions, in exactly the order the warp would consume them. Then they dequantized four weights at a time within a thirty-two-bit register, using bit-parallel tricks. Same idea as FLUTE's three-bit split, arrived at independently. Their measurements showed the arithmetic units going from being badly under-used to several times better utilised, and the kernel running at about twice the speed of half precision.
+Consider two-bit codebook methods, where the gap between a good decoder and a bad one is widest. These methods, which include QuIP-sharp, AQLM and QTIP, quantize groups of weights together as vectors from a codebook, which is how they preserve quality at just two bits per weight. But a codebook is a lookup table, and the size of that table decides everything. QuIP-sharp built its codebook from a lattice with so much symmetry that a codebook of sixty-five thousand entries can be decoded from a table of just two hundred and fifty-six, about a kilobyte, small enough to sit in the fastest on-chip cache. QTIP went further and designed its codes so that each weight can be computed from its bits in two or three ordinary instructions, with an optional two-kilobyte table replicated thirty-two times to avoid bank conflicts. These methods reach a large fraction of peak memory bandwidth. AQLM's most accurate mode, by contrast, uses a codebook of about a megabyte per layer, which does not fit in fast cache, and we will see in a minute what that costs.
+Consider the central processor world, where there are no tensor cores at all. T-MAC, which runs low-bit models on laptops and phones, splits weights into one-bit planes and keeps a sixteen-entry table in a single vector register, using the processor's own table-shuffle instruction to do the lookups. It reports kernel speedups of several times over a strong baseline. And, in a detail that makes the whole point of this lecture in one line, without its memory-layout work it was up to about seventeen percent slower than that baseline. The lookup idea alone was not enough. The layout made it work.
+And even for the most ordinary format of all, uniform four-bit integers, the kernel dominates the outcome. When the original GPTQ authors rewrote their three-bit kernel, the speedup of the same quantized model on the same hardware went from about one point nine times to about three and a quarter. Same bits, same model. Different kernel, different result.
+## When smaller is slower
+Now for the claim that sounds most surprising: sometimes a slightly larger representation is actually faster. Here is the evidence.
+Start with the starkest case. AQLM at two bits, in its most accurate mode with the megabyte-sized codebook, moves roughly seven or eight times fewer weight bytes than half precision. Yet on a consumer graphics card, with its purpose-built kernel, it generated only about twenty percent faster than half precision. And in one widely used general-purpose implementation, measured by another research group on a different consumer card, it was actually slower than half precision: about twenty tokens per second against about thirty-three. The reason given was simple: the codebook is too big to fit in the fast cache, so every lookup goes further out into the memory hierarchy. When AQLM's authors switched to a mode with two small codebooks that do fit, the speed nearly doubled, at the cost of slightly lower accuracy. Same bit width. The representation, not the bit count, decided the speed.
+Next, three bits versus four bits, in the popular llama dot c-p-p block formats. On a seven-billion-parameter model on a consumer graphics card, the three-bit variant, although its file was about a fifth smaller, took about eighteen and a half milliseconds per token, against about fifteen and a half for the four-bit variant. On a laptop processor the gap was larger still. And comparing two three-bit formats with exactly the same number of bits per weight, one based on a codebook needing several table loads per register ran at less than half the speed of the simpler one.
+Next, six bits versus four bits. In the FP6-LLM measurements on an A100, the six-bit kernel ran a few percent faster than a well-known production four-bit kernel at batch sizes of eight and sixteen. Fifty percent more bits, slightly less time.
+Next, going below four bits for activations as well as weights. The team behind QServe put it bluntly: reducing bit precision does not necessarily speed up inference. They found that a published four-bit weight and four-bit activation system ran twenty to twenty-five percent slower than production systems using four-bit weights with sixteen-bit activations, or eight-bit weights and activations. The reason was the one we already know: in the four-bit-everything scheme, partial sums had to be dequantized inside the main loop, on the slow general-purpose units. By their accounting, one operation on those units costs as much time as fifty four-bit tensor-core operations. They found the same pattern for the attention cache: a naive four-bit cache was about a fifth slower than an eight-bit one.
+And there is a fair counterexample, which is just as instructive. For the ExLlama family of kernels, lower bit rates really are faster: three bits per weight beats four, which beats five, on the same consumer card. That is not a contradiction. It is the thesis working in the other direction. Those kernels were built for those formats. When the representation and the kernel are designed together, fewer bits do mean more speed. The trouble only starts when the format is chosen for size and the kernel is left to cope.
+## When batching changes the answer
+Everything so far assumed a single user and a batch size of one. That is where weight quantization shines, because decoding is so deeply memory bound. But real serving systems batch many requests together, and batching changes the arithmetic.
+When a batch of several sequences shares one pass over the weights, each weight fetched from memory is used once per sequence. The arithmetic intensity rises in proportion to the batch size. With sixteen-bit weights on an H100, you would need a batch of roughly three hundred before the matrix multiplications stop being memory bound.
+Now here is the irony. Compressing the weights to four bits divides the bytes by four, which multiplies the arithmetic intensity by four. So the batch size at which you hit the compute ceiling drops by four, to around seventy-five. Compression makes you compute bound sooner. And once you are compute bound, the bytes you saved no longer matter, but the decode instructions you added still do. At that point the dequantization overhead is pure cost.
+You can watch this happen in the measurements. Marlin gets close to the ideal four-times speedup up to batch sizes of about sixteen to thirty-two, then its advantage shrinks steadily, to about one and a half times at a batch of one hundred and twenty-eight. In a full serving system, on a seven-billion-parameter model, the end-to-end gain went from nearly three times at batch one to about one point two times at a batch of one hundred and twenty-eight. The QServe team's roofline analysis puts the crossover on an A100, where four-bit weights with sixteen-bit activations stop beating eight-bit weights with eight-bit activations, at under about eighty concurrent sequences. And one kernel library states outright that once compute bound, four-bit weight-only kernels are no faster than plain half precision.
+Prefill is the extreme case. When a model processes a long prompt, the whole prompt is one enormous batch, and the work is compute bound from the start. In one measurement of a thirteen-billion-parameter model processing prompts on an A100, half precision processed about two hundred and thirty tokens per second, a common four-bit format about a hundred and seventy, and another about a hundred and forty. The compressed models were slower, because in the compute-bound regime you only pay for decoding and gain nothing from the saved bytes.
+So the right representation depends on the regime. A format that is excellent for single-user decoding can be the wrong choice for a heavily batched server or for prompt processing. The executable representation is not a property of the model alone. It is a property of the model, the hardware, and the workload together.
+## Hardware that speaks the format
+All of this has been about software working around the hardware. The last few years show the hardware moving towards the software.
+The most important step is block-scaled floating point. An industry group published the microscaling formats: small floating-point elements, in eight, six or four bits, grouped into blocks of thirty-two elements that share a single eight-bit power-of-two scale. The four-bit version costs four and a quarter bits per element once the scale is counted. NVIDIA's Blackwell generation adds its own four-bit variant with blocks of sixteen elements, an eight-bit floating-point scale per block, and a single thirty-two-bit scale per tensor, which comes to about four and a half bits per element.
+What makes these formats different from everything we have discussed is not their bit count. It is that the tensor cores consume them directly. On Blackwell, the matrix instruction reads the packed four-bit elements and applies the block scales inside the instruction itself. There is no unpacking on the slow general-purpose units, no two-instruction budget, no magic-number trick. The decode cost goes to essentially zero because the decoder is now part of the tensor core. And because the multiplication itself happens at four bits, the arithmetic rate goes up too: on NVIDIA's own figures for its B200 systems, four-bit tensor throughput is twice eight-bit, which is twice sixteen-bit. The newest parts push four-bit to three times eight-bit, while cutting eight-bit integer throughput sharply, which tells you where the hardware makers think the future is: block-scaled floating point, not integers.
+There is a quieter example that makes the thesis almost literally. Blackwell's asynchronous copy engine can keep six-bit and four-bit data packed tightly in main memory, where bytes cost bandwidth, and pad each group out to an aligned hundred-and-twenty-eight-bit slot as it copies into on-chip shared memory, where the tensor cores need regular addresses. That is exactly the split we have been describing: compact where you pay for bytes, aligned where you pay for access, with the conversion happening in the data path. The hardware designers built FLUTE's lesson into the copy engine.
+Researchers have also proposed going further. The LUT Tensor Core proposal, evaluated in simulation rather than silicon, designs a tensor core around table lookups over activation partial sums, the second kind of lookup kernel we mentioned earlier. It reports a unit about a sixth the area of a conventional tensor core and large speedups for very low-bit weights. Whether that idea reaches production is open. But notice that it answers FLUTE's closing request for hardware that indexes small tables quickly and multiplies mixed types directly.
+The trend is clear. The formats that win in the long run are the ones hardware can consume directly. And the formats hardware chooses to consume are the ones whose decode is cheap: power-of-two element sizes, simple shared scales, small blocks. That is the same set of properties the best software kernels have been fighting to achieve.
+## A design rule for our own hardware
+So let's turn this into a rule we can use, whether we are choosing a format for an existing processor, writing a kernel, or designing our own hardware.
+The wrong question is: what is the lowest bit width we can support? That question optimises the file, and we have seen repeatedly that the file is not what runs.
+The better question is: what representation moves the fewest bytes per useful computation, while still being cheap to decode? Let me unpack that into a checklist.
+First, count every byte. Bits per weight must include scales, zero points, codebooks, outlier indices, and padding. A nominal three-bit format with heavy metadata may move as many bytes as a clean four-bit one.
+Second, check the decode budget. At the memory-bound operating point, how many instructions per weight can the decode spend before it becomes the bottleneck? On current data-centre graphics processors, the answer is a couple of cheap operations. If a format needs table lookups, big codebooks, or conversions, measure whether it fits.
+Third, respect the native grain. Element sizes that divide the natural load sizes are cheap. For sizes that don't, bit-slicing into power-of-two streams, as FLUTE and FP6-LLM do, beats both end-to-end packing and padding.
+Fourth, lay out for the consumer. Store weights in the order the compute unit wants them, arranged offline for the memory transaction size, the warp, and the matrix instruction's fragment layout. The natural order of the original matrix is irrelevant at run time.
+Fifth, keep tables small, and on the fast side of the memory hierarchy. A table that fits in registers or a single bank-friendly slice of shared memory is fast. A table that spills out of cache can erase the benefit of compression. Replicate tables to avoid bank conflicts if you can afford the space.
+Sixth, know your regime. Single-user decoding rewards compression almost linearly. Heavy batching and prompt processing are compute bound, and there the decode overhead is pure cost, unless the hardware multiplies in the compressed format directly.
+And seventh, if you are designing the hardware, give it the decoder. Native block-scaled formats, mixed-input matrix instructions, fast small-table indexing, and copy engines that repack data on the way on-chip are what turn a clever format into a free one.
+Put all of that together and you get the sentence this lecture has been building to. Sometimes a slightly larger representation is faster, because it aligns better with the hardware: six bits that decode in a couple of instructions beat four bits that need a pile of them; four bits with a small table beat two bits with a big one; a plain four-bit format that the tensor core reads directly beats a cleverer one that it cannot. The goal is not the smallest model. The goal is the cheapest executable representation.
+## What to remember
+Let me close with the key ideas, and then some questions to test yourself.
+Decoding a single token is memory bound by more than two orders of magnitude, so bytes moved per token set the speed limit. Quantization lowers that limit, but only if the compressed bytes can be consumed efficiently. Every byte counts, including metadata. The decode step lives on the slow general-purpose units and has a budget of roughly two cheap operations per weight. Memory is read in aligned chunks of fixed sizes, so bit widths that do not fit those chunks need either bit-slicing or padding. Tensor cores need data in a fixed register layout, so weights should be arranged offline. Lookup tables in shared memory are limited by bank conflicts and throughput. FLUTE combines bit-sliced three-bit storage, paired lookups, duplicated tables, and careful work splitting to make lookup formats fast. The same ideas appear in six-bit kernels, in lattice and trellis codebooks, and on laptop processors. Smaller formats can be slower when their decode is expensive, and batching erodes the advantage of weight-only compression. Hardware is converging on block-scaled formats that the tensor cores consume directly.
+Now, ten questions, with brief answers after each.
+One. Why is single-user decoding memory bound? Because a matrix-vector product does about one operation per byte of half-precision weights, while the processor can do a few hundred operations per byte of bandwidth.
+Two. Roughly what speed ceiling does bandwidth impose on an eight-billion-parameter model in half precision on a high-end data-centre card, and what happens at four bits? About two hundred tokens per second at sixteen bits, rising to about eight hundred at four bits, before real-world efficiency losses.
+Three. Why is a four-bit model rarely four bits per weight? Because scales, zero points, codebooks and outlier indices add metadata, typically an eighth to a half of a bit per weight or more.
+Four. Why is dequantizing in a separate kernel so harmful? Because it writes the expanded weights back to memory and reads them again, which moves more bytes than not quantizing.
+Five. What is the decode budget per weight, and why is it so small? A couple of cheap integer operations, because decoding runs on the general-purpose units, which are an order of magnitude slower than the tensor cores.
+Six. Why are three-bit weights awkward to load, and how does FLUTE solve it? Three does not divide the natural load sizes, so values straddle words; FLUTE splits each code into a one-bit stream and a two-bit stream, each of which loads cleanly, and reassembles them in registers.
+Seven. What problem does FLUTE's paired lookup table solve, and what problem does it create? It halves the number of lookups by returning two values per read; the larger table causes shared-memory bank conflicts, which FLUTE reduces by duplicating the table across banks.
+Eight. Why did the same FLUTE kernel give a much smaller speedup on the A100 than on the A6000? Because the A100's faster memory makes each saved byte worth less, so fixed decode costs become a larger share of the total.
+Nine. Give an example where a lower-bit format ran slower than a higher-bit one, and explain why. AQLM's most accurate two-bit mode barely beat, or even lost to, half precision because its large codebook did not fit in fast cache; or llama dot c-p-p's three-bit format ran slower than its four-bit format because of its more complex decode.
+Ten. What question should replace "what is the lowest bit width we can support?" What representation moves the fewest bytes per useful computation while still being cheap to decode, on this hardware, for this workload.
+That is Lecture 1a. Next time, in Lecture 1b, we will look closely at trellis quantization, one of the formats designed from the start around cheap decoding. Thanks for listening.

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+# Trellis Quantization: Trading Memory for Cheap Compute
+### Lecture 1b in the Quantization and Kernels series
+*Approx. 65 minutes spoken. Written to be listened to: numbers are rounded and said in words, the few formulas are described rather than written, and benchmark figures are the ones reported by the paper authors and project maintainers, on the hardware they name. The lecture builds from the hardware up. First why moving bytes is the expensive part of generating a token, then how quantization has tried to move fewer of them, then the trellis idea itself, and finally what happened when two community projects tried to make it fast on real machines.*
+---
+## Cold open
+Here is a strange trade to consider. Suppose you could make a large language model smaller in memory, but only by making the processor do more work every time it reads a weight. Not a little more work, either. Instead of reading a number and using it, the processor would read a short string of bits, run it through a tiny pseudo-random number generator, massage the result with some bit tricks, and only then have the weight it wanted.
+On the face of it, that sounds like a bad deal. We are adding arithmetic to every single weight in a model with tens of billions of them.
+And yet, on a modern graphics card generating one token at a time, this trade can make the model faster. Not just smaller, faster. The reason is that during that kind of generation, the processor's arithmetic units are mostly sitting idle, waiting for memory. Work that fits inside that idle time is close to free. Bytes you do not have to move are not free at all.
+That is the idea behind today's subject: trellis quantization, as introduced by a paper called QTIP from Cornell, and as adapted by two community projects, ExLlamaV3 and ik llama dot cpp. We will see that the idea works beautifully on some machines and poorly on others, and that the difference tells us something general. The lesson is not "use trellis quantization." The lesson is that if your hardware has spare integer or bit manipulation capacity, you may be able to spend it to move far fewer bytes. And if you get to design the hardware yourself, that trade might be worth building in.
+We will get there in steps. First the systems side: why generating a token is limited by memory, and how much spare arithmetic is really lying around. Then the software side: how quantization has evolved, why low-bit formats hit a wall, and how a trellis gets past it. Then the practice: what the community found when they ran it on real graphics cards, CPUs, and Apple chips.
+## Part one — the memory wall at batch one
+Let's start with what a language model actually does when it produces one token for one user. People call this batch-one decoding.
+Almost all of the work in a transformer layer is matrix multiplication. When you are processing a single token, each of those multiplications has a very particular shape: a big weight matrix times a single vector. That is called a matrix-vector product. Every weight in the matrix gets read from memory, multiplied by one number from the input vector, added into a running sum, and then never touched again for the rest of that token.
+Count what that costs. Each weight gives you two floating point operations, one multiply and one add. If the weight is stored in sixteen-bit floating point, that is two bytes. So you get two operations per two bytes, or one operation per byte moved. That ratio, operations per byte, is called arithmetic intensity. There is a handy rule of thumb for it here: the arithmetic intensity is roughly sixteen divided by the number of bits per weight. Sixteen-bit weights give you one. Four-bit weights give you four. Two-bit weights give you eight.
+Now compare that to what the hardware can do. The standard way to reason about this is the roofline model, from Williams, Waterman, and Patterson in two thousand and nine. The idea is simple. A processor has a peak rate of arithmetic and a peak rate of memory bandwidth. The speed you actually get is the smaller of two things: the peak arithmetic, or the bandwidth multiplied by your arithmetic intensity. The point where those two limits meet is called the ridge point, and it is just peak arithmetic divided by bandwidth.
+Take a consumer card, the RTX forty ninety. It has roughly one terabyte per second of memory bandwidth, and something like a hundred and sixty-five trillion half-precision tensor operations per second. Divide one by the other and the ridge sits at around a hundred and sixty operations per byte. A data centre H one hundred has more than three times the bandwidth, but also far more arithmetic, so its ridge is up near three hundred.
+Batch-one decoding with sixteen-bit weights lives at an arithmetic intensity of one. Even with two-bit weights, it lives at eight. That is a tiny fraction of the ridge on every machine that matters. In roofline terms, you are deep on the sloped, memory-bound side of the roof. The arithmetic units could do fifty or a hundred times more work than you are asking of them, and it would not change the speed at all, because they are waiting on memory.
+This gives a clean upper bound on generation speed. Since every weight has to be read once per token, the best possible tokens per second is the memory bandwidth divided by the size of the weights. Let's make that concrete with a seventy-billion-parameter model on that forty ninety. In sixteen-bit form the weights are a hundred and forty gigabytes, which does not fit at all, and even if it did, you would be capped at about seven tokens per second. At four bits it is thirty-five gigabytes, still too big for a twenty-four gigabyte card. At two bits it is seventeen and a half gigabytes, it fits, and the ceiling rises to nearly sixty tokens per second.
+So in this regime, the number of bits per weight is the speed. Halve the bits and you roughly double the ceiling. That is why so much effort goes into squeezing weights below four bits, where things get genuinely hard.
+## Part two — bytes are the expensive part
+There is a second way to see the same wall, and it matters especially for anyone designing hardware: energy.
+In twenty fourteen, Mark Horowitz gave a well-known talk at the solid state circuits conference titled "Computing's energy problem." Its numbers, for an older forty-five nanometre process, have been reproduced in countless papers since. A thirty-two-bit integer addition costs about a tenth of a picojoule. A thirty-two-bit integer multiply, about three picojoules. A thirty-two-bit floating point multiply, a little under four. Reading thirty-two bits from a small on-chip memory, about five. And reading thirty-two bits from off-chip DRAM? About six hundred and forty picojoules.
+Sit with that ratio. Fetching a word from main memory costs roughly six thousand times as much energy as adding two integers, and a couple of hundred times as much as multiplying them. Song Han's group summarised it as memory access being three orders of magnitude more expensive than simple arithmetic.
+Modern memory is better, but the gap persists. Measurements from NVIDIA researchers put graphics memory of the GDDR5 generation at around fourteen picojoules per bit, and stacked high-bandwidth memory at around four picojoules per bit. Either way, a sixteen-bit weight fetched from DRAM costs tens to hundreds of picojoules, and a two-bit weight costs an eighth of that. The savings from not moving those fourteen extra bits could pay for dozens of simple integer operations.
+There is a caveat, and it will come back later. On a general-purpose processor, the cost of an instruction is not just its arithmetic. It is also fetching the instruction, decoding it, reading and writing registers, and scheduling it. Horowitz estimated that overhead at tens of picojoules per instruction on a conventional CPU, which dwarfs the add itself. Graphics cards and vector units amortise that overhead across many lanes at once. And a fixed-function hardware decoder removes it almost entirely. So the question "is decoding cheaper than moving bytes?" has a different answer depending on how the decoding is done. Hold on to that.
+## Part three — the idle integer units
+Let's be more precise about the spare arithmetic, because "the processor is idle" is too vague to design around.
+A modern NVIDIA streaming multiprocessor has separate pipelines for different kinds of work. There are floating point pipelines, there are tensor cores for matrix math, and there are integer pipelines. On recent generations, including the Ampere consumer cards, Ada, and Hopper, the integer pipe can issue sixty-four thirty-two-bit integer operations per clock per multiprocessor. And the important detail is that a full thirty-two-bit integer multiply-add runs at that same rate as a simple integer add. Multiplication is not a second-class citizen on these chips.
+There are also some unusual instructions that turn out to matter. One is called LOP3. It computes any logical function of three inputs in one instruction, chosen by an eight-bit lookup code. So "mask these bits, then flip these others" can be a single operation. There is a byte permute instruction. There are bit-field extract and insert operations. And there is a family of small integer dot product instructions, the best known being one called dp4a, which takes four bytes from one register and four bytes from another, multiplies them in pairs, and adds all four products into an accumulator, in one go.
+Now let's do a budget. Take the forty ninety again. It has a hundred and twenty-eight multiprocessors, each issuing sixty-four integer instructions per clock, at around two and a half gigahertz. That is about twenty trillion integer instructions per second. Meanwhile, at two bits per weight, its terabyte per second of bandwidth delivers about four trillion weights per second. Divide one by the other: you can afford roughly five integer instructions per weight before the integer pipe becomes the bottleneck, and you get a similar number of floating point slots on top of that.
+Do the same sum for the H one hundred and something interesting happens. It has more bandwidth, so it delivers far more weights per second, but its integer throughput is not proportionally higher. The budget drops to a little over one integer instruction per weight. Keep that in mind, because the faster the memory, the tighter the decoding budget becomes. A trick that is free on a consumer card can become the bottleneck on a data centre card with faster memory.
+There is one more wrinkle on NVIDIA hardware. Converting an integer to a floating point number with the native conversion instruction is slow, a quarter the rate of ordinary integer work. That is why quantization kernels have long used a trick, described by Kim and colleagues at Microsoft in twenty twenty-two and used in the widely deployed Marlin kernel. You take the few bits of a small integer and use a single LOP3 to splice them into the mantissa of a carefully chosen half-precision constant. The result is a valid floating point number equal to a known offset plus your integer. One subtraction removes the offset. No conversion instruction needed. We will see exactly this style of bit trickery at the heart of the trellis decoder.
+So the systems picture is this. At batch one, memory is the wall. Arithmetic, and integer arithmetic in particular, is plentiful but finite, and the exact budget depends on the ratio of integer throughput to bandwidth on each chip. Now let's look at how software has tried to exploit that.
+## Part four — the scalar grid and where it breaks
+The simplest form of weight quantization is scalar. You take each weight on its own and round it to the nearest point on a small grid of allowed values, with a scale factor shared by a group of weights. That is round to nearest. At four bits, with sensible group sizes, it holds up. At two or three bits it falls apart.
+Two famous improvements kept the scalar grid but got smarter about rounding. GPTQ, from Frantar and colleagues, quantizes a layer one column at a time. It uses a sample of real activations to estimate how sensitive the layer's output is to each weight, a quantity we call the proxy Hessian. After rounding each column, it pushes the rounding error onto the columns that have not been rounded yet, so later choices compensate for earlier ones. AWQ, from Lin and colleagues, notices that a small fraction of input channels carry large activations and matter far more than the rest. It scales those channels up before quantizing, and folds the inverse scale into the activations, so the important weights get a finer effective grid.
+Both are excellent, and at four bits they are hard to beat for the price. But neither can escape a basic geometric fact about rounding one number at a time.
+Think of each weight as a point on a line. A scalar quantizer chops the line into intervals and replaces each point with the centre of its interval. Now picture two weights at once, as a point in a plane. Two independent scalar quantizers chop the plane into little squares. In three dimensions, cubes. The question is: how efficient are cubes at covering space? And the answer is: not very. For a fixed number of cells, cubes leave more distance, on average, between a point and its cell centre than rounder shapes would.
+Information theory tells us exactly how much we are leaving on the table. If we could use perfectly spherical cells in very high dimensions, the ultimate improvement over cubes is a factor of two pi e over twelve in mean squared error, which is about one and a half decibels, or roughly a quarter of a bit per weight. That is called the granular gain, and a quarter of a bit per weight sounds small until you remember that at two bits per weight, it is a twelve and a half percent budget increase for free. And at low rates there is an additional gain from placing the codepoints where the weights actually are, which is even larger.
+To collect that gain, you have to stop quantizing one weight at a time.
+## Part five — vector quantization and the codebook explosion
+Vector quantization quantizes a group of weights together. You pick a codebook, a list of allowed vectors, and for each group of, say, eight weights, you store the index of the closest codebook vector. At two bits per weight and eight weights per group, that index is sixteen bits long, so the codebook has sixty-five thousand five hundred and thirty-six entries.
+That works, and it is how the strongest low-bit methods of twenty twenty-four got their results. But notice the problem. The codebook size is two to the power of the bits per weight times the dimension. Eight weights at two bits is two to the sixteen. Sixteen weights at two bits is two to the thirty-two, about four billion vectors. You cannot store that, and you certainly cannot search it. Brute-force encoding costs as much as the codebook is large. So practical vector quantization has been stuck at around eight dimensions, which collects only part of the available gain.
+And even at eight dimensions, the codebook has a systems cost. AQLM, from Egiazarian, Alistarh, and colleagues, uses learned additive codebooks. In its typical two-bit setting, one codebook of sixty-five thousand entries, each eight half-precision values, comes to about a megabyte. That does not fit in the small, fast memory next to the arithmetic units. So during decoding, every group of weights triggers a lookup into a table that lives in slower memory, and those lookups collide with each other. In the QTIP paper's measurements, a two-bit AQLM model of seven billion parameters ran at about eighty tokens per second on a card where the uncompressed model ran at about fifty-six. Faster than full precision, but far below what the reduced size should allow.
+This is a systems lesson worth pausing on. The graphics card's shared memory is split into thirty-two banks. If two threads in a group hit the same bank at once, they are serialised. A codebook with hundreds or thousands of entries, randomly indexed, produces exactly those collisions. A study of vector quantization kernels presented at the high performance computer architecture conference in twenty twenty-five found that simply parking whole codebooks in shared memory cost more than thirty percent of compute utilisation through lost occupancy. Lookup tables are not free just because they are on chip.
+QuIP sharp, from the same Cornell group that later produced QTIP, found a clever way around the table size. It used the E8 lattice, the densest known packing of spheres in eight dimensions. Because the lattice is so symmetric, you can generate all sixty-five thousand codewords from just two hundred and fifty-six stored vectors plus sign flips and a small shift. The stored part is about one kilobyte and fits in the fastest cache. QuIP sharp reached over a hundred and eighty tokens per second for a two-bit seven-billion-parameter model on that same card. But it was still eight dimensions. To go higher, you need a structure that does not need a table at all.
+## Part six — making weights look Gaussian
+Before we get to that structure, we need one more ingredient, because it is what makes everything after it possible.
+Real weight matrices are messy. Most weights are small, but a few are large, and some channels are much larger than others. A fixed codebook designed for one distribution will fit these poorly. The Cornell group's answer, introduced in the original QuIP paper and refined in QuIP sharp, is called incoherence processing.
+Here is the idea. Take the weight matrix and multiply it on both sides by random orthogonal matrices. Orthogonal means they rotate without stretching, so they can be undone exactly. After this random rotation, every entry of the new matrix is a mix of many original entries. Outliers get smeared across the whole matrix. By a central limit argument, the rotated weights look very much like independent draws from a bell curve, a Gaussian. In QuIP sharp, the rotation is a randomised Hadamard transform: a Hadamard matrix, which only contains plus and minus ones, combined with random sign flips. It can be applied in time proportional to n log n, so the rotation itself is cheap, and at inference time it can be applied to the activations instead of the weights.
+This matters for two reasons. The first is quality: no outliers means no weight gets a terrible rounding error. The second is the one that matters for us. Once every weight matrix looks like it came from the same Gaussian, you no longer need a codebook tailored to each layer. You can design one quantizer for Gaussian data and use it everywhere. And a quantizer designed for a known, fixed distribution can be generated rather than stored.
+Hold that thought. We now have all the pieces on the software side: a need for high-dimensional quantization, a problem with codebook size, and a guarantee that the data is Gaussian. The missing piece comes from an unexpected place: nineteen-eighties modem design.
+## Part seven — a trellis, borrowed from modems
+In the early nineteen-eighties, Gottfried Ungerboeck showed how to transmit more reliably over noisy telephone lines using what he called trellis-coded modulation. In nineteen ninety, Michael Marcellin and Thomas Fischer turned the idea around. Their paper, "Trellis Coded Quantization of Memoryless and Gauss-Markov Sources," pointed out that transmitting signals and compressing signals are dual problems. The same structure that makes a signal robust to noise can make a quantizer efficient.
+Here is what a trellis is, in words. Picture a machine with a fixed number of states. At each step, you are in some state, and you spend a few new bits to choose which way to go next. Each choice leads to a new state and produces one output value. After many steps, the sequence of bits you spent has traced a path through the states, and the sequence of output values along that path is your reconstruction.
+Now think about what that gives you. The set of all possible paths over, say, two hundred and fifty-six steps is a codebook of two hundred and fifty-six-dimensional vectors. It has an astronomically large number of codewords, yet you never store them. They are implied by the state machine. The trellis is a way to get the benefits of a huge vector quantizer with the bookkeeping of a small one.
+How do you find the best path for a given sequence of weights? That is the job of the Viterbi algorithm, the dynamic programming method that decodes convolutional codes in every phone. You walk through the sequence one step at a time. For each state, you remember only the single best path that ends there, and its total error. At the next step, each state looks at the few states that can lead into it, picks the best, and discards the rest. When you reach the end, you pick the best final state and trace back. The cost grows linearly with the length of the sequence and with the number of states, instead of exponentially with the dimension.
+How good is it? For a Gaussian source, the granular gain of trellis-coded quantization grows with the number of states. With a few states it already beats small lattices. With two hundred and fifty-six states it gets within about a sixth of a decibel of the one and a half decibel limit, which is better than even the twenty-four-dimensional Leech lattice, one of the most celebrated objects in mathematics. And encoding stays linear in length.
+So why was this not used for language models before twenty twenty-four? Two reasons, both systems reasons. First, a general trellis needs its structure stored: which state goes where on each choice of bits, and which output value each edge produces. For the large number of states you want, those tables are too big for fast inference. Second, and worse, decoding is sequential. To know which state you are in at step one hundred, you have to walk the path from step one. A graphics card wants to decode thousands of weights independently, in parallel, in whatever order its matrix tiles need them. A trellis that must be walked from the start is useless for that.
+## Part eight — the bitshift trellis
+This is the central idea of QTIP, by Albert Tseng, Qingyao Sun, David Hou, and Christopher De Sa, presented at NeurIPS in twenty twenty-four.
+QTIP picks a trellis whose structure is so simple that it does not need to be stored, and where every step can be decoded independently. They call it the bitshift trellis.
+Here is the construction. The state is simply a window of sixteen bits, which means sixty-five thousand five hundred and thirty-six possible states. To take one step, you shift the window over by k bits, dropping the oldest k bits off one end and letting k new bits in at the other. At two bits per weight, each step shifts in two new bits. That is the entire transition rule. The next state is the current state shifted, plus the new bits.
+Now look at what this means for the compressed data. Lay all the bits for a sequence of weights end to end in one long string. The state at any step is just a sixteen-bit window into that string, starting at a position you can compute directly. To decode the hundredth weight, you do not walk from the first. You jump straight to bit two hundred, read sixteen bits, and you have the state. Every weight depends only on a contiguous sixteen-bit window of the stream. Adjacent weights share fourteen of their sixteen bits, and moving from one to the next is just a shift.
+That solves both problems at once. The structure of the trellis costs nothing to store, because it is implied by bit shifting. And decoding is random access and fully parallel: every thread in a graphics card can decode its own weights, from its own window, with no dependence on any other thread.
+QTIP applies this to tiles of sixteen by sixteen weights, two hundred and fifty-six weights per trellis sequence, which lines up neatly with the sixteen by sixteen tiles that tensor cores operate on. So the effective dimension of the quantizer is two hundred and fifty-six, compared with eight for the E8 lattice. Thirty-two times larger.
+There is one more subtlety worth knowing about. A trellis path has to start somewhere, and naively you would need to store an extra sixteen-bit starting state for every sequence, which is wasteful. QTIP instead uses a tail-biting trellis: the path wraps around, so the final window overlaps the initial one and the bitstream is treated as a circle. That makes every sequence exactly two bits times two hundred and fifty-six weights, with no overhead. Finding the optimal wrap-around path exactly is expensive, so QTIP uses a neat approximation. Rotate the sequence by half its length, run Viterbi, read off the bits in the middle, then run Viterbi again on the original sequence, constrained to start and end with those bits. Two passes, near-optimal result.
+The encoding side is expensive but tolerable. Viterbi with sixty-five thousand states over each tile is a lot of work, but it is done once, offline, when the model is quantized, and it parallelises well on a graphics card. It is also why this is a weight-only method. Nobody is running sixty-five-thousand-state Viterbi on activations or on the key-value cache while serving.
+## Part nine — a codebook made of instructions
+We have a trellis with no stored structure. But each state still needs an output value: the reconstructed weight. With sixty-five thousand states, the obvious approach is a lookup table of sixty-five thousand half-precision numbers, which is a hundred and twenty-eight kilobytes. Too large for the fastest on-chip memory, and full of bank conflicts. We would be back to AQLM's problem.
+This is where incoherence processing pays off. Because the rotated weights are Gaussian, the output values do not need to be learned for each layer. They just need to look like a good spread of Gaussian samples. And a spread of pseudo-random Gaussian-looking numbers is something you can compute from the state with a few instructions, instead of looking up.
+QTIP calls these computed codes, and it offers three. Let me describe the most elegant one, called three-instruction, or 3INST.
+Step one: take the sixteen-bit state and run it through one step of a linear congruential generator. That is one integer multiply-add, with carefully chosen constants, producing a thirty-two-bit number whose bits are well scrambled. On NVIDIA hardware, as we saw, that is a single full-rate instruction.
+Step two: treat those thirty-two bits as two sixteen-bit halves, each of which will become a half-precision floating point number. Apply a mask that keeps the sign bit and some of the low bits of each half, and XOR in a magic constant that pins the exponent into a narrow range. Mask and XOR together are exactly the kind of three-input logic that LOP3 does in one instruction. The result is two half-precision numbers, each with a random sign and a magnitude in a bounded range. Their distribution is roughly a two-sided exponential shape.
+Step three: add the two halves together. One packed half-precision add. The sum of two such values is very close to a Gaussian.
+Three instructions, and you have a pseudo-random Gaussian-looking weight from a sixteen-bit window, with no memory access beyond reading the compressed bits. It is exactly the fast integer-to-float trick from Part three, turned into a random number generator.
+The second computed code, called one multiply-add, or 1MAD, runs the same generator, then sums the four bytes of the result. The sum of four roughly uniform bytes is roughly bell-shaped, by the central limit theorem, and it can be centred and scaled into a weight. It costs a few more instructions but is conceptually even simpler.
+The third, called HYB for hybrid, is the one QTIP actually shipped in its fastest kernels. It uses a cheap hash of the state to index a tiny table of just five hundred and twelve pairs of values, two kilobytes in total, and one bit of the hash flips a sign. Each lookup produces two weights, so the cost comes to about two instructions per weight. Two kilobytes is small enough to copy thirty-two times, once per bank, so there are no bank conflicts. And unlike the pure computed codes, the table entries can be fine-tuned.
+Here is the payoff. On a synthetic Gaussian source at two bits per weight, the best possible mean squared error, the rate-distortion bound, is one sixteenth, or about zero point zero six three. A scalar quantizer, the Lloyd-Max quantizer, gets about zero point one one eight. The E8 lattice codebook of QuIP sharp gets about zero point zero eight nine. The trellis with the three-instruction code gets about zero point zero six nine. The QTIP authors put it this way: the trellis closes the gap between QuIP sharp and an optimal two-bit quantizer by more than a factor of three. And the computed codes do essentially as well as a truly random lookup table would, while storing nothing.
+Let me restate what just happened, because it is the entire lecture in miniature. The codebook has been replaced by computation. A table that would have required memory traffic, cache capacity, and bank-conflict-free access has been turned into three instructions on units that were sitting idle anyway.
+## Part ten — what QTIP bought
+So how does it do on real models?
+On quality, the headline results are on the Llama two family, with a context length of four thousand and ninety-six, after the same fine-tuning procedure used by QuIP sharp. For the seventy-billion-parameter model at two bits per weight, the Wikitext perplexity was about three point seven for QTIP, against about three point nine for QuIP sharp and three point eight for AQLM. The full-precision model scores a little over three point one, so QTIP recovered a meaningful share of the remaining gap. For the seven-billion-parameter model at two bits, QTIP scored about five point nine against six point two for QuIP sharp. At three and four bits the improvements were smaller, as you would expect when every method is already close to full precision.
+Perhaps more striking: without any fine-tuning at all, the two-bit seven-billion model went from a perplexity of about eight point two with QuIP sharp to about six point eight with the trellis. The better quantizer alone did most of the work.
+On speed, the paper measured batch-one decoding on an RTX six thousand Ada, a workstation card with just under a terabyte per second of bandwidth. The full-precision seven-billion model ran at about fifty-six tokens per second. QTIP at two bits ran at about a hundred and eighty-eight, slightly ahead of QuIP sharp, and more than twice as fast as AQLM. At three bits about a hundred and sixty, at four bits about a hundred and forty. The authors' own summary is that QTIP matches QuIP sharp's throughput with a quantizer thirty-two times higher in dimension. The extra decoding work fit inside the idle time.
+One honest note on the seventy-billion model. At two bits it ran at about twenty-three and a half tokens per second, where the bandwidth ceiling for seventeen and a half gigabytes on that card is around fifty-five. So even this kernel was reaching a bit over forty percent of the roof. There is still a lot of overhead between "memory bound in principle" and "memory bound in practice," and we will see that gap return in the community implementations.
+The group later released a follow-up called YAQA, which improves the rounding step rather than the quantizer. It replaces the layer-by-layer error estimate with an approximation of how each layer affects the whole model's output distribution, and it reduces the divergence from the original model by about thirty percent compared with the older rounding methods. It works with QTIP's trellis. So the Cornell stack is really three separable parts: a rotation, a rounding algorithm, and a quantizer. The trellis is the quantizer.
+## Part eleven — ExLlamaV3: turning a paper into a format
+A research kernel for one family of models is not the same thing as a format people actually run. That is where community projects come in, and the most direct adaptation of QTIP is ExLlamaV3, from the developer known as turboderp. Its format, called EXL3, is described in the project's own words as a streamlined variant of QTIP.
+The core is recognisably QTIP. Weights are split into sixteen by sixteen tiles of two hundred and fifty-six weights. Each tile is a tail-biting trellis with a sixteen-bit state, and the decoder reads a sixteen-bit window that slides by k bits per weight. The bit rate per tensor can be anything from one to eight bits, and a budget allocator mixes rates across tensors to hit fractional targets like two and a quarter, or four, bits per weight overall. There is a Hessian-based rounding step with error feedback, and a fused Viterbi kernel. The practical headline is that the whole conversion runs in one pass, in a couple of minutes for small models and a few hours for seventy-billion-parameter models, on one high-end consumer card.
+The deviations are instructive, because each one is a systems decision.
+First, the rotation. QTIP rotates whole rows and columns. EXL3 rotates blocks of a hundred and twenty-eight weights along each axis. The maintainer's reasoning is that this helps kernel fusion, and it means a tensor can be split across several graphics cards at a granularity of a hundred and twenty-eight rows or columns without requantizing. A small loss of mathematical purity buys flexibility in how the model is deployed.
+Second, and more interesting, the codebook. EXL3 started with QTIP's exact three-instruction generator. Then it added a variant called MCG, which drops the additive constant from the random number generator and keeps only the multiply. Then it added one called mul1, which multiplies, then sums the four bytes of the result using the dp4a instruction, the four-way byte dot product. In mid twenty twenty-six, mul1 became the default for new models.
+Why? Here is the clever part. In mul1, the reconstructed weight is an affine function of a byte sum. And dp4a computes a sum of four byte products. So if you quantize the activations to eight-bit integers, you can compute codebook value times activation, for four bytes at once, in a single dp4a instruction. The decoding of the weight and the multiplication by the activation fuse into one integer instruction. The format evolved toward the instruction the hardware does best.
+Third, the kernel. The main matrix multiplication kernel needs an Ampere-generation card or newer. It uses asynchronous copies into shared memory and tensor core instructions of a specific shape, and the trellis decoding happens in registers, feeding the tensor cores directly. Older cards lack the right tensor core shapes and synchronisation features.
+Now, the part of this story that matters most for our lesson. Early in EXL3's life, users with RTX thirty ninety cards, the consumer Ampere generation, reported that EXL3 generation was slower than simpler formats. One user on three of those cards measured a large model at about seven tokens per second in the older EXL2 format and about three in EXL3. The maintainer's explanation was direct: EXL3 uses an algorithm that is more GPU-intensive and does not easily saturate memory bandwidth on Ampere. Simple integer formats are much easier to unpack on the fly.
+In other words, on that card the decoding did not fit inside the idle time. It became the bottleneck. And the fix, which the maintainer later described as much improved, came from finding which specific instruction was the problem. On consumer Ampere, tensor core multiply-accumulate with thirty-two-bit floating point accumulation runs at half rate, and at batch one that was dominating. Accumulating in sixteen-bit instead made batch-one generation about fourteen percent faster on the thirty ninety.
+Then consider an even more telling measurement from a user profiling the kernels. On a thirty ninety, the half-precision decoding kernel reached about eighty percent of peak memory bandwidth, which means it was properly memory-bound. On an H two hundred, a data centre Hopper card with vastly more bandwidth, the same kernel reached only about thirty percent. It was compute-bound. The eight-bit integer path, with its fused dp4a decode, made no difference on the thirty ninety, and gave about fourteen percent more end-to-end speed on the H two hundred.
+Remember the budget from Part three: about five integer instructions per weight on a consumer card, and barely more than one on a Hopper-class card. This is that budget, showing up in the wild. The same code, on a faster-memory card, runs out of decoding time. The project now even sets a different limit per architecture for when to use the integer path, precisely because the balance point differs between Ampere and Hopper.
+On quality, EXL3's published charts are persuasive at low bit rates. On an eight-billion-parameter Llama three point one model, at three bits per weight, EXL3's divergence from the original model was about a fifth of the older EXL2 format's. At four bits, it was about a quarter of EXL2's, and a little over half that of the comparable llama dot cpp i-quant. At higher bit rates, all good formats converge and the differences shrink. The maintainer is candid, too. An older version of the format notes says a faithful QTIP implementation would likely match or beat EXL3 on accuracy, and that the GGUF i-quants hold up well against state-of-the-art formats. EXL3 is a set of engineering compromises in favour of speed and practicality, and it says so.
+## Part twelve — ik llama dot cpp: one idea, many machines
+The second project takes a very different path, and it runs on far more kinds of hardware. ik llama dot cpp is a fork of llama dot cpp maintained by Iwan Kawrakow, who designed many of the quantization formats in the original project. Its trellis types are called IQ one KT through IQ four KT, at roughly one and three quarters, two and an eighth, three and an eighth, and four bits per weight.
+The first thing to know is that these are not QTIP. When he introduced them in late twenty twenty-four, Kawrakow wrote that apart from borrowing the three-instruction generator, the implementation had nothing else in common with QTIP. There is no Hadamard rotation and no tail-biting Viterbi search. Weights are organised in blocks with block scales, like other llama dot cpp formats, and each small group of weights gets a seed, found by a clustering search, that drives the generator for a few steps. You can think of it as a procedurally generated vector codebook: a trellis in name and generator, but not a sliding-window trellis like EXL3's.
+His initial verdict on quality is worth hearing: trellis-based quantization is a small improvement over the project's existing formats, but nowhere near the hype. He measured it as needing about a fifth of a bit fewer per weight for the same error. Real, but not revolutionary.
+What makes this project so useful to study is that it ran the same idea across CUDA, x86 CPUs, ARM CPUs, and Apple GPUs, and wrote down what happened on each.
+On an NVIDIA card, the original floating point generator worked well. On a forty eighty, the two-bit type ran at about a hundred and ninety tokens per second on a seven-billion-parameter model. That was a little slower than the project's simplest two-bit format, but in the same range.
+On CPUs, it was a different story, and Kawrakow predicted it. The generator produces floating point values, but fast CPU matrix kernels work on eight-bit integers. Converting every generated float to an integer costs more than the trellis saves. When the CPU port landed, its author noted, as predicted, the CPU ops are very slow. One early port generated tokens barely faster than the uncompressed model.
+So he redesigned the generator for integers. The new version multiplies the state by a constant, masks each of the four bytes of the result down to six bits, and sums the four bytes, then subtracts a fixed offset. The result is an integer between about minus a hundred and twenty-six and plus a hundred and twenty-six, roughly bell-shaped. And summing four bytes of a register is precisely what an integer dot product instruction does against a vector of ones. On NVIDIA that is dp4a. On AMD Zen four and Intel with the vector neural network extensions, there is an instruction that does eight of these at once. On ARM, the signed dot product instruction. The same idea, landing on each platform's cheap integer dot product.
+Notice the convergence. In a separate thread, a contributor proposed dropping the additive constant and using a particular thirty-two-bit multiplier. Kawrakow adopted it. That same multiplier constant is the one EXL3 locked in for its MCG codebook, and EXL3's mul1 also moved to a masked byte sum computed by dp4a. Two independent projects, starting from QTIP's floating point trick, ended up at nearly the same integer design, because that is what the hardware rewards.
+The integer redesign paid off substantially. On a Ryzen seventy-nine fifty X desktop, for an eight-billion-parameter model, token generation went from about eight tokens per second to about fourteen, and prompt processing roughly doubled. On the forty eighty it was slightly faster too, and it had a bonus: it allowed quantized integer matrix multiplication on the GPU, which avoided numerical overflow problems some models had when decoding to half precision.
+But on Apple hardware, the story went the other way. The new integer trellis was slower than the original on the Apple GPU. On the M two Max CPU, token generation for the trellis types was around ten to thirteen tokens per second, where other formats of similar size ran noticeably faster. For the one-and-three-quarter-bit type, Kawrakow did not bother to write a Metal implementation at all, because trellis performance on Metal was so low. And as of this month, the four-bit trellis type is simply turned off on Metal, with those tensors falling back to the CPU.
+His summary of the whole experience, from a discussion earlier this year, is blunt and worth quoting nearly in full. The trellis quants have good performance on a GPU. On the CPU, it depends. On Zen four or better, performance is reasonable but still lower than other types. On vanilla AVX two, it is noticeably slower. On Apple Silicon, performance is, in his word, pathetic. Elsewhere he gave the advice in one line: don't ask Apple Silicon to do too much work with a piece of data fetched from memory.
+Even on NVIDIA there is a price. One user compared four-bit formats on a thirty ninety with a twenty-seven-billion-parameter model. The trellis type had measurably better perplexity than a similar-sized non-trellis type, but generated about twelve percent slower. Their summary: quality per bit, trellis wins; speed, the simpler formats win. And Kawrakow notes that the advantage of trellis quants shrinks as bits per weight rise. At four bits, things are no longer clear-cut.
+## Part thirteen — why the same code runs differently everywhere
+Let's put the systems side and the community results together, because they explain each other.
+A trellis decoder is a short, fixed recipe: a thirty-two-bit integer multiply, some masking, and then either a floating point conversion trick or a byte sum. Whether that recipe is cheap depends entirely on how a given chip executes those particular instructions, compared with how fast it can fetch bytes.
+On recent NVIDIA graphics cards, as we saw, a thirty-two-bit integer multiply-add runs at full integer rate, LOP3 does arbitrary masking in one instruction, and dp4a sums bytes in one instruction. The integer pipe is mostly idle during batch-one generation. The recipe fits the budget. Trellis works.
+On Apple's GPUs, published microbenchmarks by the developer Philip Turner found that a thirty-two-bit integer multiply runs at a quarter of the rate of an integer add, and that shifts and bit extraction are also slow, sharing a pipeline with transcendental functions. Put that next to the bandwidth. A top Apple chip has around half a terabyte per second. By a rough estimate, at two bits per weight, that leaves room for several simple operations per weight, but less than one thirty-two-bit multiply per weight. The trellis recipe starts with a multiply. So on Apple's GPU, decoding becomes the bottleneck, not memory. And the integer redesign, which leaned harder on integer operations, made it worse there even as it made things better elsewhere.
+On x86 CPUs, the vector thirty-two-bit multiply on many Intel cores has a latency of about ten cycles, so a decode chain that depends on it stalls unless there is a lot of independent work in flight. AMD's Zen three and Zen four cores do the same multiply in about three cycles, and have the eight-way byte dot product instruction. That is exactly the split Kawrakow saw: Zen four reasonable, vanilla AVX two noticeably slower. On the other hand, a desktop CPU has only around a hundred gigabytes per second of memory bandwidth, so its per-weight compute budget is comparatively generous. That is why the CPU results improved so much once the decode used integer dot products, and why with enough cores, token generation became nearly memory-bound again.
+On ARM CPUs, a vector multiply runs at half rate, while table lookups and logic operations are cheap. That is why lookup-table methods like Microsoft's T-MAC and bitnet dot cpp do so well on ARM. They lean on the fast table lookup instruction rather than multiplies. A trellis generator leans the other way.
+And then there are the data centre GPUs, where the problem is not that integer work is slow, but that memory is so fast that the integer budget per weight shrinks to about one instruction. That is why EXL3's decode kernel was compute-bound on the H two hundred, and why the fused integer dot product path helped there and nowhere else.
+So here is the general principle, stated carefully. A compressed format has two costs: the bytes you move, and the instructions you run to reconstruct each weight from those bytes. It is fast when the second cost fits inside the time the first cost takes anyway. That depends on three things about the hardware: its bandwidth, the throughput of the specific instructions your decoder uses, and whether those instructions compete with anything else. The same format can be memory-bound on one chip and compute-bound on another. A representation is not fast or slow in the abstract. It is fast or slow on a machine.
+## Part fourteen — prefill, the other half of the bill
+Everything so far has been about generating tokens one at a time. But every request also has a prefill phase, when the model processes the whole prompt at once. And prefill is a completely different regime.
+During prefill, each weight is reused across hundreds or thousands of prompt tokens. The arithmetic intensity is multiplied by the number of tokens, which puts it far past the ridge point. Prefill is compute-bound. The integer and floating point units that were idle during generation are now busy doing the actual matrix multiplication. Every decoding instruction now competes directly with useful work.
+You can see this even with simple formats. On Apple's M four Max, in published llama dot cpp benchmarks for a seven-billion-parameter model, going from sixteen-bit weights to four-bit weights made token generation about two and a half times faster, but made prompt processing about four percent slower. Quantization pays off almost entirely in generation, and its decoding cost shows up in prefill.
+For heavy formats like the trellis, the answer both community projects reached is amortisation. Don't decode each weight per token. Decode a whole block of weights once into ordinary half-precision or thirty-two-bit floats, then run a standard high-performance matrix multiply over the block with all the prompt tokens. EXL3 reconstructs full tensors and then multiplies whenever the batch is large enough. ik llama dot cpp added a dequantize-then-multiply path for CPUs that more than doubled prompt processing speed for the trellis types in one step, and later added repacking into a simpler eight-bit layout. With that, prompt processing on CPUs became, in Kawrakow's word, excellent. Token generation remained the harder half.
+So the full design rule for a compressed weight format has two parts. During generation, the decode must fit inside the memory time. During prefill, the decode must be amortised over enough tokens that it disappears into the matrix multiply.
+## Part fifteen — the lesson for custom hardware
+Now let's step back to the point of all this.
+The lesson is not "use trellis quantization." Trellis quantization is a good quantizer. It gets close to the theoretical limit for Gaussian data at two and three bits, and it does that without a stored codebook. But on the wrong hardware it is slower than simpler formats, and at four bits and above its quality advantage is modest.
+The deeper lesson is about the trade itself. Moving a byte from off-chip memory costs hundreds to thousands of times more energy than a simple integer operation, and at batch one it is the only thing that sets the speed. If a machine has integer or bit manipulation capacity that sits idle while it waits for memory, then that capacity can be spent to move fewer bytes. The trellis is one especially clean way of doing that spending: a few instructions buy you the equivalent of a two-hundred-and-fifty-six-dimensional vector quantizer with no table.
+For a general-purpose processor, you have to take the instruction set as given and choose a decoder that fits it. That is what both community projects learned. On NVIDIA, multiply-add, LOP3, and dp4a are cheap, so use them. On Apple's GPU, thirty-two-bit multiplies and shifts are expensive, so a multiply-based generator is the wrong choice there, and a small table or pure logic might do better. On ARM CPUs, table lookups are cheap and multiplies are not.
+For custom hardware, you get to turn this around. You can build the decoder. Think about what the three-instruction decoder actually is in silicon. It is a sixteen-bit shift register window, one thirty-two-bit multiplier, a mask, and an adder. Or, in the integer version, a multiplier, a mask, and a four-input byte adder. That is a tiny block of logic. Placed right next to the multiply-accumulate units, it could expand two bits per weight into a full-precision weight every cycle, with none of the instruction fetch, decode, and register overhead that makes it costly on a general-purpose core. Horowitz's point from Part two comes back here. On a CPU, an instruction costs tens of picojoules of overhead. In a fixed-function decoder, the multiply costs a few picojoules, and the DRAM bits you avoid moving cost that much or more each.
+This is not a new idea in hardware design, and the precedents are encouraging. Stanford's EIE accelerator in twenty sixteen ran directly on compressed, weight-shared networks held in on-chip memory, and much of its roughly hundredfold energy saving came from not going to DRAM at all. NVIDIA's A one hundred added hardware compression of data moving between memory and cache for sparse data. Recent accelerator research, like the lookup table tensor core presented in twenty twenty-five, reports several-fold gains in power, performance, and area over designs that dequantize in software. And for chips that keep weights in on-chip memory, such as wafer-scale or SRAM-based designs, memory capacity rather than bandwidth is the scarce resource. There, every bit saved per weight means fewer chips per model.
+The trellis adds something specific to that tradition. Its bitshift structure gives random access, because every weight depends only on a fixed-size window of the compressed stream. That is exactly what hardware wants: no sequential walk, no variable-length decoding like Huffman codes, and a decoder whose cost is fixed and known in advance. The computed codes mean there is no codebook memory to size, fill, or keep coherent. And because incoherence processing makes every layer look Gaussian, one fixed decoder serves every layer of every model.
+Before committing, there are honest questions a hardware designer would still need to ask. Encoding is expensive, so this suits weights, not activations or the key-value cache. The Hadamard rotations add their own work at inference time, though that work is small. As the bits per weight rise, the quality advantage over simpler formats shrinks, so the trade is most valuable at two and three bits. And the software ecosystem is still fragmented. The trellis formats have not made it into mainline llama dot cpp or vLLM, partly for licensing and partly because the community formats are incompatible with each other and with the paper. An Apple team's experimental trellis support for their own machine learning framework was closed without being merged.
+## Where the field is heading
+A few threads are worth keeping an eye on.
+On the rounding side, the Cornell group's YAQA shows that a better rounding algorithm, aimed at the whole model's output rather than each layer in isolation, stacks cleanly on top of the trellis. EXL3 has already added a two-sided rounding path that cites it.
+On the quantizer side, the trellis is not the last word. A team at Qualcomm AI Research published a Leech lattice vector quantizer in March of this year, twenty-four dimensions, reporting better two-bit perplexity than QTIP on the seven-billion Llama two model. Interestingly, its reported error on a synthetic Gaussian source is actually higher than the trellis's, so the gain probably comes from other parts of its pipeline. That is worth watching rather than taking at face value. Other work extends trellis quantization to fractional bit rates and mixed schemes, and one recent preprint makes the trellis differentiable, so a model can be trained while aware of its trellis quantization, by replacing Viterbi's hard choice with a soft average over paths.
+On the kernel side, the direction is clear from both community projects: fuse the decode into integer dot products with quantized activations, so that decoding and multiplying become the same instruction. That is the software version of putting the decoder next to the multiplier.
+## Recap
+Let's pull it together in a few breaths.
+At batch one, a model's speed is set by memory bandwidth, because every weight is read once per token and used for just two operations. Fewer bits per weight means proportionally more speed, and moving bytes also dominates energy.
+Meanwhile the integer units sit mostly idle. On a consumer NVIDIA card, there is room for about five integer instructions per two-bit weight. On a data centre card with much faster memory, about one.
+Scalar quantization wastes about a quarter of a bit per weight because cubes pack space badly. Vector quantization recovers some of that, but its codebook grows exponentially with dimension and lookup tables are costly on real hardware.
+Incoherence processing rotates weights so they look Gaussian, which means one fixed quantizer can serve every layer.
+A trellis gives a very high-dimensional quantizer with a small state machine and linear-time Viterbi encoding. QTIP's bitshift trellis makes each state a sixteen-bit window into the bitstream, so decoding is random access and parallel. Its computed codes turn the state into a Gaussian-looking weight in about three instructions, with no table.
+QTIP got close to the theoretical limit at two bits and ran as fast as the best eight-dimensional method, on a card where the decode fit the idle time.
+ExLlamaV3 turned it into a practical format, then evolved its codebook toward the dp4a instruction. It found that the decode is compute-bound on some cards and memory-bound on others.
+ik llama dot cpp redesigned the generator for integers and ran it everywhere. It is good on NVIDIA, reasonable on Zen four, slower on older x86, and poor on Apple Silicon, because the cost of the same few instructions varies so much.
+Prefill is compute-bound, so heavy formats decode a block once and reuse it.
+And the lesson: if your hardware has spare integer or bit manipulation capacity, spend it to move fewer bytes, and choose a decoder that fits your hardware's cheap instructions. If you are building the hardware, a trellis decoder is small, fixed-cost, and random-access, which makes it a strong candidate to build in.
+## Self-check questions
+Ten questions, with brief answers after each.
+One. Why is batch-one decoding memory-bound on essentially every modern processor? Because each weight is used for only two operations per token, giving an arithmetic intensity of roughly sixteen divided by the bits per weight, far below the ridge point of any modern chip.
+Two. What is the upper bound on tokens per second at batch one? Memory bandwidth divided by the size of the weights, ignoring the key-value cache and other overheads.
+Three. Why can a faster memory system make decoding compute-bound? Because the number of weights arriving per second rises faster than integer throughput, so the instruction budget per weight shrinks. On a Hopper-class card it is about one instruction per weight at two bits.
+Four. What limits vector quantization to around eight dimensions? The codebook grows as two to the power of bits per weight times dimension, and both storing it and searching it become impractical.
+Five. What does incoherence processing buy, beyond removing outliers? It makes every layer's weights look Gaussian, so a single fixed quantizer, and therefore a computed code, can be used everywhere.
+Six. What is the state in QTIP's bitshift trellis, and why does it make decoding parallel? The state is a sixteen-bit window into the compressed bitstream, which shifts by k bits per weight. Any weight can be decoded from its own window without walking the path from the start.
+Seven. What does the three-instruction code do? A multiply-add scrambles the state, a single three-input logic instruction masks and XORs it into two bounded half-precision values with random signs, and one add sums them into a roughly Gaussian weight.
+Eight. Why did ik llama dot cpp redesign its trellis for integers, and why did that hurt on Apple's GPU? Converting generated floats to integers for fast CPU dot products cost more than the trellis saved. The integer version maps onto byte dot product instructions on CUDA, x86, and ARM. But on Apple's GPU, thirty-two-bit multiplies and shifts are slow, so the extra integer work made decoding the bottleneck.
+Nine. How do heavy formats avoid paying the decode cost during prefill? By decoding a block of weights once to ordinary floating point, or repacking it, and reusing it across all the prompt tokens in a standard matrix multiply.
+Ten. What is the general lesson for designing custom hardware? Off-chip bytes are far more expensive than simple logic, so a small fixed-function decoder next to the multiply-accumulate units can trade cheap computation for much less memory traffic. The trellis is attractive for that because it is random-access, table-free, and fixed-cost.
+That is the lecture. The trellis is a beautiful piece of information theory, but the reason it matters is a systems reason: it is a way to spend arithmetic you already have to avoid moving bytes you cannot afford. Thanks for listening.