Adds baseline-sme2 for loop_101 and loop_128, and a sme2-kernel:za / sme2-kernel:streaming-sve tag on the 32 simd-loop definitions that have a baseline-sme2 (tags only; nothing else in those files changes). Exact paths only. See ArtificialRay/CPU-Kernel-Baseline#107 (issue #95).
simd-loop expert baselines: baseline-sve (Graviton3, 30 loops) rebuilt + new baseline-sve2 (Graviton4, 36 loops); reference fixes for 114/126/127
baseline-sve (30): Arm's plain-SVE kernels selected by the preprocessor from the upstream simd-loops sources (asm fallbacks where the ACLE branch needs SVE2), -march=armv8.2-a+sve pinned, edge-size padding in the binding for 038 109 110 112 113 114 124 219. All 30 built and evaluated on a c7g.large against the Python reference; 29 pass (032's baseline is numerically off and is kept for continuity).
baseline-sve2 (36, new author): the previous baseline-sve files (validated on Graviton4, 2026-07-23) renamed with -march=native restored; 9 of them (038 102 103 104 105 109 120 123 124) regenerated because the old copies did not compile. Cross-compiled for armv9-a+sve2, not yet run on a c8g.
definitions: loop_126/127 mask the uint32 reference to 32 bits (numpy 2 raised on overflow); loop_114 wraps int32/int16 like the C reference (raised at n=4096).
No deletions. Generated by scripts/gen_simd_loop_harness.py on CPU-Kernel-Baseline feat/box-watchdog.
add hard-label to isa_features for every simd-loop solutions
ArtificialRay
1a19158
Replace pre-PR#15 conv2d-only trace with current simd-loop set (definitions + workloads + reference/autovec solutions)
