These gemm_ggml_* workloads (Qwen3.8-27B shapes) were never given definitions, so nothing loads them. Exact paths only; see ArtificialRay/CPU-Kernel-Baseline#94 item 3.
- Delete all gemm kernel in ncnn as they are not using gemm but gemv, which hurts the performance of large batch size
ArtificialRay
650aa4b
- Update kleidiai's gemm to use both GEMV and GEMM: for small batch size (less than 4 or 8) use GEMV for large batch size use GEMM
Kleidiai kernel changes:
ArtificialRay
d7a6eaa
- workload for 7 kernels change, keep only 2-3 decode record for the kernel, all other has batch size of at least 256
- baseline binding change:
- baseline-kleidiai-arm/conv2d/conv2d_fp32_nhwc_kh3_kw3_s1_p1_c32_c64: add N as a var input
- baseline-kleidiai-arm/gemm/gemm_bf16_n512_k512: pack A at LHS every time, remove memcmp for A
- baseline-kleidiai-arm/gemm/gemm_qs4c32_n256_k512: dynamic quant A + pack A every time, remove memcmp for A
- baseline-kleidiai-arm/gemm/gemm_qs4cx_sme2_n256_k512: same as baseline-kleidiai-arm/gemm/gemm_qs4c32_n256_k512
- baseline-kleidiai-arm/conv2d/conv2d_f16_nhwc_kh3_kw3_valid_c32_c64: use NEON to convert f16 to f32, do LHS pack every time
gate v2: real-activation tensors for the 11 Qwen3.5-4B packed gemm definitions, baseline-relative SQNR floors on all 30, exact-bsums control solution
- CV models: FP32 kernels and int8 (w8a8ch) kernels
- LLM models: BF16 kernels and int4 (Q4_K) kernels
Full precision kernels (fp32 and bf16) are ready to benchmark while low-bit kernels have correctness issue that may need a new evaluator
Update definition and workload for CV model kernels:
ArtificialRay
7e7beda
- only conv2d and conv2d depthwise are kept, remove others
- conv2d and conv2d depthwise have fp32 and int8 percision kernels
- add new maxpool2d definitions
- add workloads for new conv2d, conv2d depthwise definitions, pooling, lstm definitions.
