| {"xilinx/lutrams_xc5v.txt": "# LUT RAMs for Virtex 5, Virtex 6, Spartan 6, Series 7.\n# The corresponding mapping file is lutrams_xc5v_map.v\n\n# Single-port RAMs.\n\nram distributed $__XILINX_LUTRAM_SP_ {\n\tcost 8;\n\twidthscale;\n\toption \"ABITS\" 5 {\n\t\tabits 5;\n\t\twidths 8 global;\n\t}\n\toption \"ABITS\" 6 {\n\t\tabits 6;\n\t\twidths 4 global;\n\t}\n\toption \"ABITS\" 7 {\n\t\tabits 7;\n\t\twidths 2 global;\n\t}\n\toption \"ABITS\" 8 {\n\t\tabits 8;\n\t\twidths 1 global;\n\t}\n\tinit no_undef;\n\tprune_rom;\n\tport arsw \"RW\" {\n\t\tclock posedge;\n\t}\n}\n\n# Dual-port RAMs.\n\nram distributed $__XILINX_LUTRAM_DP_ {\n\tcost 8;\n\twidthscale;\n\toption \"ABITS\" 5 {\n\t\tabits 5;\n\t\twidths 4 global;\n\t}\n\toption \"ABITS\" 6 {\n\t\tabits 6;\n\t\twidths 2 global;\n\t}\n\toption \"ABITS\" 7 {\n\t\tabits 7;\n\t\twidths 1 global;\n\t}\n\tinit no_undef;\n\tprune_rom;\n\tport arsw \"RW\" {\n\t\tclock posedge;\n\t}\n\tport ar \"R\" {\n\t}\n}\n\n# Quad-port RAMs.\n\nram distributed $__XILINX_LUTRAM_QP_ {\n\tcost 7;\n\twidthscale;\n\toption \"ABITS\" 5 {\n\t\tabits 5;\n\t\twidths 2 global;\n\t}\n\toption \"ABITS\" 6 {\n\t\tabits 6;\n\t\twidths 1 global;\n\t}\n\tinit no_undef;\n\tprune_rom;\n\tport arsw \"RW\" {\n\t\tclock posedge;\n\t}\n\tport ar \"R0\" \"R1\" \"R2\" {\n\t}\n}\n\n# Simple dual port RAMs.\n\nram distributed $__XILINX_LUTRAM_SDP_ {\n\tcost 8;\n\twidthscale 7;\n\toption \"ABITS\" 5 {\n\t\tabits 5;\n\t\twidths 6 global;\n\t}\n\toption \"ABITS\" 6 {\n\t\tabits 6;\n\t\twidths 3 global;\n\t}\n\tinit no_undef;\n\tprune_rom;\n\tport sw \"W\" {\n\t\tclock posedge;\n\t}\n\tport ar \"R\" {\n\t}\n}\n", "xilinx/brams_xc4v.txt": "# Block RAMs for Virtex 4+.\n# The corresponding mapping files are:\n# - brams_xc3sda_map.v: Spartan 3A DSP, Spartan 6\n# - brams_xc4v_map.v: Virtex 4\n# - brams_xc5v_map.v: Virtex 5\n# - brams_xc6v_map.v: Virtex 6, Series 7\n# - brams_xcu_map.v: Ultrascale\n\nram block $__XILINX_BLOCKRAM_TDP_ {\n\tbyte 9;\n\tifdef HAS_SIZE_36 {\n\t\toption \"MODE\" \"HALF\" {\n\t\t\tabits 14;\n\t\t\twidths 1 2 4 9 18 per_port;\n\t\t\tcost 129;\n\t\t}\n\t\toption \"MODE\" \"FULL\" {\n\t\t\tabits 15;\n\t\t\twidths 1 2 4 9 18 36 per_port;\n\t\t\tcost 257;\n\t\t}\n\t\tifdef HAS_CASCADE {\n\t\t\toption \"MODE\" \"CASCADE\" {\n\t\t\t\tabits 16;\n\t\t\t\t# hack to enforce same INIT layout as in the other modes\n\t\t\t\twidths 1 2 4 9 per_port;\n\t\t\t\tcost 513;\n\t\t\t}\n\t\t}\n\t} else {\n\t\toption \"MODE\" \"FULL\" {\n\t\t\tabits 14;\n\t\t\twidths 1 2 4 9 18 36 per_port;\n\t\t\tcost 129;\n\t\t}\n\t\tifdef HAS_CASCADE {\n\t\t\toption \"MODE\" \"CASCADE\" {\n\t\t\t\tabits 15;\n\t\t\t\twidths 1 2 4 9 per_port;\n\t\t\t\tcost 257;\n\t\t\t}\n\t\t}\n\t}\n\tinit any;\n\tport srsw \"A\" \"B\" {\n\t\toption \"MODE\" \"HALF\" {\n\t\t\twidth mix;\n\t\t}\n\t\toption \"MODE\" \"FULL\" {\n\t\t\twidth mix;\n\t\t}\n\t\toption \"MODE\" \"CASCADE\" {\n\t\t\twidth mix 1;\n\t\t}\n\t\tifdef HAS_ADDRCE {\n\t\t\t# TODO\n\t\t\t# addrce;\n\t\t}\n\t\t# Spartan 6 and Virtex 6 have a bug where READ_FIRST is not usable with asynchronous clocks.\n\t\tifdef HAS_CONFLICT_BUG {\n\t\t\toption \"HAS_RDFIRST\" 1 {\n\t\t\t\tclock posedge \"C\";\n\t\t\t}\n\t\t\toption \"HAS_RDFIRST\" 0 {\n\t\t\t\tclock posedge;\n\t\t\t}\n\t\t} else {\n\t\t\tclock posedge;\n\t\t}\n\t\tclken;\n\t\trdsrst any gated_clken;\n\t\trdinit any;\n\t\tportoption \"WRITE_MODE\" \"NO_CHANGE\" {\n\t\t\trdwr no_change;\n\t\t\toption \"MODE\" \"CASCADE\" {\n\t\t\t\tforbid;\n\t\t\t}\n\t\t}\n\t\tportoption \"WRITE_MODE\" \"WRITE_FIRST\" {\n\t\t\tifdef HAS_SIZE_36 {\n\t\t\t\trdwr new;\n\t\t\t} else {\n\t\t\t\trdwr new_only;\n\t\t\t}\n\t\t}\n\t\tifdef HAS_CONFLICT_BUG {\n\t\t\toption \"HAS_RDFIRST\" 1 {\n\t\t\t\tportoption \"WRITE_MODE\" \"READ_FIRST\" {\n\t\t\t\t\trdwr old;\n\t\t\t\t\twrtrans all old;\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\tportoption \"WRITE_MODE\" \"READ_FIRST\" {\n\t\t\t\trdwr old;\n\t\t\t\twrtrans all old;\n\t\t\t}\n\t\t}\n\t\toptional_rw;\n\t}\n}\n\nifdef HAS_SIZE_36 {\n\tram block $__XILINX_BLOCKRAM_SDP_ {\n\t\tbyte 9;\n\t\toption \"MODE\" \"HALF\" {\n\t\t\tabits 14;\n\t\t\twidths 1 2 4 9 18 36 per_port;\n\t\t\tcost 129;\n\t\t}\n\t\toption \"MODE\" \"FULL\" {\n\t\t\tabits 15;\n\t\t\twidths 1 2 4 9 18 36 72 per_port;\n\t\t\tcost 257;\n\t\t}\n\t\tinit any;\n\t\tport sw \"W\" {\n\t\t\tifndef HAS_MIXWIDTH_SDP {\n\t\t\t\toption \"MODE\" \"HALF\" width 36;\n\t\t\t\toption \"MODE\" \"FULL\" width 72;\n\t\t\t}\n\t\t\tifdef HAS_ADDRCE {\n\t\t\t\t# TODO\n\t\t\t\t# addrce;\n\t\t\t}\n\t\t\t# Spartan 6 and Virtex 6 have a bug where READ_FIRST is not usable with asynchronous clocks.\n\t\t\tifdef HAS_CONFLICT_BUG {\n\t\t\t\toption \"WRITE_MODE\" \"READ_FIRST\" {\n\t\t\t\t\tclock posedge \"C\";\n\t\t\t\t}\n\t\t\t\toption \"WRITE_MODE\" \"WRITE_FIRST\" {\n\t\t\t\t\tclock posedge;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tclock posedge;\n\t\t\t}\n\t\t\tclken;\n\t\t\toption \"WRITE_MODE\" \"READ_FIRST\" {\n\t\t\t\twrtrans all old;\n\t\t\t}\n\t\t\toptional;\n\t\t}\n\t\tport sr \"R\" {\n\t\t\tifndef HAS_MIXWIDTH_SDP {\n\t\t\t\toption \"MODE\" \"HALF\" width 36;\n\t\t\t\toption \"MODE\" \"FULL\" width 72;\n\t\t\t}\n\t\t\tifdef HAS_ADDRCE {\n\t\t\t\t# TODO\n\t\t\t\t# addrce;\n\t\t\t}\n\t\t\t# Spartan 6 and Virtex 6 have a bug where READ_FIRST is not usable with asynchronous clocks.\n\t\t\tifdef HAS_CONFLICT_BUG {\n\t\t\t\toption \"WRITE_MODE\" \"READ_FIRST\" {\n\t\t\t\t\tclock posedge \"C\";\n\t\t\t\t}\n\t\t\t\toption \"WRITE_MODE\" \"WRITE_FIRST\" {\n\t\t\t\t\tclock posedge;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tclock posedge;\n\t\t\t}\n\t\t\tclken;\n\t\t\trdsrst any gated_clken;\n\t\t\trdinit any;\n\t\t\toptional;\n\t\t}\n\t}\n}\n", "ice40/brams.txt": "ram block $__ICE40_RAM4K_ {\n\tabits 11;\n\twidths 2 4 8 16 per_port;\n\tcost 64;\n\toption \"HAS_BE\" 1 {\n\t\tbyte 1;\n\t}\n\tinit any;\n\tport sw \"W\" {\n\t\toption \"HAS_BE\" 0 {\n\t\t\twidth 2 4 8;\n\t\t}\n\t\toption \"HAS_BE\" 1 {\n\t\t\twidth 16;\n\t\t\twrbe_separate;\n\t\t}\n\t\tclock anyedge;\n\t}\n\tport sr \"R\" {\n\t\tclock anyedge;\n\t\trden;\n\t}\n}\n", "ice40/spram.txt": "ram huge $__ICE40_SPRAM_ {\n\tabits 14;\n\twidth 16;\n\tcost 2048;\n\tbyte 4;\n\tport srsw \"A\" {\n\t\tclock posedge;\n\t\tclken;\n\t\twrbe_separate;\n\t\trdwr no_change;\n\t}\n}\n", "lattice/lutrams_trellis.txt": "ram distributed $__TRELLIS_DPR16X4_ {\n\tabits 4;\n\twidth 4;\n\tcost 4;\n\tinit any;\n\tprune_rom;\n\tport sw \"W\" {\n\t\tclock anyedge;\n\t}\n\tport ar \"R\" {\n\t}\n}\n", "lattice/brams_16kd.txt": "ram block $__DP16KD_ {\n\tabits 14;\n\twidths 1 2 4 9 18 per_port;\n\tbyte 9;\n\tcost 128;\n\tinit no_undef;\n\tport srsw \"A\" \"B\" {\n\t\tclock anyedge;\n\t\tclken;\n\t\twrbe_separate;\n\t\tportoption \"WRITEMODE\" \"NORMAL\" {\n\t\t\trdwr no_change;\n\t\t}\n\t\tportoption \"WRITEMODE\" \"WRITETHROUGH\" {\n\t\t\trdwr new;\n\t\t}\n\t\tportoption \"WRITEMODE\" \"READBEFOREWRITE\" {\n\t\t\trdwr old;\n\t\t}\n\t\toption \"RESETMODE\" \"SYNC\" {\n\t\t\trdsrst zero ungated block_wr;\n\t\t}\n\t\toption \"RESETMODE\" \"ASYNC\" {\n\t\t\trdarst zero;\n\t\t}\n\t\trdinit zero;\n\t}\n}\n\nram block $__PDPW16KD_ {\n\tabits 14;\n\twidths 1 2 4 9 18 36 per_port;\n\tbyte 9;\n\tcost 128;\n\tinit no_undef;\n\tport sr \"R\" {\n\t\tclock anyedge;\n\t\tclken;\n\t\toption \"RESETMODE\" \"SYNC\" {\n\t\t\trdsrst zero ungated;\n\t\t}\n\t\toption \"RESETMODE\" \"ASYNC\" {\n\t\t\trdarst zero;\n\t\t}\n\t\trdinit zero;\n\t}\n\tport sw \"W\" {\n\t\twidth 36;\n\t\tclock anyedge;\n\t\tclken;\n\t}\n}\n", "gowin/lutrams.txt": "ram distributed $__GOWIN_LUTRAM_ {\n\tabits 4;\n\twidth 4;\n\tcost 4;\n\twidthscale;\n\tinit no_undef;\n\tprune_rom;\n\tport sw \"W\" {\n\t\tclock posedge;\n\t}\n\tport ar \"R\" {\n\t}\n}\n", "gowin/brams.txt": "ram block $__GOWIN_SP_ {\n\tabits 14;\n\twidths 1 2 4 9 18 36 per_port;\n\tcost 128;\n\tbyte 9;\n\tinit no_undef;\n\tport srsw \"A\" {\n\t\tclock posedge;\n\t\tclken;\n\t\toption \"RESET_MODE\" \"SYNC\" {\n\t\t\trdsrst zero ungated;\n\t\t}\n\t\toption \"RESET_MODE\" \"ASYNC\" {\n\t\t\trdarst zero;\n\t\t}\n\t\trdinit zero;\n\t\tportoption \"WRITE_MODE\" 0 {\n\t\t\trdwr no_change;\n\t\t}\n\t\tportoption \"WRITE_MODE\" 1 {\n\t\t\trdwr new;\n\t\t}\n\t\tifndef gw5a {\n\t\t\tportoption \"WRITE_MODE\" 2 {\n\t\t\t\trdwr old;\n\t\t\t}\n\t\t}\n\t\twrbe_separate;\n\t}\n}\n\nram block $__GOWIN_DP_ {\n\tabits 14;\n\twidths 1 2 4 9 18 per_port;\n\tcost 128;\n\tbyte 9;\n\tinit no_undef;\n\tport srsw \"A\" \"B\" {\n\t\tclock posedge;\n\t\tclken;\n\t\toption \"RESET_MODE\" \"SYNC\" {\n\t\t\trdsrst zero ungated;\n\t\t}\n\t\toption \"RESET_MODE\" \"ASYNC\" {\n\t\t\trdarst zero;\n\t\t}\n\t\trdinit zero;\n\t\tportoption \"WRITE_MODE\" 0 {\n\t\t\trdwr no_change;\n\t\t}\n\t\tportoption \"WRITE_MODE\" 1 {\n\t\t\trdwr new;\n\t\t}\n\t\twrbe_separate;\n\t}\n}\n\nram block $__GOWIN_SDP_ {\n\tabits 14;\n\twidths 1 2 4 9 18 36 per_port;\n\tcost 128;\n\tbyte 9;\n\tinit no_undef;\n\tport sr \"R\" {\n\t\tclock posedge;\n\t\tclken;\n\t\toption \"RESET_MODE\" \"SYNC\" {\n\t\t\trdsrst zero ungated;\n\t\t}\n\t\toption \"RESET_MODE\" \"ASYNC\" {\n\t\t\trdarst zero;\n\t\t}\n\t\trdinit zero;\n\t}\n\tport sw \"W\" {\n\t\tclock posedge;\n\t\tclken;\n\t\twrbe_separate;\n\t}\n}\n"} |