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terminal-tasks-showcase

# premap.py: derive the $mem_v2 structure that Yosys 0.70's flow hands to memory_libmap for a gen11 query.
# Signals are token lists (LSB first): '0'/'1'/'x' constants, named input bits ('wa3'), or opaque wires.
import math
def clog2(n): return max(1, (n - 1).bit_length())
def ceil_log2(n): return 0 if n <= 1 else (n - 1).bit_length()
def ext(name, aw, ab):
    return [name + str(i) for i in range(min(aw, ab))] + ["0"] * max(0, ab - aw)
class Port:
    def __init__(self, **kw): self.__dict__.update(kw)
class MemStruct:
    pass
def bits(v, W):
    return [("1" if (v >> i) & 1 else "0") for i in range(W)]
def init_entries(q, W, D, lo, hi):
    init = q["init"]; E = []
    ones = ["1"] * W; full = ["1"] * W
    half = max(1, (W + 1) // 2)
    if init == "zero":
        for k in range(lo, hi + 1): E.append((k, [bits(0, W)], full))
    elif init == "ones":
        for k in range(lo, hi + 1): E.append((k, [ones], full))
    elif init == "half":
        for k in range(lo, lo + (D + 1) // 2): E.append((k, [bits(k, W)], full))
    elif init == "count":
        for k in range(lo, hi + 1): E.append((k, [bits(k, W)], full))
    elif init == "step2":
        for k in range(lo, hi + 1, 2): E.append((k, [bits(k, W)], full))
    elif init == "low":
        en = ["1" if i < half else "0" for i in range(W)]
        for k in range(lo, hi + 1): E.append((k, [bits(k, W)], en))
    elif init == "over":
        A = [(k, [ones], full) for k in range(lo, hi + 1)]
        B = [(k, [bits(k, W)], full) for k in range(lo, lo + (D + 3) // 4)]
        E = A + B
    elif init == "redo":
        A = [(k, [ones], full) for k in range(lo, hi + 1)]
        B = [(k, [bits(k, W)], full) for k in range(lo, hi + 1)]
        E = A + B
    elif init == "file":
        E = readmem_entries(q, W, D, lo, hi)
    return E
def readmem_entries(q, W, D, lo, hi):
    import gen11
    text = gen11.hexfile(q)
    a = q["hexargs"]
    S, F = lo + D // 4, lo + (3 * D) // 4 - 1
    start, finish = {"none": (-1, -1), "start": (S, -1), "range": (S, F), "rev": (hi, lo)}[a]
    rmin, rmax = lo, hi
    if start < 0: start = rmin
    if finish < 0: finish = rmax + 1
    inc = 1 if start <= finish else -1
    cursor = start
    E = []; cur = None; nxt = 0
    full = ["1"] * W
    stop = False
    for line in text.split("\n"):
        for tok in line.split():
            if tok.startswith("//"): break
            if tok[0] == "@":
                cursor = int(tok[1:], 16); continue
            v = int(tok, 16) & ((1 << W) - 1)
            if cur is None or cursor != nxt:
                cur = (cursor, [], full); E.append(cur); nxt = cursor
            cur[1].append(bits(v, W)); nxt += 1
            cursor += inc
            if cursor == finish + inc or (inc > 0 and cursor > rmax) or (inc < 0 and cursor < rmin):
                stop = True; break
        if stop: break
        # the same test after every line, so an "@" line can end the file as well
        if cursor == finish + inc or (inc > 0 and cursor > rmax) or (inc < 0 and cursor < rmin):
            break
    return E
def derive_words_only(q):
    W, D = int(q["W"]), int(q["D"])
    lo = 1 if q["decl"] == "one" else 0
    words = [None] * D
    K = ceil_log2(lo + D)
    ents = init_entries(q, W, D, lo, D - 1 + lo)
    ents = [((addr & 0xffffffff) & ((1 << K) - 1), ws, en) for addr, ws, en in ents]
    for addr, ws, en in ents:
        for j, wv in enumerate(ws):
            a = addr + j - lo
            if not (0 <= a < D): continue
            cur = words[a] if words[a] is not None else ["x"] * W
            words[a] = [wv[i] if en[i] == "1" else cur[i] for i in range(W)]
            if all(b == "x" for b in words[a]): words[a] = None
    return words
def derive(q):
    W, D = int(q["W"]), int(q["D"])
    decl, wstyle, rstyle, init = q["decl"], q["wstyle"], q["rstyle"], q["init"]
    dwidth, rslice, awidth, edge, rd2 = q["dwidth"], q["rslice"], q["awidth"], q["edge"], q["rd2"]
    AW = clog2(D + 1) if decl == "one" else clog2(D)
    aw = {"exact": AW, "wide": AW + 3, "narrow": max(1, AW - 2)}[awidth]
    half = max(1, (W + 1) // 2)
    dw = {"exact": W, "narrow": half, "snarrow": half, "wide": W + 4}[dwidth]
    rw = half if rslice == "low" else W
    lo = 1 if decl == "one" else 0
    OFF = lo; AB = ceil_log2(OFF + D)
    pol = (edge == "pos")
    m = MemStruct(); m.width = W; m.size = D; m.offset = OFF; m.abits = AB
    m.wr = []; m.rd = []
    def wd_ext():
        if dwidth == "narrow": return ["wd%d" % i for i in range(dw)] + ["0"] * (W - dw)
        if dwidth == "snarrow": return ["wd%d" % i for i in range(dw)] + ["wd%d" % (dw - 1)] * (W - dw)
        return ["wd%d" % i for i in range(W)]
    def opaque(tag, n):
        return ["%s%d" % (tag, i) for i in range(n)]
    def wport(en, addr, data, prio=None):
        m.wr.append(Port(en=en, addr=addr, data=data, pol=pol, prio=prio or []))
    def rport(clk, addr, data, used):
        m.rd.append(Port(clk=clk, pol=(pol if clk else False), addr=addr, data=data, used=used, en="1", xmux_share=[]))
    waddr_named = ext("wa", aw, AB)
    feedback = False
    if wstyle == "plain":
        wport(["W0E"] * W, opaque("W0A", AB), opaque("W0D", W))
    elif wstyle == "always":
        wport(["1"] * W, waddr_named, wd_ext())
    elif wstyle == "bytes":
        en = []
        for i in range(W): en.append("W0E%d" % (8 * (i // 8)))
        wport(en, waddr_named, opaque("W0D", W))
    elif wstyle == "halves":
        if W == 1: wport(["W0E"], opaque("W0A", AB), opaque("W0D", W))
        else:
            h = W // 2
            wport(["W0E0"] * h + ["W0E1"] * (W - h), waddr_named, opaque("W0D", W))
    elif wstyle == "dual":
        wport(["W0E"] * W, opaque("W0A", AB), opaque("W0D", W))
        wport(["W1E"] * W, opaque("W1A", AB), opaque("W1D", W), prio=[0])
    elif wstyle == "rmwmux":
        merged = not (awidth == "narrow" and aw < AB)
        if merged:
            wport(["W0E"] * W, opaque("W0A", AB), opaque("W0D", W))
        else:
            wport(["1"] * W, waddr_named, opaque("W0D", W)); feedback = True
    elif wstyle == "rmwadd":
        wport(["W0E"] * W, opaque("W0A", AB), opaque("W0D", W)); feedback = True
    if feedback:
        rport(False, waddr_named, opaque("MRF", W), [True] * W)
        m.rd[-1].xmux_share = [0]      # memory_libmap's sigmap_xmux resolves proc's "we ? wa : x" address mux to wa
    rport(rstyle in ("sync", "same"), ext("ra", aw, AB), ["rd%d" % i for i in range(rw)] + opaque("RDX", W - rw), [i < rw for i in range(W)])
    if rd2 != "none":
        rport(rd2 == "sync", ext("ra2", aw, AB), ["rd2_%d" % i for i in range(W)], [True] * W)
    # init: $meminit entries in priority order: (address, [word bits LSB first, ...], enable bits)
    m.entries = init_entries(q, W, D, lo, D - 1 + lo)
    # wreduce trims every $meminit address to ceil_log2(OFF + D) bits (the address wraps), before opt_mem and
    # memory_collect; get_init_data then keeps only the words inside the array, in priority order
    K = ceil_log2(OFF + D)
    m.entries = [((addr & 0xffffffff) & ((1 << K) - 1), ws, en) for addr, ws, en in m.entries]
    words = [None] * D
    for addr, ws, en in m.entries:
        for j, wv in enumerate(ws):
            a = addr + j - OFF
            if not (0 <= a < D): continue
            cur = words[a] if words[a] is not None else ["x"] * W
            words[a] = [wv[i] if en[i] == "1" else cur[i] for i in range(W)]
            if all(b == "x" for b in words[a]): words[a] = None
    m.words = words
    # opt_mem: constant lanes
    keep = []; m.pruned = []
    for i in range(W):
        a0 = a1 = True
        for p in m.wr:
            if p.en[i] != "0":
                if p.data[i] not in ("x", "0"): a0 = False
                if p.data[i] not in ("x", "1"): a1 = False
        for addr, ws, en in m.entries:
            for wv in ws:
                b = wv[i]
                if b not in ("x", "0"): a0 = False
                if b not in ("x", "1"): a1 = False
        if a0 or a1: m.pruned.append(i)
        else: keep.append(i)
    m.keep = keep
    m.ff_prune = 0
    for p in m.rd:
        if p.clk: m.ff_prune += sum(1 for i in m.pruned if p.used[i])
    if not keep:
        m.removed = True; return m
    # a read port none of whose remaining lanes is used loses all its outputs; opt_clean deletes it, and a memory
    # left without read ports is deleted as well
    m.rd = [p for p in m.rd if any(p.used[i] for i in keep)]
    if not m.rd:
        m.removed = True; return m
    m.removed = False
    m.width = len(keep)
    for p in m.wr:
        p.en = [p.en[i] for i in keep]; p.data = [p.data[i] for i in keep]
    for p in m.rd:
        p.data = [p.data[i] for i in keep]; p.used = [p.used[i] for i in keep]
    m.words = [None if wv is None else [wv[i] for i in keep] for wv in words]
    m.has_init = any(wv is not None for wv in m.words)
    return m
def const_str(bits):
    return "%d'%s" % (len(bits), "".join(reversed(bits)))
def summarize(m):
    # same shape as memstruct.summarize for comparison
    import re
    if m.removed: return None
    W = m.width; NW = len(m.wr); NR = len(m.rd)
    def pattern(bits):
        names = {}; out = []
        for b in bits:
            if b in ("0", "1", "x"): out.append(b); continue
            if b not in names: names[b] = chr(ord('a') + len(names)) if len(names) < 26 else '#'
            out.append(names[b])
        return "".join(out)
    def rle(p):
        out = []; i = 0
        while i < len(p):
            j = i
            while j < len(p) and p[j] == p[i]: j += 1
            out.append("%s%d" % (p[i], j - i) if j - i > 1 else p[i]); i = j
        return " ".join(out)
    s = {"WIDTH": str(W), "SIZE": str(m.size), "OFFSET": str(m.offset), "ABITS": str(m.abits), "RD_PORTS": str(NR), "WR_PORTS": str(NW)}
    s["RD_CLK_ENABLE"] = const_str(["1" if p.clk else "0" for p in m.rd])
    s["RD_CLK_POLARITY"] = const_str(["1" if p.pol else "0" for p in m.rd])
    s["RD_TRANSPARENCY_MASK"] = const_str(["0"] * (NR * NW)) if NR * NW else "1'0"
    s["RD_COLLISION_X_MASK"] = s["RD_TRANSPARENCY_MASK"]
    s["WR_CLK_POLARITY"] = const_str(["1" if p.pol else "0" for p in m.wr]) if NW else "1'0"
    pm = []
    for p in m.wr: pm += ["1" if j in p.prio else "0" for j in range(NW)]
    s["WR_PRIORITY_MASK"] = const_str(pm) if NW else "1'0"
    initbits = []
    for wv in m.words: initbits += (wv if wv is not None else ["x"] * W)
    v = const_str(initbits); s["INIT"] = "allx" if re.match(r"^\d+'x+$", v) else v[:60]
    s["RD_INIT_VALUE"] = "allx"
    s["WR_EN"] = [rle(pattern(p.en)) for p in m.wr]; s["WR_ADDR"] = [rle(pattern(p.addr)) for p in m.wr]; s["WR_DATA"] = [rle(pattern(p.data)) for p in m.wr]
    s["RD_EN"] = ["1"] * NR; s["RD_ADDR"] = [rle(pattern(p.addr)) for p in m.rd]; s["RD_DATA"] = [rle(pattern(p.data)) for p in m.rd]
    s["ADDR_SHARE"] = [next((j for j in range(NW) if m.wr[j].addr == p.addr), -1) for p in m.rd]
    return s

	# premap.py: derive the $mem_v2 structure that Yosys 0.70's flow hands to memory_libmap for a gen11 query.
	# Signals are token lists (LSB first): '0'/'1'/'x' constants, named input bits ('wa3'), or opaque wires.
	import math
	def clog2(n): return max(1, (n - 1).bit_length())
	def ceil_log2(n): return 0 if n <= 1 else (n - 1).bit_length()
	def ext(name, aw, ab):
	return [name + str(i) for i in range(min(aw, ab))] + ["0"] * max(0, ab - aw)
	class Port:
	def __init__(self, **kw): self.__dict__.update(kw)
	class MemStruct:
	pass
	def bits(v, W):
	return [("1" if (v >> i) & 1 else "0") for i in range(W)]
	def init_entries(q, W, D, lo, hi):
	init = q["init"]; E = []
	ones = ["1"] * W; full = ["1"] * W
	half = max(1, (W + 1) // 2)
	if init == "zero":
	for k in range(lo, hi + 1): E.append((k, [bits(0, W)], full))
	elif init == "ones":
	for k in range(lo, hi + 1): E.append((k, [ones], full))
	elif init == "half":
	for k in range(lo, lo + (D + 1) // 2): E.append((k, [bits(k, W)], full))
	elif init == "count":
	for k in range(lo, hi + 1): E.append((k, [bits(k, W)], full))
	elif init == "step2":
	for k in range(lo, hi + 1, 2): E.append((k, [bits(k, W)], full))
	elif init == "low":
	en = ["1" if i < half else "0" for i in range(W)]
	for k in range(lo, hi + 1): E.append((k, [bits(k, W)], en))
	elif init == "over":
	A = [(k, [ones], full) for k in range(lo, hi + 1)]
	B = [(k, [bits(k, W)], full) for k in range(lo, lo + (D + 3) // 4)]
	E = A + B
	elif init == "redo":
	A = [(k, [ones], full) for k in range(lo, hi + 1)]
	B = [(k, [bits(k, W)], full) for k in range(lo, hi + 1)]
	E = A + B
	elif init == "file":
	E = readmem_entries(q, W, D, lo, hi)
	return E
	def readmem_entries(q, W, D, lo, hi):
	import gen11
	text = gen11.hexfile(q)
	a = q["hexargs"]
	S, F = lo + D // 4, lo + (3 * D) // 4 - 1
	start, finish = {"none": (-1, -1), "start": (S, -1), "range": (S, F), "rev": (hi, lo)}[a]
	rmin, rmax = lo, hi
	if start < 0: start = rmin
	if finish < 0: finish = rmax + 1
	inc = 1 if start <= finish else -1
	cursor = start
	E = []; cur = None; nxt = 0
	full = ["1"] * W
	stop = False
	for line in text.split("\n"):
	for tok in line.split():
	if tok.startswith("//"): break
	if tok[0] == "@":
	cursor = int(tok[1:], 16); continue
	v = int(tok, 16) & ((1 << W) - 1)
	if cur is None or cursor != nxt:
	cur = (cursor, [], full); E.append(cur); nxt = cursor
	cur[1].append(bits(v, W)); nxt += 1
	cursor += inc
	if cursor == finish + inc or (inc > 0 and cursor > rmax) or (inc < 0 and cursor < rmin):
	stop = True; break
	if stop: break
	# the same test after every line, so an "@" line can end the file as well
	if cursor == finish + inc or (inc > 0 and cursor > rmax) or (inc < 0 and cursor < rmin):
	break
	return E
	def derive_words_only(q):
	W, D = int(q["W"]), int(q["D"])
	lo = 1 if q["decl"] == "one" else 0
	words = [None] * D
	K = ceil_log2(lo + D)
	ents = init_entries(q, W, D, lo, D - 1 + lo)
	ents = [((addr & 0xffffffff) & ((1 << K) - 1), ws, en) for addr, ws, en in ents]
	for addr, ws, en in ents:
	for j, wv in enumerate(ws):
	a = addr + j - lo
	if not (0 <= a < D): continue
	cur = words[a] if words[a] is not None else ["x"] * W
	words[a] = [wv[i] if en[i] == "1" else cur[i] for i in range(W)]
	if all(b == "x" for b in words[a]): words[a] = None
	return words
	def derive(q):
	W, D = int(q["W"]), int(q["D"])
	decl, wstyle, rstyle, init = q["decl"], q["wstyle"], q["rstyle"], q["init"]
	dwidth, rslice, awidth, edge, rd2 = q["dwidth"], q["rslice"], q["awidth"], q["edge"], q["rd2"]
	AW = clog2(D + 1) if decl == "one" else clog2(D)
	aw = {"exact": AW, "wide": AW + 3, "narrow": max(1, AW - 2)}[awidth]
	half = max(1, (W + 1) // 2)
	dw = {"exact": W, "narrow": half, "snarrow": half, "wide": W + 4}[dwidth]
	rw = half if rslice == "low" else W
	lo = 1 if decl == "one" else 0
	OFF = lo; AB = ceil_log2(OFF + D)
	pol = (edge == "pos")
	m = MemStruct(); m.width = W; m.size = D; m.offset = OFF; m.abits = AB
	m.wr = []; m.rd = []
	def wd_ext():
	if dwidth == "narrow": return ["wd%d" % i for i in range(dw)] + ["0"] * (W - dw)
	if dwidth == "snarrow": return ["wd%d" % i for i in range(dw)] + ["wd%d" % (dw - 1)] * (W - dw)
	return ["wd%d" % i for i in range(W)]
	def opaque(tag, n):
	return ["%s%d" % (tag, i) for i in range(n)]
	def wport(en, addr, data, prio=None):
	m.wr.append(Port(en=en, addr=addr, data=data, pol=pol, prio=prio or []))
	def rport(clk, addr, data, used):
	m.rd.append(Port(clk=clk, pol=(pol if clk else False), addr=addr, data=data, used=used, en="1", xmux_share=[]))
	waddr_named = ext("wa", aw, AB)
	feedback = False
	if wstyle == "plain":
	wport(["W0E"] * W, opaque("W0A", AB), opaque("W0D", W))
	elif wstyle == "always":
	wport(["1"] * W, waddr_named, wd_ext())
	elif wstyle == "bytes":
	en = []
	for i in range(W): en.append("W0E%d" % (8 * (i // 8)))
	wport(en, waddr_named, opaque("W0D", W))
	elif wstyle == "halves":
	if W == 1: wport(["W0E"], opaque("W0A", AB), opaque("W0D", W))
	else:
	h = W // 2
	wport(["W0E0"] * h + ["W0E1"] * (W - h), waddr_named, opaque("W0D", W))
	elif wstyle == "dual":
	wport(["W0E"] * W, opaque("W0A", AB), opaque("W0D", W))
	wport(["W1E"] * W, opaque("W1A", AB), opaque("W1D", W), prio=[0])
	elif wstyle == "rmwmux":
	merged = not (awidth == "narrow" and aw < AB)
	if merged:
	wport(["W0E"] * W, opaque("W0A", AB), opaque("W0D", W))
	else:
	wport(["1"] * W, waddr_named, opaque("W0D", W)); feedback = True
	elif wstyle == "rmwadd":
	wport(["W0E"] * W, opaque("W0A", AB), opaque("W0D", W)); feedback = True
	if feedback:
	rport(False, waddr_named, opaque("MRF", W), [True] * W)
	m.rd[-1].xmux_share = [0] # memory_libmap's sigmap_xmux resolves proc's "we ? wa : x" address mux to wa
	rport(rstyle in ("sync", "same"), ext("ra", aw, AB), ["rd%d" % i for i in range(rw)] + opaque("RDX", W - rw), [i < rw for i in range(W)])
	if rd2 != "none":
	rport(rd2 == "sync", ext("ra2", aw, AB), ["rd2_%d" % i for i in range(W)], [True] * W)
	# init: $meminit entries in priority order: (address, [word bits LSB first, ...], enable bits)
	m.entries = init_entries(q, W, D, lo, D - 1 + lo)
	# wreduce trims every $meminit address to ceil_log2(OFF + D) bits (the address wraps), before opt_mem and
	# memory_collect; get_init_data then keeps only the words inside the array, in priority order
	K = ceil_log2(OFF + D)
	m.entries = [((addr & 0xffffffff) & ((1 << K) - 1), ws, en) for addr, ws, en in m.entries]
	words = [None] * D
	for addr, ws, en in m.entries:
	for j, wv in enumerate(ws):
	a = addr + j - OFF
	if not (0 <= a < D): continue
	cur = words[a] if words[a] is not None else ["x"] * W
	words[a] = [wv[i] if en[i] == "1" else cur[i] for i in range(W)]
	if all(b == "x" for b in words[a]): words[a] = None
	m.words = words
	# opt_mem: constant lanes
	keep = []; m.pruned = []
	for i in range(W):
	a0 = a1 = True
	for p in m.wr:
	if p.en[i] != "0":
	if p.data[i] not in ("x", "0"): a0 = False
	if p.data[i] not in ("x", "1"): a1 = False
	for addr, ws, en in m.entries:
	for wv in ws:
	b = wv[i]
	if b not in ("x", "0"): a0 = False
	if b not in ("x", "1"): a1 = False
	if a0 or a1: m.pruned.append(i)
	else: keep.append(i)
	m.keep = keep
	m.ff_prune = 0
	for p in m.rd:
	if p.clk: m.ff_prune += sum(1 for i in m.pruned if p.used[i])
	if not keep:
	m.removed = True; return m
	# a read port none of whose remaining lanes is used loses all its outputs; opt_clean deletes it, and a memory
	# left without read ports is deleted as well
	m.rd = [p for p in m.rd if any(p.used[i] for i in keep)]
	if not m.rd:
	m.removed = True; return m
	m.removed = False
	m.width = len(keep)
	for p in m.wr:
	p.en = [p.en[i] for i in keep]; p.data = [p.data[i] for i in keep]
	for p in m.rd:
	p.data = [p.data[i] for i in keep]; p.used = [p.used[i] for i in keep]
	m.words = [None if wv is None else [wv[i] for i in keep] for wv in words]
	m.has_init = any(wv is not None for wv in m.words)
	return m
	def const_str(bits):
	return "%d'%s" % (len(bits), "".join(reversed(bits)))
	def summarize(m):
	# same shape as memstruct.summarize for comparison
	import re
	if m.removed: return None
	W = m.width; NW = len(m.wr); NR = len(m.rd)
	def pattern(bits):
	names = {}; out = []
	for b in bits:
	if b in ("0", "1", "x"): out.append(b); continue
	if b not in names: names[b] = chr(ord('a') + len(names)) if len(names) < 26 else '#'
	out.append(names[b])
	return "".join(out)
	def rle(p):
	out = []; i = 0
	while i < len(p):
	j = i
	while j < len(p) and p[j] == p[i]: j += 1
	out.append("%s%d" % (p[i], j - i) if j - i > 1 else p[i]); i = j
	return " ".join(out)
	s = {"WIDTH": str(W), "SIZE": str(m.size), "OFFSET": str(m.offset), "ABITS": str(m.abits), "RD_PORTS": str(NR), "WR_PORTS": str(NW)}
	s["RD_CLK_ENABLE"] = const_str(["1" if p.clk else "0" for p in m.rd])
	s["RD_CLK_POLARITY"] = const_str(["1" if p.pol else "0" for p in m.rd])
	s["RD_TRANSPARENCY_MASK"] = const_str(["0"] * (NR * NW)) if NR * NW else "1'0"
	s["RD_COLLISION_X_MASK"] = s["RD_TRANSPARENCY_MASK"]
	s["WR_CLK_POLARITY"] = const_str(["1" if p.pol else "0" for p in m.wr]) if NW else "1'0"
	pm = []
	for p in m.wr: pm += ["1" if j in p.prio else "0" for j in range(NW)]
	s["WR_PRIORITY_MASK"] = const_str(pm) if NW else "1'0"
	initbits = []
	for wv in m.words: initbits += (wv if wv is not None else ["x"] * W)
	v = const_str(initbits); s["INIT"] = "allx" if re.match(r"^\d+'x+$", v) else v[:60]
	s["RD_INIT_VALUE"] = "allx"
	s["WR_EN"] = [rle(pattern(p.en)) for p in m.wr]; s["WR_ADDR"] = [rle(pattern(p.addr)) for p in m.wr]; s["WR_DATA"] = [rle(pattern(p.data)) for p in m.wr]
	s["RD_EN"] = ["1"] * NR; s["RD_ADDR"] = [rle(pattern(p.addr)) for p in m.rd]; s["RD_DATA"] = [rle(pattern(p.data)) for p in m.rd]
	s["ADDR_SHARE"] = [next((j for j in range(NW) if m.wr[j].addr == p.addr), -1) for p in m.rd]
	return s