| version = "1.0" | |
| artifacts = ["/app/estimator"] | |
| [metadata] | |
| author_name = "FasterLabeling" | |
| category = "hardware-design" | |
| difficulty = "hard" | |
| tags = ["yosys", "fpga", "memory-inference", "ram-mapping", "readmemh", "memory-init", "memory_libmap", "source-only", "hidden-queries", "estimator"] | |
| # Expert in FPGA synthesis who has not seen the task, working from the shipped Yosys 0.70 source only: | |
| # the front end for each write / read idiom (conditional-write data, part-select writers, | |
| # declaration ranges, dead ports) ~35 min; initial blocks and $readmemh exactly as the AST front end lowers them | |
| # (readmem loop, address trim in wreduce, $meminit priorities) ~30 min; opt_mem's constant-lane test over the raw | |
| # $meminit cells and get_init_data ~20 min; port memory_libmap / memlib geometry, cost and selection ~40 min; the | |
| # INIT emission (gen_swizzle, INIT row loop, clean_undef) and the digest ~25 min; checks ~20 min. | |
| expert_time_estimate_min = 170 | |
| junior_time_estimate_min = 1500 | |
| [verifier] | |
| # The estimator is run as an unprivileged user on 256 hidden queries, 20 s per query (the reference needs < 0.3 s). | |
| timeout_sec = 7200.0 | |
| environment_mode = "separate" | |
| [agent] | |
| timeout_sec = 7200.0 | |
| [environment] | |
| build_timeout_sec = 1800.0 | |
| cpus = 4 | |
| memory_mb = 8192 | |
| storage_mb = 10240 | |
| network_mode = "no-network" | |