Ingest 'M. Morris Mano, Michael D. Ciletti' (hybrid-winocr + Linearized + Arctic 256-d Index)

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@@ -106,3 +106,5 @@ data/pdfs/fundamentals_of_digital_logic_with_verilog_design_third_edition.pdf fi
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+    "title": "M. Morris Mano, Michael D. Ciletti",
+    "author": "Digital Design With an Introduction to the Verilog HDL-Prentice Hall",
+    "totalPages": 565,
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+    "category": "Electronics",
+    "tags": [
+      "Electrical Circuits",
+      "Algorithms & Data Structures",
+      "System Design",
+      "MLOps & ML Systems",
+      "Operating Systems"
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+      {
+        "level": 1,
+        "title": "Cover",
+        "page": 1
+      },
+      {
+        "level": 1,
+        "title": "Title Page",
+        "page": 5
+      },
+      {
+        "level": 1,
+        "title": "Copyright Page",
+        "page": 6
+      },
+      {
+        "level": 1,
+        "title": "Contents",
+        "page": 7
+      },
+      {
+        "level": 1,
+        "title": "Preface",
+        "page": 11
+      },
+      {
+        "level": 1,
+        "title": "1 Digital Systems and Binary Numbers",
+        "page": 19
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+      {
+        "level": 2,
+        "title": "1.1 Digital Systems",
+        "page": 19
+      },
+      {
+        "level": 2,
+        "title": "1.2 Binary Numbers",
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+      {
+        "level": 2,
+        "title": "1.3 Number-Base Conversions",
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+      {
+        "level": 2,
+        "title": "1.4 Octal and Hexadecimal Numbers",
+        "page": 26
+      },
+      {
+        "level": 2,
+        "title": "1.5 Complements of Numbers",
+        "page": 28
+      },
+      {
+        "level": 2,
+        "title": "1.6 Signed Binary Numbers",
+        "page": 32
+      },
+      {
+        "level": 2,
+        "title": "1.7 Binary Codes",
+        "page": 36
+      },
+      {
+        "level": 2,
+        "title": "1.8 Binary Storage and Registers",
+        "page": 45
+      },
+      {
+        "level": 2,
+        "title": "1.9 Binary Logic",
+        "page": 48
+      },
+      {
+        "level": 1,
+        "title": "2 Boolean Algebra and Logic Gates",
+        "page": 56
+      },
+      {
+        "level": 2,
+        "title": "2.1 Introduction",
+        "page": 56
+      },
+      {
+        "level": 2,
+        "title": "2.2 Basic Definitions",
+        "page": 56
+      },
+      {
+        "level": 2,
+        "title": "2.3 Axiomatic Definition of Boolean Algebra",
+        "page": 58
+      },
+      {
+        "level": 2,
+        "title": "2.4 Basic Theorems and Properties of Boolean Algebra",
+        "page": 61
+      },
+      {
+        "level": 2,
+        "title": "2.5 Boolean Functions",
+        "page": 64
+      },
+      {
+        "level": 2,
+        "title": "2.6 Canonical and Standard Forms",
+        "page": 69
+      },
+      {
+        "level": 2,
+        "title": "2.7 Other Logic Operations",
+        "page": 76
+      },
+      {
+        "level": 2,
+        "title": "2.8 Digital Logic Gates",
+        "page": 78
+      },
+      {
+        "level": 2,
+        "title": "2.9 Integrated Circuits",
+        "page": 84
+      },
+      {
+        "level": 1,
+        "title": "3 Gate-Level Minimization",
+        "page": 91
+      },
+      {
+        "level": 2,
+        "title": "3.1 Introduction",
+        "page": 91
+      },
+      {
+        "level": 2,
+        "title": "3.2 The Map Method",
+        "page": 91
+      },
+      {
+        "level": 2,
+        "title": "3.3 Four-Variable K-Map",
+        "page": 98
+      },
+      {
+        "level": 2,
+        "title": "3.4 Product-of-Sums Simplification",
+        "page": 102
+      },
+      {
+        "level": 2,
+        "title": "3.5 Don't-Care Conditions",
+        "page": 106
+      },
+      {
+        "level": 2,
+        "title": "3.6 NAND and NOR Implementation",
+        "page": 108
+      },
+      {
+        "level": 2,
+        "title": "3.7 Other Two-Level Implementations",
+        "page": 115
+      },
+      {
+        "level": 2,
+        "title": "3.8 Exclusive-OR Function",
+        "page": 121
+      },
+      {
+        "level": 2,
+        "title": "3.9 Hardware Description Language",
+        "page": 126
+      },
+      {
+        "level": 1,
+        "title": "4 Combinational Logic",
+        "page": 143
+      },
+      {
+        "level": 2,
+        "title": "4.1 Introduction",
+        "page": 143
+      },
+      {
+        "level": 2,
+        "title": "4.2 Combinational Circuits",
+        "page": 143
+      },
+      {
+        "level": 2,
+        "title": "4.3 Analysis Procedure",
+        "page": 144
+      },
+      {
+        "level": 2,
+        "title": "4.4 Design Procedure",
+        "page": 147
+      },
+      {
+        "level": 2,
+        "title": "4.5 Binary Adder–Subtractor",
+        "page": 151
+      },
+      {
+        "level": 2,
+        "title": "4.6 Decimal Adder",
+        "page": 162
+      },
+      {
+        "level": 2,
+        "title": "4.7 Binary Multiplier",
+        "page": 164
+      },
+      {
+        "level": 2,
+        "title": "4.8 Magnitude Comparator",
+        "page": 166
+      },
+      {
+        "level": 2,
+        "title": "4.9 Decoders",
+        "page": 168
+      },
+      {
+        "level": 2,
+        "title": "4.10 Encoders",
+        "page": 173
+      },
+      {
+        "level": 2,
+        "title": "4.11 Multiplexers",
+        "page": 176
+      },
+      {
+        "level": 2,
+        "title": "4.12 HDL Models of Combinational Circuits",
+        "page": 182
+      },
+      {
+        "level": 1,
+        "title": "5 Synchronous Sequential Logic",
+        "page": 208
+      },
+      {
+        "level": 2,
+        "title": "5.1 Introduction",
+        "page": 208
+      },
+      {
+        "level": 2,
+        "title": "5.2 Sequential Circuits",
+        "page": 208
+      },
+      {
+        "level": 2,
+        "title": "5.3 Storage Elements: Latches",
+        "page": 211
+      },
+      {
+        "level": 2,
+        "title": "5.4 Storage Elements: Flip-Flops",
+        "page": 214
+      },
+      {
+        "level": 2,
+        "title": "5.5 Analysis of Clocked Sequential Circuits",
+        "page": 222
+      },
+      {
+        "level": 2,
+        "title": "5.6 Synthesizable HDL Models of Sequential Circuits",
+        "page": 235
+      },
+      {
+        "level": 2,
+        "title": "5.7 State Reduction and Assignment",
+        "page": 249
+      },
+      {
+        "level": 2,
+        "title": "5.8 Design Procedure",
+        "page": 254
+      },
+      {
+        "level": 1,
+        "title": "6 Registers and Counters",
+        "page": 273
+      },
+      {
+        "level": 2,
+        "title": "6.1 Registers",
+        "page": 273
+      },
+      {
+        "level": 2,
+        "title": "6.2 Shift Registers",
+        "page": 276
+      },
+      {
+        "level": 2,
+        "title": "6.3 Ripple Counters",
+        "page": 284
+      },
+      {
+        "level": 2,
+        "title": "6.4 Synchronous Counters",
+        "page": 289
+      },
+      {
+        "level": 2,
+        "title": "6.5 Other Counters",
+        "page": 296
+      },
+      {
+        "level": 2,
+        "title": "6.6 HDL for Registers and Counters",
+        "page": 301
+      },
+      {
+        "level": 1,
+        "title": "7 Memory and Programmable Logic",
+        "page": 317
+      },
+      {
+        "level": 2,
+        "title": "7.1 Introduction",
+        "page": 317
+      },
+      {
+        "level": 2,
+        "title": "7.2 Random-Access Memory",
+        "page": 318
+      },
+      {
+        "level": 2,
+        "title": "7.3 Memory Decoding",
+        "page": 325
+      },
+      {
+        "level": 2,
+        "title": "7.4 Error Detection and Correction",
+        "page": 330
+      },
+      {
+        "level": 2,
+        "title": "7.5 Read-Only Memory",
+        "page": 333
+      },
+      {
+        "level": 2,
+        "title": "7.6 Programmable Logic Array",
+        "page": 339
+      },
+      {
+        "level": 2,
+        "title": "7.7 Programmable Array Logic",
+        "page": 343
+      },
+      {
+        "level": 2,
+        "title": "7.8 Sequential Programmable Devices",
+        "page": 347
+      },
+      {
+        "level": 1,
+        "title": "8 Design at the Register Transfer Level",
+        "page": 369
+      },
+      {
+        "level": 2,
+        "title": "8.1 Introduction",
+        "page": 369
+      },
+      {
+        "level": 2,
+        "title": "8.2 Register Transfer Level Notation",
+        "page": 369
+      },
+      {
+        "level": 2,
+        "title": "8.3 Register Transfer Level in HDL",
+        "page": 372
+      },
+      {
+        "level": 2,
+        "title": "8.4 Algorithmic State Machines (ASMs)",
+        "page": 381
+      },
+      {
+        "level": 2,
+        "title": "8.5 Design Example (ASMD Chart)",
+        "page": 389
+      },
+      {
+        "level": 2,
+        "title": "8.6 HDL Description of Design Example",
+        "page": 399
+      },
+      {
+        "level": 2,
+        "title": "8.7 Sequential Binary Multiplier",
+        "page": 409
+      },
+      {
+        "level": 2,
+        "title": "8.8 Control Logic",
+        "page": 414
+      },
+      {
+        "level": 2,
+        "title": "8.9 HDL Description of Binary Multiplier",
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+      },
+      {
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+      {
+        "level": 2,
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+        "page": 440
+      },
+      {
+        "level": 2,
+        "title": "8.12 Latch-Free Design (Why Waste Silicon?)",
+        "page": 443
+      },
+      {
+        "level": 2,
+        "title": "8.13 Other Language Features",
+        "page": 444
+      },
+      {
+        "level": 1,
+        "title": "9 Laboratory Experiments with Standard ICs and FPGAs",
+        "page": 456
+      },
+      {
+        "level": 2,
+        "title": "9.1 Introduction to Experiments",
+        "page": 456
+      },
+      {
+        "level": 2,
+        "title": "9.2 Experiment 1: Binary and Decimal Numbers",
+        "page": 461
+      },
+      {
+        "level": 2,
+        "title": "9.3 Experiment 2: Digital Logic Gates",
+        "page": 464
+      },
+      {
+        "level": 2,
+        "title": "9.4 Experiment 3: Simplification of Boolean Functions",
+        "page": 466
+      },
+      {
+        "level": 2,
+        "title": "9.5 Experiment 4: Combinational Circuits",
+        "page": 468
+      },
+      {
+        "level": 2,
+        "title": "9.6 Experiment 5: Code Converters",
+        "page": 470
+      },
+      {
+        "level": 2,
+        "title": "9.7 Experiment 6: Design with Multiplexers",
+        "page": 471
+      },
+      {
+        "level": 2,
+        "title": "9.8 Experiment 7: Adders and Subtractors",
+        "page": 473
+      },
+      {
+        "level": 2,
+        "title": "9.9 Experiment 8: Flip-Flops",
+        "page": 475
+      },
+      {
+        "level": 2,
+        "title": "9.10 Experiment 9: Sequential Circuits",
+        "page": 478
+      },
+      {
+        "level": 2,
+        "title": "9.11 Experiment 10: Counters",
+        "page": 479
+      },
+      {
+        "level": 2,
+        "title": "9.12 Experiment 11: Shift Registers",
+        "page": 481
+      },
+      {
+        "level": 2,
+        "title": "9.13 Experiment 12: Serial Addition",
+        "page": 484
+      },
+      {
+        "level": 2,
+        "title": "9.14 Experiment 13: Memory Unit",
+        "page": 485
+      },
+      {
+        "level": 2,
+        "title": "9.15 Experiment 14: Lamp Handball",
+        "page": 487
+      },
+      {
+        "level": 2,
+        "title": "9.16 Experiment 15: Clock-Pulse Generator",
+        "page": 491
+      },
+      {
+        "level": 2,
+        "title": "9.17 Experiment 16: Parallel Adder and Accumulator",
+        "page": 493
+      },
+      {
+        "level": 2,
+        "title": "9.18 Experiment 17: Binary Multiplier",
+        "page": 496
+      },
+      {
+        "level": 2,
+        "title": "9.19 Verilog HDL Simulation Experiments and Rapid Prototyping with FPGAs",
+        "page": 498
+      },
+      {
+        "level": 1,
+        "title": "10 Standard Graphic Symbols",
+        "page": 506
+      },
+      {
+        "level": 2,
+        "title": "10.1 Rectangular-Shape Symbols",
+        "page": 506
+      },
+      {
+        "level": 2,
+        "title": "10.2 Qualifying Symbols",
+        "page": 509
+      },
+      {
+        "level": 2,
+        "title": "10.3 Dependency Notation",
+        "page": 511
+      },
+      {
+        "level": 2,
+        "title": "10.4 Symbols for Combinational Elements",
+        "page": 513
+      },
+      {
+        "level": 2,
+        "title": "10.5 Symbols for Flip-Flops",
+        "page": 515
+      },
+      {
+        "level": 2,
+        "title": "10.6 Symbols for Registers",
+        "page": 517
+      },
+      {
+        "level": 2,
+        "title": "10.7 Symbols for Counters",
+        "page": 520
+      },
+      {
+        "level": 2,
+        "title": "10.8 Symbol for RAM",
+        "page": 522
+      },
+      {
+        "level": 1,
+        "title": "Appendix",
+        "page": 525
+      },
+      {
+        "level": 1,
+        "title": "Answers to Selected Problems",
+        "page": 539
+      },
+      {
+        "level": 1,
+        "title": "Index",
+        "page": 557
+      },
+      {
+        "level": 2,
+        "title": "A",
+        "page": 557
+      },
+      {
+        "level": 2,
+        "title": "B",
+        "page": 557
+      },
+      {
+        "level": 2,
+        "title": "C",
+        "page": 558
+      },
+      {
+        "level": 2,
+        "title": "D",
+        "page": 559
+      },
+      {
+        "level": 2,
+        "title": "E",
+        "page": 559
+      },
+      {
+        "level": 2,
+        "title": "F",
+        "page": 560
+      },
+      {
+        "level": 2,
+        "title": "G",
+        "page": 560
+      },
+      {
+        "level": 2,
+        "title": "H",
+        "page": 560
+      },
+      {
+        "level": 2,
+        "title": "I",
+        "page": 560
+      },
+      {
+        "level": 2,
+        "title": "J",
+        "page": 561
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+      {
+        "level": 2,
+        "title": "K",
+        "page": 561
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+        "title": "L",
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+        "title": "R",
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+        "title": "S",
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+        "title": "W",
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+      },
+      {
+        "level": 2,
+        "title": "X",
+        "page": 565
+      }
+    ]
   }
 ]

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