Ingest 'Fundamentals of Digital Logic with Verilog Design, THIRD EDITION' (hybrid-winocr + Linearized + Arctic 256-d Index)

.gitattributes

@@ -102,3 +102,5 @@ data/pdfs/digital_electronics_by_flyod.pdf filter=lfs diff=lfs merge=lfs -text
 data/layouts/digital_electronics_by_flyod.json filter=lfs diff=lfs merge=lfs -text
 data/pdfs/digital_systems_principles_and_applications_10th_edition_tocci_w.pdf filter=lfs diff=lfs merge=lfs -text
 data/layouts/digital_systems_principles_and_applications_10th_edition_tocci_w.json filter=lfs diff=lfs merge=lfs -text
+data/pdfs/fundamentals_of_digital_logic_with_verilog_design_third_edition.pdf filter=lfs diff=lfs merge=lfs -text
+data/layouts/fundamentals_of_digital_logic_with_verilog_design_third_edition.json filter=lfs diff=lfs merge=lfs -text

data/catalog.json

@@ -20869,5 +20869,2006 @@
         "page": 969
       }
     ]
+  },
+  {
+    "id": "fundamentals_of_digital_logic_with_verilog_design_third_edition",
+    "title": "Fundamentals of Digital Logic with Verilog Design, THIRD EDITION",
+    "author": "Stephen Brown and Zvonko Vranesic",
+    "totalPages": 864,
+    "fileSize": 6280229,
+    "category": "Electronics",
+    "tags": [
+      "Electrical Circuits",
+      "Algorithms & Data Structures",
+      "Fundamentals",
+      "Electronics",
+      "Signal Processing"
+    ],
+    "coverUrl": "data/covers/fundamentals_of_digital_logic_with_verilog_design_third_edition.png",
+    "pdfUrl": "data/pdfs/fundamentals_of_digital_logic_with_verilog_design_third_edition.pdf",
+    "layoutUrl": "data/layouts/fundamentals_of_digital_logic_with_verilog_design_third_edition.json",
+    "linearized": true,
+    "toc": [
+      {
+        "level": 1,
+        "title": "Cover",
+        "page": 1
+      },
+      {
+        "level": 1,
+        "title": "Title",
+        "page": 2
+      },
+      {
+        "level": 1,
+        "title": "Copyright",
+        "page": 3
+      },
+      {
+        "level": 1,
+        "title": "Contents",
+        "page": 12
+      },
+      {
+        "level": 1,
+        "title": "Chapter 1 Introduction",
+        "page": 18
+      },
+      {
+        "level": 2,
+        "title": "1.1 Digital Hardware",
+        "page": 19
+      },
+      {
+        "level": 3,
+        "title": "1.1.1 Standard Chips",
+        "page": 21
+      },
+      {
+        "level": 3,
+        "title": "1.1.2 Programmable Logic Devices",
+        "page": 22
+      },
+      {
+        "level": 3,
+        "title": "1.1.3 Custom-Designed Chips",
+        "page": 22
+      },
+      {
+        "level": 2,
+        "title": "1.2 The Design Process",
+        "page": 23
+      },
+      {
+        "level": 2,
+        "title": "1.3 Structure of a Computer",
+        "page": 25
+      },
+      {
+        "level": 2,
+        "title": "1.4 Logic Circuit Design in This Book",
+        "page": 25
+      },
+      {
+        "level": 2,
+        "title": "1.5 Digital Representation of Information",
+        "page": 28
+      },
+      {
+        "level": 3,
+        "title": "1.5.1 Binary Numbers",
+        "page": 29
+      },
+      {
+        "level": 3,
+        "title": "1.5.2 Conversion between Decimal and Binary Systems",
+        "page": 30
+      },
+      {
+        "level": 3,
+        "title": "1.5.3 ASCII Character Code",
+        "page": 31
+      },
+      {
+        "level": 3,
+        "title": "1.5.4 Digital and Analog Information",
+        "page": 33
+      },
+      {
+        "level": 2,
+        "title": "1.6 Theory and Practice",
+        "page": 33
+      },
+      {
+        "level": 2,
+        "title": "Problems",
+        "page": 35
+      },
+      {
+        "level": 2,
+        "title": "References",
+        "page": 36
+      },
+      {
+        "level": 1,
+        "title": "Chapter 2 Introduction to Logic Circuits",
+        "page": 38
+      },
+      {
+        "level": 2,
+        "title": "2.1 Variables and Functions",
+        "page": 39
+      },
+      {
+        "level": 2,
+        "title": "2.2 Inversion",
+        "page": 42
+      },
+      {
+        "level": 2,
+        "title": "2.3 Truth Tables",
+        "page": 43
+      },
+      {
+        "level": 2,
+        "title": "2.4 Logic Gates and Networks",
+        "page": 44
+      },
+      {
+        "level": 3,
+        "title": "2.4.1 Analysis of a Logic Network",
+        "page": 46
+      },
+      {
+        "level": 2,
+        "title": "2.5 Boolean Algebra",
+        "page": 50
+      },
+      {
+        "level": 3,
+        "title": "2.5.1 The Venn Diagram",
+        "page": 54
+      },
+      {
+        "level": 3,
+        "title": "2.5.2 Notation and Terminology",
+        "page": 59
+      },
+      {
+        "level": 3,
+        "title": "2.5.3 Precedence of Operations",
+        "page": 60
+      },
+      {
+        "level": 2,
+        "title": "2.6 Synthesis Using AND, OR, and NOT Gates",
+        "page": 60
+      },
+      {
+        "level": 3,
+        "title": "2.6.1 Sum-of-Products and Product-of-Sums Forms",
+        "page": 65
+      },
+      {
+        "level": 2,
+        "title": "2.7 NAND and NOR Logic Networks",
+        "page": 71
+      },
+      {
+        "level": 2,
+        "title": "2.8 Design Examples",
+        "page": 76
+      },
+      {
+        "level": 3,
+        "title": "2.8.1 Three-Way Light Control",
+        "page": 76
+      },
+      {
+        "level": 3,
+        "title": "2.8.2 Multiplexer Circuit",
+        "page": 77
+      },
+      {
+        "level": 3,
+        "title": "2.8.3 Number Display",
+        "page": 80
+      },
+      {
+        "level": 2,
+        "title": "2.9 Introduction to CAD Tools",
+        "page": 81
+      },
+      {
+        "level": 3,
+        "title": "2.9.1 Design Entry",
+        "page": 81
+      },
+      {
+        "level": 3,
+        "title": "2.9.2 Logic Synthesis",
+        "page": 83
+      },
+      {
+        "level": 3,
+        "title": "2.9.3 Functional Simulation",
+        "page": 84
+      },
+      {
+        "level": 3,
+        "title": "2.9.4 Physical Design",
+        "page": 84
+      },
+      {
+        "level": 3,
+        "title": "2.9.5 Timing Simulation",
+        "page": 84
+      },
+      {
+        "level": 3,
+        "title": "2.9.6 Circuit Implementation",
+        "page": 85
+      },
+      {
+        "level": 3,
+        "title": "2.9.7 Complete Design Flow",
+        "page": 85
+      },
+      {
+        "level": 2,
+        "title": "2.10 Introduction to Verilog",
+        "page": 85
+      },
+      {
+        "level": 3,
+        "title": "2.10.1 Structural Specification of Logic Circuits",
+        "page": 87
+      },
+      {
+        "level": 3,
+        "title": "2.10.2 Behavioral Specification of Logic Circuits",
+        "page": 89
+      },
+      {
+        "level": 3,
+        "title": "2.10.3 Hierarchical Verilog Code",
+        "page": 93
+      },
+      {
+        "level": 3,
+        "title": "2.10.4 How NOT to Write Verilog Code",
+        "page": 95
+      },
+      {
+        "level": 2,
+        "title": "2.11 Minimization and Karnaugh Maps",
+        "page": 95
+      },
+      {
+        "level": 2,
+        "title": "2.12 Strategy for Minimization",
+        "page": 104
+      },
+      {
+        "level": 3,
+        "title": "2.12.1 Terminology",
+        "page": 104
+      },
+      {
+        "level": 3,
+        "title": "2.12.2 Minimization Procedure",
+        "page": 106
+      },
+      {
+        "level": 2,
+        "title": "2.13 Minimization of Product-of-Sums Forms",
+        "page": 108
+      },
+      {
+        "level": 2,
+        "title": "2.14 Incompletely Specified Functions",
+        "page": 111
+      },
+      {
+        "level": 2,
+        "title": "2.15 Multiple-Output Circuits",
+        "page": 113
+      },
+      {
+        "level": 2,
+        "title": "2.16 Concluding Remarks",
+        "page": 118
+      },
+      {
+        "level": 2,
+        "title": "2.17 Examples of Solved Problems",
+        "page": 118
+      },
+      {
+        "level": 2,
+        "title": "Problems",
+        "page": 128
+      },
+      {
+        "level": 2,
+        "title": "References",
+        "page": 137
+      },
+      {
+        "level": 1,
+        "title": "Chapter 3 Number Representation and Arithmetic Circuits",
+        "page": 138
+      },
+      {
+        "level": 2,
+        "title": "3.1 Positional Number Representation",
+        "page": 139
+      },
+      {
+        "level": 3,
+        "title": "3.1.1 Unsigned Integers",
+        "page": 139
+      },
+      {
+        "level": 3,
+        "title": "3.1.2 Octal and Hexadecimal Representations",
+        "page": 140
+      },
+      {
+        "level": 2,
+        "title": "3.2 Addition of Unsigned Numbers",
+        "page": 142
+      },
+      {
+        "level": 3,
+        "title": "3.2.1 Decomposed Full-Adder",
+        "page": 146
+      },
+      {
+        "level": 3,
+        "title": "3.2.2 Ripple-Carry Adder",
+        "page": 146
+      },
+      {
+        "level": 3,
+        "title": "3.2.3 Design Example",
+        "page": 147
+      },
+      {
+        "level": 2,
+        "title": "3.3 Signed Numbers",
+        "page": 149
+      },
+      {
+        "level": 3,
+        "title": "3.3.1 Negative Numbers",
+        "page": 150
+      },
+      {
+        "level": 3,
+        "title": "3.3.2 Addition and Subtraction",
+        "page": 152
+      },
+      {
+        "level": 3,
+        "title": "3.3.3 Adder and Subtractor Unit",
+        "page": 155
+      },
+      {
+        "level": 3,
+        "title": "3.3.4 Radix-Complement Schemes*",
+        "page": 156
+      },
+      {
+        "level": 3,
+        "title": "3.3.5 Arithmetic Overflow",
+        "page": 160
+      },
+      {
+        "level": 3,
+        "title": "3.3.6 Performance Issues",
+        "page": 162
+      },
+      {
+        "level": 2,
+        "title": "3.4 Fast Adders",
+        "page": 162
+      },
+      {
+        "level": 3,
+        "title": "3.4.1 Carry-Lookahead Adder",
+        "page": 163
+      },
+      {
+        "level": 2,
+        "title": "3.5 Design of Arithmetic Circuits Using CAD Tools",
+        "page": 168
+      },
+      {
+        "level": 3,
+        "title": "3.5.1 Design of Arithmetic Circuits Using Schematic Capture",
+        "page": 168
+      },
+      {
+        "level": 3,
+        "title": "3.5.2 Design of Arithmetic Circuits Using Verilog",
+        "page": 169
+      },
+      {
+        "level": 3,
+        "title": "3.5.3 Using Vectored Signals",
+        "page": 172
+      },
+      {
+        "level": 3,
+        "title": "3.5.4 Using a Generic Specification",
+        "page": 173
+      },
+      {
+        "level": 3,
+        "title": "3.5.5 Nets and Variables in Verilog",
+        "page": 175
+      },
+      {
+        "level": 3,
+        "title": "3.5.6 Arithmetic Assignment Statements",
+        "page": 176
+      },
+      {
+        "level": 3,
+        "title": "3.5.7 Module Hierarchy in Verilog Code",
+        "page": 180
+      },
+      {
+        "level": 3,
+        "title": "3.5.8 Representation of Numbers in Verilog Code",
+        "page": 183
+      },
+      {
+        "level": 2,
+        "title": "3.6 Multiplication",
+        "page": 184
+      },
+      {
+        "level": 3,
+        "title": "3.6.1 Array Multiplier for Unsigned Numbers",
+        "page": 184
+      },
+      {
+        "level": 3,
+        "title": "3.6.2 Multiplication of Signed Numbers",
+        "page": 186
+      },
+      {
+        "level": 2,
+        "title": "3.7 Other Number Representations",
+        "page": 187
+      },
+      {
+        "level": 3,
+        "title": "3.7.1 Fixed-Point Numbers",
+        "page": 187
+      },
+      {
+        "level": 3,
+        "title": "3.7.2 Floating-Point Numbers",
+        "page": 189
+      },
+      {
+        "level": 3,
+        "title": "3.7.3 Binary-Coded-Decimal Representation",
+        "page": 191
+      },
+      {
+        "level": 2,
+        "title": "3.8 Examples of Solved Problems",
+        "page": 195
+      },
+      {
+        "level": 2,
+        "title": "Problems",
+        "page": 201
+      },
+      {
+        "level": 2,
+        "title": "References",
+        "page": 205
+      },
+      {
+        "level": 1,
+        "title": "Chapter 4 Combinational-Circuit Building Blocks",
+        "page": 206
+      },
+      {
+        "level": 2,
+        "title": "4.1 Multiplexers",
+        "page": 207
+      },
+      {
+        "level": 3,
+        "title": "4.1.1 Synthesis of Logic Functions Using Multiplexers",
+        "page": 210
+      },
+      {
+        "level": 3,
+        "title": "4.1.2 Multiplexer Synthesis Using Shannon's Expansion",
+        "page": 213
+      },
+      {
+        "level": 2,
+        "title": "4.2 Decoders",
+        "page": 218
+      },
+      {
+        "level": 3,
+        "title": "4.2.1 Demultiplexers",
+        "page": 220
+      },
+      {
+        "level": 2,
+        "title": "4.3 Encoders",
+        "page": 222
+      },
+      {
+        "level": 3,
+        "title": "4.3.1 Binary Encoders",
+        "page": 222
+      },
+      {
+        "level": 3,
+        "title": "4.3.2 Priority Encoders",
+        "page": 222
+      },
+      {
+        "level": 2,
+        "title": "4.4 Code Converters",
+        "page": 225
+      },
+      {
+        "level": 2,
+        "title": "4.5 Arithmetic Comparison Circuits",
+        "page": 225
+      },
+      {
+        "level": 2,
+        "title": "4.6 Verilog for Combinational Circuits",
+        "page": 227
+      },
+      {
+        "level": 3,
+        "title": "4.6.1 The Conditional Operator",
+        "page": 227
+      },
+      {
+        "level": 3,
+        "title": "4.6.2 The If-Else Statement",
+        "page": 229
+      },
+      {
+        "level": 3,
+        "title": "4.6.3 The Case Statement",
+        "page": 232
+      },
+      {
+        "level": 3,
+        "title": "4.6.4 The For Loop",
+        "page": 238
+      },
+      {
+        "level": 3,
+        "title": "4.6.5 Verilog Operators",
+        "page": 240
+      },
+      {
+        "level": 3,
+        "title": "4.6.6 The Generate Construct",
+        "page": 245
+      },
+      {
+        "level": 3,
+        "title": "4.6.7 Tasks and Functions",
+        "page": 246
+      },
+      {
+        "level": 2,
+        "title": "4.7 Concluding Remarks",
+        "page": 249
+      },
+      {
+        "level": 2,
+        "title": "4.8 Examples of Solved Problems",
+        "page": 250
+      },
+      {
+        "level": 2,
+        "title": "Problems",
+        "page": 260
+      },
+      {
+        "level": 2,
+        "title": "References",
+        "page": 263
+      },
+      {
+        "level": 1,
+        "title": "Chapter 5 Flip-Flops, Registers, and Counters",
+        "page": 264
+      },
+      {
+        "level": 2,
+        "title": "5.1 Basic Latch",
+        "page": 266
+      },
+      {
+        "level": 2,
+        "title": "5.2 Gated SR Latch",
+        "page": 268
+      },
+      {
+        "level": 3,
+        "title": "5.2.1 Gated SR Latch with NAND Gates",
+        "page": 270
+      },
+      {
+        "level": 2,
+        "title": "5.3 Gated D Latch",
+        "page": 270
+      },
+      {
+        "level": 3,
+        "title": "5.3.1 Effects of Propagation Delays",
+        "page": 272
+      },
+      {
+        "level": 2,
+        "title": "5.4 Edge-Triggered D Flip-Flops",
+        "page": 273
+      },
+      {
+        "level": 3,
+        "title": "5.4.1 Master-Slave D Flip-Flop",
+        "page": 273
+      },
+      {
+        "level": 3,
+        "title": "5.4.2 Other Types of Edge-Triggered D Flip-Flops",
+        "page": 275
+      },
+      {
+        "level": 3,
+        "title": "5.4.3 D Flip-Flops with Clear and Preset",
+        "page": 277
+      },
+      {
+        "level": 3,
+        "title": "5.4.4 Flip-Flop Timing Parameters",
+        "page": 280
+      },
+      {
+        "level": 2,
+        "title": "5.5 T Flip-Flop",
+        "page": 280
+      },
+      {
+        "level": 2,
+        "title": "5.6 JK Flip-Flop",
+        "page": 281
+      },
+      {
+        "level": 2,
+        "title": "5.7 Summary of Terminology",
+        "page": 283
+      },
+      {
+        "level": 2,
+        "title": "5.8 Registers",
+        "page": 284
+      },
+      {
+        "level": 3,
+        "title": "5.8.1 Shift Register",
+        "page": 284
+      },
+      {
+        "level": 3,
+        "title": "5.8.2 Parallel-Access Shift Register",
+        "page": 284
+      },
+      {
+        "level": 2,
+        "title": "5.9 Counters",
+        "page": 286
+      },
+      {
+        "level": 3,
+        "title": "5.9.1 Asynchronous Counters",
+        "page": 286
+      },
+      {
+        "level": 3,
+        "title": "5.9.2 Synchronous Counters",
+        "page": 289
+      },
+      {
+        "level": 3,
+        "title": "5.9.3 Counters with Parallel Load",
+        "page": 293
+      },
+      {
+        "level": 2,
+        "title": "5.10 Reset Synchronization",
+        "page": 295
+      },
+      {
+        "level": 2,
+        "title": "5.11 Other Types of Counters",
+        "page": 297
+      },
+      {
+        "level": 3,
+        "title": "5.11.1 BCD Counter",
+        "page": 297
+      },
+      {
+        "level": 3,
+        "title": "5.11.2 Ring Counter",
+        "page": 297
+      },
+      {
+        "level": 3,
+        "title": "5.11.3 Johnson Counter",
+        "page": 300
+      },
+      {
+        "level": 3,
+        "title": "5.11.4 Remarks on Counter Design",
+        "page": 300
+      },
+      {
+        "level": 2,
+        "title": "5.12 Using Storage Elements with CAD Tools",
+        "page": 301
+      },
+      {
+        "level": 3,
+        "title": "5.12.1 Including Storage Elements in Schematics",
+        "page": 301
+      },
+      {
+        "level": 3,
+        "title": "5.12.2 Using Verilog Constructs for Storage Elements",
+        "page": 302
+      },
+      {
+        "level": 3,
+        "title": "5.12.3 Blocking and Non-Blocking Assignments",
+        "page": 305
+      },
+      {
+        "level": 3,
+        "title": "5.12.4 Non-Blocking Assignments for Combinational Circuits",
+        "page": 310
+      },
+      {
+        "level": 3,
+        "title": "5.12.5 Flip-Flops with Clear Capability",
+        "page": 310
+      },
+      {
+        "level": 2,
+        "title": "5.13 Using Verilog Constructs for Registers and Counters",
+        "page": 312
+      },
+      {
+        "level": 3,
+        "title": "5.13.1 Flip-Flops and Registers with Enable Inputs",
+        "page": 317
+      },
+      {
+        "level": 3,
+        "title": "5.13.2 Shift Registers with Enable Inputs",
+        "page": 319
+      },
+      {
+        "level": 2,
+        "title": "5.14 Design Example",
+        "page": 319
+      },
+      {
+        "level": 3,
+        "title": "5.14.1 Reaction Timer",
+        "page": 319
+      },
+      {
+        "level": 3,
+        "title": "5.14.2 Register Transfer Level (RTL) Code",
+        "page": 326
+      },
+      {
+        "level": 2,
+        "title": "5.15 Timing Analysis of Flip-flop Circuits",
+        "page": 327
+      },
+      {
+        "level": 3,
+        "title": "5.15.1 Timing Analysis with Clock Skew",
+        "page": 329
+      },
+      {
+        "level": 2,
+        "title": "5.16 Concluding Remarks",
+        "page": 331
+      },
+      {
+        "level": 2,
+        "title": "5.17 Examples of Solved Problems",
+        "page": 332
+      },
+      {
+        "level": 2,
+        "title": "Problems",
+        "page": 338
+      },
+      {
+        "level": 2,
+        "title": "References",
+        "page": 346
+      },
+      {
+        "level": 1,
+        "title": "Chapter 6 Synchronous Sequential Circuits",
+        "page": 348
+      },
+      {
+        "level": 2,
+        "title": "6.1 Basic Design Steps",
+        "page": 350
+      },
+      {
+        "level": 3,
+        "title": "6.1.1 State Diagram",
+        "page": 350
+      },
+      {
+        "level": 3,
+        "title": "6.1.2 State Table",
+        "page": 352
+      },
+      {
+        "level": 3,
+        "title": "6.1.3 State Assignment",
+        "page": 353
+      },
+      {
+        "level": 3,
+        "title": "6.1.4 Choice of Flip-Flops and Derivation of Next-State and Output Expressions",
+        "page": 354
+      },
+      {
+        "level": 3,
+        "title": "6.1.5 Timing Diagram",
+        "page": 356
+      },
+      {
+        "level": 3,
+        "title": "6.1.6 Summary of Design Steps",
+        "page": 357
+      },
+      {
+        "level": 2,
+        "title": "6.2 State-Assignment Problem",
+        "page": 361
+      },
+      {
+        "level": 3,
+        "title": "6.2.1 One-Hot Encoding",
+        "page": 364
+      },
+      {
+        "level": 2,
+        "title": "6.3 Mealy State Model",
+        "page": 366
+      },
+      {
+        "level": 2,
+        "title": "6.4 Design of Finite State Machines Using CAD Tools",
+        "page": 371
+      },
+      {
+        "level": 3,
+        "title": "6.4.1 Verilog Code for Moore-Type FSMs",
+        "page": 372
+      },
+      {
+        "level": 3,
+        "title": "6.4.2 Synthesis of Verilog Code",
+        "page": 373
+      },
+      {
+        "level": 3,
+        "title": "6.4.3 Simulating and Testing the Circuit",
+        "page": 375
+      },
+      {
+        "level": 3,
+        "title": "6.4.4 Alternative Styles of Verilog Code",
+        "page": 376
+      },
+      {
+        "level": 3,
+        "title": "6.4.5 Summary of Design Steps When Using CAD Tools",
+        "page": 377
+      },
+      {
+        "level": 3,
+        "title": "6.4.6 Specifying the State Assignment in Verilog Code",
+        "page": 378
+      },
+      {
+        "level": 3,
+        "title": "6.4.7 Specification of Mealy FSMs Using Verilog",
+        "page": 380
+      },
+      {
+        "level": 2,
+        "title": "6.5 Serial Adder Example",
+        "page": 380
+      },
+      {
+        "level": 3,
+        "title": "6.5.1 Mealy-Type FSM for Serial Adder",
+        "page": 381
+      },
+      {
+        "level": 3,
+        "title": "6.5.2 Moore-Type FSM for Serial Adder",
+        "page": 384
+      },
+      {
+        "level": 3,
+        "title": "6.5.3 Verilog Code for the Serial Adder",
+        "page": 387
+      },
+      {
+        "level": 2,
+        "title": "6.6 State Minimization",
+        "page": 389
+      },
+      {
+        "level": 3,
+        "title": "6.6.1 Partitioning Minimization Procedure",
+        "page": 391
+      },
+      {
+        "level": 3,
+        "title": "6.6.2 Incompletely Specified FSMs",
+        "page": 398
+      },
+      {
+        "level": 2,
+        "title": "6.7 Design of a Counter Using the Sequential Circuit Approach",
+        "page": 400
+      },
+      {
+        "level": 3,
+        "title": "6.7.1 State Diagram and State Table for a Modulo-8 Counter",
+        "page": 400
+      },
+      {
+        "level": 3,
+        "title": "6.7.2 State Assignment",
+        "page": 401
+      },
+      {
+        "level": 3,
+        "title": "6.7.3 Implementation Using D-Type Flip-Flops",
+        "page": 402
+      },
+      {
+        "level": 3,
+        "title": "6.7.4 Implementation Using JK-Type Flip-Flops",
+        "page": 403
+      },
+      {
+        "level": 3,
+        "title": "6.7.5 Example—A Different Counter",
+        "page": 407
+      },
+      {
+        "level": 2,
+        "title": "6.8 FSM as an Arbiter Circuit",
+        "page": 410
+      },
+      {
+        "level": 2,
+        "title": "6.9 Analysis of Synchronous Sequential Circuits",
+        "page": 414
+      },
+      {
+        "level": 2,
+        "title": "6.10 Algorithmic State Machine (ASM) Charts",
+        "page": 418
+      },
+      {
+        "level": 2,
+        "title": "6.11 Formal Model for Sequential Circuits",
+        "page": 422
+      },
+      {
+        "level": 2,
+        "title": "6.12 Concluding Remarks",
+        "page": 424
+      },
+      {
+        "level": 2,
+        "title": "6.13 Examples of Solved Problems",
+        "page": 424
+      },
+      {
+        "level": 2,
+        "title": "Problems",
+        "page": 433
+      },
+      {
+        "level": 2,
+        "title": "References",
+        "page": 437
+      },
+      {
+        "level": 1,
+        "title": "Chapter 7 Digital System Design",
+        "page": 438
+      },
+      {
+        "level": 2,
+        "title": "7.1 Bus Structure",
+        "page": 439
+      },
+      {
+        "level": 3,
+        "title": "7.1.1 Using Tri-State Drivers to Implement a Bus",
+        "page": 439
+      },
+      {
+        "level": 3,
+        "title": "7.1.2 Using Multiplexers to Implement a Bus",
+        "page": 441
+      },
+      {
+        "level": 3,
+        "title": "7.1.3 Verilog Code for Specification of Bus Structures",
+        "page": 443
+      },
+      {
+        "level": 2,
+        "title": "7.2 Simple Processor",
+        "page": 446
+      },
+      {
+        "level": 2,
+        "title": "7.3 A Bit-Counting Circuit",
+        "page": 458
+      },
+      {
+        "level": 2,
+        "title": "7.4 Shift-and-Add Multiplier",
+        "page": 463
+      },
+      {
+        "level": 2,
+        "title": "7.5 Divider",
+        "page": 472
+      },
+      {
+        "level": 2,
+        "title": "7.6 Arithmetic Mean",
+        "page": 483
+      },
+      {
+        "level": 2,
+        "title": "7.7 Sort Operation",
+        "page": 487
+      },
+      {
+        "level": 2,
+        "title": "7.8 Clock Synchronization and Timing Issues",
+        "page": 495
+      },
+      {
+        "level": 3,
+        "title": "7.8.1 Clock Distribution",
+        "page": 495
+      },
+      {
+        "level": 3,
+        "title": "7.8.2 Flip-Flop Timing Parameters",
+        "page": 498
+      },
+      {
+        "level": 3,
+        "title": "7.8.3 Asynchronous Inputs to Flip-Flops",
+        "page": 499
+      },
+      {
+        "level": 3,
+        "title": "7.8.4 Switch Debouncing",
+        "page": 500
+      },
+      {
+        "level": 2,
+        "title": "7.9 Concluding Remarks",
+        "page": 502
+      },
+      {
+        "level": 2,
+        "title": "Problems",
+        "page": 502
+      },
+      {
+        "level": 2,
+        "title": "References",
+        "page": 506
+      },
+      {
+        "level": 1,
+        "title": "Chapter 8 Optimized Implementation of Logic Functions",
+        "page": 508
+      },
+      {
+        "level": 2,
+        "title": "8.1 Multilevel Synthesis",
+        "page": 509
+      },
+      {
+        "level": 3,
+        "title": "8.1.1 Factoring",
+        "page": 510
+      },
+      {
+        "level": 3,
+        "title": "8.1.2 Functional Decomposition",
+        "page": 513
+      },
+      {
+        "level": 3,
+        "title": "8.1.3 Multilevel NAND and NOR Circuits",
+        "page": 519
+      },
+      {
+        "level": 2,
+        "title": "8.2 Analysis of Multilevel Circuits",
+        "page": 521
+      },
+      {
+        "level": 2,
+        "title": "8.3 Alternative Representations of Logic Functions",
+        "page": 527
+      },
+      {
+        "level": 3,
+        "title": "8.3.1 Cubical Representation",
+        "page": 527
+      },
+      {
+        "level": 3,
+        "title": "8.3.2 Binary Decision Diagrams",
+        "page": 531
+      },
+      {
+        "level": 2,
+        "title": "8.4 Optimization Techniques Based on Cubical Representation",
+        "page": 537
+      },
+      {
+        "level": 3,
+        "title": "8.4.1 A Tabular Method for Minimization",
+        "page": 538
+      },
+      {
+        "level": 3,
+        "title": "8.4.2 A Cubical Technique for Minimization",
+        "page": 546
+      },
+      {
+        "level": 3,
+        "title": "8.4.3 Practical Considerations",
+        "page": 553
+      },
+      {
+        "level": 2,
+        "title": "8.5 Concluding Remarks",
+        "page": 554
+      },
+      {
+        "level": 2,
+        "title": "8.6 Examples of Solved Problems",
+        "page": 554
+      },
+      {
+        "level": 2,
+        "title": "Problems",
+        "page": 563
+      },
+      {
+        "level": 2,
+        "title": "References",
+        "page": 566
+      },
+      {
+        "level": 1,
+        "title": "Chapter 9 Asynchronous Sequential Circuits",
+        "page": 568
+      },
+      {
+        "level": 2,
+        "title": "9.1 Asynchronous Behavior",
+        "page": 569
+      },
+      {
+        "level": 2,
+        "title": "9.2 Analysis of Asynchronous Circuits",
+        "page": 573
+      },
+      {
+        "level": 2,
+        "title": "9.3 Synthesis of Asynchronous Circuits",
+        "page": 581
+      },
+      {
+        "level": 2,
+        "title": "9.4 State Reduction",
+        "page": 594
+      },
+      {
+        "level": 2,
+        "title": "9.5 State Assignment",
+        "page": 609
+      },
+      {
+        "level": 3,
+        "title": "9.5.1 Transition Diagram",
+        "page": 612
+      },
+      {
+        "level": 3,
+        "title": "9.5.2 Exploiting Unspecified Next-State Entries",
+        "page": 615
+      },
+      {
+        "level": 3,
+        "title": "9.5.3 State Assignment Using Additional State Variables",
+        "page": 619
+      },
+      {
+        "level": 3,
+        "title": "9.5.4 One-Hot State Assignment",
+        "page": 624
+      },
+      {
+        "level": 2,
+        "title": "9.6 Hazards",
+        "page": 625
+      },
+      {
+        "level": 3,
+        "title": "9.6.1 Static Hazards",
+        "page": 626
+      },
+      {
+        "level": 3,
+        "title": "9.6.2 Dynamic Hazards",
+        "page": 630
+      },
+      {
+        "level": 3,
+        "title": "9.6.3 Significance of Hazards",
+        "page": 631
+      },
+      {
+        "level": 2,
+        "title": "9.7 A Complete Design Example",
+        "page": 633
+      },
+      {
+        "level": 3,
+        "title": "9.7.1 The Vending-Machine Controller",
+        "page": 633
+      },
+      {
+        "level": 2,
+        "title": "9.8 Concluding Remarks",
+        "page": 638
+      },
+      {
+        "level": 2,
+        "title": "9.9 Examples of Solved Problems",
+        "page": 640
+      },
+      {
+        "level": 2,
+        "title": "Problems",
+        "page": 648
+      },
+      {
+        "level": 2,
+        "title": "References",
+        "page": 652
+      },
+      {
+        "level": 1,
+        "title": "Chapter 10 Computer Aided Design Tools",
+        "page": 654
+      },
+      {
+        "level": 2,
+        "title": "10.1 Synthesis",
+        "page": 655
+      },
+      {
+        "level": 3,
+        "title": "10.1.1 Netlist Generation",
+        "page": 655
+      },
+      {
+        "level": 3,
+        "title": "10.1.2 Gate Optimization",
+        "page": 655
+      },
+      {
+        "level": 3,
+        "title": "10.1.3 Technology Mapping",
+        "page": 657
+      },
+      {
+        "level": 2,
+        "title": "10.2 Physical Design",
+        "page": 661
+      },
+      {
+        "level": 3,
+        "title": "10.2.1 Placement",
+        "page": 663
+      },
+      {
+        "level": 3,
+        "title": "10.2.2 Routing",
+        "page": 664
+      },
+      {
+        "level": 3,
+        "title": "10.2.3 Static Timing Analysis",
+        "page": 665
+      },
+      {
+        "level": 2,
+        "title": "10.3 Concluding Remarks",
+        "page": 667
+      },
+      {
+        "level": 2,
+        "title": "References",
+        "page": 668
+      },
+      {
+        "level": 1,
+        "title": "Chapter 11 Testing of Logic Circuits",
+        "page": 670
+      },
+      {
+        "level": 2,
+        "title": "11.1 Fault Model",
+        "page": 671
+      },
+      {
+        "level": 3,
+        "title": "11.1.1 Stuck-at Model",
+        "page": 671
+      },
+      {
+        "level": 3,
+        "title": "11.1.2 Single and Multiple Faults",
+        "page": 672
+      },
+      {
+        "level": 3,
+        "title": "11.1.3 CMOS Circuits",
+        "page": 672
+      },
+      {
+        "level": 2,
+        "title": "11.2 Complexity of a Test Set",
+        "page": 672
+      },
+      {
+        "level": 2,
+        "title": "11.3 Path Sensitizing",
+        "page": 674
+      },
+      {
+        "level": 3,
+        "title": "11.3.1 Detection of a Specific Fault",
+        "page": 676
+      },
+      {
+        "level": 2,
+        "title": "11.4 Circuits with Tree Structure",
+        "page": 678
+      },
+      {
+        "level": 2,
+        "title": "11.5 Random Tests",
+        "page": 679
+      },
+      {
+        "level": 2,
+        "title": "11.6 Testing of Sequential Circuits",
+        "page": 682
+      },
+      {
+        "level": 3,
+        "title": "11.6.1 Design for Testability",
+        "page": 682
+      },
+      {
+        "level": 2,
+        "title": "11.7 Built-in Self-Test",
+        "page": 686
+      },
+      {
+        "level": 3,
+        "title": "11.7.1 Built-in Logic Block Observer",
+        "page": 690
+      },
+      {
+        "level": 3,
+        "title": "11.7.2 Signature Analysis",
+        "page": 692
+      },
+      {
+        "level": 3,
+        "title": "11.7.3 Boundary Scan",
+        "page": 693
+      },
+      {
+        "level": 2,
+        "title": "11.8 Printed Circuit Boards",
+        "page": 693
+      },
+      {
+        "level": 3,
+        "title": "11.8.1 Testing of PCBs",
+        "page": 695
+      },
+      {
+        "level": 3,
+        "title": "11.8.2 Instrumentation",
+        "page": 696
+      },
+      {
+        "level": 2,
+        "title": "11.9 Concluding Remarks",
+        "page": 697
+      },
+      {
+        "level": 2,
+        "title": "Problems",
+        "page": 697
+      },
+      {
+        "level": 2,
+        "title": "References",
+        "page": 700
+      },
+      {
+        "level": 1,
+        "title": "Appendix A: Verilog Reference",
+        "page": 702
+      },
+      {
+        "level": 2,
+        "title": "A.1 Documentation in Verilog Code",
+        "page": 703
+      },
+      {
+        "level": 2,
+        "title": "A.2 White Space",
+        "page": 703
+      },
+      {
+        "level": 2,
+        "title": "A.3 Signals in Verilog Code",
+        "page": 703
+      },
+      {
+        "level": 2,
+        "title": "A.4 Identifier Names",
+        "page": 704
+      },
+      {
+        "level": 2,
+        "title": "A.5 Signal Values, Numbers, and Parameters",
+        "page": 704
+      },
+      {
+        "level": 3,
+        "title": "A.5.1 Parameters",
+        "page": 705
+      },
+      {
+        "level": 2,
+        "title": "A.6 Net and Variable Types",
+        "page": 705
+      },
+      {
+        "level": 3,
+        "title": "A.6.1 Nets",
+        "page": 705
+      },
+      {
+        "level": 3,
+        "title": "A.6.2 Variables",
+        "page": 706
+      },
+      {
+        "level": 3,
+        "title": "A.6.3 Memories",
+        "page": 707
+      },
+      {
+        "level": 2,
+        "title": "A.7 Operators",
+        "page": 707
+      },
+      {
+        "level": 2,
+        "title": "A.8 Verilog Module",
+        "page": 709
+      },
+      {
+        "level": 2,
+        "title": "A.9 Gate Instantiations",
+        "page": 711
+      },
+      {
+        "level": 2,
+        "title": "A.10 Concurrent Statements",
+        "page": 713
+      },
+      {
+        "level": 3,
+        "title": "A.10.1 Continuous Assignments",
+        "page": 713
+      },
+      {
+        "level": 3,
+        "title": "A.10.2 Using Parameters",
+        "page": 714
+      },
+      {
+        "level": 2,
+        "title": "A.11 Procedural Statements",
+        "page": 715
+      },
+      {
+        "level": 3,
+        "title": "A.11.1 Always and Initial Blocks",
+        "page": 715
+      },
+      {
+        "level": 3,
+        "title": "A.11.2 The If-Else Statement",
+        "page": 717
+      },
+      {
+        "level": 3,
+        "title": "A.11.3 Statement Ordering",
+        "page": 718
+      },
+      {
+        "level": 3,
+        "title": "A.11.4 The Case Statement",
+        "page": 719
+      },
+      {
+        "level": 3,
+        "title": "A.11.5 Casez and Casex Statements",
+        "page": 720
+      },
+      {
+        "level": 3,
+        "title": "A.11.6 Loop Statements",
+        "page": 721
+      },
+      {
+        "level": 3,
+        "title": "A.11.7 Blocking versus Non-blocking Assignments for Combinational Circuits",
+        "page": 725
+      },
+      {
+        "level": 2,
+        "title": "A.12 Using Subcircuits",
+        "page": 726
+      },
+      {
+        "level": 3,
+        "title": "A.12.1 Subcircuit Parameters",
+        "page": 727
+      },
+      {
+        "level": 3,
+        "title": "A.12.2 The Generate Capability",
+        "page": 729
+      },
+      {
+        "level": 2,
+        "title": "A.13 Functions and Tasks",
+        "page": 730
+      },
+      {
+        "level": 2,
+        "title": "A.14 Sequential Circuits",
+        "page": 733
+      },
+      {
+        "level": 3,
+        "title": "A.14.1 A Gated D Latch",
+        "page": 734
+      },
+      {
+        "level": 3,
+        "title": "A.14.2 D Flip-Flop",
+        "page": 734
+      },
+      {
+        "level": 3,
+        "title": "A.14.3 Flip-Flops with Reset",
+        "page": 735
+      },
+      {
+        "level": 3,
+        "title": "A.14.4 Registers",
+        "page": 735
+      },
+      {
+        "level": 3,
+        "title": "A.14.5 Shift Registers",
+        "page": 737
+      },
+      {
+        "level": 3,
+        "title": "A.14.6 Counters",
+        "page": 738
+      },
+      {
+        "level": 3,
+        "title": "A.14.7 An Example of a Sequential Circuit",
+        "page": 739
+      },
+      {
+        "level": 3,
+        "title": "A.14.8 Moore-Type Finite State Machines",
+        "page": 740
+      },
+      {
+        "level": 3,
+        "title": "A.14.9 Mealy-Type Finite State Machines",
+        "page": 741
+      },
+      {
+        "level": 2,
+        "title": "A.15 Guidelines for Writing Verilog Code",
+        "page": 742
+      },
+      {
+        "level": 2,
+        "title": "A.16 Concluding Remarks",
+        "page": 748
+      },
+      {
+        "level": 2,
+        "title": "References",
+        "page": 748
+      },
+      {
+        "level": 1,
+        "title": "Appendix B: Implementation Technology",
+        "page": 750
+      },
+      {
+        "level": 2,
+        "title": "B.1 Transistor Switches",
+        "page": 751
+      },
+      {
+        "level": 2,
+        "title": "B.2 NMOS Logic Gates",
+        "page": 753
+      },
+      {
+        "level": 2,
+        "title": "B.3 CMOS Logic Gates",
+        "page": 756
+      },
+      {
+        "level": 3,
+        "title": "B.3.1 Speed of Logic Gate Circuits",
+        "page": 763
+      },
+      {
+        "level": 2,
+        "title": "B.4 Negative Logic System",
+        "page": 764
+      },
+      {
+        "level": 2,
+        "title": "B.5 Standard Chips",
+        "page": 766
+      },
+      {
+        "level": 3,
+        "title": "B.5.1 7400-Series Standard Chips",
+        "page": 766
+      },
+      {
+        "level": 2,
+        "title": "B.6 Programmable Logic Devices",
+        "page": 770
+      },
+      {
+        "level": 3,
+        "title": "B.6.1 Programmable Logic Array (PLA)",
+        "page": 771
+      },
+      {
+        "level": 3,
+        "title": "B.6.2 Programmable Array Logic (PAL)",
+        "page": 774
+      },
+      {
+        "level": 3,
+        "title": "B.6.3 Programming of PLAs and PALs",
+        "page": 776
+      },
+      {
+        "level": 3,
+        "title": "B.6.4 Complex Programmable Logic Devices (CPLDs)",
+        "page": 778
+      },
+      {
+        "level": 3,
+        "title": "B.6.5 Field-Programmable Gate Arrays",
+        "page": 781
+      },
+      {
+        "level": 2,
+        "title": "B.7 Custom Chips, Standard Cells, and Gate Arrays",
+        "page": 786
+      },
+      {
+        "level": 2,
+        "title": "B.8 Practical Aspects",
+        "page": 788
+      },
+      {
+        "level": 3,
+        "title": "B.8.1 MOSFET Fabrication and Behavior",
+        "page": 788
+      },
+      {
+        "level": 3,
+        "title": "B.8.2 MOSFET On-Resistance",
+        "page": 792
+      },
+      {
+        "level": 3,
+        "title": "B.8.3 Voltage Levels in Logic Gates",
+        "page": 793
+      },
+      {
+        "level": 3,
+        "title": "B.8.4 Noise Margin",
+        "page": 795
+      },
+      {
+        "level": 3,
+        "title": "B.8.5 Dynamic Operation of Logic Gates",
+        "page": 796
+      },
+      {
+        "level": 3,
+        "title": "B.8.6 Power Dissipation in Logic Gates",
+        "page": 799
+      },
+      {
+        "level": 3,
+        "title": "B.8.7 Passing 1s and 0s Through Transistor Switches",
+        "page": 801
+      },
+      {
+        "level": 3,
+        "title": "B.8.8 Transmission Gates",
+        "page": 803
+      },
+      {
+        "level": 3,
+        "title": "B.8.9 Fan-in and Fan-out in Logic Gates",
+        "page": 805
+      },
+      {
+        "level": 3,
+        "title": "B.8.10 Tri-state Drivers",
+        "page": 809
+      },
+      {
+        "level": 2,
+        "title": "B.9 Static Random Access Memory (SRAM)",
+        "page": 811
+      },
+      {
+        "level": 3,
+        "title": "B.9.1 SRAM Blocks in PLDs",
+        "page": 814
+      },
+      {
+        "level": 2,
+        "title": "B.10 Implementation Details for SPLDs, CPLDs, and FPGAs",
+        "page": 814
+      },
+      {
+        "level": 3,
+        "title": "B.10.1 Implementation in FPGAs",
+        "page": 821
+      },
+      {
+        "level": 2,
+        "title": "B.11 Concluding Remarks",
+        "page": 823
+      },
+      {
+        "level": 2,
+        "title": "B.12 Examples of Solved Problems",
+        "page": 824
+      },
+      {
+        "level": 2,
+        "title": "Problems",
+        "page": 831
+      },
+      {
+        "level": 2,
+        "title": "References",
+        "page": 840
+      },
+      {
+        "level": 1,
+        "title": "Answers",
+        "page": 842
+      },
+      {
+        "level": 1,
+        "title": "Index",
+        "page": 856
+      },
+      {
+        "level": 2,
+        "title": "A",
+        "page": 856
+      },
+      {
+        "level": 2,
+        "title": "B",
+        "page": 856
+      },
+      {
+        "level": 2,
+        "title": "C",
+        "page": 857
+      },
+      {
+        "level": 2,
+        "title": "D",
+        "page": 858
+      },
+      {
+        "level": 2,
+        "title": "E",
+        "page": 858
+      },
+      {
+        "level": 2,
+        "title": "F",
+        "page": 858
+      },
+      {
+        "level": 2,
+        "title": "G",
+        "page": 859
+      },
+      {
+        "level": 2,
+        "title": "H",
+        "page": 859
+      },
+      {
+        "level": 2,
+        "title": "I",
+        "page": 859
+      },
+      {
+        "level": 2,
+        "title": "J",
+        "page": 859
+      },
+      {
+        "level": 2,
+        "title": "K",
+        "page": 859
+      },
+      {
+        "level": 2,
+        "title": "L",
+        "page": 859
+      },
+      {
+        "level": 2,
+        "title": "M",
+        "page": 860
+      },
+      {
+        "level": 2,
+        "title": "N",
+        "page": 860
+      },
+      {
+        "level": 2,
+        "title": "O",
+        "page": 861
+      },
+      {
+        "level": 2,
+        "title": "P",
+        "page": 861
+      },
+      {
+        "level": 2,
+        "title": "Q",
+        "page": 861
+      },
+      {
+        "level": 2,
+        "title": "R",
+        "page": 861
+      },
+      {
+        "level": 2,
+        "title": "S",
+        "page": 862
+      },
+      {
+        "level": 2,
+        "title": "T",
+        "page": 863
+      },
+      {
+        "level": 2,
+        "title": "U",
+        "page": 863
+      },
+      {
+        "level": 2,
+        "title": "W",
+        "page": 864
+      },
+      {
+        "level": 2,
+        "title": "X",
+        "page": 864
+      },
+      {
+        "level": 3,
+        "title": "Uploaded by [StormRG]",
+        "page": 864
+      }
+    ]
   }
 ]

data/cloud_index/manifest.json

@@ -1,11 +1,11 @@
 {
   "version": 3,
-  "updatedAt": 1793788239,
+  "updatedAt": 1793788412,
   "model": "Snowflake/snowflake-arctic-embed-m-v1.5",
   "reranker": "Xenova/ms-marco-MiniLM-L-6-v2",
   "dim": 256,
-  "totalBooks": 30,
-  "totalPassages": 29702,
+  "totalBooks": 31,
+  "totalPassages": 31302,
   "books": {
     "building_winning_algorithmic_trading_systems_kevin_j_davey": {
       "passages": 545,
@@ -157,6 +157,11 @@
       "passages": 2212,
       "ocrEngine": "hybrid-winocr",
       "linearized": true
+    },
+    "fundamentals_of_digital_logic_with_verilog_design_third_edition": {
+      "passages": 1600,
+      "ocrEngine": "hybrid-winocr",
+      "linearized": true
     }
   }
 }

data/cloud_index/passages.json.gz

@@ -1,3 +1,3 @@
 version https://git-lfs.github.com/spec/v1
-oid sha256:fd630df84aabf10119d560cf9b252ecbd1d1edee69674d36d32ca8b8e7cd14e6
-size 9722881
+oid sha256:abe81af369c770c71eb18c3fd6b185af76341f1b3d5e37173f1a345359d60641
+size 10167935

data/cloud_index/vectors.bin

@@ -1,3 +1,3 @@
 version https://git-lfs.github.com/spec/v1
-oid sha256:a04234385c8b36322fee4803c2536385e61943871c3be9b90709bbeed7e4f854
-size 7603774
+oid sha256:a1f27f998ad9c162c8cf8b2fc62fb6407963f5edbb3c3f84443d54f4f40b9cde
+size 8013374

data/layouts/fundamentals_of_digital_logic_with_verilog_design_third_edition.json

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:5831dd2eddc51f4351bfa6717c8145eafed577040b34d5108a2c53910093c7f6
+size 15707960

data/pdfs/fundamentals_of_digital_logic_with_verilog_design_third_edition.pdf

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:947945b090ba2d7ed2ead9e7d2651350fda43012e5ee1db01483830f1e07ada5
+size 6280229