| Design the sizing and biasing voltage of an Op-Amp in SKY130nm (VDD 1.8 V) as shown in the provided circuit image.
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| Here is the netlist of the circuit
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| .subckt OPAMP2_Pin_3 gnda vdda vinn vinp vout
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| xm8 net36 vb2 vdda vdda sky130_fd_pr__pfet_01v8 l='P1_L' w='P1_W*1' m='P1_M'
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| xm7 net30 vb1 vdda vdda sky130_fd_pr__pfet_01v8 l='P2_L' w='P2_W*1' m='P2_M'
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| xm5 vout vb4 vdda vdda sky130_fd_pr__pfet_01v8 l='P3_L' w='P3_W*1' m='P3_M'
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| xm6 net33 vb3 gnda gnda sky130_fd_pr__nfet_01v8 l='N1_L' w='N1_W*1' m='N1_M'
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| xm1 net36 vinn net33 gnda sky130_fd_pr__nfet_01v8 l='N2_L' w='N2_W*1' m='N2_M'
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| xm0 net30 vinp net33 gnda sky130_fd_pr__nfet_01v8 l='N3_L' w='N3_W*1' m='N3_M'
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| xm4 vout net36 gnda gnda sky130_fd_pr__nfet_01v8 l='N4_L' w='N4_W*1' m='N4_M'
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| xm3 net36 net30 gnda gnda sky130_fd_pr__nfet_01v8 l='N5_L' w='N5_W*1' m='N5_M'
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| xm2 net30 net30 gnda gnda sky130_fd_pr__nfet_01v8 l='N6_L' w='N6_W*1' m='N6_M'
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| C0 vout net36 'CAPACITOR_0'
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| V1 vb1 0 'VB1'
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| V2 vb2 0 'VB2'
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| V3 vb3 0 'VB3'
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| V4 vb4 0 'VB4'
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| .ends OPAMP2_Pin_3
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| Here are the design parameters and range.
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| parameter_bounds:
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| L_P1:
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| min: 0.13
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| max: 1.0
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| type: real
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| W_P1:
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| min: 0.2
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| max: 10.0
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| type: real
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| M_P1:
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| min: 1
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| max: 100
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| type: int
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| L_P2:
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| min: 0.13
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| max: 1.0
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| type: real
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| W_P2:
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| min: 0.2
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| max: 10.0
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| type: real
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| M_P2:
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| min: 1
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| max: 100
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| type: int
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| L_P3:
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| min: 0.13
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| max: 1.0
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| type: real
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| W_P3:
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| min: 0.2
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| max: 10.0
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| type: real
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| M_P3:
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| min: 1
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| max: 100
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| type: int
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| L_N1:
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| min: 0.13
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| max: 1.0
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| type: real
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| W_N1:
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| min: 0.2
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| max: 10.0
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| type: real
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| M_N1:
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| min: 1
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| max: 100
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| type: int
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| L_N2:
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| min: 0.13
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| max: 1.0
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| type: real
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| W_N2:
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| min: 0.2
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| max: 10.0
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| type: real
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| M_N2:
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| min: 1
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| max: 100
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| type: int
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| L_N3:
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| min: 0.13
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| max: 1.0
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| type: real
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| W_N3:
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| min: 0.2
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| max: 10.0
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| type: real
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| M_N3:
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| min: 1
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| max: 100
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| type: int
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| L_N4:
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| min: 0.13
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| max: 1.0
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| type: real
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| W_N4:
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| min: 0.2
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| max: 10.0
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| type: real
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| M_N4:
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| min: 1
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| max: 100
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| type: int
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| L_N5:
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| min: 0.13
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| max: 1.0
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| type: real
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| W_N5:
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| min: 0.2
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| max: 10.0
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| type: real
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| M_N5:
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| min: 1
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| max: 100
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| type: int
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| L_N6:
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| min: 0.13
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| max: 1.0
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| type: real
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| W_N6:
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| min: 0.2
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| max: 10.0
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| type: real
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| M_N6:
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| min: 1
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| max: 100
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| type: int
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| C0:
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| min: 1.0
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| max: 100.0
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| type: real
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| V1:
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| min: 0.0
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| max: 1.8
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| type: real
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| V2:
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| min: 0.0
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| max: 1.8
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| type: real
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| V3:
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| min: 0.0
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| max: 1.8
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| type: real
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| V4:
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| min: 0.0
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| max: 1.8
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| type: real
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| Here is the design target
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| PSRP_target = -70 # dB (from VDD @1 kHz)
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| PSRN_target = -85 # dB (from VSS @1 kHz)
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| TC_target = 2e-5 # 20 ppm/°C (gain/offset drift)
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| Power_target = 3e-4 # W ≈0.3 mW
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| vos_target = 5e-4 # V ≈0.5 mV (good layout)
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| cmrrdc_target = -75 # dB
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| dcgain_target = 85 # dB
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| GBW_target = 4e6 # Hz (with CL≈10 pF)
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| phase_margin_target = 60 # deg
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| sr_target = 2e6 # V/s ≈2 V/µs (class-A-ish output)
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| settlingTime_target = 1.5e-6 # s to ~0.1–0.5% on 10 pF
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| Provide your design parameter in this format
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| parameters:
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| L_P1:
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| W_P1:
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| M_P1:
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| L_P2:
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| W_P2:
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| M_P2:
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| L_P3:
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| W_P3:
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| M_P3:
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| L_N1:
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| W_N1:
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| M_N1:
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| L_N2:
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| W_N2:
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| M_N2:
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| L_N3:
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| W_N3:
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| M_N3:
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| L_N4:
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| W_N4:
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| M_N4:
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| L_N5:
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| W_N5:
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| M_N5:
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| L_N6:
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| W_N6:
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| M_N6:
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| C0:
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| V1:
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| V2:
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| V3:
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| V4: |
