| /* d10v.h -- Header file for D10V opcode table | |
| Copyright (C) 1996-2025 Free Software Foundation, Inc. | |
| Written by Martin Hunt (hunt@cygnus.com), Cygnus Support | |
| This file is part of GDB, GAS, and the GNU binutils. | |
| GDB, GAS, and the GNU binutils are free software; you can redistribute | |
| them and/or modify them under the terms of the GNU General Public | |
| License as published by the Free Software Foundation; either version 3, | |
| or (at your option) any later version. | |
| GDB, GAS, and the GNU binutils are distributed in the hope that they | |
| will be useful, but WITHOUT ANY WARRANTY; without even the implied | |
| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See | |
| the GNU General Public License for more details. | |
| You should have received a copy of the GNU General Public License | |
| along with this file; see the file COPYING3. If not, write to the Free | |
| Software Foundation, 51 Franklin Street - Fifth Floor, Boston, | |
| MA 02110-1301, USA. */ | |
| extern "C" { | |
| /* Format Specifier */ | |
| /* The opcode table is an array of struct d10v_opcode. */ | |
| struct d10v_opcode | |
| { | |
| /* The opcode name. */ | |
| const char *name; | |
| /* the opcode format */ | |
| int format; | |
| /* These numbers were picked so we can do if( i & SHORT_OPCODE) */ | |
| /* just a placeholder for variable-length instructions */ | |
| /* for example, "bra" will be a fake for "bra.s" and bra.l" */ | |
| /* which will immediately follow in the opcode table. */ | |
| /* the number of cycles */ | |
| int cycles; | |
| /* the execution unit(s) used */ | |
| int unit; | |
| /* execution type; parallel or sequential */ | |
| /* this field is used to decide if two instructions */ | |
| /* can be executed in parallel */ | |
| int exec_type; | |
| /* the opcode */ | |
| long opcode; | |
| /* mask. if( (i & mask) == opcode ) then match */ | |
| long mask; | |
| /* An array of operand codes. Each code is an index into the | |
| operand table. They appear in the order which the operands must | |
| appear in assembly code, and are terminated by a zero. */ | |
| unsigned char operands[6]; | |
| }; | |
| /* The table itself is sorted by major opcode number, and is otherwise | |
| in the order in which the disassembler should consider | |
| instructions. */ | |
| extern const struct d10v_opcode d10v_opcodes[]; | |
| extern const int d10v_num_opcodes; | |
| /* The operands table is an array of struct d10v_operand. */ | |
| struct d10v_operand | |
| { | |
| /* The number of bits in the operand. */ | |
| int bits; | |
| /* How far the operand is left shifted in the instruction. */ | |
| int shift; | |
| /* One bit syntax flags. */ | |
| int flags; | |
| }; | |
| /* Elements in the table are retrieved by indexing with values from | |
| the operands field of the d10v_opcodes table. */ | |
| extern const struct d10v_operand d10v_operands[]; | |
| /* Values defined for the flags field of a struct d10v_operand. */ | |
| /* the operand must be an even number */ | |
| /* the operand must be an odd number */ | |
| /* this is the destination register; it will be modified */ | |
| /* this is used by the optimizer */ | |
| /* number or symbol */ | |
| /* address or label */ | |
| /* register */ | |
| /* postincrement + */ | |
| /* postdecrement - */ | |
| /* @ */ | |
| /* @( */ | |
| /* accumulator 0 */ | |
| /* accumulator 1 */ | |
| /* f0 / f1 flag register */ | |
| /* c flag register */ | |
| /* control register */ | |
| /* predecrement mode '@-sp' */ | |
| /* signed number */ | |
| /* special accumulator shifts need a 4-bit number */ | |
| /* 1 <= x <= 16 */ | |
| /* general purpose register */ | |
| /* special imm3 values with range restricted to -2 <= imm3 <= 3 */ | |
| /* needed for rac/rachi */ | |
| /* Pre-decrement is only supported for SP. */ | |
| /* Post-decrement is not supported for SP. Like OPERAND_EVEN, and | |
| unlike OPERAND_SP, this flag doesn't prevent the instruction from | |
| matching, it only fails validation later on. */ | |
| /* Structure to hold information about predefined registers. */ | |
| struct pd_reg | |
| { | |
| char *name; /* name to recognize */ | |
| char *pname; /* name to print for this register */ | |
| int value; | |
| }; | |
| extern const struct pd_reg d10v_predefined_registers[]; | |
| int d10v_reg_name_cnt (void); | |
| /* an expressionS only has one register type, so we fake it */ | |
| /* by setting high bits to indicate type */ | |
| } | |