| /* ppc.h -- Header file for PowerPC opcode table | |
| Copyright (C) 1994-2025 Free Software Foundation, Inc. | |
| Written by Ian Lance Taylor, Cygnus Support | |
| This file is part of GDB, GAS, and the GNU binutils. | |
| GDB, GAS, and the GNU binutils are free software; you can redistribute | |
| them and/or modify them under the terms of the GNU General Public | |
| License as published by the Free Software Foundation; either version 3, | |
| or (at your option) any later version. | |
| GDB, GAS, and the GNU binutils are distributed in the hope that they | |
| will be useful, but WITHOUT ANY WARRANTY; without even the implied | |
| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See | |
| the GNU General Public License for more details. | |
| You should have received a copy of the GNU General Public License | |
| along with this file; see the file COPYING3. If not, write to the Free | |
| Software Foundation, 51 Franklin Street - Fifth Floor, Boston, | |
| MA 02110-1301, USA. */ | |
| extern "C" { | |
| typedef uint64_t ppc_cpu_t; | |
| typedef uint16_t ppc_opindex_t; | |
| /* Smaller of ppc_opindex_t and fx_pcrel_adjust maximum. Note that | |
| values extracted from fx_pcrel_adjust are masked with this constant, | |
| effectively making the field unsigned. */ | |
| /* The opcode table is an array of struct powerpc_opcode. */ | |
| struct powerpc_opcode | |
| { | |
| /* The opcode name. */ | |
| const char *name; | |
| /* The opcode itself. Those bits which will be filled in with | |
| operands are zeroes. */ | |
| uint64_t opcode; | |
| /* The opcode mask. This is used by the disassembler. This is a | |
| mask containing ones indicating those bits which must match the | |
| opcode field, and zeroes indicating those bits which need not | |
| match (and are presumably filled in by operands). */ | |
| uint64_t mask; | |
| /* One bit flags for the opcode. These are used to indicate which | |
| specific processors support the instructions. The defined values | |
| are listed below. */ | |
| ppc_cpu_t flags; | |
| /* One bit flags for the opcode. These are used to indicate which | |
| specific processors no longer support the instructions. The defined | |
| values are listed below. */ | |
| ppc_cpu_t deprecated; | |
| /* An array of operand codes. Each code is an index into the | |
| operand table. They appear in the order which the operands must | |
| appear in assembly code, and are terminated by a zero. */ | |
| ppc_opindex_t operands[8]; | |
| }; | |
| /* The table itself is sorted by major opcode number, and is otherwise | |
| in the order in which the disassembler should consider | |
| instructions. */ | |
| extern const struct powerpc_opcode powerpc_opcodes[]; | |
| extern const unsigned int powerpc_num_opcodes; | |
| extern const struct powerpc_opcode prefix_opcodes[]; | |
| extern const unsigned int prefix_num_opcodes; | |
| extern const struct powerpc_opcode vle_opcodes[]; | |
| extern const unsigned int vle_num_opcodes; | |
| extern const struct powerpc_opcode lsp_opcodes[]; | |
| extern const unsigned int lsp_num_opcodes; | |
| extern const struct powerpc_opcode spe2_opcodes[]; | |
| extern const unsigned int spe2_num_opcodes; | |
| /* Values defined for the flags field of a struct powerpc_opcode. */ | |
| /* Opcode is defined for the PowerPC architecture. */ | |
| /* Opcode is defined for the POWER (RS/6000) architecture. */ | |
| /* Opcode is defined for the POWER2 (Rios 2) architecture. */ | |
| /* Opcode is only defined on 64 bit architectures. */ | |
| /* Opcode is supported by the Motorola PowerPC 601 processor. The 601 | |
| is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions, | |
| but it also supports many additional POWER instructions. */ | |
| /* Opcode is supported in both the Power and PowerPC architectures | |
| (ie, compiler's -mcpu=common or assembler's -mcom). More than just | |
| the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER | |
| and PPC_OPCODE_POWER2 because many instructions changed mnemonics | |
| between POWER and POWERPC. */ | |
| /* Opcode is supported for any Power or PowerPC platform (this is | |
| for the assembler's -many option, and it eliminates duplicates). */ | |
| /* Opcode is supported as part of the 64-bit bridge. */ | |
| /* Opcode is supported by Altivec Vector Unit */ | |
| /* Opcode is supported by PowerPC 403 processor. */ | |
| /* Opcode is supported by PowerPC BookE processor. */ | |
| /* Opcode is only supported by Power4 architecture. */ | |
| /* Opcode is only supported by e500x2 Core. | |
| This bit, PPC_OPCODE_EFS, PPC_OPCODE_VLE, and all those with APU in | |
| their comment mark opcodes so that when those instructions are used | |
| an APUinfo entry can be generated. */ | |
| /* Opcode is supported by Integer select APU. */ | |
| /* Opcode is an e500 SPE floating point instruction. */ | |
| /* Opcode is supported by branch locking APU. */ | |
| /* Opcode is supported by performance monitor APU. */ | |
| /* Opcode is supported by cache locking APU. */ | |
| /* Opcode is supported by machine check APU. */ | |
| /* Opcode is supported by PowerPC 440 processor. */ | |
| /* Opcode is only supported by Power5 architecture. */ | |
| /* Opcode is supported by PowerPC e300 family. */ | |
| /* Opcode is only supported by Power6 architecture. */ | |
| /* Opcode is only supported by PowerPC Cell family. */ | |
| /* Opcode is supported by CPUs with paired singles support. */ | |
| /* Opcode is supported by Power E500MC */ | |
| /* Opcode is supported by PowerPC 405 processor. */ | |
| /* Opcode is supported by Vector-Scalar (VSX) Unit */ | |
| /* Opcode is only supported by Power7 architecture. */ | |
| /* Opcode is supported by A2. */ | |
| /* Opcode is supported by PowerPC 476 processor. */ | |
| /* Opcode is supported by AppliedMicro Titan core */ | |
| /* Opcode which is supported by the e500 family */ | |
| /* Opcode is supported by Power E6500 */ | |
| /* Opcode is supported by Thread management APU */ | |
| /* Opcode which is supported by the VLE extension. */ | |
| /* Opcode is only supported by Power8 architecture. */ | |
| /* Opcode is supported by ppc750cl/Gekko/Broadway. */ | |
| /* Opcode is supported by ppc7450. */ | |
| /* Opcode is supported by ppc821/850/860. */ | |
| /* Opcode is only supported by Power9 architecture. */ | |
| /* Opcode is supported by e200z4. */ | |
| /* Disassemble to instructions matching later in the opcode table | |
| with fewer "mask" bits set rather than the earlist match. Fewer | |
| "mask" bits set imply a more general form of the opcode, in fact | |
| the underlying machine instruction. */ | |
| /* Opcode is supported by PowerPC LSP */ | |
| /* Opcode is only supported by Freescale SPE2 APU. */ | |
| /* Opcode is supported by EFS2. */ | |
| /* Opcode is only supported by power10 architecture. */ | |
| /* Opcode is only supported by SVP64 extensions (LibreSOC architecture). */ | |
| /* Opcode is only supported by 'future' architecture. */ | |
| /* A macro to extract the major opcode from an instruction. */ | |
| /* A macro to determine if the instruction is a 2-byte VLE insn. */ | |
| /* A macro to extract the major opcode from a VLE instruction. */ | |
| /* A macro to convert a VLE opcode to a VLE opcode segment. */ | |
| /* Map LSP insn to lookup segment for disassembly. */ | |
| /* A macro to extract the extended opcode from a SPE2 instruction. */ | |
| /* A macro to convert a SPE2 extended opcode to a SPE2 xopcode segment. */ | |
| /* A macro to extract the prefix word from an 8-byte PREFIX instruction. */ | |
| /* A macro to extract the suffix word from an 8-byte PREFIX instruction. */ | |
| /* A macro to determine whether insn I is an 8-byte prefix instruction. */ | |
| /* A macro used to hash 8-byte PREFIX instructions. */ | |
| /* The operands table is an array of struct powerpc_operand. */ | |
| struct powerpc_operand | |
| { | |
| /* A bitmask of bits in the operand. */ | |
| uint64_t bitm; | |
| /* The shift operation to be applied to the operand. No shift | |
| is made if this is zero. For positive values, the operand | |
| is shifted left by SHIFT. For negative values, the operand | |
| is shifted right by -SHIFT. Use PPC_OPSHIFT_INV to indicate | |
| that BITM and SHIFT cannot be used to determine where the | |
| operand goes in the insn. */ | |
| int shift; | |
| /* Insertion function. This is used by the assembler. To insert an | |
| operand value into an instruction, check this field. | |
| If it is NULL, execute | |
| if (o->shift >= 0) | |
| i |= (op & o->bitm) << o->shift; | |
| else | |
| i |= (op & o->bitm) >> -o->shift; | |
| (i is the instruction which we are filling in, o is a pointer to | |
| this structure, and op is the operand value). | |
| If this field is not NULL, then simply call it with the | |
| instruction and the operand value. It will return the new value | |
| of the instruction. If the operand value is illegal, *ERRMSG | |
| will be set to a warning string (the operand will be inserted in | |
| any case). If the operand value is legal, *ERRMSG will be | |
| unchanged (most operands can accept any value). */ | |
| uint64_t (*insert) | |
| (uint64_t instruction, int64_t op, ppc_cpu_t dialect, const char **errmsg); | |
| /* Extraction function. This is used by the disassembler. To | |
| extract this operand type from an instruction, check this field. | |
| If it is NULL, compute | |
| if (o->shift >= 0) | |
| op = (i >> o->shift) & o->bitm; | |
| else | |
| op = (i << -o->shift) & o->bitm; | |
| if ((o->flags & PPC_OPERAND_SIGNED) != 0) | |
| sign_extend (op); | |
| (i is the instruction, o is a pointer to this structure, and op | |
| is the result). | |
| If this field is not NULL, then simply call it with the | |
| instruction value. It will return the value of the operand. | |
| *INVALID will be set to one by the extraction function if this | |
| operand type can not be extracted from this operand (i.e., the | |
| instruction does not match). If the operand is valid, *INVALID | |
| will not be changed. *INVALID will always be non-negative when | |
| used to extract a field from an instruction. | |
| The extraction function is also called by both the assembler and | |
| disassembler if an operand is optional, in which case the | |
| function should return the default value of the operand. | |
| *INVALID is negative in this case, and is the negative count of | |
| omitted optional operands up to and including this operand. */ | |
| int64_t (*extract) (uint64_t instruction, ppc_cpu_t dialect, int *invalid); | |
| /* One bit syntax flags. */ | |
| unsigned long flags; | |
| }; | |
| /* Elements in the table are retrieved by indexing with values from | |
| the operands field of the powerpc_opcodes table. */ | |
| extern const struct powerpc_operand powerpc_operands[]; | |
| extern const unsigned int num_powerpc_operands; | |
| /* Use with the shift field of a struct powerpc_operand to indicate | |
| that BITM and SHIFT cannot be used to determine where the operand | |
| goes in the insn. */ | |
| /* A special case, 6-bit SH field. */ | |
| /* Values defined for the flags field of a struct powerpc_operand. | |
| Keep the register bits low: They need to fit in an unsigned short. */ | |
| /* This operand names a register. The disassembler uses this to print | |
| register names with a leading 'r'. */ | |
| /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */ | |
| /* This operand names a floating point register. The disassembler | |
| prints these with a leading 'f'. */ | |
| /* This operand names a vector unit register. The disassembler | |
| prints these with a leading 'v'. */ | |
| /* This operand names a vector-scalar unit register. The disassembler | |
| prints these with a leading 'vs'. */ | |
| /* This operand names a VSX accumulator. */ | |
| /* This operand names a dense math register. */ | |
| /* This operand may use the symbolic names for the CR fields (even | |
| without -mregnames), which are | |
| lt 0 gt 1 eq 2 so 3 un 3 | |
| cr0 0 cr1 1 cr2 2 cr3 3 | |
| cr4 4 cr5 5 cr6 6 cr7 7 | |
| These may be combined arithmetically, as in cr2*4+gt. These are | |
| only supported on the PowerPC, not the POWER. */ | |
| /* This is a CR FIELD that does not use symbolic names (unless | |
| -mregnames is in effect). If both PPC_OPERAND_CR_BIT and | |
| PPC_OPERAND_CR_REG are set then treat the field as per | |
| PPC_OPERAND_CR_BIT for assembly, but as if neither of these | |
| bits are set for disassembly. */ | |
| /* This operand names a special purpose register. */ | |
| /* This operand names a paired-single graphics quantization register. */ | |
| /* This operand is a relative branch displacement. The disassembler | |
| prints these symbolically if possible. */ | |
| /* This operand is an absolute branch address. The disassembler | |
| prints these symbolically if possible. */ | |
| /* This operand takes signed values. */ | |
| /* This operand takes signed values, but also accepts a full positive | |
| range of values when running in 32 bit mode. That is, if bits is | |
| 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode, | |
| this flag is ignored. */ | |
| /* The next operand should be wrapped in parentheses rather than | |
| separated from this one by a comma. This is used for the load and | |
| store instructions which want their operands to look like | |
| reg,displacement(reg) | |
| */ | |
| /* This operand is for the DS field in a DS form instruction. */ | |
| /* This operand is for the DQ field in a DQ form instruction. */ | |
| /* This operand should be regarded as a negative number for the | |
| purposes of overflow checking (i.e., the normal most negative | |
| number is disallowed and one more than the normal most positive | |
| number is allowed). This flag will only be set for a signed | |
| operand. */ | |
| /* Valid range of operand is 0..n rather than 0..n-1. */ | |
| /* This operand is optional, and is zero if omitted. This is used for | |
| example, in the optional BF field in the comparison instructions. The | |
| assembler must count the number of operands remaining on the line, | |
| and the number of operands remaining for the opcode, and decide | |
| whether this operand is present or not. The disassembler should | |
| print this operand out only if it is not zero. */ | |
| /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand | |
| is omitted, then for the next operand use this operand value plus | |
| 1, ignoring the next operand field for the opcode. This wretched | |
| hack is needed because the Power rotate instructions can take | |
| either 4 or 5 operands. The disassembler should print this operand | |
| out regardless of the PPC_OPERAND_OPTIONAL field. */ | |
| /* This flag is only used with PPC_OPERAND_OPTIONAL. The operand is | |
| only optional when generating 32-bit code. */ | |
| /* Xilinx APU and FSL related operands */ | |
| /* Valid range of operand is 1..n rather than 0..n-1. | |
| Before encoding, the operand value is decremented. | |
| After decoding, the operand value is incremented. */ | |
| extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *); | |
| static inline int64_t | |
| ppc_optional_operand_value (const struct powerpc_operand *operand, | |
| uint64_t insn, | |
| ppc_cpu_t dialect, | |
| int num_optional) | |
| { | |
| if (operand->extract) | |
| return (*operand->extract) (insn, dialect, &num_optional); | |
| return 0; | |
| } | |
| /* PowerPC VLE insns. */ | |
| /* Form I16L, uses 16A relocs. */ | |
| /* Form I16A, uses 16D relocs. */ | |
| } | |