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## 1.3.4 Manufacturing Equipment/Process
In the super-clean room, barring any mishaps with the filter, air cleanliness measurements taken directly beneath the ULPA filter with the currently used light-scattering particle counters indicate a count of zero or near zero. Furthermore, although the probability of particles... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
| Table 1.1. Major sources of particles in semiconductor manufacturing equipment Wafer process - The process reactions themselves (reaction by-products from plasma etching, CVD, etc.) Chamber interior - Redispersion of accumulated materials in the process chamber (flaking of by-products built up on chamber walls)... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
|-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Therefore, for the purpose of improving yield, consistently reducing and preventing particle generation in each of the wafer-processing steps is most important. To this end wafer surface particle inspection and analysis tools are effective [8] (see Parts IV and V). Although devices called *in situ* particle monitors ha... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Also, increases in the frequency of cleaning have been an attempt to nip in the bud the occurrence of failed wafers on a large scale (see Part VI).
In particular, with CVD (chemical vapor deposition) equipment, dry etchers, sputters, etc., there are many particles caused by the redeposition of material accumulated on... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Wafer transport has hitherto been carried out largely by belts and associated mechanical transport means, but there is significant particle adhesion on the back-side of the wafer from these mechanical parts. The wafer chucking mechanism has the same problems (see Fig. 1.7).
In the n... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
## 1.4 Controlling Metallic Contaminants
Contaminants, the main problem of semiconductor manufacturing, take not only the form of insoluble particles, but also atomic (ionic) contaminants represented by alkali metals (Na, K, etc.) and heavy metal ions (Fe, Ni, Cu, and the like). The presence of these contaminants can ... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
In order to prevent contamination from metallic impurities effectively, it is necessary to have a simple and highly sensitive analysis and evaluation technology. At present, an analytical method is being developed which can detect metallic substances on the Si surface down to 1010_109 atoms/cm2 order, but the developme... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
## 1.5 Controlling Airborne Impurities
In addition to metallic impurities, leakage into the cleanroom of P and B
dopants resulting from problems with exhaust and maladjustments of airflow conditioning are a serious cause of wafer contamination. Further, HF
(hydrogen fluoride) vapor that leaks from the wafer-cleaning... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
From the point of view of how to prevent contamination from reaching the wafer surface, the extensive development of the localization of clean space (a structure which isolates personnel from wafers), and the limitation of wafer transport to the exclusively closed space of the super-clean area (in short, the clean tube... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
## 1.6 The Future Of Ultraclean Technology
As the semiconductor device progresses from quarter-micron to 0.18-0.10 *{tm* dimensions, and even to the era of sub-O.l *{tm* dimensions, surface preparation technology requirements will be further tightened according to the National Technology Roadmap [15]. In the future, r... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
We look forward to the realization of ultraclean wafer transport and process environments developed as a well-balanced total system. Semiconductor process engineers, cleanroom designers/constructors, equipment manufacturers, material vendors, and others in this field as well as people in academia should work more close... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
T. Ohmi: Extended Abstracts of 1SSMT '92, 3 (1992).
1300I and J300: Global Joint Guidance for 300 mm Semiconductor Factories
(1997).
The National Technology Roadmap for Semiconductors, 1997 Edition. Semiconductor Industry Association, San Jose, CA (1997).
[1]
[2] [3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
The first Si devices were mainly bipolar transistors, and were widely used as high-voltage, high-power, high-frequency transistors and integrated circuits. Even now, analog ICs are mainly bipolar transistors, and in the future they will probably continue to occupy a position of importance. The advantages of MOS transis... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Dishman *et al.* researched electrically active stacking faults in CMOS and ICs. It was seen that when decorated stacking faults exist at the junctions of the device, abnormal leakage currents increase; the researchers showed that copper precipitated there [4]. Strack *et al.* investigated the relationship between DRAM... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
However, the use of this technique demands very careful control of the process technology, as it has been demonstrated that if precipitates are made on the active region of the device, then the effect is reversed, and the leakage current increases [10-20]. Furthermore, this oxygen precipitation has a great influence on... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
As mentioned above, while the origins of CE piping have for the most part been identified, the advent of new processes and materials, and the application of new device structures, make the recurrence of similar problems likely.
For this reason it is necessary to design the device process with great care.
The follow... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
## 2.2.4 Refresh Failure Of The Dram
Though junction leakage current in the MOS device is a major problem, even more significant is the appearance ofrefresh failure ofthe DRAM. The causes
Fig. 2.3. Basic structure of stacked capacitor cell
of refresh failure can be roughly divide... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
## 2.3 Influence Of Crystal Quality On Oxide Film Perfection
The relationship between Si crystals and the thermal oxidation film is the most basic concept of the integrated circuit. At present, very strict demands are being placed on the reliability of gate oxide films in particular. Because of the relationship betwee... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
is that in wafer tests of devices with oxide film defects, in final tests, and in the various burn-in tests, rejecting everything faulty is extremely difficult. In thinking about reliability, the substrate defect density in Si demands improvements of two orders of magnitude or better.... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
## 2.4 Influence Of Silicon Crystal Quality On Device Processes
The relationships between crystals and devices discussed up to now are basically those in which the imperfections of crystals influence the device characteristics. Of additional importance are the flatness of the crystal surface, resistivity, and mechanic... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
J. Kaniewski, M. Kaniewski, and A. R. Peaker: Materials Science Forum 8386, 1463-1468 (1992).
G. H. Schwuttke, K. Brack, and E. W. Hearn: Microelectronics and Reliability 10, 467-470 (1971).
K. V. Ravi, C. J. Varker, and C. E. Yolk: J. Electrochem. Soc. 120(4),
2689-2696 (1979).
J. M. Dishman, S. E. Haszko, R. B... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Soc. 134(7), 1753-1755 (1987).
J. G. Park, Y.S. Kwak, C. S. Lim, K D. Kwack, and S. Hahn: ECS Spring Meeting Ext. Abs. **91-1,** 320-321 (1991).
H. Fujimori, Y. Ushiki, T. Ihnuma, Y. Kirino, and Y. Matsushita: Semiconductor Silicon 1998, Electrochem. Soc. PV98-1, 1033-1045 (1998).
H. Ucuiyama, T. Mchedlidze, K. M... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
T. Ando and S. Isomae: E.C.S. Spring Meeting Ext. Abs. No. 228, 328 (1991.5).
J. P. Gambino, M. D. Monkowski, J. F. Shepard, and C. C. Parks: J. Electrochem. Soc. 137(3), 976-979 (1990).
A. S. Yapsir, G. Fortno-Wiltshire, J. P. Gambino, R. H. Kastl, and C. C. Parks:
J. Vac. Sci. Technol. 8(3) Pt. 2, 2939-2949 (199... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
In an attempt to clarify the technology necessary for countermeasures, this chapter will explain the problems caused for device characteristics by contamination, reconsider the meaning of the required cleanliness level, and compare this level to the present level of process contamination.
## 3.2 Trends In Lsi Technol... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
The special characteristics of this submicron technology can be summarized as (1) finer circuit patterns, (2) thinner films, and (3) higher aspect ratios.
Fig. 3.1. Technological trends of DRAM
## 3.3 How Contaminants Degrade Device Performance
In the semiconductor process, the w... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
These connections are not independent phenomena, but rather, are interrelated in a complex way, and even hasten the development of each other. For example, particles themselves cause pattern degradation during the ultrafine process, but they can also be sources of metallic and organic contamination.
| Contaminant |... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Also, the structure of ultrafine devices with high aspect ratios causes a local concentration of stress within the wafer, which influences the distribution of metallic contaminants and other impurities; this seems to accelarate degradation, such as the reduction of the dielectric stre... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
## 3.3.1 Device Characteristic Degradation Due To Particulate Contaminants
Device characteristic degradation due to particles includes pattern defects, degradation of the insulating film's dielectric strength, and failures due to local masking durin... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Fig. 3.4. Correlations between yield and numbers of particles
ously, we must hope for rapid developments in the measurement technology of ultrafine particles.
Next, we consider the relationship between yield and the number of particles (defect density). Figure 3.4 shows the number ... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
film formation process steps, these films peel off and become particles due to the thermal cycle of films attached to places other than the wafer. The reason why particles are especially common in the dry etching step is that so many by-products are formed by the etching reaction - af... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
This is because the product wafer brings in particles from the previous step.
Though particle reduction is possible through an increase of the amount of circulated filtration chemical, optimized chemical flows, and control of the zeta potential in chemical solutions, it is necessary to develop a technique which preve... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
## 3.3.2 Device Characteristic Degradation Due To Metallic Contaminants
Table 3.2 shows the degradation of device characteristics due to a variety of metals [1-3]. It is a well-known phenomenon that when heavy metals such as Fe, Cu, and Au, among others, produce substitutional impurities in Si, energy states are forme... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Thanks to the systematic research of Takiyama *et al.* (see next chapter),
much is being made clear about the relationship between metallic contamination and the degradation of gate oxide dielectric strength. In particular, attention must be given to Ca, which is highly sensitive to causing dielectric strength degrada... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
There have been a variety of research presentations concerning the increase of junction leakage currents, as this is an obstacle to the achievement of lower power consumption LSIs. Basically, it has been explained by an increase in the uniform GR current due to the formation of the abovementioned deep energy states. Ho... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Figure 3.8 plots this leakage current against the length of the LOCOS
perimeter of the circuit pattern for the current measurement. As shown in the table within the figure, the area of each pattern differs by roughly two orders of magnitude. The leakage current shows absolutely no dependency on area; rather, its incre... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Figure 3.9 shows the investigation results of the levels of contamination in each of the present process steps. Methods which utilize charged molecules, such as ion implantation, dry etching, and plasma-enhanced CVD, show a result similar to that for particles (see Fig. 3.5): a very high metallic contamination level. T... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
| Contamination Level (atoms/ern'!) | | | | |
|-------------------------------------|-----------------------|--------------------------|------|------|
| Process | 1010 | 1011 | 1012 | 1013 |
| I ... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
| - | I 1 I | | | |
| P-CVD | ,« | I 1 | | |
| I | CJ 1 | | | |
| 1 ... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Necessary countermeasures include avoiding, as much as possible, the unnecessary irradiation of equipment parts by charged molecules, and using materials other than metal for parts which will possibly come into contact with charged molecules, such as quartz, Si, and highly pure ceramics (SiC,
graphite, etc.). If metal... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
The third type entails a small number of volatile organic compounds with comparatively small numbers of molecules, contamination caused by a substance such as alcohol. Though organics with a small molecular number (the number of carbon atoms is three or fewer) become volatile immediately after adherence, they themselve... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
A representative source of the first and second kinds of contamination is photoresist. Recently, oxygen plasma ashing has been widely adopted for resist removal, which rarely leaves even a thin residue after simple removal.
However, resist removal techniques employed after high-current ion implantation still need imp... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Other contaminants which deserve to be mentioned include native oxides and surface micro-roughness. Research on the relationships between these kinds of contamination and device characteristics is at present showing great advances. In the future, the control of native oxides and micro-roughness will become even more si... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
[8] K. Saga and T. Hattori: J. Electrochem. Soc. **144,** L253 (1997).
[9] T. Isagawa *et al.:* Ultra Clean Technology 6, 68 (1994).
# 4. Influence Of Metallic Contamination On Dielectric Degradation Of Mos Structures
Makoto Takiyama, Nippon Steel
## 4.1 Dielectric Degradation Mechanisms Of The Oxide Film Caused... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Fig. **4.1.** SEM micrograph of etch pits observed at the surface of an oxide film which is contaminated with Mg after immersing in a hot Hel solution
## 4.1.1 Formation Of Metal Oxides And Metal Silicates [1-4]
Mg, Zn, Ca, and Fe are able to form metal silicates in the metal-oxygensilicon system (Table 4.1). Figure... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
| Ele- | Vapor | Formation | Chemical | liHf" *** | Oxide | Formation of |
|------------------------------------------------------------------------------------|-----------|-------------|-------------|------------... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
| Na | 397 | possible | Na2 0 | -50 | 1092 | possible |
| Cr | 1255 | possible | Cr2 03 | -45 ... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
* Though the metal silicates could not be formed at atmospheric pressure, it could be possible under high-pressure condition.
** At the temperature at which a saturated vapor pressure of metals and metal oxides indicates 1 x 10- 6 Torr. At this temperature it is estimated that the contaminant evaporates 1 ng from the... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
diffusivity, are able to precipitate as metal silicide during the cooling process after thermal treatment. Figure 4.3 shows a cross-section TEM image of eu silicide precipitated at the Si- Si02 interface. The precipitate grows up toward the oxide film, and forces the oxide film to thi... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Figure 4.6 is an AFM image of an oxide defect. Its depth is about 45 nm, compared with the oxide film thickness of a normal area, 40 nm. The leakage current characteristics of the oxide film involving the oxide defect show close similarities to pinhole failures.
## 4.1.5 Enhancement... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
In actual LSI fabrication processes, there are many cases in which weak spots of the metal-contaminated oxide film are caused by an accumulation of a number of the above mentioned dielectric degradation mechanisms. Using Fe contamination as an example, the dependency of these five causes on LSI
manufacturing condition... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
## 4.2 Correlation Between Metallic Contamination Levels And Yield Of Oxide Breakdown Strength
4.2.1 Metallic Contamination Levels and In-Depth Profile, and Their Influence on Oxide Film Breakdown Strength
(Time Zero Dielectric Breakdown)
The relationship between metal contamination levels and the breakdown strength... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
levels below 1 x lOll atoms/cm2 contaminants other than Ca show little influence on breakdown strength yield. However, in the case of Sample 2 there is some dependency on the subsequent thermal treatment conditions, but the influence on breakdown strength yield appears at contaminatio... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
However, when electrons are injected from the surface of the oxide film, the barrier height is lowered conspicuously due to the contaminants concentrated
(a) Electron injection from the Si-Si02 interface
(oxide surface)
near the cathode, and the... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
For these reasons, it is difficult to define the relationships between breakdown strength yield and surface contamination levels. However, it is speculated from the above facts that if the surface contamination level is less than 1 x 109 atoms / cm 2 , the breakdown strength of the oxide film will not degrade.
## 4.2... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
## 4.2.3 Influence Of Other Metallic Contaminants On Dielectric Degradation
The following experimental data have been reported concerning the dielectric degradation phenomenon of oxide films due to metal contaminants other than the seven elements already mentioned above.
Although it has been reported that Na contami... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
| Tg , and Dit Element Acceleration or | Direction of | Tg | Dit | |
|-----------------------------------------|----------------|---------------------|-----------|-------------------|
| deceleration of | VFB shift | | ... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
| Mo | ? | ? | Decrease | ? |
| Na | Acceleration | Negative | ? | ? |
| Ni | Acceleration | Negative | Decreas... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
## 4.3.1 Influence On Thermal Oxidation
Most kinds of metal contaminants cause thermal oxidation to accelerate as the level of contamination increases. Since the acceleration of thermal oxidation by Na contamination has been explained by the model in which diffusion coefficients of oxidized species increase substantia... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
## 4.3.3 Influence On Generation Lifetime Of Minority Carriers (Tg)
Figure 4.11 shows the relationship between surface contamination level and normalized Tg on a contamination-controlled wafer.
Because AI, Ca, Cr, Mg, and Zn are easily incorporated into the oxide film, for the most... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
## 4.3.4 Influence On Interface State Density **(Dit)**
As long as Fe silicide does not precipitate in large amounts at the Si-Si02 interface, Fe contamination will not cause the interface state density to increase because interstitial Fe ions do not influence the interface state density.
It has been reported that, ... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
One issue concerning this equipment is the reduction of metal contamination which causes particles to adhere to the wafer backside. It is necessary to take steps to prevent the acquisition and retention of contaminants on the equipment. Semiconductor equipment manufacturers must take the same care in selecting the part... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
[7] K. Hiramoto, M. Sano, S. Sadamitsu, and N. Fujino: Jpn. J. Appl. Phys.
28(12), L2109-L2111 (1989).
[8] M. Liehr, H. Dallaporta, and J. E. Lewis: Appl. Phys. Lett. 53(7), 589-591
(1988).
[9] S. Verhaverbeke, M. Meuris, P. Mertens, M. Heyns, A. Philipossian, D. Graf, and A. Schnegg: Technical Digest of IEDM, 7... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
[19] H. Shimizu and C. Munakata: Jpn. J. Appl. Phys. 31(3), 729-731 (1992). [20] T. Itoga, H. Kojima, and A. Hiraiwa: Extended Abstracts of SSDM, 434-436, Tsukuba (1992).
[21] T. Ohmori, N. Yokoi, and K. Sato: Proceedings of 3rd International Symposium on Ultraclean Processing of Silicon Surface, session 1, Antwerp (... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
following, under certain conditions, the more concentrated the ammonia the greater the increases of micro-roughness. Increases in micro-roughness lead to degradation of the dielectric breakdown field, a phenomenon regardless of wafer type (CZ, FZ, or... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
reductions of channel mobility due to the Si-Si02 interface micro-roughness grow even more conspicuous.
Figure 5.4 shows the relationship of dopant concentration and channel mobility in n-MOSFET, with a comparison where micro-roughness is small
(R... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
## 5.2 Methods Of Measuring Micro-Roughness
The preceding paragraphs were concerned with the relationships between micro-roughness and MOS device characteristics. In general, micro-roughness is observed with scanning probe microscopes (SPM), such as a scanning tunnel microscope (STM) or an atomic force microscope (AFM... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
In the past, when performing surface micro-roughness assessment, the essential correction method of AFM height direction into micro-roughness numerical values was imperfect. What in fact is assessed is average roughness
(Ra) to a degree of 0.1 nm. In contrast to this, the step height of a currently marketed AFM correc... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
On an Si(111) surface cleaned in ultrahigh vacuum, there exists a monoatomic step of approximately 3 nm that can, it has been reported [8], be observed in open air with AFM. Use of this atomic step structure as an AFM
correction sample has been investigated [9]. By this method, which is based on the lattice constant o... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
## 5.3 Increases In Micro-Roughness Due To Wafer Cleaning
Si surface micro-roughness often increases during wet cleaning of wafers, which uses chemicals. Wet cleaning chemicals for Si wafer cleaning can be roughly divided into the following two groups:
1) chemicals which dissolve or decompose contaminants on the wafe... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
With APM in particular, when Si is oxidized by hydrogen peroxide at a temperature from 60 rv 90°C, then etching of the Si02 film by ammonia will proceed simultaneously. If ammonia touches the bare Si surface directly, then direct etching by alkali takes place, and the surface will become rough. Oxide film created by hy... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
After the APM cleaning process, in order to remove ammonia that is adhered to or permeated within the wafer or carrier a hot ultrapure water rinse is often performed. However, at this time if the concentration balance of ammonia and hydrogen peroxide brought into the hot ultrapure water bath is lost, then micro-roughne... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Examples of etching solutions whose main purpose is the removal of native oxide film and alkali/alkali earth metals are dilute hydrogen fluoride (DHF)
and buffered hydrogen fluoric acid solution (BHF). Etching by these solu-
Mixing ratio 1 : 1 : 5
tions stops at the already existin... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
It has also been reported that in the actual process, MOSFETs fabricated on the (100) substrate have higher reliability that those fabricated on the
(111) substrate [21, 22]. Therefore a (100) substrate planarization technology is necessary. There have been further reports about being able to planarize Si(100) CZ subs... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
[7J T. Ohmi and S. Aoyama: Appl. Phys. Lett. **61,** 2479 (1992). [8J M. Suzuki et *al.:* Appl. Phys. Lett. **58,** 2225 (1991).
[9J M. Suzuki et *al.:* J. Vac. Sci. Technol. AI4(3) (1996).
[lOJ W. Murray Bullis: The Electrochemical Society Proceedings **94-10,** 1156
(1994).
[l1J S. Aoyama and T. Ohmi: Material... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
[22J K. Nakamura, K. Ohmi, K. Yamamoto, K. Makihara, and T. Ohmi: Jpn. J.
Appl. Phys. 33(IB), 500-504 (1994).
[23J Y. Yanase, H. Horie, Y. Oka, M. Sano, S. Sumita, and T. Shigematsu: Electrochemical Society Ext. Abstr. No. 296, (1993).
[22J S. Verhaverbeke, T. Futatsuki, R. Messoussi, and T. Ohmi: The Electrochem... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
## 6.1 Dynamics Of Particles In The Gas Phase
Particles are subject to Brownian motion, settling by external forces such as gravity and electrical force, and the inertial motion of a fluid. Figure 6.2 shows various physical properties of the particle suspended in a gas phase.
It can be seen from the figure that the ... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
$$\left(2\right)$$
## 6.1.1 Brownian Motion
When the particle is small, it collides with gaseous molecules which are in thermal motion, causing it to move randomly. This is called Brownian motion.
The Brownian motion can be estimated by the diffusion coefficient D,
$$D={\frac{C_{c}k T}{3\pi\mu d_{p}}}\,,$$
$$\lef... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
## 6.1.2 Inertial Motion
When the velocity and direction of the fluid are altered, the particles cannot follow their alterations due to particle mass, and subsequently diverge from the streamline. This is called inertial motion, and can be evaluated by the relaxation time Tg ,
$$\left(4\right)$$
$$\tau_{\mathrm{g}}=... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
$$v_{e x t}=\tau_{\mathrm{g}}\,F_{e x t}/m_{p}\quad.$$
$$v_{t}=\frac{d_{p}^{2}\,\rho_{p}\,g\,C_{c}}{18\mu}\quad.$$
When gravity acts as the external force, by substituting F = *mpg* into the terminal settling velocity can be derived.
$$({\mathfrak{f}}{\mathfrak{o}})$$
Also, when the external force is a Coulombic fo... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
$$v_{t h}=-K_{r}\,\frac{\nu}{T}\nabla T\,,$$
$$({\mathfrak{g}})$$
where *"VT* is the temperature gradient, l/ the kinematic viscosity of the *gas,*
and Kr the thermophoretic coefficient. The next equation for Kr can be used for a wide range of particle sizes [3]:
$$K_{r}=2.294\frac{(\alpha+2.20K_{n})[1+Kn\{1.2+0.41... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
In order to compare the above movements, the distances that particles travel in 1 second were calculated; these values are shown in Fig. 6.3.
The results for Coulombic force and thermophoretic force were calculated at E = 10 V / cm and *"VT* = -1 K/ cm, respectively. For Brownian motion and inertial motion, the avera... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
$$m_{p}\frac{\mathrm{d}\mathbf{v}}{\mathrm{d}t}=\mathbf{F}_{\mathbf{ext}}+b\,m_{p}(\mathbf{u}-\mathbf{v})\,,\tag{13}$$
where b = l/Tg , U is the velocity of the fluid, v and mp are the velocity and mass of the particle, and F ext is the external force. Because this equation does not consider Brownian motion, it is use... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
$$j=-D\frac{\partial n}{\partial t}\left|\right.y=d_{p}/2\tag{15}$$ $\left.\right.$ from the $\left.\right.$ from $\left.\right.$ to $\left.\right.$ in all $\left.\right.$ the $\left.\right.$
where y is the axial distance from the wafer surface. j is called the deposition flux, and gives the number of particles deposi... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
$$F_{I}(z)=\frac{(\epsilon_{3}-1)}{(\epsilon_{3}+1)}\frac{p^{2}\,e^{2}}{4\pi\,\epsilon_{0}\,z^{2}}\quad,$$
where z is the distance between the particle and the wafer surface and EO is the dielectric constant of the gas. This force acts as an attraction.
The distance from the wafer where the image force becomes signi... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
## 6.3.3 Born Repulsion
When a particle closely approaches a wafer, Born repulsion occurs due to the overlap of the electron clouds of their molecules or atoms.
Because Born repulsion and the van der Waals force act simultanously between the particle and a deposition surface such as a wafer, the potential energy ¢ h... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
When the particle motion equation (13) and the diffusion equation (14) are solved, the boundary conditions on the wafer should be n = 0, at z = rp + *IS.*
However, when the particle diameter is larger than a few nm, it can be approximated as IS ~ 0. In this case, all particles which reach the wafer are caught on the s... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
## 6.4.1 Deposition In Stationary And Convective Fields
Consider wafers placed vertically in a wafer container. If particles uniformly fill the space between the two parallel wafers kept at distance h, and there is no temperature gradient and no convection in the space, the deposition velocity Vn can be derived from (... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
When a wafer of diameter L which is kept horizontal is placed in the horizontal flow, particle deposition is evaluated using the next equation, which considers flow, Brownian diffusion, and gravity [9):
$$v_{n}^{*}=0.739(D/L)(u_{0}\,L/\nu)\,S c^{1/3}+v_{t}\quad,$$
$$(23)$$
where v~ is the average value of deposition... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
When a wafer is placed horizontally on a holder larger than the wafer itself, and the center of the wafer coincides with the center of the vertical flow, the average deposition velocity can be found from the following equation [9):
$$v_{n}^{*}=0.7776R e_{p}^{1/2}S c^{1/3}(2D/d_{p})\quad,$$
$$(24)$$
$$|j(t)|=(D+D_{E})\,\mathrm{d}n/\mathrm{d}y-n\,u_{t}\cos\theta\quad,$$
$$(27)$$
Ij(t)1 = *(D+DE)dn/dy-nutcOSe* (27)
where y is the distance from the wafer surface and e is the angle between the normal to the wafer and the direction of gravity.
TUrbulent diffusion in the vicinity ... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
$$v(\theta)={\frac{u_{t}\cos\theta}{\exp\left\{{\frac{\pi u_{t}\cos\theta}{a\sin(\pi/a)(K_{e}D^{a-1})^{1/a}}}\right.}}}$$
$$(28)$$
The values of the constant a and of *K e* are approximately a = 2.7 and K e = 3.0 (2100/15 */.1)1* / 2, respectively [12]. EO is the energy dissipation rate
(energy dissipated by the tur... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
particle diameter dp [f.Jm] Fig. 6.7. Effects of particle charge on deposition velocity
of particle charge on deposition. In the calculation, it was assumed that the electrical field intensity E is 50 V / cm, and the polarity of the particle cha... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Electrostatic and thermophoretic forces prevent and accelerate particle deposition, so the existence and direction of these external forces must always be regarded with concern.
[1]
[2]
S. K. Friedlander: Smoke, Dust, and Haze, Wiley, New York, p. 24 (1977).
J. H. Seinfeld: Atmospheric Chemistry and Physics of Ai... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
J. G. Crump and J. H. Seinfeld: J. Aerosol Sci. Technol. 12, 405 (1981).
K. Okuyama, Y. Kousaka, S. Yamamoto, and T. Hosokawa: J. Colloid Interface Sci. 110, 214 (1986).
P. H. McMurry and D. J. Rader: J. Aerosol Sci. Technol. 4, 249 (1985).
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11] [12]
[13]
## 7. Particle... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
$$(1)$$
$$(2)$$
$\left(3\right)$.
$$\begin{array}{c}{{\rho_{\mathrm{P}}=\rho_{0}\,P/P_{0}}}\\ {{\lambda_{\mathrm{P}}=\lambda_{0}\,P_{0}/P}}\\ {{\nu_{\mathrm{P}}(=\mu/\rho_{\mathrm{P}})=\nu_{0}\,P_{0}/P}}\end{array},$$
where the subscript P means the pressure P and the subscript 0 indicates the value of normal pressur... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Figure 7.2 shows the distance moved in 1 second by such a particle due to gravitational settling, Coulombic force, Brownian motion, and thermophoresis (in the case of Brownian motion, this is the average absolute distance moved *(x)).* These values were obtained from the following e... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Equations (5-10), which show the Brownian diffusion coefficient D, gravitational settling velocity *Vt,* electrical mobility *Be,* thermophoretic velocity *Vth,* relaxation time Tg , and the average absolute distance moved due to Brownian motion *(x),* are the results when particle motion becomes stable at t » Tg . How... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Unidirectional diffusion:
$$v_{df}=-\frac{\sqrt{m_{1}}}{\Upsilon_{1}\sqrt{m_{1}}+\Upsilon_{2}\sqrt{m_{2}}}\frac{D_{12}}{\Upsilon_{2}}\nabla\Upsilon_{1}\quad.\tag{13}$$
## 7.1.2 Effect Of Temperature Gradient
Because the plasma discussed here is a low-temperature plasma, such as RF
and ECR, the temperature of the g... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
## 7.1.3 Effect Of Electric Field
In plasma, the differences in mobility of the generated electrons and ions cause an electric field. In this electric field, particles move at an electrophoretic velocity expressed by:
$$v_{e}=B_{e}\,E=\frac{C_{c}peE}{3\pi\mu d_{p}}\quad.\tag{14}$$
Figure 7.4 shows the electrophoret... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers |
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