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By following this sequence of particle analysis, identification, and reduction, and implementing countermeasures extending into the entire range of VL8I
manufacturing process steps, we are working towards improvements in device yield and reliability [7,8].
## 17.3.5 Examples Of Particle Analysis During Wafer Process... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
These photoresist particles for the most part are deposited inside the chamber when the resist patterns on the wafer surface are sputtered by ion beams, or are brought in from the prior lithography process step.
17.3.5.3 Reactive Ion Etching. According to EDX analysis, most of the particles generated by RIE equipment... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
The above are the analysis results of equipment with the most prolific particle generation; countermeasures for the reduction and prevention of particle generation based on these results are shown in Table 17.4.
By entering the examples of analysis, identification, and corrective actions into a database, it is possib... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
| for the reduction and prevention Process Source of particle generation Ion - Internal structure mateimplan- rials of ion beam line tat ion - Wafer disk wafer clamp ... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
|-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
| - Optimization of the internal structural materials of the beam line - Application of high-purity materials resistant to ion sputtering - Change to clampless mechanism - Prevention of excess resist adherence during lithography process - Slow vacuum/slow vent (common to all vacuum equipment) - Implementation ... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
| - Photo resist - Vacuum exhaust/vent - Wafer back side contamination ... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
| Dry ... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
| etching ... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
| PVD ... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
| CVD ... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
| Wet ... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
| clea- ... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
| ning ... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
| Table 17.4. continued Process Source of particle generation - Wafer boat, boat fork - Furnace tube material ... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
| - Optimization of materials and morphology, soft landing - Periodic cleaning and replacement of furnace tubes - Ultra clean treatment of the inner surfaces of piping - Optimization of precision filtering and exhaust flow in the photoresist coating cup - Optimization of reticle cleaning and application of pe... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
| Lithography ... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
By conducting detection, analysis, and identification of particles on wafers in each step of the **VLSI** manufacturing process, followed by investigation of the sources of particle generation, we are working to devise reduction and prevention countermeasures to efficiently improve yield and reliability of VLSI devices... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Improvement of the detection sensitivity of equipment used for spotting particles adhered to the wafer is an urgent task. However, in general, detection sensitivity and the speed of inspection have a reciprocal relationship, and the practical use of high-sensitivity methods is not easy. Other topics for the future incl... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Moreover, in the future, from the point of view of analyzing deep submicron particles on a large diameter wafer, currently available analysis equipment will be extremely inadequate. A breakthrough with brandnew methods is also necessary in this field of analysis of localized ultrasmall areas. It is also hoped that ther... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
[8] T. Hattori and S. Koyata: Applications of an Automated Particle Detection and Identification System in VLSI Wafer Processing, SPIE Proc. 1464,367 (1991).
[9] H. F. Stelgmeier and H. Auderset: Light Scattering Topography and Photoluminescence Topography, Applied Physics A 50, 531 (1990).
# 18. Pattern Defect Mon... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
On the other hand, tracing the same wafer in the same slot (the vertical arrow) can be called lot monitoring, in contrast to the in-line monitor. Lot monitoring is performed to analyze quantitatively the process where defects are generated, and is an engineering analysis method.
~... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
## 18.4 Wafer Inspection Systems Used For In-Line Defect Monitors And Their Advantages
The defects on product wafers are particles and pattern defects. The digital imaging technique is most effective for finding pattern defects as well as particles. The principle of the digital imaging technique is the comparison of t... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
A defect is detected when the difference in the gray levels exceeds a thresh-
old value. The **KLA** 2135 system can perform this digital analysis with a speed of 400 Mpixels per second. For example, with a sensitivity of 0.3 *J.lm* it takes abo... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
## 18.5 Goals And Benefits Of **In-Line** Defect Monitoring
The goals and benefits of inline monitoring are described in Fig. 18.6. Here, for simplicity, in-line monitoring is performed at three process steps. It is confirmed that process 1 is stable, and at the same time, excursions of process 2
| Mode 2 | Mode 3 | |
|------------------------|----------|------|
| Creation frequency (%) | | |
| between the lots | in lot | |
| Mode | 72.8 | 12.5 |
| 2 | 22.4 | 19.8 |
| 8.4 ... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Figure 18.10 shows an example of the bin/sort yield analysis. Here, the numbers of chips in process A without and with defects are called Po and *PI,*
respectively. The proportion of fatal errors in process A is defined as the kill rate:
## Ka = (Po - Pi)/Po
In the example of Fig. 18.10, the kill rates in process A... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
the excursion, the accumulated data are analyzed, and, if necessary, experiments with a "split lot" are performed. After having identified the cause, a countermeasure is taken and examined to see whether it works for reducing defectivity. By repeating this procedure, yield improveme... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
As a different example, in-line monitoring was performed at 21 process steps in a 64M pilot line. Among them, 50% used an etch process and 30% a photo process. During data analysis, cluster defects were classified into different modes. and the causes of the clusters were estimated from their defect distribution signatu... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
2) Currently available inspection systems can detect down to 0.2 p,m defects, but it is hard to understand what the defect is and where it is located in the device structure. Therefore, the turnaround time for defect management is not simply determined by inspection speed but sometimes by defect review time. Defect rev... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
| Control item Particles in air Impurities Alkaline | Impact on device performance Low yield, contamination Instability of MOS transistors Degradation of gate oxide integrity Degradation of gate oxide integrity Increase of reverse leakage current at PN junction Deterioration of gate oxide VT shift hFE de... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Table 19.2 shows the list of contamination monitoring techniques and the difficulty of implementation of these monitoring techniques in a production line [1]. For the detection of heavy metals and alkaline metals, chemical analysis such as atomic absorption spectroscopy (AAS) and inductive coupling plasma mass spectros... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
| Analysis technique | Detectable contamination/damage | Feasibility |
|--------------------------------------------|-------------------------------------------|---------------|
| Chemical analysis (AAS) | Heavy metals, alkali metals | difficult |... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
ity carrier lifetime (MCLT) by *JL-PCD* (microwave photoconductive decay)
and total reflection X-ray fluorescence (TRXRF), are suitable for monitoring the clean level. In this chapter, an evaluation technique using MOS capacitors and in-line analysis in the production line will be described.
## 19.2 Clean Level Eval... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
## 19.2.1 Detection Of Particles And Heavy Metals
Figure 19.1 shows the failure categories of dielectric breakdown in MOS capacitors [2]. The breakdowns are categorized as A-mode failure (breakdown at less than 2 MV /cm), B-mode failure (breakdown ranging 2 to 8 MV /cm),
and C-mode failure (breakdown at over 8 MV /cm... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Figures 19.2a-c show the dielectric breakdown histograms of MOS capacitors with 10 mm2 gate area with varying clean levels of wafer cleaning and gate oxidation (purity of deionized water, particle and impurity level of chemical). Although the thinner «10 nm) gate oxide film has high detection sensitivity for A-mode fai... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Figure 19.3 shows the dielectric breakdown yield vs. gate area as a parameter of defect density. Each defect density corresponds to a clean level:
$$(1)$$
A, Band C. For small gate area, less than 1 mm2 , the capacitor yield is greater than 90% for all clean levels, and it is ver... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
The ramping method and stepped current method are suitable for evaluating the clean level because the measurement time is relatively short.
Figure 19.4 shows the Weibull plot of stepped current TDDB measurement result of previous specimen. For level A, the intrinsic failures and defect-
 has also been used recently [11]. Using the TVS method, detection of 1 x 109 cm- 2 mobile ion density and ion species can be specified.
## 19.2.3 Charge Build-Up Evaluation Using Mos Cap... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
build-up monitoring using MOS capacitors is a powerful tool for improving plasma distribution and equipment design.
Figure 19.8 shows the relationship between charge build-up and the electron flood gun emission current that neutralizes the charge build-up due to the ion beam by using dielectric breakdown of MOS capac... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
As mentioned above, by evaluating the dielectric breakdown characteristics of MOS capacitors, contamination (particles, mobile ions, and heavy metals) in wafer cleaning, thermal processing, and ion implantation, and charge build-up in dry etchers, plasma ashers, plasma CVD, and ion implanters can be monitored effective... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
## 19.3.1 Heavy Metal Evaluation Using Minority Carrier Lifetime (Mclt)
The influence of heavy metals can be investigated by measuring the minority carrier lifetime using microwave photoconductive decay *(JL-PCD).* To avoid surface recombination, a 50"" 100 nm protective oxide film should be grown.
Figure 19.10 show... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
rier lifetime is very useful for detection of heavy metal contamination and the detection sensitivity is estimated at around 1 x 109 cm- 2 ; however, this depends on the heavy metal species.
## 19.3.2 Contamination Evaluation Using Trxrf
Although minority carrier lifetime measure... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
## 19.3.3 Cv Evaluation Using Non-Contact Cv Measurement Equipment
The electrical characteristics of MOS capacitors are very informative; however, the feedback is not very prompt. Thus, non-contact, non-destructive, in-line CV measurement has been requested for a long time.
Figure 19.13 shows the basic principle of ... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
On the other hand, surface charge analysis equipment using the Spy
(surface photo-voltage) method has a very similar function to that of noncontact CV apparatus. Through the transparent electrode on high dielectric
...--Sample stage T Fig. 19.... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
## 19.4 Summary
The clean level evaluation methods in production lines using MaS capacitors such as interface and dielectric breakdown characteristics, and in-line analysis techniques, such as minority carrier lifetime, TRXRF, MAIS non-contact CV, and SPY, have been described. With reducing device geometry, microconta... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
K. Yamabe *et al.:* Thermally Grown Dioxide with High Reliability, Extended Abstracts of Electrochemical Society Spring Meeting, 349 (1990).
[4]
D. L. Crook: Method of Determining Reliability Screens for Time Dependent Dielectric Breakdown, Proc. IntI. Reliability Physics Symp., 8 (1979).
D. R. Wolters and J. J. v... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
K. Okada, H. Kubo, A. Ishinaga, and K. Yoneda: A New Prediction Method for Oxide Lifetime and Its Application to Study Dielectric Mechanism, Digests of Technical Papers of Symposium on VLSI Technology (to be published June 1998).
W. H. Nicollian and J. R. Brews: MOS Physics and Technology, 435, Wiley Inter-Science (1... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Tomohisa Kitano and Kazuko Ikeda, NEC
## 20.1 Introduction
With the further miniaturization and higher integration of devices, the cleanliness of Si surface regions where the devices are fabricated is becoming more and more important. In particular, in order to guarantee long holding times for DRAM devices and to im... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
These become accumulation centres for impurities, leading to a complex problem. TEM is suitable for the observation of crystal defects caused by
plastic deformations. By observation with many different scattering vectors, the crystal defects can be characterized and identified. Fo... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
There dislocations are generated when amorphous layers become crystallized by annealing. The dislocations are generated due to stress located at the
side wall edge [4] and are due to differences in the re-cr... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
High speed and low power consumption are particularly necessary for logic devices, so it is preferable that TiSi2 is created on the diffusion layer and on the gate to lower the resistances of both the film and the contact.
The creation of TiSi2 is performed by thermal treatment in N2 atmosphere, where Ti is sputtered... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Figure 20.6 shows an example of slip dislocations. The occurrence of 12 types of slip dislocation with slip plane {111} and slip direction (110) is possible. Ideally speaking, slip dislocations generate along the crystal orientations where the thermal stress easily exceeds the value of critical shear strain [8].
Howe... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Therefore, low-temperature processing without well diffusion is preferable.
## 20.2.3 **Ion Implantation-Induced** Defects **[10]**
Ion implantation is used frequently during device manufacturing processes
such as the creation of diffusion layers, wells, and contacts, and for c... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
In order to suppress slips due to thermal stress of large diameter substrates and to cope with the miniaturization of devices, efforts to lower the process temperature are being made.
As a result, the defects caused by ion implantation cannot be properly recovered, leading to the problem of a junction leak current an... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Furthermore, factors that influence the growth of OSFs are oxidation temperature/time, atmosphere (dry or wet, and partial pressure of oxygen),
the crystal lattice orientation of the Si substrate, and impurity contamination.
Because OSF grows on the (111) lattice, for an Si(lOO) surface an OSF is observed as a bar h... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
See Sect. 21.2 for a more detailed discussion of this topic.
## 20.2.5 Contaminant-Induced Defects
In many processes the Si substrate is exposed to dangerous contaminants.
In particular, the transition metals such as Fe, Cu, Ni, and Cr create deep levels in the bandgap and become generation and recombination cente... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Furthermore, by combination with total reflection fluorescent XAFS, the local atomic and electronic structure can be detected [20]. On the other hand, in order to detect contaminants deep inside the substrate, lifetime measurements with p,-PCD [21], SPY [22], or ELYMAT [23] and deep level detection with DLTS are widely... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
| Table 20.1. Typical etchants for silicon etching Etchant Composition Etch rate/min | Remarks | ... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
| etch | CrOg | 50 g ... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
| etch | HNOg | 30cc ... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
| etch | K2Cr207 solution* | (100) ... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
| etch | HNOg | 30cc ... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
| Wright | HF | 60cc ... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
| * 0.15 mol% | ** 5 mol% | ... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Table 20.1 shows typical etching solutions and their characteristics. It is possible to detect grown-in defects, dislocations, oxygen precipitates, and silicide precipitate contamination using this etching. From the pit structures
- shallow pits or pits with deep cores - one can estimate the kind of defects.
Light-s... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Figure 20.8 shows an optimized oxygen precipitation distribution during a
thermal treatment process. In the active surface layer, no oxygen precipitates can be observed. The behavior of the oxygen precipitates depends not only on the oxygen density in bulk silicon, but also on the... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Furthermore, the differences in the conditions during Si crystal growth
(thermal history) influence the distribution of oxygen and point defects and make the behavior of grown-in defects complicated. The detection of grown-in defects is by observation of FPDs after Secco etching [28] and COP observation with particle ... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Furthermore, with the positron annihilation method the oxygen cluster extinction [32, 33] during oxygen outer diffusion, the recovery of combined oxygen/vacancy complex defects [34], and the creation of oxygen clusters
[35] due to stress occurring during oxide film growth on the Si substrate have been analyzed. In ord... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
## 20.3.2 Surface Flatness And Surface Defects
In order to improve the stepper resolution in the lithography process, the depth of focus has been lowered drastically. Therefore, Si surface flatness almost equal to the smallest feature size in the micro-pattern formation is required in terms of the LTV value. The wafer... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
As micro-roughness falls device characteristics improve. Factors influencing micro-roughness include the cleaning solution of the Si substrate, the temperature and atmosphere during oxide film formation, and mechanochemical polishing methods [38]. Figure 20.9 shows the relation between micro-roughness of a silicon wafe... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Figure 20.10 shows topographic images of the Si substrate. As a result of the suppression of the strong dynamical diffraction effect of the bulk, the weak diffraction signal of the surface strain is relatively more apparent [43].
Furthermore, from the diffractometric result in Fig... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Figure 20.12 shows defects in a trench capacitor structure of a DRAM
which has hold failure. This has been observed with TEM after having been detected by FIB [44] . Crystal defects at the bottom of the trench capacitor have been detected. The crystal defect has an octahedral structure, and EDX analysis accompanied by... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
In this chapter, we have discussed the analysis of defects in devices and Si crystals, which is an important problem for semiconductor manufacturing. In order to manufacture highly integrated and miniaturized devices with high yield, techniques for the analysis of defects are indispensable. The requirements for these a... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
T. Kitano: The Kazusa Academia Park Forum on the Science and Technology of Silicon Materials, 3 (1997).
K. Ikeda: Semiconductor Silicon, 1181 (1998).
S. M. Hu: J. Appl. Phys. 70, R53 (1991).
H. Mikobashi, N. Nishio, T. Matsumoto, H. Kikuchi, T. Kitano, and H. Kaneko: MRS Sym. Proc. 262, 626 (1992).
L. Csepregi,... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
J. M. Bloch, M. Sansone, F. Rondelez, D. G. Peiffer, P. Pincus, M. W. Kim, and P. M. Eisenberger: Phys. Rev. Lett. 54, 1039 (1985).
T. Kitano: J. Electron. Matter 21, 1027 (1992). A. S. Grove: Physics and Technology of Semiconductor Devices, John Wiley and Sons Inc. (1967).
A. M. Goodman: J. Appl. Phys. 32, 2550 (1... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Phys. 70, 7543 (1991).
[36] E. F. Steigmeier and H. Auderset: Appl. Phys. A50, 531 (1990).
[37] G. Binning, H. Roher, Ch. Gerber, and E. Weibel: Appl. Phys. Lett. 40, 176
(1982).
[38] M. Miyashita, M. Itano, T. Imaoka, I. Kawanabe, and T. Ohmi: VLSI Sci.
and Technol., 45 (1991).
[39] R. M. Smith, S. Hahn, an... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
In this chapter, we will first describe the oxidation of Si and the temperature dependence of the diffusion of dopant impurities and the solubility limit. Next, we explain "ultraclean technology" for oxidation/diffusion furnaces and the behavior of metallic impurities. Finally, another technique to control metallic imp... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
In most cases, doping of impurities into the Si substrate is carried out by ion implantation and, compared with the heat treatment of the last paragraph, at substantially lower temperatures. In the first stage of implantation, when the determines the growth rate. When the oxidation ... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
## 21.3 Activation And Diffusion Of Dopant Impurities
kinetic energy of the doping ions is high, these ions lose energy by collision with silicon atoms, and finally the ions come to rest [2]. Therefore, the Si atoms will receive kinetic energy and slip out of place in the crystal. Around the stopped ion, the creation ... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
The fundamental cell of the Si crystal is cubic, with a side length of about 0.543 nm and contains 8 atoms. The covalent bonding diameter of Si atoms is 0.1176 nm. Therefore, following the ball model, the atomic occupation rate is about 34%. Compared with Cu or Fe crystals, which have occupation rates
Fig. 21.5. Ionization energy of impurities in Si [14]
$$U=-\sigma\,V_{t h}N_{t}\frac{n_{i}}{2\cosh[(E_{t}-E_{i})/k t]}... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
See Sects. 15.2.1.2 and 15.2.2.1 for more detailed discussions of these topics.
The horizontal oxidation/diffusion furnace, which has been used for a long time, has been replaced by the vertical furnace, preventing particle problems
and air inclusion. The basic concept of the fu... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
and air inclusion. The basic concept of the furnace itself did not change, but the specifications for cleanliness have become more severe than before. In order to fulfill the stricter requirements, many techniques have been developed which include contaminant evaluation methods and high-purity materials, among others. ... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
A. S. Grove: Physics and Technology of Semiconductor Devices, Ch. 2, Wiley, NY (1967).
B. Smith: Ion Implantation Range Data for Silicon and Germanium Device Technologies, Research Studies, Forest Grove, Oregon (1977).
F. A. Trumbore: Solid Solibilities of Impurity Elements in Germanium and Silicon, Bell System Tec... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
[1]
[2]
[3]
[4] [5] [6]
[7]
[8]
[9]
[10]
[11]
[12]
[13] [14]
# 22. Cvd (Part 1): Atmospheric Pressure Flow-Pressure Cvd
Kazuo Maeda, Semiconductor Process Laboratory
## 22.1 Particle Generation Due To Cvd
This chapter will deal with the CVD technique, essential for semiconductor manufacturing. There exi... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Due to this difference in the reaction mechanism, separate treatment of the problems of particle contamination and film quality control for both methods is necessary. Generally speaking, the particle contamination and film quality is influenced in atmospheric pressure CVD and low-pressure CVD by the reactor constructio... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Regardless of whether atmospheric pressure, low-pressure, or plasma CVD is used, for the CVD technique the improvement 0f film quality and suppression of particle contamination are extremely important. This is due to the fact that the CVD film itself remains in the device (chip) as structural material.
In the followi... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Part (b) shows the deposition system in a single chamber. The gas comes from below and spreads homogeneously on the whole wafer surface. In order to obtain better film uniformity on the wafer surface the heater moves back and forth at a certain rate. The possible wafer temperature for atmospheric pressure CVD is limite... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
This is the main reason for particle contamination during the reaction.
Therefore, atmospheric pressure CVD used to be called the "particle generator". At present, for atmospheric pressure CVD the TEOS-03 reaction is
conveyor belt - **moving direction**
(a) continuous depositio... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
$$\begin{array}{l}{{\mathrm{SiH}_{4}{\mathrm{-O}}_{2}}}\\ {{\mathrm{SiH}_{4}{\mathrm{-N}}_{2}{\mathrm{O}}_{2}}}\\ {{\mathrm{TEOS-O}}_{2}}\end{array}$$
$$\begin{array}{l}{{\mathrm{(at~about~400\,^{\circ}C)}}}\\ {{\mathrm{(800\,^{\circ}C)}}}\\ {{\mathrm{(800\,^{\circ}C).}}}\end{array}... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers | ||
Here, the SiH4 gas is at present also replaced by TEOS.
## 22.3 Particle Generation 22.3.1 Characteristics Of Particles In Atmospheric Pressure And Low-Pressure Cvd
Atmospheric pressure/low-pressure CVD uses thermal activation for the reaction and not the energy of the plasma. Therefore, no problems with metals sput... | text_only | 14_Ultraclean Surface Processing of Silicon Wafers |
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