text stringlengths 0 2.2M |
|---|
}
|
if (jcp.tile_width < min_width && jcp.tile_tail < min_width)
|
jcp.tile_tail = 0;
|
}
|
/* TODO: Add stride support !
|
while ((jcp.stride_h != 1 || jcp.stride_w != 1)
|
&& (jcp.ow % jcp.tile_width != 0) || jcp.tile_width > 16) {
|
jcp.tile_width = jcp.ow / 2;
|
}
|
*/
|
// TODO: Add support for spatial tails
|
if (jcp.tile_tail != 0) return status::unimplemented;
|
// TODO: Implement efficient tile tail processing. Now just go to common
|
// case if we utilize half of tile or less.
|
if (jcp.tile_width <= jcp.max_width / 2) return status::unimplemented;
|
jcp.nb_oc_blocking = (jcp.nb_oc % 2 == 0) ? 2 : 1;
|
jcp.nb_ic_blocking = 1;
|
jcp.nb_os_blocking = (os / jcp.tile_width > 2) ? 2 : 1;
|
jcp.nb_os2_blocking = (jcp.nb_os_blocking > 1)
|
? ((jcp.nb_os_blocking * jcp.tile_width) % 2 == 0) ? 2 : 1
|
: 1;
|
jcp.nb_os = os / jcp.tile_width;
|
jcp.wsp_buffer_size = (size_t)2 * jcp.nb_os_blocking * jcp.nb_oc_blocking
|
* jcp.max_width * jcp.oc_block;
|
int ops_tile_store
|
= jcp.nb_oc_blocking * jcp.nb_os_blocking * jcp.tile_width;
|
int avaliable_ops = jcp.nb_ic_int * jcp.nb_oc_blocking * jcp.nb_os_blocking;
|
jcp.per_one_pstore
|
= (avaliable_ops) ? ops_tile_store / avaliable_ops + 1 : 0;
|
if (jcp.per_one_pstore > 12) jcp.per_one_pstore = 0;
|
const auto &oscales = attr.output_scales_;
|
jcp.is_oc_scale = oscales.mask_ == 1 << 1;
|
return status::success;
|
}
|
void jit_avx512_core_amx_1x1_fwd_kernel_t::init_scratchpad(
|
memory_tracking::registrar_t &scratchpad, const jit_conv_conf_t &jcp,
|
const primitive_attr_t &attr) {
|
scratchpad.book(key_conv_amx_wsp_buffer, jcp.nthr * jcp.wsp_buffer_size,
|
jcp.typesize_acc);
|
if (jcp.ic_without_padding % jcp.ic_block_int_np)
|
scratchpad.book(key_conv_amx_tile_buffer,
|
jcp.nthr * (jcp.wsp_buffer_size / 2), jcp.typesize_acc);
|
if (jcp.with_bias && jcp.oc != jcp.oc_without_padding) {
|
assert(jcp.ngroups == 1);
|
scratchpad.book(key_conv_padded_bias, jcp.oc, jcp.typesize_bia);
|
}
|
scratchpad.book(key_conv_amx_tilecfg, 2, 64); // 2 whole cachelines
|
}
|
} // namespace x64
|
} // namespace cpu
|
} // namespace impl
|
} // namespace dnnl
|
// vim: et ts=4 sw=4 cindent cino^=l0,\:0,N-s
|
#include <ATen/ATen.h>
|
#include <ATen/NativeFunctions.h>
|
#include <c10/util/Optional.h>
|
#include <ATen/quantized/Quantizer.h>
|
#include <c10/core/impl/DeviceGuardImplInterface.h>
|
namespace at {
|
namespace native {
|
// Take a Device that may not have device_index set (i.e., having it as -1
|
// representing the current device) and return the corresponding Device
|
// according to the actual device at the time of this function call. No-op
|
// if the device_index is set.
|
static inline Device ensure_has_index(Device device) {
|
if (device.is_cpu() || device.has_index()) {
|
return device;
|
}
|
const c10::impl::DeviceGuardImplInterface* impl = c10::impl::getDeviceGuardImpl(device.type());
|
return impl->getDevice();
|
}
|
static inline optional<Device> ensure_has_index(optional<Device> device) {
|
if (!device.has_value()) {
|
return nullopt;
|
}
|
return ensure_has_index(device.value());
|
}
|
Tensor _to_copy(
|
const Tensor& self,
|
c10::optional<ScalarType> dtype,
|
c10::optional<Layout> layout,
|
c10::optional<Device> device,
|
c10::optional<bool> pin_memory,
|
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