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| {: , : null, : 233907, : 1577836800000, : null, : 1623373181403, : 1763244026006, : null, : , : null, : , : {: , : , : , : [, , , , , , , , ], : [, , , , , , , , ], : , : , : , : , : }, : [], : [], : [], : []} |
| {: , : null, : 7316, : 1626452000567, : 1626452000567, : null, : 1626452000567, : 1626452000567, : null, : , : null, : , : {: , : [, , , , , , , , ], : [, , , , , , , , ], : , : }, : [], : [], : [], : []} |
| {: , : , : 6, : 1608571690029, : null, : 1608571690029, : 1760257885415, : null, : , : null, : , : {: , : [, , , , ], : [, , , , ], : [, , , ], : , : , : , : , : , : o}nig and Henrik Linusson},\nbooktitle={Research Symposium on Tiny Machine Learning},\nyear={2021},\nurl={https://openreview.net/forum?id=L37gp2avJVu}\n}venueidtinyml.org/tinyML/2021/Research_SymposiumvenuetinyML 2021 Postersignaturestinyml.org/tinyML/2021/Research_Symposiumreaderseveryonenonreaderswriterstinyml.org/tinyML/2021/Research_Symposiumpdateodate |
| idLYzEISv1breoriginalk3oGznPlDYMnumbercdateddatetcdatetmdatetddateforumLYzEISv1brereplytoinvitationtinyml.org/tinyML/2021/Research_Symposium/-/Blind_SubmissioncontenttitleTTVOS: Lightweight Video Object Segmentation with Adaptive Template Attention Module and Temporal Consistency Lossauthorids~Hyojin_Park1~Ganesh_Venkatesh1~Nojun_Kwak1authorsHyojin ParkGanesh VenkateshNojun KwakkeywordsSemi-supervised video segmentationvideo trackinglightweight segmentationTL;DR we propose an adaptive template matching method and a novel temporal consistency loss for Semi-supervised video object segmentationabstractSemi-supervised video object segmentation (semi-VOS) is widely used in many applications.\nThis task is tracking class-agnostic objects by a given segmentation mask.\nFor doing this, various approaches have been developed based on online-learning, memory networks, and optical flow.\nThese methods show high accuracy but are hard to be utilized in real-world applications due to slow inference time and tremendous complexity.\nTo resolve this problem, template matching methods are devised for fast processing speed, sacrificing lots of performance.\nWe introduce a novel semi-VOS model based on a temple matching method and a novel temporal consistency loss to reduce the performance gap from heavy models while expediting inference time a lot.\nOur temple matching method consists of short-term and long-term matching.\nThe short-term matching enhances target object localization, while long-term matching improves fine details and handles object shape-changing through the newly proposed adaptive template attention module.\nHowever, the long-term matching causes error-propagation due to the inflow of the past estimated results when updating the template.\nTo mitigate this problem, we also propose a temporal consistency loss for better temporal coherence between neighboring frames by adopting the concept of a transition matrix.\nOur model obtains 79.5% J&F score at the speed of 73.8 FPS on the DAVIS16 benchmark.pdf/pdf/7bbef9e496b21f8fa57f84f62fe8b1b19f537d66.pdfpaperhashpark|ttvos_lightweight_video_object_segmentation_with_adaptive_template_attention_module_and_temporal_consistency_losscommunity_implementations[ 4 code implementations](https://www.catalyzex.com/paper/ttvos-lightweight-video-object-segmentation/code)_bibtex@inproceedings{\npark2021ttvos,\ntitle={{\\{}TTVOS{\\}}: Lightweight Video Object Segmentation with Adaptive Template Attention Module and Temporal Consistency Loss},\nauthor={Hyojin Park and Ganesh Venkatesh and Nojun Kwak},\nbooktitle={Research Symposium on Tiny Machine Learning},\nyear={2021},\nurl={https://openreview.net/forum?id=LYzEISv1bre}\n}venueidtinyml.org/tinyML/2021/Research_SymposiumvenuetinyML 2021 Regularsignaturestinyml.org/tinyML/2021/Research_Symposiumreaderseveryonenonreaderswriterstinyml.org/tinyML/2021/Research_Symposiumpdateodate |
| idgcaV8J8pQrxoriginallk5inr6PFH7numbercdateddatetcdatetmdatetddateforumgcaV8J8pQrxreplytoinvitationtinyml.org/tinyML/2021/Research_Symposium/-/Blind_SubmissioncontenttitleSmartphone Impostor Detection with Behavioral Data Privacy and Minimalist Hardware Supportauthorids~Guangyuan_Hu1~Zecheng_He1~Ruby_B._Lee1authorsGuangyuan HuZecheng HeRuby B. LeekeywordsAnomaly detectiondeep learninghardware acceleratorsecurityTL;DRPrivacy-preserving impostor detection with deep learning and the hardware support.abstractImpostors are attackers who take over a smartphone and gain access to the legitimate user's confidential and private information. This paper proposes a defense-in-depth mechanism that can detect impostors quickly with simple Deep Learning algorithms, which can achieve better detection accuracy than the best prior work which used Machine Learning algorithms requiring computation of multiple features. Different from previous work, we then consider protecting the privacy of a user's behavioral (sensor) data by not exposing it outside the smartphone. For this scenario, we propose a Recurrent Neural Network (RNN) based Deep Learning algorithm that uses only the legitimate user's sensor data to learn his/her normal behavior. We propose to use Prediction Error Distribution (PED) to enhance the detection accuracy. To make the on-device, real-time detection possible, we show how a minimalist hardware module, dubbed SID for Smartphone Imposter Detector, can be designed and integrated into smartphones for self-contained impostor detection. Experimental results show that SID can support real-time impostor detection, at a very low hardware cost and energy consumption, compared to other RNN accelerators.", "pdf": "/pdf/6d4d3b33f10d8c1930ee81ff017dbaf6c9f649c5.pdf", "paperhash": "hu|smartphone_impostor_detection_with_behavioral_data_privacy_and_minimalist_hardware_support", "_bibtex": "@inproceedings{\nhu2021smartphone,\ntitle={Smartphone Impostor Detection with Behavioral Data Privacy and Minimalist Hardware Support},\nauthor={Guangyuan Hu and Zecheng He and Ruby B. Lee},\nbooktitle={Research Symposium on Tiny Machine Learning},\nyear={2021},\nurl={https://openreview.net/forum?id=gcaV8J8pQrx}\n}", "venueid": "tinyml.org/tinyML/2021/Research_Symposium", "venue": "tinyML 2021 Regular"}, "signatures": ["tinyml.org/tinyML/2021/Research_Symposium"], "readers": ["everyone"], "nonreaders": [], "writers": ["tinyml.org/tinyML/2021/Research_Symposium"], "pdate": 1612735229175, "odate": 1608571692695} |
| {"id": "TeRZyNF9anM", "original": "SwFajU1QRtN", "number": 22, "cdate": 1608571692984, "ddate": null, "tcdate": 1608571692984, "tmdate": 1683307472832, "tddate": null, "forum": "TeRZyNF9anM", "replyto": null, "invitation": "tinyml.org/tinyML/2021/Research_Symposium/-/Blind_Submission", "content": {"title": "SWIS - Shared Weight bIt Sparsity for Efficient Neural Network Acceleration", "authorids": ["~Shurui_Li1", "~Wojciech_Romaszkan1", "agraening@ucla.edu", "~Puneet_Gupta1"], "authors": ["Shurui Li", "Wojciech Romaszkan", "Alexander Graening", "Puneet Gupta"], "keywords": ["machine learning", "accelerators", "neural networks", "quantization"], "TL;DR": "SWIS - a methodology for more efficient neural network quantization and execution on bit-serial accelerators.", "abstract": "Quantization is spearheading the increase in performance and efficiency of neural network computing systems making headway into commodity hardware. We present SWIS - Shared Weight bIt Sparsity, a quantization framework for efficient neural network inference acceleration delivering improved performance and storage compression through an offline weight decomposition and scheduling algorithm. SWIS can achieve up to 52% (19.8%) point accuracy improvement when quantizing MobileNet-v2 to 4 (2) bits post-training (with retraining) showing the strength of leveraging shared bit-sparsity in weights. SWIS accelerator gives up to 6X speedup and 1.8X energy improvement over state of the art bit-serial architectures. ", "pdf": "/pdf/5493ae686b17e1657ae31e342fb4b9750e13a4d2.pdf", "paperhash": "li|swis_shared_weight_bit_sparsity_for_efficient_neural_network_acceleration", "_bibtex": "@inproceedings{\nli2021swis,\ntitle={{\\{}SWIS{\\}} - Shared Weight bIt Sparsity for Efficient Neural Network Acceleration},\nauthor={Shurui Li and Wojciech Romaszkan and Alexander Graening and Puneet Gupta},\nbooktitle={Research Symposium on Tiny Machine Learning},\nyear={2021},\nurl={https://openreview.net/forum?id=TeRZyNF9anM}\n}", "venueid": "tinyml.org/tinyML/2021/Research_Symposium", "venue": "tinyML 2021 Regular"}, "signatures": ["tinyml.org/tinyML/2021/Research_Symposium"], "readers": ["everyone"], "nonreaders": [], "writers": ["tinyml.org/tinyML/2021/Research_Symposium"], "pdate": 1612735228903, "odate": 1608571693043} |
| {"id": "rlHeH9tx3SM", "original": "e9jUH6sVjIJ", "number": 19, "cdate": 1608571692441, "ddate": null, "tcdate": 1608571692441, "tmdate": 1683307472609, "tddate": null, "forum": "rlHeH9tx3SM", "replyto": null, "invitation": "tinyml.org/tinyML/2021/Research_Symposium/-/Blind_Submission", "content": {"title": "Privacy-Preserving Inference on the Edge: Mitigating a New Threat Model", "authorids": ["~Kartik_Prabhu1", "bjun2@stanford.edu", "~Pan_Hu1", "zasgar@stanford.edu", "~Sachin_Katti1", "petewarden@google.com"], "authors": ["Kartik Prabhu", "Brian Jun", "Pan Hu", "Zain Asgar", "Sachin Katti", "Pete Warden"], "keywords": ["privacy", "security", "edge inference", "embedded", "secure enclave", "TEE"], "TL;DR": "This paper proposes using a secure enclave for privacy-preserving machine learning at the edge.", "abstract": "With the explosion of machine learning at the edge, there's a major need for privacy-preserving machine learning for edge devices. As the number of devices in homes and other private spaces increases, we can expect to see more malicious actors exploiting the inherent recording capabilities in these systems to harm people. This paper proposes that machine learning is not the problem, but rather a solution, which along with the use of a secure enclave, offers a pragmatic approach to preserving privacy. With a simple programming framework, we show how machine learning application developers can be as productive as usual, while still keeping user data private. We demonstrate our implementation for privacy-preserving machine learning on an embedded system, the Nordic NRF5340 PDK with Arm Cotex-M-33, using a relatively large model for person-detection. pdf/pdf/5e62b1d1876a50831ea54e20f26f304ed1137506.pdfpaperhashprabhu|privacypreserving_inference_on_the_edge_mitigating_a_new_threat_model_bibtex@inproceedings{\nprabhu2021privacypreserving,\ntitle={Privacy-Preserving Inference on the Edge: Mitigating a New Threat Model},\nauthor={Kartik Prabhu and Brian Jun and Pan Hu and Zain Asgar and Sachin Katti and Pete Warden},\nbooktitle={Research Symposium on Tiny Machine Learning},\nyear={2021},\nurl={https://openreview.net/forum?id=rlHeH9tx3SM}\n}venueidtinyml.org/tinyML/2021/Research_SymposiumvenuetinyML 2021 Postersignaturestinyml.org/tinyML/2021/Research_Symposiumreaderseveryonenonreaderswriterstinyml.org/tinyML/2021/Research_Symposiumpdateodate |
| idJGNDej3tup9originalQGpP6kX0wdenumbercdateddatetcdatetmdatetddateforumJGNDej3tup9replytoinvitationtinyml.org/tinyML/2021/Research_Symposium/-/Blind_SubmissioncontenttitleHypervector Design for Efficient Hyperdimensional Computing on Edge Devicesauthorids~Toygun_Basaklar1tuncel@wisc.edunarayana3@wisc.edusuat.gumussoy@siemens.comuogras@wisc.eduauthorsToygun BasaklarYigit TuncelShruti Yadav NarayanaSuat GumussoyUmit Y. OgraskeywordsHyperdimensional computinglow-power learning algorithmoptimizationTL;DRThis paper presents a hypervector design technique for efficient hyperdimensional computing. It aims to achieve high accuracy and robustness with smaller dimensions while significantly reducing energy consumption and computational resources.abstractHyperdimensional computing (HDC) has emerged as a new light-weight learning algorithm with smaller computation and energy requirements compared to conventional techniques. In HDC, data points are represented by high dimensional vectors (hypervectors), which are mapped to high dimensional space (hyperspace). Typically, a large hypervector dimension ($\\geq1000$) is required to achieve accuracies comparable to conventional alternatives. However, unnecessarily large hypervectors increase hardware and energy costs, which can undermine their benefits. This paper presents a technique to minimize the hypervector dimension while maintaining the accuracy and improving the robustness of the classifier. To this end, we formulate hypervector design as a multi-objective optimization problem for the first time in the literature. The proposed approach decreases the hypervector dimension by more than $128\\times$ while maintaining or increasing the accuracy achieved by conventional HDC. Experiments on a commercial hardware platform show that the proposed approach achieves more than two orders of magnitude reduction in model size, inference time, and energy consumption. We also demonstrate the trade-off between accuracy and robustness to noise and provide Pareto front solutions as a design parameter in our hypervector design.\npdf/pdf/fc43d8eca4cf8f650ef92b6ce8fa9c61c8c31b97.pdfpaperhashbasaklar|hypervector_design_for_efficient_hyperdimensional_computing_on_edge_devices_bibtex@inproceedings{\nbasaklar2021hypervector,\ntitle={Hypervector Design for Efficient Hyperdimensional Computing on Edge Devices},\nauthor={Toygun Basaklar and Yigit Tuncel and Shruti Yadav Narayana and Suat Gumussoy and Umit Y. Ogras},\nbooktitle={Research Symposium on Tiny Machine Learning},\nyear={2021},\nurl={https://openreview.net/forum?id=JGNDej3tup9}\n}venueidtinyml.org/tinyML/2021/Research_SymposiumvenuetinyML 2021 Regularsignaturestinyml.org/tinyML/2021/Research_Symposiumreaderseveryonenonreaderswriterstinyml.org/tinyML/2021/Research_Symposiumpdateodate |
| id-iuG__7I9QEoriginalrhve3N1YDenumbercdateddatetcdatetmdatetddateforum-iuG__7I9QEreplytoinvitationtinyml.org/tinyML/2021/Research_Symposium/-/Blind_SubmissioncontenttitleDoes Form Follow Function? An Empirical Exploration of the Impact of Deep Neural Network Architecture Design on Hardware-Specific Accelerationauthorids~Saad_Abbasi1~Mohammad_Javad_Shafiee1ellick.chan@northwestern.edualexander.wong@uwaterloo.caauthorsSaad AbbasiMohammad Javad ShafieeEllick ChanAlexander WongkeywordsNeural NetworksEdge DevicesHardware AccelerationOpenVINOMacro-ArchitecturesEmbedded Machine LearningDesign PatternsTL;DRWe examine whether neural network design has an impact on hardware acceleration. The network latency, number of FLOPS and cache efficacy of several neural network design patterns are measured to establish which macro-architectures are efficient.abstractAdvances in deep learning during the last decade have led to state-of-the-art performance across a wide variety of tasks. However, one of the biggest challenges with the widespread adoption of deep learning in an operational manner has been high computational complexity. This challenge is particularly important to tackle given the recent proliferation of smart sensors and edge devices. This has led to hardware-specific acceleration platforms designed specifically to accelerate deep neural network inference based on microprocessor architectural traits. While promising, the degree of inference speed gains achieved via hardware-specific acceleration can vary significantly depending on the design of the deep neural network architecture and the microprocessor being leveraged for inference. The fine-grained relationship between form and function with respect to deep neural network architecture design and hardware-specific acceleration is one area that is not well studied in the research literature, with form often dictated by accuracy as opposed to hardware function. In this study, a comprehensive empirical exploration is conducted to investigate the impact of deep neural network architecture design on the degree of inference speedup that can be achieved via hardware-specific acceleration. More specifically, we empirically study the impact of a variety of commonly used macro-architecture design patterns across different architectural depths through the lens of OpenVINO microprocessor-specific and GPU-specific acceleration. Experimental results showed that while leveraging hardware-specific acceleration achieved an average inference speed-up of 380%, the degree of inference speed-up varied drastically depending on the macro-architecture design pattern, with the greatest speedup achieved on the depthwise bottleneck convolution design pattern at 550%. Furthermore, we conduct an in-depth exploration of the correlation between FLOPs requirement, level 3 cache efficacy, and network latency with increasing architectural depth and width. Finally, we analyze the inference time reductions using hardware-specific acceleration when compared to native deep learning frameworks across a wide variety of hand-crafted deep convolutional neural network architecture designs as well as ones found via neural architecture search strategies. We found that the DARTS-derived architecture to benefit from the greatest improvement from hardware acceleration (1200%) while the depthwise bottleneck convolution-based MobileNet-V2 to have the lowest overall inference time of around 2.4 ms. These findings illustrate the importance of tailoring network architecture design to account for the intricacies of microprocessor architecture traits to enable greater hardware-specific acceleration.pdf/pdf/4f520b6099ff41b045f75937975142a42d81e737.pdfpaperhashabbasi|does_form_follow_function_an_empirical_exploration_of_the_impact_of_deep_neural_network_architecture_design_on_hardwarespecific_acceleration_bibtex@inproceedings{\nabbasi2021does,\ntitle={Does Form Follow Function? An Empirical Exploration of the Impact of Deep Neural Network Architecture Design on Hardware-Specific Acceleration},\nauthor={Saad Abbasi and Mohammad Javad Shafiee and Ellick Chan and Alexander Wong},\nbooktitle={Research Symposium on Tiny Machine Learning},\nyear={2021},\nurl={https://openreview.net/forum?id=-iuG__7I9QE}\n}venueidtinyml.org/tinyML/2021/Research_SymposiumvenuetinyML 2021 Postersignaturestinyml.org/tinyML/2021/Research_Symposiumreaderseveryonenonreaderswriterstinyml.org/tinyML/2021/Research_Symposiumpdateodate |
| idgddOffMRWE3originalEyeCD1WPnZOnumbercdateddatetcdatetmdatetddateforumgddOffMRWE3replytoinvitationtinyml.org/tinyML/2021/Research_Symposium/-/Blind_SubmissioncontenttitleMemory-Efficient, Limb Position-Aware Hand Gesture Recognition using Hyperdimensional Computingauthorids~Andy_Zhou1~Rikky_Muller1~Jan_Rabaey1authorsAndy ZhouRikky MullerJan Rabaeykeywordshyperdimensional computinggesture recognitionmulti-context classificationTL;DRSensor fusion enables memory-efficient storage of hyperdimensional computing classification parameters for gesture recognition in multiple limb positions.abstractElectromyogram (EMG) pattern recognition can be used to classify hand gestures and movements for human-machine interface and prosthetics applications, but it often faces reliability issues resulting from limb position change. One method to address this is dual-stage classification, in which the limb position is first determined using additional sensors to select between multiple position-specific gesture classifiers. While improving performance, this also increases model complexity and memory footprint, making a dual-stage classifier difficult to implement in a wearable device with limited resources. In this paper, we present sensor fusion of accelerometer and EMG signals using a hyperdimensional computing model to emulate dual-stage classification in a memory-efficient way. We demonstrate two methods of encoding accelerometer features to act as keys for retrieval of position-specific parameters from multiple models stored in superposition. Through validation on a dataset of 13 gestures in 8 limb positions, we obtain a classification accuracy of up to $93.34\\%$, an improvement of $17.79\\%$ over using a model trained solely on EMG. We achieve this while only marginally increasing memory footprint over a single limb position model, requiring $8\\times$ less memory than a traditional dual-stage classification architecture.pdf/pdf/c53cc34a2776ecea8ddbc14e7c7f5efcd17ad164.pdfpaperhashzhou|memoryefficient_limb_positionaware_hand_gesture_recognition_using_hyperdimensional_computing_bibtex@inproceedings{\nzhou2021memoryefficient,\ntitle={Memory-Efficient, Limb Position-Aware Hand Gesture Recognition using Hyperdimensional Computing},\nauthor={Andy Zhou and Rikky Muller and Jan Rabaey},\nbooktitle={Research Symposium on Tiny Machine Learning},\nyear={2021},\nurl={https://openreview.net/forum?id=gddOffMRWE3}\n}venueidtinyml.org/tinyML/2021/Research_SymposiumvenuetinyML 2021 Regularsignaturestinyml.org/tinyML/2021/Research_Symposiumreaderseveryonenonreaderswriterstinyml.org/tinyML/2021/Research_Symposiumpdateodate |
| idzEJDxAKKiatoriginallUhSrazFtFTnumbercdateddatetcdatetmdatetddateforumzEJDxAKKiatreplytoinvitationtinyml.org/tinyML/2021/Research_Symposium/-/Blind_SubmissioncontenttitleDeep Learning for Compute in Memoryauthorids~Matthias_Reisser1spitre@qti.qualcomm.comxiaochun@qti.qualcomm.com~Harris_Teague1zwang@qti.qualcomm.com~Max_Welling1authorsMatthias ReisserSaurabh PitreXiaochun ZhuHarris TeagueJoseph WangMax WellingkeywordsCompute in MemoryDeep LearningNoise aware trainingbinary neural networkSimulationTL;DRWe show how a differentiable simulator for compute in memory hardware can make neural networks robust and inform hardware designabstractCompute in Memory (CIM) accelerators for neural networks promise large efficiency gains, allowing for deep learning applications on extremely resource-constrained devices. Compared to classical digital processors, computations on CIM accelerators are subject to a variety of noise sources such as process variations, thermal effects, quantization, and more. In this work, we show how fundamental hardware design choices influence the predictive performance of neural networks and how training these models to be hardware-aware can make them more robust for CIM deployment. Through various experiments, we make the trade-offs between energy efficiency and model capacity explicit and showcase the benefits of taking a systems view on CIM accelerator and neural network training co-design.pdf/pdf/fa14dd2dd2078aaa3fcfb91c1a9b4a876540d4a1.pdfpaperhashreisser|deep_learning_for_compute_in_memory_bibtex@inproceedings{\nreisser2021deep,\ntitle={Deep Learning for Compute in Memory},\nauthor={Matthias Reisser and Saurabh Pitre and Xiaochun Zhu and Harris Teague and Joseph Wang and Max Welling},\nbooktitle={Research Symposium on Tiny Machine Learning},\nyear={2021},\nurl={https://openreview.net/forum?id=zEJDxAKKiat}\n}venueidtinyml.org/tinyML/2021/Research_SymposiumvenuetinyML 2021 Postersignaturestinyml.org/tinyML/2021/Research_Symposiumreaderseveryonenonreaderswriterstinyml.org/tinyML/2021/Research_Symposiumpdateodate |
| idO0kjwqJyhNdoriginal_Ip7mTD2ss2numbercdateddatetcdatetmdatetddateforumO0kjwqJyhNdreplytoinvitationtinyml.org/tinyML/2021/Research_Symposium/-/Blind_SubmissioncontenttitleCompiler Toolchains for Deep Learning Workloads on Embedded Platformsauthorids~Max_Sponner1bernd.waschneck@infineon.comakash.kumar@tu-dresden.deauthorsMax SponnerBernd WaschneckAkash Kumarkeywordsdeep learningembeddeddeep learning compilerembedded deep learningTL;DRA survey of available deep learning compilers as well as an example implementation for a new accelerator device.abstractAs the usage of deep learning becomes increasingly popular in mobile and embedded solutions, it is necessary to convert the framework-specific network representations into executable code for these embedded platforms.\nThis paper starts with a survey and benchmark of the available open source deep learning compiler toolchains, which focuses on the capabilities and performance of the toolchains in regard to targeting embedded microcontrollers that are combined with a dedicated accelerator in a heterogeneous fashion.\nThe second part focuses on the implementation and evaluation of a compilation flow that targets such a solution and reuses one of the existing toolchains to demonstrate the necessary steps for hardware developers to build a software flow for their product.pdf/pdf/4c97f0ea5e9843d685fb53bded2728b59880e1a2.pdfpaperhashsponner|compiler_toolchains_for_deep_learning_workloads_on_embedded_platforms_bibtex@inproceedings{\nsponner2021compiler,\ntitle={Compiler Toolchains for Deep Learning Workloads on Embedded Platforms},\nauthor={Max Sponner and Bernd Waschneck and Akash Kumar},\nbooktitle={Research Symposium on Tiny Machine Learning},\nyear={2021},\nurl={https://openreview.net/forum?id=O0kjwqJyhNd}\n}venueidtinyml.org/tinyML/2021/Research_SymposiumvenuetinyML 2021 Regularsignaturestinyml.org/tinyML/2021/Research_Symposiumreaderseveryonenonreaderswriterstinyml.org/tinyML/2021/Research_Symposiumpdateodate |
| id_Qtnx5BY6ZToriginaljmYfsICSpmlnumbercdateddatetcdatetmdatetddateforum_Qtnx5BY6ZTreplytoinvitationtinyml.org/tinyML/2021/Research_Symposium/-/Blind_SubmissioncontenttitleAn Ultra-low Power RNN Classifier for Always-On Voice Wake- Up Detection Robust to Real-World Scenariosauthorids~Emmanuel_Hardy1franck.badets@cea.frauthorsEmmanuel HardyFranck BadetskeywordsVoice Activity Detection (VAD)Wake-Up SensorRecurrent Neural Network (RNN)Gated Recurrent Unit (GRU)Machine LearningInternet of Things (IoT)Ultra Low PowerApproximate QuantizationASICTL;DRWe show the superiority of RNNs as ultra-low power classifiers for Voice Wake-Up tasks in terms of detection performance, robustness to unseen noises and low complexity.abstractWe present in this paper an ultra-low power (ULP) Recurrent Neural Network (RNN) based classifier for an always-on voice Wake-Up Sensor (WUS) with performances suitable for real-world applications. The purpose of our sensor is to bring down by at least a factor 100 the power consumption in background noise of always-on speech processing algorithms such as Automatic Speech Recognition, Keyword Spotting, Speaker Verification, etc. Unlike the other published approaches, we designed our wake-up sensor to be robust to unseen real-world noises for realistic levels of speech and noise by carefully designing the dataset and the loss function. We also specifically trained it to mark only the speech start rather than adopting a traditional Voice Activity Detection (VAD) approach. We achieve less than 3% No Trigger Rate (NTR) for a duty cycle less than 1% in challenging background noises pooled. We demonstrate the superiority of RNNs on this task compared to the other tested approaches, with an estimated power consumption of 30 nW in 65nm CMOS and a minimal memory footprint of 0.52 kB.pdf/pdf/6d9cb0cd863b7d9fa6991283519e197f54539b7d.pdfpaperhashhardy|an_ultralow_power_rnn_classifier_for_alwayson_voice_wake_up_detection_robust_to_realworld_scenarios_bibtex@inproceedings{\nhardy2021an,\ntitle={An Ultra-low Power {\\{}RNN{\\}} Classifier for Always-On Voice Wake- Up Detection Robust to Real-World Scenarios},\nauthor={Emmanuel Hardy and Franck Badets},\nbooktitle={Research Symposium on Tiny Machine Learning},\nyear={2021},\nurl={https://openreview.net/forum?id=_Qtnx5BY6ZT}\n}venueidtinyml.org/tinyML/2021/Research_SymposiumvenuetinyML 2021 Postersignaturestinyml.org/tinyML/2021/Research_Symposiumreaderseveryonenonreaderswriterstinyml.org/tinyML/2021/Research_Symposiumpdateodate |
| idz7GTwNqUuUtoriginalnumbercdatemdateddatetcdatetmdatetddateforum8RxxwAut1BIreplyto8RxxwAut1BIinvitationNeurIPS.cc/2021/Track/Datasets_and_Benchmarks/Round1/Paper120/-/Official_ReviewcontenttitleStandardized and Diverse Benchmarks for TinyMLrating7: Good paper, acceptconfidence4: The reviewer is confident but not absolutely certain that the evaluation is correctsummary and contributionsThe paper collects and adapts previously published datasets to construct a standardized benchmark for TinyML methods, which previously suffer from poor comparability due to software/hardware heterogeneity. The tasks include keyword spotting, visual wake words, image classification, and anomaly detection. The benchmark has two divisions, one allowing any changes to the pipeline and one only allowing post training optimization. It measures accuracy, latency and energy use.strengths1. The benchmark contains a wide range of tasks, despite lacking NLP-related ones. The tasks are also oriented at low-resource environments and applications can be found in real life (e.g., single person detection for doorbells). \n2. The measurement considers latency, energy and accuracy. The use of a quality threshold instead of the commonly used tradeoff curve comparisons greatly simplifies the comparison. \n3. The benchmark has two divisions: an open division that allows the change of model, data, training, and a closed division that focuses more on post-training optimization. This allows different methods that focus on different parts of the whole optimization process to show their benefits more clearly.\n4. The challenges for constructing a standardized TinyML benchmark are well summarized in the related work section. weaknessesThe running and submission process to the benchmark, as documented in the Appendix, requires significantly more effort than a typical benchmark submission, where submitters usually only submit the test results. This can limit the number of submitters. However, this is perhaps a tradeoff that has to be made for more comparability for the widely heterogenous TinyML works.\n\nIt would also be nice to include a summary of the execution process in the main paper instead of only documenting in Appendix.\n\ncorrectnessYes. The benchmark is constructed from previously published datasets, with adaptations made for low-resource and simplicity considerations. The evaluation and experiment design are well documented in paper.clarityThe paper is well written.relation to prior workYes.documentationYes.ethicsThe potential ethical impact was discussed in paper.additional feedbackPlease see strengths and weaknesses.signaturesNeurIPS.cc/2021/Track/Datasets_and_Benchmarks/Round1/Paper120/Reviewer_k8efreaderseveryonenonreaderswritersNeurIPS.cc/2021/Track/Datasets_and_Benchmarks/Round1NeurIPS.cc/2021/Track/Datasets_and_Benchmarks/Round1/Paper120/Reviewer_k8efforumContent |
| idC1mPUP7uKNporiginalIqBWy3IYCOKnumbercdateddatetcdatetmdatetddateforumC1mPUP7uKNpreplytoinvitationNeurIPS.cc/2021/Conference/-/Blind_SubmissioncontenttitleMemory-efficient Patch-based Inference for Tiny Deep Learningauthorids~Ji_Lin1~Wei-Ming_Chen1~Han_Cai1~Chuang_Gan1~Song_Han5authorsJi LinWei-Ming ChenHan CaiChuang GanSong Hankeywordstiny deep learningtinyMLabstractTiny deep learning on microcontroller units (MCUs) is challenging due to the limited memory size. We find that the memory bottleneck is due to the imbalanced memory distribution in convolutional neural network (CNN) designs: the first several blocks have an order of magnitude larger memory usage than the rest of the network. To alleviate this issue, we propose a generic patch-by-patch inference scheduling, which operates only on a small spatial region of the feature map and significantly cuts down the peak memory. However, naive implementation brings overlapping patches and computation overhead. We further propose receptive field redistribution to shift the receptive field and FLOPs to the later stage and reduce the computation overhead. Manually redistributing the receptive field is difficult. We automate the process with neural architecture search to jointly optimize the neural architecture and inference scheduling, leading to MCUNetV2. Patch-based inference effectively reduces the peak memory usage of existing networks by4-8×. Co-designed with neural networks, MCUNetV2 sets a record ImageNetaccuracy on MCU (71.8%) and achieves >90% accuracy on the visual wake words dataset under only 32kB SRAM. MCUNetV2 also unblocks object detection on tiny devices, achieving 16.9% higher mAP on Pascal VOC compared to the state-of-the-art result. Our study largely addressed the memory bottleneck in tinyML and paved the way for various vision applications beyond image classification.submission_historycode_of_conductI certify that all co-authors of this work have read and commit to adhering to the NeurIPS Statement on Ethics, Fairness, Inclusivity, and Code of Conduct.paperhashlin|memoryefficient_patchbased_inference_for_tiny_deep_learningTL;DRBreaking the memory bottleneck of tinyML with patch-based inference.pdf/pdf/7e958fd6848b1cb5dca1687c5e93bfa46724e3f6.pdfchecklistsupplementary_material/attachment/bea8e335190cded8dab22397faa9228e4d6f494e.pdfthumbnailsubmission_history_-_venue_and_yearsubmission_history_-_improvements_made_bibtex@inproceedings{\nlin2021memoryefficient,\ntitle={Memory-efficient Patch-based Inference for Tiny Deep Learning},\nauthor={Ji Lin and Wei-Ming Chen and Han Cai and Chuang Gan and Song Han},\nbooktitle={Advances in Neural Information Processing Systems},\neditor={A. Beygelzimer and Y. Dauphin and P. Liang and J. Wortman Vaughan},\nyear={2021},\nurl={https://openreview.net/forum?id=C1mPUP7uKNp}\n}venueNeurIPS 2021 PostervenueidNeurIPS.cc/2021/ConferencesignaturesNeurIPS.cc/2021/ConferencereaderseveryonenonreaderswritersNeurIPS.cc/2021/Conferencemdatepdateodate |
| id-erZz2NsR_Eoriginalnumbercdateddatetcdatetmdatetddateforum-erZz2NsR_Ereplytoinvitationdblp.org/-/recordcontentvenueCoRR 2021venueiddblp.org/journals/CORR/2021_bibtex@article{DBLP:journals/corr/abs-2106-04008,\n publtype={informal},\n author={Vijay Janapa Reddi and Brian Plancher and Susan Kennedy and Laurence Moroney and Pete Warden and Anant Agarwal and Colby R. Banbury and Massimo Banzi and Matthew Bennett and Benjamin Brown and Sharad Chitlangia and Radhika Ghosal and Sarah Grafman and Rupert Jaeger and Srivatsan Krishnan and Maximilian Lam and Daniel Leiker and Cara Mann and Mark Mazumder and Dominic Pajak and Dhilan Ramaprasad and J. Evan Smith and Matthew Stewart and Dustin Tingley},\n title={Widening Access to Applied Machine Learning with TinyML},\n year={2021},\n cdate={1609459200000},\n journal={CoRR},\n volume={abs/2106.04008},\n url={https://arxiv.org/abs/2106.04008}\n}\nauthorsVijay Janapa ReddiBrian PlancherSusan KennedyLaurence MoroneyPete WardenAnant AgarwalColby R. BanburyMassimo BanziMatthew BennettBenjamin BrownSharad ChitlangiaRadhika GhosalSarah GrafmanRupert JaegerSrivatsan KrishnanMaximilian LamDaniel LeikerCara MannMark MazumderDominic PajakDhilan RamaprasadJ. Evan SmithMatthew StewartDustin Tingleyauthorids~Vijay_Janapa_Reddi1~Brian_Plancher1https://dblp.org/search/pid/api?q=author:Susan_Kennedy:https://dblp.org/search/pid/api?q=author:Laurence_Moroney:~Pete_Warden2https://dblp.org/search/pid/api?q=author:Anant_Agarwal:~Colby_Banbury1https://dblp.org/search/pid/api?q=author:Massimo_Banzi:https://dblp.org/search/pid/api?q=author:Matthew_Bennett:https://dblp.org/search/pid/api?q=author:Benjamin_Brown:https://dblp.org/search/pid/api?q=author:Sharad_Chitlangia:https://dblp.org/search/pid/api?q=author:Radhika_Ghosal:https://dblp.org/search/pid/api?q=author:Sarah_Grafman:https://dblp.org/search/pid/api?q=author:Rupert_Jaeger:https://dblp.org/search/pid/api?q=author:Srivatsan_Krishnan:https://dblp.org/search/pid/api?q=author:Maximilian_Lam:https://dblp.org/search/pid/api?q=author:Daniel_Leiker:https://dblp.org/search/pid/api?q=author:Cara_Mann:https://dblp.org/search/pid/api?q=author:Mark_Mazumder:https://dblp.org/search/pid/api?q=author:Dominic_Pajak:https://dblp.org/search/pid/api?q=author:Dhilan_Ramaprasad:https://dblp.org/search/pid/api?q=author:J._Evan_Smith:https://dblp.org/search/pid/api?q=author:Matthew_Stewart:https://dblp.org/search/pid/api?q=author:Dustin_Tingley:htmlhttps://arxiv.org/abs/2106.04008titleWidening Access to Applied Machine Learning with TinyMLpaperhashreddi|widening_access_to_applied_machine_learning_with_tinymlabstractBroadening access to both computational and educational resources is critical to diffusing machine-learning (ML) innovation. However, today, most ML resources and experts are siloed in a few countries and organizations. In this paper, we describe our pedagogical approach to increasing access to applied ML through a massive open online course (MOOC) on Tiny Machine Learning (TinyML). We suggest that TinyML, ML on resource-constrained embedded devices, is an attractive means to widen access because TinyML both leverages low-cost and globally accessible hardware, and encourages the development of complete, self-contained applications, from data collection to deployment. To this end, a collaboration between academia (Harvard University) and industry (Google) produced a four-part MOOC that provides application-oriented instruction on how to develop solutions using TinyML. The series is openly available on the edX MOOC platform, has no prerequisites beyond basic programming, and is designed for learners from a global variety of backgrounds. It introduces pupils to real-world applications, ML algorithms, data-set engineering, and the ethical considerations of these technologies via hands-on programming and deployment of TinyML applications in both the cloud and their own microcontrollers. To facilitate continued learning, community building, and collaboration beyond the courses, we launched a standalone website, a forum, a chat, and an optional course-project competition. We also released the course materials publicly, hoping they will inspire the next generation of ML practitioners and educators and further broaden access to cutting-edge ML technologies.pdfhttp://arxiv.org/pdf/2106.04008v2signatures~Colby_Banbury1readerseveryonenonreaderswritersdblp.org |
| id_nzKmar_Nporiginalnumbercdatemdateddatetcdatetmdatetddateforum_nzKmar_Npreplytoinvitationdblp.org/-/recordcontentvenueCoRR 2023venueiddblp.org/journals/CORR/2023_bibtex@article{DBLP:journals/corr/abs-2301-11899,\n publtype={informal},\n author={Shvetank Prakash and Matthew Stewart and Colby R. Banbury and Mark Mazumder and Pete Warden and Brian Plancher and Vijay Janapa Reddi},\n title={Is TinyML Sustainable? Assessing the Environmental Impacts of Machine Learning on Microcontrollers},\n year={2023},\n cdate={1672531200000},\n journal={CoRR},\n volume={abs/2301.11899},\n url={https://doi.org/10.48550/arXiv.2301.11899},\n}\nauthorsShvetank PrakashMatthew StewartColby R. BanburyMark MazumderPete WardenBrian PlancherVijay Janapa Reddiauthoridshttps://dblp.org/search/pid/api?q=author:Shvetank_Prakash:https://dblp.org/search/pid/api?q=author:Matthew_Stewart:~Colby_R._Banbury1https://dblp.org/search/pid/api?q=author:Mark_Mazumder:~Pete_Warden2~Brian_Plancher1~Vijay_Janapa_Reddi1htmlhttps://doi.org/10.48550/arXiv.2301.11899titleIs TinyML Sustainable? Assessing the Environmental Impacts of Machine Learning on Microcontrollerspaperhashprakash|is_tinyml_sustainable_assessing_the_environmental_impacts_of_machine_learning_on_microcontrollersabstractThe sustained growth of carbon emissions and global waste elicits significant sustainability concerns for our environment's future. The growing Internet of Things (IoT) has the potential to exacerbate this issue. However, an emerging area known as Tiny Machine Learning (TinyML) has the opportunity to help address these environmental challenges through sustainable computing practices. TinyML, the deployment of machine learning (ML) algorithms onto low-cost, low-power microcontroller systems, enables on-device sensor analytics that unlocks numerous always-on ML applications. This article discusses both the potential of these TinyML applications to address critical sustainability challenges, as well as the environmental footprint of this emerging technology. Through a complete life cycle analysis (LCA), we find that TinyML systems present opportunities to offset their carbon emissions by enabling applications that reduce the emissions of other sectors. Nevertheless, when globally scaled, the carbon footprint of TinyML systems is not negligible, necessitating that designers factor in environmental impact when formulating new devices. Finally, we outline research directions to enable further sustainable contributions of TinyML.", "pdf": "http://arxiv.org/pdf/2301.11899v2"}, "signatures": ["~Colby_Banbury1"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "RAjc2DxwHeP", "original": null, "number": 665449, "cdate": 1640995200000, "pdate": 1640995200000, "mdate": 1682647057405, "ddate": null, "tcdate": 1682647057405, "tmdate": 1692808218615, "tddate": null, "forum": "RAjc2DxwHeP", "replyto": null, "invitation": "dblp.org/-/record", "content": {"venue": "CoNGA 2022", "venueid": "dblp.org/conf/CONGA/2022", "_bibtex": "@inproceedings{DBLP:conf/conga/LangroudiKPMK22,\n author={Hamed Fatemi Langroudi and Vedant Karia and Tej Pandit and Becky Mashaido and Dhireesha Kudithipudi},\n title={ACTION: Automated Hardware-Software Codesign Framework for Low-precision Numerical Format SelecTION in TinyML},\n year={2022},\n cdate={1640995200000},\n pages={50-65},\n url={https://doi.org/10.1007/978-3-031-09779-9_4},\n booktitle={CoNGA},\n crossref={conf/conga/2022},\n}\n", "authors": ["Hamed Fatemi Langroudi", "Vedant Karia", "Tej Pandit", "Becky Mashaido", "Dhireesha Kudithipudi"], "authorids": ["~Hamed_Fatemi1", "https://dblp.org/search/pid/api?q=author:Vedant_Karia:", "https://dblp.org/search/pid/api?q=author:Tej_Pandit:", "https://dblp.org/search/pid/api?q=author:Becky_Mashaido:", "https://dblp.org/search/pid/api?q=author:Dhireesha_Kudithipudi:"], "html": "https://doi.org/10.1007/978-3-031-09779-9_4", "title": "ACTION: Automated Hardware-Software Codesign Framework for Low-precision Numerical Format SelecTION in TinyML", "paperhash": "langroudi|action_automated_hardwaresoftware_codesign_framework_for_lowprecision_numerical_format_selection_in_tinyml", "abstract": "In this paper, a new low-precision hardware-software codesign framework is presented, to optimally select the numerical formats and bit-precision for TinyML models and benchmarks. The selection is performed by integer linear programming using constraints mandated by tiny edge devices. Practitioners can use the proposed framework to reduce design costs in the early stages of designing accelerators for TinyML models. The efficacy of various numerical formats is studied within a new low-precision framework, ACTION. Results assert that generalized posit and tapered fixed are suitable numerical formats for TinyML when the trade-off between accuracy and hardware complexity is desired."}, "signatures": ["~Hamed_Fatemi1"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "Kaqj8z1iWGc", "original": null, "number": 839796, "cdate": 1640995200000, "pdate": 1640995200000, "mdate": 1684337125182, "ddate": null, "tcdate": 1684337125182, "tmdate": 1693236905085, "tddate": null, "forum": "Kaqj8z1iWGc", "replyto": null, "invitation": "dblp.org/-/record", "content": {"venue": "CoRR 2022", "venueid": "dblp.org/journals/CORR/2022", "_bibtex": "@article{DBLP:journals/corr/abs-2203-05492,\n publtype={informal},\n author={Shaojie Zhuo and Hongyu Chen and Ramchalam Kinattinkara Ramakrishnan and Tommy Chen and Chen Feng and Yicheng Lin and Parker Zhang and Liang Shen},\n title={An Empirical Study of Low Precision Quantization for TinyML},\n year={2022},\n cdate={1640995200000},\n journal={CoRR},\n volume={abs/2203.05492},\n url={https://doi.org/10.48550/arXiv.2203.05492},\n}\n", "authors": ["Shaojie Zhuo", "Hongyu Chen", "Ramchalam Kinattinkara Ramakrishnan", "Tommy Chen", "Chen Feng", "Yicheng Lin", "Parker Zhang", "Liang Shen"], "authorids": ["https://dblp.org/search/pid/api?q=author:Shaojie_Zhuo:", "~Hongyu_Chen1", "https://dblp.org/search/pid/api?q=author:Ramchalam_Kinattinkara_Ramakrishnan:", "https://dblp.org/search/pid/api?q=author:Tommy_Chen:", "https://dblp.org/search/pid/api?q=author:Chen_Feng:", "https://dblp.org/search/pid/api?q=author:Yicheng_Lin:", "https://dblp.org/search/pid/api?q=author:Parker_Zhang:", "https://dblp.org/search/pid/api?q=author:Liang_Shen_0007:"], "html": "https://doi.org/10.48550/arXiv.2203.05492", "title": "An Empirical Study of Low Precision Quantization for TinyML", "paperhash": "zhuo|an_empirical_study_of_low_precision_quantization_for_tinyml", "abstract": "Tiny machine learning (tinyML) has emerged during the past few years aiming to deploy machine learning models to embedded AI processors with highly constrained memory and computation capacity. Low precision quantization is an important model compression technique that can greatly reduce both memory consumption and computation cost of model inference. In this study, we focus on post-training quantization (PTQ) algorithms that quantize a model to low-bit (less than 8-bit) precision with only a small set of calibration data and benchmark them on different tinyML use cases. To achieve a fair comparison, we build a simulated quantization framework to investigate recent PTQ algorithms. Furthermore, we break down those algorithms into essential components and re-assembled a generic PTQ pipeline. With ablation study on different alternatives of components in the pipeline, we reveal key design choices when performing low precision quantization. We hope this work could provide useful data points and shed lights on the future research of low precision quantization.", "pdf": "http://arxiv.org/pdf/2203.05492v1"}, "signatures": ["~Hongyu_Chen1"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "Owom9CGC_B0", "original": null, "number": 937288, "cdate": 1672531200000, "pdate": 1672531200000, "mdate": 1699240841715, "ddate": null, "tcdate": 1699240841715, "tmdate": 1709224532480, "tddate": null, "forum": "Owom9CGC_B0", "replyto": null, "invitation": "dblp.org/-/record", "content": {"venue": "CoRR 2023", "venueid": "dblp.org/journals/CORR/2023", "_bibtex": "@article{DBLP:journals/corr/abs-2304-05544,\n publtype={informal},\n author={Andrew Sabot and Vikas Natesh and H. T. Kung and Wei-Te Ting},\n title={MEMA Runtime Framework: Minimizing External Memory Accesses for TinyML on Microcontrollers},\n year={2023},\n cdate={1672531200000},\n journal={CoRR},\n volume={abs/2304.05544},\n url={https://doi.org/10.48550/arXiv.2304.05544},\n}\n", "authors": ["Andrew Sabot", "Vikas Natesh", "H. T. Kung", "Wei-Te Ting"], "authorids": ["~Andrew_Sabot1", "~Vikas_Natesh1", "https://dblp.org/search/pid/api?q=author:H._T._Kung_0001:", "https://dblp.org/search/pid/api?q=author:Wei-Te_Ting:"], "html": "https://doi.org/10.48550/arXiv.2304.05544", "title": "MEMA Runtime Framework: Minimizing External Memory Accesses for TinyML on Microcontrollers", "paperhash": "sabot|mema_runtime_framework_minimizing_external_memory_accesses_for_tinyml_on_microcontrollers", "abstract": "We present the MEMA framework for the easy and quick derivation of efficient inference runtimes that minimize external memory accesses for matrix multiplication on TinyML systems. The framework accounts for hardware resource constraints and problem sizes in analytically determining optimized schedules and kernels that minimize memory accesses. MEMA provides a solution to a well-known problem in the current practice, that is, optimal schedules tend to be found only through a time consuming and heuristic search of a large scheduling space. We compare the performance of runtimes derived from MEMA to existing state-of-the-art libraries on ARM-based TinyML systems. For example, for neural network benchmarks on the ARM Cortex-M4, we achieve up to a 1.8x speedup and 44% energy reduction over CMSIS-NN.", "pdf": "http://arxiv.org/pdf/2304.05544v1"}, "signatures": ["~Vikas_Natesh1"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "0wudOFqbys", "original": null, "number": 925907, "cdate": 1640995200000, "pdate": 1640995200000, "mdate": 1699173145534, "ddate": null, "tcdate": 1699173145534, "tmdate": 1779793445045, "tddate": null, "forum": "0wudOFqbys", "replyto": null, "invitation": "dblp.org/-/record", "content": {"venue": "AIMLSystems 2022", "venueid": "dblp.org/conf/AIML2/2022", "_bibtex": "@inproceedings{DBLP:conf/aiml2/MukherjeeUDK22,\n author={Arijit Mukherjee and Arijit Ukil and Swarnava Dey and Gitesh Kulkarni},\n title={TinyML Techniques for running Machine Learning models on Edge Devices},\n year={2022},\n cdate={1640995200000},\n pages={27:1-27:2},\n url={https://doi.org/10.1145/3564121.3564812},\n booktitle={AIMLSystems},\n crossref={conf/aiml2/2022},\n}\n", "authors": ["Arijit Mukherjee", "Arijit Ukil", "Swarnava Dey", "Gitesh Kulkarni"], "authorids": ["https://dblp.org/search/pid/api?q=author:Arijit_Mukherjee:", "~Arijit_Ukil1", "~Swarnava_Dey1", "https://dblp.org/search/pid/api?q=author:Gitesh_Kulkarni:"], "html": "https://doi.org/10.1145/3564121.3564812", "title": "TinyML Techniques for running Machine Learning models on Edge Devices", "paperhash": "mukherjee|tinyml_techniques_for_running_machine_learning_models_on_edge_devices", "abstract": "Resource-constrained platforms such as micro-controllers are the workhorses in embedded systems, being deployed to capture data from sensors and send the collected data to cloud for processing. Recently, a great interest is seen in the research community and industry to use these devices for performing Artificial Intelligence/Machine Learning (AI/ML) inference tasks in the areas of computer vision, natural language processing, machine monitoring etc. leading to the realization of embedded intelligence at the edge. This task is challenging and needs a significant knowledge of AI/ML applications, algorithms, and computer architecture and their interactions to achieve the desired performance. In this tutorial we cover a few aspects that will help embedded systems designers and AI/ML engineers and scientists to deploy the AI/ML models on the Tiny Edge Devices at an optimum level of performance."}, "signatures": ["~Swarnava_Dey1"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "ofMc9EJNS7S", "original": null, "number": 466762, "cdate": 1609459200000, "mdate": 1668013807898, "ddate": null, "tcdate": 1668013807898, "tmdate": 1741165756211, "tddate": null, "forum": "ofMc9EJNS7S", "replyto": null, "invitation": "dblp.org/-/record", "content": {"venue": "CoRR 2021", "venueid": "dblp.org/journals/CORR/2021", "_bibtex": "@article{DBLP:journals/corr/abs-2110-10486,\n publtype={informal},\n author={Leonardo Ravaglia and Manuele Rusci and Davide Nadalini and Alessandro Capotondi and Francesco Conti and Luca Benini},\n title={A TinyML Platform for On-Device Continual Learning with Quantized Latent Replays},\n year={2021},\n cdate={1609459200000},\n journal={CoRR},\n volume={abs/2110.10486},\n url={https://arxiv.org/abs/2110.10486}\n}\n", "authors": ["Leonardo Ravaglia", "Manuele Rusci", "Davide Nadalini", "Alessandro Capotondi", "Francesco Conti", "Luca Benini"], "authorids": ["https://dblp.org/search/pid/api?q=author:Leonardo_Ravaglia:", "https://dblp.org/search/pid/api?q=author:Manuele_Rusci:", "https://dblp.org/search/pid/api?q=author:Davide_Nadalini:", "~Alessandro_Capotondi1", "https://dblp.org/search/pid/api?q=author:Francesco_Conti_0001:", "~Luca_Benini2"], "html": "https://arxiv.org/abs/2110.10486", "title": "A TinyML Platform for On-Device Continual Learning with Quantized Latent Replays", "paperhash": "ravaglia|a_tinyml_platform_for_ondevice_continual_learning_with_quantized_latent_replays", "abstract": "In the last few years, research and development on Deep Learning models and techniques for ultra-low-power devices in a word, TinyML has mainly focused on a train-then-deploy assumption, with static models that cannot be adapted to newly collected data without cloud-based data collection and fine-tuning. Latent Replay-based Continual Learning (CL) techniques[1] enable online, serverless adaptation in principle, but so farthey have still been too computation and memory-hungry for ultra-low-power TinyML devices, which are typically based on microcontrollers. In this work, we introduce a HW/SW platform for end-to-end CL based on a 10-core FP32-enabled parallel ultra-low-power (PULP) processor. We rethink the baseline Latent Replay CL algorithm, leveraging quantization of the frozen stage of the model and Latent Replays (LRs) to reduce their memory cost with minimal impact on accuracy. In particular, 8-bit compression of the LR memory proves to be almost lossless (-0.26% with 3000LR) compared to the full-precision baseline implementation, but requires 4x less memory, while 7-bit can also be used with an additional minimal accuracy degradation (up to 5%). We also introduce optimized primitives for forward and backward propagation on the PULP processor. Our results show that by combining these techniques, continual learning can be achieved in practice using less than 64MB of memory an amount compatible with embedding in TinyML devices. On an advanced 22nm prototype of our platform, called VEGA, the proposed solution performs onaverage 65x faster than a low-power STM32 L4 microcontroller, being 37x more energy efficient enough for a lifetime of 535h when learning a new mini-batch of data once every minute.", "pdf": "http://arxiv.org/pdf/2110.10486v1"}, "signatures": ["~Luca_Benini2"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "1bfxzyyCn3T", "original": null, "number": 468254, "cdate": 1609459200000, "mdate": 1668013909394, "ddate": null, "tcdate": 1668013909394, "tmdate": 1668998778734, "tddate": null, "forum": "1bfxzyyCn3T", "replyto": null, "invitation": "dblp.org/-/record", "content": {"venue": "CoRR 2021", "venueid": "dblp.org/journals/CORR/2021", "_bibtex": "@article{DBLP:journals/corr/abs-2110-10486,\n publtype={informal},\n author={Leonardo Ravaglia and Manuele Rusci and Davide Nadalini and Alessandro Capotondi and Francesco Conti and Luca Benini},\n title={A TinyML Platform for On-Device Continual Learning with Quantized Latent Replays},\n year={2021},\n cdate={1609459200000},\n journal={CoRR},\n volume={abs/2110.10486},\n url={https://arxiv.org/abs/2110.10486}\n}\n", "authors": ["Leonardo Ravaglia", "Manuele Rusci", "Davide Nadalini", "Alessandro Capotondi", "Francesco Conti", "Luca Benini"], "authorids": ["https://dblp.org/search/pid/api?q=author:Leonardo_Ravaglia:", "https://dblp.org/search/pid/api?q=author:Manuele_Rusci:", "https://dblp.org/search/pid/api?q=author:Davide_Nadalini:", "https://dblp.org/search/pid/api?q=author:Alessandro_Capotondi:", "https://dblp.org/search/pid/api?q=author:Francesco_Conti_0001:", "~Luca_Benini2"], "html": "https://arxiv.org/abs/2110.10486", "title": "A TinyML Platform for On-Device Continual Learning with Quantized Latent Replays", "paperhash": "ravaglia|a_tinyml_platform_for_ondevice_continual_learning_with_quantized_latent_replays", "abstract": "In the last few years, research and development on Deep Learning models and techniques for ultra-low-power devices in a word, TinyML has mainly focused on a train-then-deploy assumption, with static models that cannot be adapted to newly collected data without cloud-based data collection and fine-tuning. Latent Replay-based Continual Learning (CL) techniques[1] enable online, serverless adaptation in principle, but so farthey have still been too computation and memory-hungry for ultra-low-power TinyML devices, which are typically based on microcontrollers. In this work, we introduce a HW/SW platform for end-to-end CL based on a 10-core FP32-enabled parallel ultra-low-power (PULP) processor. We rethink the baseline Latent Replay CL algorithm, leveraging quantization of the frozen stage of the model and Latent Replays (LRs) to reduce their memory cost with minimal impact on accuracy. In particular, 8-bit compression of the LR memory proves to be almost lossless (-0.26% with 3000LR) compared to the full-precision baseline implementation, but requires 4x less memory, while 7-bit can also be used with an additional minimal accuracy degradation (up to 5%). We also introduce optimized primitives for forward and backward propagation on the PULP processor. Our results show that by combining these techniques, continual learning can be achieved in practice using less than 64MB of memory an amount compatible with embedding in TinyML devices. On an advanced 22nm prototype of our platform, called VEGA, the proposed solution performs onaverage 65x faster than a low-power STM32 L4 microcontroller, being 37x more energy efficient enough for a lifetime of 535h when learning a new mini-batch of data once every minute.", "pdf": "http://arxiv.org/pdf/2110.10486v1"}, "signatures": ["~Luca_Benini2"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "1ErETB63t6Y", "original": null, "number": 1011757, "cdate": 1640995200000, "pdate": 1640995200000, "mdate": 1709098853597, "ddate": null, "tcdate": 1709098853597, "tmdate": 1709104182942, "tddate": null, "forum": "1ErETB63t6Y", "replyto": null, "invitation": "dblp.org/-/record", "content": {"venue": "CoRR 2022", "venueid": "dblp.org/journals/CORR/2022", "_bibtex": "@article{DBLP:journals/corr/abs-2204-10546,\n publtype={informal},\n author={Josen Daniel De Leon and Rowel Atienza},\n title={Depth Pruning with Auxiliary Networks for TinyML},\n year={2022},\n cdate={1640995200000},\n journal={CoRR},\n volume={abs/2204.10546},\n url={https://doi.org/10.48550/arXiv.2204.10546},\n}\n", "authors": ["Josen Daniel De Leon", "Rowel Atienza"], "authorids": ["https://dblp.org/search/pid/api?q=author:Josen_Daniel_De_Leon:", "~Rowel_Atienza1"], "html": "https://doi.org/10.48550/arXiv.2204.10546", "title": "Depth Pruning with Auxiliary Networks for TinyML", "paperhash": "leon|depth_pruning_with_auxiliary_networks_for_tinyml", "abstract": "Pruning is a neural network optimization technique that sacrifices accuracy in exchange for lower computational requirements. Pruning has been useful when working with extremely constrained environments in tinyML. Unfortunately, special hardware requirements and limited study on its effectiveness on already compact models prevent its wider adoption. Depth pruning is a form of pruning that requires no specialized hardware but suffers from a large accuracy falloff. To improve this, we propose a modification that utilizes a highly efficient auxiliary network as an effective interpreter of intermediate feature maps. Our results show a parameter reduction of 93% on the MLPerfTiny Visual Wakewords (VWW) task and 28% on the Keyword Spotting (KWS) task with accuracy cost of 0.65% and 1.06% respectively. When evaluated on a Cortex-M0 microcontroller, our proposed method reduces the VWW model size by 4.7x and latency by 1.6x while counter intuitively gaining 1% accuracy. KWS model size on Cortex-M0 was also reduced by 1.2x and latency by 1.2x at the cost of 2.21% accuracy.", "pdf": "http://arxiv.org/pdf/2204.10546v1"}, "signatures": ["~Rowel_Atienza1"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "v52CxI9mZU", "original": null, "number": 467146, "cdate": 1640995200000, "mdate": 1668013816800, "ddate": null, "tcdate": 1668013816800, "tmdate": 1669005501926, "tddate": null, "forum": "v52CxI9mZU", "replyto": null, "invitation": "dblp.org/-/record", "content": {"venue": "COOL CHIPS 2022", "venueid": "dblp.org/conf/COOLCHIPS/2022", "_bibtex": "@inproceedings{DBLP:conf/coolchips/SchererMRFB22,\n author={Moritz Scherer and Alfio Di Mauro and Georg Rutishauser and Tim Fischer and Luca Benini},\n title={A 1036 TOp/s/W, 12.2 mW, 2.72 μJ/Inference All Digital TNN Accelerator in 22 nm FDX Technology for TinyML Applications},\n year={2022},\n cdate={1640995200000},\n pages={1-3},\n url={https://doi.org/10.1109/COOLCHIPS54332.2022.9772668},\n booktitle={COOL CHIPS},\n crossref={conf/coolchips/2022}\n}\n", "authors": ["Moritz Scherer", "Alfio Di Mauro", "Georg Rutishauser", "Tim Fischer", "Luca Benini"], "authorids": ["https://dblp.org/search/pid/api?q=author:Moritz_Scherer:", "https://dblp.org/search/pid/api?q=author:Alfio_Di_Mauro:", "https://dblp.org/search/pid/api?q=author:Georg_Rutishauser:", "https://dblp.org/search/pid/api?q=author:Tim_Fischer:", "~Luca_Benini2"], "html": "https://doi.org/10.1109/COOLCHIPS54332.2022.9772668", "title": "A 1036 TOp/s/W, 12.2 mW, 2.72 μJ/Inference All Digital TNN Accelerator in 22 nm FDX Technology for TinyML Applications", "paperhash": "scherer|a_1036_topsw_122_mw_272_jinference_all_digital_tnn_accelerator_in_22_nm_fdx_technology_for_tinyml_applications", "abstract": "Tiny Machine Learning (TinyML) applications impose μJ/Inference constraints, with maximum power consumption of a few tens of mW. It is extremely challenging to meet these requirement at a reasonable accuracy level. In this work, we address this challenge with a flexible, fully digital Ternary Neural Network (TNN) accelerator in a RISC-V-based SoC. The design achieves 2.72 μJ/Inference, 12.2 mW, 3200 Inferences/sec at 0.5 V for a non-trivial 9-layer, 96 channels-per-layer network with CIFAR-10 accuracy of 86 %. The peak energy efficiency is 1036 TOp/s/W, outperforming the state-of-the-art in silicon-proven TinyML accelerators by 1.67x.", "pdf": "https://ieeexplore.ieee.org/iel7/9772691/9772665/09772668.pdf"}, "signatures": ["~Luca_Benini2"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "ZJe-XahpyBf", "original": "We0AFRSuI-", "number": 1175, "cdate": 1652737312323, "mdate": null, "ddate": null, "tcdate": 1652737312323, "tmdate": 1770510500849, "tddate": null, "forum": "ZJe-XahpyBf", "replyto": null, "invitation": "NeurIPS.cc/2022/Conference/-/Blind_Submission", "content": {"title": "UDC: Unified DNAS for Compressible TinyML Models for Neural Processing Units", "authorids": ["~Igor_Fedorov1", "~Ramon_Matas1", "~Hokchhay_Tann1", "~Chuteng_Zhou1", "~Matthew_Mattina1", "~Paul_Whatmough1"], "authors": ["Igor Fedorov", "Ramon Matas", "Hokchhay Tann", "Chuteng Zhou", "Matthew Mattina", "Paul Whatmough"], "keywords": ["NAS", "compression", "NPU"], "abstract": "Deploying TinyML models on low-cost IoT hardware is very challenging, due to limited device memory capacity. Neural processing unit (NPU) hardware address the memory challenge by using model compression to exploit weight quantization and sparsity to fit more parameters in the same footprint. However, designing compressible neural networks (NNs) is challenging, as it expands the design space across which we must make balanced trade-offs. This paper demonstrates Unified DNAS for Compressible (UDC) NNs, which explores a large search space to generate state-of-the-art compressible NNs for NPU. ImageNet results show UDC networks are up to 3.35x smaller (iso-accuracy) or 6.25% more accurate (iso-model size) than previous work.", "pdf": "/pdf/e8fc860715fc863b27a588dd72126bd5caef831a.pdf", "supplementary_material": "/attachment/767b785dec29394d7adaa9f4c4120948cd94cd15.pdf", "paperhash": "fedorov|udc_unified_dnas_for_compressible_tinyml_models_for_neural_processing_units", "venue": "NeurIPS 2022 Accept", "venueid": "NeurIPS.cc/2022/Conference", "_bibtex": "@inproceedings{\nfedorov2022udc,\ntitle={{UDC}: Unified {DNAS} for Compressible Tiny{ML} Models for Neural Processing Units},\nauthor={Igor Fedorov and Ramon Matas and Hokchhay Tann and Chuteng Zhou and Matthew Mattina and Paul Whatmough},\nbooktitle={Advances in Neural Information Processing Systems},\neditor={Alice H. Oh and Alekh Agarwal and Danielle Belgrave and Kyunghyun Cho},\nyear={2022},\nurl={https://openreview.net/forum?id=ZJe-XahpyBf}\n}", "community_implementations": "[ 2 code implementations](https://www.catalyzex.com/paper/udc-unified-dnas-for-compressible-tinyml/code)"}, "signatures": ["NeurIPS.cc/2022/Conference"], "readers": ["everyone"], "nonreaders": [], "writers": ["NeurIPS.cc/2022/Conference"], "pdate": 1667239200000} |
| {"id": "x83oZBc212", "original": null, "number": 467685, "cdate": 1609459200000, "mdate": 1668013841374, "ddate": null, "tcdate": 1668013841374, "tmdate": 1741165756211, "tddate": null, "forum": "x83oZBc212", "replyto": null, "invitation": "dblp.org/-/record", "content": {"venue": "IEEE J. Emerg. Sel. Topics Circuits Syst. 2021", "venueid": "dblp.org/journals/ESTICAS/2021", "_bibtex": "@article{DBLP:journals/esticas/RavagliaRNCCB21,\n author={Leonardo Ravaglia and Manuele Rusci and Davide Nadalini and Alessandro Capotondi and Francesco Conti and Luca Benini},\n title={A TinyML Platform for On-Device Continual Learning With Quantized Latent Replays},\n year={2021},\n cdate={1609459200000},\n journal={IEEE J. Emerg. Sel. Topics Circuits Syst.},\n volume={11},\n number={4},\n pages={789-802},\n url={https://doi.org/10.1109/JETCAS.2021.3121554}\n}\n", "authors": ["Leonardo Ravaglia", "Manuele Rusci", "Davide Nadalini", "Alessandro Capotondi", "Francesco Conti", "Luca Benini"], "authorids": ["https://dblp.org/search/pid/api?q=author:Leonardo_Ravaglia:", "https://dblp.org/search/pid/api?q=author:Manuele_Rusci:", "https://dblp.org/search/pid/api?q=author:Davide_Nadalini:", "~Alessandro_Capotondi1", "https://dblp.org/search/pid/api?q=author:Francesco_Conti_0001:", "~Luca_Benini2"], "html": "https://doi.org/10.1109/JETCAS.2021.3121554", "title": "A TinyML Platform for On-Device Continual Learning With Quantized Latent Replays", "paperhash": "ravaglia|a_tinyml_platform_for_ondevice_continual_learning_with_quantized_latent_replays", "abstract": "In the last few years, research and development on Deep Learning models & techniques for ultra-low-power devices– in a word, <italic xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\">TinyML</i> – has mainly focused on a <italic xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\">train-then-deploy</i> assumption, with static models that cannot be adapted to newly collected data without cloud-based data collection and fine-tuning. Latent Replay-based Continual Learning (CL) techniques (Pellegrini <italic xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\">et al.</i> , 2020) enable online, serverless adaptation in principle, but so far they have still been too computation- and memory-hungry for ultra-low-power TinyML devices, which are typically based on microcontrollers. In this work, we introduce a HW/SW platform for end-to-end CL based on a 10-core <italic xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\">FP32</i> -enabled parallel ultra-low-power (PULP) processor. We rethink the baseline Latent Replay CL algorithm, leveraging quantization of the frozen stage of the model and Latent Replays (LRs) to reduce their memory cost with minimal impact on accuracy. In particular, 8-bit compression of the LR memory proves to be almost lossless (−0.26% with 3000LR) compared to the full-precision baseline implementation, but requires <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$4\\times $ </tex-math></inline-formula> less memory, while 7-bit can also be used with an additional minimal accuracy degradation (up to 5%). We also introduce optimized primitives for forward and backward propagation on the PULP processor, together with data tiling strategies to fully exploit its memory hierarchy, while maximizing efficiency. Our results show that by combining these techniques, continual learning can be achieved in practice using less than 64MB of memory – an amount compatible with embedding in TinyML devices. On an advanced 22nm prototype of our platform, called <italic xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\">VEGA</i> , the proposed solution performs on average <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$65 \\times $ </tex-math></inline-formula> faster than a low-power STM32 L4 microcontroller, being <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$37\\times $ </tex-math></inline-formula> more energy efficient – enough for a lifetime of 535h when learning a new mini-batch of data once every minute.", "pdf": "https://ieeexplore.ieee.org/iel7/5503868/9647029/09580920.pdf"}, "signatures": ["~Luca_Benini2"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "8RxxwAut1BI", "original": null, "number": 120, "cdate": 1623114411919, "ddate": null, "tcdate": 1623114411919, "tmdate": 1748261625235, "tddate": null, "forum": "8RxxwAut1BI", "replyto": null, "invitation": "NeurIPS.cc/2021/Track/Datasets_and_Benchmarks/Round1/-/Submission", "content": {"title": "MLPerf Tiny Benchmark", "authorids": ["~Colby_Banbury1", "~Vijay_Janapa_Reddi1", "peter.torelli@eembc.org", "njeff@google.com", "csaba.kiraly@digicatapult.org.uk", "~Jeremy_Holleman1", "pietro.montino@gmail.com", "~David_Kanter2", "~Pete_Warden1", "~Danilo_Pau1", "~Urmish_Thakker1", "antonio.torrini@silabs.com", "jay@syntiant.com", "~Giuseppe_Di_Guglielmo1", "~Javier_Duarte1", "honson@latentai.com", "~Nhan_Tran1", "wniu@connect.ust.hk", "xuxs@pcl.ac.cn"], "authors": ["Colby Banbury", "Vijay Janapa Reddi", "Peter Torelli", "Nat Jeffries", "Csaba Kiraly", "Jeremy Holleman", "Pietro Montino", "David Kanter", "Pete Warden", "Danilo Pau", "Urmish Thakker", "antonio torrini", "jay cordaro", "Giuseppe Di Guglielmo", "Javier Duarte", "Honson Tran", "Nhan Tran", "niu wenxu", "xu xuesong"], "keywords": ["Machine learning", "Benchmark", "Embedded", "IoT", "Neural Network", "Ultra-Low-Power"], "TL;DR": "We present MLPerf Tiny, a suite of benchmarks for evaluating the energy, latency, and accuracy of TinyML hardware, models, and runtimes. ", "abstract": "Advancements in ultra-low-power tiny machine learning (TinyML) systems promise to unlock an entirely new class of smart applications. However, continued progress is limited by the lack of a widely accepted and easily reproducible benchmark for these systems. To meet this need, we present MLPerf Tiny, the first industry-standard benchmark suite for ultra-low-power tiny machine learning systems. The benchmark suite is the collaborative effort of more than 50 organizations from industry and academia and reflects the needs of the community. MLPerf Tiny measures the accuracy, latency, and energy of machine learning inference to properly evaluate the tradeoffs between systems. Additionally, MLPerf Tiny implements a modular design that enables benchmark submitters to show the benefits of their product, regardless of where it falls on the ML deployment stack, in a fair and reproducible manner. The suite features four benchmarks: keyword spotting, visual wake words, image classification, and anomaly detection.", "pdf": "/pdf/a34581862e6fcf42b6afd1babbf505ee9ef30779.pdf", "URL": "https://github.com/mlcommons/tiny", "paperhash": "banbury|mlperf_tiny_benchmark", "_bibtex": "@inproceedings{\nbanbury2021mlperf,\ntitle={{MLP}erf Tiny Benchmark},\nauthor={Colby Banbury and Vijay Janapa Reddi and Peter Torelli and Nat Jeffries and Csaba Kiraly and Jeremy Holleman and Pietro Montino and David Kanter and Pete Warden and Danilo Pau and Urmish Thakker and antonio torrini and jay cordaro and Giuseppe Di Guglielmo and Javier Duarte and Honson Tran and Nhan Tran and niu wenxu and xu xuesong},\nbooktitle={Thirty-fifth Conference on Neural Information Processing Systems Datasets and Benchmarks Track (Round 1)},\nyear={2021},\nurl={https://openreview.net/forum?id=8RxxwAut1BI}\n}", "venueid": "NeurIPS.cc/2021/Track/Datasets_and_Benchmarks/Round1", "venue": "NeurIPS 2021 Datasets and Benchmarks Track (Round 1)", "supplementary_material": "/attachment/7db4215ab92683b56da0ce411a9d84b214d1e0ba.zip", "contribution_process_agreement": "Yes", "author_statement": "Yes", "community_implementations": "[ 1 code implementation](https://www.catalyzex.com/paper/mlperf-tiny-benchmark/code)"}, "signatures": ["~Colby_Banbury1"], "readers": ["everyone"], "nonreaders": [], "writers": ["NeurIPS.cc/2021/Track/Datasets_and_Benchmarks/Round1", "~Colby_Banbury1", "~Vijay_Janapa_Reddi1", "peter.torelli@eembc.org", "njeff@google.com", "csaba.kiraly@digicatapult.org.uk", "~Jeremy_Holleman1", "pietro.montino@gmail.com", "~David_Kanter2", "~Pete_Warden1", "~Danilo_Pau1", "~Urmish_Thakker1", "antonio.torrini@silabs.com", "jay@syntiant.com", "~Giuseppe_Di_Guglielmo1", "~Javier_Duarte1", "honson@latentai.com", "~Nhan_Tran1", "wniu@connect.ust.hk", "xuxs@pcl.ac.cn"], "mdate": null, "pdate": 1627570548705, "odate": 1623183911018} |
| {"id": "DbYHSwEaQpE", "original": null, "number": 522744, "cdate": 1640995200000, "mdate": 1668525245586, "ddate": null, "tcdate": 1668525245586, "tmdate": 1691024161037, "tddate": null, "forum": "DbYHSwEaQpE", "replyto": null, "invitation": "dblp.org/-/record", "content": {"venue": "CCRIS 2022", "venueid": "dblp.org/conf/CCRIS/2022", "_bibtex": "@inproceedings{DBLP:conf/ccris/ZhuLHZLDJ22,\n author={Xiangyu Zhu and Rui Li and Jia Hu and Hui Zhang and Qingcai Luo and Qiang Duan and Kai Jiang},\n title={A Guided Task and Obstacle Alert Robot System Based on TinyML and Augmented Reality},\n year={2022},\n cdate={1640995200000},\n pages={225-229},\n url={https://doi.org/10.1145/3562007.3562050},\n booktitle={CCRIS},\n crossref={conf/ccris/2022}\n}\n", "authors": ["Xiangyu Zhu", "Rui Li", "Jia Hu", "Hui Zhang", "Qingcai Luo", "Qiang Duan", "Kai Jiang"], "authorids": ["~Xiangyu_Zhu3", "https://dblp.org/search/pid/api?q=author:Rui_Li:", "https://dblp.org/search/pid/api?q=author:Jia_Hu:", "https://dblp.org/search/pid/api?q=author:Hui_Zhang:", "https://dblp.org/search/pid/api?q=author:Qingcai_Luo:", "https://dblp.org/search/pid/api?q=author:Qiang_Duan:", "https://dblp.org/search/pid/api?q=author:Kai_Jiang:"], "html": "https://doi.org/10.1145/3562007.3562050", "title": "A Guided Task and Obstacle Alert Robot System Based on TinyML and Augmented Reality", "paperhash": "zhu|a_guided_task_and_obstacle_alert_robot_system_based_on_tinyml_and_augmented_reality", "abstract": "Currently, the robot system has been widely applied and rapidly developed. It applies to diverse fields such as service, patrol, life, etc. Most patrol robot systems are based on augmented reality and SLAM to complete guided navigation tasks. The AI system is embedded in the robot for objects detection during the navigation tasks. Since the traditional AI model is computationally intensive at system deployment, it requests special computing devices to support, such as GPUs and TPUs. However, edge devices have too limited memory to run traditional AI models, which significantly limits the application of edge devices. This paper proposed an embedded system based on TinyML approach, which combined an augmented reality robot system with a lightweight AI model so that it can be deployed on edge device or MCU. The goal of this system is to detect the objects during the navigation task and give warning to users to remove obstacle for continuously operating. CCS CONCEPTS • Computer systems organization • Embedded and cyber-physical systems • Robotics"}, "signatures": ["~Xiangyu_Zhu3"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "poVE-vFgMh", "original": null, "number": 901934, "cdate": 1672531200000, "pdate": 1672531200000, "mdate": 1697298721741, "ddate": null, "tcdate": 1697298721741, "tmdate": 1762753111085, "tddate": null, "forum": "poVE-vFgMh", "replyto": null, "invitation": "dblp.org/-/record", "content": {"venue": "CoRR 2023", "venueid": "dblp.org/journals/CORR/2023", "_bibtex": "@article{DBLP:journals/corr/abs-2309-11932,\n publtype={informal},\n author={Luigi Capogrosso and Federico Cunico and Dong Seon Cheng and Franco Fummi and Marco Cristani},\n title={A Machine Learning-oriented Survey on Tiny Machine Learning},\n year={2023},\n cdate={1672531200000},\n journal={CoRR},\n volume={abs/2309.11932},\n url={https://doi.org/10.48550/arXiv.2309.11932},\n}\n", "authors": ["Luigi Capogrosso", "Federico Cunico", "Dong Seon Cheng", "Franco Fummi", "Marco Cristani"], "authorids": [null, "https://dblp.org/search/pid/api?q=author:Federico_Cunico:", "https://dblp.org/search/pid/api?q=author:Dong_Seon_Cheng:", "~Franco_Fummi1", "~Marco_Cristani1"], "html": "https://doi.org/10.48550/arXiv.2309.11932", "title": "A Machine Learning-oriented Survey on Tiny Machine Learning", "paperhash": "capogrosso|a_machine_learningoriented_survey_on_tiny_machine_learning", "abstract": "The emergence of Tiny Machine Learning (TinyML) has positively revolutionized the field of Artificial Intelligence by promoting the joint design of resource-constrained IoT hardware devices and their learning-based software architectures. TinyML carries an essential role within the fourth and fifth industrial revolutions in helping societies, economies, and individuals employ effective AI-infused computing technologies (e.g., smart cities, automotive, and medical robotics). Given its multidisciplinary nature, the field of TinyML has been approached from many different angles: this comprehensive survey wishes to provide an up-to-date overview focused on all the learning algorithms within TinyML-based solutions. The survey is based on the Preferred Reporting Items for Systematic Reviews and Meta-Analyses (PRISMA) methodological flow, allowing for a systematic and complete literature survey. In particular, firstly we will examine the three different workflows for implementing a TinyML-based system, i.e., ML-oriented, HW-oriented, and co-design. Secondly, we propose a taxonomy that covers the learning panorama under the TinyML lens, examining in detail the different families of model optimization and design, as well as the state-of-the-art learning techniques. Thirdly, this survey will present the distinct features of hardware devices and software tools that represent the current state-of-the-art for TinyML intelligent edge applications. Finally, we discuss the challenges and future directions.", "pdf": "http://arxiv.org/pdf/2309.11932v2"}, "signatures": ["~Luigi_Capogrosso1"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "bzUcYfFC-M", "original": null, "number": 629306, "cdate": 1640995200000, "mdate": 1681738197162, "ddate": null, "tcdate": 1681738197162, "tmdate": 1731504589605, "tddate": null, "forum": "bzUcYfFC-M", "replyto": null, "invitation": "dblp.org/-/record", "content": {"venue": "CoRR 2022", "venueid": "dblp.org/journals/CORR/2022", "_bibtex": "@article{DBLP:journals/corr/abs-2212-03332,\n publtype={informal},\n author={Shawn Hymel and Colby R. Banbury and Daniel Situnayake and Alex Elium and Carl Ward and Mat Kelcey and Mathijs Baaijens and Mateusz Majchrzycki and Jenny Plunkett and David Tischler and Alessandro Grande and Louis Moreau and Dmitry Maslov and Artie Beavis and Jan Jongboom and Vijay Janapa Reddi},\n title={Edge Impulse: An MLOps Platform for Tiny Machine Learning},\n year={2022},\n cdate={1640995200000},\n journal={CoRR},\n volume={abs/2212.03332},\n url={https://doi.org/10.48550/arXiv.2212.03332},\n}\n", "authors": ["Shawn Hymel", "Colby R. Banbury", "Daniel Situnayake", "Alex Elium", "Carl Ward", "Mat Kelcey", "Mathijs Baaijens", "Mateusz Majchrzycki", "Jenny Plunkett", "David Tischler", "Alessandro Grande", "Louis Moreau", "Dmitry Maslov", "Artie Beavis", "Jan Jongboom", "Vijay Janapa Reddi"], "authorids": ["https://dblp.org/search/pid/api?q=author:Shawn_Hymel:", "~Colby_R._Banbury1", "https://dblp.org/search/pid/api?q=author:Daniel_Situnayake:", "https://dblp.org/search/pid/api?q=author:Alex_Elium:", "https://dblp.org/search/pid/api?q=author:Carl_Ward:", "https://dblp.org/search/pid/api?q=author:Mat_Kelcey:", "https://dblp.org/search/pid/api?q=author:Mathijs_Baaijens:", "https://dblp.org/search/pid/api?q=author:Mateusz_Majchrzycki:", "https://dblp.org/search/pid/api?q=author:Jenny_Plunkett:", "https://dblp.org/search/pid/api?q=author:David_Tischler:", "https://dblp.org/search/pid/api?q=author:Alessandro_Grande:", "https://dblp.org/search/pid/api?q=author:Louis_Moreau:", "https://dblp.org/search/pid/api?q=author:Dmitry_Maslov:", "https://dblp.org/search/pid/api?q=author:Artie_Beavis:", "https://dblp.org/search/pid/api?q=author:Jan_Jongboom:", "~Vijay_Janapa_Reddi1"], "html": "https://doi.org/10.48550/arXiv.2212.03332", "title": "Edge Impulse: An MLOps Platform for Tiny Machine Learning", "paperhash": "hymel|edge_impulse_an_mlops_platform_for_tiny_machine_learning", "abstract": "Edge Impulse is a cloud-based machine learning operations (MLOps) platform for developing embedded and edge ML (TinyML) systems that can be deployed to a wide range of hardware targets. Current TinyML workflows are plagued by fragmented software stacks and heterogeneous deployment hardware, making ML model optimizations difficult and unportable. We present Edge Impulse, a practical MLOps platform for developing TinyML systems at scale. Edge Impulse addresses these challenges and streamlines the TinyML design cycle by supporting various software and hardware optimizations to create an extensible and portable software stack for a multitude of embedded systems. As of Oct. 2022, Edge Impulse hosts 118,185 projects from 50,953 developers.", "pdf": "http://arxiv.org/pdf/2212.03332v3"}, "signatures": ["~Colby_Banbury1"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "CSQp0XjCMw", "original": null, "number": 704565, "cdate": 1640995200000, "pdate": 1640995200000, "mdate": 1683880108234, "ddate": null, "tcdate": 1683880108234, "tmdate": 1692906183006, "tddate": null, "forum": "CSQp0XjCMw", "replyto": null, "invitation": "dblp.org/-/record", "content": {"venue": "CoRR 2022", "venueid": "dblp.org/journals/CORR/2022", "_bibtex": "@article{DBLP:journals/corr/abs-2210-16556,\n publtype={informal},\n author={Shikhar Jaiswal and Rahul Kiran Kranti Goli and Aayan Kumar and Vivek Seshadri and Rahul Sharma},\n title={MinUn: Accurate ML Inference on Microcontrollers},\n year={2022},\n cdate={1640995200000},\n journal={CoRR},\n volume={abs/2210.16556},\n url={https://doi.org/10.48550/arXiv.2210.16556},\n}\n", "authors": ["Shikhar Jaiswal", "Rahul Kiran Kranti Goli", "Aayan Kumar", "Vivek Seshadri", "Rahul Sharma"], "authorids": ["~Shikhar_Jaiswal1", "https://dblp.org/search/pid/api?q=author:Rahul_Kiran_Kranti_Goli:", "https://dblp.org/search/pid/api?q=author:Aayan_Kumar:", "https://dblp.org/search/pid/api?q=author:Vivek_Seshadri:", "https://dblp.org/search/pid/api?q=author:Rahul_Sharma_0001:"], "html": "https://doi.org/10.48550/arXiv.2210.16556", "title": "MinUn: Accurate ML Inference on Microcontrollers", "paperhash": "jaiswal|minun_accurate_ml_inference_on_microcontrollers", "abstract": "Running machine learning inference on tiny devices, known as TinyML, is an emerging research area. This task requires generating inference code that uses memory frugally, a task that standard ML frameworks are ill-suited for. A deployment framework for TinyML must be a) parametric in the number representation to take advantage of the emerging representations like posits, b) carefully assign high-precision to a few tensors so that most tensors can be kept in low-precision while still maintaining model accuracy, and c) avoid memory fragmentation. We describe MinUn, the first TinyML framework that holistically addresses these issues to generate efficient code for ARM microcontrollers (e.g., Arduino Uno, Due and STM32H747) that outperforms the prior TinyML frameworks.", "pdf": "http://arxiv.org/pdf/2210.16556v2"}, "signatures": ["~Shikhar_Jaiswal1"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "lIcP7auADN", "original": null, "number": 943227, "cdate": 1672531200000, "pdate": 1672531200000, "mdate": 1699277164607, "ddate": null, "tcdate": 1699277164607, "tmdate": 1699288170496, "tddate": null, "forum": "lIcP7auADN", "replyto": null, "invitation": "dblp.org/-/record", "content": {"venue": "CICC 2023", "venueid": "dblp.org/conf/CICC/2023", "_bibtex": "@inproceedings{DBLP:conf/cicc/LinHOWS23,\n author={Chuan-Tung Lin and Paul Xuanyuanliang Huang and Jonghyun Oh and Dewei Wang and Mingoo Seok},\n title={iMCU: A 102-μJ, 61-ms Digital In-Memory Computingbased Microcontroller Unit for Edge TinyML},\n year={2023},\n cdate={1672531200000},\n pages={1-2},\n url={https://doi.org/10.1109/CICC57935.2023.10121221},\n booktitle={CICC},\n crossref={conf/cicc/2023},\n}\n", "authors": ["Chuan-Tung Lin", "Paul Xuanyuanliang Huang", "Jonghyun Oh", "Dewei Wang", "Mingoo Seok"], "authorids": ["https://dblp.org/search/pid/api?q=author:Chuan-Tung_Lin:", "https://dblp.org/search/pid/api?q=author:Paul_Xuanyuanliang_Huang:", "https://dblp.org/search/pid/api?q=author:Jonghyun_Oh:", "https://dblp.org/search/pid/api?q=author:Dewei_Wang:", "~Mingoo_Seok1"], "html": "https://doi.org/10.1109/CICC57935.2023.10121221", "title": "iMCU: A 102-μJ, 61-ms Digital In-Memory Computingbased Microcontroller Unit for Edge TinyML", "paperhash": "lin|imcu_a_102j_61ms_digital_inmemory_computingbased_microcontroller_unit_for_edge_tinyml", "abstract": "TinyML envisions performing a deep neural network (DNN)-based inference on an edge device, which makes it paramount to create a neural microcontroller unit (MCU). Toward this vision, some of the recent MCUs integrated in-memory computing (IMC) based accelerators [1–3]. However, they employ analog-mixed-signal (AMS) versions, exhibiting limited robustness over process, voltage, and temperature (PVT) variations [1–2]. They also employ a large amount of IMC hardware, which increases silicon area and cost. Also, they do not support a practical software dev framework [1–3] such as TensorFlow Lite for Microcontrollers (TFLite-micro) [5]. Because of this, those MCUs did not present the performance for the standard benchmark MLPerf-Tiny [6], which makes it difficult to evaluate them against the state-of-the-art neural MCUs. In this paper, we present $i M C U$, the IMC-based MCU in $28 \\mathrm{~nm}$, which outperforms the current best neural MCU (SiLab’s xG24-DK2601B [6]) by 88X in energy-delay product (EDP) while performing MLPerfTiny. Also, iMCU integrates a digital version of IMC hardware for maximal robustness. We also optimize the acceleration targets and the computation flow to employ the least amount of IMC hardware yet still enable significant acceleration. Hence, iMCU’s total area is only $2.03 \\mathrm{~mm}^{2}$ while integrating $433 \\mathrm{~KB}$ SRAM and $32 \\mathrm{~KB}$ IMC SRAM.", "pdf": "https://ieeexplore.ieee.org/iel7/10121189/10121178/10121221.pdf"}, "signatures": ["~Mingoo_Seok1"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "YJe6hF5EBXH", "original": null, "number": 1, "cdate": 1612535511458, "ddate": null, "tcdate": 1612535511458, "tmdate": 1612735231816, "tddate": null, "forum": "iqcQPOrPcb7", "replyto": "iqcQPOrPcb7", "invitation": "tinyml.org/tinyML/2021/Research_Symposium/Paper1/-/Decision", "content": {"title": "Paper Decision", "decision": "Accept (Regular)", "comment": "Congratulations on your paper's acceptance! \n\nYour paper has been accepted as a full-length regular paper. \n\nPlease read the reviews carefully and make sure the concerns are addressed in your final submission. \n\nAll accepted papers will be given a slot in the TinyML Summit schedule for an oral presentation on Friday, March 26, 2021. \n\nCamera ready instructions will follow soon. All papers will be hosted on arXiv and published papers will have the following header stamp: “Published as a conference paper at TinyML Research Symposium 2021.” The paper will also be presented on the program website. \nsignaturestinyml.org/tinyML/2021/Research_Symposium/Program_Chairsreaderseveryonenonreaderswriterstinyml.org/tinyML/2021/Research_Symposium/Program_ChairsforumContent |
| idb0l2TEugJILoriginalnumbercdateddatetcdatetmdatetddateforumsWpCoxCEHKAreplytosWpCoxCEHKAinvitationtinyml.org/tinyML/2021/Research_Symposium/Paper3/-/DecisioncontenttitlePaper DecisiondecisionAccept (Regular)commentCongratulations on your paper's acceptance! \n\nYour paper has been accepted as a full-length regular paper. \n\nPlease read the reviews carefully and make sure the concerns are addressed in your final submission. \n\nAll accepted papers will be given a slot in the TinyML Summit schedule for an oral presentation on Friday, March 26, 2021. \n\nCamera ready instructions will follow soon. All papers will be hosted on arXiv and published papers will have the following header stamp: “Published as a conference paper at TinyML Research Symposium 2021.” The paper will also be presented on the program website. \n"}, "signatures": ["tinyml.org/tinyML/2021/Research_Symposium/Program_Chairs"], "readers": ["everyone"], "nonreaders": [], "writers": ["tinyml.org/tinyML/2021/Research_Symposium/Program_Chairs"], "forumContent": {"title": "Characterization of Neural Networks Automatically Mapped on Automotive-grade Microcontrollers", "authorids": ["~Danilo_Pau1", "davide.denaro@st.com", "luigi.zambrano@st.com", "crocioni.giulia@gmail.com", "giambattista.gruosso@polimi.it", "giuseppe.di-giore@st.com"], "authors": ["Danilo Pau", "Davide Denaro", "Luigi Zambrano", "Giulia Crocioni", "Giambattista Gruosso", "Giuseppe Di Giore"], "keywords": ["Microcontrollers", "Neural Networks", "LiIon Battery", "Electric Vehicles", "Machine Learning", "embedded software", "CAN networks"], "TL;DR": "Can intrusion detection and battery charge prediction use cases automatically mapped on Automotive grade MCUs", "abstract": "Neural networks and Machine Learning in general, represent today\none of the greatest expectations for the realization of models\nthat can serve to determine the behavior and operation of different\nphysical systems. Undoubtedly the calculation resources necessary\nfor the training and the realization of the model are great especially\nif linked to the amount of data needed to detect the salient parameters\nof the model. At the same time, the models so obtained can be\nintegrated on embedded systems, thanks to TinyML technologies,\nallowing to work exactly where the physical phenomena to analyze\nhappen. In the consumer and industrial world these technologies\nhave taken hold, and are also watched with interest by other sectors\nsuch as the automotiveworld. In this articlewe present a framework\nfor the implementation of models based on neural networks on\nautomotive family microprocessors, demonstrating their efficiency\nin two typical applications of the vehicle world: intrusion detection\non the CAN bus communication network and the determination of\nthe residual capacity of batteries for electric vehicles.", "pdf": "/pdf/4189504b4815b743ab40c927dc4798d2ee9264b0.pdf", "paperhash": "pau|characterization_of_neural_networks_automatically_mapped_on_automotivegrade_microcontrollers", "_bibtex": "@inproceedings{\npau2021characterization,\ntitle={Characterization of Neural Networks Automatically Mapped on Automotive-grade Microcontrollers},\nauthor={Danilo Pau and Davide Denaro and Luigi Zambrano and Giulia Crocioni and Giambattista Gruosso and Giuseppe Di Giore},\nbooktitle={Research Symposium on Tiny Machine Learning},\nyear={2021},\nurl={https://openreview.net/forum?id=sWpCoxCEHKA}\n}", "venueid": "tinyml.org/tinyML/2021/Research_Symposium", "venue": "tinyML 2021 Regular"}} |
| {"id": "5whjM_LpDNz", "original": null, "number": 1, "cdate": 1612536814835, "ddate": null, "tcdate": 1612536814835, "tmdate": 1612735231259, "tddate": null, "forum": "O0kjwqJyhNd", "replyto": "O0kjwqJyhNd", "invitation": "tinyml.org/tinyML/2021/Research_Symposium/Paper5/-/Decision", "content": {"title": "Paper Decision", "decision": "Accept (Regular)", "comment": "Congratulations on your paper's acceptance! \n\nYour paper has been accepted as a full-length regular paper. \n\nPlease read the reviews carefully and make sure the concerns are addressed in your final submission. \n\nAll accepted papers will be given a slot in the TinyML Summit schedule for an oral presentation on Friday, March 26, 2021. \n\nCamera ready instructions will follow soon. All papers will be hosted on arXiv and published papers will have the following header stamp: “Published as a conference paper at TinyML Research Symposium 2021.” The paper will also be presented on the program website. \nsignaturestinyml.org/tinyML/2021/Research_Symposium/Program_Chairsreaderseveryonenonreaderswriterstinyml.org/tinyML/2021/Research_Symposium/Program_ChairsforumContenttitleCompiler Toolchains for Deep Learning Workloads on Embedded Platformsauthorids~Max_Sponner1bernd.waschneck@infineon.comakash.kumar@tu-dresden.deauthorsMax SponnerBernd WaschneckAkash Kumarkeywordsdeep learningembeddeddeep learning compilerembedded deep learningTL;DRA survey of available deep learning compilers as well as an example implementation for a new accelerator device.abstractAs the usage of deep learning becomes increasingly popular in mobile and embedded solutions, it is necessary to convert the framework-specific network representations into executable code for these embedded platforms.\nThis paper starts with a survey and benchmark of the available open source deep learning compiler toolchains, which focuses on the capabilities and performance of the toolchains in regard to targeting embedded microcontrollers that are combined with a dedicated accelerator in a heterogeneous fashion.\nThe second part focuses on the implementation and evaluation of a compilation flow that targets such a solution and reuses one of the existing toolchains to demonstrate the necessary steps for hardware developers to build a software flow for their product.pdf/pdf/4c97f0ea5e9843d685fb53bded2728b59880e1a2.pdfpaperhashsponner|compiler_toolchains_for_deep_learning_workloads_on_embedded_platforms_bibtex@inproceedings{\nsponner2021compiler,\ntitle={Compiler Toolchains for Deep Learning Workloads on Embedded Platforms},\nauthor={Max Sponner and Bernd Waschneck and Akash Kumar},\nbooktitle={Research Symposium on Tiny Machine Learning},\nyear={2021},\nurl={https://openreview.net/forum?id=O0kjwqJyhNd}\n}venueidtinyml.org/tinyML/2021/Research_SymposiumvenuetinyML 2021 Regular |
| idvYS85VSZ-SPoriginalnumbercdateddatetcdatetmdatetddateforumYBFqldo30vGreplytoYBFqldo30vGinvitationtinyml.org/tinyML/2021/Research_Symposium/Paper9/-/DecisioncontenttitlePaper DecisiondecisionAccept (Regular)commentCongratulations on your paper's acceptance! \n\nYour paper has been accepted as a full-length regular paper. \n\nPlease read the reviews carefully and make sure the concerns are addressed in your final submission. \n\nAll accepted papers will be given a slot in the TinyML Summit schedule for an oral presentation on Friday, March 26, 2021. \n\nCamera ready instructions will follow soon. All papers will be hosted on arXiv and published papers will have the following header stamp: “Published as a conference paper at TinyML Research Symposium 2021.” The paper will also be presented on the program website. \n"}, "signatures": ["tinyml.org/tinyML/2021/Research_Symposium/Program_Chairs"], "readers": ["everyone"], "nonreaders": [], "writers": ["tinyml.org/tinyML/2021/Research_Symposium/Program_Chairs"], "forumContent": {"title": "hls4ml: An Open-Source Co-Design Workflow to Empower Scientific Low-Power Machine Learning Devices", "authorids": ["farah@fnal.gov", "bhawks@fnal.gov", "therwig@fnal.gov", "jhirsch@fnal.gov", "sergo@fnal.gov", "~Nhan_Tran1", "~Luca_Carloni1", "~Giuseppe_Di_Guglielmo1", "pcharris@mit.edu", "jkrupa@mit.edu", "drankin@mit.edu", "manuelvalentin2028@u.northwestern.edu", "~Josiah_Hester1", "yingyi.luo@eecs.northwestern.edu", "johnmamish2024@u.northwestern.edu", "~Seda_Memik1", "thea.aarrestad@cern.ch", "hamza.javed@cern.ch", "vladimir.loncar@cern.ch", "maurizio.pierini@cern.ch", "adrian.pol@cern.ch", "sioni@cern.ch", "~Javier_Duarte1", "hauck@uw.edu", "~Shih-Chieh_Hsu1", "jngadiub@caltech.edu", "liu3173@purdue.edu", "dhoang@fnal.gov", "ejkreinar@gmail.com", "zhenbin.wu@cern.ch"], "authors": ["Farah Fahim", "Benjamin Hawks", "Christian Herwig", "James Hirschauer", "Sergo Jindariani", "Nhan Tran", "Luca Carloni", "Giuseppe Di Guglielmo", "Philip Harris", "Jeffrey Krupa", "Dylan Rankin", "Manuel Blanco Valentin", "Josiah Hester", "Yingyi Luo", "John Mamish", "Seda Memik", "Thea Aarrestad", "Hamza Javed", "Vladimir Loncar", "Maurizio Pierini", "Adrian Alan Pol", "Sioni Summers", "Javier Duarte", "Scott Hauck", "Shih-Chieh Hsu", "Jennifer Ngadiuba", "Mia Liu", "Duc Hoang", "Edward Kreinar", "Zhenbin Wu"], "keywords": ["hls4ml", "machine learning", "neural networks", "tinyML", "FPGA", "ASIC", "low-power", "low-latency"], "TL;DR": "We present hls4ml, an open-source software-hardware co-design workflow to translate machine learning algorithms for implementation in FPGAs and ASICs to support science.", "abstract": "Accessible machine learning algorithms, software, and diagnostic tools for energy-efficient devices and systems are extremely valuable across a broad range of application domains. In scientific domains, real-time near-sensor processing can drastically improve experimental design and accelerate scientific discoveries. We have developed hls4ml, an open-source software-hardware co-design workflow to interpret and translate machine learning algorithms for implementation in FPGAs and ASICs specifically to support domain scientists. In this paper, we describe the essential features of the hls4ml workflow including network optimization techniques---such as pruning and quantization-aware training---which can be incorporated naturally into the device implementations. We expand on previous hls4ml work by extending capabilities and techniques towards low-power implementations and increased usability: new Python APIs, quantization-aware pruning, end-to-end FPGA workflows, long pipeline kernels for low power, and new device backends include an ASIC workflow. Taken together, these and continued efforts in hls4ml will arm a new generation of domain scientists with accessible, efficient, and powerful tools for machine-learning-accelerated discovery.", "pdf": "/pdf/569bd9d76f35c4db31d8857ad544898a46fba85e.pdf", "paperhash": "fahim|hls4ml_an_opensource_codesign_workflow_to_empower_scientific_lowpower_machine_learning_devices", "_bibtex": "@inproceedings{\nfahim2021hlsml,\ntitle={hls4ml: An Open-Source Co-Design Workflow to Empower Scientific Low-Power Machine Learning Devices},\nauthor={Farah Fahim and Benjamin Hawks and Christian Herwig and James Hirschauer and Sergo Jindariani and Nhan Tran and Luca Carloni and Giuseppe Di Guglielmo and Philip Harris and Jeffrey Krupa and Dylan Rankin and Manuel Blanco Valentin and Josiah Hester and Yingyi Luo and John Mamish and Seda Memik and Thea Aarrestad and Hamza Javed and Vladimir Loncar and Maurizio Pierini and Adrian Alan Pol and Sioni Summers and Javier Duarte and Scott Hauck and Shih-Chieh Hsu and Jennifer Ngadiuba and Mia Liu and Duc Hoang and Edward Kreinar and Zhenbin Wu},\nbooktitle={Research Symposium on Tiny Machine Learning},\nyear={2021},\nurl={https://openreview.net/forum?id=YBFqldo30vG}\n}", "venueid": "tinyml.org/tinyML/2021/Research_Symposium", "venue": "tinyML 2021 Regular"}} |
| {"id": "GnCtOC1qCAo", "original": null, "number": 1, "cdate": 1612536926141, "ddate": null, "tcdate": 1612536926141, "tmdate": 1612735230525, "tddate": null, "forum": "tuSJVF8lp_h", "replyto": "tuSJVF8lp_h", "invitation": "tinyml.org/tinyML/2021/Research_Symposium/Paper10/-/Decision", "content": {"title": "Paper Decision", "decision": "Accept (Regular)", "comment": "Congratulations on your paper's acceptance! \n\nYour paper has been accepted as a full-length regular paper. \n\nPlease read the reviews carefully and make sure the concerns are addressed in your final submission. \n\nAll accepted papers will be given a slot in the TinyML Summit schedule for an oral presentation on Friday, March 26, 2021. \n\nCamera ready instructions will follow soon. All papers will be hosted on arXiv and published papers will have the following header stamp: “Published as a conference paper at TinyML Research Symposium 2021.” The paper will also be presented on the program website. \nsignaturestinyml.org/tinyML/2021/Research_Symposium/Program_Chairsreaderseveryonenonreaderswriterstinyml.org/tinyML/2021/Research_Symposium/Program_ChairsforumContenttitleQuantization-Guided Training for Compact TinyML Modelsauthorids~Sek_M._Chai1authorsSek M. Chaikeywordsdeep learningquantizationvisual wakeupTL;DRWe propose a training method to produce tinyML models below 8-bit precision, with benchmark results for visual wakeup systems.abstractWe address the methodology to train and quantize deep neural networks (DNNs) in order to produce compact models while maintaining algorithmic accuracy. In this paper, we propose a Quantization Guided Training (QGT) method to guide DNN training towards optimized low-bit-precision targets, and reach extreme compression levels below 8-bit precision. Unlike standard quantization-aware training (QAT) approaches, QGT uses customized regularization to encourage weight values towards a distribution that maximizes accuracy while reducing quantization errors. We validate QGT using state-of-the-art model architectures (MobileNet, ResNet) on vision datasets. We also demonstrate the effectiveness with an 81KB tiny model for person detection down to 2-bit precision (representing 17.7x size reduction), while maintaining an accuracy drop of only 3\\% compared to a floating-point baseline. pdf/pdf/9ca076693c0f443413e0608b95058a68a4430b95.pdfpaperhashchai|quantizationguided_training_for_compact_tinyml_models_bibtex@inproceedings{\nchai2021quantizationguided,\ntitle={Quantization-Guided Training for Compact Tiny{\\{}ML{\\}} Models},\nauthor={Sek M. Chai},\nbooktitle={Research Symposium on Tiny Machine Learning},\nyear={2021},\nurl={https://openreview.net/forum?id=tuSJVF8lp_h}\n}venueidtinyml.org/tinyML/2021/Research_SymposiumvenuetinyML 2021 Regular |
| id_jFyIUsOebBoriginalnumbercdateddatetcdatetmdatetddateforumgddOffMRWE3replytogddOffMRWE3invitationtinyml.org/tinyML/2021/Research_Symposium/Paper11/-/DecisioncontenttitlePaper DecisiondecisionAccept (Regular)commentCongratulations on your paper's acceptance! \n\nYour paper has been accepted as a full-length regular paper. \n\nPlease read the reviews carefully and make sure the concerns are addressed in your final submission. \n\nAll accepted papers will be given a slot in the TinyML Summit schedule for an oral presentation on Friday, March 26, 2021. \n\nCamera ready instructions will follow soon. All papers will be hosted on arXiv and published papers will have the following header stamp: “Published as a conference paper at TinyML Research Symposium 2021.” The paper will also be presented on the program website. \n"}, "signatures": ["tinyml.org/tinyML/2021/Research_Symposium/Program_Chairs"], "readers": ["everyone"], "nonreaders": [], "writers": ["tinyml.org/tinyML/2021/Research_Symposium/Program_Chairs"], "forumContent": {"title": "Memory-Efficient, Limb Position-Aware Hand Gesture Recognition using Hyperdimensional Computing", "authorids": ["~Andy_Zhou1", "~Rikky_Muller1", "~Jan_Rabaey1"], "authors": ["Andy Zhou", "Rikky Muller", "Jan Rabaey"], "keywords": ["hyperdimensional computing", "gesture recognition", "multi-context classification"], "TL;DR": "Sensor fusion enables memory-efficient storage of hyperdimensional computing classification parameters for gesture recognition in multiple limb positions.", "abstract": "Electromyogram (EMG) pattern recognition can be used to classify hand gestures and movements for human-machine interface and prosthetics applications, but it often faces reliability issues resulting from limb position change. One method to address this is dual-stage classification, in which the limb position is first determined using additional sensors to select between multiple position-specific gesture classifiers. While improving performance, this also increases model complexity and memory footprint, making a dual-stage classifier difficult to implement in a wearable device with limited resources. In this paper, we present sensor fusion of accelerometer and EMG signals using a hyperdimensional computing model to emulate dual-stage classification in a memory-efficient way. We demonstrate two methods of encoding accelerometer features to act as keys for retrieval of position-specific parameters from multiple models stored in superposition. Through validation on a dataset of 13 gestures in 8 limb positions, we obtain a classification accuracy of up to $93.34\\%$, an improvement of $17.79\\%$ over using a model trained solely on EMG. We achieve this while only marginally increasing memory footprint over a single limb position model, requiring $8\\times$ less memory than a traditional dual-stage classification architecture.", "pdf": "/pdf/c53cc34a2776ecea8ddbc14e7c7f5efcd17ad164.pdf", "paperhash": "zhou|memoryefficient_limb_positionaware_hand_gesture_recognition_using_hyperdimensional_computing", "_bibtex": "@inproceedings{\nzhou2021memoryefficient,\ntitle={Memory-Efficient, Limb Position-Aware Hand Gesture Recognition using Hyperdimensional Computing},\nauthor={Andy Zhou and Rikky Muller and Jan Rabaey},\nbooktitle={Research Symposium on Tiny Machine Learning},\nyear={2021},\nurl={https://openreview.net/forum?id=gddOffMRWE3}\n}", "venueid": "tinyml.org/tinyML/2021/Research_Symposium", "venue": "tinyML 2021 Regular"}} |
| {"id": "-la7zex2xng", "original": null, "number": 1, "cdate": 1612536971821, "ddate": null, "tcdate": 1612536971821, "tmdate": 1612735230107, "tddate": null, "forum": "JGNDej3tup9", "replyto": "JGNDej3tup9", "invitation": "tinyml.org/tinyML/2021/Research_Symposium/Paper13/-/Decision", "content": {"title": "Paper Decision", "decision": "Accept (Regular)", "comment": "Congratulations on your paper's acceptance! \n\nYour paper has been accepted as a full-length regular paper. \n\nPlease read the reviews carefully and make sure the concerns are addressed in your final submission. \n\nAll accepted papers will be given a slot in the TinyML Summit schedule for an oral presentation on Friday, March 26, 2021. \n\nCamera ready instructions will follow soon. All papers will be hosted on arXiv and published papers will have the following header stamp: “Published as a conference paper at TinyML Research Symposium 2021.” The paper will also be presented on the program website. \nsignaturestinyml.org/tinyML/2021/Research_Symposium/Program_Chairsreaderseveryonenonreaderswriterstinyml.org/tinyML/2021/Research_Symposium/Program_ChairsforumContent |
| idG0MheA2sL6originalnumbercdateddatetcdatetmdatetddateforumLYzEISv1brereplytoLYzEISv1breinvitationtinyml.org/tinyML/2021/Research_Symposium/Paper18/-/DecisioncontenttitlePaper DecisiondecisionAccept (Regular)commentCongratulations on your paper's acceptance! \n\nYour paper has been accepted as a full-length regular paper. \n\nPlease read the reviews carefully and make sure the concerns are addressed in your final submission. \n\nAll accepted papers will be given a slot in the TinyML Summit schedule for an oral presentation on Friday, March 26, 2021. \n\nCamera ready instructions will follow soon. All papers will be hosted on arXiv and published papers will have the following header stamp: “Published as a conference paper at TinyML Research Symposium 2021.” The paper will also be presented on the program website. \n"}, "signatures": ["tinyml.org/tinyML/2021/Research_Symposium/Program_Chairs"], "readers": ["everyone"], "nonreaders": [], "writers": ["tinyml.org/tinyML/2021/Research_Symposium/Program_Chairs"], "forumContent": {}} |
| {"id": "eI8SKO3cAl", "original": null, "number": 1, "cdate": 1612537068748, "ddate": null, "tcdate": 1612537068748, "tmdate": 1612735229122, "tddate": null, "forum": "gcaV8J8pQrx", "replyto": "gcaV8J8pQrx", "invitation": "tinyml.org/tinyML/2021/Research_Symposium/Paper20/-/Decision", "content": {"title": "Paper Decision", "decision": "Accept (Regular)", "comment": "Congratulations on your paper's acceptance! \n\nYour paper has been accepted as a full-length regular paper. \n\nPlease read the reviews carefully and make sure the concerns are addressed in your final submission. \n\nAll accepted papers will be given a slot in the TinyML Summit schedule for an oral presentation on Friday, March 26, 2021. \n\nCamera ready instructions will follow soon. All papers will be hosted on arXiv and published papers will have the following header stamp: “Published as a conference paper at TinyML Research Symposium 2021.” The paper will also be presented on the program website. \nsignaturestinyml.org/tinyML/2021/Research_Symposium/Program_Chairsreaderseveryonenonreaderswriterstinyml.org/tinyML/2021/Research_Symposium/Program_ChairsforumContenttitleSmartphone Impostor Detection with Behavioral Data Privacy and Minimalist Hardware Supportauthorids~Guangyuan_Hu1~Zecheng_He1~Ruby_B._Lee1authorsGuangyuan HuZecheng HeRuby B. LeekeywordsAnomaly detectiondeep learninghardware acceleratorsecurityTL;DRPrivacy-preserving impostor detection with deep learning and the hardware support.abstractImpostors are attackers who take over a smartphone and gain access to the legitimate user's confidential and private information. This paper proposes a defense-in-depth mechanism that can detect impostors quickly with simple Deep Learning algorithms, which can achieve better detection accuracy than the best prior work which used Machine Learning algorithms requiring computation of multiple features. Different from previous work, we then consider protecting the privacy of a user's behavioral (sensor) data by not exposing it outside the smartphone. For this scenario, we propose a Recurrent Neural Network (RNN) based Deep Learning algorithm that uses only the legitimate user's sensor data to learn his/her normal behavior. We propose to use Prediction Error Distribution (PED) to enhance the detection accuracy. To make the on-device, real-time detection possible, we show how a minimalist hardware module, dubbed SID for Smartphone Imposter Detector, can be designed and integrated into smartphones for self-contained impostor detection. Experimental results show that SID can support real-time impostor detection, at a very low hardware cost and energy consumption, compared to other RNN accelerators.", "pdf": "/pdf/6d4d3b33f10d8c1930ee81ff017dbaf6c9f649c5.pdf", "paperhash": "hu|smartphone_impostor_detection_with_behavioral_data_privacy_and_minimalist_hardware_support", "_bibtex": "@inproceedings{\nhu2021smartphone,\ntitle={Smartphone Impostor Detection with Behavioral Data Privacy and Minimalist Hardware Support},\nauthor={Guangyuan Hu and Zecheng He and Ruby B. Lee},\nbooktitle={Research Symposium on Tiny Machine Learning},\nyear={2021},\nurl={https://openreview.net/forum?id=gcaV8J8pQrx}\n}", "venueid": "tinyml.org/tinyML/2021/Research_Symposium", "venue": "tinyML 2021 Regular"}} |
| {"id": "T0xhOeqsyNZ", "original": null, "number": 1, "cdate": 1612537098736, "ddate": null, "tcdate": 1612537098736, "tmdate": 1612735228847, "tddate": null, "forum": "TeRZyNF9anM", "replyto": "TeRZyNF9anM", "invitation": "tinyml.org/tinyML/2021/Research_Symposium/Paper22/-/Decision", "content": {"title": "Paper Decision", "decision": "Accept (Regular)", "comment": "Congratulations on your paper's acceptance! \n\nYour paper has been accepted as a full-length regular paper. \n\nPlease read the reviews carefully and make sure the concerns are addressed in your final submission. \n\nAll accepted papers will be given a slot in the TinyML Summit schedule for an oral presentation on Friday, March 26, 2021. \n\nCamera ready instructions will follow soon. All papers will be hosted on arXiv and published papers will have the following header stamp: “Published as a conference paper at TinyML Research Symposium 2021.” The paper will also be presented on the program website. \nsignaturestinyml.org/tinyML/2021/Research_Symposium/Program_Chairsreaderseveryonenonreaderswriterstinyml.org/tinyML/2021/Research_Symposium/Program_ChairsforumContenttitleSWIS - Shared Weight bIt Sparsity for Efficient Neural Network Accelerationauthorids~Shurui_Li1~Wojciech_Romaszkan1agraening@ucla.edu~Puneet_Gupta1authorsShurui LiWojciech RomaszkanAlexander GraeningPuneet Guptakeywordsmachine learningacceleratorsneural networksquantizationTL;DRSWIS - a methodology for more efficient neural network quantization and execution on bit-serial accelerators.abstractQuantization is spearheading the increase in performance and efficiency of neural network computing systems making headway into commodity hardware. We present SWIS - Shared Weight bIt Sparsity, a quantization framework for efficient neural network inference acceleration delivering improved performance and storage compression through an offline weight decomposition and scheduling algorithm. SWIS can achieve up to 52% (19.8%) point accuracy improvement when quantizing MobileNet-v2 to 4 (2) bits post-training (with retraining) showing the strength of leveraging shared bit-sparsity in weights. SWIS accelerator gives up to 6X speedup and 1.8X energy improvement over state of the art bit-serial architectures. pdf/pdf/5493ae686b17e1657ae31e342fb4b9750e13a4d2.pdfpaperhashli|swis_shared_weight_bit_sparsity_for_efficient_neural_network_acceleration_bibtex@inproceedings{\nli2021swis,\ntitle={{\\{}SWIS{\\}} - Shared Weight bIt Sparsity for Efficient Neural Network Acceleration},\nauthor={Shurui Li and Wojciech Romaszkan and Alexander Graening and Puneet Gupta},\nbooktitle={Research Symposium on Tiny Machine Learning},\nyear={2021},\nurl={https://openreview.net/forum?id=TeRZyNF9anM}\n}venueidtinyml.org/tinyML/2021/Research_SymposiumvenuetinyML 2021 Regular |
| idXQn7VUP9RJzoriginalnumbercdatemdateddatetcdatetmdatetddateforumXQn7VUP9RJzreplytoinvitationdblp.org/-/recordcontentvenueCoRR 2022venueiddblp.org/journals/CORR/2022_bibtex@article{DBLP:journals/corr/abs-2203-04737,\n publtype={informal},\n author={Gourav Datta and Souvik Kundu and Zihan Yin and Ravi Teja Lakkireddy and Joe Mathai and Ajey Jacob and Peter A. Beerel and Akhilesh R. Jaiswal},\n title={P2M: A Processing-in-Pixel-in-Memory Paradigm for Resource-Constrained TinyML Applications},\n year={2022},\n cdate={1640995200000},\n journal={CoRR},\n volume={abs/2203.04737},\n url={https://doi.org/10.48550/arXiv.2203.04737},\n}\nauthorsGourav DattaSouvik KunduZihan YinRavi Teja LakkireddyJoe MathaiAjey JacobPeter A. BeerelAkhilesh R. Jaiswalauthoridshttps://dblp.org/search/pid/api?q=author:Gourav_Datta:https://dblp.org/search/pid/api?q=author:Souvik_Kundu_0002:https://dblp.org/search/pid/api?q=author:Zihan_Yin:https://dblp.org/search/pid/api?q=author:Ravi_Teja_Lakkireddy:~Joe_Mathai1https://dblp.org/search/pid/api?q=author:Ajey_Jacob:~Peter_A._Beerel1https://dblp.org/search/pid/api?q=author:Akhilesh_R._Jaiswal:htmlhttps://doi.org/10.48550/arXiv.2203.04737titleP2M: A Processing-in-Pixel-in-Memory Paradigm for Resource-Constrained TinyML Applicationspaperhashdatta|p2m_a_processinginpixelinmemory_paradigm_for_resourceconstrained_tinyml_applicationsabstractThe demand to process vast amounts of data generated from state-of-the-art high resolution cameras has motivated novel energy-efficient on-device AI solutions. Visual data in such cameras are usually captured in the form of analog voltages by a sensor pixel array, and then converted to the digital domain for subsequent AI processing using analog-to-digital converters (ADC). Recent research has tried to take advantage of massively parallel low-power analog/digital computing in the form of near- and in-sensor processing, in which the AI computation is performed partly in the periphery of the pixel array and partly in a separate on-board CPU/accelerator. Unfortunately, high-resolution input images still need to be streamed between the camera and the AI processing unit, frame by frame, causing energy, bandwidth, and security bottlenecks. To mitigate this problem, we propose a novel Processing-in-Pixel-in-memory (P2M) paradigm, that customizes the pixel array by adding support for analog multi-channel, multi-bit convolution, batch normalization, and ReLU (Rectified Linear Units). Our solution includes a holistic algorithm-circuit co-design approach and the resulting P2M paradigm can be used as a drop-in replacement for embedding memory-intensive first few layers of convolutional neural network (CNN) models within foundry-manufacturable CMOS image sensor platforms. Our experimental results indicate that P2M reduces data transfer bandwidth from sensors and analog to digital conversions by ~21x, and the energy-delay product (EDP) incurred in processing a MobileNetV2 model on a TinyML use case for visual wake words dataset (VWW) by up to ~11x compared to standard near-processing or in-sensor implementations, without any significant drop in test accuracy.pdfhttp://arxiv.org/pdf/2203.04737v2signatures~Joe_Mathai1readerseveryonenonreaderswritersdblp.org |
| idfD4t1rsc3XoriginalnumbercdatepdatemdateddatetcdatetmdatetddateforumfD4t1rsc3Xreplytoinvitationdblp.org/-/recordcontentvenueCoRR 2021venueiddblp.org/journals/CORR/2021_bibtex@article{DBLP:journals/corr/abs-2110-01107,\n publtype={informal},\n author={Kavya Kopparapu and Eric Lin},\n title={TinyFedTL: Federated Transfer Learning on Tiny Devices},\n year={2021},\n cdate={1609459200000},\n journal={CoRR},\n volume={abs/2110.01107},\n url={https://arxiv.org/abs/2110.01107},\n}\nauthorsKavya KopparapuEric Linauthoridshttps://dblp.org/search/pid/api?q=author:Kavya_Kopparapu:~Eric_Lin1htmlhttps://arxiv.org/abs/2110.01107titleTinyFedTL: Federated Transfer Learning on Tiny Devicespaperhashkopparapu|tinyfedtl_federated_transfer_learning_on_tiny_devicesabstractTinyML has rose to popularity in an era where data is everywhere. However, the data that is in most demand is subject to strict privacy and security guarantees. In addition, the deployment of TinyML hardware in the real world has significant memory and communication constraints that traditional ML fails to address. In light of these challenges, we present TinyFedTL, the first implementation of federated transfer learning on a resource-constrained microcontroller.pdfhttp://arxiv.org/pdf/2110.01107v1signatures~Eric_Lin1readerseveryonenonreaderswritersdblp.org |
| idKCLjPbvV-qoriginalnumbercdatemdateddatetcdatetmdatetddateforum9RQh6MOOaDreplyto9RQh6MOOaDinvitationICLR.cc/2023/Conference/Paper630/-/Public_CommentcontenttitleA Comment On HDC Dimension Reduction TopiccommentGlad to see a work improving HDC performance! We are also researching similar topics, and recently published our findings in tinyML'22 [1], in which we successfully reduced the dimensions of HDC by orders of magnitude (e.g., 4/64 for MNIST dataset), yet why we name it as Low Dimensional Computing or LDC. Specially, our LDC projects the classic HDC process to BNN structure, and it can retain all efficiency that HDC has during inference, as well as the accuracy. You are welcome to discuss any considerations with us.\n\n[1] Shijin Duan, Xiaolin Xu, and Shaolei Ren. A brain-inspired low-dimensional computing classifier for inference on tiny devices. In tinyML Research Symposium 2022, 2022."}, "signatures": ["~Shijin_Duan1"], "readers": ["everyone"], "nonreaders": [], "writers": ["ICLR.cc/2023/Conference", "~Shijin_Duan1"], "forumContent": {}} |
| {"id": "N7RIhEOalVK", "original": null, "number": 2, "cdate": 1659459410694, "ddate": null, "tcdate": 1659459410694, "tmdate": 1659466790271, "tddate": null, "forum": "zGvRdBW06F5", "replyto": "P5n4a2nqXk4", "invitation": "NeurIPS.cc/2022/Conference/Paper2198/-/Official_Comment", "content": {"title": "Author Response", "comment": "We thank the reviewer very much for the positive comments and insightful suggestions.\n\n**Q1: The necessity of on-device training and its applications. Compare training on the cloud and update the parameters locally.**\n\nOn-device training has a broad range of applications: it can customize the deep learning models for personalized use cases. For example, Google uses on-device learning to improve the smart keyboard prediction; voice assistants like Alexa and Siri can adapt to different users’ accents; cameras can continually recognize more objects to facilitate smart home and smart manufacturing.\n\nOn-device training also has unique advantages. Firstly, it can protect users’ privacy by keeping data locally, especially for sensitive scenarios like healthcare. Secondly, it reduces the data transfer cost and cloud operating cost (which could be huge considering the billions of IoT devices in our daily life). Thirdly, it enables new learning paradigms like life-long learning and federated learning.\n\nOn the contrary, uploading the data to the cloud for training can lead to serious privacy and security issues. It may not be feasible as the regularizations become more strict (e.g., the EU’s GDPR makes it very difficult to collect user data in a centralized cloud for training). It also leads to higher cloud operating costs. Therefore, we believe efficient on-device learning has unique advantages and will enable various novel applications.\n\n**Q2: Is the training time reasonable for on-device learning applications?**\n\nOur framework can enable practical on-device training applications even on a small microcontroller with limited computation capacity. We have built a video demo (see [here]([https://drive.google.com/drive/folders/1E0MU7rPHy7NbnlZDKVAIGuN1TTwogF9U?usp=sharing](https://drive.google.com/drive/folders/1E0MU7rPHy7NbnlZDKVAIGuN1TTwogF9U?usp=sharing)) and the supplementary Section A) showing that we can transfer a model to a new target task (Visual Wake Words) within only 200 seconds (which could be further reduced by 3x if we make a good synchronization).\n\nFor the detailed timing breakdown of finetuning MobileNetV2-w0.35, we need 325ms to train on one sample. For tinyML applications, we usually need a small number of samples (e.g., <100) to recognize an object, so the total training time is quite acceptable (within minutes). For lifelong learning settings, the training on streaming new data is amortized during a very long period, so the training cost for a certain period is still very affordable.\n\nWe also compare the training time for the same workload with a cloud GPU NVIDIA GeForce RTX 3090 using PyTorch, and it takes 20.4ms to train on one sample, which is an order of magnitude faster than our tinyML setting. However, the GPU power is 350W, **three orders of magnitude** higher than microcontrollers (360mW), which is not suitable for tinyML. Given the modest total training time analyzed above, we believe our framework can enable a vast range of realistic low-power on-device training applications.\n\n**Q3: The choice of the used neural network structures.**\n\nOur proposed techniques do not rely on a specific model architecture. They are **general techniques** and can be applied to different CNN model architectures. We chose the three network architectures since they are widely used vision models in tinyML settings. For example, the MCUNet model [45] achieves state-of-the-art accuracy for tinyML applications, outperforming other network architectures in terms of accuracy vs. memory tradeoff. Note that to be friendly for quantization and deployment, the three models do not have attention blocks or Swish activation functions.\n"}, "signatures": ["NeurIPS.cc/2022/Conference/Paper2198/Authors"], "readers": ["everyone"], "nonreaders": [], "writers": ["NeurIPS.cc/2022/Conference", "NeurIPS.cc/2022/Conference/Paper2198/Authors"], "forumContent": {}} |
| {"id": "0yzyBY_tbuX", "original": null, "number": 1, "cdate": 1612536891731, "ddate": null, "tcdate": 1612536891731, "tmdate": 1612735231402, "tddate": null, "forum": "_Qtnx5BY6ZT", "replyto": "_Qtnx5BY6ZT", "invitation": "tinyml.org/tinyML/2021/Research_Symposium/Paper4/-/Decision", "content": {"title": "Paper Decision", "decision": "Accept (Poster)", "comment": "Based on the reviewer feedback, your paper has been accepted as a poster.\n\nPlease read the reviews carefully and make sure the concerns are addressed in your poster submission. \n\nAccepted posters are given a 5-minute slot for an oral presentation on Friday, March 26, 2021, to pitch the main ideas of your work and to stimulate discussions. Detailed instructions will follow soon. All final posters will earn a stamp of acceptance as such: “Published as a poster at TinyML Research Symposium 2021.”\n"}, "signatures": ["tinyml.org/tinyML/2021/Research_Symposium/Program_Chairs"], "readers": ["everyone"], "nonreaders": [], "writers": ["tinyml.org/tinyML/2021/Research_Symposium/Program_Chairs"], "forumContent": {"title": "An Ultra-low Power RNN Classifier for Always-On Voice Wake- Up Detection Robust to Real-World Scenarios", "authorids": ["~Emmanuel_Hardy1", "franck.badets@cea.fr"], "authors": ["Emmanuel Hardy", "Franck Badets"], "keywords": ["Voice Activity Detection (VAD)", "Wake-Up Sensor", "Recurrent Neural Network (RNN)", "Gated Recurrent Unit (GRU)", "Machine Learning", "Internet of Things (IoT)", "Ultra Low Power", "Approximate Quantization", "ASIC"], "TL;DR": "We show the superiority of RNNs as ultra-low power classifiers for Voice Wake-Up tasks in terms of detection performance, robustness to unseen noises and low complexity.", "abstract": "We present in this paper an ultra-low power (ULP) Recurrent Neural Network (RNN) based classifier for an always-on voice Wake-Up Sensor (WUS) with performances suitable for real-world applications. The purpose of our sensor is to bring down by at least a factor 100 the power consumption in background noise of always-on speech processing algorithms such as Automatic Speech Recognition, Keyword Spotting, Speaker Verification, etc. Unlike the other published approaches, we designed our wake-up sensor to be robust to unseen real-world noises for realistic levels of speech and noise by carefully designing the dataset and the loss function. We also specifically trained it to mark only the speech start rather than adopting a traditional Voice Activity Detection (VAD) approach. We achieve less than 3% No Trigger Rate (NTR) for a duty cycle less than 1% in challenging background noises pooled. We demonstrate the superiority of RNNs on this task compared to the other tested approaches, with an estimated power consumption of 30 nW in 65nm CMOS and a minimal memory footprint of 0.52 kB.", "pdf": "/pdf/6d9cb0cd863b7d9fa6991283519e197f54539b7d.pdf", "paperhash": "hardy|an_ultralow_power_rnn_classifier_for_alwayson_voice_wake_up_detection_robust_to_realworld_scenarios", "_bibtex": "@inproceedings{\nhardy2021an,\ntitle={An Ultra-low Power {\\{}RNN{\\}} Classifier for Always-On Voice Wake- Up Detection Robust to Real-World Scenarios},\nauthor={Emmanuel Hardy and Franck Badets},\nbooktitle={Research Symposium on Tiny Machine Learning},\nyear={2021},\nurl={https://openreview.net/forum?id=_Qtnx5BY6ZT}\n}", "venueid": "tinyml.org/tinyML/2021/Research_Symposium", "venue": "tinyML 2021 Poster"}} |
| {"id": "z_5qhwetMD", "original": null, "number": 1, "cdate": 1612536832707, "ddate": null, "tcdate": 1612536832707, "tmdate": 1612735231121, "tddate": null, "forum": "L37gp2avJVu", "replyto": "L37gp2avJVu", "invitation": "tinyml.org/tinyML/2021/Research_Symposium/Paper6/-/Decision", "content": {"title": "Paper Decision", "decision": "Accept (Poster)", "comment": "Based on the reviewer feedback, your paper has been accepted as a poster.\n\nPlease read the reviews carefully and make sure the concerns are addressed in your poster submission. \n\nAccepted posters are given a 5-minute slot for an oral presentation on Friday, March 26, 2021, to pitch the main ideas of your work and to stimulate discussions. Detailed instructions will follow soon. All final posters will earn a stamp of acceptance as such: “Published as a poster at TinyML Research Symposium 2021.”\n"}, "signatures": ["tinyml.org/tinyML/2021/Research_Symposium/Program_Chairs"], "readers": ["everyone"], "nonreaders": [], "writers": ["tinyml.org/tinyML/2021/Research_Symposium/Program_Chairs"], "forumContent": {}} |
| {"id": "USCgpJIdaM5", "original": null, "number": 1, "cdate": 1612536864345, "ddate": null, "tcdate": 1612536864345, "tmdate": 1612735230812, "tddate": null, "forum": "zEJDxAKKiat", "replyto": "zEJDxAKKiat", "invitation": "tinyml.org/tinyML/2021/Research_Symposium/Paper8/-/Decision", "content": {"title": "Paper Decision", "decision": "Accept (Poster)", "comment": "Based on the reviewer feedback, your paper has been accepted as a poster.\n\nPlease read the reviews carefully and make sure the concerns are addressed in your poster submission. \n\nAccepted posters are given a 5-minute slot for an oral presentation on Friday, March 26, 2021, to pitch the main ideas of your work and to stimulate discussions. Detailed instructions will follow soon. All final posters will earn a stamp of acceptance as such: “Published as a poster at TinyML Research Symposium 2021.”\n"}, "signatures": ["tinyml.org/tinyML/2021/Research_Symposium/Program_Chairs"], "readers": ["everyone"], "nonreaders": [], "writers": ["tinyml.org/tinyML/2021/Research_Symposium/Program_Chairs"], "forumContent": {"title": "Deep Learning for Compute in Memory", "authorids": ["~Matthias_Reisser1", "spitre@qti.qualcomm.com", "xiaochun@qti.qualcomm.com", "~Harris_Teague1", "zwang@qti.qualcomm.com", "~Max_Welling1"], "authors": ["Matthias Reisser", "Saurabh Pitre", "Xiaochun Zhu", "Harris Teague", "Joseph Wang", "Max Welling"], "keywords": ["Compute in Memory", "Deep Learning", "Noise aware training", "binary neural network", "Simulation"], "TL;DR": "We show how a differentiable simulator for compute in memory hardware can make neural networks robust and inform hardware design", "abstract": "Compute in Memory (CIM) accelerators for neural networks promise large efficiency gains, allowing for deep learning applications on extremely resource-constrained devices. Compared to classical digital processors, computations on CIM accelerators are subject to a variety of noise sources such as process variations, thermal effects, quantization, and more. In this work, we show how fundamental hardware design choices influence the predictive performance of neural networks and how training these models to be hardware-aware can make them more robust for CIM deployment. Through various experiments, we make the trade-offs between energy efficiency and model capacity explicit and showcase the benefits of taking a systems view on CIM accelerator and neural network training co-design.", "pdf": "/pdf/fa14dd2dd2078aaa3fcfb91c1a9b4a876540d4a1.pdf", "paperhash": "reisser|deep_learning_for_compute_in_memory", "_bibtex": "@inproceedings{\nreisser2021deep,\ntitle={Deep Learning for Compute in Memory},\nauthor={Matthias Reisser and Saurabh Pitre and Xiaochun Zhu and Harris Teague and Joseph Wang and Max Welling},\nbooktitle={Research Symposium on Tiny Machine Learning},\nyear={2021},\nurl={https://openreview.net/forum?id=zEJDxAKKiat}\n}", "venueid": "tinyml.org/tinyML/2021/Research_Symposium", "venue": "tinyML 2021 Poster"}} |
| {"id": "Nj2aVJ8ZgqX", "original": null, "number": 1, "cdate": 1612536954882, "ddate": null, "tcdate": 1612536954882, "tmdate": 1612735230243, "tddate": null, "forum": "-iuG__7I9QE", "replyto": "-iuG__7I9QE", "invitation": "tinyml.org/tinyML/2021/Research_Symposium/Paper12/-/Decision", "content": {"title": "Paper Decision", "decision": "Accept (Poster)", "comment": "Based on the reviewer feedback, your paper has been accepted as a poster.\n\nPlease read the reviews carefully and make sure the concerns are addressed in your poster submission. \n\nAccepted posters are given a 5-minute slot for an oral presentation on Friday, March 26, 2021, to pitch the main ideas of your work and to stimulate discussions. Detailed instructions will follow soon. All final posters will earn a stamp of acceptance as such: “Published as a poster at TinyML Research Symposium 2021.”\n"}, "signatures": ["tinyml.org/tinyML/2021/Research_Symposium/Program_Chairs"], "readers": ["everyone"], "nonreaders": [], "writers": ["tinyml.org/tinyML/2021/Research_Symposium/Program_Chairs"], "forumContent": {}} |
| {"id": "EL45R1J2Pl6", "original": null, "number": 1, "cdate": 1612536998440, "ddate": null, "tcdate": 1612536998440, "tmdate": 1612735229829, "tddate": null, "forum": "m7Aqzt7Xf4S", "replyto": "m7Aqzt7Xf4S", "invitation": "tinyml.org/tinyML/2021/Research_Symposium/Paper15/-/Decision", "content": {"title": "Paper Decision", "decision": "Accept (Poster)", "comment": "Based on the reviewer feedback, your paper has been accepted as a poster.\n\nPlease read the reviews carefully and make sure the concerns are addressed in your poster submission. \n\nAccepted posters are given a 5-minute slot for an oral presentation on Friday, March 26, 2021, to pitch the main ideas of your work and to stimulate discussions. Detailed instructions will follow soon. All final posters will earn a stamp of acceptance as such: “Published as a poster at TinyML Research Symposium 2021.”\n"}, "signatures": ["tinyml.org/tinyML/2021/Research_Symposium/Program_Chairs"], "readers": ["everyone"], "nonreaders": [], "writers": ["tinyml.org/tinyML/2021/Research_Symposium/Program_Chairs"], "forumContent": {}} |
| {"id": "lkElrEfSMJv", "original": null, "number": 1, "cdate": 1612537012777, "ddate": null, "tcdate": 1612537012777, "tmdate": 1612735229690, "tddate": null, "forum": "xCLZfHvH3iU", "replyto": "xCLZfHvH3iU", "invitation": "tinyml.org/tinyML/2021/Research_Symposium/Paper16/-/Decision", "content": {"title": "Paper Decision", "decision": "Accept (Poster)", "comment": "Based on the reviewer feedback, your paper has been accepted as a poster.\n\nPlease read the reviews carefully and make sure the concerns are addressed in your poster submission. \n\nAccepted posters are given a 5-minute slot for an oral presentation on Friday, March 26, 2021, to pitch the main ideas of your work and to stimulate discussions. Detailed instructions will follow soon. All final posters will earn a stamp of acceptance as such: “Published as a poster at TinyML Research Symposium 2021.”\n"}, "signatures": ["tinyml.org/tinyML/2021/Research_Symposium/Program_Chairs"], "readers": ["everyone"], "nonreaders": [], "writers": ["tinyml.org/tinyML/2021/Research_Symposium/Program_Chairs"], "forumContent": {}} |
| {"id": "H2-kQvKgQgT", "original": null, "number": 1, "cdate": 1612537057044, "ddate": null, "tcdate": 1612537057044, "tmdate": 1612735229257, "tddate": null, "forum": "rlHeH9tx3SM", "replyto": "rlHeH9tx3SM", "invitation": "tinyml.org/tinyML/2021/Research_Symposium/Paper19/-/Decision", "content": {"title": "Paper Decision", "decision": "Accept (Poster)", "comment": "Based on the reviewer feedback, your paper has been accepted as a poster.\n\nPlease read the reviews carefully and make sure the concerns are addressed in your poster submission. \n\nAccepted posters are given a 5-minute slot for an oral presentation on Friday, March 26, 2021, to pitch the main ideas of your work and to stimulate discussions. Detailed instructions will follow soon. All final posters will earn a stamp of acceptance as such: “Published as a poster at TinyML Research Symposium 2021.”\n"}, "signatures": ["tinyml.org/tinyML/2021/Research_Symposium/Program_Chairs"], "readers": ["everyone"], "nonreaders": [], "writers": ["tinyml.org/tinyML/2021/Research_Symposium/Program_Chairs"], "forumContent": {"title": "Privacy-Preserving Inference on the Edge: Mitigating a New Threat Model", "authorids": ["~Kartik_Prabhu1", "bjun2@stanford.edu", "~Pan_Hu1", "zasgar@stanford.edu", "~Sachin_Katti1", "petewarden@google.com"], "authors": ["Kartik Prabhu", "Brian Jun", "Pan Hu", "Zain Asgar", "Sachin Katti", "Pete Warden"], "keywords": ["privacy", "security", "edge inference", "embedded", "secure enclave", "TEE"], "TL;DR": "This paper proposes using a secure enclave for privacy-preserving machine learning at the edge.", "abstract": "With the explosion of machine learning at the edge, there's a major need for privacy-preserving machine learning for edge devices. As the number of devices in homes and other private spaces increases, we can expect to see more malicious actors exploiting the inherent recording capabilities in these systems to harm people. This paper proposes that machine learning is not the problem, but rather a solution, which along with the use of a secure enclave, offers a pragmatic approach to preserving privacy. With a simple programming framework, we show how machine learning application developers can be as productive as usual, while still keeping user data private. We demonstrate our implementation for privacy-preserving machine learning on an embedded system, the Nordic NRF5340 PDK with Arm Cotex-M-33, using a relatively large model for person-detection. pdf/pdf/5e62b1d1876a50831ea54e20f26f304ed1137506.pdfpaperhashprabhu|privacypreserving_inference_on_the_edge_mitigating_a_new_threat_model_bibtex@inproceedings{\nprabhu2021privacypreserving,\ntitle={Privacy-Preserving Inference on the Edge: Mitigating a New Threat Model},\nauthor={Kartik Prabhu and Brian Jun and Pan Hu and Zain Asgar and Sachin Katti and Pete Warden},\nbooktitle={Research Symposium on Tiny Machine Learning},\nyear={2021},\nurl={https://openreview.net/forum?id=rlHeH9tx3SM}\n}venueidtinyml.org/tinyML/2021/Research_SymposiumvenuetinyML 2021 Poster |
| id9TKvEDJamlqoriginalnumbercdatepdatemdateddatetcdatetmdatetddateforum9TKvEDJamlqreplytoinvitationdblp.org/-/recordcontentvenueDCIS 2022venueiddblp.org/conf/DCIS/2022_bibtex@inproceedings{DBLP:conf/dcis/Garcia-RedondoB22,\n author={Fernando García-Redondo and Ali BanaGozar and Kanishkan Vadivel and Henk Corporaal and Shidhartha Das},\n title={SACA: System-level Analog CIM Accelerators Simulation Framework: Accurate Simulation of Non-Ideal Components},\n year={2022},\n cdate={1640995200000},\n pages={1-6},\n url={https://doi.org/10.1109/DCIS55711.2022.9970112},\n booktitle={DCIS},\n crossref={conf/dcis/2022},\n}\nauthorsFernando García-RedondoAli BanaGozarKanishkan VadivelHenk CorporaalShidhartha Dasauthorids~Fernando_García-Redondo1https://dblp.org/search/pid/api?q=author:Ali_BanaGozar:~Kanishkan_Vadivel1https://dblp.org/search/pid/api?q=author:Henk_Corporaal:https://dblp.org/search/pid/api?q=author:Shidhartha_Das:htmlhttps://doi.org/10.1109/DCIS55711.2022.9970112titleSACA: System-level Analog CIM Accelerators Simulation Framework: Accurate Simulation of Non-Ideal Componentspaperhashgarcíaredondo|saca_systemlevel_analog_cim_accelerators_simulation_framework_accurate_simulation_of_nonideal_componentsabstractAlways-ON accelerators running TinyML applications are strongly limited by the memory and computation resources available in edge devices. Compute-In-Memory (CIM) architectures based on non-volatile memories (NVM) promise to bring the required compute and memory demands of Deep Neural Networks (DNN) to the edge while consuming extremely low power. However, their system-level design is constrained by the device and periphery noise which strongly impacts and compromises the accuracy of the DNN workload. In this paper SACA, a framework for simulating host & CIM accelerator systems, is presented. The simulator quantifies the system reliability by taking into account device-level non-idealities. The accuracy of two representative TinyML workloads is analyzed based on the crossbar characteristics -NVM technology, crossbar size, periphery characteristics. To demonstrate the capabilities of SACA, extensive experiments are carried out. We have characterized a convolutional network tackling CIFAR10 image classification and a fully connected network performing Human Activity Recognition. The results lead to optimal energy/performance/accuracy profiles, while the overall analysis highlights the dramatic effects of IR-drop on larger crossbars, degrading the system's accuracy and compromising its reliability.", "pdf": "https://ieeexplore.ieee.org/iel7/9969904/9970010/09970112.pdf"}, "signatures": ["~Kanishkan_Vadivel1"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "3e91k6-DNDG", "original": null, "number": 812768, "cdate": 1640995200000, "pdate": 1640995200000, "mdate": 1684209272051, "ddate": null, "tcdate": 1684209272051, "tmdate": 1693170372629, "tddate": null, "forum": "3e91k6-DNDG", "replyto": null, "invitation": "dblp.org/-/record", "content": {"venue": "PerCom Workshops 2022", "venueid": "dblp.org/conf/PERCOM/2022", "_bibtex": "@inproceedings{DBLP:conf/percom/KopparapuLBS22,\n author={Kavya Kopparapu and Eric Lin and John G. Breslin and Bharath Sudharsan},\n title={TinyFedTL: Federated Transfer Learning on Ubiquitous Tiny IoT Devices},\n year={2022},\n cdate={1640995200000},\n pages={79-81},\n url={https://doi.org/10.1109/PerComWorkshops53856.2022.9767250},\n booktitle={PerCom Workshops},\n crossref={conf/percom/2022w},\n}\n", "authors": ["Kavya Kopparapu", "Eric Lin", "John G. Breslin", "Bharath Sudharsan"], "authorids": ["https://dblp.org/search/pid/api?q=author:Kavya_Kopparapu:", "~Eric_Lin1", "https://dblp.org/search/pid/api?q=author:John_G._Breslin:", "https://dblp.org/search/pid/api?q=author:Bharath_Sudharsan:"], "html": "https://doi.org/10.1109/PerComWorkshops53856.2022.9767250", "title": "TinyFedTL: Federated Transfer Learning on Ubiquitous Tiny IoT Devices", "paperhash": "kopparapu|tinyfedtl_federated_transfer_learning_on_ubiquitous_tiny_iot_devices", "abstract": "TinyML refers to the intersection of machine learning (ML), mathematical optimization, and tiny IoT embedded systems. In the current era of ubiquitous connectivity and pervasive data, TinyML has emerged as an effective method to continuously analyze real-world data without the resource overhead of traditional ML hardware. However, as valuable data around us is subjected to strict privacy and security guarantees, there is a distinct lack of ML solutions that operate under both constrained computing environments and privacy concerns.In light of these challenges, we present TinyFedTL <sup xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\">1</sup> , the first open-sourced implementation of federated learning (FL) at the most resource-constrained level in IoT containing microcontroller unit (MCU) and small CPU based devices. Using transfer learning (TL) as a representative task, we demonstrate that privacy-centric FL on devices with a tiny memory footprint (less than 1MB) is not only possible but also effective. Researchers and engineers can use TinyFedTL to open up data across various fields that can be used to gain insights for improving quality of life or user experience without sacrificing privacy.", "pdf": "https://ieeexplore.ieee.org/iel7/9766442/9767206/09767250.pdf"}, "signatures": ["~Eric_Lin1"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "xp76oQF9RN9", "original": null, "number": 618508, "cdate": 1640995200000, "mdate": 1681665918766, "ddate": null, "tcdate": 1681665918766, "tmdate": 1699142290807, "tddate": null, "forum": "xp76oQF9RN9", "replyto": null, "invitation": "dblp.org/-/record", "content": {"venue": "CoRR 2022", "venueid": "dblp.org/journals/CORR/2022", "_bibtex": "@article{DBLP:journals/corr/abs-2208-06980,\n publtype={informal},\n author={Alexander Wong and Mohammad Javad Shafiee and Saad Abbasi and Saeejith Nair and Mahmoud Famouri},\n title={Faster Attention Is What You Need: A Fast Self-Attention Neural Network Backbone Architecture for the Edge via Double-Condensing Attention Condensers},\n year={2022},\n cdate={1640995200000},\n journal={CoRR},\n volume={abs/2208.06980},\n url={https://doi.org/10.48550/arXiv.2208.06980},\n}\n", "authors": ["Alexander Wong", "Mohammad Javad Shafiee", "Saad Abbasi", "Saeejith Nair", "Mahmoud Famouri"], "authorids": ["~Alexander_Wong2", "~Mohammad_Javad_Shafiee1", "https://dblp.org/search/pid/api?q=author:Saad_Abbasi:", "https://dblp.org/search/pid/api?q=author:Saeejith_Nair:", "https://dblp.org/search/pid/api?q=author:Mahmoud_Famouri:"], "html": "https://doi.org/10.48550/arXiv.2208.06980", "title": "Faster Attention Is What You Need: A Fast Self-Attention Neural Network Backbone Architecture for the Edge via Double-Condensing Attention Condensers", "paperhash": "wong|faster_attention_is_what_you_need_a_fast_selfattention_neural_network_backbone_architecture_for_the_edge_via_doublecondensing_attention_condensers", "abstract": "With the growing adoption of deep learning for on-device TinyML applications, there has been an ever-increasing demand for efficient neural network backbones optimized for the edge. Recently, the introduction of attention condenser networks have resulted in low-footprint, highly-efficient, self-attention neural networks that strike a strong balance between accuracy and speed. In this study, we introduce a faster attention condenser design called double-condensing attention condensers that allow for highly condensed feature embeddings. We further employ a machine-driven design exploration strategy that imposes design constraints based on best practices for greater efficiency and robustness to produce the macro-micro architecture constructs of the backbone. The resulting backbone (which we name AttendNeXt) achieves significantly higher inference throughput on an embedded ARM processor when compared to several other state-of-the-art efficient backbones (>10x faster than FB-Net C at higher accuracy and speed and >10x faster than MobileOne-S1 at smaller size) while having a small model size (>1.37x smaller than MobileNetv3-L at higher accuracy and speed) and strong accuracy (1.1% higher top-1 accuracy than MobileViT XS on ImageNet at higher speed). These promising results demonstrate that exploring different efficient architecture designs and self-attention mechanisms can lead to interesting new building blocks for TinyML applications.", "pdf": "http://arxiv.org/pdf/2208.06980v3"}, "signatures": ["~Mohammad_Javad_Shafiee1"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "AmoW_UOHC7Z", "original": null, "number": 940504, "cdate": 1640995200000, "pdate": 1640995200000, "mdate": 1699262108885, "ddate": null, "tcdate": 1699262108885, "tmdate": 1747299036925, "tddate": null, "forum": "AmoW_UOHC7Z", "replyto": null, "invitation": "dblp.org/-/record", "content": {"venue": "DCIS 2022", "venueid": "dblp.org/conf/DCIS/2022", "_bibtex": "@inproceedings{DBLP:conf/dcis/VadivelGBCD22,\n author={Kanishkan Vadivel and Fernando García-Redondo and Ali BanaGozar and Henk Corporaal and Shidhartha Das},\n title={SACA: System-level Analog CIM Accelerators Simulation Framework: Architecture and Cycle-accurate System-to-device Simulator},\n year={2022},\n cdate={1640995200000},\n pages={1-6},\n url={https://doi.org/10.1109/DCIS55711.2022.9970090},\n booktitle={DCIS},\n crossref={conf/dcis/2022},\n}\n", "authors": ["Kanishkan Vadivel", "Fernando García-Redondo", "Ali BanaGozar", "Henk Corporaal", "Shidhartha Das"], "authorids": ["~Kanishkan_Vadivel1", "~Fernando_García-Redondo1", "https://dblp.org/search/pid/api?q=author:Ali_BanaGozar:", "https://dblp.org/search/pid/api?q=author:Henk_Corporaal:", "https://dblp.org/search/pid/api?q=author:Shidhartha_Das:"], "html": "https://doi.org/10.1109/DCIS55711.2022.9970090", "title": "SACA: System-level Analog CIM Accelerators Simulation Framework: Architecture and Cycle-accurate System-to-device Simulator", "paperhash": "vadivel|saca_systemlevel_analog_cim_accelerators_simulation_framework_architecture_and_cycleaccurate_systemtodevice_simulator", "abstract": "Analog Computation-In-Memory (CIM) architectures promise to bring to the edge the required compute and memory demands of TinyML applications while consuming extremely low power. However, the analog CIM paradigm is suitable for accelerating vector-matrix multiplication patterns alone, and the accuracy of the computation itself is stirred by the CIM device and its driving circuit non-idealities. Despite these practical constraints, CIM accelerators are often developed and evaluated in isolation without considering real-world system-level conditions, such as sharing system resources (host CPU, main-memory, and interconnect) for inter-layer pre/post-processing, data alignment, and data movement. These make it challenging to evaluate the energy, performance, area, and accuracy tradeoff for practical, end-to-end applications. To address this, we propose a first SoC level, gem5-based, open-source simulation framework for CIM accelerator design. It supports the modeling of hierarchical CIM accelerators for different device technologies and digital/mixed-signal driving circuit configurations, along with their non-ideal behaviour. The associated full-stack software provides APIs for (re-)configuring the CIM accelerator for offloading computations at the system level. To demonstrate some capabilities of the SACA, we carried out design space exploration on two representative TinyML tasks - Human Activity Recognition and CIFAR10 image classification. The results lead to optimal accelerator profiles and indicate a tradeoff between the energy, area, performance, and accuracy for different configurations.", "pdf": "https://ieeexplore.ieee.org/iel7/9969904/9970010/09970090.pdf"}, "signatures": ["~Kanishkan_Vadivel1"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "c4sc1Bbr20e", "original": null, "number": 618537, "cdate": 1577836800000, "mdate": 1681665918901, "ddate": null, "tcdate": 1681665918901, "tmdate": 1699142293063, "tddate": null, "forum": "c4sc1Bbr20e", "replyto": null, "invitation": "dblp.org/-/record", "content": {"venue": "CoRR 2020", "venueid": "dblp.org/journals/CORR/2020", "_bibtex": "@article{DBLP:journals/corr/abs-2009-14385,\n publtype={informal},\n author={Alexander Wong and Mahmoud Famouri and Mohammad Javad Shafiee},\n title={AttendNets: Tiny Deep Image Recognition Neural Networks for the Edge via Visual Attention Condensers},\n year={2020},\n cdate={1577836800000},\n journal={CoRR},\n volume={abs/2009.14385},\n url={https://arxiv.org/abs/2009.14385},\n}\n", "authors": ["Alexander Wong", "Mahmoud Famouri", "Mohammad Javad Shafiee"], "authorids": ["~Alexander_Wong2", "https://dblp.org/search/pid/api?q=author:Mahmoud_Famouri:", "~Mohammad_Javad_Shafiee1"], "html": "https://arxiv.org/abs/2009.14385", "title": "AttendNets: Tiny Deep Image Recognition Neural Networks for the Edge via Visual Attention Condensers", "paperhash": "wong|attendnets_tiny_deep_image_recognition_neural_networks_for_the_edge_via_visual_attention_condensers", "abstract": "While significant advances in deep learning has resulted in state-of-the-art performance across a large number of complex visual perception tasks, the widespread deployment of deep neural networks for TinyML applications involving on-device, low-power image recognition remains a big challenge given the complexity of deep neural networks. In this study, we introduce AttendNets, low-precision, highly compact deep neural networks tailored for on-device image recognition. More specifically, AttendNets possess deep self-attention architectures based on visual attention condensers, which extends on the recently introduced stand-alone attention condensers to improve spatial-channel selective attention. Furthermore, AttendNets have unique machine-designed macroarchitecture and microarchitecture designs achieved via a machine-driven design exploration strategy. Experimental results on ImageNet$_{50}$ benchmark dataset for the task of on-device image recognition showed that AttendNets have significantly lower architectural and computational complexity when compared to several deep neural networks in research literature designed for efficiency while achieving highest accuracies (with the smallest AttendNet achieving $\\sim$7.2% higher accuracy, while requiring $\\sim$3$\\times$ fewer multiply-add operations, $\\sim$4.17$\\times$ fewer parameters, and $\\sim$16.7$\\times$ lower weight memory requirements than MobileNet-V1). Based on these promising results, AttendNets illustrate the effectiveness of visual attention condensers as building blocks for enabling various on-device visual perception tasks for TinyML applications.", "pdf": "http://arxiv.org/pdf/2009.14385v1"}, "signatures": ["~Mohammad_Javad_Shafiee1"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "Cn1y_dYFeSV", "original": "uPZAkiYW_k4", "number": 9, "cdate": 1664902716549, "mdate": null, "ddate": null, "tcdate": 1664902716549, "tmdate": 1683308574058, "tddate": null, "forum": "Cn1y_dYFeSV", "replyto": null, "invitation": "NeurIPS.cc/2022/Workshop/Attention/-/Blind_Submission", "content": {"title": "Faster Attention Is What You Need: A Fast Self-Attention Neural Network Backbone Architecture for the Edge via Double-Condensing Attention Condensers", "authorids": ["~Alexander_Wong2", "~Mohammad_Javad_Shafiee1", "~Saad_Abbasi1", "smnair@uwaterloo.ca", "mahmoud@darwinai.ca"], "authors": ["Alexander Wong", "Mohammad Javad Shafiee", "Saad Abbasi", "Saeejith Nair", "Mahmoud Famouri"], "keywords": [], "abstract": "With the growing adoption of deep learning for on-device TinyML applications, there has been an ever-increasing demand for more efficient neural network backbones optimized for the edge. Recently, the introduction of attention condenser networks have resulted in low-footprint, highly-efficient, self-attention neural networks that strike a strong balance between accuracy and speed. In this study, we introduce a new faster attention condenser design called double-condensing attention condensers that enable more condensed feature embedding. We further employ a machine-driven design exploration strategy that imposes best practices design constraints for greater efficiency and robustness to produce the macro-micro architecture constructs of the backbone. The resulting backbone (which we name \\textbf{AttendNeXt}) achieves significantly higher inference throughput on an embedded ARM processor when compared to several other state-of-the-art efficient backbones ($>10\\times$ faster than FB-Net C at higher accuracy and speed and $>10\\times$ faster than MobileOne-S1 at smaller size) while having a small model size ($>1.37\\times$ smaller than MobileNetv3-L at higher accuracy and speed) and strong accuracy (1.1\\% higher top-1 accuracy than MobileViT XS on ImageNet at higher speed). These promising results demonstrate that exploring different efficient architecture designs and self-attention mechanisms can lead to interesting new building blocks for TinyML applications.", "pdf": "/pdf/849fab55d345604a16fe3b127fea2f544ecb15fa.pdf", "financial-aid": "Yes, I need financial assistance to present in-person at the workshop.", "paperhash": "wong|faster_attention_is_what_you_need_a_fast_selfattention_neural_network_backbone_architecture_for_the_edge_via_doublecondensing_attention_condensers", "venue": "Attention Workshop, NeurIPS 2022 Poster", "venueid": "NeurIPS.cc/2022/Workshop/Attention", "_bibtex": "@inproceedings{\nwong2022faster,\ntitle={Faster Attention Is What You Need: A Fast Self-Attention Neural Network Backbone Architecture for the Edge via Double-Condensing Attention Condensers},\nauthor={Alexander Wong and Mohammad Javad Shafiee and Saad Abbasi and Saeejith Nair and Mahmoud Famouri},\nbooktitle={NeurIPS '22 Workshop on All Things Attention: Bridging Different Perspectives on Attention},\nyear={2022},\nurl={https://openreview.net/forum?id=Cn1y_dYFeSV}\n}signaturesNeurIPS.cc/2022/Workshop/AttentionreaderseveryonenonreaderswritersNeurIPS.cc/2022/Workshop/Attentionpdateodate |
| idwTzu1E_K3soriginalnumbercdatemdateddatetcdatetmdatetddateforummXPoBtnpMnuyreplyto29mfjjiStaBinvitationICLR.cc/2023/Conference/Paper3864/-/Official_CommentcontenttitleSatisfied by author response addressing comments in my reviewcommentDear authors,\n\nI apologize for the slight delay in my update and I thank you very much for the detailed response to the comments I raised in my review. \n\n`..On the other hand, accuracy significantly drops at the small supervised models while the unsupervised models are less sensitive to the model size. The performance difference is particularly large at the model which size is 0.09MB: the unsupervised model achieves 71.7% and the supervised model shows 59.9%.`\n\nThis is awesome! I'm really impressed that the unsupervised model is quite robust to low model sizes. Thank you also \n\n`We would first like to note that NeAW is an innovation in learning rule, rather than in model architecture. The advantage of NeAW is the unsupervised learning, which enables learning from less labelled data, even for low-complexity models. The alternative model architectures with lower/comparative complexity referred by the reviewer are trained in a supervised fashion.`\n\nI agree, I believe NeAW is trying to push for advances in both TinyML and unsupervised representation learning. Hence, I was recommending a holistic evaluation that also includes supervised models. However, I acknowledge that the proposed NeAW learning rule is a meaningful improvement to existing unsupervised Hebbian/AntiHebbian learning rules. \n\nI also appreciate the additional data and figures to study the effect of a and b. I would like to make a small suggestion to improve the clarity of this plot. I would suggest using a suitable colormap that highlights the low and high values of a and b in Fig. 13 (a), (c).\n\nThank you also for committing to upload the code on GitHub if the paper is accepted. \n\nAs my response to the author rebuttal above suggests, I am more convinced than before of the value of the contribution of the NeAW learning rule to TinyML and unsupervised (Hebbian) representation learning. I am hence raising my score to 8 and recommend acceptance of this paper. I think this paper presents some really key contributions to produce low-cost unsupervised machine learning models."}, "signatures": ["ICLR.cc/2023/Conference/Paper3864/Reviewer_rCep"], "readers": ["everyone"], "nonreaders": [], "writers": ["ICLR.cc/2023/Conference", "ICLR.cc/2023/Conference/Paper3864/Reviewer_rCep"], "forumContent": {}} |
| {"id": "-YY3H7gBhh_", "original": null, "number": 652552, "cdate": 1577836800000, "mdate": 1682346403833, "ddate": null, "tcdate": 1682346403833, "tmdate": 1747384501686, "tddate": null, "forum": "-YY3H7gBhh_", "replyto": null, "invitation": "dblp.org/-/record", "content": {"venue": "CoRR 2020", "venueid": "dblp.org/journals/CORR/2020", "_bibtex": "@article{DBLP:journals/corr/abs-2007-10319,\n publtype={informal},\n author={Ji Lin and Wei-Ming Chen and Yujun Lin and John Cohn and Chuang Gan and Song Han},\n title={MCUNet: Tiny Deep Learning on IoT Devices},\n year={2020},\n cdate={1577836800000},\n journal={CoRR},\n volume={abs/2007.10319},\n url={https://arxiv.org/abs/2007.10319},\n}\n", "authors": ["Ji Lin", "Wei-Ming Chen", "Yujun Lin", "John Cohn", "Chuang Gan", "Song Han"], "authorids": ["https://dblp.org/search/pid/api?q=author:Ji_Lin_0002:", "~Wei-Ming_Chen1", "https://dblp.org/search/pid/api?q=author:Yujun_Lin_0001:", "https://dblp.org/search/pid/api?q=author:John_Cohn:", "https://dblp.org/search/pid/api?q=author:Chuang_Gan:", "~Song_Han5"], "html": "https://arxiv.org/abs/2007.10319", "title": "MCUNet: Tiny Deep Learning on IoT Devices", "paperhash": "lin|mcunet_tiny_deep_learning_on_iot_devices", "abstract": "Machine learning on tiny IoT devices based on microcontroller units (MCU) is appealing but challenging: the memory of microcontrollers is 2-3 orders of magnitude smaller even than mobile phones. We propose MCUNet, a framework that jointly designs the efficient neural architecture (TinyNAS) and the lightweight inference engine (TinyEngine), enabling ImageNet-scale inference on microcontrollers. TinyNAS adopts a two-stage neural architecture search approach that first optimizes the search space to fit the resource constraints, then specializes the network architecture in the optimized search space. TinyNAS can automatically handle diverse constraints (i.e.device, latency, energy, memory) under low search costs.TinyNAS is co-designed with TinyEngine, a memory-efficient inference library to expand the search space and fit a larger model. TinyEngine adapts the memory scheduling according to the overall network topology rather than layer-wise optimization, reducing the memory usage by 4.8x, and accelerating the inference by 1.7-3.3x compared to TF-Lite Micro and CMSIS-NN. MCUNet is the first to achieves >70% ImageNet top1 accuracy on an off-the-shelf commercial microcontroller, using 3.5x less SRAM and 5.7x less Flash compared to quantized MobileNetV2 and ResNet-18. On visual&audio wake words tasks, MCUNet achieves state-of-the-art accuracy and runs 2.4-3.4x faster than MobileNetV2 and ProxylessNAS-based solutions with 3.7-4.1x smaller peak SRAM. Our study suggests that the era of always-on tiny machine learning on IoT devices has arrived. Code and models can be found here: https://tinyml.mit.edu.", "pdf": "http://arxiv.org/pdf/2007.10319v2"}, "signatures": ["~Wei-Ming_Chen1"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "iCWTS-5VIf", "original": null, "number": 1, "cdate": 1627336714865, "mdate": null, "ddate": null, "tcdate": 1627336714865, "tmdate": 1627336714865, "tddate": null, "forum": "8RxxwAut1BI", "replyto": "8RxxwAut1BI", "invitation": "NeurIPS.cc/2021/Track/Datasets_and_Benchmarks/Round1/Paper120/-/Decision", "content": {"title": "Paper Decision", "decision": "Accept", "comment": "The paper proposes a benchmark for machine learning models running on low-power devices. All reviewers saw value in the proposed benchmark, but initially had some minor concerns and requested more details about how to run the benchmark, wanted to see more evaluation results, and wanted to see more discussion about connections between different layers of the TinyML stack (Figure 1). The authors were able to address these concerns through their responses and revisions to the paper, and in the end all reviewers voted to accept the paper. Congratulations on having your paper accepted to the NeurIPS 2021 Datasets and Benchmarks Track! The authors are encouraged to use the additional space in the camera-ready version of the paper to continue refining the language and presentation in light of the new additions suggested by reviewers."}, "signatures": ["NeurIPS.cc/2021/Track/Datasets_and_Benchmarks/Round1/Program_Chairs"], "readers": ["everyone"], "nonreaders": [], "writers": ["NeurIPS.cc/2021/Track/Datasets_and_Benchmarks/Round1/Program_Chairs"], "forumContent": {}} |
| {"id": "2lmarEcvaid", "original": null, "number": 990790, "cdate": 1640995200000, "pdate": 1640995200000, "mdate": 1705989814390, "ddate": null, "tcdate": 1705989814390, "tmdate": 1705991984041, "tddate": null, "forum": "2lmarEcvaid", "replyto": null, "invitation": "dblp.org/-/record", "content": {"venue": "AAAI 2022", "venueid": "dblp.org/conf/AAAI/2022", "_bibtex": "@inproceedings{DBLP:conf/aaai/XuLZL022,\n author={Kunran Xu and Yishi Li and Huawei Zhang and Rui Lai and Lin Gu},\n title={EtinyNet: Extremely Tiny Network for TinyML},\n year={2022},\n cdate={1640995200000},\n pages={4628-4636},\n url={https://doi.org/10.1609/aaai.v36i4.20387},\n booktitle={AAAI},\n crossref={conf/aaai/2022},\n}\n", "authors": ["Kunran Xu", "Yishi Li", "Huawei Zhang", "Rui Lai", "Lin Gu"], "authorids": ["https://dblp.org/search/pid/api?q=author:Kunran_Xu:", "https://dblp.org/search/pid/api?q=author:Yishi_Li:", "https://dblp.org/search/pid/api?q=author:Huawei_Zhang:", "https://dblp.org/search/pid/api?q=author:Rui_Lai:", "~Lin_Gu2"], "html": "https://doi.org/10.1609/aaai.v36i4.20387", "title": "EtinyNet: Extremely Tiny Network for TinyML", "paperhash": "xu|etinynet_extremely_tiny_network_for_tinyml", "abstract": "There are many AI applications in high-income countries because their implementation depends on expensive GPU cards (~2000$) and reliable power supply (~200W). To deploy AI in resource-poor settings on cheaper (~20$) and low-power devices (", "pdf": "https://ojs.aaai.org/index.php/AAAI/article/download/20387/20146"}, "signatures": ["~Lin_Gu4"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "FPrN6sojmdl", "original": null, "number": 665450, "cdate": 1609459200000, "pdate": 1609459200000, "mdate": 1682647057407, "ddate": null, "tcdate": 1682647057407, "tmdate": 1692808220156, "tddate": null, "forum": "FPrN6sojmdl", "replyto": null, "invitation": "dblp.org/-/record", "content": {"venue": "CoRR 2021", "venueid": "dblp.org/journals/CORR/2021", "_bibtex": "@article{DBLP:journals/corr/abs-2104-02233,\n publtype={informal},\n author={Hamed Fatemi Langroudi and Vedant Karia and Tej Pandit and Dhireesha Kudithipudi},\n title={TENT: Efficient Quantization of Neural Networks on the tiny Edge with Tapered FixEd PoiNT},\n year={2021},\n cdate={1609459200000},\n journal={CoRR},\n volume={abs/2104.02233},\n url={https://arxiv.org/abs/2104.02233},\n}\n", "authors": ["Hamed Fatemi Langroudi", "Vedant Karia", "Tej Pandit", "Dhireesha Kudithipudi"], "authorids": ["~Hamed_Fatemi1", "https://dblp.org/search/pid/api?q=author:Vedant_Karia:", "https://dblp.org/search/pid/api?q=author:Tej_Pandit:", "https://dblp.org/search/pid/api?q=author:Dhireesha_Kudithipudi:"], "html": "https://arxiv.org/abs/2104.02233", "title": "TENT: Efficient Quantization of Neural Networks on the tiny Edge with Tapered FixEd PoiNT", "paperhash": "langroudi|tent_efficient_quantization_of_neural_networks_on_the_tiny_edge_with_tapered_fixed_point", "abstract": "In this research, we propose a new low-precision framework, TENT, to leverage the benefits of a tapered fixed-point numerical format in TinyML models. We introduce a tapered fixed-point quantization algorithm that matches the numerical format's dynamic range and distribution to that of the deep neural network model's parameter distribution at each layer. An accelerator architecture for the tapered fixed-point with TENT framework is proposed. Results show that the accuracy on classification tasks improves up to ~31 % with an energy overhead of ~17-30 % as compared to fixed-point, for ConvNet and ResNet-18 models.", "pdf": "http://arxiv.org/pdf/2104.02233v1"}, "signatures": ["~Hamed_Fatemi1"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "3j7oseeqOvI", "original": null, "number": 3, "cdate": 1657508126663, "ddate": null, "tcdate": 1657508126663, "tmdate": 1659891597203, "tddate": null, "forum": "zGvRdBW06F5", "replyto": "zGvRdBW06F5", "invitation": "NeurIPS.cc/2022/Conference/Paper2198/-/Official_Review", "content": {"rating": "6: Weak Accept: Technically solid, moderate-to-high impact paper, with no major concerns with respect to evaluation, resources, reproducibility, ethical considerations.", "confidence": "5: You are absolutely certain about your assessment. You are very familiar with the related work and checked the math/other details carefully.", "summary": "This paper presents a system-algorithm co-design approach towards conducting transfer learning training on tiny microcontroller-based systems with less than 256KB memory. The ideas focus on: (1) improving optimization characteristics of quantization aware training, (2) gradient sparsification, (3) new compile time optimizations with Tiny Training Engine. Results are shown on several tinyML applications.", "strengths_and_weaknesses": "The paper has several strengths:\n\n1. Training on-device is much more difficult than inference on-device. Hence, doing simple transfer learning kind of tasks on tiny devices is interesting.\n\n2. The paper makes significant contributions towards optimization of quantized networks as well as training support compilers for tiny devices.\n\n3. The results demonstrate significant memory savings compared to standard deep learning frameworks (Tensorflow/Pytorch).\n\nDespite the strengths, the paper does have several significant weaknesses:\n\n1. One of the main motivations that authors use to disregard several existing training time/adaptation techniques (e.g, the ones that rely on updating only the normalization layers (reference [25] in paper)) is that the normalization layers are not present once the model is deployed on tiny devices. This happens because deployment tools like TFLITE, etc., fuse the batchnorm layers into convolution weights. However, this fusing process is extremely cheap, and the compiler needs to do it only once for inference. Can we not keep the norm layers for the on-device training purposes and fuse them only when running inference? Would training only the norm layers result in significant savings compared to the proposed approach? This is a major class of upcoming cheap training time/adaptation techniques and solid evidence must be presented to show that the proposed approach indeed outperforms this new class of models. The baselines considered for comparison (“update last k layers”, “update last k biases”, “update only the classifier”) are not strong. If “update only norm layers” kind of techniques are effective, it may also reduce the motivation behind the proposed quantization scaling method.\n\n2. The improvements to the optimization problem for quantization aware training seem general. However, the authors have not provided any evidence that this would result in general improvements in quantization-aware training (and not just for tinyML applications). Specifically, would the proposed scaling method reduce the gap between FP32 and INT8 models for non-transfer learning scenarios? This kind of experiment can clarify whether the proposed technique is limited to transfer learning only or does it apply to general quantization-aware training? If it only works for transfer learning and not in general, why? Some discussion around specific conditions under which the proposed method works would strengthen the paper.\n\n3. There are many existing gradient sparsification techniques. Authors have not presented any comparison against existing gradient sparsification techniques. For instance, this paper and the many references it cites are relevant: https://arxiv.org/pdf/1712.01887.pdf. Some newer papers probably exist in this space. The above paper is from 2017. I would recommend authors to do a thorough comparison against SotA gradient sparsification techniques.\n\n4. Will the code for tiny training engine be open sourced?\n\nOverall, I like the idea in this paper and the fact that this is the first paper that trains models on-device for realistic applications under 256KB. This is a significant contribution. However, I would like to make sure that the paper is not missing significant baselines and comparisons. I can increase the rating if the above weaknesses are adequately addressed.\n\n\n---Update after rebuttal---\nI have read other reviews and author response. The authors have provided good clarification and insightful new experiments during the rebuttal. They have satisfactorily answered my questions. As a result I have increased the rating to \"6: Weak Accept\". If the paper is accepted, I would like the authors to just show a simple comparison between standard quantization-aware-training (QAT, e.g., where BNs are still present and are fused after QAT is complete) and QAS on real quantized graph (e.g., the one without BN). While I can see that on a real quantized graph, QAS has benefits for non-transfer learning scenarios (based on new results), it would be useful to see the gap between regular QAT and QAS on real quantized graphs. Indeed, this can help motivate future works that may improve upon QAS to close the gap between QAT and quantization algorithms that directly work on real quantized graphs.\n", "questions": "Please refer to the last section. ", "limitations": "Mostly yes. Other things like point 2 above (see weaknesses) can help further.", "ethics_flag": "No", "ethics_review_area": [], "soundness": "3 good", "presentation": "4 excellent", "contribution": "3 good", "code_of_conduct": "Yes"}, "signatures": ["NeurIPS.cc/2022/Conference/Paper2198/Reviewer_JJZV"], "readers": ["everyone"], "nonreaders": [], "writers": ["NeurIPS.cc/2022/Conference", "NeurIPS.cc/2022/Conference/Paper2198/Reviewer_JJZV"], "forumContent": {}} |
| {"id": "xJoMgbzEe82", "original": null, "number": 466976, "cdate": 1577836800000, "mdate": 1668013811738, "ddate": null, "tcdate": 1668013811738, "tmdate": 1741165756385, "tddate": null, "forum": "xJoMgbzEe82", "replyto": null, "invitation": "dblp.org/-/record", "content": {"venue": "CoRR 2020", "venueid": "dblp.org/journals/CORR/2020", "_bibtex": "@article{DBLP:journals/corr/abs-2007-00302,\n publtype={informal},\n author={Miguel de Prado and Romain Donze and Alessandro Capotondi and Manuele Rusci and Serge Monnerat and Luca Benini and Nuria Pazos},\n title={Robust navigation with tinyML for autonomous mini-vehicles},\n year={2020},\n cdate={1577836800000},\n journal={CoRR},\n volume={abs/2007.00302},\n url={https://arxiv.org/abs/2007.00302}\n}\n", "authors": ["Miguel de Prado", "Romain Donze", "Alessandro Capotondi", "Manuele Rusci", "Serge Monnerat", "Luca Benini", "Nuria Pazos"], "authorids": ["https://dblp.org/search/pid/api?q=author:Miguel_de_Prado:", "https://dblp.org/search/pid/api?q=author:Romain_Donze:", "~Alessandro_Capotondi1", "https://dblp.org/search/pid/api?q=author:Manuele_Rusci:", "https://dblp.org/search/pid/api?q=author:Serge_Monnerat:", "~Luca_Benini2", "https://dblp.org/search/pid/api?q=author:Nuria_Pazos:"], "html": "https://arxiv.org/abs/2007.00302", "title": "Robust navigation with tinyML for autonomous mini-vehicles", "paperhash": "prado|robust_navigation_with_tinyml_for_autonomous_minivehicles", "abstract": "Standard-size autonomous navigation vehicles have rapidly improved thanks to the breakthroughs of deep learning. However, scaling autonomous driving to low-power systems deployed on dynamic environments poses several challenges that prevent their adoption. To address them, we propose a closed-loop learning flow for autonomous driving mini-vehicles that includes the target environment in-the-loop. We leverage a family of compact and high-throughput tinyCNNs to control the mini-vehicle, which learn in the target environment by imitating a computer vision algorithm, i.e., the expert. Thus, the tinyCNNs, having only access to an on-board fast-rate linear camera, gain robustness to lighting conditions and improve over time. Further, we leverage GAP8, a parallel ultra-low-power RISC-V SoC, to meet the inference requirements. When running the family of CNNs, our GAP8's solution outperforms any other implementation on the STM32L4 and NXP k64f (Cortex-M4), reducing the latency by over 13x and the energy consummation by 92%.pdfhttp://arxiv.org/pdf/2007.00302v2signatures~Luca_Benini2readerseveryonenonreaderswritersdblp.org |
| idjelGPeZMm1YoriginalnumbercdatemdateddatetcdatetmdatetddateforumjelGPeZMm1Yreplytoinvitationdblp.org/-/recordcontentvenueCoRR 2020venueiddblp.org/journals/CORR/2020_bibtex@article{DBLP:journals/corr/abs-2007-00302,\n publtype={informal},\n author={Miguel de Prado and Romain Donze and Alessandro Capotondi and Manuele Rusci and Serge Monnerat and Luca Benini and Nuria Pazos},\n title={Robust navigation with tinyML for autonomous mini-vehicles},\n year={2020},\n cdate={1577836800000},\n journal={CoRR},\n volume={abs/2007.00302},\n url={https://arxiv.org/abs/2007.00302}\n}\nauthorsMiguel de PradoRomain DonzeAlessandro CapotondiManuele RusciSerge MonneratLuca BeniniNuria Pazosauthoridshttps://dblp.org/search/pid/api?q=author:Miguel_de_Prado:https://dblp.org/search/pid/api?q=author:Romain_Donze:https://dblp.org/search/pid/api?q=author:Alessandro_Capotondi:https://dblp.org/search/pid/api?q=author:Manuele_Rusci:https://dblp.org/search/pid/api?q=author:Serge_Monnerat:~Luca_Benini2https://dblp.org/search/pid/api?q=author:Nuria_Pazos:htmlhttps://arxiv.org/abs/2007.00302titleRobust navigation with tinyML for autonomous mini-vehiclespaperhashprado|robust_navigation_with_tinyml_for_autonomous_minivehiclesabstractStandard-size autonomous navigation vehicles have rapidly improved thanks to the breakthroughs of deep learning. However, scaling autonomous driving to low-power systems deployed on dynamic environments poses several challenges that prevent their adoption. To address them, we propose a closed-loop learning flow for autonomous driving mini-vehicles that includes the target environment in-the-loop. We leverage a family of compact and high-throughput tinyCNNs to control the mini-vehicle, which learn in the target environment by imitating a computer vision algorithm, i.e., the expert. Thus, the tinyCNNs, having only access to an on-board fast-rate linear camera, gain robustness to lighting conditions and improve over time. Further, we leverage GAP8, a parallel ultra-low-power RISC-V SoC, to meet the inference requirements. When running the family of CNNs, our GAP8's solution outperforms any other implementation on the STM32L4 and NXP k64f (Cortex-M4), reducing the latency by over 13x and the energy consummation by 92%.", "pdf": "http://arxiv.org/pdf/2007.00302v2"}, "signatures": ["~Luca_Benini2"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "Rov5nl2tAf", "original": null, "number": 913144, "cdate": 1609459200000, "pdate": 1609459200000, "mdate": 1699142291740, "ddate": null, "tcdate": 1699142291740, "tmdate": 1699149916176, "tddate": null, "forum": "Rov5nl2tAf", "replyto": null, "invitation": "dblp.org/-/record", "content": {"venue": "CoRR 2021", "venueid": "dblp.org/journals/CORR/2021", "_bibtex": "@article{DBLP:journals/corr/abs-2104-14623,\n publtype={informal},\n author={Xiaoyu Wen and Mahmoud Famouri and Andrew Hryniowski and Alexander Wong},\n title={AttendSeg: A Tiny Attention Condenser Neural Network for Semantic Segmentation on the Edge},\n year={2021},\n cdate={1609459200000},\n journal={CoRR},\n volume={abs/2104.14623},\n url={https://arxiv.org/abs/2104.14623},\n}\n", "authors": ["Xiaoyu Wen", "Mahmoud Famouri", "Andrew Hryniowski", "Alexander Wong"], "authorids": ["https://dblp.org/search/pid/api?q=author:Xiaoyu_Wen:", "https://dblp.org/search/pid/api?q=author:Mahmoud_Famouri:", "https://dblp.org/search/pid/api?q=author:Andrew_Hryniowski:", "~Alexander_Wong2"], "html": "https://arxiv.org/abs/2104.14623", "title": "AttendSeg: A Tiny Attention Condenser Neural Network for Semantic Segmentation on the Edge", "paperhash": "wen|attendseg_a_tiny_attention_condenser_neural_network_for_semantic_segmentation_on_the_edge", "abstract": "In this study, we introduce \\textbf{AttendSeg}, a low-precision, highly compact deep neural network tailored for on-device semantic segmentation. AttendSeg possesses a self-attention network architecture comprising of light-weight attention condensers for improved spatial-channel selective attention at a very low complexity. The unique macro-architecture and micro-architecture design properties of AttendSeg strike a strong balance between representational power and efficiency, achieved via a machine-driven design exploration strategy tailored specifically for the task at hand. Experimental results demonstrated that the proposed AttendSeg can achieve segmentation accuracy comparable to much larger deep neural networks with greater complexity while possessing a significantly lower architecture and computational complexity (requiring as much as >27x fewer MACs, >72x fewer parameters, and >288x lower weight memory requirements), making it well-suited for TinyML applications on the edge.", "pdf": "http://arxiv.org/pdf/2104.14623v1"}, "signatures": ["~Alexander_Wong2"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "cAr6FRvI__", "original": null, "number": 403493, "cdate": 1609459200000, "mdate": 1667336578730, "ddate": null, "tcdate": 1667336578730, "tmdate": 1684724772474, "tddate": null, "forum": "cAr6FRvI__", "replyto": null, "invitation": "dblp.org/-/record", "content": {"venue": "CoRR 2021", "venueid": "dblp.org/journals/CORR/2021", "_bibtex": "@article{DBLP:journals/corr/abs-2104-10645,\n publtype={informal},\n author={Lennart Heim and Andreas Biri and Zhongnan Qu and Lothar Thiele},\n title={Measuring what Really Matters: Optimizing Neural Networks for TinyML},\n year={2021},\n cdate={1609459200000},\n journal={CoRR},\n volume={abs/2104.10645},\n url={https://arxiv.org/abs/2104.10645}\n}\n", "authors": ["Lennart Heim", "Andreas Biri", "Zhongnan Qu", "Lothar Thiele"], "authorids": ["https://dblp.org/search/pid/api?q=author:Lennart_Heim:", "https://dblp.org/search/pid/api?q=author:Andreas_Biri:", "~Zhongnan_Qu1", "~Lothar_Thiele1"], "html": "https://arxiv.org/abs/2104.10645", "title": "Measuring what Really Matters: Optimizing Neural Networks for TinyML", "paperhash": "heim|measuring_what_really_matters_optimizing_neural_networks_for_tinyml", "abstract": "With the surge of inexpensive computational and memory resources, neural networks (NNs) have experienced an unprecedented growth in architectural and computational complexity. Introducing NNs to resource-constrained devices enables cost-efficient deployments, widespread availability, and the preservation of sensitive data. This work addresses the challenges of bringing Machine Learning to MCUs, where we focus on the ubiquitous ARM Cortex-M architecture. The detailed effects and trade-offs that optimization methods, software frameworks, and MCU hardware architecture have on key performance metrics such as inference latency and energy consumption have not been previously studied in depth for state-of-the-art frameworks such as TensorFlow Lite Micro. We find that empirical investigations which measure the perceptible metrics - performance as experienced by the user - are indispensable, as the impact of specialized instructions and layer types can be subtle. To this end, we propose an implementation-aware design as a cost-effective method for verification and benchmarking. Employing our developed toolchain, we demonstrate how existing NN deployments on resource-constrained devices can be improved by systematically optimizing NNs to their targeted application scenario.", "pdf": "http://arxiv.org/pdf/2104.10645v1"}, "signatures": ["~Zhongnan_Qu1"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "e4SeyYYhLY", "original": null, "number": 342231, "cdate": 1609459200000, "mdate": 1654554822901, "ddate": null, "tcdate": 1654554822901, "tmdate": 1731610763511, "tddate": null, "forum": "e4SeyYYhLY", "replyto": null, "invitation": "dblp.org/-/record", "content": {"venue": "CoRR 2021", "venueid": "dblp.org/journals/CORR/2021", "_bibtex": "@article{DBLP:journals/corr/abs-2106-07597,\n publtype={informal},\n author={Colby R. Banbury and Vijay Janapa Reddi and Peter Torelli and Jeremy Holleman and Nat Jeffries and Csaba Király and Pietro Montino and David Kanter and Sebastian Ahmed and Danilo Pau and Urmish Thakker and Antonio Torrini and Pete Warden and Jay Cordaro and Giuseppe Di Guglielmo and Javier M. Duarte and Stephen Gibellini and Videet Parekh and Honson Tran and Nhan Tran and Wenxu Niu and Xuesong Xu},\n title={MLPerf Tiny Benchmark},\n year={2021},\n cdate={1609459200000},\n journal={CoRR},\n volume={abs/2106.07597},\n url={https://arxiv.org/abs/2106.07597}\n}\n", "authors": ["Colby R. Banbury", "Vijay Janapa Reddi", "Peter Torelli", "Jeremy Holleman", "Nat Jeffries", "Csaba Király", "Pietro Montino", "David Kanter", "Sebastian Ahmed", "Danilo Pau", "Urmish Thakker", "Antonio Torrini", "Pete Warden", "Jay Cordaro", "Giuseppe Di Guglielmo", "Javier M. Duarte", "Stephen Gibellini", "Videet Parekh", "Honson Tran", "Nhan Tran", "Wenxu Niu", "Xuesong Xu"], "authorids": ["~Colby_R._Banbury1", "~Vijay_Janapa_Reddi1", "https://dblp.org/search/pid/api?q=author:Peter_Torelli:", "https://dblp.org/search/pid/api?q=author:Jeremy_Holleman:", "~Nat_Jeffries1", "https://dblp.org/search/pid/api?q=author:Csaba_Király_0002:", "https://dblp.org/search/pid/api?q=author:Pietro_Montino:", "https://dblp.org/search/pid/api?q=author:David_Kanter:", "https://dblp.org/search/pid/api?q=author:Sebastian_Ahmed:", "https://dblp.org/search/pid/api?q=author:Danilo_Pau:", "https://dblp.org/search/pid/api?q=author:Urmish_Thakker:", "https://dblp.org/search/pid/api?q=author:Antonio_Torrini:", "~Pete_Warden2", "https://dblp.org/search/pid/api?q=author:Jay_Cordaro:", "https://dblp.org/search/pid/api?q=author:Giuseppe_Di_Guglielmo:", "~Javier_M._Duarte1", "https://dblp.org/search/pid/api?q=author:Stephen_Gibellini:", "https://dblp.org/search/pid/api?q=author:Videet_Parekh:", "https://dblp.org/search/pid/api?q=author:Honson_Tran:", "~Nhan_Tran1", "https://dblp.org/search/pid/api?q=author:Wenxu_Niu:", "https://dblp.org/search/pid/api?q=author:Xuesong_Xu:"], "html": "https://arxiv.org/abs/2106.07597", "title": "MLPerf Tiny Benchmark", "paperhash": "banbury|mlperf_tiny_benchmark", "abstract": "Advancements in ultra-low-power tiny machine learning (TinyML) systems promise to unlock an entirely new class of smart applications. However, continued progress is limited by the lack of a widely accepted and easily reproducible benchmark for these systems. To meet this need, we present MLPerf Tiny, the first industry-standard benchmark suite for ultra-low-power tiny machine learning systems. The benchmark suite is the collaborative effort of more than 50 organizations from industry and academia and reflects the needs of the community. MLPerf Tiny measures the accuracy, latency, and energy of machine learning inference to properly evaluate the tradeoffs between systems. Additionally, MLPerf Tiny implements a modular design that enables benchmark submitters to show the benefits of their product, regardless of where it falls on the ML deployment stack, in a fair and reproducible manner. The suite features four benchmarks: keyword spotting, visual wake words, image classification, and anomaly detection.", "pdf": "http://arxiv.org/pdf/2106.07597v4"}, "signatures": ["~Javier_Duarte1"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "jwEVie4li4", "original": null, "number": 342221, "cdate": 1609459200000, "mdate": 1654554822885, "ddate": null, "tcdate": 1654554822885, "tmdate": 1731610763455, "tddate": null, "forum": "jwEVie4li4", "replyto": null, "invitation": "dblp.org/-/record", "content": {"venue": "NeurIPS Datasets and Benchmarks 2021", "venueid": "dblp.org/conf/NIPS/2021", "_bibtex": "@inproceedings{DBLP:conf/nips/BanburyRTJ0HMKW21,\n author={Colby R. Banbury and Vijay Janapa Reddi and Peter Torelli and Nat Jeffries and Csaba Király and Jeremy Holleman and Pietro Montino and David Kanter and Pete Warden and Danilo Pau and Urmish Thakker and Antonio Torrini and Jay Cordaro and Giuseppe Di Guglielmo and Javier M. Duarte and Honson Tran and Nhan Tran and Wenxu Niu and Xuesong Xu},\n title={MLPerf Tiny Benchmark},\n year={2021},\n cdate={1609459200000},\n url={https://datasets-benchmarks-proceedings.neurips.cc/paper/2021/hash/da4fb5c6e93e74d3df8527599fa62642-Abstract-round1.html},\n booktitle={NeurIPS Datasets and Benchmarks},\n crossref={conf/nips/2021db}\n}\n", "authors": ["Colby R. Banbury", "Vijay Janapa Reddi", "Peter Torelli", "Nat Jeffries", "Csaba Király", "Jeremy Holleman", "Pietro Montino", "David Kanter", "Pete Warden", "Danilo Pau", "Urmish Thakker", "Antonio Torrini", "Jay Cordaro", "Giuseppe Di Guglielmo", "Javier M. Duarte", "Honson Tran", "Nhan Tran", "Wenxu Niu", "Xuesong Xu"], "authorids": ["~Colby_R._Banbury1", "~Vijay_Janapa_Reddi1", "https://dblp.org/search/pid/api?q=author:Peter_Torelli:", "~Nat_Jeffries1", "https://dblp.org/search/pid/api?q=author:Csaba_Király_0002:", "https://dblp.org/search/pid/api?q=author:Jeremy_Holleman:", "https://dblp.org/search/pid/api?q=author:Pietro_Montino:", "https://dblp.org/search/pid/api?q=author:David_Kanter:", "~Pete_Warden2", "https://dblp.org/search/pid/api?q=author:Danilo_Pau:", "https://dblp.org/search/pid/api?q=author:Urmish_Thakker:", "https://dblp.org/search/pid/api?q=author:Antonio_Torrini:", "https://dblp.org/search/pid/api?q=author:Jay_Cordaro:", "https://dblp.org/search/pid/api?q=author:Giuseppe_Di_Guglielmo:", "~Javier_M._Duarte1", "https://dblp.org/search/pid/api?q=author:Honson_Tran:", "~Nhan_Tran1", "https://dblp.org/search/pid/api?q=author:Wenxu_Niu:", "https://dblp.org/search/pid/api?q=author:Xuesong_Xu:"], "html": "https://datasets-benchmarks-proceedings.neurips.cc/paper/2021/hash/da4fb5c6e93e74d3df8527599fa62642-Abstract-round1.html", "title": "MLPerf Tiny Benchmark", "paperhash": "banbury|mlperf_tiny_benchmark", "abstract": "Advancements in ultra-low-power tiny machine learning (TinyML) systems promise to unlock an entirely new class of smart applications. However, continued progress is limited by the lack of a widely accepted and easily reproducible benchmark for these systems. To meet this need, we present MLPerf Tiny, the first industry-standard benchmark suite for ultra-low-power tiny machine learning systems. The benchmark suite is the collaborative effort of more than 50 organizations from industry and academia and reflects the needs of the community. MLPerf Tiny measures the accuracy, latency, and energy of machine learning inference to properly evaluate the tradeoffs between systems. Additionally, MLPerf Tiny implements a modular design that enables benchmark submitters to show the benefits of their product, regardless of where it falls on the ML deployment stack, in a fair and reproducible manner. The suite features four benchmarks: keyword spotting, visual wake words, image classification, and anomaly detection.", "pdf": "https://datasets-benchmarks-proceedings.neurips.cc/paper/2021/file/da4fb5c6e93e74d3df8527599fa62642-Paper-round1.pdf"}, "signatures": ["~Javier_Duarte1"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "wtKSixofaed", "original": null, "number": 7, "cdate": 1659183969687, "ddate": null, "tcdate": 1659183969687, "tmdate": 1659183969687, "tddate": null, "forum": "ZJe-XahpyBf", "replyto": "klLT4YWJSFv", "invitation": "NeurIPS.cc/2022/Conference/Paper1175/-/Official_Comment", "content": {"title": "Response to reviewer 2bCy (1/2)", "comment": "We thank the reviewer for providing feedback on our work. In the following, we address the reviewer’s questions.\n\n> For example, experiment setups and code examples are helpful, especially if no source code available\n\nThe detailed experimental setups are described in Appendices E-G. The complete algorithm pseudo-code is presented in Algorithms 1-2, line 220. We are happy to provide some additional pseudo-code in the revision, so as to make using our approach easier by others. \n\n> The results are useful but not significant. In some scenarios with strict limitations on model size, the proposed method could be used\n\nIn the TinyML setting, where models are deployed on resource constrained embedded hardware, model size is a hugely important factor because of the severely limited Flash storage capacity (see the references in lines 26-28). Therefore, taking full advantage of the model compression ability of modern NPUs offers a unique opportunity for deploying more accurate models on more efficient hardware. \n\n> What is the role of the Vela compiler in the proposed framework? Are the results on model size, e.g., in Fig. 4 & Fig. 5, from the use of the Vela compiler afterwards?\n\nAs we discuss in lines 272-274, we use Eq. (2) to measure compressed model size in all figures and for all competing methods, including UDC. Vela is not used in any of our results comparing UDC to existing NAS methods. We introduce the Vela compiler / compression engine as motivation for our work and as a real-world realization of a deployment scenario which uses model compression. The only place where we use Vela to report compressed model sizes is in Table 4, where we verify that the compression rate predicted by Eq. (2) is achievable by the Vela compiler (indeed Vela achieves even higher compression ratio compared to Eq. (2)).\n\n> What are the performance results, in terms of latency/inference time, of the searched, compressed, and deployed models? Setting the optimization goal to be smallest model size is reasonable if the model size matters the most. But what is the impact on inference performance? The work mentioned using unstructured pruning, would that hurt the performance? Please comment on that.”\n\nIn the use case we studied, decompression is implemented in the Ethos U55 hardware. Since all models pass through a decompression stage during inference, there is no penalty for executing compressed models (i.e. as generated by UDC) compared to off-the-shelf models on the Ethos U55 hardware (or any hardware which has HW decompression). Moreover, for a given model, weight compression leads to memory bandwidth savings, further compounding the benefit at inference time. Reducing model size allows for larger portions of weight stationary execution through compiler optimizations such as cascading (https://developer.arm.com/documentation/101888/0500/NPU-software-overview/NPU-software-tooling/The-Vela-compiler). These optimizations result in less data movement from external memory, and thus, less energy consumption and possibly lower latency.\n\nAs a side note, although our models are heavily pruned and therefore highly compressible by Vela, there is no computational benefit to this pruning since neither the hardware nor inference software stack are designed to take advantage of sparsity to save computation. As such, we don’t expect much of a latency improvement when comparing a given model to its pruned and quantized counterpart. With that being said, it is possible to design future TinyML hardware that takes advantage of model sparsity and more aggressive quantization to give good latency improvement as well."}, "signatures": ["NeurIPS.cc/2022/Conference/Paper1175/Authors"], "readers": ["everyone"], "nonreaders": [], "writers": ["NeurIPS.cc/2022/Conference", "NeurIPS.cc/2022/Conference/Paper1175/Authors"], "forumContent": {}} |
| {"id": "Efyuue1pAN", "original": null, "number": 885613, "cdate": 1672531200000, "pdate": 1672531200000, "mdate": 1695973053446, "ddate": null, "tcdate": 1695973053446, "tmdate": 1700212189145, "tddate": null, "forum": "Efyuue1pAN", "replyto": null, "invitation": "dblp.org/-/record", "content": {"venue": "CoRR 2023", "venueid": "dblp.org/journals/CORR/2023", "_bibtex": "@article{DBLP:journals/corr/abs-2304-03986,\n publtype={informal},\n author={Alberto Marchisio and Davide Dura and Maurizio Capra and Maurizio Martina and Guido Masera and Muhammad Shafique},\n title={SwiftTron: An Efficient Hardware Accelerator for Quantized Transformers},\n year={2023},\n cdate={1672531200000},\n journal={CoRR},\n volume={abs/2304.03986},\n url={https://doi.org/10.48550/arXiv.2304.03986},\n}\n", "authors": ["Alberto Marchisio", "Davide Dura", "Maurizio Capra", "Maurizio Martina", "Guido Masera", "Muhammad Shafique"], "authorids": ["~Alberto_Marchisio1", "https://dblp.org/search/pid/api?q=author:Davide_Dura:", "https://dblp.org/search/pid/api?q=author:Maurizio_Capra:", "https://dblp.org/search/pid/api?q=author:Maurizio_Martina:", "https://dblp.org/search/pid/api?q=author:Guido_Masera:", "~Muhammad_Shafique1"], "html": "https://doi.org/10.48550/arXiv.2304.03986", "title": "SwiftTron: An Efficient Hardware Accelerator for Quantized Transformers", "paperhash": "marchisio|swifttron_an_efficient_hardware_accelerator_for_quantized_transformers", "abstract": "Transformers' compute-intensive operations pose enormous challenges for their deployment in resource-constrained EdgeAI / tinyML devices. As an established neural network compression technique, quantization reduces the hardware computational and memory resources. In particular, fixed-point quantization is desirable to ease the computations using lightweight blocks, like adders and multipliers, of the underlying hardware. However, deploying fully-quantized Transformers on existing general-purpose hardware, generic AI accelerators, or specialized architectures for Transformers with floating-point units might be infeasible and/or inefficient. Towards this, we propose SwiftTron, an efficient specialized hardware accelerator designed for Quantized Transformers. SwiftTron supports the execution of different types of Transformers' operations (like Attention, Softmax, GELU, and Layer Normalization) and accounts for diverse scaling factors to perform correct computations. We synthesize the complete SwiftTron architecture in a $65$ nm CMOS technology with the ASIC design flow. Our Accelerator executes the RoBERTa-base model in 1.83 ns, while consuming 33.64 mW power, and occupying an area of 273 mm^2. To ease the reproducibility, the RTL of our SwiftTron architecture is released at https://github.com/albertomarchisio/SwiftTron.", "pdf": "http://arxiv.org/pdf/2304.03986v2"}, "signatures": ["~Alberto_Marchisio1"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "WCZayGLleHv", "original": null, "number": 467090, "cdate": 1609459200000, "mdate": 1668013814902, "ddate": null, "tcdate": 1668013814902, "tmdate": 1741165756202, "tddate": null, "forum": "WCZayGLleHv", "replyto": null, "invitation": "dblp.org/-/record", "content": {"venue": "Sensors 2021", "venueid": "dblp.org/journals/SENSORS/2021", "_bibtex": "@article{DBLP:journals/sensors/PradoRCDBP21,\n author={Miguel de Prado and Manuele Rusci and Alessandro Capotondi and Romain Donze and Luca Benini and Nuria Pazos},\n title={Robustifying the Deployment of tinyML Models for Autonomous Mini-Vehicles},\n year={2021},\n cdate={1609459200000},\n journal={Sensors},\n volume={21},\n number={4},\n pages={1339},\n url={https://doi.org/10.3390/s21041339}\n}\n", "authors": ["Miguel de Prado", "Manuele Rusci", "Alessandro Capotondi", "Romain Donze", "Luca Benini", "Nuria Pazos"], "authorids": ["https://dblp.org/search/pid/api?q=author:Miguel_de_Prado:", "https://dblp.org/search/pid/api?q=author:Manuele_Rusci:", "~Alessandro_Capotondi1", "https://dblp.org/search/pid/api?q=author:Romain_Donze:", "~Luca_Benini2", "https://dblp.org/search/pid/api?q=author:Nuria_Pazos:"], "html": "https://doi.org/10.3390/s21041339", "title": "Robustifying the Deployment of tinyML Models for Autonomous Mini-Vehicles", "paperhash": "prado|robustifying_the_deployment_of_tinyml_models_for_autonomous_minivehicles", "abstract": "Standard-sized autonomous vehicles have rapidly improved thanks to the breakthroughs of deep learning. However, scaling autonomous driving to mini-vehicles poses several challenges due to their limited on-board storage and computing capabilities. Moreover, autonomous systems lack robustness when deployed in dynamic environments where the underlying distribution is different from the distribution learned during training. To address these challenges, we propose a closed-loop learning flow for autonomous driving mini-vehicles that includes the target deployment environment in-the-loop. We leverage a family of compact and high-throughput tinyCNNs to control the mini-vehicle that learn by imitating a computer vision algorithm, i.e., the expert, in the target environment. Thus, the tinyCNNs, having only access to an on-board fast-rate linear camera, gain robustness to lighting conditions and improve over time. Moreover, we introduce an online predictor that can choose between different tinyCNN models at runtime—trading accuracy and latency—which minimises the inference’s energy consumption by up to 3.2×. Finally, we leverage GAP8, a parallel ultra-low-power RISC-V-based micro-controller unit (MCU), to meet the real-time inference requirements. When running the family of tinyCNNs, our solution running on GAP8 outperforms any other implementation on the STM32L4 and NXP k64f (traditional single-core MCUs), reducing the latency by over 13× and the energy consumption by 92%.", "pdf": "https://www.mdpi.com/1424-8220/21/4/1339/pdf?version=1614069891"}, "signatures": ["~Luca_Benini2"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "WqGXEIMRUIB", "original": null, "number": 466730, "cdate": 1609459200000, "mdate": 1668013807830, "ddate": null, "tcdate": 1668013807830, "tmdate": 1741165756175, "tddate": null, "forum": "WqGXEIMRUIB", "replyto": null, "invitation": "dblp.org/-/record", "content": {"venue": "ISCAS 2021", "venueid": "dblp.org/conf/ISCAS/2021", "_bibtex": "@inproceedings{DBLP:conf/iscas/PradoRDCMBP21,\n author={Miguel de Prado and Manuele Rusci and Romain Donze and Alessandro Capotondi and Serge Monnerat and Luca Benini and Nuria Pazos},\n title={Robustifying the Deployment of tinyML Models for Autonomous Mini-Vehicles},\n year={2021},\n cdate={1609459200000},\n pages={1-5},\n url={https://doi.org/10.1109/ISCAS51556.2021.9401154},\n booktitle={ISCAS},\n crossref={conf/iscas/2021}\n}\n", "authors": ["Miguel de Prado", "Manuele Rusci", "Romain Donze", "Alessandro Capotondi", "Serge Monnerat", "Luca Benini", "Nuria Pazos"], "authorids": ["https://dblp.org/search/pid/api?q=author:Miguel_de_Prado:", "https://dblp.org/search/pid/api?q=author:Manuele_Rusci:", "https://dblp.org/search/pid/api?q=author:Romain_Donze:", "~Alessandro_Capotondi1", "https://dblp.org/search/pid/api?q=author:Serge_Monnerat:", "~Luca_Benini2", "https://dblp.org/search/pid/api?q=author:Nuria_Pazos:"], "html": "https://doi.org/10.1109/ISCAS51556.2021.9401154", "title": "Robustifying the Deployment of tinyML Models for Autonomous Mini-Vehicles", "paperhash": "prado|robustifying_the_deployment_of_tinyml_models_for_autonomous_minivehicles", "abstract": "Standard-size autonomous navigation vehicles have rapidly improved thanks to the breakthroughs of deep learning. However, scaling autonomous driving to low-power systems deployed on dynamic environments poses several challenges that prevent their adoption. To address them, we propose a closed- loop learning flow for autonomous driving mini-vehicles that includes the target environment in-the-loop. We leverage a family of compact and high-throughput tinyCNNs to control the mini- vehicle, which learn in the target environment by imitating a computer vision algorithm, i.e., the expert. Thus, the tinyCNNs, having only access to an on-board fast-rate linear camera, gain robustness to lighting conditions and improve over time. Further, we leverage GAP8, a parallel ultra-low-power RISC-V SoC, to meet the inference requirements. When running the family of CNNs, our GAP8's solution outperforms any other implementation on the STM32L4 and NXP k64f (Cortex-M4), reducing the latency by over 13x and the energy consummation by 92%.pdfhttps://ieeexplore.ieee.org/iel7/9401028/9401051/09401154.pdfsignatures~Luca_Benini2readerseveryonenonreaderswritersdblp.org |
| idxfdjz_e03pjoriginalnumbercdatepdatemdateddatetcdatetmdatetddateforumxfdjz_e03pjreplytoinvitationdblp.org/-/recordcontentvenueUbiComp/ISWC Adjunct 2021venueiddblp.org/conf/HUC/2021_bibtex@inproceedings{DBLP:conf/huc/BianL21,\n author={Sizhen Bian and Paul Lukowicz},\n title={Capacitive Sensing Based On-board Hand Gesture Recognition with TinyML},\n year={2021},\n cdate={1609459200000},\n pages={4-5},\n url={https://doi.org/10.1145/3460418.3479287},\n booktitle={UbiComp/ISWC Adjunct},\n crossref={conf/huc/2021ap},\n}\nauthorsSizhen BianPaul Lukowiczauthorids~Sizhen_Bian1https://dblp.org/search/pid/api?q=author:Paul_Lukowicz:htmlhttps://doi.org/10.1145/3460418.3479287titleCapacitive Sensing Based On-board Hand Gesture Recognition with TinyMLpaperhashbian|capacitive_sensing_based_onboard_hand_gesture_recognition_with_tinymlabstractAlthough hand gesture recognition has been widely explored with sensing modalities like IMU, electromyography and camera, it is still a challenge of those modalities to provide a compact, power-efficient on-board inferencing solution. In this work, we present a capacitive-sensing wristband surrounded by four single-end electrodes for on-board hand gesture recognition. By deploying a single convolutional hidden layer as the classifier at the sensing edge, the wristband can recognize seven hand gestures from a single user with an accuracy of 96.4%.signatures~Sizhen_Bian1readerseveryonenonreaderswritersdblp.org |
| id20w_lToBC5originalnumbercdatemdateddatetcdatetmdatetddateforum20w_lToBC5replytoinvitationdblp.org/-/recordcontentvenueISCAS 2021venueiddblp.org/conf/ISCAS/2021_bibtex@inproceedings{DBLP:conf/iscas/PradoRDCMBP21,\n author={Miguel de Prado and Manuele Rusci and Romain Donze and Alessandro Capotondi and Serge Monnerat and Luca Benini and Nuria Pazos},\n title={Robustifying the Deployment of tinyML Models for Autonomous Mini-Vehicles},\n year={2021},\n cdate={1609459200000},\n pages={1-5},\n url={https://doi.org/10.1109/ISCAS51556.2021.9401154},\n booktitle={ISCAS},\n crossref={conf/iscas/2021}\n}\nauthorsMiguel de PradoManuele RusciRomain DonzeAlessandro CapotondiSerge MonneratLuca BeniniNuria Pazosauthoridshttps://dblp.org/search/pid/api?q=author:Miguel_de_Prado:https://dblp.org/search/pid/api?q=author:Manuele_Rusci:https://dblp.org/search/pid/api?q=author:Romain_Donze:https://dblp.org/search/pid/api?q=author:Alessandro_Capotondi:https://dblp.org/search/pid/api?q=author:Serge_Monnerat:~Luca_Benini2https://dblp.org/search/pid/api?q=author:Nuria_Pazos:htmlhttps://doi.org/10.1109/ISCAS51556.2021.9401154titleRobustifying the Deployment of tinyML Models for Autonomous Mini-Vehiclespaperhashprado|robustifying_the_deployment_of_tinyml_models_for_autonomous_minivehiclesabstractStandard-size autonomous navigation vehicles have rapidly improved thanks to the breakthroughs of deep learning. However, scaling autonomous driving to low-power systems deployed on dynamic environments poses several challenges that prevent their adoption. To address them, we propose a closed- loop learning flow for autonomous driving mini-vehicles that includes the target environment in-the-loop. We leverage a family of compact and high-throughput tinyCNNs to control the mini- vehicle, which learn in the target environment by imitating a computer vision algorithm, i.e., the expert. Thus, the tinyCNNs, having only access to an on-board fast-rate linear camera, gain robustness to lighting conditions and improve over time. Further, we leverage GAP8, a parallel ultra-low-power RISC-V SoC, to meet the inference requirements. When running the family of CNNs, our GAP8's solution outperforms any other implementation on the STM32L4 and NXP k64f (Cortex-M4), reducing the latency by over 13x and the energy consummation by 92%.", "pdf": "https://ieeexplore.ieee.org/iel7/9401028/9401051/09401154.pdf"}, "signatures": ["~Luca_Benini2"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "zGvRdBW06F5", "original": "1zam04jRMON", "number": 2198, "cdate": 1652737358814, "mdate": null, "ddate": null, "tcdate": 1652737358814, "tmdate": 1770510480531, "tddate": null, "forum": "zGvRdBW06F5", "replyto": null, "invitation": "NeurIPS.cc/2022/Conference/-/Blind_Submission", "content": {"title": "On-Device Training Under 256KB Memory", "authorids": ["~Ji_Lin1", "~Ligeng_Zhu1", "~Wei-Ming_Chen1", "~Wei-Chen_Wang1", "~Chuang_Gan1", "~Song_Han5"], "authors": ["Ji Lin", "Ligeng Zhu", "Wei-Ming Chen", "Wei-Chen Wang", "Chuang Gan", "Song Han"], "keywords": ["on-device training", "tinyML", "tiny deep learning"], "TL;DR": "We propose the first framework for on-device training on tiny IoT devices, even under a limited memory budget of 256KB.", "abstract": "On-device training enables the model to adapt to new data collected from the sensors by fine-tuning a pre-trained model. Users can benefit from customized AI models without having to transfer the data to the cloud, protecting the privacy. However, the training memory consumption is prohibitive for IoT devices that have tiny memory resources. We propose an algorithm-system co-design framework to make on-device training possible with only 256KB of memory. On-device training faces two unique challenges: (1) the quantized graphs of neural networks are hard to optimize due to low bit-precision and the lack of normalization; (2) the limited hardware resource (memory and computation) does not allow full backpropagation. To cope with the optimization difficulty, we propose Quantization- Aware Scaling to calibrate the gradient scales and stabilize 8-bit quantized training. To reduce the memory footprint, we propose Sparse Update to skip the gradient computation of less important layers and sub-tensors. The algorithm innovation is implemented by a lightweight training system, Tiny Training Engine, which prunes the backward computation graph to support sparse updates and offload the runtime auto-differentiation to compile time. Our framework is the first practical solution for on-device transfer learning of visual recognition on tiny IoT devices (e.g., a microcontroller with only 256KB SRAM), using less than 1/1000 of the memory of PyTorch and TensorFlow while matching the accuracy. Our study enables IoT devices not only to perform inference but also to continuously adapt to new data for on-device lifelong learning. A video demo can be found here: https://youtu.be/XaDCO8YtmBw.", "paperhash": "lin|ondevice_training_under_256kb_memory", "pdf": "/pdf/442200720bf2d14debe720a048cf47d6cc9c59c3.pdf", "supplementary_material": "/attachment/13cb0e331edc4ff9d08caf77d52a24b20219ef52.pdf", "venue": "NeurIPS 2022 Accept", "venueid": "NeurIPS.cc/2022/Conference", "_bibtex": "@inproceedings{\nlin2022ondevice,\ntitle={On-Device Training Under 256{KB} Memory},\nauthor={Ji Lin and Ligeng Zhu and Wei-Ming Chen and Wei-Chen Wang and Chuang Gan and Song Han},\nbooktitle={Advances in Neural Information Processing Systems},\neditor={Alice H. Oh and Alekh Agarwal and Danielle Belgrave and Kyunghyun Cho},\nyear={2022},\nurl={https://openreview.net/forum?id=zGvRdBW06F5}\n}", "community_implementations": "[ 1 code implementation](https://www.catalyzex.com/paper/on-device-training-under-256kb-memory/code)"}, "signatures": ["NeurIPS.cc/2022/Conference"], "readers": ["everyone"], "nonreaders": [], "writers": ["NeurIPS.cc/2022/Conference"], "pdate": 1667239200000} |
| {"id": "_GcWoi0SQm", "original": "BicHhHVl5hb", "number": 6467, "cdate": 1663850572392, "mdate": null, "ddate": null, "tcdate": 1663850572392, "tmdate": 1676331000003, "tddate": null, "forum": "_GcWoi0SQm", "replyto": null, "invitation": "ICLR.cc/2023/Conference/-/Withdrawn_Submission", "content": {"title": "Free Bits: Platform-Aware Latency Optimization of Mixed-Precision Neural Networks for Edge Deployment", "authorids": ["~Georg_Martin_Rutishauser1", "f.conti@unibo.it", "~Luca_Benini1"], "authors": ["Georg Martin Rutishauser", "Francesco Conti", "Luca Benini"], "keywords": ["Edge AI", "TinyML", "Mixed-Precision Quantization"], "TL;DR": "By combining differentiable precision search with platform-aware heuristics, we can reduce end-to-end latency of DNNS running on microcontrollers by up to 29.2%.", "abstract": "Mixed-precision quantization, where a deep neural network's layers are quantized to different precisions, offers the opportunity to optimize the trade-offs between model size, latency, and statistical accuracy beyond what can be achieved with homogeneous-bit-width quantization.\nHowever, the search space for layer-wise quantization policies is intractable, and the execution latency of mixed-precision networks is related non-trivially and non-monotonically to precision, depending on the deployment target. This establishes the need for hardware-aware, directed heuristic search algorithms.\nThis paper proposes a hybrid search methodology for mixed-precision network configurations consisting of a hardware-agnostic differentiable search algorithm followed by a hardware-aware heuristic optimization to find mixed-precision configurations latency-optimized for a specific hardware target. We evaluate our algorithm on MobileNetV1 and MobileNetV2 and deploy the resulting networks on a family of multi-core RISC-V microcontroller platforms, each with different hardware characteristics. We achieve up to $29.2\\%$ reduction of end-to-end latency compared to an 8-bit model at a negligible accuracy drop from a full-precision baseline on the 1000-class ImageNet dataset. We demonstrate speedups relative to an 8-bit baseline even on systems with no hardware support for sub-byte arithmetic at zero accuracy drop. Furthermore, we show the superiority of our approach to both a purely heuristic search and differentiable search targeting reduced binary operation counts.anonymous_urlI certify that there is no URL (e.g., github page) that could be used to find authors’ identity.no_acknowledgement_sectionI certify that there is no acknowledgement section in this submission for double blind review.code_of_ethicsI acknowledge that I and all co-authors of this work have read and commit to adhering to the ICLR Code of Ethicssubmission_guidelinesYesresubmissionstudent_authorPlease_choose_the_closest_area_that_your_submission_falls_intoInfrastructure (eg, datasets, competitions, implementations, libraries)paperhashrutishauser|free_bits_platformaware_latency_optimization_of_mixedprecision_neural_networks_for_edge_deploymentpdf/pdf/6c1c5ccc42d70fac6dae65ce2ee9d2f924828296.pdf_bibtex@misc{\nrutishauser2023free,\ntitle={Free Bits: Platform-Aware Latency Optimization of Mixed-Precision Neural Networks for Edge Deployment},\nauthor={Georg Martin Rutishauser and Francesco Conti and Luca Benini},\nyear={2023},\nurl={https://openreview.net/forum?id=_GcWoi0SQm}\n}venuevenueidsignaturesICLR.cc/2023/ConferencereaderseveryonenonreaderswritersICLR.cc/2023/Conferencepdateodate |
| idCkzg9vKidN1originalnumbercdatemdateddatetcdatetmdatetddateforumCkzg9vKidN1replytoinvitationdblp.org/-/recordcontentvenueNeurIPS 2020venueiddblp.org/conf/NIPS/2020_bibtex@inproceedings{DBLP:conf/nips/CaiGZ020,\n author={Han Cai and Chuang Gan and Ligeng Zhu and Song Han},\n title={TinyTL: Reduce Memory, Not Parameters for Efficient On-Device Learning},\n year={2020},\n cdate={1577836800000},\n url={https://proceedings.neurips.cc/paper/2020/hash/81f7acabd411274fcf65ce2070ed568a-Abstract.html},\n booktitle={NeurIPS},\n crossref={conf/nips/2020}\n}\nauthorsHan CaiChuang GanLigeng ZhuSong Hanauthoridshttps://dblp.org/search/pid/api?q=author:Han_Cai:https://dblp.org/search/pid/api?q=author:Chuang_Gan:~Ligeng_Zhu1~Song_Han5htmlhttps://proceedings.neurips.cc/paper/2020/hash/81f7acabd411274fcf65ce2070ed568a-Abstract.htmltitleTinyTL: Reduce Memory, Not Parameters for Efficient On-Device Learningpaperhashcai|tinytl_reduce_memory_not_parameters_for_efficient_ondevice_learningabstractEfficient on-device learning requires a small memory footprint at training time to fit the tight memory constraint. Existing work solves this problem by reducing the number of trainable parameters. However, this doesn't directly translate to memory saving since the major bottleneck is the activations, not parameters. In this work, we present Tiny-Transfer-Learning (TinyTL) for memory-efficient on-device learning. TinyTL freezes the weights while only learns the memory-efficient bias modules, thus no need to store the intermediate activations. To maintain the adaptation capacity, we introduce a new memory-efficient bias module, the lite residual module, to refine the feature extractor by learning small residual feature maps adding only 3.8% memory overhead. Extensive experiments show that TinyTL significantly saves the memory (up to 6.5x) with little accuracy loss compared to fine-tuning the full network. Compared to fine-tuning the last layer, TinyTL provides significant accuracy improvements (up to 33.8%) with little memory overhead. Furthermore, combined with feature extractor adaptation, TinyTL provides 7.5-12.9x memory saving without sacrificing accuracy compared to fine-tuning the full Inception-V3. Code is released at https://github.com/mit-han-lab/tinyML/tree/master/tinyTL.", "pdf": "https://proceedings.neurips.cc/paper_files/paper/2020/file/81f7acabd411274fcf65ce2070ed568a-Paper.pdf"}, "signatures": ["~Ligeng_Zhu1"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "d0DXKtpvmgB", "original": null, "number": 717427, "cdate": 1609459200000, "pdate": 1609459200000, "mdate": 1683884435252, "ddate": null, "tcdate": 1683884435252, "tmdate": 1692937704333, "tddate": null, "forum": "d0DXKtpvmgB", "replyto": null, "invitation": "dblp.org/-/record", "content": {"venue": "CoRR 2021", "venueid": "dblp.org/journals/CORR/2021", "_bibtex": "@article{DBLP:journals/corr/abs-2107-02690,\n publtype={informal},\n author={Armin Moin and Atta Badii and Stephan Günnemann},\n title={Enabling Un-/Semi-Supervised Machine Learning for MDSE of the Real-World CPS/IoT Applications},\n year={2021},\n cdate={1609459200000},\n journal={CoRR},\n volume={abs/2107.02690},\n url={https://arxiv.org/abs/2107.02690},\n}\n", "authors": ["Armin Moin", "Atta Badii", "Stephan Günnemann"], "authorids": ["https://dblp.org/search/pid/api?q=author:Armin_Moin:", "https://dblp.org/search/pid/api?q=author:Atta_Badii:", "~Stephan_Günnemann1"], "html": "https://arxiv.org/abs/2107.02690", "title": "Enabling Un-/Semi-Supervised Machine Learning for MDSE of the Real-World CPS/IoT Applications", "paperhash": "moin|enabling_unsemisupervised_machine_learning_for_mdse_of_the_realworld_cpsiot_applications", "abstract": "Software engineering of network-centric Artificial Intelligence (AI) and Internet of Things (IoT) enabled Cyber-Physical Systems (CPS) and services, involves complex design and validation challenges. In this paper, we propose a novel approach, based on the model-driven software engineering paradigm, in particular the domain-specific modeling methodology. We focus on a sub-discipline of AI, namely Machine Learning (ML) and propose the delegation of data analytics and ML to the IoT edge. This way, we may increase the service quality of ML, for example, its availability and performance, regardless of the network conditions, as well as maintaining the privacy, security and sustainability. We let practitioners assign ML tasks to heterogeneous edge devices, including highly resource-constrained embedded microcontrollers with main memories in the order of Kilobytes, and energy consumption in the order of milliwatts. This is known as TinyML. Furthermore, we show how software models with different levels of abstraction, namely platform-independent and platform-specific models can be used in the software development process. Finally, we validate the proposed approach using a case study addressing the predictive maintenance of a hydraulics system with various networked sensors and actuators.", "pdf": "http://arxiv.org/pdf/2107.02690v2"}, "signatures": ["~Stephan_Günnemann1"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "-4AlFLBP353", "original": null, "number": 466858, "cdate": 1640995200000, "mdate": 1668013808597, "ddate": null, "tcdate": 1668013808597, "tmdate": 1669007207960, "tddate": null, "forum": "-4AlFLBP353", "replyto": null, "invitation": "dblp.org/-/record", "content": {"venue": "SAMOS 2022", "venueid": "dblp.org/conf/SAMOS/2022", "_bibtex": "@inproceedings{DBLP:conf/samos/NadaliniRTRBC22,\n author={Davide Nadalini and Manuele Rusci and Giuseppe Tagliavini and Leonardo Ravaglia and Luca Benini and Francesco Conti},\n title={PULP-TrainLib: Enabling On-Device Training for RISC-V Multi-core MCUs Through Performance-Driven Autotuning},\n year={2022},\n cdate={1640995200000},\n pages={200-216},\n url={https://doi.org/10.1007/978-3-031-15074-6_13},\n booktitle={SAMOS},\n crossref={conf/samos/2022}\n}\n", "authors": ["Davide Nadalini", "Manuele Rusci", "Giuseppe Tagliavini", "Leonardo Ravaglia", "Luca Benini", "Francesco Conti"], "authorids": ["https://dblp.org/search/pid/api?q=author:Davide_Nadalini:", "https://dblp.org/search/pid/api?q=author:Manuele_Rusci:", "https://dblp.org/search/pid/api?q=author:Giuseppe_Tagliavini:", "https://dblp.org/search/pid/api?q=author:Leonardo_Ravaglia:", "~Luca_Benini2", "https://dblp.org/search/pid/api?q=author:Francesco_Conti_0001:"], "html": "https://doi.org/10.1007/978-3-031-15074-6_13", "title": "PULP-TrainLib: Enabling On-Device Training for RISC-V Multi-core MCUs Through Performance-Driven Autotuning", "paperhash": "nadalini|pulptrainlib_enabling_ondevice_training_for_riscv_multicore_mcus_through_performancedriven_autotuning", "abstract": "An open challenge in making Internet-of-Things sensor nodes “smart” and self-adaptive is to enable on-chip Deep Neural Network (DNN) training on Ultra-Low-Power (ULP) microcontroller units (MCUs). To this aim, we present a framework, based on PULP-TrainLib, to deploy DNN training tasks on RISC-V-based Parallel-ULP (PULP) MCUs. PULP-TrainLib is a library of parallel software DNN primitives enabling the execution of forward and backward steps on PULP MCUs. To optimize PULP-TrainLib’s kernels, we propose a strategy to automatically select and configure (autotune) the fastest among a set of tiling options and optimized floating-point matrix multiplication kernels, according to the tensor shapes of every DNN layer. Results on an 8-core RISC-V MCU show that our auto-tuned primitives improve MAC/clk by up to 2.4 $$\\times $$ compared to “one-size-fits-all” matrix multiplication, achieving up to 4.39 MAC/clk - 36.6 $$\\times $$ better than a commercial STM32L4 MCU executing the same DNN layer training workload. Furthermore, our strategy proves to be 30.7 $$\\times $$ faster than AIfES, a state-of-the-art training library for MCUs, while training a complete TinyML model."}, "signatures": ["~Luca_Benini2"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "qZZ8GFIXd_", "original": null, "number": 13, "cdate": 1637812705362, "mdate": 1637812705362, "ddate": null, "tcdate": 1637812705362, "tmdate": 1637812705362, "tddate": null, "forum": "TYw3-OlrRm-", "replyto": "2UifWvizbnK", "invitation": "ICLR.cc/2022/Conference/Paper3904/-/Official_Comment", "content": {"title": "Thank you for the feedback. Our clarifications (1/4)", "comment": "Thanks for your additional feedback.\n\n> #### 1. The concepts of large or tiny depend on how we define them.\n\nWe politely yet firmly point out that your comments misread the problem setting of our paper. \n- **Tiny deep learning is an important research direction.** It targets on-device machine learning with resource-constrained edge devices (e.g., billions of IoT devices [1]). There is a rich research community [2,3,4,5] studying this problem, and it has many real-world applications, such as smart home, smart retail, smart manufacturing, etc. We are solving a very important challenge that has real-world impacts.\n- The size of a tiny neural network is determined by the actual hardware constraint, it's not a subjective concept. For instance, a microcontroller has only 1MB of Flash, therefore a tiny model should be smaller than 1MB. Our tiny model design is targeting real-world settings. \n- Though ResNet-50 can be somehow defined as a \ model compared with ViT_large, GPT3, it is too large to be deployed on IoT devices. Thus, it is not a tiny neural network in the context of our paper.\n\n**References**\n\n[1] https://www.statista.com/statistics/471264/iot-number-of-connected-devices-worldwide/\n\n[2] https://www.tinyml.org/\n\n[3] Lin, Ji, et al. “MCUNet: Tiny Deep Learning on IoT Devices.” Advances in Neural Information Processing Systems 33 (2020): 11711-11722.\n\n[4] Saha, Oindrila, et al. “RNNPool: Efficient Non-linear Pooling for RAM Constrained Inference.” Advances in Neural Information Processing Systems 33 (2020).\n\n[5] Banbury, Colby, et al. “Micronets: Neural network architectures for deploying tinyml applications on commodity microcontrollers.” Proceedings of Machine Learning and Systems 3 (2021).signaturesICLR.cc/2022/Conference/Paper3904/AuthorsreaderseveryonenonreaderswritersICLR.cc/2022/ConferenceICLR.cc/2022/Conference/Paper3904/AuthorsforumContent |
| idrQ_gRQZDsuoriginalnumbercdatemdateddatetcdatetmdatetddateforumrQ_gRQZDsureplytoinvitationdblp.org/-/recordcontentvenueMLSys 2021venueiddblp.org/conf/MLSYS/2021_bibtex@inproceedings{DBLP:conf/mlsys/BanburyZFNTGRMW21,\n author={Colby R. Banbury and Chuteng Zhou and Igor Fedorov and Ramon Matas Navarro and Urmish Thakker and Dibakar Gope and Vijay Janapa Reddi and Matthew Mattina and Paul N. Whatmough},\n title={MicroNets: Neural Network Architectures for Deploying TinyML Applications on Commodity Microcontrollers},\n year={2021},\n cdate={1609459200000},\n url={https://proceedings.mlsys.org/paper/2021/hash/a3c65c2974270fd093ee8a9bf8ae7d0b-Abstract.html},\n booktitle={MLSys},\n crossref={conf/mlsys/2021},\n}\nauthorsColby R. BanburyChuteng ZhouIgor FedorovRamon Matas NavarroUrmish ThakkerDibakar GopeVijay Janapa ReddiMatthew MattinaPaul N. Whatmoughauthorids~Colby_R._Banbury1https://dblp.org/search/pid/api?q=author:Chuteng_Zhou:https://dblp.org/search/pid/api?q=author:Igor_Fedorov:https://dblp.org/search/pid/api?q=author:Ramon_Matas_Navarro:https://dblp.org/search/pid/api?q=author:Urmish_Thakker:~Dibakar_Gope1~Vijay_Janapa_Reddi1https://dblp.org/search/pid/api?q=author:Matthew_Mattina:~Paul_N._Whatmough6htmlhttps://proceedings.mlsys.org/paper/2021/hash/a3c65c2974270fd093ee8a9bf8ae7d0b-Abstract.htmltitleMicroNets: Neural Network Architectures for Deploying TinyML Applications on Commodity Microcontrollerspaperhashbanbury|micronets_neural_network_architectures_for_deploying_tinyml_applications_on_commodity_microcontrollerssignatures~Colby_Banbury1readerseveryonenonreaderswritersdblp.org |
| idTkqde8772coriginalnumbercdatepdatemdateddatetcdatetmdatetddateforumTkqde8772creplytoinvitationdblp.org/-/recordcontentvenueCOMPSAC 2022venueiddblp.org/conf/COMPSAC/2022_bibtex@inproceedings{DBLP:conf/compsac/MoinCBG22,\n author={Armin Moin and Moharram Challenger and Atta Badii and Stephan Günnemann},\n title={Supporting AI Engineering on the IoT Edge through Model-Driven TinyML},\n year={2022},\n cdate={1640995200000},\n pages={884-893},\n url={https://doi.org/10.1109/COMPSAC54236.2022.00140},\n booktitle={COMPSAC},\n crossref={conf/compsac/2022},\n}\nauthorsArmin MoinMoharram ChallengerAtta BadiiStephan Günnemannauthoridshttps://dblp.org/search/pid/api?q=author:Armin_Moin:https://dblp.org/search/pid/api?q=author:Moharram_Challenger:https://dblp.org/search/pid/api?q=author:Atta_Badii:~Stephan_Günnemann1htmlhttps://doi.org/10.1109/COMPSAC54236.2022.00140titleSupporting AI Engineering on the IoT Edge through Model-Driven TinyMLpaperhashmoin|supporting_ai_engineering_on_the_iot_edge_through_modeldriven_tinymlabstractSoftware engineering of network-centric Artificial Intelligence (AI) and Internet of Things (IoT) enabled Cyber-Physical Systems (CPS) and services, involves complex design and validation challenges. In this paper, we propose a novel approach, based on the model-driven software engineering paradigm, in particular the domain-specific modeling methodology. We focus on a sub-discipline of AI, namely Machine Learning (ML) and propose the delegation of data analytics and ML to the IoT edge. This way, we may increase the service quality of ML, for example, its availability and performance, regardless of the network conditions, as well as maintaining the privacy, security and sustainability. We let practitioners assign ML tasks to heterogeneous edge devices, including highly resource-constrained embedded microcontrollers with main memories in the order of Kilobytes, and energy consumption in the order of milliwatts. This is known as Tiny ML. Furthermore, we show how software models with different levels of abstraction, namely platform-independent and platform-specific models can be used in the software development process. Finally, we validate the proposed approach using a case study addressing the predictive maintenance of a hydraulics system with various networked sensors and actuators.pdfhttps://ieeexplore.ieee.org/iel7/9842455/9842394/09842593.pdfsignatures~Stephan_Günnemann1readerseveryonenonreaderswritersdblp.org |
| id7n6SdxtfZjKoriginalnumbercdatemdateddatetcdatetmdatetddateforum0sEIBFb4csreplyto_XlEdq1U03binvitationICLR.cc/2022/Conference/Paper4282/-/Official_CommentcontenttitleSecond response to Reviewer n45GcommentWe would like to thank the reviewer for their feedback.\n\nRegarding adversarial training: we believe it is an important topic worth investigating as a standalone rather than a subpart of another work. Similar to the previous related work mentioned by the reviewer (Liu et al, 2021), in this paper we focus on designing adversarial attacks. \n\nRegarding tDSC: to the best of our knowledge, when the stimulation is small enough, it can be imperceptible on the EEG. We will be glad if the reviewer can kindly suggest related literature discussing the large electrical interference occurring at the bio-potential sensors within milliseconds of stimulation. We recognize that the realization of the specific adversarial attack designed by our algorithm needs further investigation.\n\nRegarding DeepConvNet: it performs slightly worse than ShallowConvNet in terms of classification accuracy, which performs similarly to EEGNet, while requiring orders of magnitude more resources in terms of memory and computation. Since our focus is oriented towards embedded BCI in the field of tinyML, we chose the most energy-efficient model and did not consider DeepConvNet. However, we believe our methods can be easily adapted to other deep learning models.\n\nRegarding comparisons to related works: as mentioned in the general response, besides other baselines, we also reproduced the methods by Liu et al (2021) to compare to our approach. The results are added to Figure 1 and show that our method yields up to 16.5% more attack success rate than (Liu et al., 2021). \n\nRegarding the dataset for subject-specific validation: we chose the IV 2a dataset from the BCI Competition for subject-specific validation due to its popularity for this kind of studies in BCI. Reviewer 2xxQ also requested to validate our methods on another dataset, hence, we chose to do subject-specific studies on BCI Competition IV 2a. signaturesICLR.cc/2022/Conference/Paper4282/AuthorsreaderseveryonenonreaderswritersICLR.cc/2022/ConferenceICLR.cc/2022/Conference/Paper4282/AuthorsforumContent |
| idl-Z5VdKOmvzoriginalnumbercdatepdatemdateddatetcdatetmdatetddateforuml-Z5VdKOmvzreplytoinvitationdblp.org/-/recordcontentvenueCODES+ISSS 2021venueiddblp.org/conf/CODES/2021_bibtex@inproceedings{DBLP:conf/codes/0001EFFG0HKMBP021,\n author={Oliver Bringmann and Wolfgang Ecker and Ingo Feldner and Adrian Frischknecht and Christoph Gerum and Timo Hämäläinen and Muhammad Abdullah Hanif and Michael J. Klaiber and Daniel Mueller-Gritschneder and Paul Palomero Bernardo and Sebastian Siegfried Prebeck and Muhammad Shafique},\n title={Automated HW/SW co-design for edge AI: state, challenges and steps ahead},\n year={2021},\n cdate={1609459200000},\n pages={11-20},\n url={https://doi.org/10.1145/3478684.3479261},\n booktitle={CODES+ISSS},\n crossref={conf/codes/2021},\n}\nauthorsOliver BringmannWolfgang EckerIngo FeldnerAdrian FrischknechtChristoph GerumTimo HämäläinenMuhammad Abdullah HanifMichael J. KlaiberDaniel Mueller-GritschnederPaul Palomero BernardoSebastian Siegfried PrebeckMuhammad Shafiqueauthorids~Oliver_Bringmann1https://dblp.org/search/pid/api?q=author:Wolfgang_Ecker:https://dblp.org/search/pid/api?q=author:Ingo_Feldner:https://dblp.org/search/pid/api?q=author:Adrian_Frischknecht:https://dblp.org/search/pid/api?q=author:Christoph_Gerum:https://dblp.org/search/pid/api?q=author:Timo_Hämäläinen_0001:~Muhammad_Abdullah_Hanif1https://dblp.org/search/pid/api?q=author:Michael_J._Klaiber:~Daniel_Mueller-Gritschneder1https://dblp.org/search/pid/api?q=author:Paul_Palomero_Bernardo:https://dblp.org/search/pid/api?q=author:Sebastian_Siegfried_Prebeck:~Muhammad_Shafique1htmlhttps://doi.org/10.1145/3478684.3479261titleAutomated HW/SW co-design for edge AI: state, challenges and steps aheadpaperhashbringmann|automated_hwsw_codesign_for_edge_ai_state_challenges_and_steps_aheadabstractGigantic rates of data production in the era of Big Data, Internet of Thing (IoT), and Smart Cyber Physical Systems (CPS) pose incessantly escalating demands for massive data processing, storage, and transmission while continuously interacting with the physical world using edge sensors and actuators. For IoT systems, there is now a strong trend to move the intelligence from the cloud to the edge or the extreme edge (known as TinyML). Yet, this shift to edge AI systems requires to design powerful machine learning systems under very strict resource constraints. This poses a difficult design task that needs to take the complete system stack from machine learning algorithm, to model optimization and compression, to software implementation, to hardware platform and ML accelerator design into account. This paper discusses the open research challenges to achieve such a holistic Design Space Exploration for a HW/SW Co-design for Edge AI Systems and discusses the current state with three currently developed flows: one design flow for systems with tightly-coupled accelerator architectures based on RISC-V, one approach using loosely-coupled, application-specific accelerators as well as one framework that integrates software and hardware optimization techniques to built efficient Deep Neural Network (DNN) systems.pdfhttps://dl.acm.org/doi/pdf/10.1145/3478684.3479261signatures~Muhammad_Abdullah_Hanif1readerseveryonenonreaderswritersdblp.org |
| idntay434GQporiginalnumbercdatepdatemdateddatetcdatetmdatetddateforumntay434GQpreplytoinvitationdblp.org/-/recordcontentvenueCSCWD 2023venueiddblp.org/conf/CSCWD/2023_bibtex@inproceedings{DBLP:conf/cscwd/0011LWLWZ23,\n author={Chen Yang and Zou Lai and Yingchao Wang and Shulin Lan and Lihui Wang and Liehuang Zhu},\n title={A Novel Bearing Fault Diagnosis Method based on Stacked Autoencoder and End-edge Collaboration},\n year={2023},\n cdate={1672531200000},\n pages={393-398},\n url={https://doi.org/10.1109/CSCWD57460.2023.10152598},\n booktitle={CSCWD},\n crossref={conf/cscwd/2023},\n}\nauthorsChen YangZou LaiYingchao WangShulin LanLihui WangLiehuang Zhuauthoridshttps://dblp.org/search/pid/api?q=author:Chen_Yang_0011:https://dblp.org/search/pid/api?q=author:Zou_Lai:~Yingchao_Wang1https://dblp.org/search/pid/api?q=author:Shulin_Lan:https://dblp.org/search/pid/api?q=author:Lihui_Wang_0001:~Liehuang_Zhu1htmlhttps://doi.org/10.1109/CSCWD57460.2023.10152598titleA Novel Bearing Fault Diagnosis Method based on Stacked Autoencoder and End-edge Collaborationpaperhashyang|a_novel_bearing_fault_diagnosis_method_based_on_stacked_autoencoder_and_endedge_collaborationabstractThe deep learning based fault diagnosis methods show excellent performance. However, cost and delay factors make it difficult for their widespread industrial application. Microcontroller units (MCUs) in industrial equipment have the advantages of real-time response and high reliability and usually have some redundant computational resource. However, even lightweight deep learning models cannot be deployed in MCUs due to severely limited computational resources. This paper proposes an end-edge collaborative fault diagnosis framework, by combining real-time decision-making at the end with dynamic adaptive diagnosis at the edge to improve inference performance. The model’s minimum input size is deduced through theoretical analysis of the bearing working mechanism, and to make the model suitable for MCUs, we leverage the differential characteristics of the bearing vibration data and proposed a TinyML model based on stacked autoencoders. The pre-autoencoder extracts differential features, while the post-autoencoder performs fault diagnosis based on pooled differential features. Finally, the stacked-autoencoder model and collaborative framework were evaluated using the CWRU bearing dataset, achieving 384x compression in parameter size and 100% accuracy for binary fault classification, requiring only 6.44kB RAM. With the dynamic adaptive collaboration mechanism, the proposed fault diagnosis framework can reduce the edge load by approximately 94%.pdfhttps://ieeexplore.ieee.org/iel7/10152543/10151991/10152598.pdfsignatures~Yingchao_Wang1readerseveryonenonreaderswritersdblp.org |
| idm06kjYCejcdoriginalnumbercdatepdatemdateddatetcdatetmdatetddateforumm06kjYCejcdreplytoinvitationdblp.org/-/recordcontentvenueCoRR 2023venueiddblp.org/journals/CORR/2023_bibtex@article{DBLP:journals/corr/abs-2311-01759,\n publtype={informal},\n author={Jianlei Yang and Jiacheng Liao and Fanding Lei and Meichen Liu and Junyi Chen and Lingkun Long and Han Wan and Bei Yu and Weisheng Zhao},\n title={TinyFormer: Efficient Transformer Design and Deployment on Tiny Devices},\n year={2023},\n cdate={1672531200000},\n journal={CoRR},\n volume={abs/2311.01759},\n url={https://doi.org/10.48550/arXiv.2311.01759},\n}\nauthorsJianlei YangJiacheng LiaoFanding LeiMeichen LiuJunyi ChenLingkun LongHan WanBei YuWeisheng Zhaoauthorids~Jianlei_Yang1https://dblp.org/search/pid/api?q=author:Jiacheng_Liao:https://dblp.org/search/pid/api?q=author:Fanding_Lei:https://dblp.org/search/pid/api?q=author:Meichen_Liu:https://dblp.org/search/pid/api?q=author:Junyi_Chen:https://dblp.org/search/pid/api?q=author:Lingkun_Long:https://dblp.org/search/pid/api?q=author:Han_Wan:https://dblp.org/search/pid/api?q=author:Bei_Yu_0001:https://dblp.org/search/pid/api?q=author:Weisheng_Zhao:htmlhttps://doi.org/10.48550/arXiv.2311.01759titleTinyFormer: Efficient Transformer Design and Deployment on Tiny Devicespaperhashyang|tinyformer_efficient_transformer_design_and_deployment_on_tiny_devicesabstractDeveloping deep learning models on tiny devices (e.g. Microcontroller units, MCUs) has attracted much attention in various embedded IoT applications. However, it is challenging to efficiently design and deploy recent advanced models (e.g. transformers) on tiny devices due to their severe hardware resource constraints. In this work, we propose TinyFormer, a framework specifically designed to develop and deploy resource-efficient transformers on MCUs. TinyFormer mainly consists of SuperNAS, SparseNAS and SparseEngine. Separately, SuperNAS aims to search for an appropriate supernet from a vast search space. SparseNAS evaluates the best sparse single-path model including transformer architecture from the identified supernet. Finally, SparseEngine efficiently deploys the searched sparse models onto MCUs. To the best of our knowledge, SparseEngine is the first deployment framework capable of performing inference of sparse models with transformer on MCUs. Evaluation results on the CIFAR-10 dataset demonstrate that TinyFormer can develop efficient transformers with an accuracy of $96.1\\%$ while adhering to hardware constraints of $1$MB storage and $320$KB memory. Additionally, TinyFormer achieves significant speedups in sparse inference, up to $12.2\\times$, when compared to the CMSIS-NN library. TinyFormer is believed to bring powerful transformers into TinyML scenarios and greatly expand the scope of deep learning applications.pdfhttp://arxiv.org/pdf/2311.01759v1signatures~Jianlei_Yang1readerseveryonenonreaderswritersdblp.org |
| idERhIA5Y7IaToriginalToW4mEwG6C3numbercdateddatetcdatetmdatetddateforumERhIA5Y7IaTreplytoinvitationtinyml.org/tinyML/2021/Research_Symposium/-/Blind_SubmissioncontenttitleMini-NAS: A Neural Architecture Search Framework for Small Scale Image Classification Applicationsauthorids~Shahid_Siddiqui1~Christos_Kyrkou1~Theocharis_Theocharides1authorsShahid SiddiquiChristos KyrkouTheocharis TheocharideskeywordsTinyML DatasetsNeural Architecture SearchSearch SpacesTiny AutoMLImage ClassificationConvolutional NetworksTL;DRThis work proposes a suit 30 of small scale image classification datasets and a NAS framework that can discover high accuracy high efficiency networks for various datasets including CIFAR-10.abstractNeural architecture search (NAS) has shown promising results on image classification datasets such as CIFAR-10 and ImageNet. The desire for higher accuracy coupled with the need for computationally affordable NAS, solely for these benchmarks however, has had a profound effect on the design of NAS search spaces and algorithms. Many real world use cases on the other hand, may not always come with datasets as large as ImageNet or even CIFAR-10 and the required network sizes may only be a few hundred KBs, therefore, the optimizations done to speed up NAS may not be ideal for these. For instance, modular search spaces reduce search complexity as compared to global ones but offer only partial network discovery and a fine grain control over network efficiency is lost. Similarly, a transition from algorithms searching in discrete search spaces to continuous ones brings significant efficiency gains but reward signals in the former provide more confident search directions. In this work, we first present a suit of 30 image classification datasets that mimics possible real world use cases. Next, we present a powerful yet minimal global search space that contains all vital ingredients to create structurally diverse still parameter efficient networks. Lastly, we propose an algorithm that can efficiently navigate a huge discrete search space and is specifically tailored for discovering high accuracy, low complexity tiny convolution networks. The proposed NAS system, Mini-NAS, on average, discovers 14.7x more parameter efficient networks for 30 datasets as compared to MobileNetV2 while achieving on par accuracy. On CIFAR-10, Mini-NAS discovers a model that is 2.3x, 1.9x and 1.2x smaller than the smallest models discovered by RL, gradient-based and evolutionary NAS methods respectively while the search cost is only 2.4 days.pdf/pdf/045b4f72b0b2711957b8f8d41371d04a9aea5cb1.pdfpaperhashsiddiqui|mininas_a_neural_architecture_search_framework_for_small_scale_image_classification_applications_bibtex@misc{\nsiddiqui2021mininas,\ntitle={Mini-{\\{}NAS{\\}}: A Neural Architecture Search Framework for Small Scale Image Classification Applications},\nauthor={Shahid Siddiqui and Christos Kyrkou and Theocharis Theocharides},\nyear={2021},\nurl={https://openreview.net/forum?id=ERhIA5Y7IaT}\n}signaturestinyml.org/tinyML/2021/Research_Symposiumreaderseveryonenonreaderswriterstinyml.org/tinyML/2021/Research_Symposiumodate |
| idTbs8ORY1yk7originalnumbercdateddatetcdatetmdatetddateforumzGvRdBW06F5replyto99ibPJaWTBIinvitationNeurIPS.cc/2022/Conference/Paper2198/-/Official_CommentcontenttitleAuthor ResponsecommentWe thank reviewer xaNn’s useful comments and would like to respond as follows:\n\n**Q1: Can the proposed methods generalize to other commodity devices (e.g., NVIDIA Jetson or Neural chips, not just STM series)? Does the sparse update rely on specific chips to achieve true speedup?**\n\n- **The int8 operations are well-supported on commodity devices**: The int8 operations used in our method follow a standard TF-Lite protocol [33]. It is not specific to the STM series; instead, it is widely supported on a wide range of hardware like NVIDIA GPUs (CUDA Cores, Tensor Cores), Arm CPUs, Intel’s CPUs, Qualcomm’s SoCs, etc. Therefore, our quantized training method is general and can be extended to different devices.\n- **Our techniques can bring general speedup**: The other components like sparse update, compile-time differentiation, backward graph pruning, operator reordering, etc. are not specific to any device or platform. They are general techniques to make on-device adaptation more efficient and do not require special support from the underlying hardware.\n- **Speedup from the sparse update on more edge platforms**: Our sparse update uses channel/op level sparsity and does **not** involve fine-grained sparsity. Therefore it can accelerate training on various hardware platforms. We report the latency (ms) of training MobilenetV2-0.35 with Tiny Training Engie (TTE) using input size 1x3x128x128 in the following table. Our sparse update scheme shows consistent speedup (1.4x-3.0x) over conventional dense/full update while maintaining the same accuracy.\n\n| | Dense-Update | Sparse Update (ours) | Speedup |\n|---------------------|:------------:|----------------------|:-------:|\n| Raspberry Pi CPU | 74.0ms | 24.4ms | 3.0x |\n| Qualcomm S8Gen1 CPU | 39.9ms | 28.4ms | 1.4x |\n| Jetson Nano GPU | 5.2ms | 2.8ms | 1.8x |\n\n**Q2: The performance of segmentation and detection tasks.**\n\nTinyML suffers from an extremely small memory size. It is very difficult to support even the **inference** of applications like segmentation and object detection [47] because of the large input resolution. For example, a single 640x640x3 image (a widely used resolution for the MSCOCO dataset) takes 1200 kB to store and already exceeds the available memory on a microcontroller (320KB), let alone the cost for neural networks’ forward and backward. Segmentation and detection need special designs to handle the large resolution challenge, and we leave it for future work.\n\n**Q3: Can this method train from scratch instead of fine-tuning the pre-trained models?** \n\nOur method can also support training from scratch. Experiments in supplementary Section K show that our QAS (with pre-measured weight and activation ranges) is still effective for these non-transfer learning scenarios: training with QAS consistently improves the average accuracy on 8 datasets from 48.3% to 65.4%. Please refer to Section K for details.\n\n |Method | Average of Other Datasets | Cars |CF10 |CF100 |CUB |Flowers |Foods | Pets |VWW | \n|---------------------|:------------:|:------------:|:------------:|:------------:|:------------:|:------------:|:------------:|:------------:|:------------:|\n| SGD-M | 48.3 | 15.8 | 63.5 | 41.0 |30.3 |69.8 | 34.1 |52.5 | 79.2 |\n| SGD-M+QAS | 65.4 | 52.0 |85.5 |58.7 |47.1 |78.2 |53.1 |63.3 |85.6 | \n\n\n\n\n\nWe use pre-training because it usually delivers better performance on downstream tasks compared to training from scratch. Recent lifelong learning work [a, b] also performed fine-tuning from pre-trained weights rather than training from scratch.\n\n[a] Mehta et al., An Empirical Investigation of the Role of Pre-training in Lifelong Learning\n\n[b] Wang et al., Learning to Prompt for Continual Learning\n\n**Q4: Show the training speed or time cost when applying to the downstream tasks.**\n\nWe have provided the training latency in Figure 9(c). Compared with baselines, our method achieves more than 20x training speed up. For example, it takes 325ms to update MobileNetV2-w0.35 on one image, which is 29x faster than the existing baseline (9456ms). So if a new sample comes in, we can finish the training within a second for a timely update.\n\nFor tinyML applications, we usually need a small number of samples for training, so the total training time is also modest. For example, we have built a real demo of fine-tuning the model for a new task (Visual Wake Words) with 100 training images in supplementary Section A. The total training time for MobileNetV2-w0.35 would be just 33s, well within a minute. Given the modest total training time, we believe our framework can enable a vast range of realistic low-power on-device training applications.signaturesNeurIPS.cc/2022/Conference/Paper2198/AuthorsreaderseveryonenonreaderswritersNeurIPS.cc/2022/ConferenceNeurIPS.cc/2022/Conference/Paper2198/AuthorsforumContent |
| idYDZnw8GwGooriginalnumbercdatemdateddatetcdatetmdatetddateforumOhytAdNSzO-replytoGsnH291vdErinvitationICLR.cc/2022/Conference/Paper687/-/Official_CommentcontenttitleResponse to Reviewer zFw4comment> + Q1: Biggest concern about this paper is novelty. It has some good findings, it shows good numbers, and it also teaches us something. However, the method (for search) is based on existing work, the application to other devices is quite straightforward (though surely requires a lot of hard work), and to me, it is more like a technical report about something is well executed, rather than an interesting \ that has a good deal of scientific merit.\n\nA1: Thank you for appreciating our findings inside this work and the corresponding “usefulness and practical friendness”! We humbly clarify that we did not claim the novelty of the method (for search), and instead our main contribution is the study and analysis of the scaled architectures and their corresponding transferability across different devices, ViT variants, and recognition tasks (i.e., the “usefulness and practical friendness” mentioned by you). For example, we show that a scaled vanilla ViT model without bells and whistles can achieve comparable or superior accuracy-efficiency trade-off than most of the latest ViT variants, which can provide a new perspective for designing ViTs with more favorable accuracy-efficiency trade-offs. \n\nFurthermore, we hope to humbly remind that our work’s contributions, including your mentioned “usefulness and practical friendliness” and “it is even a good learning experience for me” as well as Reviewer WMJX’s comment of “the analysis of the transferability of different scaling strategies on different hardware devices in this work is very positive and provides great inspiration to relevant fields”, match the ICLR criterion of “bring value to the ICLR community when they convincingly demonstrate new, relevant, impactful knowledge” mentioned in the ICLR Reviewer Guide. Finally, as we all recognize, there are quite many works (e.g., [5,6,7,8]) which share a similar goal of providing insights and usefulness to the community as our work, have been published in first-tier machine learning conferences like ICLR, and they have enhanced our understanding and inspired further innovations. \n\n> + Q2: One more concern is about the word \. I don't think the study presented in this paper is about \"scaling\". To me the scaling is more about methods that scales up to larger models -- when people say about doing things \"at scale\", it indicates at \"a large\" scale. I come with the expectation that this paper can show how to scale our existing model to the next generation of model size, but only to find this paper is more about \"speed-accuracy\" trade-offs. So I would recommend replacing the term \"scale\" with \"speed-accuracy trade-off\" to be precise.\n\nA2: Thank you for your comment! While your mentioned “how to scale our existing model to the next generation of model size” is an important problem, we would like to humbly point out that scaling the models **down** is equally useful for deploying them into resource-constrained daily-life devices [1,2,3,4], which is one of our exploration goals, e.g., “can these scaling strategies be transferred across different real hardware devices?”. As such, in our humble opinion, the “scaling” terminology still holds for our work as we consider both scaling up and down ViTs. We will better clarify in our final version.\n\n*[1] Lin, Ji, et al. \"Memory-efficient Patch-based Inference for Tiny Deep Learning.\" Thirty-Fifth Conference on Neural Information Processing Systems, 2021.*\n\n*[2] David, Robert, et al. \"Tensorflow lite micro: Embedded machine learning on tinyml systems.\" arXiv preprint arXiv:2010.08678 (2020).*\n\n*[3] Banbury, Colby, et al. \"Micronets: Neural network architectures for deploying tinyml applications on commodity microcontrollers.\" Proceedings of Machine Learning and Systems 3 (2021).*\n\n*[4] Coiffier, Guillaume, Ghouthi Boukli Hacene, and Vincent Gripon. \"ThriftyNets: Convolutional Neural Networks with Tiny Parameter Budget.\" IoT 2.2 (2021): 222-235.*\n\n*[5] Neyshabur, Behnam, Hanie Sedghi, and Chiyuan Zhang. \"What is being transferred in transfer learning?.\" Thirty-Fourth Conference on Neural Information Processing Systems. 2020.*\n\n*[6] Nguyen, Thao, Maithra Raghu, and Simon Kornblith. \"Do wide and deep networks learn the same things? uncovering how neural network representations vary with width and depth.\" International Conference on Learning Representations, 2021.*\n\n*[7] Recht, Benjamin, et al. \"Do imagenet classifiers generalize to imagenet?.\" International Conference on Machine Learning. PMLR, 2019.*\n\n*[8] Ying, Chris, et al. \"Nas-bench-101: Towards reproducible neural architecture search.\" International Conference on Machine Learning. PMLR, 2019.*\n"}, "signatures": ["ICLR.cc/2022/Conference/Paper687/Authors"], "readers": ["everyone"], "nonreaders": [], "writers": ["ICLR.cc/2022/Conference", "ICLR.cc/2022/Conference/Paper687/Authors"], "forumContent": {}} |
| {"id": "5xH5iw44xTN", "original": null, "number": 652546, "cdate": 1609459200000, "mdate": 1682346403791, "ddate": null, "tcdate": 1682346403791, "tmdate": 1747384501573, "tddate": null, "forum": "5xH5iw44xTN", "replyto": null, "invitation": "dblp.org/-/record", "content": {"venue": "CoRR 2021", "venueid": "dblp.org/journals/CORR/2021", "_bibtex": "@article{DBLP:journals/corr/abs-2110-15352,\n publtype={informal},\n author={Ji Lin and Wei-Ming Chen and Han Cai and Chuang Gan and Song Han},\n title={MCUNetV2: Memory-Efficient Patch-based Inference for Tiny Deep Learning},\n year={2021},\n cdate={1609459200000},\n journal={CoRR},\n volume={abs/2110.15352},\n url={https://arxiv.org/abs/2110.15352},\n}\n", "authors": ["Ji Lin", "Wei-Ming Chen", "Han Cai", "Chuang Gan", "Song Han"], "authorids": ["https://dblp.org/search/pid/api?q=author:Ji_Lin_0002:", "~Wei-Ming_Chen1", "https://dblp.org/search/pid/api?q=author:Han_Cai:", "https://dblp.org/search/pid/api?q=author:Chuang_Gan:", "~Song_Han5"], "html": "https://arxiv.org/abs/2110.15352", "title": "MCUNetV2: Memory-Efficient Patch-based Inference for Tiny Deep Learning", "paperhash": "lin|mcunetv2_memoryefficient_patchbased_inference_for_tiny_deep_learning", "abstract": "Tiny deep learning on microcontroller units (MCUs) is challenging due to the limited memory size. We find that the memory bottleneck is due to the imbalanced memory distribution in convolutional neural network (CNN) designs: the first several blocks have an order of magnitude larger memory usage than the rest of the network. To alleviate this issue, we propose a generic patch-by-patch inference scheduling, which operates only on a small spatial region of the feature map and significantly cuts down the peak memory. However, naive implementation brings overlapping patches and computation overhead. We further propose network redistribution to shift the receptive field and FLOPs to the later stage and reduce the computation overhead. Manually redistributing the receptive field is difficult. We automate the process with neural architecture search to jointly optimize the neural architecture and inference scheduling, leading to MCUNetV2. Patch-based inference effectively reduces the peak memory usage of existing networks by 4-8x. Co-designed with neural networks, MCUNetV2 sets a record ImageNet accuracy on MCU (71.8%), and achieves >90% accuracy on the visual wake words dataset under only 32kB SRAM. MCUNetV2 also unblocks object detection on tiny devices, achieving 16.9% higher mAP on Pascal VOC compared to the state-of-the-art result. Our study largely addressed the memory bottleneck in tinyML and paved the way for various vision applications beyond image classification.", "pdf": "http://arxiv.org/pdf/2110.15352v1"}, "signatures": ["~Wei-Ming_Chen1"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "la1uhe7PkSI", "original": null, "number": 652547, "cdate": 1609459200000, "mdate": 1682346403800, "ddate": null, "tcdate": 1682346403800, "tmdate": 1747384501464, "tddate": null, "forum": "la1uhe7PkSI", "replyto": null, "invitation": "dblp.org/-/record", "content": {"venue": "NeurIPS 2021", "venueid": "dblp.org/conf/NIPS/2021", "_bibtex": "@inproceedings{DBLP:conf/nips/LinCCGH21,\n author={Ji Lin and Wei-Ming Chen and Han Cai and Chuang Gan and Song Han},\n title={Memory-efficient Patch-based Inference for Tiny Deep Learning},\n year={2021},\n cdate={1609459200000},\n pages={2346-2358},\n url={https://proceedings.neurips.cc/paper/2021/hash/1371bccec2447b5aa6d96d2a540fb401-Abstract.html},\n booktitle={NeurIPS},\n crossref={conf/nips/2021},\n}\n", "authors": ["Ji Lin", "Wei-Ming Chen", "Han Cai", "Chuang Gan", "Song Han"], "authorids": ["https://dblp.org/search/pid/api?q=author:Ji_Lin_0002:", "~Wei-Ming_Chen1", "https://dblp.org/search/pid/api?q=author:Han_Cai:", "https://dblp.org/search/pid/api?q=author:Chuang_Gan:", "~Song_Han5"], "html": "https://proceedings.neurips.cc/paper/2021/hash/1371bccec2447b5aa6d96d2a540fb401-Abstract.html", "title": "Memory-efficient Patch-based Inference for Tiny Deep Learning", "paperhash": "lin|memoryefficient_patchbased_inference_for_tiny_deep_learning", "abstract": "Tiny deep learning on microcontroller units (MCUs) is challenging due to the limited memory size. We find that the memory bottleneck is due to the imbalanced memory distribution in convolutional neural network (CNN) designs: the first several blocks have an order of magnitude larger memory usage than the rest of the network. To alleviate this issue, we propose a generic patch-by-patch inference scheduling, which operates only on a small spatial region of the feature map and significantly cuts down the peak memory. However, naive implementation brings overlapping patches and computation overhead. We further propose receptive field redistribution to shift the receptive field and FLOPs to the later stage and reduce the computation overhead. Manually redistributing the receptive field is difficult. We automate the process with neural architecture search to jointly optimize the neural architecture and inference scheduling, leading to MCUNetV2. Patch-based inference effectively reduces the peak memory usage of existing networks by4-8×. Co-designed with neural networks, MCUNetV2 sets a record ImageNetaccuracy on MCU (71.8%) and achieves >90% accuracy on the visual wake words dataset under only 32kB SRAM. MCUNetV2 also unblocks object detection on tiny devices, achieving 16.9% higher mAP on Pascal VOC compared to the state-of-the-art result. Our study largely addressed the memory bottleneck in tinyML and paved the way for various vision applications beyond image classification.", "pdf": "https://proceedings.neurips.cc/paper_files/paper/2021/file/1371bccec2447b5aa6d96d2a540fb401-Paper.pdf"}, "signatures": ["~Wei-Ming_Chen1"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "WdWAIYwDqFY", "original": null, "number": 518441, "cdate": 1640995200000, "mdate": 1668511357367, "ddate": null, "tcdate": 1668511357367, "tmdate": 1691002581067, "tddate": null, "forum": "WdWAIYwDqFY", "replyto": null, "invitation": "dblp.org/-/record", "content": {"venue": "AICAS 2022", "venueid": "dblp.org/conf/AICAS/2022", "_bibtex": "@inproceedings{DBLP:conf/aicas/GiordanoPM22,\n author={Marco Giordano and Luigi Piccinelli and Michele Magno},\n title={Survey and Comparison of Milliwatts Micro controllers for Tiny Machine Learning at the Edge},\n year={2022},\n cdate={1640995200000},\n pages={94-97},\n url={https://doi.org/10.1109/AICAS54282.2022.9870017},\n booktitle={AICAS},\n crossref={conf/aicas/2022}\n}\n", "authors": ["Marco Giordano", "Luigi Piccinelli", "Michele Magno"], "authorids": ["https://dblp.org/search/pid/api?q=author:Marco_Giordano:", "~Luigi_Piccinelli1", "https://dblp.org/search/pid/api?q=author:Michele_Magno:"], "html": "https://doi.org/10.1109/AICAS54282.2022.9870017", "title": "Survey and Comparison of Milliwatts Micro controllers for Tiny Machine Learning at the Edge", "paperhash": "giordano|survey_and_comparison_of_milliwatts_micro_controllers_for_tiny_machine_learning_at_the_edge", "abstract": "Low power Internet of Things devices are growing in number and computational capabilities, pushing to ubiquitous deployment of smart sensors that embed on board both the sensing and the processing. Thus, one of the most emerging requirements of such devices is to provide intelligence in resource-constrained processors that consume few milliwatts of power. This work focuses on surveying, comparing and evaluating seven different recent and popular microcontrollers with a power envelope from a few up to hundreds of milliwatts against a Convolutional Neural Networks workload for a non trivial task such as face recognition. The evaluation reports key points of tiny machine learning performance of the target microcontrollers in terms of inference time, power consumption, energy per inference and computational efficiency. Experimental results highlight best-in-class power consumption for Ambiq Apollo3 and Sony Spresense at 41.3 μW/MHz and 128.2 μW/MHz respectively. The computational efficiency primacy goes instead to the MAX78000 and then to xCORE.ai at 117 MAC/cycle and 7.69 MAC/cycle respectively, achieving the fastest inference at 1.4 ms and 1.5 ms respectively. The platforms that required the least energy per inference were the MAX78000 and GAP8, at 0.09 mJ/inference and 0.52 mJ/inference respectively. The benchmarked tinyML network will be released openly to allow other researchers to run future comparisons on novel low power microprocessors.", "pdf": "https://ieeexplore.ieee.org/iel7/9869844/9869845/09870017.pdf"}, "signatures": ["~Luigi_Piccinelli1"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "hw6s-qry_qx", "original": null, "number": 18274, "cdate": 1683882255414, "mdate": 1683882255414, "ddate": null, "tcdate": 1683882255414, "tmdate": 1683882255414, "tddate": null, "forum": "hw6s-qry_qx", "replyto": null, "invitation": "OpenReview.net/Archive/-/Direct_Upload", "content": {"title": "Survey and Comparison of Milliwatts Micro controllers for Tiny Machine Learning at the Edge", "authorids": ["~Marco_Giordano1", "~Luigi_Piccinelli1", "~Michele_Magno1"], "authors": ["Marco Giordano", "Luigi Piccinelli", "Michele Magno"], "abstract": "Low power Internet of Things devices are growing in number and computational capabilities, pushing to ubiquitous deployment of smart sensors that embed on board both the sensing and the processing. Thus, one of the most emerging requirements of such devices is to provide intelligence in resource-constrained processors that consume few milliwatts of power. This work focuses on surveying, comparing and evaluating seven different recent and popular microcontrollers with a power envelope from a few up to hundreds of milliwatts against a Convolutional Neural Networks workload for a non trivial task such as face recognition. The evaluation reports key points of tiny machine learning performance of the target microcontrollers in terms of inference time, power consumption, energy per inference and computational efficiency. Experimental results highlight best-in-class power consumption for Ambiq Apollo3 and Sony Spresense at 41.3 μW/MHz and 128.2 μW/MHz respectively. The computational efficiency primacy goes instead to the MAX78000 and then to xCORE.ai at 117 MAC/cycle and 7.69 MAC/cycle respectively, achieving the fastest inference at 1.4 ms and 1.5 ms respectively. The platforms that required the least energy per inference were the MAX78000 and GAP8, at 0.09 mJ/inference and 0.52 mJ/inference respectively. The benchmarked tinyML network will be released openly to allow other researchers to run future comparisons on novel low power microprocessors.", "html": "https://ieeexplore.ieee.org/abstract/document/9870017", "paperhash": "giordano|survey_and_comparison_of_milliwatts_micro_controllers_for_tiny_machine_learning_at_the_edge"}, "signatures": ["~Marco_Giordano1"], "readers": ["everyone"], "nonreaders": [], "writers": ["~Marco_Giordano1"]} |
| {"id": "jaggClc6o-b", "original": null, "number": 13072, "cdate": 1668201286145, "mdate": 1668201286145, "ddate": null, "tcdate": 1668201286145, "tmdate": 1668511375700, "tddate": null, "forum": "jaggClc6o-b", "replyto": null, "invitation": "OpenReview.net/Archive/-/Direct_Upload", "content": {"title": "Survey and Comparison of Milliwatts Micro controllers for Tiny Machine Learning at the Edge", "authorids": [null, "~Michele_Magno1", "marco.giordano@pbl.ee.ethz.ch"], "authors": ["Luigi Piccinelli", "Michele Magno", "Marco Giordano"], "abstract": "Low power Internet of Things devices are growing in number and computational capabilities, pushing to ubiquitous deployment of smart sensors that embed on board both the sensing and the processing. Thus, one of the most emerging requirements of such devices is to provide intelligence in resource-constrained processors that consume few milliwatts of power. This work focuses on surveying, comparing and evaluating seven different recent and popular microcontrollers with a power envelope from a few up to hundreds of milliwatts against a Convolutional Neural Networks workload for a non trivial task such as face recognition. The evaluation reports key points of tiny machine learning performance of the target microcontrollers in terms of inference time, power consumption, energy per inference and computational efficiency. Experimental results highlight best-in-class power consumption for Ambiq Apollo3 and Sony Spresense at 41.3 μW/MHz and 128.2 μW/MHz respectively. The computational efficiency primacy goes instead to the MAX78000 and then to xCORE.ai at 117 MAC/cycle and 7.69 MAC/cycle respectively, achieving the fastest inference at 1.4 ms and 1.5 ms respectively. The platforms that required the least energy per inference were the MAX78000 and GAP8, at 0.09 mJ/inference and 0.52 mJ/inference respectively. The benchmarked tinyML network will be released openly to allow other researchers to run future comparisons on novel low power microprocessors.", "pdf": "https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9870017", "paperhash": "piccinelli|survey_and_comparison_of_milliwatts_micro_controllers_for_tiny_machine_learning_at_the_edge"}, "signatures": ["~Luigi_Piccinelli1"], "readers": ["everyone"], "nonreaders": [], "writers": ["~Luigi_Piccinelli1"]} |
| {"id": "RldSUkrJNjq", "original": null, "number": 18281, "cdate": 1683882316919, "mdate": 1683882316919, "ddate": null, "tcdate": 1683882316919, "tmdate": 1683882316919, "tddate": null, "forum": "RldSUkrJNjq", "replyto": null, "invitation": "OpenReview.net/Archive/-/Direct_Upload", "content": {"title": "Real-Time Low Power Audio Distortion Circuit Modeling: a TinyML Deep Learning Approach", "authorids": ["~Marco_Giordano1", "davide.plozza@pbl.ee.ethz.ch", "~Michele_Magno1"], "authors": ["Marco Giordano", "Davide Plozza", "Michele Magno"], "abstract": "This work proposes a combined approach using deep learning and standard signal conditioning to model analog audio distortion circuits in real-time. The proposed model targets low latency and low power resource-constrained processors, and it is based on a quantized neural network. Pre- and post-processing consisting in filtering and dithering has been applied to improve the performance of the proposed optimized model. The model has been compared with a real-time state-of-art model WaveNet3 running on a modern desktop computer, which we used as performance reference. Our proposed model achieves a parameter size reduction of 8.4x and a neural network multiply-accumulation operations reduction of 5.1x with respect to the WaveNet3, while maintaining comparable performance. The model has been optimized and deployed on the novel MAX78000 microcontroller which features an on-board convolutional neural network hardware accelerator. Experimental results show real-time operation with a total latency of less than 10 ms and a power consumption as low as 91.8 mW in active mode, making the system suited for live music performances. Experimental results also demonstrate the capability of the hardware accelerator of the MAX78000 to reach 53.2 multiply-accumulation operations per cycle.", "html": "https://ieeexplore.ieee.org/abstract/document/9870024", "paperhash": "giordano|realtime_low_power_audio_distortion_circuit_modeling_a_tinyml_deep_learning_approach"}, "signatures": ["~Marco_Giordano1"], "readers": ["everyone"], "nonreaders": [], "writers": ["~Marco_Giordano1"]} |
| {"id": "TsmjiWKhlgl", "original": null, "number": 2, "cdate": 1657267956939, "ddate": null, "tcdate": 1657267956939, "tmdate": 1657267956939, "tddate": null, "forum": "ZJe-XahpyBf", "replyto": "ZJe-XahpyBf", "invitation": "NeurIPS.cc/2022/Conference/Paper1175/-/Official_Review", "content": {"rating": "6: Weak Accept: Technically solid, moderate-to-high impact paper, with no major concerns with respect to evaluation, resources, reproducibility, ethical considerations.", "confidence": "3: You are fairly confident in your assessment. It is possible that you did not understand some parts of the submission or that you are unfamiliar with some pieces of related work. Math/other details were not carefully checked.", "summary": "The authors present am updated Differential Neural Architecture Search algorithm, UDC, which incorporates model compression features such as weight sparsity and quantization as part of the search space for the ideal (high accuracy, small model size) neural network (NN) model. In addition, keeping in mind the constraints typically faced by TinyML models, the authors also enforce a strict limit on the model size to ensure it can be implemented in resource constrained IoT applications. Further, the presented algorithm enables effective exploration of accuracy vs model size tradeoff. Lastly, the paper demonstrates the pareto dominance of NNs designed by UDC compared to prior art for a range of ML benchmarks and varying hardware constraints on Ethos U55 NPU.", "strengths_and_weaknesses": "The paper presents a thorough comparison of UDC against past techniques that attempt similar co-optimization of ML models while accounting for hardware constraints. UDC tackles a wider range of constraints compared to all listed in prior art. \n\nSection 3 and 4 describe the details of the design model and the proposed DNAS algorithm. These sections were somewhat hard to follow, however, it is understandable considering the mathematical nature of problem. It is not obvious what these variables denote, ξ & ν, kindly add a description. \n\nSection 6 shows a comparative study of generating NNs using UDC and other prior art for state-of-the-art (SOTA) ML benchmarks under different memory size constraints. Figure 4 illustrates the superiority of UDC in terms of accuracy and model size, could the authors also shed light on the runtime it takes to converge to the final NN design UDC picks compared to other approaches (e.g., MCUNet). Considering UDC accounts for a larger set of constraints compared to other approaches it would be interesting if it can demonstrate comparable runtimes too. \n\nFigure 5b, compares UDC results to random search, and the authors do share some insight on UDC runtime compared to training a baseline network (~2x), if they could share this runtime information it would be handy. Also note that authors should be careful that while comparing to random search the resource utilization for UDC should be similar e.g., running equal number of parallel GPU instances for a fair comparison. It would be interesting to know how long it takes to converge the random search to the optimal design picked up by UDC (withing reasonable time constraints of course).\n \nAdditionally, could authors share how they selected the memory size constraint values for the experiments shared in the paper, is there some understanding if the superiority of UDC holds for larger/smaller mem constraints and if yes how a user could understand if they fall in that range. \n\nTo conclude, this work promises a very useful optimization tool for designing small but high accuracy NNs that can fit on typical IoT devices servicing TinyML applications.\n", "questions": "Refer to questions addressed in Strengths/Weakness section.", "limitations": "Authors do not present any data showing the timing performance of UDC compared to other approaches, some perspective on that would be helpful. Also any explanation on how the memory size constraints were selected for presented experiments would be helpful. ", "ethics_flag": "No", "ethics_review_area": [], "soundness": "3 good", "presentation": "4 excellent", "contribution": "4 excellent", "code_of_conduct": "Yes"}, "signatures": ["NeurIPS.cc/2022/Conference/Paper1175/Reviewer_c4gz"], "readers": ["everyone"], "nonreaders": [], "writers": ["NeurIPS.cc/2022/Conference", "NeurIPS.cc/2022/Conference/Paper1175/Reviewer_c4gz"], "forumContent": {}} |
| {"id": "UzEsp65mjM0", "original": null, "number": 905083, "cdate": 1577836800000, "pdate": 1577836800000, "mdate": 1698314126623, "ddate": null, "tcdate": 1698314126623, "tmdate": 1698326641579, "tddate": null, "forum": "UzEsp65mjM0", "replyto": null, "invitation": "dblp.org/-/record", "content": {"venue": "SenSys 2020", "venueid": "dblp.org/conf/SENSYS/2020", "_bibtex": "@inproceedings{DBLP:conf/sensys/HuIAK20,\n author={Pan Hu and Junha Im and Zain Asgar and Sachin Katti},\n title={Starfish: resilient image compression for AIoT cameras},\n year={2020},\n cdate={1577836800000},\n pages={395-408},\n url={https://doi.org/10.1145/3384419.3430769},\n booktitle={SenSys},\n crossref={conf/sensys/2020},\n}\n", "authors": ["Pan Hu", "Junha Im", "Zain Asgar", "Sachin Katti"], "authorids": ["~Pan_Hu1", "https://dblp.org/search/pid/api?q=author:Junha_Im:", "https://dblp.org/search/pid/api?q=author:Zain_Asgar:", "https://dblp.org/search/pid/api?q=author:Sachin_Katti:"], "html": "https://doi.org/10.1145/3384419.3430769", "title": "Starfish: resilient image compression for AIoT cameras", "paperhash": "hu|starfish_resilient_image_compression_for_aiot_cameras", "abstract": "Cameras are key enablers for a wide range of IoT use cases including smart cities, intelligent transportation, AI-enabled farms, and more. These IoT applications require cloud software (including models) to act on the images. However, traditional task oblivious compression techniques are a poor fit for delivering images over low power IoT networks that are lossy and limited in capacity. The key challenge is their brittleness against packet loss; they are highly sensitive to small amounts of packet loss requiring retransmission for transport, which further reduces the available capacity of the network. We propose Starfish, a design that achieves better compression ratios and is graceful with packet loss. In addition to that, Starfish features content-awareness and task-awareness, meaning that we can build specialized codecs for each application scenario and optimized for task objectives, including objective/perceptual quality as well as AI tasks directly. We carefully design the DNN architecture and use an AutoML method to search for TinyML models that work on extremely low power/cost AIoT accelerators. Starfish is not only the first image compress framework that works on a $3 AIoT accelerators but also outperforms JPEG, a well-established baseline, by up to 3x, in terms of bandwidth efficiency and up to 2.5x as efficient in energy consumption. It also features graceful and gradual performance degradation in the presence of packet loss. The application-level simulation indicates that Starfish could deliver 3.7x images while providing better image quality."}, "signatures": ["~Pan_Hu1"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "N0xG3O6HcZT", "original": null, "number": 467473, "cdate": 1640995200000, "mdate": 1668013828668, "ddate": null, "tcdate": 1668013828668, "tmdate": 1695380521685, "tddate": null, "forum": "N0xG3O6HcZT", "replyto": null, "invitation": "dblp.org/-/record", "content": {"venue": "CoRR 2022", "venueid": "dblp.org/journals/CORR/2022", "_bibtex": "@article{DBLP:journals/corr/abs-2201-01089,\n publtype={informal},\n author={Angelo Garofalo and Gianmarco Ottavi and Francesco Conti and Geethan Karunaratne and Irem Boybat and Luca Benini and Davide Rossi},\n title={A Heterogeneous In-Memory Computing Cluster For Flexible End-to-End Inference of Real-World Deep Neural Networks},\n year={2022},\n cdate={1640995200000},\n journal={CoRR},\n volume={abs/2201.01089},\n url={https://arxiv.org/abs/2201.01089}\n}\n", "authors": ["Angelo Garofalo", "Gianmarco Ottavi", "Francesco Conti", "Geethan Karunaratne", "Irem Boybat", "Luca Benini", "Davide Rossi"], "authorids": ["https://dblp.org/search/pid/api?q=author:Angelo_Garofalo:", "https://dblp.org/search/pid/api?q=author:Gianmarco_Ottavi:", "https://dblp.org/search/pid/api?q=author:Francesco_Conti_0001:", "~Geethan_Karunaratne1", "https://dblp.org/search/pid/api?q=author:Irem_Boybat:", "~Luca_Benini2", "https://dblp.org/search/pid/api?q=author:Davide_Rossi:"], "html": "https://arxiv.org/abs/2201.01089", "title": "A Heterogeneous In-Memory Computing Cluster For Flexible End-to-End Inference of Real-World Deep Neural Networks", "paperhash": "garofalo|a_heterogeneous_inmemory_computing_cluster_for_flexible_endtoend_inference_of_realworld_deep_neural_networks", "abstract": "Deployment of modern TinyML tasks on small battery-constrained IoT devices requires high computational energy efficiency. Analog In-Memory Computing (IMC) using non-volatile memory (NVM) promises major efficiency improvements in deep neural network (DNN) inference and serves as on-chip memory storage for DNN weights. However, IMC's functional flexibility limitations and their impact on performance, energy, and area efficiency are not yet fully understood at the system level. To target practical end-to-end IoT applications, IMC arrays must be enclosed in heterogeneous programmable systems, introducing new system-level challenges which we aim at addressing in this work. We present a heterogeneous tightly-coupled clustered architecture integrating 8 RISC-V cores, an in-memory computing accelerator (IMA), and digital accelerators. We benchmark the system on a highly heterogeneous workload such as the Bottleneck layer from a MobileNetV2, showing 11.5x performance and 9.5x energy efficiency improvements, compared to highly optimized parallel execution on the cores. Furthermore, we explore the requirements for end-to-end inference of a full mobile-grade DNN (MobileNetV2) in terms of IMC array resources, by scaling up our heterogeneous architecture to a multi-array accelerator. Our results show that our solution, on the end-to-end inference of the MobileNetV2, is one order of magnitude better in terms of execution latency than existing programmable architectures and two orders of magnitude better than state-of-the-art heterogeneous solutions integrating in-memory computing analog cores.pdfhttp://arxiv.org/pdf/2201.01089v1signatures~Luca_Benini2readerseveryonenonreaderswritersdblp.org |
| idWGs0Fw5kqKoriginalnumbercdateddatetcdatetmdatetddateforumZJe-XahpyBfreplyto0KGklds9VVkinvitationNeurIPS.cc/2022/Conference/Paper1175/-/Official_CommentcontenttitleResponse to reviewer c4gz (2/2)comment> It would be interesting to know how long it takes to converge the random search to the optimal design picked up by UDC (within reasonable time constraints of course).\n\nWe agree that it would be interesting to conduct this study, but we can already see that UDC achieves significantly better results compared to random search, using a small fraction of the trials. We did not have spare computational resources to extend the random search to multiple hundreds or thousands of trials, but we will try and generate these results for the revision.\n\n> Additionally, could authors share how they selected the memory size constraint values for the experiments shared in the paper\n\nIn practice, the model size constraints are determined by the Flash memory size of the deployment hardware platform. To be sure, 0.5-1.25 MB Flash sizes are fairly common for commodity hardware platforms (i.e. STM32F446RE, STM32F746ZG, STM32F767ZI) and are often used in research papers targeting deployment on constrained hardware platforms [1,2]. As such we targeted this range because it represents a reasonable, but extremely challenging deployment scenario.\n\n> is there some understanding if the superiority of UDC holds for larger/smaller mem constraints and if yes how a user could understand if they fall in that range.\n\nSince we only experimented with UDC in the very low to medium model size regime, we are hesitant to speculate how well UDC would perform in the very high model size regime. With that being said, we can see in Fig. 4a that UDC finds an ImageNet model with >72% accuracy while being 3.35x smaller than an APQ model at 4MB, which is considered a rather large model size in the context of resource constrained hardware deployment. This suggests that UDC does scale well when moving from very small to medium sized models. \n\n[1] Ji Lin, Wei-Ming Chen, Yujun Lin, Chuang Gan, Song Han, et al. \ Advances in Neural Information Processing Systems, 2020.\n\n[2] Colby Banbury, Chuteng Zhou, Igor Fedorov, Ramon Matas, Urmish Thakker, Dibakar Gope, Vijay Janapa Reddi, Matthew Mattina, and Paul Whatmough. \ Proceedings of Machine Learning and Systems, 3, 2021.\nsignaturesNeurIPS.cc/2022/Conference/Paper1175/AuthorsreaderseveryonenonreaderswritersNeurIPS.cc/2022/ConferenceNeurIPS.cc/2022/Conference/Paper1175/AuthorsforumContent |
| idblIJ51Ux0iuoriginalnumbercdatepdatemdateddatetcdatetmdatetddateforumblIJ51Ux0iureplytoinvitationdblp.org/-/recordcontentvenueBodySys@MobiSys 2023venueiddblp.org/conf/MOBISYS/2023_bibtex@inproceedings{DBLP:conf/mobisys/MukhopadhyayDG23a,\n author={Shalini Mukhopadhyay and Swarnava Dey and Avik Ghose},\n title={TinyPuff: Automated design of Tiny Smoking Puff Classifiers for Body Worn Devices},\n year={2023},\n cdate={1672531200000},\n pages={7-12},\n url={https://doi.org/10.1145/3597061.3597259},\n booktitle={BodySys@MobiSys},\n crossref={conf/mobisys/2023bodysys},\n}\nauthorsShalini MukhopadhyaySwarnava DeyAvik Ghoseauthoridshttps://dblp.org/search/pid/api?q=author:Shalini_Mukhopadhyay:~Swarnava_Dey1https://dblp.org/search/pid/api?q=author:Avik_Ghose:htmlhttps://doi.org/10.1145/3597061.3597259titleTinyPuff: Automated design of Tiny Smoking Puff Classifiers for Body Worn Devicespaperhashmukhopadhyay|tinypuff_automated_design_of_tiny_smoking_puff_classifiers_for_body_worn_devicesabstractSmoking is a significant cause of death and deterioration of health worldwide, affecting active and passive smokers. Cessation of smoking contributes to an essential health and wellness application owing to the broad range of health problems such as cancer, hypertension, and several cardiopulmonary diseases. Personalized smoking-cessation applications can be very effective in helping users to stop smoking if there are detections and interventions done at the right time. This requires real-time detection of smoking puffs. Such applications are made feasible by day-long monitoring and smoking puff detection from unobtrusive devices such as wearables. This paper proposes a deep inference technique for the real-time detection of smoking puffs on a wearable device. We show that a simple, sequential Convolutional Neural Network (CNN) using only 6-axis Inertial signals can be utilized in place of complex and resource-consuming Deep Learning models. The accuracy achieved is comparable to State-of-the-Art techniques with an F1 score of 0.81, although the model size is tiny - 114 kB. Such small models can be deployed on the lowest configuration hardware platforms, achieving accurate but high-speed, low-power inference on conventional smartwatches. We ensure that the auto-designed models are directly compatible with resource-constrained platforms such as TensorFlow Lite and TensorFlow Lite for Microcontrollers (TFLM) without requiring further use of model reduction and optimization techniques. Our proposed approach will allow affordable wearable device manufacturers to run smoking detection on their devices, as it is tiny enough to fit TinyML platforms and is only dependent on IMU sensors that are universally available.signatures~Swarnava_Dey1readerseveryonenonreaderswritersdblp.org |
| idMjPY3Ce3yJoriginalnumbercdatepdatemdateddatetcdatetmdatetddateforumMjPY3Ce3yJreplytoinvitationdblp.org/-/recordcontentvenueCoRR 2022venueiddblp.org/journals/CORR/2022_bibtex@article{DBLP:journals/corr/abs-2201-02863,\n publtype={informal},\n author={Jaewoo Song and Fangzhen Lin},\n title={PocketNN: Integer-only Training and Inference of Neural Networks via Direct Feedback Alignment and Pocket Activations in Pure C++},\n year={2022},\n cdate={1640995200000},\n journal={CoRR},\n volume={abs/2201.02863},\n url={https://arxiv.org/abs/2201.02863},\n}\nauthorsJaewoo SongFangzhen Linauthoridshttps://dblp.org/search/pid/api?q=author:Jaewoo_Song:~Fangzhen_Lin1htmlhttps://arxiv.org/abs/2201.02863titlePocketNN: Integer-only Training and Inference of Neural Networks via Direct Feedback Alignment and Pocket Activations in Pure C++paperhashsong|pocketnn_integeronly_training_and_inference_of_neural_networks_via_direct_feedback_alignment_and_pocket_activations_in_pure_cabstractStandard deep learning algorithms are implemented using floating-point real numbers. This presents an obstacle for implementing them on low-end devices which may not have dedicated floating-point units (FPUs). As a result, researchers in tinyML have considered machine learning algorithms that can train and run a deep neural network (DNN) on a low-end device using integer operations only. In this paper we propose PocketNN, a light and self-contained proof-of-concept framework in pure C++ for the training and inference of DNNs using only integers. Unlike other approaches, PocketNN directly operates on integers without requiring any explicit quantization algorithms or customized fixed-point formats. This was made possible by pocket activations, which are a family of activation functions devised for integer-only DNNs, and an emerging DNN training algorithm called direct feedback alignment (DFA). Unlike the standard backpropagation (BP), DFA trains each layer independently, thus avoiding integer overflow which is a key problem when using BP with integer-only operations. We used PocketNN to train some DNNs on two well-known datasets, MNIST and Fashion-MNIST. Our experiments show that the DNNs trained with our PocketNN achieved 96.98% and 87.7% accuracies on MNIST and Fashion-MNIST datasets, respectively. The accuracies are very close to the equivalent DNNs trained using BP with floating-point real number operations, such that accuracy degradations were just 1.02%p and 2.09%p, respectively. Finally, our PocketNN has high compatibility and portability for low-end devices as it is open source and implemented in pure C++ without any dependencies.pdfhttp://arxiv.org/pdf/2201.02863v6signatures~Fangzhen_Lin1readerseveryonenonreaderswritersdblp.org |
| idpAfBKXKlWboriginalnumbercdatemdateddatetcdatetmdatetddateforumpAfBKXKlWbreplytoinvitationdblp.org/-/recordcontentvenueCoRR 2022venueiddblp.org/journals/CORR/2022_bibtex@article{DBLP:journals/corr/abs-2206-15472,\n publtype={informal},\n author={Ji Lin and Ligeng Zhu and Wei-Ming Chen and Wei-Chen Wang and Chuang Gan and Song Han},\n title={On-Device Training Under 256KB Memory},\n year={2022},\n cdate={1640995200000},\n journal={CoRR},\n volume={abs/2206.15472},\n url={https://doi.org/10.48550/arXiv.2206.15472}\n}\nauthorsJi LinLigeng ZhuWei-Ming ChenWei-Chen WangChuang GanSong Hanauthoridshttps://dblp.org/search/pid/api?q=author:Ji_Lin_0002:~Ligeng_Zhu1~Wei-Ming_Chen1https://dblp.org/search/pid/api?q=author:Wei-Chen_Wang:https://dblp.org/search/pid/api?q=author:Chuang_Gan:~Song_Han5htmlhttps://doi.org/10.48550/arXiv.2206.15472titleOn-Device Training Under 256KB Memorypaperhashlin|ondevice_training_under_256kb_memoryabstractOn-device training enables the model to adapt to new data collected from the sensors by fine-tuning a pre-trained model. Users can benefit from customized AI models without having to transfer the data to the cloud, protecting the privacy. However, the training memory consumption is prohibitive for IoT devices that have tiny memory resources. We propose an algorithm-system co-design framework to make on-device training possible with only 256KB of memory. On-device training faces two unique challenges: (1) the quantized graphs of neural networks are hard to optimize due to low bit-precision and the lack of normalization; (2) the limited hardware resource does not allow full back-propagation. To cope with the optimization difficulty, we propose Quantization-Aware Scaling to calibrate the gradient scales and stabilize 8-bit quantized training. To reduce the memory footprint, we propose Sparse Update to skip the gradient computation of less important layers and sub-tensors. The algorithm innovation is implemented by a lightweight training system, Tiny Training Engine, which prunes the backward computation graph to support sparse updates and offload the runtime auto-differentiation to compile time. Our framework is the first solution to enable tiny on-device training of convolutional neural networks under 256KB SRAM and 1MB Flash without auxiliary memory, using less than 1/1000 of the memory of PyTorch and TensorFlow while matching the accuracy on tinyML application VWW. Our study enables IoT devices not only to perform inference but also to continuously adapt to new data for on-device lifelong learning. A video demo can be found here: https://youtu.be/XaDCO8YtmBw.pdfhttp://arxiv.org/pdf/2206.15472v3signatures~Ligeng_Zhu1readerseveryonenonreaderswritersdblp.org |
| id6d5hQ3fkG-6originalnumbercdatepdatemdateddatetcdatetmdatetddateforum6d5hQ3fkG-6replytoinvitationdblp.org/-/recordcontentvenueCoRR 2020venueiddblp.org/journals/CORR/2020_bibtex@article{DBLP:journals/corr/abs-2008-04245,\n publtype={informal},\n author={Alexander Wong and Mahmoud Famouri and Maya Pavlova and Siddharth Surana},\n title={TinySpeech: Attention Condensers for Deep Speech Recognition Neural Networks on Edge Devices},\n year={2020},\n cdate={1577836800000},\n journal={CoRR},\n volume={abs/2008.04245},\n url={https://arxiv.org/abs/2008.04245},\n}\nauthorsAlexander WongMahmoud FamouriMaya PavlovaSiddharth Suranaauthorids~Alexander_Wong2https://dblp.org/search/pid/api?q=author:Mahmoud_Famouri:https://dblp.org/search/pid/api?q=author:Maya_Pavlova:https://dblp.org/search/pid/api?q=author:Siddharth_Surana:htmlhttps://arxiv.org/abs/2008.04245titleTinySpeech: Attention Condensers for Deep Speech Recognition Neural Networks on Edge Devicespaperhashwong|tinyspeech_attention_condensers_for_deep_speech_recognition_neural_networks_on_edge_devicesabstractAdvances in deep learning have led to state-of-the-art performance across a multitude of speech recognition tasks. Nevertheless, the widespread deployment of deep neural networks for on-device speech recognition remains a challenge, particularly in edge scenarios where the memory and computing resources are highly constrained (e.g., low-power embedded devices) or where the memory and computing budget dedicated to speech recognition is low (e.g., mobile devices performing numerous tasks besides speech recognition). In this study, we introduce the concept of attention condensers for building low-footprint, highly-efficient deep neural networks for on-device speech recognition on the edge. An attention condenser is a self-attention mechanism that learns and produces a condensed embedding characterizing joint local and cross-channel activation relationships, and performs selective attention accordingly. To illustrate its efficacy, we introduce TinySpeech, low-precision deep neural networks comprising largely of attention condensers tailored for on-device speech recognition using a machine-driven design exploration strategy, with one tailored specifically with microcontroller operation constraints. Experimental results on the Google Speech Commands benchmark dataset for limited-vocabulary speech recognition showed that TinySpeech networks achieved significantly lower architectural complexity (as much as $507\\times$ fewer parameters), lower computational complexity (as much as $48\\times$ fewer multiply-add operations), and lower storage requirements (as much as $2028\\times$ lower weight memory requirements) when compared to previous work. These results not only demonstrate the efficacy of attention condensers for building highly efficient networks for on-device speech recognition, but also illuminate its potential for accelerating deep learning on the edge and empowering TinyML applications.pdfhttp://arxiv.org/pdf/2008.04245v6signatures~Alexander_Wong2readerseveryonenonreaderswritersdblp.org |
| idwF9fY2Ps7XoriginalnumbercdatemdateddatetcdatetmdatetddateforumwF9fY2Ps7Xreplytoinvitationdblp.org/-/recordcontentvenueCoRR 2022venueiddblp.org/journals/CORR/2022_bibtex@article{DBLP:journals/corr/abs-2201-01863,\n publtype={informal},\n author={Shvetank Prakash and Tim Callahan and Joseph Bushagour and Colby R. Banbury and Alan V. Green and Pete Warden and Tim Ansell and Vijay Janapa Reddi},\n title={CFU Playground: Full-Stack Open-Source Framework for Tiny Machine Learning (tinyML) Acceleration on FPGAs},\n year={2022},\n cdate={1640995200000},\n journal={CoRR},\n volume={abs/2201.01863},\n url={https://arxiv.org/abs/2201.01863},\n}\nauthorsShvetank PrakashTim CallahanJoseph BushagourColby R. BanburyAlan V. GreenPete WardenTim AnsellVijay Janapa Reddiauthoridshttps://dblp.org/search/pid/api?q=author:Shvetank_Prakash:https://dblp.org/search/pid/api?q=author:Tim_Callahan:https://dblp.org/search/pid/api?q=author:Joseph_Bushagour:~Colby_R._Banbury1https://dblp.org/search/pid/api?q=author:Alan_V._Green:~Pete_Warden2https://dblp.org/search/pid/api?q=author:Tim_Ansell:~Vijay_Janapa_Reddi1htmlhttps://arxiv.org/abs/2201.01863titleCFU Playground: Full-Stack Open-Source Framework for Tiny Machine Learning (tinyML) Acceleration on FPGAspaperhashprakash|cfu_playground_fullstack_opensource_framework_for_tiny_machine_learning_tinyml_acceleration_on_fpgasabstractNeed for the efficient processing of neural networks has given rise to the development of hardware accelerators. The increased adoption of specialized hardware has highlighted the need for more agile design flows for hardware-software co-design and domain-specific optimizations. In this paper, we present CFU Playground: a full-stack open-source framework that enables rapid and iterative design and evaluation of machine learning (ML) accelerators for embedded ML systems. Our tool provides a completely open-source end-to-end flow for hardware-software co-design on FPGAs and future systems research. This full-stack framework gives the users access to explore experimental and bespoke architectures that are customized and co-optimized for embedded ML. Our rapid, deploy-profile-optimization feedback loop lets ML hardware and software developers achieve significant returns out of a relatively small investment in customization. Using CFU Playground's design and evaluation loop, we show substantial speedups between 55$\\times$ and 75$\\times$. The soft CPU coupled with the accelerator opens up a new, rich design space between the two components that we explore in an automated fashion using Vizier, an open-source black-box optimization service.", "pdf": "http://arxiv.org/pdf/2201.01863v3"}, "signatures": ["~Colby_Banbury1"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "y0d7w5cpZJ", "original": null, "number": 466710, "cdate": 1640995200000, "mdate": 1668013807648, "ddate": null, "tcdate": 1668013807648, "tmdate": 1695380521530, "tddate": null, "forum": "y0d7w5cpZJ", "replyto": null, "invitation": "dblp.org/-/record", "content": {"venue": "IEEE J. Emerg. Sel. Topics Circuits Syst. 2022", "venueid": "dblp.org/journals/ESTICAS/2022", "_bibtex": "@article{DBLP:journals/esticas/GarofaloOCKBBR22,\n author={Angelo Garofalo and Gianmarco Ottavi and Francesco Conti and Geethan Karunaratne and Irem Boybat and Luca Benini and Davide Rossi},\n title={A Heterogeneous In-Memory Computing Cluster for Flexible End-to-End Inference of Real-World Deep Neural Networks},\n year={2022},\n cdate={1640995200000},\n journal={IEEE J. Emerg. Sel. Topics Circuits Syst.},\n volume={12},\n number={2},\n pages={422-435},\n url={https://doi.org/10.1109/JETCAS.2022.3170152}\n}\n", "authors": ["Angelo Garofalo", "Gianmarco Ottavi", "Francesco Conti", "Geethan Karunaratne", "Irem Boybat", "Luca Benini", "Davide Rossi"], "authorids": ["https://dblp.org/search/pid/api?q=author:Angelo_Garofalo:", "https://dblp.org/search/pid/api?q=author:Gianmarco_Ottavi:", "https://dblp.org/search/pid/api?q=author:Francesco_Conti_0001:", "~Geethan_Karunaratne1", "https://dblp.org/search/pid/api?q=author:Irem_Boybat:", "~Luca_Benini2", "https://dblp.org/search/pid/api?q=author:Davide_Rossi:"], "html": "https://doi.org/10.1109/JETCAS.2022.3170152", "title": "A Heterogeneous In-Memory Computing Cluster for Flexible End-to-End Inference of Real-World Deep Neural Networks", "paperhash": "garofalo|a_heterogeneous_inmemory_computing_cluster_for_flexible_endtoend_inference_of_realworld_deep_neural_networks", "abstract": "Deployment of modern TinyML tasks on small battery-constrained IoT devices requires high computational energy efficiency. Analog In-Memory Computing (IMC) using non-volatile memory (NVM) promises major efficiency improvements in deep neural network (DNN) inference and serves as on-chip memory storage for DNN weights. However, IMC’s functional flexibility limitations and their impact on performance, energy, and area efficiency are not yet fully understood at the system level. To target practical end-to-end IoT applications, IMC arrays must be enclosed in heterogeneous programmable systems, introducing new system-level challenges which we aim at addressing in this work. We present a heterogeneous tightly-coupled clustered architecture integrating 8 RISC-V cores, an in-memory computing accelerator (IMA), and digital accelerators. We benchmark the system on a highly heterogeneous workload such as the Bottleneck layer from a MobileNetV2, showing <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$11.5\\times $ </tex-math></inline-formula> performance and <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$9.5\\times $ </tex-math></inline-formula> energy efficiency improvements, compared to highly optimized parallel execution on the cores. Furthermore, we explore the requirements for end-to-end inference of a full mobile-grade DNN (MobileNetV2) in terms of IMC array resources, by scaling up our heterogeneous architecture to a multi-array accelerator. Our results show that our solution, on the end-to-end inference of the MobileNetV2, is one order of magnitude better in terms of execution latency than existing programmable architectures and two orders of magnitude better than state-of-the-art heterogeneous solutions integrating in-memory computing analog cores.", "pdf": "https://ieeexplore.ieee.org/iel7/5503868/9794907/09764758.pdf"}, "signatures": ["~Luca_Benini2"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "BJm8_R2RAe", "original": null, "number": 468021, "cdate": 1640995200000, "mdate": 1668013906288, "ddate": null, "tcdate": 1668013906288, "tmdate": 1668999476578, "tddate": null, "forum": "BJm8_R2RAe", "replyto": null, "invitation": "dblp.org/-/record", "content": {"venue": "IEEE J. Emerg. Sel. Topics Circuits Syst. 2022", "venueid": "dblp.org/journals/ESTICAS/2022", "_bibtex": "@article{DBLP:journals/esticas/GarofaloOCKBBR22,\n author={Angelo Garofalo and Gianmarco Ottavi and Francesco Conti and Geethan Karunaratne and Irem Boybat and Luca Benini and Davide Rossi},\n title={A Heterogeneous In-Memory Computing Cluster for Flexible End-to-End Inference of Real-World Deep Neural Networks},\n year={2022},\n cdate={1640995200000},\n journal={IEEE J. Emerg. Sel. Topics Circuits Syst.},\n volume={12},\n number={2},\n pages={422-435},\n url={https://doi.org/10.1109/JETCAS.2022.3170152}\n}\n", "authors": ["Angelo Garofalo", "Gianmarco Ottavi", "Francesco Conti", "Geethan Karunaratne", "Irem Boybat", "Luca Benini", "Davide Rossi"], "authorids": ["https://dblp.org/search/pid/api?q=author:Angelo_Garofalo:", "https://dblp.org/search/pid/api?q=author:Gianmarco_Ottavi:", "https://dblp.org/search/pid/api?q=author:Francesco_Conti_0001:", "https://dblp.org/search/pid/api?q=author:Geethan_Karunaratne:", "https://dblp.org/search/pid/api?q=author:Irem_Boybat:", "~Luca_Benini2", "https://dblp.org/search/pid/api?q=author:Davide_Rossi:"], "html": "https://doi.org/10.1109/JETCAS.2022.3170152", "title": "A Heterogeneous In-Memory Computing Cluster for Flexible End-to-End Inference of Real-World Deep Neural Networks", "paperhash": "garofalo|a_heterogeneous_inmemory_computing_cluster_for_flexible_endtoend_inference_of_realworld_deep_neural_networks", "abstract": "Deployment of modern TinyML tasks on small battery-constrained IoT devices requires high computational energy efficiency. Analog In-Memory Computing (IMC) using non-volatile memory (NVM) promises major efficiency improvements in deep neural network (DNN) inference and serves as on-chip memory storage for DNN weights. However, IMC’s functional flexibility limitations and their impact on performance, energy, and area efficiency are not yet fully understood at the system level. To target practical end-to-end IoT applications, IMC arrays must be enclosed in heterogeneous programmable systems, introducing new system-level challenges which we aim at addressing in this work. We present a heterogeneous tightly-coupled clustered architecture integrating 8 RISC-V cores, an in-memory computing accelerator (IMA), and digital accelerators. We benchmark the system on a highly heterogeneous workload such as the Bottleneck layer from a MobileNetV2, showing <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$11.5\\times $ </tex-math></inline-formula> performance and <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$9.5\\times $ </tex-math></inline-formula> energy efficiency improvements, compared to highly optimized parallel execution on the cores. Furthermore, we explore the requirements for end-to-end inference of a full mobile-grade DNN (MobileNetV2) in terms of IMC array resources, by scaling up our heterogeneous architecture to a multi-array accelerator. Our results show that our solution, on the end-to-end inference of the MobileNetV2, is one order of magnitude better in terms of execution latency than existing programmable architectures and two orders of magnitude better than state-of-the-art heterogeneous solutions integrating in-memory computing analog cores.", "pdf": "https://ieeexplore.ieee.org/iel7/5503868/9794907/09764758.pdf"}, "signatures": ["~Luca_Benini2"], "readers": ["everyone"], "nonreaders": [], "writers": ["dblp.org"]} |
| {"id": "PRZ9josN6d2", "original": null, "number": 21548, "cdate": 1686639478573, "mdate": 1686639478573, "ddate": null, "tcdate": 1686639478573, "tmdate": 1686639478573, "tddate": null, "forum": "PRZ9josN6d2", "replyto": null, "invitation": "OpenReview.net/Archive/-/Direct_Upload", "content": {"title": "AURITUS: An Open-Source Optimization Toolkit for Training and Development of Human Movement Models and Filters Using Earables", "authorids": ["swapnilsayan@g.ucla.edu", "ssandha@ucla.edu", "sypei@g.ucla.edu", "vivek13jain@g.ucla.edu", "~Ziqi_Wang8", "lyc1998kumamon@g.ucla.edu", "~Ankur_Sarker1", "~Mani_Srivastava1"], "authors": ["Swapnil Sayan Saha", "Sandeep Singh Sandha", "Siyou Pei", "Vivek Jain", "Ziqi Wang", "Yuchen Li", "Ankur Sarker", "Mani Srivastava"], "abstract": "Smart ear-worn devices (called earables) are being equipped with various onboard sensors and algorithms, transforming earphones from simple audio transducers to multi-modal interfaces making rich inferences about human motion and vital signals. However, developing sensory applications using earables is currently quite cumbersome with several barriers in the way. First, time-series data from earable sensors incorporate information about physical phenomena in complex settings, requiring machine-learning (ML) models learned from large-scale labeled data. This is challenging in the context of earables because large-scale open-source datasets are missing. Secondly, the small size and compute constraints of earable devices make on-device integration of many existing algorithms for tasks such as human activity and head-pose estimation difficult. To address these challenges, we introduce Auritus, an extendable and open-source optimization toolkit designed to enhance and replicate earable applications. Auritus serves two primary functions. Firstly, Auritus handles data collection, pre-processing, and labeling tasks for creating customized earable datasets using graphical tools. The system includes an open-source dataset with 2.43 million inertial samples related to head and full-body movements, consisting of 34 head poses and 9 activities from 45 volunteers. Secondly, Auritus provides a tightly-integrated hardware-in-the-loop (HIL) optimizer and TinyML interface to develop lightweight and real-time machine-learning (ML) models for activity detection and filters for head-pose tracking. To validate the utlity of Auritus, we showcase three sample applications, namely fall detection, spatial audio rendering, and augmented reality (AR) interfacing. Auritus recognizes activities with 91% leave 1-out test accuracy (98% test accuracy) using real-time models as small as 6-13 kB. Our models are 98-740x smaller and 3-6% more accurate over the state-of-the-art. We also estimate head pose with absolute errors as low as 5 degrees using 20kB filters, achieving up to 1.6x precision improvement over existing techniques. We make the entire system open-source so that researchers and developers can contribute to any layer of the system or rapidly prototype their applications using our dataset and algorithms.", "pdf": "https://dl.acm.org/doi/pdf/10.1145/3534586", "html": "https://dl.acm.org/doi/abs/10.1145/3534586", "paperhash": "saha|auritus_an_opensource_optimization_toolkit_for_training_and_development_of_human_movement_models_and_filters_using_earables"}, "signatures": ["~Ziqi_Wang8"], "readers": ["everyone"], "nonreaders": [], "writers": ["~Ziqi_Wang8"]} |
| {"id": "q_wGNskA3L", "original": null, "number": 5, "cdate": 1659448806369, "ddate": null, "tcdate": 1659448806369, "tmdate": 1659576283258, "tddate": null, "forum": "E28hy5isRzC", "replyto": "DNsmRaM7D5v", "invitation": "NeurIPS.cc/2022/Conference/Paper6382/-/Official_Comment", "content": {"title": "Response to Reviewer xZvK (1/2)", "comment": "Thanks for all your constructive comments. Please see below our response to the specific questions.\n\n> Q1: Equation 6: what variable is the summation applied on? Q based on its different value ranges?\n\nA1: The summation in Equation 6 represents the variance of the quantization value Q, and Q is the quantization variable of R.\nBesides, the detailed computation process of the different value ranges of Q is described in Lines 126-128.\n\n> Q2: What is so special about the plot?\n\nA2: As mentioned in Lines 156-163, the two insights are derived from Table 1, Table 2 and Figure 5: 1) Increasing the initial standard deviation $\\sigma$ will help us distinguish the disparity of entropy between different bits; 2) Quantization of activations and weights has different effects on accuracy. For example, A3W4 and A4W3 models have the same BitOps, but A4W3 models have about 2\\% accuracy higher than A3W4, which means that quantization on activations and weights has different effects on accuracy. A3W6 and A6W3 models have the same situation. Therefore, we set different values of $\\sigma_A$ and $\\sigma_W$ to show differences between activations and weights.\n\n> Q3: QBR strategy is not clear.\n\nA3: We revised the caption of Figure 7 and a brief description of QBR lines 178-181. The detailed description and algorithm are in Appendix C. In addition, we add an analysis of QBR and w/o QBR models in Appendix C of the revised version. Please have a look.\n\n> Q4: The fundamental assumption of the system\n\nA4: There are two main budget constraints on IoT devices, i.e., memory and storage. Storage is a constraint of the full model and memory is a block-wise constraint, which is widely adopted in previous tinyML literature, such as MCUNet V1 and V2. \n\n> Q5: Why does initialization of X and W matter? \n\nA5: It is worth noting that searching and training models don't use the same initialization. The initialization of X and W matter in searching because we design a QE-Score for measuring the expressiveness of the mixed-precision quantization model. When training, X is not needed to be initialized, and W uses the default Kaming initialization.\n\n> Q6: The derivation of QE-score seems problematic.\n\nA6: The bias of the convolutional layer is set to zero and the activation function is omitted in searching for simplification (Lines 103-108), following the work of ZenNAS [1] and MAE-DET [2] which has been proved that this will not affect the expressiveness of the network. The training of CNN models has been well studied, and some components can be integrated to boost performance. We deliberately avoid using these components to keep our design simple and universal. Nevertheless, these auxiliary components can be easily plugged into the architecture without any special modification.\n\n> Q7: The derivation of QE-Score does not follow a realistic assumption.\n\nA7: As mentioned in Theorem 1 (lines 95-96), for any continuous distribution with specific mean and variance, its differential entropy is maximized when the distribution is a Gaussian distribution, and it only depends on the variance (lines 96-98): $H(F) \\propto log(\\sigma^2)$; According to the Maximum Entropy Principle (Lines 90-92), the expressiveness of a continuous random distribution is positively correlated with its differential entropy. Similarly, if we regard a convolution neural network as such a system, the expressiveness of the output feature map is maximized when its entropy achieves maximum;\nFurthermore, the distribution of the output feature map is high-dimensional. We assume it obeys the Gaussian distribution to estimate the upper bound of the entropy, which represents its expressiveness (Lines 103-108).\n\n\n\n\n signaturesNeurIPS.cc/2022/Conference/Paper6382/AuthorsreaderseveryonenonreaderswritersNeurIPS.cc/2022/ConferenceNeurIPS.cc/2022/Conference/Paper6382/AuthorsforumContent |
| idF_HROsgu5IcoriginalnumbercdateddatetcdatetmdatetddateforumzGvRdBW06F5replytoUuc9sZ_FtYainvitationNeurIPS.cc/2022/Conference/Paper2198/-/Official_CommentcontenttitleAuthor Responsecomment**Q1: The comparison between QAS and LSQ (Esser et al., 2019)**\n\nWe have cited the LSQ paper in the revised version. Our paper has a **fundamentally different** setting compared to LSQ; QAS also **consistently outperforms** the scaling method in LSQ in our setting (73.5% vs. 39.8% accuracy).\n\nSetting-wise:\n1. LSQ is doing QAT on a **fake** quantization graph: the full precision weights need to be stored and updated during training, which costs 4x larger memory than int8 weights and does not lead to training memory saving. In fact, this is the setting of most existing papers aiming to train an accurate quantized model for efficient **inference** where our goal is efficient **training**.\n2. In our setting, we are updating a **real** quantized graph, where all the weights and biases are integers from the very beginning and stay as integers after updates. We are not targeting the quantization process itself (like LSQ); instead, we are _given_ a quantized graph and want to update it for transfer learning.\nPlease also kindly refer to supplementary Section D for the comparison between real quantized graphs and fake quantized graphs.\n\nWe perform experiments to compare QAS with the scaling method in LSQ:\n\n1. QAS consistently outperforms LSQ scaling. QAS can achieve an average accuracy of 73.5% on 8 datasets, while LSQ scaling only achieves 39.8% despite grid tuning on hyper-parameters.\n2. QAS is based on the mathematical derivation of the quantization process, while LSQ scaling is based on a heuristic to keep the same weight/gradient scale across parameters. We think such a heuristic does not apply to the **real** quantized graph with very different tensor ranges (e.g., int32 has a $10^7\\times$ larger range than int8) and leads to unstable training. This is a unique challenge when we update the real quantized graph and has not been observed in previous work.\n\n**Q2: Compare with HFP8 and the follow-up FP4 work.**\n\nWe have cited the two papers in the revised version. The two papers target a fundamentally different setting to ours. The two papers use hybrid and customized FP8 or FP4 formats, which are only supported in specialized hardware. It cannot run on general-purpose hardware like MCUs, Arm CPUs, Intel CPUs, etc. While our work focuses on int8 quantization, which can efficiently run on general-purpose hardware and has wider applications like tinyML.\n\nWe kindly remind the reviewer that QAS is just one part of our methods. Sparse update and training engine optimization bring **much larger memory saving** (17.9x, 1.9x in Figure 1), which should not be neglected. Limiting the scope to quantization does not provide a holistic view of our work.\n\n**Q3: Regarding using “tricks” to enable on-device learning.**\n\nOur proposed methods are fundamental principles instead of simple tricks. Our framework is the **first** solution to actually enable tiny on-device training of CNNs under a 256KB memory budget. We believe our design principles will shed light on later studies.\n\n1. We are targeting a new setting of updating the **real** quantized graph instead of using QAT to train a fake quantized graph for inference. Existing optimization methods will lead to inferior accuracy while QAS successfully addresses the difficulties.\n2. Sparse layer/tensor update is a novel memory-efficient update method. It consistently outperforms existing work like BN-only update [25], bias-only update [12], fine-tuning last k layers, etc. in terms of accuracy-memory trade-off.\n3. Efficient training systems on edge are rarely explored. Our Tiny Training Engine provides fundamental designs like compile-time differentiation, backward graph pruning, op reordering, etc. to improve memory and computation efficiency.\n\n**Q4: Experiments on a broader range of datasets.**\n\nWe have thoroughly verified the effectiveness of our proposed method on 8 datasets: Cars, CIFAR-10, CIFAR-100, CUB, Flowers, Food, Pets, and VWW, where our method achieves consistent improvement. These datasets are widely used to benchmark transfer learning in previous work (e.g., [13, 39]). So we believe the results we provided are comprehensive. Note that for the experimental results in the paper, we report the **average** accuracy on the 8 datasets to reflect the overall performance.\n\n**Q5: Ablation study on QAS vs. w/o gradient scaling.**\n\nWe have already provided the ablation study in Table 1, comparing vanilla SGD-M (i.e., w/o gradient scaling) and SGD-M+QAS. QAS consistently improves the average learning accuracy on 8 datasets (73.5% w/ scaling v.s. 64.9% w/o scaling).\n\n**Q6: Statement of open sourcing.**\n\nOur method is fully reproducible. We will open source the code upon publication. We have uploaded the [code to reproduce the video demo](https://anonymous.4open.science/r/on-device-training-0FE3) of transfer learning to the VWW dataset on a microcontroller (see supplementary Section A). We hope the code will help the community reproduce our work and inspire more later studies.signaturesNeurIPS.cc/2022/Conference/Paper2198/AuthorsreaderseveryonenonreaderswritersNeurIPS.cc/2022/ConferenceNeurIPS.cc/2022/Conference/Paper2198/AuthorsforumContent |
| idRl55uZo0Tf5originalnumbercdatemdateddatetcdatetmdatetddateforum2DJwuD-elOtreplytog8_dK8QVb9MinvitationICLR.cc/2022/Conference/Paper4168/-/Official_CommentcontenttitleAddressing specific reviewer comments (1/2)comment\nWe thank the reviewer for their constructive comments. Below we address the reviewer's main concerns.\n\n- **Communication Limited Settings, Latency and Energy experiments.** \\\n In the main rebuttal thread, we have shown the relation between coverage and latency. We explicitly define latency and provide detailed experiments. In addition, we have added these experiments in Section.3.4 with setup details in Appendix B.6. \n \n- **Comparison with Neurosurgeon** \n\t- Given a fixed high-cost model, Neurosurgeon splits the computation between the device and cloud model by processing the initial part of the network on the device and processing the remaining on the cloud. \n\t- It is a very computationally expensive approach compared to our proposal, as every model incurs communication overhead. In their case, the communication cost is not just the input data (image) but a set of feature maps that will be much larger and have more redundancy. For instance, a typical image would consist of $224 \\times 224 \\times 3$ floats, while a feature map in their VGG baseline can go up to intermediate stage $224 \\times 224 \\times 64$.\n\t- In our case, there will be many instances where we do not route the example to the global model, say at a coverage level of $80\\%$, our routing scheme on average will only route $20\\%$ examples to the global model. In contrast, Neurosurgeon aims to split the computation of a given model between the edge device and cloud, i.e. to achieve accuracy of a global model, the total computation for this high-cost model will be used irrespective of the input example. \n- **Comparison with AppealNet** \n\t- AppealNet formulation does not explicitly model any coverage constraint that enables the base model to operate at a tunable coverage level. In contrast, we explicitly model a coverage penalty.\n\t- Jointly learning the routing without any supervision is a hard problem. Instead, we relax this formulation by introducing the routing oracle that specializes in a routing network for a given base and global pair. With this oracle, the task of learning routing reduces to a binary classification problem with the routing labels obtained from the oracle. This also decouples the routing task from the base and global entanglement.\n\t- In addition, we propose a neural architecture search that finds a pair of base and global architectures that optimise the hybrid accuracy at any given combined resource usage. \n\t- Empirically, AppealNet does not have any evaluations for the Imagenet scale dataset. The closest comparison we can find is with the Tiny-Imagenet dataset (one-tenth of the size of the Imagenet). While we cannot compare the two directly, since we solve a much harder problem than Tiny-Imagenet, we can make the following observations. At $70\\%$ coverage level, for AppealNet, the minimum performance difference between the hybrid model and the global model is $\\approx 1.2\\%$ (see AppealNet, Fig.5(d)), while our closest to the global in case of the MobileNet baseline is $0.3\\%$ (see our paper Table 1, row 3). Note that AppealNet performance will go down on Imagenet in comparison to Tiny-Imagenet due to the hardness of the problem.\n- **Incorrect numbers for MCUNet baseline in the introduction.** \\\n\t We thank the reviewer for pointing out the error in our citation. We borrowed the pre-trained models from the MCUNet github repository (https://github.com/mit-han-lab/tinyml/tree/master/mcunet). We seem to have mixed the controllers STM32F746 (320kB SRAM, 1MB Flash) and STM32H743 (512kB SRAM, 2MB Flash). \n\t- On STM32H743, MCUNet model (467M FLOPs, 3.3M Params) achieves $70.7\\%$ Top-1 accuracy. \n\t- On STM32F746, MCUNet model (12.8M FLOPs, 0.6M Params) has 5FPS latency and achieves $51.5\\%$ Top-1 accuracy. We have access to STM32F746 controller and we have used this 5FPS latency model in our experiments. We have clarified this statement in the paper. \n\t- MCUNet authors did not release the deployment implementations, instead we rely on their released tf-lite binaries for execution using the tf-lite library. The 5FPS model is the only one that does not lead to OOM error (see \"MCUNet under different latency constraints\" on their github ). \n\t- Once again, we re-iterate the point that our hybrid model only improves by using an improved base model. In this case, if a better base model existed than 12.8M FLOPs achieving 51.5\\% Top-1, our hybrid performance will only increase. \n- **Latency is not a device constraint, it is an application constraint. Suggests using clock frequency instead of latency in introduction.** \\\n We believe there has been a slight misunderstanding of the way we use the term device constraint. We do not mean a constraint imposed on the device. Instead, we mean a constraint imposed on the model by the device. Our use of the term device constraint is in line with the popular use of that term in the literature (OFA, MCUNet, FBNet, etc.).\n\n"}, "signatures": ["ICLR.cc/2022/Conference/Paper4168/Authors"], "readers": ["everyone"], "nonreaders": [], "writers": ["ICLR.cc/2022/Conference", "ICLR.cc/2022/Conference/Paper4168/Authors"], "forumContent": {}} |
| {"id": "ifMzwhUcXqp", "original": null, "number": 1, "cdate": 1628475649899, "mdate": null, "ddate": null, "tcdate": 1628475649899, "tmdate": 1628619164762, "tddate": null, "forum": "C1mPUP7uKNp", "replyto": "7N-qsOAxj6x", "invitation": "NeurIPS.cc/2021/Conference/Paper6438/-/Official_Comment", "content": {"title": "Author Response", "comment": "Thanks so much for the constructive feedback and detailed comments. \n\n**[1. Contribution highlight: patch-based inference schedule, not search method.]**\n\nWe only leverage the search technique to automatically optimize the network and inference system and ease human labor. Other search techniques (e.g., reinforcement learning, Bayesian optimization) are also feasible in our cases.\n\nThe main contributions of our paper are:\n\n- Systematically analyze the memory usage pattern of efficient CNN designs and point out the critical issue of imbalanced memory distribution for the TinyML setting.\n- Propose a patch-based inference scheduling to significantly reduce the peak memory for inference.\n- Propose network redistribution technique to reduce the computation overhead from overlapping patches.\n- Leverage automated search techniques to jointly optimize the neural architecture and inference scheduling.\n\n\n**[2. Network redistribution will not degrade the performance on larger object detection datasets like MS-COCO.]**\n\nThanks for the suggestion. Firstly, the network redistribution technique only _shifts_ parts of the receptive field from the early network stage to the later stage, but not _reduces_ the overall receptive field. The input features to the detection head still have the same receptive field compared to the original network. With the technique, we can further accommodate a larger input resolution given the same memory constraint, which is critical to object detection.\n\nWe validate the object detection performance on the MS-COCO dataset. We compare the object detection performance of the MobileNetV2 backbone (MbV2) with YOLO-V3 and its redistributed version (MbV2-RD) in the following table (extension of Table 1 in the original paper). MbV2-RD has similar or slightly better performance on both VOC and COCO datasets.\n\n| | VOC mAP | COCO mAP | COCO AP50 |\n| ------- | ------- | -------- | ------------ |\n| MbV2 | 75.4% | 24.8% | 44.1% |\n| MbV2-RD | 75.7% | 25.0% | 44.3% |\n\nWe further compare the object detection performance fitting MCUs of 512kB SRAM limit (extension of Table 3 of the original paper). The improvement on COCO is consistent and significant.\n\n| Model | Peak SRAM | VOC mAP | COCO mAP | COCO AP50 |\n| ----------- | --------- | ------- | -------- | ------------ |\n| MCUNet [26] | 466kB | 51.4% | 13.1% | 26.1% |\n| PatchNN | 438kB | 68.3% | 16.7% | 32.8% |\n\n**[3. Joint NAS is valid and affordable on larger detection datasets like MS-COCO.]**\n\nFor joint NAS, we used a one-shot NAS method based on once-for-all networks [4]. It only requires training the super network once at roughly 2x of the cost compared to normal network training. For the search part, we need to sample a valid neural architecture and inference scheduling under constraints (which can be verified instantly) and measure the performance on a hold-out validation set, consuming a modest computation cost.\n\nWe have performed the joint NAS on the large-scale image classification dataset ImageNet in the paper. The COCO dataset consumes the same level of training cost compared to ImageNet. Please see the COCO results in the table above which demonstrates the feasibility.\n\n**[4. Claim that pruning, quantization, and NAS cannot address the memory bottleneck.]**\n\nSorry for the confusion. The claim is indeed improper. Model compression techniques can reduce the memory cost. But traditional mobile architecture designs target reducing model size or computation, not the inference peak memory (which is more related to activation size). For example, compared to ResNet-18, MobileNetV2 has 4.6x smaller model size and 6x smaller computation, but the peak memory is 1.8x larger [26]; while PatchNN reduces both computation and peak memory. We will correct the sentence in the final version.\n\nThe model compression techniques and our proposed method are orthogonal. They can be combined to further improve memory efficiency.\n\n**[5. Overestimate the peak memory in a multi-branch setting.]**\n\nFor multi-branch cases, if some branches share the same input or output activation, we only count the shared activation once to ensure no repeated calculation. We will add the details in the final version.\n\n**[6. Percentage of memory cost by the weights.]**\n\nAll the analysis in this paper is based on batch size 1, and the activation still dominates the peak memory. \n\nDuring the model inference on MCUs, the weights of each layer can be partially fetched from the Flash and released after computation, thus it will not become the memory bottleneck. For the backbone of PatchNN-M4 on ImageNet (Table 2), the analytic peak memory is 1089kB (per-layer inference) and 196kB (per-patch inference). The biggest weight tensor for each layer is 60kB. We can see that the activation size is the major bottleneck, which could be addressed by patch-based inference. \n\n**[7. Typos.]**\n\nThanks. We will correct the typos in the final version.\n\n\n**Reference**\n\n[4] Han Cai, Chuang Gan, Tianzhe Wang, Zhekai Zhang, and Song Han. Once for All: Train One Network and Specialize it for Efficient Deployment. In ICLR, 2020\n\n[26] Ji Lin, Wei-Ming Chen, Yujun Lin, John Cohn, Chuang Gan, and Song Han. MCUNet: Tiny Deep Learning on IoT Devices. In NeurIPS, 2020.\n\n\n\n\n\n\n"}, "signatures": ["NeurIPS.cc/2021/Conference/Paper6438/Authors"], "readers": ["everyone"], "nonreaders": [], "writers": ["NeurIPS.cc/2021/Conference", "NeurIPS.cc/2021/Conference/Paper6438/Authors"], "forumContent": {}} |
| {"id": "iDkvQ_NvtMy", "original": null, "number": 1, "cdate": 1661507728105, "ddate": null, "tcdate": 1661507728105, "tmdate": 1661603289680, "tddate": null, "forum": "vF3WefcoePW", "replyto": "vF3WefcoePW", "invitation": "NeurIPS.cc/2022/Conference/Paper8440/-/Meta_Review", "content": {"metareview": "The paper proposes to train classifiers for binary data based on logic gate networks, also called arithmetic circuits or algebraic circuits in the knowledge representation and complexity literature [1,2]. The main motivation is that, once trained, they can be run fast by leveraging only binary operations. The authors achieve this by using the classical way to relax logic operations, via a first-order approximation with fuzzy norms. \n\nThe reviewers found the proposed approach interesting and potentially useful for resource-constrained scenarios (where resources do not lack during training but during inference). I agree with them that this paper fits the tinyML literature more than the knowledge representation or reasoning (nowadays falling under the neuro-symbolic) one. However, I agree that believe the paper needs to fix certain aspects for the camera ready.\n\nFirst, it is not clear why the authors are selecting the set of 16 logical operators, where, ideally only 2 are necessary (eg. AND, or product, and NOT, or negation) as all the others can be retrieved as combinations of the these two, as Table 1 illustrates. Furthermore, as using all 16 operators is the major bottleneck that makes the networks being very slow during training, an ablation test with a (even not minimal) subset of the operators is recommended. Clearly there is a trade-off in terms of accuracy w.r.t. the subset of ops used for a fixed depth network. And this trade-off needs to be made clear in the contribution (The authors can elaborate more than only saying \"Omitting subsets of the operators decreased performance in all of our experiments.\"). \n\nSecond, there are a number of claims that need to be fixed. For example, the issue with differentiability with the relaxed functions is that gradients are constant everywhere, and only not defined on a single zero-measure point (between the zero and one regions). This is also one of the issues when trying to learn decision tree structures in a differentiable way. Additionally, the discussion on decision trees being very different from logic gate networks/algebraic circuits is very misleading and needs to be fixed. In fact, a decision node in a tree can be easily represented as a sum unit over some product units or equivalently OR and AND units in propositional logic or SMT [3, 4].\n\nThird, since during training the authors are effectively using a probabilistic mixture model (Eqs 2,3), they are training something similar to a sum product network (without any relevant structural properties, and with negative weights) [5,1]. Therefore, the effect of the temperature parameter is important in retrieving a binary operator and not sufficiently investigated. An ablation study is recommended.\n\nLastly, for the larger experiments, it seems the authors are reporting the results of competitors which, however, use a different preprocessing (e.g. they use more gray-scale values for CIFAR). This makes the space and time consumption not comparable across models and requires a clarification.\n\nI advice the authors to take care of these aspects to make the paper stronger.\n\n\n\n[1] Darwiche and Marquis, \"A Knowledge Compilation Map\", 2001\n[2] Arora and Barak, \"Computational complexity: a modern approach\" 2009.\n[3] Khosravi, et al. \"Handling missing data in decision trees: A probabilistic approach.\" 2020\n[4] Devos, et al. \"Verifying tree ensembles by reasoning about potential instances.\" 2021\n[5] Choi, et al. \"Probabilistic Circuits: A Unifying Framework for Tractable Probabilistic Models\" 2020 ", "recommendation": "Accept", "confidence": "Less certain", "award": "No"}, "signatures": ["NeurIPS.cc/2022/Conference/Paper8440/Area_Chair_NhdK"], "readers": ["everyone"], "nonreaders": [], "writers": ["NeurIPS.cc/2022/Conference/Program_Chairs", "NeurIPS.cc/2022/Conference/Paper8440/Area_Chairs"], "pdate": null, "forumContent": {}} |
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