PCB_COMPONENTS_LABELLED / models /17_class_pcb_v5_safe

Commit History

  1. Add 17-class results plot

    Verified signature
    40c28b4
  2. Add 17-class training results

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    47b303c
  3. Add 17-class training args

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    21f16af
  4. Add 17-class best.pt (pcb_v5_safe)

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    64ef46b