Active filters: verilog
beatsprom/semiconductor-rtl-verilog-chip-design-2026
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vkenbeek/verilog-wavedrom
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Nellyw888/RTL-Coder_small
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Nellyw888/RTL-Coder_7b_reasoning
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Nellyw888/VeriReason-RTL-Coder_7b_reasoning_tb
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Nellyw888/VeriReason-RTL-Coder_7b_reasoning_tb_simple
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Nellyw888/RTL-Coder_7b_reasoning_tb_combined
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AbiralArch/hardware-cvdp-problems
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AbiralArch/verilog-training-data
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AbiralArch/autovcoder-datasets
AbiralArch/hardware-cvdp-examples
AbiralArch/hardware-verilogeval-v2
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AbiralArch/hardware-shailja-vgen
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AbiralArch/hardware-cvdp-complete
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Arrakark/scalared_guidelines
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HPAI-BSC/NotSoTiny-25-12-CVDP
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mcc311/haven-hdl-benchmark
architect-ubc-capstone/rtl-augmented
architect-ubc-capstone/rtl-augmented-v2
architect-ubc-capstone/rtl-augmented-v3
Adel9st/Verilog-Turkish-Dataset
muratkarahan/verilogeval-v1-qwen-base-results
muratkarahan/verilogeval-v1-codev-qwen-v2-results