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Release v0.4.0: selective MLX model downloads
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{
"queue": [
{
"id": "head-layout",
"class": "exact-or-numerical",
"mechanism": "Contiguous per-head Q/K/V might remove strided memory access; count copy costs. Reject no operator/block win or quality gate."
},
{
"id": "m5-fc2-tiles",
"class": "exact-or-numerical",
"mechanism": "Native FC2 K=14336 selects BK64; test MPP BK128/256/512 and cache walk. FP32 accumulation, BF16 epilogue. Full trajectory validates reduction changes."
},
{
"id": "vector-unpack",
"class": "exact",
"mechanism": "Reconstruct 2/4/8 lossless BF16 lanes per thread, fewer redundant nibble loads. Decode+GEMM and full packed block must improve."
},
{
"id": "sparse-embedding",
"class": "exact",
"mechanism": "Read only actual token rows, avoiding loading 1.45GiB vocabulary on cold encoding; measure phase-specific peak."
},
{
"id": "exact-qk-rope",
"class": "numerical-until-proven",
"mechanism": "Replicate native RMS reduction and cast order in one head-major producer. Retain native fallback."
}
],
"deprioritized": [
{
"mechanism": "CoreML CPU/GPU/ANE/all VAE",
"reason": "Already measured complete images in v2. All-GPU ~MLX speed, ANE slower and b8 corrupted tiles; VAE <=3% total latency limits payoff."
},
{
"mechanism": "Unscaled FP16 GEMM, skipped flow heads, approximate Q4/Q8",
"reason": "Actual full trajectories previously failed finite or visual accuracy gates."
},
{
"mechanism": "MPS/CPU dense, whole DiT CoreML export",
"reason": "Prior real operator tests did not identify a throughput advantage; huge export/compile and memory cost. Revisit only if a new operator mechanism qualifies."
}
]
}