Kernels:
Trusted publisher
Uploaded using `kernel-builder`.
Browse files- build/torch-cuda/_ops.py +1 -1
- build/torch-cuda/metadata.json +7 -7
- build/torch-cuda/metadata.json.sigstore +1 -1
- build/torch-cuda/ops/common/chunk_delta_h.py +9 -1
- build/torch-cuda/ops/common/chunk_o.py +18 -5
- build/torch-cuda/ops/gated_delta_rule/chunk_fwd.py +6 -3
- build/torch-cuda/ops/gated_delta_rule/wy_fast.py +6 -2
build/torch-cuda/_ops.py
CHANGED
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@@ -28,7 +28,7 @@ def get_backend() -> str:
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def _find_ops_name() -> str:
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kernel_name = "fla"
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-
unique_id = "
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backend = get_backend()
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return f"_{kernel_name}_{backend}_{unique_id}"
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def _find_ops_name() -> str:
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kernel_name = "fla"
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+
unique_id = "5162251"
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backend = get_backend()
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return f"_{kernel_name}_{backend}_{unique_id}"
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build/torch-cuda/metadata.json
CHANGED
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@@ -1,6 +1,6 @@
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{
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"name": "fla",
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-
"id": "
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"version": 1,
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"kernels-minver": "0.14.0",
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"license": "MIT",
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@@ -15,7 +15,7 @@
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"algorithm": "sha256",
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"files": {
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"__init__.py": "bVRNYUhThvULeUaovvQFZCJ9IZZsC+0kU/HbnXdYT1A=",
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-
"_ops.py": "
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"modules/activations.py": "Lp7xLUf7r785nt93NFhqoSQM+G7AK2e6kviE2/0TRJs=",
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@@ -87,11 +87,11 @@
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| 87 |
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| 90 |
-
"ops/common/chunk_delta_h.py": "
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"ops/common/chunk_h.py": "imyz71p9AD6nOtStpN+zzgE0yVbGnq4DO3FitrO3hvc=",
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"ops/common/chunk_h_parallel.py": "YGNR5a+eC7UShlVAvQF3fSLK+HXoP2Nc06H3p/PyzVg=",
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"ops/common/chunk_h_split.py": "zYoWf1Li3Q7MFPusp5BRf1F+OuGzxxTeiZ3hdunYnCY=",
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-
"ops/common/chunk_o.py": "
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"ops/common/chunk_scaled_dot_kkt.py": "MyoKTPKUUZlOzdC4FdP4etL6pPBGzaNL5DJQyH3603E=",
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"ops/common/fused_chunk.py": "nKIxBC8UD00KuY7WGFysC8P4ELNLEJhHmT60VcqyHbc=",
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"ops/common/fused_recurrent.py": "RnQdVD59iOcRa8sSK4XcQT59RhZJr42YplDaQrDt97o=",
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@@ -125,11 +125,11 @@
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| 125 |
"ops/gated_delta_product/naive.py": "Q907vtcavFpalFlttThkWSb/SaTa4vqAG+I/nWvKDno=",
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| 126 |
"ops/gated_delta_rule/__init__.py": "Xt0hhHr3CECyZDmBIZakdufk3bvvIa/V/iBmpkYwpnw=",
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| 127 |
"ops/gated_delta_rule/chunk.py": "DFEZWmp016p+65pnDynAMVOY+NsUTGOfVcXsAhQr1i4=",
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| 128 |
-
"ops/gated_delta_rule/chunk_fwd.py": "
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| 129 |
"ops/gated_delta_rule/fused_recurrent.py": "M7x3/U1Xnf5mndUc+lvGpzxu4KDNc2Sfevv+RVZZFNk=",
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| 130 |
"ops/gated_delta_rule/gate.py": "H9JLPKjgZmorhyV+1IJFSMIa6x9admDn+EXXlwg167g=",
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| 131 |
"ops/gated_delta_rule/naive.py": "0c8XmSNJ/T6Ur5mbIuPTqBvkotGIHOW3CjRXJXFm4Ms=",
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| 132 |
-
"ops/gated_delta_rule/wy_fast.py": "
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| 133 |
"ops/gated_oja_rule/__init__.py": "oShC/cL0jMy+xWR7YBV9QxkAdxt1xasXDCypGAU6Hgo=",
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| 134 |
"ops/gated_oja_rule/chunk.py": "lq+5BXEaJLfL4dqqcJb4TmtyF9OrP9Wh+JpRfpdzd2s=",
|
| 135 |
"ops/gated_oja_rule/chunk_h.py": "kr6KBcPbFRrIQFBoQjmt1wsyvO1pyLeGW5v/k+NI87Q=",
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@@ -312,7 +312,7 @@
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"dirty": false
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},
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"kernel": {
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-
"commit": "
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"dirty": false
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}
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}
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{
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"name": "fla",
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+
"id": "_fla_cuda_5162251",
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"version": 1,
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| 5 |
"kernels-minver": "0.14.0",
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"license": "MIT",
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|
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"algorithm": "sha256",
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"files": {
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"__init__.py": "bVRNYUhThvULeUaovvQFZCJ9IZZsC+0kU/HbnXdYT1A=",
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"_ops.py": "We4E5voCRwsORI7w045Qn7sM/YCixIMpgi4VN6yKmxA=",
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"layers.py": "/39XVQW4d4GHeNROqT67ujKbItdteLBtm0PT6zq41YQ=",
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"modules/__init__.py": "6ZjjRMt6Rf+2OegXDC8w58RD1IW3SBK+dxBoZa4Uohc=",
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"modules/activations.py": "Lp7xLUf7r785nt93NFhqoSQM+G7AK2e6kviE2/0TRJs=",
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| 87 |
"ops/common/backends/tilelang/chunk_bwd.py": "5zXyBzqIXRgoZdZ8zjLNEIz3jBksHpaVxnqUk66ckjQ=",
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"ops/common/backends/tilelang/parallel_attn_bwd.py": "4OlC0Vj9N1auoz9ZCUeOcBt8QSg4eTByDUnc9BPpZ7k=",
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"ops/common/backends/tilelang/parallel_attn_fwd.py": "7INMyGs1d3H8BKcjRnMvu/NHMm9VeNFTETR5z7ZO15c=",
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| 90 |
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"ops/common/chunk_delta_h.py": "QmkSsbbyOHai9cVaMB8O/8ep4NxiM6ieUVKmja6USw8=",
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| 91 |
"ops/common/chunk_h.py": "imyz71p9AD6nOtStpN+zzgE0yVbGnq4DO3FitrO3hvc=",
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"ops/common/chunk_h_parallel.py": "YGNR5a+eC7UShlVAvQF3fSLK+HXoP2Nc06H3p/PyzVg=",
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"ops/common/chunk_h_split.py": "zYoWf1Li3Q7MFPusp5BRf1F+OuGzxxTeiZ3hdunYnCY=",
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"ops/common/chunk_o.py": "1yUHQ+B2J1PQpxTFEa8R6JxpyV1k/TNXiXkOvFRfQAo=",
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"ops/common/fused_chunk.py": "nKIxBC8UD00KuY7WGFysC8P4ELNLEJhHmT60VcqyHbc=",
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"ops/gated_delta_product/naive.py": "Q907vtcavFpalFlttThkWSb/SaTa4vqAG+I/nWvKDno=",
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"dirty": false
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},
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"kernel": {
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+
"commit": "5162251f728a6da1e248654bb8287ae73a866e9b",
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"dirty": false
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}
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}
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build/torch-cuda/metadata.json.sigstore
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|
build/torch-cuda/ops/common/chunk_delta_h.py
CHANGED
|
@@ -14,6 +14,7 @@ from ...ops.utils import prepare_chunk_indices, prepare_chunk_offsets
|
|
| 14 |
from ...ops.utils.cache import fla_cache_autotune
|
| 15 |
from ...ops.utils.op import exp2
|
| 16 |
from ...utils import (
|
|
|
|
| 17 |
IS_NVIDIA_BLACKWELL,
|
| 18 |
IS_NVIDIA_HOPPER,
|
| 19 |
autotune_cache_kwargs,
|
|
@@ -25,7 +26,14 @@ NUM_WARPS = [2, 4] if IS_NVIDIA_HOPPER else [2, 4, 8, 16]
|
|
| 25 |
# TODO: Triton mainline fixes a Blackwell tl.dot recurrence race.
|
| 26 |
# Keep this kernel on num_warps=2 for Blackwell until Triton 3.8 is released
|
| 27 |
# and we re-validate the wider config space.
|
| 28 |
-
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 29 |
|
| 30 |
|
| 31 |
@triton.heuristics({
|
|
|
|
| 14 |
from ...ops.utils.cache import fla_cache_autotune
|
| 15 |
from ...ops.utils.op import exp2
|
| 16 |
from ...utils import (
|
| 17 |
+
IS_INTEL,
|
| 18 |
IS_NVIDIA_BLACKWELL,
|
| 19 |
IS_NVIDIA_HOPPER,
|
| 20 |
autotune_cache_kwargs,
|
|
|
|
| 26 |
# TODO: Triton mainline fixes a Blackwell tl.dot recurrence race.
|
| 27 |
# Keep this kernel on num_warps=2 for Blackwell until Triton 3.8 is released
|
| 28 |
# and we re-validate the wider config space.
|
| 29 |
+
# Intel needs more warps than NVIDIA here: 8 warps is ~1.5x faster than the best
|
| 30 |
+
# config reachable under the [2, 4] cap.
|
| 31 |
+
if IS_NVIDIA_BLACKWELL:
|
| 32 |
+
GATED_DELTA_RULE_FWD_H_NUM_WARPS = [2]
|
| 33 |
+
elif IS_INTEL:
|
| 34 |
+
GATED_DELTA_RULE_FWD_H_NUM_WARPS = [2, 4, 8, 16]
|
| 35 |
+
else:
|
| 36 |
+
GATED_DELTA_RULE_FWD_H_NUM_WARPS = [2, 4]
|
| 37 |
|
| 38 |
|
| 39 |
@triton.heuristics({
|
build/torch-cuda/ops/common/chunk_o.py
CHANGED
|
@@ -14,6 +14,7 @@ from ...ops.utils import prepare_chunk_indices
|
|
| 14 |
from ...ops.utils.cache import fla_cache_autotune
|
| 15 |
from ...ops.utils.op import exp2
|
| 16 |
from ...utils import (
|
|
|
|
| 17 |
IS_NVIDIA_HOPPER,
|
| 18 |
TRITON_ABOVE_3_4_0,
|
| 19 |
TRITON_ABOVE_3_7_1,
|
|
@@ -24,6 +25,22 @@ from ...utils import (
|
|
| 24 |
BKV_LIST = [64, 128] if check_shared_mem() else ([32, 64] if check_shared_mem('ada') else [32])
|
| 25 |
NUM_WARPS = [2, 4] if IS_NVIDIA_HOPPER else [2, 4, 8]
|
| 26 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 27 |
|
| 28 |
@triton.heuristics({
|
| 29 |
'USE_G': lambda args: args['g'] is not None,
|
|
@@ -31,11 +48,7 @@ NUM_WARPS = [2, 4] if IS_NVIDIA_HOPPER else [2, 4, 8]
|
|
| 31 |
'IS_VARLEN': lambda args: args['cu_seqlens'] is not None,
|
| 32 |
})
|
| 33 |
@fla_cache_autotune(
|
| 34 |
-
configs=
|
| 35 |
-
triton.Config({'BK': 128, 'BV': 128}, num_warps=8, num_stages=3),
|
| 36 |
-
triton.Config({'BK': 64, 'BV': 64}, num_warps=4, num_stages=3),
|
| 37 |
-
triton.Config({'BK': 32, 'BV': 32}, num_warps=2, num_stages=3),
|
| 38 |
-
],
|
| 39 |
key=['H', 'HV', 'K', 'V', 'BT', 'STATE_V_FIRST'],
|
| 40 |
**autotune_cache_kwargs,
|
| 41 |
)
|
|
|
|
| 14 |
from ...ops.utils.cache import fla_cache_autotune
|
| 15 |
from ...ops.utils.op import exp2
|
| 16 |
from ...utils import (
|
| 17 |
+
IS_INTEL,
|
| 18 |
IS_NVIDIA_HOPPER,
|
| 19 |
TRITON_ABOVE_3_4_0,
|
| 20 |
TRITON_ABOVE_3_7_1,
|
|
|
|
| 25 |
BKV_LIST = [64, 128] if check_shared_mem() else ([32, 64] if check_shared_mem('ada') else [32])
|
| 26 |
NUM_WARPS = [2, 4] if IS_NVIDIA_HOPPER else [2, 4, 8]
|
| 27 |
|
| 28 |
+
# Upstream pairs each tile size with a single warp count, which is tuned for NVIDIA.
|
| 29 |
+
# On Intel that pairing is off by a factor of two: BK=BV=64 is fastest at 8 warps but is
|
| 30 |
+
# only offered at 4, so the autotuner falls back to the 32x32 config and leaves ~2.2x on
|
| 31 |
+
# the table. Widen the space there instead of changing the defaults for other vendors.
|
| 32 |
+
_O_CONFIGS = [
|
| 33 |
+
triton.Config({'BK': 128, 'BV': 128}, num_warps=8, num_stages=3),
|
| 34 |
+
triton.Config({'BK': 64, 'BV': 64}, num_warps=4, num_stages=3),
|
| 35 |
+
triton.Config({'BK': 32, 'BV': 32}, num_warps=2, num_stages=3),
|
| 36 |
+
]
|
| 37 |
+
if IS_INTEL:
|
| 38 |
+
_O_CONFIGS += [
|
| 39 |
+
triton.Config({'BK': BK, 'BV': BV}, num_warps=w, num_stages=2)
|
| 40 |
+
for BK, BV in [(128, 64), (64, 64), (64, 32), (32, 64), (32, 32)]
|
| 41 |
+
for w in (4, 8)
|
| 42 |
+
]
|
| 43 |
+
|
| 44 |
|
| 45 |
@triton.heuristics({
|
| 46 |
'USE_G': lambda args: args['g'] is not None,
|
|
|
|
| 48 |
'IS_VARLEN': lambda args: args['cu_seqlens'] is not None,
|
| 49 |
})
|
| 50 |
@fla_cache_autotune(
|
| 51 |
+
configs=_O_CONFIGS,
|
|
|
|
|
|
|
|
|
|
|
|
|
| 52 |
key=['H', 'HV', 'K', 'V', 'BT', 'STATE_V_FIRST'],
|
| 53 |
**autotune_cache_kwargs,
|
| 54 |
)
|
build/torch-cuda/ops/gated_delta_rule/chunk_fwd.py
CHANGED
|
@@ -14,7 +14,7 @@ from ...ops.gated_delta_rule.wy_fast import recompute_w_u_fwd
|
|
| 14 |
from ...ops.utils import prepare_chunk_indices, solve_tril
|
| 15 |
from ...ops.utils.cache import fla_cache_autotune
|
| 16 |
from ...ops.utils.op import exp2
|
| 17 |
-
from ...utils import IS_TF32_SUPPORTED, autotune_cache_kwargs
|
| 18 |
|
| 19 |
if IS_TF32_SUPPORTED:
|
| 20 |
SOLVE_TRIL_DOT_PRECISION = tl.constexpr('tf32')
|
|
@@ -361,7 +361,10 @@ def chunk_gated_delta_rule_fwd_intra(
|
|
| 361 |
if chunk_indices is None and cu_seqlens is not None:
|
| 362 |
chunk_indices = prepare_chunk_indices(cu_seqlens, BT)
|
| 363 |
|
| 364 |
-
|
|
|
|
|
|
|
|
|
|
| 365 |
# Step 1: fused kkt + solve_tril
|
| 366 |
BC = 16
|
| 367 |
NT = triton.cdiv(T, BT) if cu_seqlens is None else len(chunk_indices)
|
|
@@ -381,7 +384,7 @@ def chunk_gated_delta_rule_fwd_intra(
|
|
| 381 |
BC=BC,
|
| 382 |
)
|
| 383 |
else:
|
| 384 |
-
# Step 1: mathematically equivalent unfused kkt + solve_tril
|
| 385 |
A = chunk_scaled_dot_kkt_fwd(
|
| 386 |
k=k,
|
| 387 |
g=g,
|
|
|
|
| 14 |
from ...ops.utils import prepare_chunk_indices, solve_tril
|
| 15 |
from ...ops.utils.cache import fla_cache_autotune
|
| 16 |
from ...ops.utils.op import exp2
|
| 17 |
+
from ...utils import IS_INTEL, IS_TF32_SUPPORTED, autotune_cache_kwargs
|
| 18 |
|
| 19 |
if IS_TF32_SUPPORTED:
|
| 20 |
SOLVE_TRIL_DOT_PRECISION = tl.constexpr('tf32')
|
|
|
|
| 361 |
if chunk_indices is None and cu_seqlens is not None:
|
| 362 |
chunk_indices = prepare_chunk_indices(cu_seqlens, BT)
|
| 363 |
|
| 364 |
+
# The fused kernel keeps ten [BC, BC] fp32 accumulators live across the K loop.
|
| 365 |
+
# That fits NVIDIA's register file but spills on Intel GPUs, where the unfused
|
| 366 |
+
# two-kernel path measures 2.3-3.0x faster despite the extra HBM round-trip.
|
| 367 |
+
if BT == 64 and not IS_INTEL:
|
| 368 |
# Step 1: fused kkt + solve_tril
|
| 369 |
BC = 16
|
| 370 |
NT = triton.cdiv(T, BT) if cu_seqlens is None else len(chunk_indices)
|
|
|
|
| 384 |
BC=BC,
|
| 385 |
)
|
| 386 |
else:
|
| 387 |
+
# Step 1: mathematically equivalent unfused kkt + solve_tril
|
| 388 |
A = chunk_scaled_dot_kkt_fwd(
|
| 389 |
k=k,
|
| 390 |
g=g,
|
build/torch-cuda/ops/gated_delta_rule/wy_fast.py
CHANGED
|
@@ -12,7 +12,7 @@ import triton.language as tl
|
|
| 12 |
from ...ops.utils import prepare_chunk_indices
|
| 13 |
from ...ops.utils.cache import fla_cache_autotune
|
| 14 |
from ...ops.utils.op import exp2
|
| 15 |
-
from ...utils import IS_NVIDIA_BLACKWELL, autotune_cache_kwargs, check_shared_mem
|
| 16 |
|
| 17 |
# Blackwell can select unstable Triton configs for prepare_wy_repr_bwd_kernel
|
| 18 |
# during autotuning (see #913). Restrict it to the config that has been
|
|
@@ -20,6 +20,10 @@ from ...utils import IS_NVIDIA_BLACKWELL, autotune_cache_kwargs, check_shared_me
|
|
| 20 |
PREPARE_WY_REPR_BWD_NUM_WARPS = [2] if IS_NVIDIA_BLACKWELL else [2, 4]
|
| 21 |
PREPARE_WY_REPR_BWD_NUM_STAGES = [4] if IS_NVIDIA_BLACKWELL else [2, 3, 4]
|
| 22 |
|
|
|
|
|
|
|
|
|
|
|
|
|
| 23 |
|
| 24 |
@triton.heuristics({
|
| 25 |
'USE_G': lambda args: args['g'] is not None,
|
|
@@ -28,7 +32,7 @@ PREPARE_WY_REPR_BWD_NUM_STAGES = [4] if IS_NVIDIA_BLACKWELL else [2, 3, 4]
|
|
| 28 |
@fla_cache_autotune(
|
| 29 |
configs=[
|
| 30 |
triton.Config({}, num_warps=num_warps, num_stages=num_stages)
|
| 31 |
-
for num_warps in
|
| 32 |
for num_stages in [2, 3, 4]
|
| 33 |
],
|
| 34 |
key=['H', 'HV', 'K', 'V', 'BT', 'BK', 'BV', 'IS_VARLEN'],
|
|
|
|
| 12 |
from ...ops.utils import prepare_chunk_indices
|
| 13 |
from ...ops.utils.cache import fla_cache_autotune
|
| 14 |
from ...ops.utils.op import exp2
|
| 15 |
+
from ...utils import IS_INTEL, IS_NVIDIA_BLACKWELL, autotune_cache_kwargs, check_shared_mem
|
| 16 |
|
| 17 |
# Blackwell can select unstable Triton configs for prepare_wy_repr_bwd_kernel
|
| 18 |
# during autotuning (see #913). Restrict it to the config that has been
|
|
|
|
| 20 |
PREPARE_WY_REPR_BWD_NUM_WARPS = [2] if IS_NVIDIA_BLACKWELL else [2, 4]
|
| 21 |
PREPARE_WY_REPR_BWD_NUM_STAGES = [4] if IS_NVIDIA_BLACKWELL else [2, 3, 4]
|
| 22 |
|
| 23 |
+
# Intel keeps scaling past the warp counts NVIDIA prefers: 16 warps is ~1.3x faster
|
| 24 |
+
# than 8 for recompute_w_u.
|
| 25 |
+
RECOMPUTE_W_U_NUM_WARPS = [2, 4, 8, 16] if IS_INTEL else [2, 4, 8]
|
| 26 |
+
|
| 27 |
|
| 28 |
@triton.heuristics({
|
| 29 |
'USE_G': lambda args: args['g'] is not None,
|
|
|
|
| 32 |
@fla_cache_autotune(
|
| 33 |
configs=[
|
| 34 |
triton.Config({}, num_warps=num_warps, num_stages=num_stages)
|
| 35 |
+
for num_warps in RECOMPUTE_W_U_NUM_WARPS
|
| 36 |
for num_stages in [2, 3, 4]
|
| 37 |
],
|
| 38 |
key=['H', 'HV', 'K', 'V', 'BT', 'BK', 'BV', 'IS_VARLEN'],
|