Fix q8_0 gemv: reduction-across-simdgroups convention

q8_0's mul_mv splits the K reduction across simdgroups and combines them through
threadgroup memory, where the K-quants give each simdgroup its own rows. It
therefore needs a grid that is not divided by nsg, and it needs smem bound --
upstream branches on exactly this. Without both, q8_0 returned garbage while the
K-quants were correct.

gguf_metal/ggml_dispatch.mm

@@ -38,14 +38,21 @@ struct TypeInfo {
   int block_bytes;
   int mv_nsg;         // N_SG_*  from ggml-metal-impl.h
   int mv_nr0;         // N_R0_*
+  // Two gemv conventions upstream. The K-quants give each simdgroup its own rows
+  // (first_row = (tgpig.x*NSG + sgitg)*nr0), so the grid is divided by nsg and nothing is shared.
+  // q8_0 instead splits the K reduction across simdgroups (r0 = tgpig.x*NR0) and combines them
+  // through threadgroup memory in helper_mv_reduce_and_write -- so its grid must NOT be divided by
+  // nsg, and it needs smem. Getting either wrong silently returns garbage.
+  bool mv_reduce_across_sgs;
+  size_t mv_smem;
 };
 
 const std::unordered_map<int, TypeInfo> &type_table() {
   static const std::unordered_map<int, TypeInfo> table = {
-      {GGML_Q8_0, {"q8_0", 32, 34, N_SG_Q8_0, N_R0_Q8_0}},
-      {GGML_Q4_K, {"q4_K", 256, 144, N_SG_Q4_K, N_R0_Q4_K}},
-      {GGML_Q5_K, {"q5_K", 256, 176, N_SG_Q5_K, N_R0_Q5_K}},
-      {GGML_Q6_K, {"q6_K", 256, 210, N_SG_Q6_K, N_R0_Q6_K}},
+      {GGML_Q8_0, {"q8_0", 32, 34, N_SG_Q8_0, N_R0_Q8_0, true, 32 * sizeof(float) * N_R0_Q8_0}},
+      {GGML_Q4_K, {"q4_K", 256, 144, N_SG_Q4_K, N_R0_Q4_K, false, 0}},
+      {GGML_Q5_K, {"q5_K", 256, 176, N_SG_Q5_K, N_R0_Q5_K, false, 0}},
+      {GGML_Q6_K, {"q6_K", 256, 210, N_SG_Q6_K, N_R0_Q6_K, false, 0}},
   };
   return table;
 }
@@ -180,7 +187,11 @@ extern "C" int gguf_metal_mul_mat(void *blocks, size_t blocks_off, void *x, size
       [enc setBuffer:b_blocks offset:blocks_off atIndex:1];
       [enc setBuffer:b_x offset:x_off atIndex:2];
       [enc setBuffer:b_out offset:out_off atIndex:3];
-      const NSUInteger gx = (N + nr0 * nsg - 1) / (nr0 * nsg);
+      if (info->mv_smem) {
+        [enc setThreadgroupMemoryLength:info->mv_smem atIndex:0];
+      }
+      const NSUInteger gx = info->mv_reduce_across_sgs ? (N + nr0 - 1) / nr0
+                                                       : (N + nr0 * nsg - 1) / (nr0 * nsg);
       [enc dispatchThreadgroups:MTLSizeMake(gx, M, 1)
           threadsPerThreadgroup:MTLSizeMake(32, nsg, 1)];
     }

result-torch212

@@ -0,0 +1 @@
+/nix/store/vsc5ambf7shc0cv3fip7zvfzaxsjk4z2-gguf-kernels-torch-ext

result-torch213

@@ -0,0 +1 @@
+/nix/store/ipmkgsrz5mzwi56m3264vhb2nm2vpgfy-gguf-kernels-torch-ext