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b017ab3 | 1 2 3 4 5 6 7 8 | TOPLEVEL_LANG = verilog
VERILOG_SOURCES = design_active.v
TOPLEVEL = half_adder
COCOTB_TEST_MODULES = test_half_adder
SIM = icarus
include $(shell cocotb-config --makefiles)/Makefile.sim |