server/tasks/medium/02_decoder_logic/testbench.v

`timescale 1ns/1ps

module tb_decoder2x4;

reg a;
reg b;
wire y0;
wire y1;
wire y2;
wire y3;

decoder2x4 uut (
    .a(a),
    .b(b),
    .y0(y0),
    .y1(y1),
    .y2(y2),
    .y3(y3)
);

initial begin
    $display("a b | y3 y2 y1 y0");
    $display("-----------------");

    a=0; b=0; #10; $display("%b %b |  %b  %b  %b  %b", a, b, y3, y2, y1, y0);
    a=0; b=1; #10; $display("%b %b |  %b  %b  %b  %b", a, b, y3, y2, y1, y0);
    a=1; b=0; #10; $display("%b %b |  %b  %b  %b  %b", a, b, y3, y2, y1, y0);
    a=1; b=1; #10; $display("%b %b |  %b  %b  %b  %b", a, b, y3, y2, y1, y0);

    $finish;
end

endmodule