Delete the miscalibrated sm_120 SAME-S fp8 encoder

Move deprecated sm_120 TRT engines under legacy/

Move deprecated sm_90 TRT engines under legacy/

retire fp8_fast; remove the superseded sm_90 fp8 engines (miscalibrated encoder, 8192-ceiling decoders)

retire fp8_fast; remove the superseded sm_90 fp8 engines (miscalibrated encoder, 8192-ceiling decoders)

retire fp8_fast; remove the superseded sm_90 fp8 engines (miscalibrated encoder, 8192-ceiling decoders)

retire fp8_fast; remove the superseded sm_90 fp8 engines (miscalibrated encoder, 8192-ceiling decoders)

retire fp8_fast; remove the superseded sm_90 fp8 engines (miscalibrated encoder, 8192-ceiling decoders)

retire fp8_fast; remove the superseded sm_90 fp8 engines (miscalibrated encoder, 8192-ceiling decoders)

retire fp8_fast; remove the superseded sm_90 fp8 engines (miscalibrated encoder, 8192-ceiling decoders)

SAME-L/SAME-S: bake the limiter ceiling so the chunkable decoders keep the ('latent','pcm') signature; add the SAME-S fp8 chunkable pair

SAME-L/SAME-S: bake the limiter ceiling so the chunkable decoders keep the ('latent','pcm') signature; add the SAME-S fp8 chunkable pair

SAME-L/SAME-S: bake the limiter ceiling so the chunkable decoders keep the ('latent','pcm') signature; add the SAME-S fp8 chunkable pair

SAME-L/SAME-S: bake the limiter ceiling so the chunkable decoders keep the ('latent','pcm') signature; add the SAME-S fp8 chunkable pair

SAME-L/SAME-S: bake the limiter ceiling so the chunkable decoders keep the ('latent','pcm') signature; add the SAME-S fp8 chunkable pair

SAME-S: add the chunkable bf16 pair (two profiles, limiter)

SAME-S: add the chunkable bf16 pair (two profiles, limiter)

SAME-L encoders: low band 64 -> 256 (1.3-1.5x faster, cos 0.99831 -> 0.99969)

SAME-L encoders: low band 64 -> 256 (1.3-1.5x faster, cos 0.99831 -> 0.99969)

SAME-L: remove miscalibrated enc_fp8.trt (activation scales 1.3-28x too small; superseded by enc_fp8_chunkable.trt on sm_90)

SAME-L: remove miscalibrated enc_fp8.trt (activation scales 1.3-28x too small; superseded by enc_fp8_chunkable.trt on sm_90)

SAME-L: add enc_fp8_chunkable.trt (fp16, two-profile chunkable)

SAME-L: add dec_fp8_chunkable_limiter.trt (fp16, two-profile chunkable, runtime limiter ceiling)

SAME-L: add enc_fp16_chunkable.trt (fp16, two-profile chunkable)

SAME-L: add dec_fp16_chunkable_limiter.trt (fp16, two-profile chunkable, runtime limiter ceiling)

Delete old fp16mixed names + retired medium dit_bf16.trt (fp16 rename shipped)

Rename fp16mixed->fp16 DiT/T5Gemma engines+onnx (copies; deletes follow after code merge)

Remove redundant w8_bf16 engines (int8 weights fold to bf16 at build → identical size/speed to the bf16 baseline)

Add sm_120 TRT engines (AOT SWA, wide profile) for the quantized tiers

Add sm_90 TRT engines (wide profile) for the quantized tiers

Add fp8 tier for sm-music / sm-sfx DiTs (clean fp8-linear graft on fp16mixed)

Add fp8 tier for sm-music / sm-sfx DiTs (clean fp8-linear graft on fp16mixed)

sm_120 sa3-m: add the fp8 medium-DiT tier (176 fp8 GEMM + 96 bf16 fused MHA, 1.43-1.95x vs fp16mixed) (#7)

sa3-m fp8: ship calibrated-bakedmin engine (176 fp8 GEMM + 96 bf16 fused MHA + baked fp32 RoPE; calibration by @ryanontheinside #47)

sm_120 SAME-L: AOT (graph-capturable) engines + tensorRT/README.md (#6)

Upload tensorRT/sm_90/sa3-m/dit_fp8.trt with huggingface_hub

Fix the bf16 medium DiT: bake RoPE's tables into the graph (clipping 3.112% -> 0.014%) (#5)

Rebuild medium DiT fp16-mixed engines (sm_90 + new sm_120): attention now fuses, 4.3x faster (#4)

Add bf16 medium DiT TRT engine (sm_90) — FMHA-fused, medium default (#1)

Add FP32 SAME-L + SAME-S TRT decoders

Decoder ONNX: clip+scale in FP32 before int32 cast

DiT engines: replace BF16 with FP16-mixed (FP32 islands) + add FP32 variants

DiT TRT engines: rebuild with profile min=1 (sm_90)

T5Gemma: FP16-mixed (FP32 attention island) — fixes BF16 numerical bug

Decoder TRT engines: PCM-baked-in (sm_90)

Drop L-range suffix from SAME-L decoder filename

Reorganize tensorRT/ into per-arch subdirs; rebuild DiT engines with conditioner baked in

Remove padding_embedding.pt — these ship with the inference code repo

Remove pipeline_state from tensorRT/ — it ships with the inference code repo, not here

Add pipeline_state + per-model padding_embedding for SA3 TRT pipeline